1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Only provide customized ctpop vector bit twiddling for vector types we
991 // know to perform better than using the popcnt instructions on each vector
992 // element. If popcnt isn't supported, always provide the custom version.
993 if (!Subtarget->hasPOPCNT()) {
994 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
995 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
998 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
999 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1000 MVT VT = (MVT::SimpleValueType)i;
1001 // Do not attempt to custom lower non-power-of-2 vectors
1002 if (!isPowerOf2_32(VT.getVectorNumElements()))
1004 // Do not attempt to custom lower non-128-bit vectors
1005 if (!VT.is128BitVector())
1007 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1008 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1012 // We support custom legalizing of sext and anyext loads for specific
1013 // memory vector types which we can load as a scalar (or sequence of
1014 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1015 // loads these must work with a single scalar load.
1016 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1026 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1027 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1028 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1029 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1033 if (Subtarget->is64Bit()) {
1034 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1038 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1039 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1040 MVT VT = (MVT::SimpleValueType)i;
1042 // Do not attempt to promote non-128-bit vectors
1043 if (!VT.is128BitVector())
1046 setOperationAction(ISD::AND, VT, Promote);
1047 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1048 setOperationAction(ISD::OR, VT, Promote);
1049 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1050 setOperationAction(ISD::XOR, VT, Promote);
1051 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1052 setOperationAction(ISD::LOAD, VT, Promote);
1053 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1054 setOperationAction(ISD::SELECT, VT, Promote);
1055 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1058 // Custom lower v2i64 and v2f64 selects.
1059 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1060 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1061 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1065 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1069 // As there is no 64-bit GPR available, we need build a special custom
1070 // sequence to convert from v2i32 to v2f32.
1071 if (!Subtarget->is64Bit())
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1074 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1075 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1077 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1079 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1080 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1081 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1084 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1085 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1090 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1107 // FIXME: Do we need to handle scalar-to-vector here?
1108 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1110 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1112 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1113 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1114 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1115 // There is no BLENDI for byte vectors. We don't need to custom lower
1116 // some vselects for now.
1117 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1119 // SSE41 brings specific instructions for doing vector sign extend even in
1120 // cases where we don't have SRA.
1121 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1122 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1123 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1125 // i8 and i16 vectors are custom because the source register and source
1126 // source memory operand types are not the same width. f32 vectors are
1127 // custom since the immediate controlling the insert encodes additional
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1139 // FIXME: these should be Legal, but that's only for the case where
1140 // the index is constant. For now custom expand to deal with that.
1141 if (Subtarget->is64Bit()) {
1142 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1147 if (Subtarget->hasSSE2()) {
1148 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1154 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1157 // In the customized shift lowering, the legal cases in AVX2 will be
1159 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1163 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1165 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1168 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1169 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1172 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1173 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1174 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1176 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1178 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1180 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1191 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1193 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1204 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1206 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1207 // even though v8i16 is a legal type.
1208 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1209 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1210 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1212 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1213 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1214 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1216 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1217 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1219 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1221 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1233 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1235 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1240 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1241 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1242 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1251 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1252 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1253 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1254 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1255 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1257 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1258 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1260 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1261 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1262 setOperationAction(ISD::FMA, MVT::f32, Legal);
1263 setOperationAction(ISD::FMA, MVT::f64, Legal);
1266 if (Subtarget->hasInt256()) {
1267 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1268 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1269 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1270 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1272 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1273 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1274 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1275 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1277 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1278 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1279 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1280 // Don't lower v32i8 because there is no 128-bit byte mul
1282 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1283 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1284 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1285 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1287 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1288 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1290 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1291 // when we have a 256bit-wide blend with immediate.
1292 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1294 // Only provide customized ctpop vector bit twiddling for vector types we
1295 // know to perform better than using the popcnt instructions on each
1296 // vector element. If popcnt isn't supported, always provide the custom
1298 if (!Subtarget->hasPOPCNT())
1299 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1301 // Custom CTPOP always performs better on natively supported v8i32
1302 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1304 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1305 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1306 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1307 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1309 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1312 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1314 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1315 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1317 // Don't lower v32i8 because there is no 128-bit byte mul
1320 // In the customized shift lowering, the legal cases in AVX2 will be
1322 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1323 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1325 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1326 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1328 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1330 // Custom lower several nodes for 256-bit types.
1331 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1332 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1333 MVT VT = (MVT::SimpleValueType)i;
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 // Extract subvector is special because the value type
1340 // (result) is 128-bit but the source is 256-bit wide.
1341 if (VT.is128BitVector()) {
1342 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1344 // Do not attempt to custom lower other non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1350 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1351 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1352 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1353 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1354 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1357 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1358 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1359 MVT VT = (MVT::SimpleValueType)i;
1361 // Do not attempt to promote non-256-bit vectors
1362 if (!VT.is256BitVector())
1365 setOperationAction(ISD::AND, VT, Promote);
1366 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1367 setOperationAction(ISD::OR, VT, Promote);
1368 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1369 setOperationAction(ISD::XOR, VT, Promote);
1370 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1371 setOperationAction(ISD::LOAD, VT, Promote);
1372 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1373 setOperationAction(ISD::SELECT, VT, Promote);
1374 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1378 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1379 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1380 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1381 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1382 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1384 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1385 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1386 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1388 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1389 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1390 setOperationAction(ISD::XOR, MVT::i1, Legal);
1391 setOperationAction(ISD::OR, MVT::i1, Legal);
1392 setOperationAction(ISD::AND, MVT::i1, Legal);
1393 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1394 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1395 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1398 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1400 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1401 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1407 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1408 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1409 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1410 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1411 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1412 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1413 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1414 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1420 if (Subtarget->is64Bit()) {
1421 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1430 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1431 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1432 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1433 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1434 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1435 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1436 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1437 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1439 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1441 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1444 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1445 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1446 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1447 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1448 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1462 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1465 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1506 // Custom lower several nodes.
1507 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1508 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1509 MVT VT = (MVT::SimpleValueType)i;
1511 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1512 // Extract subvector is special because the value type
1513 // (result) is 256/128-bit but the source is 512-bit wide.
1514 if (VT.is128BitVector() || VT.is256BitVector()) {
1515 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1517 if (VT.getVectorElementType() == MVT::i1)
1518 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1520 // Do not attempt to custom lower other non-512-bit vectors
1521 if (!VT.is512BitVector())
1524 if ( EltSize >= 32) {
1525 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1526 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1527 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1528 setOperationAction(ISD::VSELECT, VT, Legal);
1529 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1530 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1531 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1532 setOperationAction(ISD::MLOAD, VT, Legal);
1533 setOperationAction(ISD::MSTORE, VT, Legal);
1536 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1537 MVT VT = (MVT::SimpleValueType)i;
1539 // Do not attempt to promote non-256-bit vectors.
1540 if (!VT.is512BitVector())
1543 setOperationAction(ISD::SELECT, VT, Promote);
1544 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1548 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1549 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1550 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1552 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1553 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1555 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1556 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1557 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1558 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1559 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1560 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1561 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1562 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1563 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1565 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1566 const MVT VT = (MVT::SimpleValueType)i;
1568 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1570 // Do not attempt to promote non-256-bit vectors.
1571 if (!VT.is512BitVector())
1575 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1576 setOperationAction(ISD::VSELECT, VT, Legal);
1581 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1582 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1583 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1585 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1586 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1587 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1589 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1590 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1591 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1592 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1593 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1594 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1597 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1598 // of this type with custom code.
1599 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1600 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1601 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1605 // We want to custom lower some of our intrinsics.
1606 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1607 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1608 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1609 if (!Subtarget->is64Bit())
1610 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1612 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1613 // handle type legalization for these operations here.
1615 // FIXME: We really should do custom legalization for addition and
1616 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1617 // than generic legalization for 64-bit multiplication-with-overflow, though.
1618 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1619 // Add/Sub/Mul with overflow operations are custom lowered.
1621 setOperationAction(ISD::SADDO, VT, Custom);
1622 setOperationAction(ISD::UADDO, VT, Custom);
1623 setOperationAction(ISD::SSUBO, VT, Custom);
1624 setOperationAction(ISD::USUBO, VT, Custom);
1625 setOperationAction(ISD::SMULO, VT, Custom);
1626 setOperationAction(ISD::UMULO, VT, Custom);
1630 if (!Subtarget->is64Bit()) {
1631 // These libcalls are not available in 32-bit.
1632 setLibcallName(RTLIB::SHL_I128, nullptr);
1633 setLibcallName(RTLIB::SRL_I128, nullptr);
1634 setLibcallName(RTLIB::SRA_I128, nullptr);
1637 // Combine sin / cos into one node or libcall if possible.
1638 if (Subtarget->hasSinCos()) {
1639 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1640 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1641 if (Subtarget->isTargetDarwin()) {
1642 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1643 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1644 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1645 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1649 if (Subtarget->isTargetWin64()) {
1650 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1651 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1652 setOperationAction(ISD::SREM, MVT::i128, Custom);
1653 setOperationAction(ISD::UREM, MVT::i128, Custom);
1654 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1655 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1658 // We have target-specific dag combine patterns for the following nodes:
1659 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1660 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1661 setTargetDAGCombine(ISD::VSELECT);
1662 setTargetDAGCombine(ISD::SELECT);
1663 setTargetDAGCombine(ISD::SHL);
1664 setTargetDAGCombine(ISD::SRA);
1665 setTargetDAGCombine(ISD::SRL);
1666 setTargetDAGCombine(ISD::OR);
1667 setTargetDAGCombine(ISD::AND);
1668 setTargetDAGCombine(ISD::ADD);
1669 setTargetDAGCombine(ISD::FADD);
1670 setTargetDAGCombine(ISD::FSUB);
1671 setTargetDAGCombine(ISD::FMA);
1672 setTargetDAGCombine(ISD::SUB);
1673 setTargetDAGCombine(ISD::LOAD);
1674 setTargetDAGCombine(ISD::STORE);
1675 setTargetDAGCombine(ISD::ZERO_EXTEND);
1676 setTargetDAGCombine(ISD::ANY_EXTEND);
1677 setTargetDAGCombine(ISD::SIGN_EXTEND);
1678 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1679 setTargetDAGCombine(ISD::TRUNCATE);
1680 setTargetDAGCombine(ISD::SINT_TO_FP);
1681 setTargetDAGCombine(ISD::SETCC);
1682 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1683 setTargetDAGCombine(ISD::BUILD_VECTOR);
1684 if (Subtarget->is64Bit())
1685 setTargetDAGCombine(ISD::MUL);
1686 setTargetDAGCombine(ISD::XOR);
1688 computeRegisterProperties();
1690 // On Darwin, -Os means optimize for size without hurting performance,
1691 // do not reduce the limit.
1692 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1693 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1694 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1695 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1696 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1697 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1698 setPrefLoopAlignment(4); // 2^4 bytes.
1700 // Predictable cmov don't hurt on atom because it's in-order.
1701 PredictableSelectIsExpensive = !Subtarget->isAtom();
1702 EnableExtLdPromotion = true;
1703 setPrefFunctionAlignment(4); // 2^4 bytes.
1705 verifyIntrinsicTables();
1708 // This has so far only been implemented for 64-bit MachO.
1709 bool X86TargetLowering::useLoadStackGuardNode() const {
1710 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1713 TargetLoweringBase::LegalizeTypeAction
1714 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1715 if (ExperimentalVectorWideningLegalization &&
1716 VT.getVectorNumElements() != 1 &&
1717 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1718 return TypeWidenVector;
1720 return TargetLoweringBase::getPreferredVectorAction(VT);
1723 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1725 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1727 const unsigned NumElts = VT.getVectorNumElements();
1728 const EVT EltVT = VT.getVectorElementType();
1729 if (VT.is512BitVector()) {
1730 if (Subtarget->hasAVX512())
1731 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1732 EltVT == MVT::f32 || EltVT == MVT::f64)
1734 case 8: return MVT::v8i1;
1735 case 16: return MVT::v16i1;
1737 if (Subtarget->hasBWI())
1738 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1740 case 32: return MVT::v32i1;
1741 case 64: return MVT::v64i1;
1745 if (VT.is256BitVector() || VT.is128BitVector()) {
1746 if (Subtarget->hasVLX())
1747 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1748 EltVT == MVT::f32 || EltVT == MVT::f64)
1750 case 2: return MVT::v2i1;
1751 case 4: return MVT::v4i1;
1752 case 8: return MVT::v8i1;
1754 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1755 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1757 case 8: return MVT::v8i1;
1758 case 16: return MVT::v16i1;
1759 case 32: return MVT::v32i1;
1763 return VT.changeVectorElementTypeToInteger();
1766 /// Helper for getByValTypeAlignment to determine
1767 /// the desired ByVal argument alignment.
1768 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1771 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1772 if (VTy->getBitWidth() == 128)
1774 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1775 unsigned EltAlign = 0;
1776 getMaxByValAlign(ATy->getElementType(), EltAlign);
1777 if (EltAlign > MaxAlign)
1778 MaxAlign = EltAlign;
1779 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1780 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1781 unsigned EltAlign = 0;
1782 getMaxByValAlign(STy->getElementType(i), EltAlign);
1783 if (EltAlign > MaxAlign)
1784 MaxAlign = EltAlign;
1791 /// Return the desired alignment for ByVal aggregate
1792 /// function arguments in the caller parameter area. For X86, aggregates
1793 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1794 /// are at 4-byte boundaries.
1795 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1796 if (Subtarget->is64Bit()) {
1797 // Max of 8 and alignment of type.
1798 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1805 if (Subtarget->hasSSE1())
1806 getMaxByValAlign(Ty, Align);
1810 /// Returns the target specific optimal type for load
1811 /// and store operations as a result of memset, memcpy, and memmove
1812 /// lowering. If DstAlign is zero that means it's safe to destination
1813 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1814 /// means there isn't a need to check it against alignment requirement,
1815 /// probably because the source does not need to be loaded. If 'IsMemset' is
1816 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1817 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1818 /// source is constant so it does not need to be loaded.
1819 /// It returns EVT::Other if the type should be determined using generic
1820 /// target-independent logic.
1822 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1823 unsigned DstAlign, unsigned SrcAlign,
1824 bool IsMemset, bool ZeroMemset,
1826 MachineFunction &MF) const {
1827 const Function *F = MF.getFunction();
1828 if ((!IsMemset || ZeroMemset) &&
1829 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1830 Attribute::NoImplicitFloat)) {
1832 (Subtarget->isUnalignedMemAccessFast() ||
1833 ((DstAlign == 0 || DstAlign >= 16) &&
1834 (SrcAlign == 0 || SrcAlign >= 16)))) {
1836 if (Subtarget->hasInt256())
1838 if (Subtarget->hasFp256())
1841 if (Subtarget->hasSSE2())
1843 if (Subtarget->hasSSE1())
1845 } else if (!MemcpyStrSrc && Size >= 8 &&
1846 !Subtarget->is64Bit() &&
1847 Subtarget->hasSSE2()) {
1848 // Do not use f64 to lower memcpy if source is string constant. It's
1849 // better to use i32 to avoid the loads.
1853 if (Subtarget->is64Bit() && Size >= 8)
1858 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1860 return X86ScalarSSEf32;
1861 else if (VT == MVT::f64)
1862 return X86ScalarSSEf64;
1867 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1872 *Fast = Subtarget->isUnalignedMemAccessFast();
1876 /// Return the entry encoding for a jump table in the
1877 /// current function. The returned value is a member of the
1878 /// MachineJumpTableInfo::JTEntryKind enum.
1879 unsigned X86TargetLowering::getJumpTableEncoding() const {
1880 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1882 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1883 Subtarget->isPICStyleGOT())
1884 return MachineJumpTableInfo::EK_Custom32;
1886 // Otherwise, use the normal jump table encoding heuristics.
1887 return TargetLowering::getJumpTableEncoding();
1891 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1892 const MachineBasicBlock *MBB,
1893 unsigned uid,MCContext &Ctx) const{
1894 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1895 Subtarget->isPICStyleGOT());
1896 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1898 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1899 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1902 /// Returns relocation base for the given PIC jumptable.
1903 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1904 SelectionDAG &DAG) const {
1905 if (!Subtarget->is64Bit())
1906 // This doesn't have SDLoc associated with it, but is not really the
1907 // same as a Register.
1908 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1912 /// This returns the relocation base for the given PIC jumptable,
1913 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1914 const MCExpr *X86TargetLowering::
1915 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1916 MCContext &Ctx) const {
1917 // X86-64 uses RIP relative addressing based on the jump table label.
1918 if (Subtarget->isPICStyleRIPRel())
1919 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1921 // Otherwise, the reference is relative to the PIC base.
1922 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1925 // FIXME: Why this routine is here? Move to RegInfo!
1926 std::pair<const TargetRegisterClass*, uint8_t>
1927 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1928 const TargetRegisterClass *RRC = nullptr;
1930 switch (VT.SimpleTy) {
1932 return TargetLowering::findRepresentativeClass(VT);
1933 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1934 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1937 RRC = &X86::VR64RegClass;
1939 case MVT::f32: case MVT::f64:
1940 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1941 case MVT::v4f32: case MVT::v2f64:
1942 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1944 RRC = &X86::VR128RegClass;
1947 return std::make_pair(RRC, Cost);
1950 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1951 unsigned &Offset) const {
1952 if (!Subtarget->isTargetLinux())
1955 if (Subtarget->is64Bit()) {
1956 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1958 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1970 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1971 unsigned DestAS) const {
1972 assert(SrcAS != DestAS && "Expected different address spaces!");
1974 return SrcAS < 256 && DestAS < 256;
1977 //===----------------------------------------------------------------------===//
1978 // Return Value Calling Convention Implementation
1979 //===----------------------------------------------------------------------===//
1981 #include "X86GenCallingConv.inc"
1984 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1985 MachineFunction &MF, bool isVarArg,
1986 const SmallVectorImpl<ISD::OutputArg> &Outs,
1987 LLVMContext &Context) const {
1988 SmallVector<CCValAssign, 16> RVLocs;
1989 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1990 return CCInfo.CheckReturn(Outs, RetCC_X86);
1993 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1994 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1999 X86TargetLowering::LowerReturn(SDValue Chain,
2000 CallingConv::ID CallConv, bool isVarArg,
2001 const SmallVectorImpl<ISD::OutputArg> &Outs,
2002 const SmallVectorImpl<SDValue> &OutVals,
2003 SDLoc dl, SelectionDAG &DAG) const {
2004 MachineFunction &MF = DAG.getMachineFunction();
2005 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2007 SmallVector<CCValAssign, 16> RVLocs;
2008 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2009 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2012 SmallVector<SDValue, 6> RetOps;
2013 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2014 // Operand #1 = Bytes To Pop
2015 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2018 // Copy the result values into the output registers.
2019 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2020 CCValAssign &VA = RVLocs[i];
2021 assert(VA.isRegLoc() && "Can only return in registers!");
2022 SDValue ValToCopy = OutVals[i];
2023 EVT ValVT = ValToCopy.getValueType();
2025 // Promote values to the appropriate types.
2026 if (VA.getLocInfo() == CCValAssign::SExt)
2027 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 else if (VA.getLocInfo() == CCValAssign::ZExt)
2029 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 else if (VA.getLocInfo() == CCValAssign::AExt)
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2032 else if (VA.getLocInfo() == CCValAssign::BCvt)
2033 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2035 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2036 "Unexpected FP-extend for return value.");
2038 // If this is x86-64, and we disabled SSE, we can't return FP values,
2039 // or SSE or MMX vectors.
2040 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2041 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2042 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2043 report_fatal_error("SSE register return with SSE disabled");
2045 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2046 // llvm-gcc has never done it right and no one has noticed, so this
2047 // should be OK for now.
2048 if (ValVT == MVT::f64 &&
2049 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2050 report_fatal_error("SSE2 register return with SSE2 disabled");
2052 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2053 // the RET instruction and handled by the FP Stackifier.
2054 if (VA.getLocReg() == X86::FP0 ||
2055 VA.getLocReg() == X86::FP1) {
2056 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2057 // change the value to the FP stack register class.
2058 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2059 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2060 RetOps.push_back(ValToCopy);
2061 // Don't emit a copytoreg.
2065 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2066 // which is returned in RAX / RDX.
2067 if (Subtarget->is64Bit()) {
2068 if (ValVT == MVT::x86mmx) {
2069 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2070 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2071 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2073 // If we don't have SSE2 available, convert to v4f32 so the generated
2074 // register is legal.
2075 if (!Subtarget->hasSSE2())
2076 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2082 Flag = Chain.getValue(1);
2083 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2086 // The x86-64 ABIs require that for returning structs by value we copy
2087 // the sret argument into %rax/%eax (depending on ABI) for the return.
2088 // Win32 requires us to put the sret argument to %eax as well.
2089 // We saved the argument into a virtual register in the entry block,
2090 // so now we copy the value out and into %rax/%eax.
2091 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2092 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2093 MachineFunction &MF = DAG.getMachineFunction();
2094 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2095 unsigned Reg = FuncInfo->getSRetReturnReg();
2097 "SRetReturnReg should have been set in LowerFormalArguments().");
2098 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2101 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2102 X86::RAX : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2104 Flag = Chain.getValue(1);
2106 // RAX/EAX now acts like a return value.
2107 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2110 RetOps[0] = Chain; // Update chain.
2112 // Add the flag if we have it.
2114 RetOps.push_back(Flag);
2116 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2119 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2120 if (N->getNumValues() != 1)
2122 if (!N->hasNUsesOfValue(1, 0))
2125 SDValue TCChain = Chain;
2126 SDNode *Copy = *N->use_begin();
2127 if (Copy->getOpcode() == ISD::CopyToReg) {
2128 // If the copy has a glue operand, we conservatively assume it isn't safe to
2129 // perform a tail call.
2130 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2132 TCChain = Copy->getOperand(0);
2133 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2136 bool HasRet = false;
2137 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2139 if (UI->getOpcode() != X86ISD::RET_FLAG)
2141 // If we are returning more than one value, we can definitely
2142 // not make a tail call see PR19530
2143 if (UI->getNumOperands() > 4)
2145 if (UI->getNumOperands() == 4 &&
2146 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2159 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2160 ISD::NodeType ExtendKind) const {
2162 // TODO: Is this also valid on 32-bit?
2163 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2164 ReturnMVT = MVT::i8;
2166 ReturnMVT = MVT::i32;
2168 EVT MinVT = getRegisterType(Context, ReturnMVT);
2169 return VT.bitsLT(MinVT) ? MinVT : VT;
2172 /// Lower the result values of a call into the
2173 /// appropriate copies out of appropriate physical registers.
2176 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::InputArg> &Ins,
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2182 // Assign locations to each value returned by this call.
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 bool Is64Bit = Subtarget->is64Bit();
2185 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2189 // Copy all of the result registers out of their specified physreg.
2190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2191 CCValAssign &VA = RVLocs[i];
2192 EVT CopyVT = VA.getValVT();
2194 // If this is x86-64, and we disabled SSE, we can't return FP values
2195 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2196 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2197 report_fatal_error("SSE register return with SSE disabled");
2200 // If we prefer to use the value in xmm registers, copy it out as f80 and
2201 // use a truncate to move it from fp stack reg to xmm reg.
2202 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2203 isScalarFPTypeInSSEReg(VA.getValVT()))
2206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2207 CopyVT, InFlag).getValue(1);
2208 SDValue Val = Chain.getValue(0);
2210 if (CopyVT != VA.getValVT())
2211 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2212 // This truncation won't change the value.
2213 DAG.getIntPtrConstant(1));
2215 InFlag = Chain.getValue(2);
2216 InVals.push_back(Val);
2222 //===----------------------------------------------------------------------===//
2223 // C & StdCall & Fast Calling Convention implementation
2224 //===----------------------------------------------------------------------===//
2225 // StdCall calling convention seems to be standard for many Windows' API
2226 // routines and around. It differs from C calling convention just a little:
2227 // callee should clean up the stack, not caller. Symbols should be also
2228 // decorated in some fancy way :) It doesn't support any vector arguments.
2229 // For info on fast calling convention see Fast Calling Convention (tail call)
2230 // implementation LowerX86_32FastCCCallTo.
2232 /// CallIsStructReturn - Determines whether a call uses struct return
2234 enum StructReturnType {
2239 static StructReturnType
2240 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2242 return NotStructReturn;
2244 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2245 if (!Flags.isSRet())
2246 return NotStructReturn;
2247 if (Flags.isInReg())
2248 return RegStructReturn;
2249 return StackStructReturn;
2252 /// Determines whether a function uses struct return semantics.
2253 static StructReturnType
2254 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2256 return NotStructReturn;
2258 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2259 if (!Flags.isSRet())
2260 return NotStructReturn;
2261 if (Flags.isInReg())
2262 return RegStructReturn;
2263 return StackStructReturn;
2266 /// Make a copy of an aggregate at address specified by "Src" to address
2267 /// "Dst" with size and alignment information specified by the specific
2268 /// parameter attribute. The copy will be passed as a byval function parameter.
2270 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2271 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2273 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2275 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2276 /*isVolatile*/false, /*AlwaysInline=*/true,
2277 MachinePointerInfo(), MachinePointerInfo());
2280 /// Return true if the calling convention is one that
2281 /// supports tail call optimization.
2282 static bool IsTailCallConvention(CallingConv::ID CC) {
2283 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2284 CC == CallingConv::HiPE);
2287 /// \brief Return true if the calling convention is a C calling convention.
2288 static bool IsCCallConvention(CallingConv::ID CC) {
2289 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2290 CC == CallingConv::X86_64_SysV);
2293 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2294 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2298 CallingConv::ID CalleeCC = CS.getCallingConv();
2299 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2305 /// Return true if the function is being made into
2306 /// a tailcall target by changing its ABI.
2307 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2308 bool GuaranteedTailCallOpt) {
2309 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2313 X86TargetLowering::LowerMemArgument(SDValue Chain,
2314 CallingConv::ID CallConv,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 const CCValAssign &VA,
2318 MachineFrameInfo *MFI,
2320 // Create the nodes corresponding to a load from this parameter slot.
2321 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2322 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2323 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2324 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2327 // If value is passed by pointer we have address passed instead of the value
2329 if (VA.getLocInfo() == CCValAssign::Indirect)
2330 ValVT = VA.getLocVT();
2332 ValVT = VA.getValVT();
2334 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2335 // changed with more analysis.
2336 // In case of tail call optimization mark all arguments mutable. Since they
2337 // could be overwritten by lowering of arguments in case of a tail call.
2338 if (Flags.isByVal()) {
2339 unsigned Bytes = Flags.getByValSize();
2340 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2341 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2342 return DAG.getFrameIndex(FI, getPointerTy());
2344 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2345 VA.getLocMemOffset(), isImmutable);
2346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2347 return DAG.getLoad(ValVT, dl, Chain, FIN,
2348 MachinePointerInfo::getFixedStack(FI),
2349 false, false, false, 0);
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2355 const X86Subtarget *Subtarget) {
2356 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 static const MCPhysReg GPR64ArgRegsWin64[] = {
2360 X86::RCX, X86::RDX, X86::R8, X86::R9
2362 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2365 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2366 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2368 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2371 // FIXME: Get this from tablegen.
2372 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2373 CallingConv::ID CallConv,
2374 const X86Subtarget *Subtarget) {
2375 assert(Subtarget->is64Bit());
2376 if (Subtarget->isCallingConvWin64(CallConv)) {
2377 // The XMM registers which might contain var arg parameters are shadowed
2378 // in their paired GPR. So we only need to save the GPR to their home
2380 // TODO: __vectorcall will change this.
2384 const Function *Fn = MF.getFunction();
2385 bool NoImplicitFloatOps = Fn->getAttributes().
2386 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2387 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2388 "SSE register cannot be used when SSE is disabled!");
2389 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2390 !Subtarget->hasSSE1())
2391 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2395 static const MCPhysReg XMMArgRegs64Bit[] = {
2396 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2397 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2399 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2403 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2404 CallingConv::ID CallConv,
2406 const SmallVectorImpl<ISD::InputArg> &Ins,
2409 SmallVectorImpl<SDValue> &InVals)
2411 MachineFunction &MF = DAG.getMachineFunction();
2412 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2414 const Function* Fn = MF.getFunction();
2415 if (Fn->hasExternalLinkage() &&
2416 Subtarget->isTargetCygMing() &&
2417 Fn->getName() == "main")
2418 FuncInfo->setForceFramePointer(true);
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 bool Is64Bit = Subtarget->is64Bit();
2422 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2424 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2425 "Var args not supported with calling convention fastcc, ghc or hipe");
2427 // Assign locations to all of the incoming arguments.
2428 SmallVector<CCValAssign, 16> ArgLocs;
2429 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2431 // Allocate shadow area for Win64
2433 CCInfo.AllocateStack(32, 8);
2435 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2437 unsigned LastVal = ~0U;
2439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2440 CCValAssign &VA = ArgLocs[i];
2441 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2443 assert(VA.getValNo() != LastVal &&
2444 "Don't support value assigned to multiple locs yet");
2446 LastVal = VA.getValNo();
2448 if (VA.isRegLoc()) {
2449 EVT RegVT = VA.getLocVT();
2450 const TargetRegisterClass *RC;
2451 if (RegVT == MVT::i32)
2452 RC = &X86::GR32RegClass;
2453 else if (Is64Bit && RegVT == MVT::i64)
2454 RC = &X86::GR64RegClass;
2455 else if (RegVT == MVT::f32)
2456 RC = &X86::FR32RegClass;
2457 else if (RegVT == MVT::f64)
2458 RC = &X86::FR64RegClass;
2459 else if (RegVT.is512BitVector())
2460 RC = &X86::VR512RegClass;
2461 else if (RegVT.is256BitVector())
2462 RC = &X86::VR256RegClass;
2463 else if (RegVT.is128BitVector())
2464 RC = &X86::VR128RegClass;
2465 else if (RegVT == MVT::x86mmx)
2466 RC = &X86::VR64RegClass;
2467 else if (RegVT == MVT::i1)
2468 RC = &X86::VK1RegClass;
2469 else if (RegVT == MVT::v8i1)
2470 RC = &X86::VK8RegClass;
2471 else if (RegVT == MVT::v16i1)
2472 RC = &X86::VK16RegClass;
2473 else if (RegVT == MVT::v32i1)
2474 RC = &X86::VK32RegClass;
2475 else if (RegVT == MVT::v64i1)
2476 RC = &X86::VK64RegClass;
2478 llvm_unreachable("Unknown argument type!");
2480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2483 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2484 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2486 if (VA.getLocInfo() == CCValAssign::SExt)
2487 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2488 DAG.getValueType(VA.getValVT()));
2489 else if (VA.getLocInfo() == CCValAssign::ZExt)
2490 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2491 DAG.getValueType(VA.getValVT()));
2492 else if (VA.getLocInfo() == CCValAssign::BCvt)
2493 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2495 if (VA.isExtInLoc()) {
2496 // Handle MMX values passed in XMM regs.
2497 if (RegVT.isVector())
2498 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2500 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2503 assert(VA.isMemLoc());
2504 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2507 // If value is passed via pointer - do a load.
2508 if (VA.getLocInfo() == CCValAssign::Indirect)
2509 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2510 MachinePointerInfo(), false, false, false, 0);
2512 InVals.push_back(ArgValue);
2515 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2517 // The x86-64 ABIs require that for returning structs by value we copy
2518 // the sret argument into %rax/%eax (depending on ABI) for the return.
2519 // Win32 requires us to put the sret argument to %eax as well.
2520 // Save the argument into a virtual register so that we can access it
2521 // from the return points.
2522 if (Ins[i].Flags.isSRet()) {
2523 unsigned Reg = FuncInfo->getSRetReturnReg();
2525 MVT PtrTy = getPointerTy();
2526 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2527 FuncInfo->setSRetReturnReg(Reg);
2529 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2530 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2536 unsigned StackSize = CCInfo.getNextStackOffset();
2537 // Align stack specially for tail calls.
2538 if (FuncIsMadeTailCallSafe(CallConv,
2539 MF.getTarget().Options.GuaranteedTailCallOpt))
2540 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2542 // If the function takes variable number of arguments, make a frame index for
2543 // the start of the first vararg value... for expansion of llvm.va_start. We
2544 // can skip this if there are no va_start calls.
2545 if (MFI->hasVAStart() &&
2546 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2547 CallConv != CallingConv::X86_ThisCall))) {
2548 FuncInfo->setVarArgsFrameIndex(
2549 MFI->CreateFixedObject(1, StackSize, true));
2552 // Figure out if XMM registers are in use.
2553 bool HaveXMMArgs = Is64Bit && !IsWin64;
2554 bool NoImplicitFloatOps = Fn->getAttributes().hasAttribute(
2555 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2556 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2557 "SSE register cannot be used when SSE is disabled!");
2558 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2559 !Subtarget->hasSSE1())
2560 HaveXMMArgs = false;
2562 // 64-bit calling conventions support varargs and register parameters, so we
2563 // have to do extra work to spill them in the prologue.
2564 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2565 // Find the first unallocated argument registers.
2566 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2567 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2568 unsigned NumIntRegs =
2569 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2570 unsigned NumXMMRegs =
2571 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2572 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2573 "SSE register cannot be used when SSE is disabled!");
2575 // Gather all the live in physical registers.
2576 SmallVector<SDValue, 6> LiveGPRs;
2577 SmallVector<SDValue, 8> LiveXMMRegs;
2579 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2580 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2582 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2584 if (!ArgXMMs.empty()) {
2585 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2586 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2587 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2588 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2589 LiveXMMRegs.push_back(
2590 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2595 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2596 // Get to the caller-allocated home save location. Add 8 to account
2597 // for the return address.
2598 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2599 FuncInfo->setRegSaveFrameIndex(
2600 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2601 // Fixup to set vararg frame on shadow area (4 x i64).
2603 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2605 // For X86-64, if there are vararg parameters that are passed via
2606 // registers, then we must store them to their spots on the stack so
2607 // they may be loaded by deferencing the result of va_next.
2608 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2609 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2610 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2611 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2614 // Store the integer parameter registers.
2615 SmallVector<SDValue, 8> MemOps;
2616 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2618 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2619 for (SDValue Val : LiveGPRs) {
2620 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2621 DAG.getIntPtrConstant(Offset));
2623 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2624 MachinePointerInfo::getFixedStack(
2625 FuncInfo->getRegSaveFrameIndex(), Offset),
2627 MemOps.push_back(Store);
2631 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2632 // Now store the XMM (fp + vector) parameter registers.
2633 SmallVector<SDValue, 12> SaveXMMOps;
2634 SaveXMMOps.push_back(Chain);
2635 SaveXMMOps.push_back(ALVal);
2636 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2637 FuncInfo->getRegSaveFrameIndex()));
2638 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2639 FuncInfo->getVarArgsFPOffset()));
2640 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2642 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2643 MVT::Other, SaveXMMOps));
2646 if (!MemOps.empty())
2647 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2650 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2651 // Find the largest legal vector type.
2652 MVT VecVT = MVT::Other;
2653 // FIXME: Only some x86_32 calling conventions support AVX512.
2654 if (Subtarget->hasAVX512() &&
2655 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2656 CallConv == CallingConv::Intel_OCL_BI)))
2657 VecVT = MVT::v16f32;
2658 else if (Subtarget->hasAVX())
2660 else if (Subtarget->hasSSE2())
2663 // We forward some GPRs and some vector types.
2664 SmallVector<MVT, 2> RegParmTypes;
2665 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2666 RegParmTypes.push_back(IntVT);
2667 if (VecVT != MVT::Other)
2668 RegParmTypes.push_back(VecVT);
2670 // Compute the set of forwarded registers. The rest are scratch.
2671 SmallVectorImpl<ForwardedRegister> &Forwards =
2672 FuncInfo->getForwardedMustTailRegParms();
2673 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2675 // Conservatively forward AL on x86_64, since it might be used for varargs.
2676 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2677 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2678 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2681 // Copy all forwards from physical to virtual registers.
2682 for (ForwardedRegister &F : Forwards) {
2683 // FIXME: Can we use a less constrained schedule?
2684 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2685 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2686 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2690 // Some CCs need callee pop.
2691 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2692 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2693 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2695 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2696 // If this is an sret function, the return should pop the hidden pointer.
2697 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2698 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2699 argsAreStructReturn(Ins) == StackStructReturn)
2700 FuncInfo->setBytesToPopOnReturn(4);
2704 // RegSaveFrameIndex is X86-64 only.
2705 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2706 if (CallConv == CallingConv::X86_FastCall ||
2707 CallConv == CallingConv::X86_ThisCall)
2708 // fastcc functions can't have varargs.
2709 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2712 FuncInfo->setArgumentStackSize(StackSize);
2718 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2719 SDValue StackPtr, SDValue Arg,
2720 SDLoc dl, SelectionDAG &DAG,
2721 const CCValAssign &VA,
2722 ISD::ArgFlagsTy Flags) const {
2723 unsigned LocMemOffset = VA.getLocMemOffset();
2724 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2725 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2726 if (Flags.isByVal())
2727 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2729 return DAG.getStore(Chain, dl, Arg, PtrOff,
2730 MachinePointerInfo::getStack(LocMemOffset),
2734 /// Emit a load of return address if tail call
2735 /// optimization is performed and it is required.
2737 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2738 SDValue &OutRetAddr, SDValue Chain,
2739 bool IsTailCall, bool Is64Bit,
2740 int FPDiff, SDLoc dl) const {
2741 // Adjust the Return address stack slot.
2742 EVT VT = getPointerTy();
2743 OutRetAddr = getReturnAddressFrameIndex(DAG);
2745 // Load the "old" Return address.
2746 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2747 false, false, false, 0);
2748 return SDValue(OutRetAddr.getNode(), 1);
2751 /// Emit a store of the return address if tail call
2752 /// optimization is performed and it is required (FPDiff!=0).
2753 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2754 SDValue Chain, SDValue RetAddrFrIdx,
2755 EVT PtrVT, unsigned SlotSize,
2756 int FPDiff, SDLoc dl) {
2757 // Store the return address to the appropriate stack slot.
2758 if (!FPDiff) return Chain;
2759 // Calculate the new stack slot for the return address.
2760 int NewReturnAddrFI =
2761 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2763 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2764 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2765 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2771 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2772 SmallVectorImpl<SDValue> &InVals) const {
2773 SelectionDAG &DAG = CLI.DAG;
2775 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2776 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2777 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2778 SDValue Chain = CLI.Chain;
2779 SDValue Callee = CLI.Callee;
2780 CallingConv::ID CallConv = CLI.CallConv;
2781 bool &isTailCall = CLI.IsTailCall;
2782 bool isVarArg = CLI.IsVarArg;
2784 MachineFunction &MF = DAG.getMachineFunction();
2785 bool Is64Bit = Subtarget->is64Bit();
2786 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2787 StructReturnType SR = callIsStructReturn(Outs);
2788 bool IsSibcall = false;
2789 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2791 if (MF.getTarget().Options.DisableTailCalls)
2794 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2796 // Force this to be a tail call. The verifier rules are enough to ensure
2797 // that we can lower this successfully without moving the return address
2800 } else if (isTailCall) {
2801 // Check if it's really possible to do a tail call.
2802 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2803 isVarArg, SR != NotStructReturn,
2804 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2805 Outs, OutVals, Ins, DAG);
2807 // Sibcalls are automatically detected tailcalls which do not require
2809 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2816 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2817 "Var args not supported with calling convention fastcc, ghc or hipe");
2819 // Analyze operands of the call, assigning locations to each operand.
2820 SmallVector<CCValAssign, 16> ArgLocs;
2821 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2823 // Allocate shadow area for Win64
2825 CCInfo.AllocateStack(32, 8);
2827 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2829 // Get a count of how many bytes are to be pushed on the stack.
2830 unsigned NumBytes = CCInfo.getNextStackOffset();
2832 // This is a sibcall. The memory operands are available in caller's
2833 // own caller's stack.
2835 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2836 IsTailCallConvention(CallConv))
2837 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2840 if (isTailCall && !IsSibcall && !IsMustTail) {
2841 // Lower arguments at fp - stackoffset + fpdiff.
2842 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2844 FPDiff = NumBytesCallerPushed - NumBytes;
2846 // Set the delta of movement of the returnaddr stackslot.
2847 // But only set if delta is greater than previous delta.
2848 if (FPDiff < X86Info->getTCReturnAddrDelta())
2849 X86Info->setTCReturnAddrDelta(FPDiff);
2852 unsigned NumBytesToPush = NumBytes;
2853 unsigned NumBytesToPop = NumBytes;
2855 // If we have an inalloca argument, all stack space has already been allocated
2856 // for us and be right at the top of the stack. We don't support multiple
2857 // arguments passed in memory when using inalloca.
2858 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2860 if (!ArgLocs.back().isMemLoc())
2861 report_fatal_error("cannot use inalloca attribute on a register "
2863 if (ArgLocs.back().getLocMemOffset() != 0)
2864 report_fatal_error("any parameter with the inalloca attribute must be "
2865 "the only memory argument");
2869 Chain = DAG.getCALLSEQ_START(
2870 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2872 SDValue RetAddrFrIdx;
2873 // Load return address for tail calls.
2874 if (isTailCall && FPDiff)
2875 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2876 Is64Bit, FPDiff, dl);
2878 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2879 SmallVector<SDValue, 8> MemOpChains;
2882 // Walk the register/memloc assignments, inserting copies/loads. In the case
2883 // of tail call optimization arguments are handle later.
2884 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2885 DAG.getSubtarget().getRegisterInfo());
2886 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2887 // Skip inalloca arguments, they have already been written.
2888 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2889 if (Flags.isInAlloca())
2892 CCValAssign &VA = ArgLocs[i];
2893 EVT RegVT = VA.getLocVT();
2894 SDValue Arg = OutVals[i];
2895 bool isByVal = Flags.isByVal();
2897 // Promote the value if needed.
2898 switch (VA.getLocInfo()) {
2899 default: llvm_unreachable("Unknown loc info!");
2900 case CCValAssign::Full: break;
2901 case CCValAssign::SExt:
2902 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2904 case CCValAssign::ZExt:
2905 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2907 case CCValAssign::AExt:
2908 if (RegVT.is128BitVector()) {
2909 // Special case: passing MMX values in XMM registers.
2910 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2911 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2912 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2914 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2916 case CCValAssign::BCvt:
2917 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2919 case CCValAssign::Indirect: {
2920 // Store the argument.
2921 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2922 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2923 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2924 MachinePointerInfo::getFixedStack(FI),
2931 if (VA.isRegLoc()) {
2932 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2933 if (isVarArg && IsWin64) {
2934 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2935 // shadow reg if callee is a varargs function.
2936 unsigned ShadowReg = 0;
2937 switch (VA.getLocReg()) {
2938 case X86::XMM0: ShadowReg = X86::RCX; break;
2939 case X86::XMM1: ShadowReg = X86::RDX; break;
2940 case X86::XMM2: ShadowReg = X86::R8; break;
2941 case X86::XMM3: ShadowReg = X86::R9; break;
2944 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2946 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2947 assert(VA.isMemLoc());
2948 if (!StackPtr.getNode())
2949 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2951 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2952 dl, DAG, VA, Flags));
2956 if (!MemOpChains.empty())
2957 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2959 if (Subtarget->isPICStyleGOT()) {
2960 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2964 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2966 // If we are tail calling and generating PIC/GOT style code load the
2967 // address of the callee into ECX. The value in ecx is used as target of
2968 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2969 // for tail calls on PIC/GOT architectures. Normally we would just put the
2970 // address of GOT into ebx and then call target@PLT. But for tail calls
2971 // ebx would be restored (since ebx is callee saved) before jumping to the
2974 // Note: The actual moving to ECX is done further down.
2975 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2976 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2977 !G->getGlobal()->hasProtectedVisibility())
2978 Callee = LowerGlobalAddress(Callee, DAG);
2979 else if (isa<ExternalSymbolSDNode>(Callee))
2980 Callee = LowerExternalSymbol(Callee, DAG);
2984 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2985 // From AMD64 ABI document:
2986 // For calls that may call functions that use varargs or stdargs
2987 // (prototype-less calls or calls to functions containing ellipsis (...) in
2988 // the declaration) %al is used as hidden argument to specify the number
2989 // of SSE registers used. The contents of %al do not need to match exactly
2990 // the number of registers, but must be an ubound on the number of SSE
2991 // registers used and is in the range 0 - 8 inclusive.
2993 // Count the number of XMM registers allocated.
2994 static const MCPhysReg XMMArgRegs[] = {
2995 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2996 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2998 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2999 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3000 && "SSE registers cannot be used when SSE is disabled");
3002 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3003 DAG.getConstant(NumXMMRegs, MVT::i8)));
3006 if (isVarArg && IsMustTail) {
3007 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3008 for (const auto &F : Forwards) {
3009 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3010 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3014 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3015 // don't need this because the eligibility check rejects calls that require
3016 // shuffling arguments passed in memory.
3017 if (!IsSibcall && isTailCall) {
3018 // Force all the incoming stack arguments to be loaded from the stack
3019 // before any new outgoing arguments are stored to the stack, because the
3020 // outgoing stack slots may alias the incoming argument stack slots, and
3021 // the alias isn't otherwise explicit. This is slightly more conservative
3022 // than necessary, because it means that each store effectively depends
3023 // on every argument instead of just those arguments it would clobber.
3024 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3026 SmallVector<SDValue, 8> MemOpChains2;
3029 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3030 CCValAssign &VA = ArgLocs[i];
3033 assert(VA.isMemLoc());
3034 SDValue Arg = OutVals[i];
3035 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3036 // Skip inalloca arguments. They don't require any work.
3037 if (Flags.isInAlloca())
3039 // Create frame index.
3040 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3041 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3042 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3043 FIN = DAG.getFrameIndex(FI, getPointerTy());
3045 if (Flags.isByVal()) {
3046 // Copy relative to framepointer.
3047 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3048 if (!StackPtr.getNode())
3049 StackPtr = DAG.getCopyFromReg(Chain, dl,
3050 RegInfo->getStackRegister(),
3052 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3054 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3058 // Store relative to framepointer.
3059 MemOpChains2.push_back(
3060 DAG.getStore(ArgChain, dl, Arg, FIN,
3061 MachinePointerInfo::getFixedStack(FI),
3066 if (!MemOpChains2.empty())
3067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3069 // Store the return address to the appropriate stack slot.
3070 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3071 getPointerTy(), RegInfo->getSlotSize(),
3075 // Build a sequence of copy-to-reg nodes chained together with token chain
3076 // and flag operands which copy the outgoing args into registers.
3078 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3079 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3080 RegsToPass[i].second, InFlag);
3081 InFlag = Chain.getValue(1);
3084 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3085 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3086 // In the 64-bit large code model, we have to make all calls
3087 // through a register, since the call instruction's 32-bit
3088 // pc-relative offset may not be large enough to hold the whole
3090 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3091 // If the callee is a GlobalAddress node (quite common, every direct call
3092 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3095 // We should use extra load for direct calls to dllimported functions in
3097 const GlobalValue *GV = G->getGlobal();
3098 if (!GV->hasDLLImportStorageClass()) {
3099 unsigned char OpFlags = 0;
3100 bool ExtraLoad = false;
3101 unsigned WrapperKind = ISD::DELETED_NODE;
3103 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3104 // external symbols most go through the PLT in PIC mode. If the symbol
3105 // has hidden or protected visibility, or if it is static or local, then
3106 // we don't need to use the PLT - we can directly call it.
3107 if (Subtarget->isTargetELF() &&
3108 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3109 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3110 OpFlags = X86II::MO_PLT;
3111 } else if (Subtarget->isPICStyleStubAny() &&
3112 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3119 } else if (Subtarget->isPICStyleRIPRel() &&
3120 isa<Function>(GV) &&
3121 cast<Function>(GV)->getAttributes().
3122 hasAttribute(AttributeSet::FunctionIndex,
3123 Attribute::NonLazyBind)) {
3124 // If the function is marked as non-lazy, generate an indirect call
3125 // which loads from the GOT directly. This avoids runtime overhead
3126 // at the cost of eager binding (and one extra byte of encoding).
3127 OpFlags = X86II::MO_GOTPCREL;
3128 WrapperKind = X86ISD::WrapperRIP;
3132 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3133 G->getOffset(), OpFlags);
3135 // Add a wrapper if needed.
3136 if (WrapperKind != ISD::DELETED_NODE)
3137 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3138 // Add extra indirection if needed.
3140 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3141 MachinePointerInfo::getGOT(),
3142 false, false, false, 0);
3144 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3145 unsigned char OpFlags = 0;
3147 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3148 // external symbols should go through the PLT.
3149 if (Subtarget->isTargetELF() &&
3150 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3151 OpFlags = X86II::MO_PLT;
3152 } else if (Subtarget->isPICStyleStubAny() &&
3153 (!Subtarget->getTargetTriple().isMacOSX() ||
3154 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3155 // PC-relative references to external symbols should go through $stub,
3156 // unless we're building with the leopard linker or later, which
3157 // automatically synthesizes these stubs.
3158 OpFlags = X86II::MO_DARWIN_STUB;
3161 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3163 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3164 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3165 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3168 // Returns a chain & a flag for retval copy to use.
3169 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3170 SmallVector<SDValue, 8> Ops;
3172 if (!IsSibcall && isTailCall) {
3173 Chain = DAG.getCALLSEQ_END(Chain,
3174 DAG.getIntPtrConstant(NumBytesToPop, true),
3175 DAG.getIntPtrConstant(0, true), InFlag, dl);
3176 InFlag = Chain.getValue(1);
3179 Ops.push_back(Chain);
3180 Ops.push_back(Callee);
3183 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3185 // Add argument registers to the end of the list so that they are known live
3187 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3188 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3189 RegsToPass[i].second.getValueType()));
3191 // Add a register mask operand representing the call-preserved registers.
3192 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3193 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3194 assert(Mask && "Missing call preserved mask for calling convention");
3195 Ops.push_back(DAG.getRegisterMask(Mask));
3197 if (InFlag.getNode())
3198 Ops.push_back(InFlag);
3202 //// If this is the first return lowered for this function, add the regs
3203 //// to the liveout set for the function.
3204 // This isn't right, although it's probably harmless on x86; liveouts
3205 // should be computed from returns not tail calls. Consider a void
3206 // function making a tail call to a function returning int.
3207 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3210 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3211 InFlag = Chain.getValue(1);
3213 // Create the CALLSEQ_END node.
3214 unsigned NumBytesForCalleeToPop;
3215 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3216 DAG.getTarget().Options.GuaranteedTailCallOpt))
3217 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3218 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3219 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3220 SR == StackStructReturn)
3221 // If this is a call to a struct-return function, the callee
3222 // pops the hidden struct pointer, so we have to push it back.
3223 // This is common for Darwin/X86, Linux & Mingw32 targets.
3224 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3225 NumBytesForCalleeToPop = 4;
3227 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3229 // Returns a flag for retval copy to use.
3231 Chain = DAG.getCALLSEQ_END(Chain,
3232 DAG.getIntPtrConstant(NumBytesToPop, true),
3233 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3236 InFlag = Chain.getValue(1);
3239 // Handle result values, copying them out of physregs into vregs that we
3241 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3242 Ins, dl, DAG, InVals);
3245 //===----------------------------------------------------------------------===//
3246 // Fast Calling Convention (tail call) implementation
3247 //===----------------------------------------------------------------------===//
3249 // Like std call, callee cleans arguments, convention except that ECX is
3250 // reserved for storing the tail called function address. Only 2 registers are
3251 // free for argument passing (inreg). Tail call optimization is performed
3253 // * tailcallopt is enabled
3254 // * caller/callee are fastcc
3255 // On X86_64 architecture with GOT-style position independent code only local
3256 // (within module) calls are supported at the moment.
3257 // To keep the stack aligned according to platform abi the function
3258 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3259 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3260 // If a tail called function callee has more arguments than the caller the
3261 // caller needs to make sure that there is room to move the RETADDR to. This is
3262 // achieved by reserving an area the size of the argument delta right after the
3263 // original RETADDR, but before the saved framepointer or the spilled registers
3264 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3276 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3277 /// for a 16 byte align requirement.
3279 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3280 SelectionDAG& DAG) const {
3281 MachineFunction &MF = DAG.getMachineFunction();
3282 const TargetMachine &TM = MF.getTarget();
3283 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3284 TM.getSubtargetImpl()->getRegisterInfo());
3285 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3286 unsigned StackAlignment = TFI.getStackAlignment();
3287 uint64_t AlignMask = StackAlignment - 1;
3288 int64_t Offset = StackSize;
3289 unsigned SlotSize = RegInfo->getSlotSize();
3290 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3291 // Number smaller than 12 so just add the difference.
3292 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3294 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3295 Offset = ((~AlignMask) & Offset) + StackAlignment +
3296 (StackAlignment-SlotSize);
3301 /// MatchingStackOffset - Return true if the given stack call argument is
3302 /// already available in the same position (relatively) of the caller's
3303 /// incoming argument stack.
3305 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3306 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3307 const X86InstrInfo *TII) {
3308 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3310 if (Arg.getOpcode() == ISD::CopyFromReg) {
3311 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3312 if (!TargetRegisterInfo::isVirtualRegister(VR))
3314 MachineInstr *Def = MRI->getVRegDef(VR);
3317 if (!Flags.isByVal()) {
3318 if (!TII->isLoadFromStackSlot(Def, FI))
3321 unsigned Opcode = Def->getOpcode();
3322 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3323 Def->getOperand(1).isFI()) {
3324 FI = Def->getOperand(1).getIndex();
3325 Bytes = Flags.getByValSize();
3329 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3330 if (Flags.isByVal())
3331 // ByVal argument is passed in as a pointer but it's now being
3332 // dereferenced. e.g.
3333 // define @foo(%struct.X* %A) {
3334 // tail call @bar(%struct.X* byval %A)
3337 SDValue Ptr = Ld->getBasePtr();
3338 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3341 FI = FINode->getIndex();
3342 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3343 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3344 FI = FINode->getIndex();
3345 Bytes = Flags.getByValSize();
3349 assert(FI != INT_MAX);
3350 if (!MFI->isFixedObjectIndex(FI))
3352 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3355 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3356 /// for tail call optimization. Targets which want to do tail call
3357 /// optimization should implement this function.
3359 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3360 CallingConv::ID CalleeCC,
3362 bool isCalleeStructRet,
3363 bool isCallerStructRet,
3365 const SmallVectorImpl<ISD::OutputArg> &Outs,
3366 const SmallVectorImpl<SDValue> &OutVals,
3367 const SmallVectorImpl<ISD::InputArg> &Ins,
3368 SelectionDAG &DAG) const {
3369 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3372 // If -tailcallopt is specified, make fastcc functions tail-callable.
3373 const MachineFunction &MF = DAG.getMachineFunction();
3374 const Function *CallerF = MF.getFunction();
3376 // If the function return type is x86_fp80 and the callee return type is not,
3377 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3378 // perform a tailcall optimization here.
3379 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3382 CallingConv::ID CallerCC = CallerF->getCallingConv();
3383 bool CCMatch = CallerCC == CalleeCC;
3384 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3385 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3387 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3388 if (IsTailCallConvention(CalleeCC) && CCMatch)
3393 // Look for obvious safe cases to perform tail call optimization that do not
3394 // require ABI changes. This is what gcc calls sibcall.
3396 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3397 // emit a special epilogue.
3398 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3399 DAG.getSubtarget().getRegisterInfo());
3400 if (RegInfo->needsStackRealignment(MF))
3403 // Also avoid sibcall optimization if either caller or callee uses struct
3404 // return semantics.
3405 if (isCalleeStructRet || isCallerStructRet)
3408 // An stdcall/thiscall caller is expected to clean up its arguments; the
3409 // callee isn't going to do that.
3410 // FIXME: this is more restrictive than needed. We could produce a tailcall
3411 // when the stack adjustment matches. For example, with a thiscall that takes
3412 // only one argument.
3413 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3414 CallerCC == CallingConv::X86_ThisCall))
3417 // Do not sibcall optimize vararg calls unless all arguments are passed via
3419 if (isVarArg && !Outs.empty()) {
3421 // Optimizing for varargs on Win64 is unlikely to be safe without
3422 // additional testing.
3423 if (IsCalleeWin64 || IsCallerWin64)
3426 SmallVector<CCValAssign, 16> ArgLocs;
3427 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3430 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3431 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3432 if (!ArgLocs[i].isRegLoc())
3436 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3437 // stack. Therefore, if it's not used by the call it is not safe to optimize
3438 // this into a sibcall.
3439 bool Unused = false;
3440 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3447 SmallVector<CCValAssign, 16> RVLocs;
3448 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3450 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3451 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3452 CCValAssign &VA = RVLocs[i];
3453 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3458 // If the calling conventions do not match, then we'd better make sure the
3459 // results are returned in the same way as what the caller expects.
3461 SmallVector<CCValAssign, 16> RVLocs1;
3462 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3464 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3466 SmallVector<CCValAssign, 16> RVLocs2;
3467 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3469 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3471 if (RVLocs1.size() != RVLocs2.size())
3473 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3474 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3476 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3478 if (RVLocs1[i].isRegLoc()) {
3479 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3482 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3488 // If the callee takes no arguments then go on to check the results of the
3490 if (!Outs.empty()) {
3491 // Check if stack adjustment is needed. For now, do not do this if any
3492 // argument is passed on the stack.
3493 SmallVector<CCValAssign, 16> ArgLocs;
3494 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3497 // Allocate shadow area for Win64
3499 CCInfo.AllocateStack(32, 8);
3501 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3502 if (CCInfo.getNextStackOffset()) {
3503 MachineFunction &MF = DAG.getMachineFunction();
3504 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3507 // Check if the arguments are already laid out in the right way as
3508 // the caller's fixed stack objects.
3509 MachineFrameInfo *MFI = MF.getFrameInfo();
3510 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3511 const X86InstrInfo *TII =
3512 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3513 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3514 CCValAssign &VA = ArgLocs[i];
3515 SDValue Arg = OutVals[i];
3516 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3517 if (VA.getLocInfo() == CCValAssign::Indirect)
3519 if (!VA.isRegLoc()) {
3520 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3527 // If the tailcall address may be in a register, then make sure it's
3528 // possible to register allocate for it. In 32-bit, the call address can
3529 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3530 // callee-saved registers are restored. These happen to be the same
3531 // registers used to pass 'inreg' arguments so watch out for those.
3532 if (!Subtarget->is64Bit() &&
3533 ((!isa<GlobalAddressSDNode>(Callee) &&
3534 !isa<ExternalSymbolSDNode>(Callee)) ||
3535 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3536 unsigned NumInRegs = 0;
3537 // In PIC we need an extra register to formulate the address computation
3539 unsigned MaxInRegs =
3540 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3542 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3543 CCValAssign &VA = ArgLocs[i];
3546 unsigned Reg = VA.getLocReg();
3549 case X86::EAX: case X86::EDX: case X86::ECX:
3550 if (++NumInRegs == MaxInRegs)
3562 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3563 const TargetLibraryInfo *libInfo) const {
3564 return X86::createFastISel(funcInfo, libInfo);
3567 //===----------------------------------------------------------------------===//
3568 // Other Lowering Hooks
3569 //===----------------------------------------------------------------------===//
3571 static bool MayFoldLoad(SDValue Op) {
3572 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3575 static bool MayFoldIntoStore(SDValue Op) {
3576 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3579 static bool isTargetShuffle(unsigned Opcode) {
3581 default: return false;
3582 case X86ISD::BLENDI:
3583 case X86ISD::PSHUFB:
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3588 case X86ISD::PALIGNR:
3589 case X86ISD::MOVLHPS:
3590 case X86ISD::MOVLHPD:
3591 case X86ISD::MOVHLPS:
3592 case X86ISD::MOVLPS:
3593 case X86ISD::MOVLPD:
3594 case X86ISD::MOVSHDUP:
3595 case X86ISD::MOVSLDUP:
3596 case X86ISD::MOVDDUP:
3599 case X86ISD::UNPCKL:
3600 case X86ISD::UNPCKH:
3601 case X86ISD::VPERMILPI:
3602 case X86ISD::VPERM2X128:
3603 case X86ISD::VPERMI:
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVSHDUP:
3613 case X86ISD::MOVSLDUP:
3614 case X86ISD::MOVDDUP:
3615 return DAG.getNode(Opc, dl, VT, V1);
3619 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3620 SDValue V1, unsigned TargetMask,
3621 SelectionDAG &DAG) {
3623 default: llvm_unreachable("Unknown x86 shuffle node");
3624 case X86ISD::PSHUFD:
3625 case X86ISD::PSHUFHW:
3626 case X86ISD::PSHUFLW:
3627 case X86ISD::VPERMILPI:
3628 case X86ISD::VPERMI:
3629 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3633 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3634 SDValue V1, SDValue V2, unsigned TargetMask,
3635 SelectionDAG &DAG) {
3637 default: llvm_unreachable("Unknown x86 shuffle node");
3638 case X86ISD::PALIGNR:
3639 case X86ISD::VALIGN:
3641 case X86ISD::VPERM2X128:
3642 return DAG.getNode(Opc, dl, VT, V1, V2,
3643 DAG.getConstant(TargetMask, MVT::i8));
3647 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3648 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3650 default: llvm_unreachable("Unknown x86 shuffle node");
3651 case X86ISD::MOVLHPS:
3652 case X86ISD::MOVLHPD:
3653 case X86ISD::MOVHLPS:
3654 case X86ISD::MOVLPS:
3655 case X86ISD::MOVLPD:
3658 case X86ISD::UNPCKL:
3659 case X86ISD::UNPCKH:
3660 return DAG.getNode(Opc, dl, VT, V1, V2);
3664 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3665 MachineFunction &MF = DAG.getMachineFunction();
3666 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3667 DAG.getSubtarget().getRegisterInfo());
3668 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3669 int ReturnAddrIndex = FuncInfo->getRAIndex();
3671 if (ReturnAddrIndex == 0) {
3672 // Set up a frame object for the return address.
3673 unsigned SlotSize = RegInfo->getSlotSize();
3674 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3677 FuncInfo->setRAIndex(ReturnAddrIndex);
3680 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3683 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3684 bool hasSymbolicDisplacement) {
3685 // Offset should fit into 32 bit immediate field.
3686 if (!isInt<32>(Offset))
3689 // If we don't have a symbolic displacement - we don't have any extra
3691 if (!hasSymbolicDisplacement)
3694 // FIXME: Some tweaks might be needed for medium code model.
3695 if (M != CodeModel::Small && M != CodeModel::Kernel)
3698 // For small code model we assume that latest object is 16MB before end of 31
3699 // bits boundary. We may also accept pretty large negative constants knowing
3700 // that all objects are in the positive half of address space.
3701 if (M == CodeModel::Small && Offset < 16*1024*1024)
3704 // For kernel code model we know that all object resist in the negative half
3705 // of 32bits address space. We may not accept negative offsets, since they may
3706 // be just off and we may accept pretty large positive ones.
3707 if (M == CodeModel::Kernel && Offset >= 0)
3713 /// isCalleePop - Determines whether the callee is required to pop its
3714 /// own arguments. Callee pop is necessary to support tail calls.
3715 bool X86::isCalleePop(CallingConv::ID CallingConv,
3716 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3717 switch (CallingConv) {
3720 case CallingConv::X86_StdCall:
3721 case CallingConv::X86_FastCall:
3722 case CallingConv::X86_ThisCall:
3724 case CallingConv::Fast:
3725 case CallingConv::GHC:
3726 case CallingConv::HiPE:
3733 /// \brief Return true if the condition is an unsigned comparison operation.
3734 static bool isX86CCUnsigned(unsigned X86CC) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case X86::COND_E: return true;
3738 case X86::COND_G: return false;
3739 case X86::COND_GE: return false;
3740 case X86::COND_L: return false;
3741 case X86::COND_LE: return false;
3742 case X86::COND_NE: return true;
3743 case X86::COND_B: return true;
3744 case X86::COND_A: return true;
3745 case X86::COND_BE: return true;
3746 case X86::COND_AE: return true;
3748 llvm_unreachable("covered switch fell through?!");
3751 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3752 /// specific condition code, returning the condition code and the LHS/RHS of the
3753 /// comparison to make.
3754 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3755 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3757 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3758 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3759 // X > -1 -> X == 0, jump !sign.
3760 RHS = DAG.getConstant(0, RHS.getValueType());
3761 return X86::COND_NS;
3763 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3764 // X < 0 -> X == 0, jump on sign.
3767 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3769 RHS = DAG.getConstant(0, RHS.getValueType());
3770 return X86::COND_LE;
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Invalid integer condition!");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETGT: return X86::COND_G;
3778 case ISD::SETGE: return X86::COND_GE;
3779 case ISD::SETLT: return X86::COND_L;
3780 case ISD::SETLE: return X86::COND_LE;
3781 case ISD::SETNE: return X86::COND_NE;
3782 case ISD::SETULT: return X86::COND_B;
3783 case ISD::SETUGT: return X86::COND_A;
3784 case ISD::SETULE: return X86::COND_BE;
3785 case ISD::SETUGE: return X86::COND_AE;
3789 // First determine if it is required or is profitable to flip the operands.
3791 // If LHS is a foldable load, but RHS is not, flip the condition.
3792 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3793 !ISD::isNON_EXTLoad(RHS.getNode())) {
3794 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3795 std::swap(LHS, RHS);
3798 switch (SetCCOpcode) {
3804 std::swap(LHS, RHS);
3808 // On a floating point condition, the flags are set as follows:
3810 // 0 | 0 | 0 | X > Y
3811 // 0 | 0 | 1 | X < Y
3812 // 1 | 0 | 0 | X == Y
3813 // 1 | 1 | 1 | unordered
3814 switch (SetCCOpcode) {
3815 default: llvm_unreachable("Condcode should be pre-legalized away");
3817 case ISD::SETEQ: return X86::COND_E;
3818 case ISD::SETOLT: // flipped
3820 case ISD::SETGT: return X86::COND_A;
3821 case ISD::SETOLE: // flipped
3823 case ISD::SETGE: return X86::COND_AE;
3824 case ISD::SETUGT: // flipped
3826 case ISD::SETLT: return X86::COND_B;
3827 case ISD::SETUGE: // flipped
3829 case ISD::SETLE: return X86::COND_BE;
3831 case ISD::SETNE: return X86::COND_NE;
3832 case ISD::SETUO: return X86::COND_P;
3833 case ISD::SETO: return X86::COND_NP;
3835 case ISD::SETUNE: return X86::COND_INVALID;
3839 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3840 /// code. Current x86 isa includes the following FP cmov instructions:
3841 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3842 static bool hasFPCMov(unsigned X86CC) {
3858 /// isFPImmLegal - Returns true if the target can instruction select the
3859 /// specified FP immediate natively. If false, the legalizer will
3860 /// materialize the FP immediate as a load from a constant pool.
3861 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3862 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3863 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3869 /// \brief Returns true if it is beneficial to convert a load of a constant
3870 /// to just the constant itself.
3871 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3873 assert(Ty->isIntegerTy());
3875 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3876 if (BitSize == 0 || BitSize > 64)
3881 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3882 unsigned Index) const {
3883 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3886 return (Index == 0 || Index == ResVT.getVectorNumElements());
3889 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3890 /// the specified range (L, H].
3891 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3892 return (Val < 0) || (Val >= Low && Val < Hi);
3895 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3896 /// specified value.
3897 static bool isUndefOrEqual(int Val, int CmpVal) {
3898 return (Val < 0 || Val == CmpVal);
3901 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3902 /// from position Pos and ending in Pos+Size, falls within the specified
3903 /// sequential range (L, L+Pos]. or is undef.
3904 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3905 unsigned Pos, unsigned Size, int Low) {
3906 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3907 if (!isUndefOrEqual(Mask[i], Low))
3912 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3913 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3914 /// operand - by default will match for first operand.
3915 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3916 bool TestSecondOperand = false) {
3917 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3918 VT != MVT::v2f64 && VT != MVT::v2i64)
3921 unsigned NumElems = VT.getVectorNumElements();
3922 unsigned Lo = TestSecondOperand ? NumElems : 0;
3923 unsigned Hi = Lo + NumElems;
3925 for (unsigned i = 0; i < NumElems; ++i)
3926 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3932 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3933 /// is suitable for input to PSHUFHW.
3934 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3935 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3938 // Lower quadword copied in order or undef.
3939 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3942 // Upper quadword shuffled.
3943 for (unsigned i = 4; i != 8; ++i)
3944 if (!isUndefOrInRange(Mask[i], 4, 8))
3947 if (VT == MVT::v16i16) {
3948 // Lower quadword copied in order or undef.
3949 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3952 // Upper quadword shuffled.
3953 for (unsigned i = 12; i != 16; ++i)
3954 if (!isUndefOrInRange(Mask[i], 12, 16))
3961 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3962 /// is suitable for input to PSHUFLW.
3963 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3964 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3967 // Upper quadword copied in order.
3968 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3971 // Lower quadword shuffled.
3972 for (unsigned i = 0; i != 4; ++i)
3973 if (!isUndefOrInRange(Mask[i], 0, 4))
3976 if (VT == MVT::v16i16) {
3977 // Upper quadword copied in order.
3978 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3981 // Lower quadword shuffled.
3982 for (unsigned i = 8; i != 12; ++i)
3983 if (!isUndefOrInRange(Mask[i], 8, 12))
3990 /// \brief Return true if the mask specifies a shuffle of elements that is
3991 /// suitable for input to intralane (palignr) or interlane (valign) vector
3993 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3994 unsigned NumElts = VT.getVectorNumElements();
3995 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3996 unsigned NumLaneElts = NumElts/NumLanes;
3998 // Do not handle 64-bit element shuffles with palignr.
3999 if (NumLaneElts == 2)
4002 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4004 for (i = 0; i != NumLaneElts; ++i) {
4009 // Lane is all undef, go to next lane
4010 if (i == NumLaneElts)
4013 int Start = Mask[i+l];
4015 // Make sure its in this lane in one of the sources
4016 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4017 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4020 // If not lane 0, then we must match lane 0
4021 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4024 // Correct second source to be contiguous with first source
4025 if (Start >= (int)NumElts)
4026 Start -= NumElts - NumLaneElts;
4028 // Make sure we're shifting in the right direction.
4029 if (Start <= (int)(i+l))
4034 // Check the rest of the elements to see if they are consecutive.
4035 for (++i; i != NumLaneElts; ++i) {
4036 int Idx = Mask[i+l];
4038 // Make sure its in this lane
4039 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4040 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4043 // If not lane 0, then we must match lane 0
4044 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4047 if (Idx >= (int)NumElts)
4048 Idx -= NumElts - NumLaneElts;
4050 if (!isUndefOrEqual(Idx, Start+i))
4059 /// \brief Return true if the node specifies a shuffle of elements that is
4060 /// suitable for input to PALIGNR.
4061 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4062 const X86Subtarget *Subtarget) {
4063 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4064 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4065 VT.is512BitVector())
4066 // FIXME: Add AVX512BW.
4069 return isAlignrMask(Mask, VT, false);
4072 /// \brief Return true if the node specifies a shuffle of elements that is
4073 /// suitable for input to VALIGN.
4074 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4075 const X86Subtarget *Subtarget) {
4076 // FIXME: Add AVX512VL.
4077 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4079 return isAlignrMask(Mask, VT, true);
4082 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4083 /// the two vector operands have swapped position.
4084 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4085 unsigned NumElems) {
4086 for (unsigned i = 0; i != NumElems; ++i) {
4090 else if (idx < (int)NumElems)
4091 Mask[i] = idx + NumElems;
4093 Mask[i] = idx - NumElems;
4097 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4098 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4099 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4100 /// reverse of what x86 shuffles want.
4101 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4103 unsigned NumElems = VT.getVectorNumElements();
4104 unsigned NumLanes = VT.getSizeInBits()/128;
4105 unsigned NumLaneElems = NumElems/NumLanes;
4107 if (NumLaneElems != 2 && NumLaneElems != 4)
4110 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4111 bool symetricMaskRequired =
4112 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4114 // VSHUFPSY divides the resulting vector into 4 chunks.
4115 // The sources are also splitted into 4 chunks, and each destination
4116 // chunk must come from a different source chunk.
4118 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4119 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4121 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4122 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4124 // VSHUFPDY divides the resulting vector into 4 chunks.
4125 // The sources are also splitted into 4 chunks, and each destination
4126 // chunk must come from a different source chunk.
4128 // SRC1 => X3 X2 X1 X0
4129 // SRC2 => Y3 Y2 Y1 Y0
4131 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4133 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4134 unsigned HalfLaneElems = NumLaneElems/2;
4135 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4136 for (unsigned i = 0; i != NumLaneElems; ++i) {
4137 int Idx = Mask[i+l];
4138 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4139 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4141 // For VSHUFPSY, the mask of the second half must be the same as the
4142 // first but with the appropriate offsets. This works in the same way as
4143 // VPERMILPS works with masks.
4144 if (!symetricMaskRequired || Idx < 0)
4146 if (MaskVal[i] < 0) {
4147 MaskVal[i] = Idx - l;
4150 if ((signed)(Idx - l) != MaskVal[i])
4158 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4160 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4169 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4170 return isUndefOrEqual(Mask[0], 6) &&
4171 isUndefOrEqual(Mask[1], 7) &&
4172 isUndefOrEqual(Mask[2], 2) &&
4173 isUndefOrEqual(Mask[3], 3);
4176 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4177 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4179 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4180 if (!VT.is128BitVector())
4183 unsigned NumElems = VT.getVectorNumElements();
4188 return isUndefOrEqual(Mask[0], 2) &&
4189 isUndefOrEqual(Mask[1], 3) &&
4190 isUndefOrEqual(Mask[2], 2) &&
4191 isUndefOrEqual(Mask[3], 3);
4194 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4195 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4196 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4197 if (!VT.is128BitVector())
4200 unsigned NumElems = VT.getVectorNumElements();
4202 if (NumElems != 2 && NumElems != 4)
4205 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4206 if (!isUndefOrEqual(Mask[i], i + NumElems))
4209 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4210 if (!isUndefOrEqual(Mask[i], i))
4216 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4217 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4218 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4219 if (!VT.is128BitVector())
4222 unsigned NumElems = VT.getVectorNumElements();
4224 if (NumElems != 2 && NumElems != 4)
4227 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4228 if (!isUndefOrEqual(Mask[i], i))
4231 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4232 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4238 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4239 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4240 /// i. e: If all but one element come from the same vector.
4241 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4242 // TODO: Deal with AVX's VINSERTPS
4243 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4246 unsigned CorrectPosV1 = 0;
4247 unsigned CorrectPosV2 = 0;
4248 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4249 if (Mask[i] == -1) {
4257 else if (Mask[i] == i + 4)
4261 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4262 // We have 3 elements (undefs count as elements from any vector) from one
4263 // vector, and one from another.
4270 // Some special combinations that can be optimized.
4273 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4274 SelectionDAG &DAG) {
4275 MVT VT = SVOp->getSimpleValueType(0);
4278 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4281 ArrayRef<int> Mask = SVOp->getMask();
4283 // These are the special masks that may be optimized.
4284 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4285 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4286 bool MatchEvenMask = true;
4287 bool MatchOddMask = true;
4288 for (int i=0; i<8; ++i) {
4289 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4290 MatchEvenMask = false;
4291 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4292 MatchOddMask = false;
4295 if (!MatchEvenMask && !MatchOddMask)
4298 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4300 SDValue Op0 = SVOp->getOperand(0);
4301 SDValue Op1 = SVOp->getOperand(1);
4303 if (MatchEvenMask) {
4304 // Shift the second operand right to 32 bits.
4305 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4306 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4308 // Shift the first operand left to 32 bits.
4309 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4310 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4312 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4313 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4316 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4317 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4318 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4319 bool HasInt256, bool V2IsSplat = false) {
4321 assert(VT.getSizeInBits() >= 128 &&
4322 "Unsupported vector type for unpckl");
4324 unsigned NumElts = VT.getVectorNumElements();
4325 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4326 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4329 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4330 "Unsupported vector type for unpckh");
4332 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4333 unsigned NumLanes = VT.getSizeInBits()/128;
4334 unsigned NumLaneElts = NumElts/NumLanes;
4336 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4337 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4338 int BitI = Mask[l+i];
4339 int BitI1 = Mask[l+i+1];
4340 if (!isUndefOrEqual(BitI, j))
4343 if (!isUndefOrEqual(BitI1, NumElts))
4346 if (!isUndefOrEqual(BitI1, j + NumElts))
4355 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4356 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4357 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4358 bool HasInt256, bool V2IsSplat = false) {
4359 assert(VT.getSizeInBits() >= 128 &&
4360 "Unsupported vector type for unpckh");
4362 unsigned NumElts = VT.getVectorNumElements();
4363 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4364 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4367 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4368 "Unsupported vector type for unpckh");
4370 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4371 unsigned NumLanes = VT.getSizeInBits()/128;
4372 unsigned NumLaneElts = NumElts/NumLanes;
4374 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4375 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4376 int BitI = Mask[l+i];
4377 int BitI1 = Mask[l+i+1];
4378 if (!isUndefOrEqual(BitI, j))
4381 if (isUndefOrEqual(BitI1, NumElts))
4384 if (!isUndefOrEqual(BitI1, j+NumElts))
4392 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4393 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4395 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4396 unsigned NumElts = VT.getVectorNumElements();
4397 bool Is256BitVec = VT.is256BitVector();
4399 if (VT.is512BitVector())
4401 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4402 "Unsupported vector type for unpckh");
4404 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4405 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4408 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4409 // FIXME: Need a better way to get rid of this, there's no latency difference
4410 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4411 // the former later. We should also remove the "_undef" special mask.
4412 if (NumElts == 4 && Is256BitVec)
4415 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4416 // independently on 128-bit lanes.
4417 unsigned NumLanes = VT.getSizeInBits()/128;
4418 unsigned NumLaneElts = NumElts/NumLanes;
4420 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4421 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4422 int BitI = Mask[l+i];
4423 int BitI1 = Mask[l+i+1];
4425 if (!isUndefOrEqual(BitI, j))
4427 if (!isUndefOrEqual(BitI1, j))
4435 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4436 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4438 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4439 unsigned NumElts = VT.getVectorNumElements();
4441 if (VT.is512BitVector())
4444 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4445 "Unsupported vector type for unpckh");
4447 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4448 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4451 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4452 // independently on 128-bit lanes.
4453 unsigned NumLanes = VT.getSizeInBits()/128;
4454 unsigned NumLaneElts = NumElts/NumLanes;
4456 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4457 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4458 int BitI = Mask[l+i];
4459 int BitI1 = Mask[l+i+1];
4460 if (!isUndefOrEqual(BitI, j))
4462 if (!isUndefOrEqual(BitI1, j))
4469 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4470 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4471 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4472 if (!VT.is512BitVector())
4475 unsigned NumElts = VT.getVectorNumElements();
4476 unsigned HalfSize = NumElts/2;
4477 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4478 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4483 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4484 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4492 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4493 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4494 /// MOVSD, and MOVD, i.e. setting the lowest element.
4495 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4496 if (VT.getVectorElementType().getSizeInBits() < 32)
4498 if (!VT.is128BitVector())
4501 unsigned NumElts = VT.getVectorNumElements();
4503 if (!isUndefOrEqual(Mask[0], NumElts))
4506 for (unsigned i = 1; i != NumElts; ++i)
4507 if (!isUndefOrEqual(Mask[i], i))
4513 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4514 /// as permutations between 128-bit chunks or halves. As an example: this
4516 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4517 /// The first half comes from the second half of V1 and the second half from the
4518 /// the second half of V2.
4519 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4520 if (!HasFp256 || !VT.is256BitVector())
4523 // The shuffle result is divided into half A and half B. In total the two
4524 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4525 // B must come from C, D, E or F.
4526 unsigned HalfSize = VT.getVectorNumElements()/2;
4527 bool MatchA = false, MatchB = false;
4529 // Check if A comes from one of C, D, E, F.
4530 for (unsigned Half = 0; Half != 4; ++Half) {
4531 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4537 // Check if B comes from one of C, D, E, F.
4538 for (unsigned Half = 0; Half != 4; ++Half) {
4539 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4545 return MatchA && MatchB;
4548 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4549 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4550 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4551 MVT VT = SVOp->getSimpleValueType(0);
4553 unsigned HalfSize = VT.getVectorNumElements()/2;
4555 unsigned FstHalf = 0, SndHalf = 0;
4556 for (unsigned i = 0; i < HalfSize; ++i) {
4557 if (SVOp->getMaskElt(i) > 0) {
4558 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4562 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4563 if (SVOp->getMaskElt(i) > 0) {
4564 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4569 return (FstHalf | (SndHalf << 4));
4572 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4573 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4574 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4578 unsigned NumElts = VT.getVectorNumElements();
4580 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4581 for (unsigned i = 0; i != NumElts; ++i) {
4584 Imm8 |= Mask[i] << (i*2);
4589 unsigned LaneSize = 4;
4590 SmallVector<int, 4> MaskVal(LaneSize, -1);
4592 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4593 for (unsigned i = 0; i != LaneSize; ++i) {
4594 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4598 if (MaskVal[i] < 0) {
4599 MaskVal[i] = Mask[i+l] - l;
4600 Imm8 |= MaskVal[i] << (i*2);
4603 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4610 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4611 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4612 /// Note that VPERMIL mask matching is different depending whether theunderlying
4613 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4614 /// to the same elements of the low, but to the higher half of the source.
4615 /// In VPERMILPD the two lanes could be shuffled independently of each other
4616 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4617 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4618 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4619 if (VT.getSizeInBits() < 256 || EltSize < 32)
4621 bool symetricMaskRequired = (EltSize == 32);
4622 unsigned NumElts = VT.getVectorNumElements();
4624 unsigned NumLanes = VT.getSizeInBits()/128;
4625 unsigned LaneSize = NumElts/NumLanes;
4626 // 2 or 4 elements in one lane
4628 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4629 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4630 for (unsigned i = 0; i != LaneSize; ++i) {
4631 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4633 if (symetricMaskRequired) {
4634 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4635 ExpectedMaskVal[i] = Mask[i+l] - l;
4638 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4646 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4647 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4648 /// element of vector 2 and the other elements to come from vector 1 in order.
4649 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4650 bool V2IsSplat = false, bool V2IsUndef = false) {
4651 if (!VT.is128BitVector())
4654 unsigned NumOps = VT.getVectorNumElements();
4655 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4658 if (!isUndefOrEqual(Mask[0], 0))
4661 for (unsigned i = 1; i != NumOps; ++i)
4662 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4663 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4664 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4670 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4671 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4672 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4673 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4674 const X86Subtarget *Subtarget) {
4675 if (!Subtarget->hasSSE3())
4678 unsigned NumElems = VT.getVectorNumElements();
4680 if ((VT.is128BitVector() && NumElems != 4) ||
4681 (VT.is256BitVector() && NumElems != 8) ||
4682 (VT.is512BitVector() && NumElems != 16))
4685 // "i+1" is the value the indexed mask element must have
4686 for (unsigned i = 0; i != NumElems; i += 2)
4687 if (!isUndefOrEqual(Mask[i], i+1) ||
4688 !isUndefOrEqual(Mask[i+1], i+1))
4694 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4695 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4696 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4697 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4698 const X86Subtarget *Subtarget) {
4699 if (!Subtarget->hasSSE3())
4702 unsigned NumElems = VT.getVectorNumElements();
4704 if ((VT.is128BitVector() && NumElems != 4) ||
4705 (VT.is256BitVector() && NumElems != 8) ||
4706 (VT.is512BitVector() && NumElems != 16))
4709 // "i" is the value the indexed mask element must have
4710 for (unsigned i = 0; i != NumElems; i += 2)
4711 if (!isUndefOrEqual(Mask[i], i) ||
4712 !isUndefOrEqual(Mask[i+1], i))
4718 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4719 /// specifies a shuffle of elements that is suitable for input to 256-bit
4720 /// version of MOVDDUP.
4721 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4722 if (!HasFp256 || !VT.is256BitVector())
4725 unsigned NumElts = VT.getVectorNumElements();
4729 for (unsigned i = 0; i != NumElts/2; ++i)
4730 if (!isUndefOrEqual(Mask[i], 0))
4732 for (unsigned i = NumElts/2; i != NumElts; ++i)
4733 if (!isUndefOrEqual(Mask[i], NumElts/2))
4738 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4739 /// specifies a shuffle of elements that is suitable for input to 128-bit
4740 /// version of MOVDDUP.
4741 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4742 if (!VT.is128BitVector())
4745 unsigned e = VT.getVectorNumElements() / 2;
4746 for (unsigned i = 0; i != e; ++i)
4747 if (!isUndefOrEqual(Mask[i], i))
4749 for (unsigned i = 0; i != e; ++i)
4750 if (!isUndefOrEqual(Mask[e+i], i))
4755 /// isVEXTRACTIndex - Return true if the specified
4756 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4757 /// suitable for instruction that extract 128 or 256 bit vectors
4758 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4759 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4760 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4763 // The index should be aligned on a vecWidth-bit boundary.
4765 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4767 MVT VT = N->getSimpleValueType(0);
4768 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4769 bool Result = (Index * ElSize) % vecWidth == 0;
4774 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4775 /// operand specifies a subvector insert that is suitable for input to
4776 /// insertion of 128 or 256-bit subvectors
4777 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4778 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4779 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4781 // The index should be aligned on a vecWidth-bit boundary.
4783 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4785 MVT VT = N->getSimpleValueType(0);
4786 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4787 bool Result = (Index * ElSize) % vecWidth == 0;
4792 bool X86::isVINSERT128Index(SDNode *N) {
4793 return isVINSERTIndex(N, 128);
4796 bool X86::isVINSERT256Index(SDNode *N) {
4797 return isVINSERTIndex(N, 256);
4800 bool X86::isVEXTRACT128Index(SDNode *N) {
4801 return isVEXTRACTIndex(N, 128);
4804 bool X86::isVEXTRACT256Index(SDNode *N) {
4805 return isVEXTRACTIndex(N, 256);
4808 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4809 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4810 /// Handles 128-bit and 256-bit.
4811 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4812 MVT VT = N->getSimpleValueType(0);
4814 assert((VT.getSizeInBits() >= 128) &&
4815 "Unsupported vector type for PSHUF/SHUFP");
4817 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4818 // independently on 128-bit lanes.
4819 unsigned NumElts = VT.getVectorNumElements();
4820 unsigned NumLanes = VT.getSizeInBits()/128;
4821 unsigned NumLaneElts = NumElts/NumLanes;
4823 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4824 "Only supports 2, 4 or 8 elements per lane");
4826 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4828 for (unsigned i = 0; i != NumElts; ++i) {
4829 int Elt = N->getMaskElt(i);
4830 if (Elt < 0) continue;
4831 Elt &= NumLaneElts - 1;
4832 unsigned ShAmt = (i << Shift) % 8;
4833 Mask |= Elt << ShAmt;
4839 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4840 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4841 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4842 MVT VT = N->getSimpleValueType(0);
4844 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4845 "Unsupported vector type for PSHUFHW");
4847 unsigned NumElts = VT.getVectorNumElements();
4850 for (unsigned l = 0; l != NumElts; l += 8) {
4851 // 8 nodes per lane, but we only care about the last 4.
4852 for (unsigned i = 0; i < 4; ++i) {
4853 int Elt = N->getMaskElt(l+i+4);
4854 if (Elt < 0) continue;
4855 Elt &= 0x3; // only 2-bits.
4856 Mask |= Elt << (i * 2);
4863 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4864 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4865 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4866 MVT VT = N->getSimpleValueType(0);
4868 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4869 "Unsupported vector type for PSHUFHW");
4871 unsigned NumElts = VT.getVectorNumElements();
4874 for (unsigned l = 0; l != NumElts; l += 8) {
4875 // 8 nodes per lane, but we only care about the first 4.
4876 for (unsigned i = 0; i < 4; ++i) {
4877 int Elt = N->getMaskElt(l+i);
4878 if (Elt < 0) continue;
4879 Elt &= 0x3; // only 2-bits
4880 Mask |= Elt << (i * 2);
4887 /// \brief Return the appropriate immediate to shuffle the specified
4888 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4889 /// VALIGN (if Interlane is true) instructions.
4890 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4892 MVT VT = SVOp->getSimpleValueType(0);
4893 unsigned EltSize = InterLane ? 1 :
4894 VT.getVectorElementType().getSizeInBits() >> 3;
4896 unsigned NumElts = VT.getVectorNumElements();
4897 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4898 unsigned NumLaneElts = NumElts/NumLanes;
4902 for (i = 0; i != NumElts; ++i) {
4903 Val = SVOp->getMaskElt(i);
4907 if (Val >= (int)NumElts)
4908 Val -= NumElts - NumLaneElts;
4910 assert(Val - i > 0 && "PALIGNR imm should be positive");
4911 return (Val - i) * EltSize;
4914 /// \brief Return the appropriate immediate to shuffle the specified
4915 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4916 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4917 return getShuffleAlignrImmediate(SVOp, false);
4920 /// \brief Return the appropriate immediate to shuffle the specified
4921 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4922 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4923 return getShuffleAlignrImmediate(SVOp, true);
4927 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4928 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4929 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4930 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4933 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4935 MVT VecVT = N->getOperand(0).getSimpleValueType();
4936 MVT ElVT = VecVT.getVectorElementType();
4938 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4939 return Index / NumElemsPerChunk;
4942 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4943 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4944 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4945 llvm_unreachable("Illegal insert subvector for VINSERT");
4948 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4950 MVT VecVT = N->getSimpleValueType(0);
4951 MVT ElVT = VecVT.getVectorElementType();
4953 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4954 return Index / NumElemsPerChunk;
4957 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4958 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4959 /// and VINSERTI128 instructions.
4960 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4961 return getExtractVEXTRACTImmediate(N, 128);
4964 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4965 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4966 /// and VINSERTI64x4 instructions.
4967 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4968 return getExtractVEXTRACTImmediate(N, 256);
4971 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4972 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4973 /// and VINSERTI128 instructions.
4974 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4975 return getInsertVINSERTImmediate(N, 128);
4978 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4979 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4980 /// and VINSERTI64x4 instructions.
4981 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4982 return getInsertVINSERTImmediate(N, 256);
4985 /// isZero - Returns true if Elt is a constant integer zero
4986 static bool isZero(SDValue V) {
4987 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4988 return C && C->isNullValue();
4991 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4993 bool X86::isZeroNode(SDValue Elt) {
4996 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4997 return CFP->getValueAPF().isPosZero();
5001 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5002 /// match movhlps. The lower half elements should come from upper half of
5003 /// V1 (and in order), and the upper half elements should come from the upper
5004 /// half of V2 (and in order).
5005 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5008 if (VT.getVectorNumElements() != 4)
5010 for (unsigned i = 0, e = 2; i != e; ++i)
5011 if (!isUndefOrEqual(Mask[i], i+2))
5013 for (unsigned i = 2; i != 4; ++i)
5014 if (!isUndefOrEqual(Mask[i], i+4))
5019 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5020 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5022 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5023 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5025 N = N->getOperand(0).getNode();
5026 if (!ISD::isNON_EXTLoad(N))
5029 *LD = cast<LoadSDNode>(N);
5033 // Test whether the given value is a vector value which will be legalized
5035 static bool WillBeConstantPoolLoad(SDNode *N) {
5036 if (N->getOpcode() != ISD::BUILD_VECTOR)
5039 // Check for any non-constant elements.
5040 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5041 switch (N->getOperand(i).getNode()->getOpcode()) {
5043 case ISD::ConstantFP:
5050 // Vectors of all-zeros and all-ones are materialized with special
5051 // instructions rather than being loaded.
5052 return !ISD::isBuildVectorAllZeros(N) &&
5053 !ISD::isBuildVectorAllOnes(N);
5056 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5057 /// match movlp{s|d}. The lower half elements should come from lower half of
5058 /// V1 (and in order), and the upper half elements should come from the upper
5059 /// half of V2 (and in order). And since V1 will become the source of the
5060 /// MOVLP, it must be either a vector load or a scalar load to vector.
5061 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5062 ArrayRef<int> Mask, MVT VT) {
5063 if (!VT.is128BitVector())
5066 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5068 // Is V2 is a vector load, don't do this transformation. We will try to use
5069 // load folding shufps op.
5070 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5073 unsigned NumElems = VT.getVectorNumElements();
5075 if (NumElems != 2 && NumElems != 4)
5077 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5078 if (!isUndefOrEqual(Mask[i], i))
5080 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5081 if (!isUndefOrEqual(Mask[i], i+NumElems))
5086 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5087 /// to an zero vector.
5088 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5089 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5090 SDValue V1 = N->getOperand(0);
5091 SDValue V2 = N->getOperand(1);
5092 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5093 for (unsigned i = 0; i != NumElems; ++i) {
5094 int Idx = N->getMaskElt(i);
5095 if (Idx >= (int)NumElems) {
5096 unsigned Opc = V2.getOpcode();
5097 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5099 if (Opc != ISD::BUILD_VECTOR ||
5100 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5102 } else if (Idx >= 0) {
5103 unsigned Opc = V1.getOpcode();
5104 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5106 if (Opc != ISD::BUILD_VECTOR ||
5107 !X86::isZeroNode(V1.getOperand(Idx)))
5114 /// getZeroVector - Returns a vector of specified type with all zero elements.
5116 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5117 SelectionDAG &DAG, SDLoc dl) {
5118 assert(VT.isVector() && "Expected a vector type");
5120 // Always build SSE zero vectors as <4 x i32> bitcasted
5121 // to their dest type. This ensures they get CSE'd.
5123 if (VT.is128BitVector()) { // SSE
5124 if (Subtarget->hasSSE2()) { // SSE2
5125 SDValue Cst = DAG.getConstant(0, MVT::i32);
5126 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5128 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5129 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5131 } else if (VT.is256BitVector()) { // AVX
5132 if (Subtarget->hasInt256()) { // AVX2
5133 SDValue Cst = DAG.getConstant(0, MVT::i32);
5134 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5137 // 256-bit logic and arithmetic instructions in AVX are all
5138 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5139 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5140 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5141 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5143 } else if (VT.is512BitVector()) { // AVX-512
5144 SDValue Cst = DAG.getConstant(0, MVT::i32);
5145 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5146 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5147 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5148 } else if (VT.getScalarType() == MVT::i1) {
5149 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5150 SDValue Cst = DAG.getConstant(0, MVT::i1);
5151 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5152 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5154 llvm_unreachable("Unexpected vector type");
5156 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5159 /// getOnesVector - Returns a vector of specified type with all bits set.
5160 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5161 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5162 /// Then bitcast to their original type, ensuring they get CSE'd.
5163 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5165 assert(VT.isVector() && "Expected a vector type");
5167 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5169 if (VT.is256BitVector()) {
5170 if (HasInt256) { // AVX2
5171 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5172 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5175 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5177 } else if (VT.is128BitVector()) {
5178 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5180 llvm_unreachable("Unexpected vector type");
5182 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5185 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5186 /// that point to V2 points to its first element.
5187 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5188 for (unsigned i = 0; i != NumElems; ++i) {
5189 if (Mask[i] > (int)NumElems) {
5195 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5196 /// operation of specified width.
5197 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5199 unsigned NumElems = VT.getVectorNumElements();
5200 SmallVector<int, 8> Mask;
5201 Mask.push_back(NumElems);
5202 for (unsigned i = 1; i != NumElems; ++i)
5204 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5207 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5208 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5210 unsigned NumElems = VT.getVectorNumElements();
5211 SmallVector<int, 8> Mask;
5212 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5214 Mask.push_back(i + NumElems);
5216 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5219 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5220 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5222 unsigned NumElems = VT.getVectorNumElements();
5223 SmallVector<int, 8> Mask;
5224 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5225 Mask.push_back(i + Half);
5226 Mask.push_back(i + NumElems + Half);
5228 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5231 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5232 // a generic shuffle instruction because the target has no such instructions.
5233 // Generate shuffles which repeat i16 and i8 several times until they can be
5234 // represented by v4f32 and then be manipulated by target suported shuffles.
5235 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5236 MVT VT = V.getSimpleValueType();
5237 int NumElems = VT.getVectorNumElements();
5240 while (NumElems > 4) {
5241 if (EltNo < NumElems/2) {
5242 V = getUnpackl(DAG, dl, VT, V, V);
5244 V = getUnpackh(DAG, dl, VT, V, V);
5245 EltNo -= NumElems/2;
5252 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5253 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5254 MVT VT = V.getSimpleValueType();
5257 if (VT.is128BitVector()) {
5258 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5259 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5260 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5262 } else if (VT.is256BitVector()) {
5263 // To use VPERMILPS to splat scalars, the second half of indicies must
5264 // refer to the higher part, which is a duplication of the lower one,
5265 // because VPERMILPS can only handle in-lane permutations.
5266 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5267 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5269 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5270 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5273 llvm_unreachable("Vector size not supported");
5275 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5278 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5279 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5280 MVT SrcVT = SV->getSimpleValueType(0);
5281 SDValue V1 = SV->getOperand(0);
5284 int EltNo = SV->getSplatIndex();
5285 int NumElems = SrcVT.getVectorNumElements();
5286 bool Is256BitVec = SrcVT.is256BitVector();
5288 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5289 "Unknown how to promote splat for type");
5291 // Extract the 128-bit part containing the splat element and update
5292 // the splat element index when it refers to the higher register.
5294 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5295 if (EltNo >= NumElems/2)
5296 EltNo -= NumElems/2;
5299 // All i16 and i8 vector types can't be used directly by a generic shuffle
5300 // instruction because the target has no such instruction. Generate shuffles
5301 // which repeat i16 and i8 several times until they fit in i32, and then can
5302 // be manipulated by target suported shuffles.
5303 MVT EltVT = SrcVT.getVectorElementType();
5304 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5305 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5307 // Recreate the 256-bit vector and place the same 128-bit vector
5308 // into the low and high part. This is necessary because we want
5309 // to use VPERM* to shuffle the vectors
5311 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5314 return getLegalSplat(DAG, V1, EltNo);
5317 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5318 /// vector of zero or undef vector. This produces a shuffle where the low
5319 /// element of V2 is swizzled into the zero/undef vector, landing at element
5320 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5321 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5323 const X86Subtarget *Subtarget,
5324 SelectionDAG &DAG) {
5325 MVT VT = V2.getSimpleValueType();
5327 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5328 unsigned NumElems = VT.getVectorNumElements();
5329 SmallVector<int, 16> MaskVec;
5330 for (unsigned i = 0; i != NumElems; ++i)
5331 // If this is the insertion idx, put the low elt of V2 here.
5332 MaskVec.push_back(i == Idx ? NumElems : i);
5333 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5336 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5337 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5338 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5339 /// shuffles which use a single input multiple times, and in those cases it will
5340 /// adjust the mask to only have indices within that single input.
5341 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5342 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5343 unsigned NumElems = VT.getVectorNumElements();
5347 bool IsFakeUnary = false;
5348 switch(N->getOpcode()) {
5349 case X86ISD::BLENDI:
5350 ImmN = N->getOperand(N->getNumOperands()-1);
5351 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5354 ImmN = N->getOperand(N->getNumOperands()-1);
5355 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5356 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5358 case X86ISD::UNPCKH:
5359 DecodeUNPCKHMask(VT, Mask);
5360 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5362 case X86ISD::UNPCKL:
5363 DecodeUNPCKLMask(VT, Mask);
5364 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5366 case X86ISD::MOVHLPS:
5367 DecodeMOVHLPSMask(NumElems, Mask);
5368 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5370 case X86ISD::MOVLHPS:
5371 DecodeMOVLHPSMask(NumElems, Mask);
5372 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5374 case X86ISD::PALIGNR:
5375 ImmN = N->getOperand(N->getNumOperands()-1);
5376 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5378 case X86ISD::PSHUFD:
5379 case X86ISD::VPERMILPI:
5380 ImmN = N->getOperand(N->getNumOperands()-1);
5381 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5384 case X86ISD::PSHUFHW:
5385 ImmN = N->getOperand(N->getNumOperands()-1);
5386 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5389 case X86ISD::PSHUFLW:
5390 ImmN = N->getOperand(N->getNumOperands()-1);
5391 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5394 case X86ISD::PSHUFB: {
5396 SDValue MaskNode = N->getOperand(1);
5397 while (MaskNode->getOpcode() == ISD::BITCAST)
5398 MaskNode = MaskNode->getOperand(0);
5400 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5401 // If we have a build-vector, then things are easy.
5402 EVT VT = MaskNode.getValueType();
5403 assert(VT.isVector() &&
5404 "Can't produce a non-vector with a build_vector!");
5405 if (!VT.isInteger())
5408 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5410 SmallVector<uint64_t, 32> RawMask;
5411 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5412 SDValue Op = MaskNode->getOperand(i);
5413 if (Op->getOpcode() == ISD::UNDEF) {
5414 RawMask.push_back((uint64_t)SM_SentinelUndef);
5417 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5420 APInt MaskElement = CN->getAPIntValue();
5422 // We now have to decode the element which could be any integer size and
5423 // extract each byte of it.
5424 for (int j = 0; j < NumBytesPerElement; ++j) {
5425 // Note that this is x86 and so always little endian: the low byte is
5426 // the first byte of the mask.
5427 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5428 MaskElement = MaskElement.lshr(8);
5431 DecodePSHUFBMask(RawMask, Mask);
5435 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5439 SDValue Ptr = MaskLoad->getBasePtr();
5440 if (Ptr->getOpcode() == X86ISD::Wrapper)
5441 Ptr = Ptr->getOperand(0);
5443 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5444 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5447 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5448 // FIXME: Support AVX-512 here.
5449 Type *Ty = C->getType();
5450 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5451 Ty->getVectorNumElements() != 32))
5454 DecodePSHUFBMask(C, Mask);
5460 case X86ISD::VPERMI:
5461 ImmN = N->getOperand(N->getNumOperands()-1);
5462 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5466 case X86ISD::MOVSD: {
5467 // The index 0 always comes from the first element of the second source,
5468 // this is why MOVSS and MOVSD are used in the first place. The other
5469 // elements come from the other positions of the first source vector
5470 Mask.push_back(NumElems);
5471 for (unsigned i = 1; i != NumElems; ++i) {
5476 case X86ISD::VPERM2X128:
5477 ImmN = N->getOperand(N->getNumOperands()-1);
5478 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5479 if (Mask.empty()) return false;
5481 case X86ISD::MOVSLDUP:
5482 DecodeMOVSLDUPMask(VT, Mask);
5484 case X86ISD::MOVSHDUP:
5485 DecodeMOVSHDUPMask(VT, Mask);
5487 case X86ISD::MOVDDUP:
5488 case X86ISD::MOVLHPD:
5489 case X86ISD::MOVLPD:
5490 case X86ISD::MOVLPS:
5491 // Not yet implemented
5493 default: llvm_unreachable("unknown target shuffle node");
5496 // If we have a fake unary shuffle, the shuffle mask is spread across two
5497 // inputs that are actually the same node. Re-map the mask to always point
5498 // into the first input.
5501 if (M >= (int)Mask.size())
5507 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5508 /// element of the result of the vector shuffle.
5509 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5512 return SDValue(); // Limit search depth.
5514 SDValue V = SDValue(N, 0);
5515 EVT VT = V.getValueType();
5516 unsigned Opcode = V.getOpcode();
5518 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5519 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5520 int Elt = SV->getMaskElt(Index);
5523 return DAG.getUNDEF(VT.getVectorElementType());
5525 unsigned NumElems = VT.getVectorNumElements();
5526 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5527 : SV->getOperand(1);
5528 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5531 // Recurse into target specific vector shuffles to find scalars.
5532 if (isTargetShuffle(Opcode)) {
5533 MVT ShufVT = V.getSimpleValueType();
5534 unsigned NumElems = ShufVT.getVectorNumElements();
5535 SmallVector<int, 16> ShuffleMask;
5538 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5541 int Elt = ShuffleMask[Index];
5543 return DAG.getUNDEF(ShufVT.getVectorElementType());
5545 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5547 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5551 // Actual nodes that may contain scalar elements
5552 if (Opcode == ISD::BITCAST) {
5553 V = V.getOperand(0);
5554 EVT SrcVT = V.getValueType();
5555 unsigned NumElems = VT.getVectorNumElements();
5557 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5561 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5562 return (Index == 0) ? V.getOperand(0)
5563 : DAG.getUNDEF(VT.getVectorElementType());
5565 if (V.getOpcode() == ISD::BUILD_VECTOR)
5566 return V.getOperand(Index);
5571 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5572 /// shuffle operation which come from a consecutively from a zero. The
5573 /// search can start in two different directions, from left or right.
5574 /// We count undefs as zeros until PreferredNum is reached.
5575 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5576 unsigned NumElems, bool ZerosFromLeft,
5578 unsigned PreferredNum = -1U) {
5579 unsigned NumZeros = 0;
5580 for (unsigned i = 0; i != NumElems; ++i) {
5581 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5582 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5586 if (X86::isZeroNode(Elt))
5588 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5589 NumZeros = std::min(NumZeros + 1, PreferredNum);
5597 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5598 /// correspond consecutively to elements from one of the vector operands,
5599 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5601 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5602 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5603 unsigned NumElems, unsigned &OpNum) {
5604 bool SeenV1 = false;
5605 bool SeenV2 = false;
5607 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5608 int Idx = SVOp->getMaskElt(i);
5609 // Ignore undef indicies
5613 if (Idx < (int)NumElems)
5618 // Only accept consecutive elements from the same vector
5619 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5623 OpNum = SeenV1 ? 0 : 1;
5627 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5628 /// logical left shift of a vector.
5629 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5630 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5632 SVOp->getSimpleValueType(0).getVectorNumElements();
5633 unsigned NumZeros = getNumOfConsecutiveZeros(
5634 SVOp, NumElems, false /* check zeros from right */, DAG,
5635 SVOp->getMaskElt(0));
5641 // Considering the elements in the mask that are not consecutive zeros,
5642 // check if they consecutively come from only one of the source vectors.
5644 // V1 = {X, A, B, C} 0
5646 // vector_shuffle V1, V2 <1, 2, 3, X>
5648 if (!isShuffleMaskConsecutive(SVOp,
5649 0, // Mask Start Index
5650 NumElems-NumZeros, // Mask End Index(exclusive)
5651 NumZeros, // Where to start looking in the src vector
5652 NumElems, // Number of elements in vector
5653 OpSrc)) // Which source operand ?
5658 ShVal = SVOp->getOperand(OpSrc);
5662 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5663 /// logical left shift of a vector.
5664 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5665 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5667 SVOp->getSimpleValueType(0).getVectorNumElements();
5668 unsigned NumZeros = getNumOfConsecutiveZeros(
5669 SVOp, NumElems, true /* check zeros from left */, DAG,
5670 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5676 // Considering the elements in the mask that are not consecutive zeros,
5677 // check if they consecutively come from only one of the source vectors.
5679 // 0 { A, B, X, X } = V2
5681 // vector_shuffle V1, V2 <X, X, 4, 5>
5683 if (!isShuffleMaskConsecutive(SVOp,
5684 NumZeros, // Mask Start Index
5685 NumElems, // Mask End Index(exclusive)
5686 0, // Where to start looking in the src vector
5687 NumElems, // Number of elements in vector
5688 OpSrc)) // Which source operand ?
5693 ShVal = SVOp->getOperand(OpSrc);
5697 /// isVectorShift - Returns true if the shuffle can be implemented as a
5698 /// logical left or right shift of a vector.
5699 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5700 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5701 // Although the logic below support any bitwidth size, there are no
5702 // shift instructions which handle more than 128-bit vectors.
5703 if (!SVOp->getSimpleValueType(0).is128BitVector())
5706 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5707 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5713 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5715 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5716 unsigned NumNonZero, unsigned NumZero,
5718 const X86Subtarget* Subtarget,
5719 const TargetLowering &TLI) {
5726 for (unsigned i = 0; i < 16; ++i) {
5727 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5728 if (ThisIsNonZero && First) {
5730 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5732 V = DAG.getUNDEF(MVT::v8i16);
5737 SDValue ThisElt, LastElt;
5738 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5739 if (LastIsNonZero) {
5740 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5741 MVT::i16, Op.getOperand(i-1));
5743 if (ThisIsNonZero) {
5744 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5745 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5746 ThisElt, DAG.getConstant(8, MVT::i8));
5748 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5752 if (ThisElt.getNode())
5753 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5754 DAG.getIntPtrConstant(i/2));
5758 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5761 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5763 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5764 unsigned NumNonZero, unsigned NumZero,
5766 const X86Subtarget* Subtarget,
5767 const TargetLowering &TLI) {
5774 for (unsigned i = 0; i < 8; ++i) {
5775 bool isNonZero = (NonZeros & (1 << i)) != 0;
5779 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5781 V = DAG.getUNDEF(MVT::v8i16);
5784 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5785 MVT::v8i16, V, Op.getOperand(i),
5786 DAG.getIntPtrConstant(i));
5793 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5794 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5795 const X86Subtarget *Subtarget,
5796 const TargetLowering &TLI) {
5797 // Find all zeroable elements.
5799 for (int i=0; i < 4; ++i) {
5800 SDValue Elt = Op->getOperand(i);
5801 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5803 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5804 [](bool M) { return !M; }) > 1 &&
5805 "We expect at least two non-zero elements!");
5807 // We only know how to deal with build_vector nodes where elements are either
5808 // zeroable or extract_vector_elt with constant index.
5809 SDValue FirstNonZero;
5810 unsigned FirstNonZeroIdx;
5811 for (unsigned i=0; i < 4; ++i) {
5814 SDValue Elt = Op->getOperand(i);
5815 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5816 !isa<ConstantSDNode>(Elt.getOperand(1)))
5818 // Make sure that this node is extracting from a 128-bit vector.
5819 MVT VT = Elt.getOperand(0).getSimpleValueType();
5820 if (!VT.is128BitVector())
5822 if (!FirstNonZero.getNode()) {
5824 FirstNonZeroIdx = i;
5828 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5829 SDValue V1 = FirstNonZero.getOperand(0);
5830 MVT VT = V1.getSimpleValueType();
5832 // See if this build_vector can be lowered as a blend with zero.
5834 unsigned EltMaskIdx, EltIdx;
5836 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5837 if (Zeroable[EltIdx]) {
5838 // The zero vector will be on the right hand side.
5839 Mask[EltIdx] = EltIdx+4;
5843 Elt = Op->getOperand(EltIdx);
5844 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5845 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5846 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5848 Mask[EltIdx] = EltIdx;
5852 // Let the shuffle legalizer deal with blend operations.
5853 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5854 if (V1.getSimpleValueType() != VT)
5855 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5856 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5859 // See if we can lower this build_vector to a INSERTPS.
5860 if (!Subtarget->hasSSE41())
5863 SDValue V2 = Elt.getOperand(0);
5864 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5867 bool CanFold = true;
5868 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5872 SDValue Current = Op->getOperand(i);
5873 SDValue SrcVector = Current->getOperand(0);
5876 CanFold = SrcVector == V1 &&
5877 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5883 assert(V1.getNode() && "Expected at least two non-zero elements!");
5884 if (V1.getSimpleValueType() != MVT::v4f32)
5885 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5886 if (V2.getSimpleValueType() != MVT::v4f32)
5887 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5889 // Ok, we can emit an INSERTPS instruction.
5891 for (int i = 0; i < 4; ++i)
5895 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5896 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5897 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5898 DAG.getIntPtrConstant(InsertPSMask));
5899 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5902 /// getVShift - Return a vector logical shift node.
5904 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5905 unsigned NumBits, SelectionDAG &DAG,
5906 const TargetLowering &TLI, SDLoc dl) {
5907 assert(VT.is128BitVector() && "Unknown type for VShift");
5908 EVT ShVT = MVT::v2i64;
5909 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5910 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5911 return DAG.getNode(ISD::BITCAST, dl, VT,
5912 DAG.getNode(Opc, dl, ShVT, SrcOp,
5913 DAG.getConstant(NumBits,
5914 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5918 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5920 // Check if the scalar load can be widened into a vector load. And if
5921 // the address is "base + cst" see if the cst can be "absorbed" into
5922 // the shuffle mask.
5923 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5924 SDValue Ptr = LD->getBasePtr();
5925 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5927 EVT PVT = LD->getValueType(0);
5928 if (PVT != MVT::i32 && PVT != MVT::f32)
5933 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5934 FI = FINode->getIndex();
5936 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5937 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5938 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5939 Offset = Ptr.getConstantOperandVal(1);
5940 Ptr = Ptr.getOperand(0);
5945 // FIXME: 256-bit vector instructions don't require a strict alignment,
5946 // improve this code to support it better.
5947 unsigned RequiredAlign = VT.getSizeInBits()/8;
5948 SDValue Chain = LD->getChain();
5949 // Make sure the stack object alignment is at least 16 or 32.
5950 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5951 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5952 if (MFI->isFixedObjectIndex(FI)) {
5953 // Can't change the alignment. FIXME: It's possible to compute
5954 // the exact stack offset and reference FI + adjust offset instead.
5955 // If someone *really* cares about this. That's the way to implement it.
5958 MFI->setObjectAlignment(FI, RequiredAlign);
5962 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5963 // Ptr + (Offset & ~15).
5966 if ((Offset % RequiredAlign) & 3)
5968 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5970 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5971 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5973 int EltNo = (Offset - StartOffset) >> 2;
5974 unsigned NumElems = VT.getVectorNumElements();
5976 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5977 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5978 LD->getPointerInfo().getWithOffset(StartOffset),
5979 false, false, false, 0);
5981 SmallVector<int, 8> Mask;
5982 for (unsigned i = 0; i != NumElems; ++i)
5983 Mask.push_back(EltNo);
5985 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5991 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5992 /// vector of type 'VT', see if the elements can be replaced by a single large
5993 /// load which has the same value as a build_vector whose operands are 'elts'.
5995 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5997 /// FIXME: we'd also like to handle the case where the last elements are zero
5998 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5999 /// There's even a handy isZeroNode for that purpose.
6000 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6001 SDLoc &DL, SelectionDAG &DAG,
6002 bool isAfterLegalize) {
6003 EVT EltVT = VT.getVectorElementType();
6004 unsigned NumElems = Elts.size();
6006 LoadSDNode *LDBase = nullptr;
6007 unsigned LastLoadedElt = -1U;
6009 // For each element in the initializer, see if we've found a load or an undef.
6010 // If we don't find an initial load element, or later load elements are
6011 // non-consecutive, bail out.
6012 for (unsigned i = 0; i < NumElems; ++i) {
6013 SDValue Elt = Elts[i];
6015 if (!Elt.getNode() ||
6016 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6019 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6021 LDBase = cast<LoadSDNode>(Elt.getNode());
6025 if (Elt.getOpcode() == ISD::UNDEF)
6028 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6029 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6034 // If we have found an entire vector of loads and undefs, then return a large
6035 // load of the entire vector width starting at the base pointer. If we found
6036 // consecutive loads for the low half, generate a vzext_load node.
6037 if (LastLoadedElt == NumElems - 1) {
6039 if (isAfterLegalize &&
6040 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6043 SDValue NewLd = SDValue();
6045 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
6046 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6047 LDBase->getPointerInfo(),
6048 LDBase->isVolatile(), LDBase->isNonTemporal(),
6049 LDBase->isInvariant(), 0);
6050 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6051 LDBase->getPointerInfo(),
6052 LDBase->isVolatile(), LDBase->isNonTemporal(),
6053 LDBase->isInvariant(), LDBase->getAlignment());
6055 if (LDBase->hasAnyUseOfValue(1)) {
6056 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6058 SDValue(NewLd.getNode(), 1));
6059 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6060 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6061 SDValue(NewLd.getNode(), 1));
6067 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6068 //of a v4i32 / v4f32. It's probably worth generalizing.
6069 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6070 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6071 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6072 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6074 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6075 LDBase->getPointerInfo(),
6076 LDBase->getAlignment(),
6077 false/*isVolatile*/, true/*ReadMem*/,
6080 // Make sure the newly-created LOAD is in the same position as LDBase in
6081 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6082 // update uses of LDBase's output chain to use the TokenFactor.
6083 if (LDBase->hasAnyUseOfValue(1)) {
6084 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6085 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6086 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6087 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6088 SDValue(ResNode.getNode(), 1));
6091 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6096 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6097 /// to generate a splat value for the following cases:
6098 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6099 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6100 /// a scalar load, or a constant.
6101 /// The VBROADCAST node is returned when a pattern is found,
6102 /// or SDValue() otherwise.
6103 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6104 SelectionDAG &DAG) {
6105 // VBROADCAST requires AVX.
6106 // TODO: Splats could be generated for non-AVX CPUs using SSE
6107 // instructions, but there's less potential gain for only 128-bit vectors.
6108 if (!Subtarget->hasAVX())
6111 MVT VT = Op.getSimpleValueType();
6114 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6115 "Unsupported vector type for broadcast.");
6120 switch (Op.getOpcode()) {
6122 // Unknown pattern found.
6125 case ISD::BUILD_VECTOR: {
6126 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6127 BitVector UndefElements;
6128 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6130 // We need a splat of a single value to use broadcast, and it doesn't
6131 // make any sense if the value is only in one element of the vector.
6132 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6136 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6137 Ld.getOpcode() == ISD::ConstantFP);
6139 // Make sure that all of the users of a non-constant load are from the
6140 // BUILD_VECTOR node.
6141 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6146 case ISD::VECTOR_SHUFFLE: {
6147 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6149 // Shuffles must have a splat mask where the first element is
6151 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6154 SDValue Sc = Op.getOperand(0);
6155 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6156 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6158 if (!Subtarget->hasInt256())
6161 // Use the register form of the broadcast instruction available on AVX2.
6162 if (VT.getSizeInBits() >= 256)
6163 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6164 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6167 Ld = Sc.getOperand(0);
6168 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6169 Ld.getOpcode() == ISD::ConstantFP);
6171 // The scalar_to_vector node and the suspected
6172 // load node must have exactly one user.
6173 // Constants may have multiple users.
6175 // AVX-512 has register version of the broadcast
6176 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6177 Ld.getValueType().getSizeInBits() >= 32;
6178 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6185 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6186 bool IsGE256 = (VT.getSizeInBits() >= 256);
6188 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6189 // instruction to save 8 or more bytes of constant pool data.
6190 // TODO: If multiple splats are generated to load the same constant,
6191 // it may be detrimental to overall size. There needs to be a way to detect
6192 // that condition to know if this is truly a size win.
6193 const Function *F = DAG.getMachineFunction().getFunction();
6194 bool OptForSize = F->getAttributes().
6195 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6197 // Handle broadcasting a single constant scalar from the constant pool
6199 // On Sandybridge (no AVX2), it is still better to load a constant vector
6200 // from the constant pool and not to broadcast it from a scalar.
6201 // But override that restriction when optimizing for size.
6202 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6203 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6204 EVT CVT = Ld.getValueType();
6205 assert(!CVT.isVector() && "Must not broadcast a vector type");
6207 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6208 // For size optimization, also splat v2f64 and v2i64, and for size opt
6209 // with AVX2, also splat i8 and i16.
6210 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6211 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6212 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6213 const Constant *C = nullptr;
6214 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6215 C = CI->getConstantIntValue();
6216 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6217 C = CF->getConstantFPValue();
6219 assert(C && "Invalid constant type");
6221 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6222 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6223 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6224 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6225 MachinePointerInfo::getConstantPool(),
6226 false, false, false, Alignment);
6228 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6232 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6234 // Handle AVX2 in-register broadcasts.
6235 if (!IsLoad && Subtarget->hasInt256() &&
6236 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6237 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6239 // The scalar source must be a normal load.
6243 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6244 (Subtarget->hasVLX() && ScalarSize == 64))
6245 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6247 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6248 // double since there is no vbroadcastsd xmm
6249 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6250 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6251 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6254 // Unsupported broadcast.
6258 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6259 /// underlying vector and index.
6261 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6263 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6265 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6266 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6269 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6271 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6273 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6274 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6277 // In this case the vector is the extract_subvector expression and the index
6278 // is 2, as specified by the shuffle.
6279 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6280 SDValue ShuffleVec = SVOp->getOperand(0);
6281 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6282 assert(ShuffleVecVT.getVectorElementType() ==
6283 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6285 int ShuffleIdx = SVOp->getMaskElt(Idx);
6286 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6287 ExtractedFromVec = ShuffleVec;
6293 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6294 MVT VT = Op.getSimpleValueType();
6296 // Skip if insert_vec_elt is not supported.
6297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6298 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6302 unsigned NumElems = Op.getNumOperands();
6306 SmallVector<unsigned, 4> InsertIndices;
6307 SmallVector<int, 8> Mask(NumElems, -1);
6309 for (unsigned i = 0; i != NumElems; ++i) {
6310 unsigned Opc = Op.getOperand(i).getOpcode();
6312 if (Opc == ISD::UNDEF)
6315 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6316 // Quit if more than 1 elements need inserting.
6317 if (InsertIndices.size() > 1)
6320 InsertIndices.push_back(i);
6324 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6325 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6326 // Quit if non-constant index.
6327 if (!isa<ConstantSDNode>(ExtIdx))
6329 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6331 // Quit if extracted from vector of different type.
6332 if (ExtractedFromVec.getValueType() != VT)
6335 if (!VecIn1.getNode())
6336 VecIn1 = ExtractedFromVec;
6337 else if (VecIn1 != ExtractedFromVec) {
6338 if (!VecIn2.getNode())
6339 VecIn2 = ExtractedFromVec;
6340 else if (VecIn2 != ExtractedFromVec)
6341 // Quit if more than 2 vectors to shuffle
6345 if (ExtractedFromVec == VecIn1)
6347 else if (ExtractedFromVec == VecIn2)
6348 Mask[i] = Idx + NumElems;
6351 if (!VecIn1.getNode())
6354 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6355 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6356 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6357 unsigned Idx = InsertIndices[i];
6358 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6359 DAG.getIntPtrConstant(Idx));
6365 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6367 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6369 MVT VT = Op.getSimpleValueType();
6370 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6371 "Unexpected type in LowerBUILD_VECTORvXi1!");
6374 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6375 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6376 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6377 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6380 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6381 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6382 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6383 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6386 bool AllContants = true;
6387 uint64_t Immediate = 0;
6388 int NonConstIdx = -1;
6389 bool IsSplat = true;
6390 unsigned NumNonConsts = 0;
6391 unsigned NumConsts = 0;
6392 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6393 SDValue In = Op.getOperand(idx);
6394 if (In.getOpcode() == ISD::UNDEF)
6396 if (!isa<ConstantSDNode>(In)) {
6397 AllContants = false;
6402 if (cast<ConstantSDNode>(In)->getZExtValue())
6403 Immediate |= (1ULL << idx);
6405 if (In != Op.getOperand(0))
6410 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6411 DAG.getConstant(Immediate, MVT::i16));
6412 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6413 DAG.getIntPtrConstant(0));
6416 if (NumNonConsts == 1 && NonConstIdx != 0) {
6419 SDValue VecAsImm = DAG.getConstant(Immediate,
6420 MVT::getIntegerVT(VT.getSizeInBits()));
6421 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6424 DstVec = DAG.getUNDEF(VT);
6425 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6426 Op.getOperand(NonConstIdx),
6427 DAG.getIntPtrConstant(NonConstIdx));
6429 if (!IsSplat && (NonConstIdx != 0))
6430 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6431 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6434 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6435 DAG.getConstant(-1, SelectVT),
6436 DAG.getConstant(0, SelectVT));
6438 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6439 DAG.getConstant((Immediate | 1), SelectVT),
6440 DAG.getConstant(Immediate, SelectVT));
6441 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6444 /// \brief Return true if \p N implements a horizontal binop and return the
6445 /// operands for the horizontal binop into V0 and V1.
6447 /// This is a helper function of PerformBUILD_VECTORCombine.
6448 /// This function checks that the build_vector \p N in input implements a
6449 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6450 /// operation to match.
6451 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6452 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6453 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6456 /// This function only analyzes elements of \p N whose indices are
6457 /// in range [BaseIdx, LastIdx).
6458 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6460 unsigned BaseIdx, unsigned LastIdx,
6461 SDValue &V0, SDValue &V1) {
6462 EVT VT = N->getValueType(0);
6464 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6465 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6466 "Invalid Vector in input!");
6468 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6469 bool CanFold = true;
6470 unsigned ExpectedVExtractIdx = BaseIdx;
6471 unsigned NumElts = LastIdx - BaseIdx;
6472 V0 = DAG.getUNDEF(VT);
6473 V1 = DAG.getUNDEF(VT);
6475 // Check if N implements a horizontal binop.
6476 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6477 SDValue Op = N->getOperand(i + BaseIdx);
6480 if (Op->getOpcode() == ISD::UNDEF) {
6481 // Update the expected vector extract index.
6482 if (i * 2 == NumElts)
6483 ExpectedVExtractIdx = BaseIdx;
6484 ExpectedVExtractIdx += 2;
6488 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6493 SDValue Op0 = Op.getOperand(0);
6494 SDValue Op1 = Op.getOperand(1);
6496 // Try to match the following pattern:
6497 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6498 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6499 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6500 Op0.getOperand(0) == Op1.getOperand(0) &&
6501 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6502 isa<ConstantSDNode>(Op1.getOperand(1)));
6506 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6507 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6509 if (i * 2 < NumElts) {
6510 if (V0.getOpcode() == ISD::UNDEF)
6511 V0 = Op0.getOperand(0);
6513 if (V1.getOpcode() == ISD::UNDEF)
6514 V1 = Op0.getOperand(0);
6515 if (i * 2 == NumElts)
6516 ExpectedVExtractIdx = BaseIdx;
6519 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6520 if (I0 == ExpectedVExtractIdx)
6521 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6522 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6523 // Try to match the following dag sequence:
6524 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6525 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6529 ExpectedVExtractIdx += 2;
6535 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6536 /// a concat_vector.
6538 /// This is a helper function of PerformBUILD_VECTORCombine.
6539 /// This function expects two 256-bit vectors called V0 and V1.
6540 /// At first, each vector is split into two separate 128-bit vectors.
6541 /// Then, the resulting 128-bit vectors are used to implement two
6542 /// horizontal binary operations.
6544 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6546 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6547 /// the two new horizontal binop.
6548 /// When Mode is set, the first horizontal binop dag node would take as input
6549 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6550 /// horizontal binop dag node would take as input the lower 128-bit of V1
6551 /// and the upper 128-bit of V1.
6553 /// HADD V0_LO, V0_HI
6554 /// HADD V1_LO, V1_HI
6556 /// Otherwise, the first horizontal binop dag node takes as input the lower
6557 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6558 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6560 /// HADD V0_LO, V1_LO
6561 /// HADD V0_HI, V1_HI
6563 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6564 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6565 /// the upper 128-bits of the result.
6566 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6567 SDLoc DL, SelectionDAG &DAG,
6568 unsigned X86Opcode, bool Mode,
6569 bool isUndefLO, bool isUndefHI) {
6570 EVT VT = V0.getValueType();
6571 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6572 "Invalid nodes in input!");
6574 unsigned NumElts = VT.getVectorNumElements();
6575 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6576 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6577 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6578 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6579 EVT NewVT = V0_LO.getValueType();
6581 SDValue LO = DAG.getUNDEF(NewVT);
6582 SDValue HI = DAG.getUNDEF(NewVT);
6585 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6586 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6587 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6588 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6589 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6591 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6592 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6593 V1_LO->getOpcode() != ISD::UNDEF))
6594 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6596 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6597 V1_HI->getOpcode() != ISD::UNDEF))
6598 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6601 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6604 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6605 /// sequence of 'vadd + vsub + blendi'.
6606 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6607 const X86Subtarget *Subtarget) {
6609 EVT VT = BV->getValueType(0);
6610 unsigned NumElts = VT.getVectorNumElements();
6611 SDValue InVec0 = DAG.getUNDEF(VT);
6612 SDValue InVec1 = DAG.getUNDEF(VT);
6614 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6615 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6617 // Odd-numbered elements in the input build vector are obtained from
6618 // adding two integer/float elements.
6619 // Even-numbered elements in the input build vector are obtained from
6620 // subtracting two integer/float elements.
6621 unsigned ExpectedOpcode = ISD::FSUB;
6622 unsigned NextExpectedOpcode = ISD::FADD;
6623 bool AddFound = false;
6624 bool SubFound = false;
6626 for (unsigned i = 0, e = NumElts; i != e; i++) {
6627 SDValue Op = BV->getOperand(i);
6629 // Skip 'undef' values.
6630 unsigned Opcode = Op.getOpcode();
6631 if (Opcode == ISD::UNDEF) {
6632 std::swap(ExpectedOpcode, NextExpectedOpcode);
6636 // Early exit if we found an unexpected opcode.
6637 if (Opcode != ExpectedOpcode)
6640 SDValue Op0 = Op.getOperand(0);
6641 SDValue Op1 = Op.getOperand(1);
6643 // Try to match the following pattern:
6644 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6645 // Early exit if we cannot match that sequence.
6646 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6647 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6648 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6649 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6650 Op0.getOperand(1) != Op1.getOperand(1))
6653 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6657 // We found a valid add/sub node. Update the information accordingly.
6663 // Update InVec0 and InVec1.
6664 if (InVec0.getOpcode() == ISD::UNDEF)
6665 InVec0 = Op0.getOperand(0);
6666 if (InVec1.getOpcode() == ISD::UNDEF)
6667 InVec1 = Op1.getOperand(0);
6669 // Make sure that operands in input to each add/sub node always
6670 // come from a same pair of vectors.
6671 if (InVec0 != Op0.getOperand(0)) {
6672 if (ExpectedOpcode == ISD::FSUB)
6675 // FADD is commutable. Try to commute the operands
6676 // and then test again.
6677 std::swap(Op0, Op1);
6678 if (InVec0 != Op0.getOperand(0))
6682 if (InVec1 != Op1.getOperand(0))
6685 // Update the pair of expected opcodes.
6686 std::swap(ExpectedOpcode, NextExpectedOpcode);
6689 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6690 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6691 InVec1.getOpcode() != ISD::UNDEF)
6692 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6697 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6698 const X86Subtarget *Subtarget) {
6700 EVT VT = N->getValueType(0);
6701 unsigned NumElts = VT.getVectorNumElements();
6702 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6703 SDValue InVec0, InVec1;
6705 // Try to match an ADDSUB.
6706 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6707 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6708 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6709 if (Value.getNode())
6713 // Try to match horizontal ADD/SUB.
6714 unsigned NumUndefsLO = 0;
6715 unsigned NumUndefsHI = 0;
6716 unsigned Half = NumElts/2;
6718 // Count the number of UNDEF operands in the build_vector in input.
6719 for (unsigned i = 0, e = Half; i != e; ++i)
6720 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6723 for (unsigned i = Half, e = NumElts; i != e; ++i)
6724 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6727 // Early exit if this is either a build_vector of all UNDEFs or all the
6728 // operands but one are UNDEF.
6729 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6732 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6733 // Try to match an SSE3 float HADD/HSUB.
6734 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6735 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6737 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6738 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6739 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6740 // Try to match an SSSE3 integer HADD/HSUB.
6741 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6742 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6744 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6745 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6748 if (!Subtarget->hasAVX())
6751 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6752 // Try to match an AVX horizontal add/sub of packed single/double
6753 // precision floating point values from 256-bit vectors.
6754 SDValue InVec2, InVec3;
6755 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6756 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6757 ((InVec0.getOpcode() == ISD::UNDEF ||
6758 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6759 ((InVec1.getOpcode() == ISD::UNDEF ||
6760 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6761 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6763 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6764 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6765 ((InVec0.getOpcode() == ISD::UNDEF ||
6766 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6767 ((InVec1.getOpcode() == ISD::UNDEF ||
6768 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6769 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6770 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6771 // Try to match an AVX2 horizontal add/sub of signed integers.
6772 SDValue InVec2, InVec3;
6774 bool CanFold = true;
6776 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6777 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6778 ((InVec0.getOpcode() == ISD::UNDEF ||
6779 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6780 ((InVec1.getOpcode() == ISD::UNDEF ||
6781 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6782 X86Opcode = X86ISD::HADD;
6783 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6784 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6785 ((InVec0.getOpcode() == ISD::UNDEF ||
6786 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6787 ((InVec1.getOpcode() == ISD::UNDEF ||
6788 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6789 X86Opcode = X86ISD::HSUB;
6794 // Fold this build_vector into a single horizontal add/sub.
6795 // Do this only if the target has AVX2.
6796 if (Subtarget->hasAVX2())
6797 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6799 // Do not try to expand this build_vector into a pair of horizontal
6800 // add/sub if we can emit a pair of scalar add/sub.
6801 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6804 // Convert this build_vector into a pair of horizontal binop followed by
6806 bool isUndefLO = NumUndefsLO == Half;
6807 bool isUndefHI = NumUndefsHI == Half;
6808 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6809 isUndefLO, isUndefHI);
6813 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6814 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6816 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6817 X86Opcode = X86ISD::HADD;
6818 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6819 X86Opcode = X86ISD::HSUB;
6820 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6821 X86Opcode = X86ISD::FHADD;
6822 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6823 X86Opcode = X86ISD::FHSUB;
6827 // Don't try to expand this build_vector into a pair of horizontal add/sub
6828 // if we can simply emit a pair of scalar add/sub.
6829 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6832 // Convert this build_vector into two horizontal add/sub followed by
6834 bool isUndefLO = NumUndefsLO == Half;
6835 bool isUndefHI = NumUndefsHI == Half;
6836 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6837 isUndefLO, isUndefHI);
6844 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6847 MVT VT = Op.getSimpleValueType();
6848 MVT ExtVT = VT.getVectorElementType();
6849 unsigned NumElems = Op.getNumOperands();
6851 // Generate vectors for predicate vectors.
6852 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6853 return LowerBUILD_VECTORvXi1(Op, DAG);
6855 // Vectors containing all zeros can be matched by pxor and xorps later
6856 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6857 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6858 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6859 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6862 return getZeroVector(VT, Subtarget, DAG, dl);
6865 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6866 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6867 // vpcmpeqd on 256-bit vectors.
6868 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6869 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6872 if (!VT.is512BitVector())
6873 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6876 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6877 if (Broadcast.getNode())
6880 unsigned EVTBits = ExtVT.getSizeInBits();
6882 unsigned NumZero = 0;
6883 unsigned NumNonZero = 0;
6884 unsigned NonZeros = 0;
6885 bool IsAllConstants = true;
6886 SmallSet<SDValue, 8> Values;
6887 for (unsigned i = 0; i < NumElems; ++i) {
6888 SDValue Elt = Op.getOperand(i);
6889 if (Elt.getOpcode() == ISD::UNDEF)
6892 if (Elt.getOpcode() != ISD::Constant &&
6893 Elt.getOpcode() != ISD::ConstantFP)
6894 IsAllConstants = false;
6895 if (X86::isZeroNode(Elt))
6898 NonZeros |= (1 << i);
6903 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6904 if (NumNonZero == 0)
6905 return DAG.getUNDEF(VT);
6907 // Special case for single non-zero, non-undef, element.
6908 if (NumNonZero == 1) {
6909 unsigned Idx = countTrailingZeros(NonZeros);
6910 SDValue Item = Op.getOperand(Idx);
6912 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6913 // the value are obviously zero, truncate the value to i32 and do the
6914 // insertion that way. Only do this if the value is non-constant or if the
6915 // value is a constant being inserted into element 0. It is cheaper to do
6916 // a constant pool load than it is to do a movd + shuffle.
6917 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6918 (!IsAllConstants || Idx == 0)) {
6919 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6921 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6922 EVT VecVT = MVT::v4i32;
6923 unsigned VecElts = 4;
6925 // Truncate the value (which may itself be a constant) to i32, and
6926 // convert it to a vector with movd (S2V+shuffle to zero extend).
6927 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6928 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6930 // If using the new shuffle lowering, just directly insert this.
6931 if (ExperimentalVectorShuffleLowering)
6933 ISD::BITCAST, dl, VT,
6934 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6936 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6938 // Now we have our 32-bit value zero extended in the low element of
6939 // a vector. If Idx != 0, swizzle it into place.
6941 SmallVector<int, 4> Mask;
6942 Mask.push_back(Idx);
6943 for (unsigned i = 1; i != VecElts; ++i)
6945 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6948 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6952 // If we have a constant or non-constant insertion into the low element of
6953 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6954 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6955 // depending on what the source datatype is.
6958 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6960 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6961 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6962 if (VT.is256BitVector() || VT.is512BitVector()) {
6963 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6964 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6965 Item, DAG.getIntPtrConstant(0));
6967 assert(VT.is128BitVector() && "Expected an SSE value type!");
6968 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6969 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6970 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6973 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6974 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6975 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6976 if (VT.is256BitVector()) {
6977 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6978 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6980 assert(VT.is128BitVector() && "Expected an SSE value type!");
6981 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6983 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6987 // Is it a vector logical left shift?
6988 if (NumElems == 2 && Idx == 1 &&
6989 X86::isZeroNode(Op.getOperand(0)) &&
6990 !X86::isZeroNode(Op.getOperand(1))) {
6991 unsigned NumBits = VT.getSizeInBits();
6992 return getVShift(true, VT,
6993 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6994 VT, Op.getOperand(1)),
6995 NumBits/2, DAG, *this, dl);
6998 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7001 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7002 // is a non-constant being inserted into an element other than the low one,
7003 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7004 // movd/movss) to move this into the low element, then shuffle it into
7006 if (EVTBits == 32) {
7007 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7009 // If using the new shuffle lowering, just directly insert this.
7010 if (ExperimentalVectorShuffleLowering)
7011 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7013 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7014 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7015 SmallVector<int, 8> MaskVec;
7016 for (unsigned i = 0; i != NumElems; ++i)
7017 MaskVec.push_back(i == Idx ? 0 : 1);
7018 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7022 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7023 if (Values.size() == 1) {
7024 if (EVTBits == 32) {
7025 // Instead of a shuffle like this:
7026 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7027 // Check if it's possible to issue this instead.
7028 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7029 unsigned Idx = countTrailingZeros(NonZeros);
7030 SDValue Item = Op.getOperand(Idx);
7031 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7032 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7037 // A vector full of immediates; various special cases are already
7038 // handled, so this is best done with a single constant-pool load.
7042 // For AVX-length vectors, see if we can use a vector load to get all of the
7043 // elements, otherwise build the individual 128-bit pieces and use
7044 // shuffles to put them in place.
7045 if (VT.is256BitVector() || VT.is512BitVector()) {
7046 SmallVector<SDValue, 64> V;
7047 for (unsigned i = 0; i != NumElems; ++i)
7048 V.push_back(Op.getOperand(i));
7050 // Check for a build vector of consecutive loads.
7051 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7054 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7056 // Build both the lower and upper subvector.
7057 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7058 makeArrayRef(&V[0], NumElems/2));
7059 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7060 makeArrayRef(&V[NumElems / 2], NumElems/2));
7062 // Recreate the wider vector with the lower and upper part.
7063 if (VT.is256BitVector())
7064 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7065 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7068 // Let legalizer expand 2-wide build_vectors.
7069 if (EVTBits == 64) {
7070 if (NumNonZero == 1) {
7071 // One half is zero or undef.
7072 unsigned Idx = countTrailingZeros(NonZeros);
7073 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7074 Op.getOperand(Idx));
7075 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7080 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7081 if (EVTBits == 8 && NumElems == 16) {
7082 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7084 if (V.getNode()) return V;
7087 if (EVTBits == 16 && NumElems == 8) {
7088 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7090 if (V.getNode()) return V;
7093 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7094 if (EVTBits == 32 && NumElems == 4) {
7095 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7100 // If element VT is == 32 bits, turn it into a number of shuffles.
7101 SmallVector<SDValue, 8> V(NumElems);
7102 if (NumElems == 4 && NumZero > 0) {
7103 for (unsigned i = 0; i < 4; ++i) {
7104 bool isZero = !(NonZeros & (1 << i));
7106 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7108 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7111 for (unsigned i = 0; i < 2; ++i) {
7112 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7115 V[i] = V[i*2]; // Must be a zero vector.
7118 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7121 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7124 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7129 bool Reverse1 = (NonZeros & 0x3) == 2;
7130 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7134 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7135 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7137 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7140 if (Values.size() > 1 && VT.is128BitVector()) {
7141 // Check for a build vector of consecutive loads.
7142 for (unsigned i = 0; i < NumElems; ++i)
7143 V[i] = Op.getOperand(i);
7145 // Check for elements which are consecutive loads.
7146 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7150 // Check for a build vector from mostly shuffle plus few inserting.
7151 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7155 // For SSE 4.1, use insertps to put the high elements into the low element.
7156 if (getSubtarget()->hasSSE41()) {
7158 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7159 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7161 Result = DAG.getUNDEF(VT);
7163 for (unsigned i = 1; i < NumElems; ++i) {
7164 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7165 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7166 Op.getOperand(i), DAG.getIntPtrConstant(i));
7171 // Otherwise, expand into a number of unpckl*, start by extending each of
7172 // our (non-undef) elements to the full vector width with the element in the
7173 // bottom slot of the vector (which generates no code for SSE).
7174 for (unsigned i = 0; i < NumElems; ++i) {
7175 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7176 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7178 V[i] = DAG.getUNDEF(VT);
7181 // Next, we iteratively mix elements, e.g. for v4f32:
7182 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7183 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7184 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7185 unsigned EltStride = NumElems >> 1;
7186 while (EltStride != 0) {
7187 for (unsigned i = 0; i < EltStride; ++i) {
7188 // If V[i+EltStride] is undef and this is the first round of mixing,
7189 // then it is safe to just drop this shuffle: V[i] is already in the
7190 // right place, the one element (since it's the first round) being
7191 // inserted as undef can be dropped. This isn't safe for successive
7192 // rounds because they will permute elements within both vectors.
7193 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7194 EltStride == NumElems/2)
7197 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7206 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7207 // to create 256-bit vectors from two other 128-bit ones.
7208 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7210 MVT ResVT = Op.getSimpleValueType();
7212 assert((ResVT.is256BitVector() ||
7213 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7215 SDValue V1 = Op.getOperand(0);
7216 SDValue V2 = Op.getOperand(1);
7217 unsigned NumElems = ResVT.getVectorNumElements();
7218 if(ResVT.is256BitVector())
7219 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7221 if (Op.getNumOperands() == 4) {
7222 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7223 ResVT.getVectorNumElements()/2);
7224 SDValue V3 = Op.getOperand(2);
7225 SDValue V4 = Op.getOperand(3);
7226 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7227 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7229 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7232 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7233 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7234 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7235 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7236 Op.getNumOperands() == 4)));
7238 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7239 // from two other 128-bit ones.
7241 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7242 return LowerAVXCONCAT_VECTORS(Op, DAG);
7246 //===----------------------------------------------------------------------===//
7247 // Vector shuffle lowering
7249 // This is an experimental code path for lowering vector shuffles on x86. It is
7250 // designed to handle arbitrary vector shuffles and blends, gracefully
7251 // degrading performance as necessary. It works hard to recognize idiomatic
7252 // shuffles and lower them to optimal instruction patterns without leaving
7253 // a framework that allows reasonably efficient handling of all vector shuffle
7255 //===----------------------------------------------------------------------===//
7257 /// \brief Tiny helper function to identify a no-op mask.
7259 /// This is a somewhat boring predicate function. It checks whether the mask
7260 /// array input, which is assumed to be a single-input shuffle mask of the kind
7261 /// used by the X86 shuffle instructions (not a fully general
7262 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7263 /// in-place shuffle are 'no-op's.
7264 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7265 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7266 if (Mask[i] != -1 && Mask[i] != i)
7271 /// \brief Helper function to classify a mask as a single-input mask.
7273 /// This isn't a generic single-input test because in the vector shuffle
7274 /// lowering we canonicalize single inputs to be the first input operand. This
7275 /// means we can more quickly test for a single input by only checking whether
7276 /// an input from the second operand exists. We also assume that the size of
7277 /// mask corresponds to the size of the input vectors which isn't true in the
7278 /// fully general case.
7279 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7281 if (M >= (int)Mask.size())
7286 /// \brief Test whether there are elements crossing 128-bit lanes in this
7289 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7290 /// and we routinely test for these.
7291 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7292 int LaneSize = 128 / VT.getScalarSizeInBits();
7293 int Size = Mask.size();
7294 for (int i = 0; i < Size; ++i)
7295 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7300 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7302 /// This checks a shuffle mask to see if it is performing the same
7303 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7304 /// that it is also not lane-crossing. It may however involve a blend from the
7305 /// same lane of a second vector.
7307 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7308 /// non-trivial to compute in the face of undef lanes. The representation is
7309 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7310 /// entries from both V1 and V2 inputs to the wider mask.
7312 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7313 SmallVectorImpl<int> &RepeatedMask) {
7314 int LaneSize = 128 / VT.getScalarSizeInBits();
7315 RepeatedMask.resize(LaneSize, -1);
7316 int Size = Mask.size();
7317 for (int i = 0; i < Size; ++i) {
7320 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7321 // This entry crosses lanes, so there is no way to model this shuffle.
7324 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7325 if (RepeatedMask[i % LaneSize] == -1)
7326 // This is the first non-undef entry in this slot of a 128-bit lane.
7327 RepeatedMask[i % LaneSize] =
7328 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7329 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7330 // Found a mismatch with the repeated mask.
7336 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7337 // 2013 will allow us to use it as a non-type template parameter.
7340 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7342 /// See its documentation for details.
7343 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7344 if (Mask.size() != Args.size())
7346 for (int i = 0, e = Mask.size(); i < e; ++i) {
7347 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7348 if (Mask[i] != -1 && Mask[i] != *Args[i])
7356 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7359 /// This is a fast way to test a shuffle mask against a fixed pattern:
7361 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7363 /// It returns true if the mask is exactly as wide as the argument list, and
7364 /// each element of the mask is either -1 (signifying undef) or the value given
7365 /// in the argument.
7366 static const VariadicFunction1<
7367 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7369 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7371 /// This helper function produces an 8-bit shuffle immediate corresponding to
7372 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7373 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7376 /// NB: We rely heavily on "undef" masks preserving the input lane.
7377 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7378 SelectionDAG &DAG) {
7379 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7380 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7381 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7382 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7383 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7386 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7387 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7388 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7389 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7390 return DAG.getConstant(Imm, MVT::i8);
7393 /// \brief Try to emit a blend instruction for a shuffle.
7395 /// This doesn't do any checks for the availability of instructions for blending
7396 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7397 /// be matched in the backend with the type given. What it does check for is
7398 /// that the shuffle mask is in fact a blend.
7399 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7400 SDValue V2, ArrayRef<int> Mask,
7401 const X86Subtarget *Subtarget,
7402 SelectionDAG &DAG) {
7404 unsigned BlendMask = 0;
7405 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7406 if (Mask[i] >= Size) {
7407 if (Mask[i] != i + Size)
7408 return SDValue(); // Shuffled V2 input!
7409 BlendMask |= 1u << i;
7412 if (Mask[i] >= 0 && Mask[i] != i)
7413 return SDValue(); // Shuffled V1 input!
7415 switch (VT.SimpleTy) {
7420 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7421 DAG.getConstant(BlendMask, MVT::i8));
7425 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7429 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7430 // that instruction.
7431 if (Subtarget->hasAVX2()) {
7432 // Scale the blend by the number of 32-bit dwords per element.
7433 int Scale = VT.getScalarSizeInBits() / 32;
7435 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7436 if (Mask[i] >= Size)
7437 for (int j = 0; j < Scale; ++j)
7438 BlendMask |= 1u << (i * Scale + j);
7440 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7441 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7442 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7443 return DAG.getNode(ISD::BITCAST, DL, VT,
7444 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7445 DAG.getConstant(BlendMask, MVT::i8)));
7449 // For integer shuffles we need to expand the mask and cast the inputs to
7450 // v8i16s prior to blending.
7451 int Scale = 8 / VT.getVectorNumElements();
7453 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7454 if (Mask[i] >= Size)
7455 for (int j = 0; j < Scale; ++j)
7456 BlendMask |= 1u << (i * Scale + j);
7458 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7459 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7460 return DAG.getNode(ISD::BITCAST, DL, VT,
7461 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7462 DAG.getConstant(BlendMask, MVT::i8)));
7466 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7467 SmallVector<int, 8> RepeatedMask;
7468 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7469 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7470 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7472 for (int i = 0; i < 8; ++i)
7473 if (RepeatedMask[i] >= 16)
7474 BlendMask |= 1u << i;
7475 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7476 DAG.getConstant(BlendMask, MVT::i8));
7481 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7482 // Scale the blend by the number of bytes per element.
7483 int Scale = VT.getScalarSizeInBits() / 8;
7484 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7486 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7487 // mix of LLVM's code generator and the x86 backend. We tell the code
7488 // generator that boolean values in the elements of an x86 vector register
7489 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7490 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7491 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7492 // of the element (the remaining are ignored) and 0 in that high bit would
7493 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7494 // the LLVM model for boolean values in vector elements gets the relevant
7495 // bit set, it is set backwards and over constrained relative to x86's
7497 SDValue VSELECTMask[32];
7498 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7499 for (int j = 0; j < Scale; ++j)
7500 VSELECTMask[Scale * i + j] =
7501 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7502 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7504 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7505 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7507 ISD::BITCAST, DL, VT,
7508 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7509 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7514 llvm_unreachable("Not a supported integer vector type!");
7518 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7519 /// unblended shuffles followed by an unshuffled blend.
7521 /// This matches the extremely common pattern for handling combined
7522 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7524 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7528 SelectionDAG &DAG) {
7529 // Shuffle the input elements into the desired positions in V1 and V2 and
7530 // blend them together.
7531 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7532 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7533 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7534 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7535 if (Mask[i] >= 0 && Mask[i] < Size) {
7536 V1Mask[i] = Mask[i];
7538 } else if (Mask[i] >= Size) {
7539 V2Mask[i] = Mask[i] - Size;
7540 BlendMask[i] = i + Size;
7543 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7544 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7545 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7548 /// \brief Try to lower a vector shuffle as a byte rotation.
7550 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7551 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7552 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7553 /// try to generically lower a vector shuffle through such an pattern. It
7554 /// does not check for the profitability of lowering either as PALIGNR or
7555 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7556 /// This matches shuffle vectors that look like:
7558 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7560 /// Essentially it concatenates V1 and V2, shifts right by some number of
7561 /// elements, and takes the low elements as the result. Note that while this is
7562 /// specified as a *right shift* because x86 is little-endian, it is a *left
7563 /// rotate* of the vector lanes.
7565 /// Note that this only handles 128-bit vector widths currently.
7566 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7569 const X86Subtarget *Subtarget,
7570 SelectionDAG &DAG) {
7571 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7573 // We need to detect various ways of spelling a rotation:
7574 // [11, 12, 13, 14, 15, 0, 1, 2]
7575 // [-1, 12, 13, 14, -1, -1, 1, -1]
7576 // [-1, -1, -1, -1, -1, -1, 1, 2]
7577 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7578 // [-1, 4, 5, 6, -1, -1, 9, -1]
7579 // [-1, 4, 5, 6, -1, -1, -1, -1]
7582 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7585 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7587 // Based on the mod-Size value of this mask element determine where
7588 // a rotated vector would have started.
7589 int StartIdx = i - (Mask[i] % Size);
7591 // The identity rotation isn't interesting, stop.
7594 // If we found the tail of a vector the rotation must be the missing
7595 // front. If we found the head of a vector, it must be how much of the head.
7596 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7599 Rotation = CandidateRotation;
7600 else if (Rotation != CandidateRotation)
7601 // The rotations don't match, so we can't match this mask.
7604 // Compute which value this mask is pointing at.
7605 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7607 // Compute which of the two target values this index should be assigned to.
7608 // This reflects whether the high elements are remaining or the low elements
7610 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7612 // Either set up this value if we've not encountered it before, or check
7613 // that it remains consistent.
7616 else if (TargetV != MaskV)
7617 // This may be a rotation, but it pulls from the inputs in some
7618 // unsupported interleaving.
7622 // Check that we successfully analyzed the mask, and normalize the results.
7623 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7624 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7630 assert(VT.getSizeInBits() == 128 &&
7631 "Rotate-based lowering only supports 128-bit lowering!");
7632 assert(Mask.size() <= 16 &&
7633 "Can shuffle at most 16 bytes in a 128-bit vector!");
7635 // The actual rotate instruction rotates bytes, so we need to scale the
7636 // rotation based on how many bytes are in the vector.
7637 int Scale = 16 / Mask.size();
7639 // SSSE3 targets can use the palignr instruction
7640 if (Subtarget->hasSSSE3()) {
7641 // Cast the inputs to v16i8 to match PALIGNR.
7642 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7643 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7645 return DAG.getNode(ISD::BITCAST, DL, VT,
7646 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7647 DAG.getConstant(Rotation * Scale, MVT::i8)));
7650 // Default SSE2 implementation
7651 int LoByteShift = 16 - Rotation * Scale;
7652 int HiByteShift = Rotation * Scale;
7654 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7655 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7656 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7658 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7659 DAG.getConstant(8 * LoByteShift, MVT::i8));
7660 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7661 DAG.getConstant(8 * HiByteShift, MVT::i8));
7662 return DAG.getNode(ISD::BITCAST, DL, VT,
7663 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7666 /// \brief Compute whether each element of a shuffle is zeroable.
7668 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7669 /// Either it is an undef element in the shuffle mask, the element of the input
7670 /// referenced is undef, or the element of the input referenced is known to be
7671 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7672 /// as many lanes with this technique as possible to simplify the remaining
7674 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7675 SDValue V1, SDValue V2) {
7676 SmallBitVector Zeroable(Mask.size(), false);
7678 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7679 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7681 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7683 // Handle the easy cases.
7684 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7689 // If this is an index into a build_vector node, dig out the input value and
7691 SDValue V = M < Size ? V1 : V2;
7692 if (V.getOpcode() != ISD::BUILD_VECTOR)
7695 SDValue Input = V.getOperand(M % Size);
7696 // The UNDEF opcode check really should be dead code here, but not quite
7697 // worth asserting on (it isn't invalid, just unexpected).
7698 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7705 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7707 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7708 /// byte-shift instructions. The mask must consist of a shifted sequential
7709 /// shuffle from one of the input vectors and zeroable elements for the
7710 /// remaining 'shifted in' elements.
7712 /// Note that this only handles 128-bit vector widths currently.
7713 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7714 SDValue V2, ArrayRef<int> Mask,
7715 SelectionDAG &DAG) {
7716 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7718 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7720 int Size = Mask.size();
7721 int Scale = 16 / Size;
7723 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7724 ArrayRef<int> Mask) {
7725 for (int i = StartIndex; i < EndIndex; i++) {
7728 if (i + Base != Mask[i] - MaskOffset)
7734 for (int Shift = 1; Shift < Size; Shift++) {
7735 int ByteShift = Shift * Scale;
7737 // PSRLDQ : (little-endian) right byte shift
7738 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7739 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7740 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7741 bool ZeroableRight = true;
7742 for (int i = Size - Shift; i < Size; i++) {
7743 ZeroableRight &= Zeroable[i];
7746 if (ZeroableRight) {
7747 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7748 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7750 if (ValidShiftRight1 || ValidShiftRight2) {
7751 // Cast the inputs to v2i64 to match PSRLDQ.
7752 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7753 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7754 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7755 DAG.getConstant(ByteShift * 8, MVT::i8));
7756 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7760 // PSLLDQ : (little-endian) left byte shift
7761 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7762 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7763 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7764 bool ZeroableLeft = true;
7765 for (int i = 0; i < Shift; i++) {
7766 ZeroableLeft &= Zeroable[i];
7770 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7771 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7773 if (ValidShiftLeft1 || ValidShiftLeft2) {
7774 // Cast the inputs to v2i64 to match PSLLDQ.
7775 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7776 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7777 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7778 DAG.getConstant(ByteShift * 8, MVT::i8));
7779 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7787 /// \brief Lower a vector shuffle as a zero or any extension.
7789 /// Given a specific number of elements, element bit width, and extension
7790 /// stride, produce either a zero or any extension based on the available
7791 /// features of the subtarget.
7792 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7793 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7794 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7795 assert(Scale > 1 && "Need a scale to extend.");
7796 int EltBits = VT.getSizeInBits() / NumElements;
7797 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7798 "Only 8, 16, and 32 bit elements can be extended.");
7799 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7801 // Found a valid zext mask! Try various lowering strategies based on the
7802 // input type and available ISA extensions.
7803 if (Subtarget->hasSSE41()) {
7804 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7805 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7806 NumElements / Scale);
7807 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7808 return DAG.getNode(ISD::BITCAST, DL, VT,
7809 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7812 // For any extends we can cheat for larger element sizes and use shuffle
7813 // instructions that can fold with a load and/or copy.
7814 if (AnyExt && EltBits == 32) {
7815 int PSHUFDMask[4] = {0, -1, 1, -1};
7817 ISD::BITCAST, DL, VT,
7818 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7819 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7820 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7822 if (AnyExt && EltBits == 16 && Scale > 2) {
7823 int PSHUFDMask[4] = {0, -1, 0, -1};
7824 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7825 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7826 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7827 int PSHUFHWMask[4] = {1, -1, -1, -1};
7829 ISD::BITCAST, DL, VT,
7830 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7831 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7832 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7835 // If this would require more than 2 unpack instructions to expand, use
7836 // pshufb when available. We can only use more than 2 unpack instructions
7837 // when zero extending i8 elements which also makes it easier to use pshufb.
7838 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7839 assert(NumElements == 16 && "Unexpected byte vector width!");
7840 SDValue PSHUFBMask[16];
7841 for (int i = 0; i < 16; ++i)
7843 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7844 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7845 return DAG.getNode(ISD::BITCAST, DL, VT,
7846 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7847 DAG.getNode(ISD::BUILD_VECTOR, DL,
7848 MVT::v16i8, PSHUFBMask)));
7851 // Otherwise emit a sequence of unpacks.
7853 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7854 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7855 : getZeroVector(InputVT, Subtarget, DAG, DL);
7856 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7857 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7861 } while (Scale > 1);
7862 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7865 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7867 /// This routine will try to do everything in its power to cleverly lower
7868 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7869 /// check for the profitability of this lowering, it tries to aggressively
7870 /// match this pattern. It will use all of the micro-architectural details it
7871 /// can to emit an efficient lowering. It handles both blends with all-zero
7872 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7873 /// masking out later).
7875 /// The reason we have dedicated lowering for zext-style shuffles is that they
7876 /// are both incredibly common and often quite performance sensitive.
7877 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7878 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7879 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7880 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7882 int Bits = VT.getSizeInBits();
7883 int NumElements = Mask.size();
7885 // Define a helper function to check a particular ext-scale and lower to it if
7887 auto Lower = [&](int Scale) -> SDValue {
7890 for (int i = 0; i < NumElements; ++i) {
7892 continue; // Valid anywhere but doesn't tell us anything.
7893 if (i % Scale != 0) {
7894 // Each of the extend elements needs to be zeroable.
7898 // We no lorger are in the anyext case.
7903 // Each of the base elements needs to be consecutive indices into the
7904 // same input vector.
7905 SDValue V = Mask[i] < NumElements ? V1 : V2;
7908 else if (InputV != V)
7909 return SDValue(); // Flip-flopping inputs.
7911 if (Mask[i] % NumElements != i / Scale)
7912 return SDValue(); // Non-consecutive strided elemenst.
7915 // If we fail to find an input, we have a zero-shuffle which should always
7916 // have already been handled.
7917 // FIXME: Maybe handle this here in case during blending we end up with one?
7921 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7922 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7925 // The widest scale possible for extending is to a 64-bit integer.
7926 assert(Bits % 64 == 0 &&
7927 "The number of bits in a vector must be divisible by 64 on x86!");
7928 int NumExtElements = Bits / 64;
7930 // Each iteration, try extending the elements half as much, but into twice as
7932 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7933 assert(NumElements % NumExtElements == 0 &&
7934 "The input vector size must be divisble by the extended size.");
7935 if (SDValue V = Lower(NumElements / NumExtElements))
7939 // No viable ext lowering found.
7943 /// \brief Try to get a scalar value for a specific element of a vector.
7945 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7946 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7947 SelectionDAG &DAG) {
7948 MVT VT = V.getSimpleValueType();
7949 MVT EltVT = VT.getVectorElementType();
7950 while (V.getOpcode() == ISD::BITCAST)
7951 V = V.getOperand(0);
7952 // If the bitcasts shift the element size, we can't extract an equivalent
7954 MVT NewVT = V.getSimpleValueType();
7955 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7958 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7959 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7960 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7965 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7967 /// This is particularly important because the set of instructions varies
7968 /// significantly based on whether the operand is a load or not.
7969 static bool isShuffleFoldableLoad(SDValue V) {
7970 while (V.getOpcode() == ISD::BITCAST)
7971 V = V.getOperand(0);
7973 return ISD::isNON_EXTLoad(V.getNode());
7976 /// \brief Try to lower insertion of a single element into a zero vector.
7978 /// This is a common pattern that we have especially efficient patterns to lower
7979 /// across all subtarget feature sets.
7980 static SDValue lowerVectorShuffleAsElementInsertion(
7981 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7982 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7983 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7985 MVT EltVT = VT.getVectorElementType();
7987 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7988 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7990 bool IsV1Zeroable = true;
7991 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7992 if (i != V2Index && !Zeroable[i]) {
7993 IsV1Zeroable = false;
7997 // Check for a single input from a SCALAR_TO_VECTOR node.
7998 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7999 // all the smarts here sunk into that routine. However, the current
8000 // lowering of BUILD_VECTOR makes that nearly impossible until the old
8001 // vector shuffle lowering is dead.
8002 if (SDValue V2S = getScalarValueForVectorElement(
8003 V2, Mask[V2Index] - Mask.size(), DAG)) {
8004 // We need to zext the scalar if it is smaller than an i32.
8005 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8006 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8007 // Using zext to expand a narrow element won't work for non-zero
8012 // Zero-extend directly to i32.
8014 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8016 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8017 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8018 EltVT == MVT::i16) {
8019 // Either not inserting from the low element of the input or the input
8020 // element size is too small to use VZEXT_MOVL to clear the high bits.
8024 if (!IsV1Zeroable) {
8025 // If V1 can't be treated as a zero vector we have fewer options to lower
8026 // this. We can't support integer vectors or non-zero targets cheaply, and
8027 // the V1 elements can't be permuted in any way.
8028 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8029 if (!VT.isFloatingPoint() || V2Index != 0)
8031 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8032 V1Mask[V2Index] = -1;
8033 if (!isNoopShuffleMask(V1Mask))
8035 // This is essentially a special case blend operation, but if we have
8036 // general purpose blend operations, they are always faster. Bail and let
8037 // the rest of the lowering handle these as blends.
8038 if (Subtarget->hasSSE41())
8041 // Otherwise, use MOVSD or MOVSS.
8042 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8043 "Only two types of floating point element types to handle!");
8044 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8048 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8050 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8053 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8054 // the desired position. Otherwise it is more efficient to do a vector
8055 // shift left. We know that we can do a vector shift left because all
8056 // the inputs are zero.
8057 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8058 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8059 V2Shuffle[V2Index] = 0;
8060 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8062 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8064 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8066 V2Index * EltVT.getSizeInBits(),
8067 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8068 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8074 /// \brief Try to lower broadcast of a single element.
8076 /// For convenience, this code also bundles all of the subtarget feature set
8077 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8078 /// a convenient way to factor it out.
8079 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8081 const X86Subtarget *Subtarget,
8082 SelectionDAG &DAG) {
8083 if (!Subtarget->hasAVX())
8085 if (VT.isInteger() && !Subtarget->hasAVX2())
8088 // Check that the mask is a broadcast.
8089 int BroadcastIdx = -1;
8091 if (M >= 0 && BroadcastIdx == -1)
8093 else if (M >= 0 && M != BroadcastIdx)
8096 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8097 "a sorted mask where the broadcast "
8100 // Go up the chain of (vector) values to try and find a scalar load that
8101 // we can combine with the broadcast.
8103 switch (V.getOpcode()) {
8104 case ISD::CONCAT_VECTORS: {
8105 int OperandSize = Mask.size() / V.getNumOperands();
8106 V = V.getOperand(BroadcastIdx / OperandSize);
8107 BroadcastIdx %= OperandSize;
8111 case ISD::INSERT_SUBVECTOR: {
8112 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8113 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8117 int BeginIdx = (int)ConstantIdx->getZExtValue();
8119 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8120 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8121 BroadcastIdx -= BeginIdx;
8132 // Check if this is a broadcast of a scalar. We special case lowering
8133 // for scalars so that we can more effectively fold with loads.
8134 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8135 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8136 V = V.getOperand(BroadcastIdx);
8138 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8140 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8142 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8143 // We can't broadcast from a vector register w/o AVX2, and we can only
8144 // broadcast from the zero-element of a vector register.
8148 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8151 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8153 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8154 /// support for floating point shuffles but not integer shuffles. These
8155 /// instructions will incur a domain crossing penalty on some chips though so
8156 /// it is better to avoid lowering through this for integer vectors where
8158 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8159 const X86Subtarget *Subtarget,
8160 SelectionDAG &DAG) {
8162 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8163 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8164 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8165 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8166 ArrayRef<int> Mask = SVOp->getMask();
8167 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8169 if (isSingleInputShuffleMask(Mask)) {
8170 // Straight shuffle of a single input vector. Simulate this by using the
8171 // single input as both of the "inputs" to this instruction..
8172 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8174 if (Subtarget->hasAVX()) {
8175 // If we have AVX, we can use VPERMILPS which will allow folding a load
8176 // into the shuffle.
8177 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8178 DAG.getConstant(SHUFPDMask, MVT::i8));
8181 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8182 DAG.getConstant(SHUFPDMask, MVT::i8));
8184 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8185 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8187 // Use dedicated unpack instructions for masks that match their pattern.
8188 if (isShuffleEquivalent(Mask, 0, 2))
8189 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8190 if (isShuffleEquivalent(Mask, 1, 3))
8191 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8193 // If we have a single input, insert that into V1 if we can do so cheaply.
8194 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8195 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8196 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8198 // Try inverting the insertion since for v2 masks it is easy to do and we
8199 // can't reliably sort the mask one way or the other.
8200 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8201 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8202 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8203 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8207 // Try to use one of the special instruction patterns to handle two common
8208 // blend patterns if a zero-blend above didn't work.
8209 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8210 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8211 // We can either use a special instruction to load over the low double or
8212 // to move just the low double.
8214 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8216 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8218 if (Subtarget->hasSSE41())
8219 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8223 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8224 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8225 DAG.getConstant(SHUFPDMask, MVT::i8));
8228 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8230 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8231 /// the integer unit to minimize domain crossing penalties. However, for blends
8232 /// it falls back to the floating point shuffle operation with appropriate bit
8234 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8235 const X86Subtarget *Subtarget,
8236 SelectionDAG &DAG) {
8238 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8239 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8240 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8241 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8242 ArrayRef<int> Mask = SVOp->getMask();
8243 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8245 if (isSingleInputShuffleMask(Mask)) {
8246 // Check for being able to broadcast a single element.
8247 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8248 Mask, Subtarget, DAG))
8251 // Straight shuffle of a single input vector. For everything from SSE2
8252 // onward this has a single fast instruction with no scary immediates.
8253 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8254 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8255 int WidenedMask[4] = {
8256 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8257 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8259 ISD::BITCAST, DL, MVT::v2i64,
8260 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8261 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8264 // Try to use byte shift instructions.
8265 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8266 DL, MVT::v2i64, V1, V2, Mask, DAG))
8269 // If we have a single input from V2 insert that into V1 if we can do so
8271 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8272 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8273 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8275 // Try inverting the insertion since for v2 masks it is easy to do and we
8276 // can't reliably sort the mask one way or the other.
8277 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8278 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8279 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8280 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8284 // Use dedicated unpack instructions for masks that match their pattern.
8285 if (isShuffleEquivalent(Mask, 0, 2))
8286 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8287 if (isShuffleEquivalent(Mask, 1, 3))
8288 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8290 if (Subtarget->hasSSE41())
8291 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8295 // Try to use byte rotation instructions.
8296 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8297 if (Subtarget->hasSSSE3())
8298 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8299 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8302 // We implement this with SHUFPD which is pretty lame because it will likely
8303 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8304 // However, all the alternatives are still more cycles and newer chips don't
8305 // have this problem. It would be really nice if x86 had better shuffles here.
8306 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8307 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8308 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8309 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8312 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8314 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8315 /// It makes no assumptions about whether this is the *best* lowering, it simply
8317 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8318 ArrayRef<int> Mask, SDValue V1,
8319 SDValue V2, SelectionDAG &DAG) {
8320 SDValue LowV = V1, HighV = V2;
8321 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8324 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8326 if (NumV2Elements == 1) {
8328 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8331 // Compute the index adjacent to V2Index and in the same half by toggling
8333 int V2AdjIndex = V2Index ^ 1;
8335 if (Mask[V2AdjIndex] == -1) {
8336 // Handles all the cases where we have a single V2 element and an undef.
8337 // This will only ever happen in the high lanes because we commute the
8338 // vector otherwise.
8340 std::swap(LowV, HighV);
8341 NewMask[V2Index] -= 4;
8343 // Handle the case where the V2 element ends up adjacent to a V1 element.
8344 // To make this work, blend them together as the first step.
8345 int V1Index = V2AdjIndex;
8346 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8347 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8348 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8350 // Now proceed to reconstruct the final blend as we have the necessary
8351 // high or low half formed.
8358 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8359 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8361 } else if (NumV2Elements == 2) {
8362 if (Mask[0] < 4 && Mask[1] < 4) {
8363 // Handle the easy case where we have V1 in the low lanes and V2 in the
8367 } else if (Mask[2] < 4 && Mask[3] < 4) {
8368 // We also handle the reversed case because this utility may get called
8369 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8370 // arrange things in the right direction.
8376 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8377 // trying to place elements directly, just blend them and set up the final
8378 // shuffle to place them.
8380 // The first two blend mask elements are for V1, the second two are for
8382 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8383 Mask[2] < 4 ? Mask[2] : Mask[3],
8384 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8385 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8386 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8387 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8389 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8392 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8393 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8394 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8395 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8398 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8399 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8402 /// \brief Lower 4-lane 32-bit floating point shuffles.
8404 /// Uses instructions exclusively from the floating point unit to minimize
8405 /// domain crossing penalties, as these are sufficient to implement all v4f32
8407 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8408 const X86Subtarget *Subtarget,
8409 SelectionDAG &DAG) {
8411 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8412 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8413 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8414 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8415 ArrayRef<int> Mask = SVOp->getMask();
8416 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8419 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8421 if (NumV2Elements == 0) {
8422 // Check for being able to broadcast a single element.
8423 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8424 Mask, Subtarget, DAG))
8427 if (Subtarget->hasAVX()) {
8428 // If we have AVX, we can use VPERMILPS which will allow folding a load
8429 // into the shuffle.
8430 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8431 getV4X86ShuffleImm8ForMask(Mask, DAG));
8434 // Otherwise, use a straight shuffle of a single input vector. We pass the
8435 // input vector to both operands to simulate this with a SHUFPS.
8436 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8437 getV4X86ShuffleImm8ForMask(Mask, DAG));
8440 // Use dedicated unpack instructions for masks that match their pattern.
8441 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8442 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8443 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8444 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8446 // There are special ways we can lower some single-element blends. However, we
8447 // have custom ways we can lower more complex single-element blends below that
8448 // we defer to if both this and BLENDPS fail to match, so restrict this to
8449 // when the V2 input is targeting element 0 of the mask -- that is the fast
8451 if (NumV2Elements == 1 && Mask[0] >= 4)
8452 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8453 Mask, Subtarget, DAG))
8456 if (Subtarget->hasSSE41())
8457 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8461 // Check for whether we can use INSERTPS to perform the blend. We only use
8462 // INSERTPS when the V1 elements are already in the correct locations
8463 // because otherwise we can just always use two SHUFPS instructions which
8464 // are much smaller to encode than a SHUFPS and an INSERTPS.
8465 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8467 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8470 // When using INSERTPS we can zero any lane of the destination. Collect
8471 // the zero inputs into a mask and drop them from the lanes of V1 which
8472 // actually need to be present as inputs to the INSERTPS.
8473 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8475 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8476 bool InsertNeedsShuffle = false;
8478 for (int i = 0; i < 4; ++i)
8482 } else if (Mask[i] != i) {
8483 InsertNeedsShuffle = true;
8488 // We don't want to use INSERTPS or other insertion techniques if it will
8489 // require shuffling anyways.
8490 if (!InsertNeedsShuffle) {
8491 // If all of V1 is zeroable, replace it with undef.
8492 if ((ZMask | 1 << V2Index) == 0xF)
8493 V1 = DAG.getUNDEF(MVT::v4f32);
8495 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8496 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8498 // Insert the V2 element into the desired position.
8499 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8500 DAG.getConstant(InsertPSMask, MVT::i8));
8504 // Otherwise fall back to a SHUFPS lowering strategy.
8505 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8508 /// \brief Lower 4-lane i32 vector shuffles.
8510 /// We try to handle these with integer-domain shuffles where we can, but for
8511 /// blends we use the floating point domain blend instructions.
8512 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8513 const X86Subtarget *Subtarget,
8514 SelectionDAG &DAG) {
8516 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8517 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8518 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8519 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8520 ArrayRef<int> Mask = SVOp->getMask();
8521 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8523 // Whenever we can lower this as a zext, that instruction is strictly faster
8524 // than any alternative. It also allows us to fold memory operands into the
8525 // shuffle in many cases.
8526 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8527 Mask, Subtarget, DAG))
8531 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8533 if (NumV2Elements == 0) {
8534 // Check for being able to broadcast a single element.
8535 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8536 Mask, Subtarget, DAG))
8539 // Straight shuffle of a single input vector. For everything from SSE2
8540 // onward this has a single fast instruction with no scary immediates.
8541 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8542 // but we aren't actually going to use the UNPCK instruction because doing
8543 // so prevents folding a load into this instruction or making a copy.
8544 const int UnpackLoMask[] = {0, 0, 1, 1};
8545 const int UnpackHiMask[] = {2, 2, 3, 3};
8546 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8547 Mask = UnpackLoMask;
8548 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8549 Mask = UnpackHiMask;
8551 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8552 getV4X86ShuffleImm8ForMask(Mask, DAG));
8555 // Try to use byte shift instructions.
8556 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8557 DL, MVT::v4i32, V1, V2, Mask, DAG))
8560 // There are special ways we can lower some single-element blends.
8561 if (NumV2Elements == 1)
8562 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8563 Mask, Subtarget, DAG))
8566 // Use dedicated unpack instructions for masks that match their pattern.
8567 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8568 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8569 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8570 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8572 if (Subtarget->hasSSE41())
8573 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8577 // Try to use byte rotation instructions.
8578 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8579 if (Subtarget->hasSSSE3())
8580 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8581 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8584 // We implement this with SHUFPS because it can blend from two vectors.
8585 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8586 // up the inputs, bypassing domain shift penalties that we would encur if we
8587 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8589 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8590 DAG.getVectorShuffle(
8592 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8593 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8596 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8597 /// shuffle lowering, and the most complex part.
8599 /// The lowering strategy is to try to form pairs of input lanes which are
8600 /// targeted at the same half of the final vector, and then use a dword shuffle
8601 /// to place them onto the right half, and finally unpack the paired lanes into
8602 /// their final position.
8604 /// The exact breakdown of how to form these dword pairs and align them on the
8605 /// correct sides is really tricky. See the comments within the function for
8606 /// more of the details.
8607 static SDValue lowerV8I16SingleInputVectorShuffle(
8608 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8609 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8610 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8611 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8612 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8614 SmallVector<int, 4> LoInputs;
8615 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8616 [](int M) { return M >= 0; });
8617 std::sort(LoInputs.begin(), LoInputs.end());
8618 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8619 SmallVector<int, 4> HiInputs;
8620 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8621 [](int M) { return M >= 0; });
8622 std::sort(HiInputs.begin(), HiInputs.end());
8623 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8625 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8626 int NumHToL = LoInputs.size() - NumLToL;
8628 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8629 int NumHToH = HiInputs.size() - NumLToH;
8630 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8631 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8632 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8633 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8635 // Check for being able to broadcast a single element.
8636 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8637 Mask, Subtarget, DAG))
8640 // Try to use byte shift instructions.
8641 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8642 DL, MVT::v8i16, V, V, Mask, DAG))
8645 // Use dedicated unpack instructions for masks that match their pattern.
8646 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8647 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8648 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8649 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8651 // Try to use byte rotation instructions.
8652 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8653 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8656 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8657 // such inputs we can swap two of the dwords across the half mark and end up
8658 // with <=2 inputs to each half in each half. Once there, we can fall through
8659 // to the generic code below. For example:
8661 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8662 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8664 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8665 // and an existing 2-into-2 on the other half. In this case we may have to
8666 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8667 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8668 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8669 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8670 // half than the one we target for fixing) will be fixed when we re-enter this
8671 // path. We will also combine away any sequence of PSHUFD instructions that
8672 // result into a single instruction. Here is an example of the tricky case:
8674 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8675 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8677 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8679 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8680 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8682 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8683 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8685 // The result is fine to be handled by the generic logic.
8686 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8687 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8688 int AOffset, int BOffset) {
8689 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8690 "Must call this with A having 3 or 1 inputs from the A half.");
8691 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8692 "Must call this with B having 1 or 3 inputs from the B half.");
8693 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8694 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8696 // Compute the index of dword with only one word among the three inputs in
8697 // a half by taking the sum of the half with three inputs and subtracting
8698 // the sum of the actual three inputs. The difference is the remaining
8701 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8702 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8703 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8704 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8705 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8706 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8707 int TripleNonInputIdx =
8708 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8709 TripleDWord = TripleNonInputIdx / 2;
8711 // We use xor with one to compute the adjacent DWord to whichever one the
8713 OneInputDWord = (OneInput / 2) ^ 1;
8715 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8716 // and BToA inputs. If there is also such a problem with the BToB and AToB
8717 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8718 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8719 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8720 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8721 // Compute how many inputs will be flipped by swapping these DWords. We
8723 // to balance this to ensure we don't form a 3-1 shuffle in the other
8725 int NumFlippedAToBInputs =
8726 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8727 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8728 int NumFlippedBToBInputs =
8729 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8730 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8731 if ((NumFlippedAToBInputs == 1 &&
8732 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8733 (NumFlippedBToBInputs == 1 &&
8734 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8735 // We choose whether to fix the A half or B half based on whether that
8736 // half has zero flipped inputs. At zero, we may not be able to fix it
8737 // with that half. We also bias towards fixing the B half because that
8738 // will more commonly be the high half, and we have to bias one way.
8739 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8740 ArrayRef<int> Inputs) {
8741 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8742 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8743 PinnedIdx ^ 1) != Inputs.end();
8744 // Determine whether the free index is in the flipped dword or the
8745 // unflipped dword based on where the pinned index is. We use this bit
8746 // in an xor to conditionally select the adjacent dword.
8747 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8748 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8749 FixFreeIdx) != Inputs.end();
8750 if (IsFixIdxInput == IsFixFreeIdxInput)
8752 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8753 FixFreeIdx) != Inputs.end();
8754 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8755 "We need to be changing the number of flipped inputs!");
8756 int PSHUFHalfMask[] = {0, 1, 2, 3};
8757 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8758 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8760 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8763 if (M != -1 && M == FixIdx)
8765 else if (M != -1 && M == FixFreeIdx)
8768 if (NumFlippedBToBInputs != 0) {
8770 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8771 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8773 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8775 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8776 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8781 int PSHUFDMask[] = {0, 1, 2, 3};
8782 PSHUFDMask[ADWord] = BDWord;
8783 PSHUFDMask[BDWord] = ADWord;
8784 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8785 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8786 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8787 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8789 // Adjust the mask to match the new locations of A and B.
8791 if (M != -1 && M/2 == ADWord)
8792 M = 2 * BDWord + M % 2;
8793 else if (M != -1 && M/2 == BDWord)
8794 M = 2 * ADWord + M % 2;
8796 // Recurse back into this routine to re-compute state now that this isn't
8797 // a 3 and 1 problem.
8798 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8801 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8802 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8803 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8804 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8806 // At this point there are at most two inputs to the low and high halves from
8807 // each half. That means the inputs can always be grouped into dwords and
8808 // those dwords can then be moved to the correct half with a dword shuffle.
8809 // We use at most one low and one high word shuffle to collect these paired
8810 // inputs into dwords, and finally a dword shuffle to place them.
8811 int PSHUFLMask[4] = {-1, -1, -1, -1};
8812 int PSHUFHMask[4] = {-1, -1, -1, -1};
8813 int PSHUFDMask[4] = {-1, -1, -1, -1};
8815 // First fix the masks for all the inputs that are staying in their
8816 // original halves. This will then dictate the targets of the cross-half
8818 auto fixInPlaceInputs =
8819 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8820 MutableArrayRef<int> SourceHalfMask,
8821 MutableArrayRef<int> HalfMask, int HalfOffset) {
8822 if (InPlaceInputs.empty())
8824 if (InPlaceInputs.size() == 1) {
8825 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8826 InPlaceInputs[0] - HalfOffset;
8827 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8830 if (IncomingInputs.empty()) {
8831 // Just fix all of the in place inputs.
8832 for (int Input : InPlaceInputs) {
8833 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8834 PSHUFDMask[Input / 2] = Input / 2;
8839 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8840 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8841 InPlaceInputs[0] - HalfOffset;
8842 // Put the second input next to the first so that they are packed into
8843 // a dword. We find the adjacent index by toggling the low bit.
8844 int AdjIndex = InPlaceInputs[0] ^ 1;
8845 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8846 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8847 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8849 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8850 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8852 // Now gather the cross-half inputs and place them into a free dword of
8853 // their target half.
8854 // FIXME: This operation could almost certainly be simplified dramatically to
8855 // look more like the 3-1 fixing operation.
8856 auto moveInputsToRightHalf = [&PSHUFDMask](
8857 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8858 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8859 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8861 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8862 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8864 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8866 int LowWord = Word & ~1;
8867 int HighWord = Word | 1;
8868 return isWordClobbered(SourceHalfMask, LowWord) ||
8869 isWordClobbered(SourceHalfMask, HighWord);
8872 if (IncomingInputs.empty())
8875 if (ExistingInputs.empty()) {
8876 // Map any dwords with inputs from them into the right half.
8877 for (int Input : IncomingInputs) {
8878 // If the source half mask maps over the inputs, turn those into
8879 // swaps and use the swapped lane.
8880 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8881 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8882 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8883 Input - SourceOffset;
8884 // We have to swap the uses in our half mask in one sweep.
8885 for (int &M : HalfMask)
8886 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8888 else if (M == Input)
8889 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8891 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8892 Input - SourceOffset &&
8893 "Previous placement doesn't match!");
8895 // Note that this correctly re-maps both when we do a swap and when
8896 // we observe the other side of the swap above. We rely on that to
8897 // avoid swapping the members of the input list directly.
8898 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8901 // Map the input's dword into the correct half.
8902 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8903 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8905 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8907 "Previous placement doesn't match!");
8910 // And just directly shift any other-half mask elements to be same-half
8911 // as we will have mirrored the dword containing the element into the
8912 // same position within that half.
8913 for (int &M : HalfMask)
8914 if (M >= SourceOffset && M < SourceOffset + 4) {
8915 M = M - SourceOffset + DestOffset;
8916 assert(M >= 0 && "This should never wrap below zero!");
8921 // Ensure we have the input in a viable dword of its current half. This
8922 // is particularly tricky because the original position may be clobbered
8923 // by inputs being moved and *staying* in that half.
8924 if (IncomingInputs.size() == 1) {
8925 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8926 int InputFixed = std::find(std::begin(SourceHalfMask),
8927 std::end(SourceHalfMask), -1) -
8928 std::begin(SourceHalfMask) + SourceOffset;
8929 SourceHalfMask[InputFixed - SourceOffset] =
8930 IncomingInputs[0] - SourceOffset;
8931 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8933 IncomingInputs[0] = InputFixed;
8935 } else if (IncomingInputs.size() == 2) {
8936 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8937 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8938 // We have two non-adjacent or clobbered inputs we need to extract from
8939 // the source half. To do this, we need to map them into some adjacent
8940 // dword slot in the source mask.
8941 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8942 IncomingInputs[1] - SourceOffset};
8944 // If there is a free slot in the source half mask adjacent to one of
8945 // the inputs, place the other input in it. We use (Index XOR 1) to
8946 // compute an adjacent index.
8947 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8948 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8949 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8950 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8951 InputsFixed[1] = InputsFixed[0] ^ 1;
8952 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8953 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8954 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8955 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8956 InputsFixed[0] = InputsFixed[1] ^ 1;
8957 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8958 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8959 // The two inputs are in the same DWord but it is clobbered and the
8960 // adjacent DWord isn't used at all. Move both inputs to the free
8962 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8963 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8964 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8965 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8967 // The only way we hit this point is if there is no clobbering
8968 // (because there are no off-half inputs to this half) and there is no
8969 // free slot adjacent to one of the inputs. In this case, we have to
8970 // swap an input with a non-input.
8971 for (int i = 0; i < 4; ++i)
8972 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8973 "We can't handle any clobbers here!");
8974 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8975 "Cannot have adjacent inputs here!");
8977 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8978 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8980 // We also have to update the final source mask in this case because
8981 // it may need to undo the above swap.
8982 for (int &M : FinalSourceHalfMask)
8983 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8984 M = InputsFixed[1] + SourceOffset;
8985 else if (M == InputsFixed[1] + SourceOffset)
8986 M = (InputsFixed[0] ^ 1) + SourceOffset;
8988 InputsFixed[1] = InputsFixed[0] ^ 1;
8991 // Point everything at the fixed inputs.
8992 for (int &M : HalfMask)
8993 if (M == IncomingInputs[0])
8994 M = InputsFixed[0] + SourceOffset;
8995 else if (M == IncomingInputs[1])
8996 M = InputsFixed[1] + SourceOffset;
8998 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8999 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9002 llvm_unreachable("Unhandled input size!");
9005 // Now hoist the DWord down to the right half.
9006 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9007 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9008 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9009 for (int &M : HalfMask)
9010 for (int Input : IncomingInputs)
9012 M = FreeDWord * 2 + Input % 2;
9014 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9015 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9016 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9017 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9019 // Now enact all the shuffles we've computed to move the inputs into their
9021 if (!isNoopShuffleMask(PSHUFLMask))
9022 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9023 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9024 if (!isNoopShuffleMask(PSHUFHMask))
9025 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9026 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9027 if (!isNoopShuffleMask(PSHUFDMask))
9028 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9029 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9030 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9031 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9033 // At this point, each half should contain all its inputs, and we can then
9034 // just shuffle them into their final position.
9035 assert(std::count_if(LoMask.begin(), LoMask.end(),
9036 [](int M) { return M >= 4; }) == 0 &&
9037 "Failed to lift all the high half inputs to the low mask!");
9038 assert(std::count_if(HiMask.begin(), HiMask.end(),
9039 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9040 "Failed to lift all the low half inputs to the high mask!");
9042 // Do a half shuffle for the low mask.
9043 if (!isNoopShuffleMask(LoMask))
9044 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9045 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9047 // Do a half shuffle with the high mask after shifting its values down.
9048 for (int &M : HiMask)
9051 if (!isNoopShuffleMask(HiMask))
9052 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9053 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9058 /// \brief Detect whether the mask pattern should be lowered through
9061 /// This essentially tests whether viewing the mask as an interleaving of two
9062 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9063 /// lowering it through interleaving is a significantly better strategy.
9064 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9065 int NumEvenInputs[2] = {0, 0};
9066 int NumOddInputs[2] = {0, 0};
9067 int NumLoInputs[2] = {0, 0};
9068 int NumHiInputs[2] = {0, 0};
9069 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9073 int InputIdx = Mask[i] >= Size;
9076 ++NumLoInputs[InputIdx];
9078 ++NumHiInputs[InputIdx];
9081 ++NumEvenInputs[InputIdx];
9083 ++NumOddInputs[InputIdx];
9086 // The minimum number of cross-input results for both the interleaved and
9087 // split cases. If interleaving results in fewer cross-input results, return
9089 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9090 NumEvenInputs[0] + NumOddInputs[1]);
9091 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9092 NumLoInputs[0] + NumHiInputs[1]);
9093 return InterleavedCrosses < SplitCrosses;
9096 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9098 /// This strategy only works when the inputs from each vector fit into a single
9099 /// half of that vector, and generally there are not so many inputs as to leave
9100 /// the in-place shuffles required highly constrained (and thus expensive). It
9101 /// shifts all the inputs into a single side of both input vectors and then
9102 /// uses an unpack to interleave these inputs in a single vector. At that
9103 /// point, we will fall back on the generic single input shuffle lowering.
9104 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9106 MutableArrayRef<int> Mask,
9107 const X86Subtarget *Subtarget,
9108 SelectionDAG &DAG) {
9109 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9110 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9111 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9112 for (int i = 0; i < 8; ++i)
9113 if (Mask[i] >= 0 && Mask[i] < 4)
9114 LoV1Inputs.push_back(i);
9115 else if (Mask[i] >= 4 && Mask[i] < 8)
9116 HiV1Inputs.push_back(i);
9117 else if (Mask[i] >= 8 && Mask[i] < 12)
9118 LoV2Inputs.push_back(i);
9119 else if (Mask[i] >= 12)
9120 HiV2Inputs.push_back(i);
9122 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9123 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9126 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9127 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9128 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9130 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9131 HiV1Inputs.size() + HiV2Inputs.size();
9133 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9134 ArrayRef<int> HiInputs, bool MoveToLo,
9136 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9137 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9138 if (BadInputs.empty())
9141 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9142 int MoveOffset = MoveToLo ? 0 : 4;
9144 if (GoodInputs.empty()) {
9145 for (int BadInput : BadInputs) {
9146 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9147 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9150 if (GoodInputs.size() == 2) {
9151 // If the low inputs are spread across two dwords, pack them into
9153 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9154 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9155 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9156 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9158 // Otherwise pin the good inputs.
9159 for (int GoodInput : GoodInputs)
9160 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9163 if (BadInputs.size() == 2) {
9164 // If we have two bad inputs then there may be either one or two good
9165 // inputs fixed in place. Find a fixed input, and then find the *other*
9166 // two adjacent indices by using modular arithmetic.
9168 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9169 [](int M) { return M >= 0; }) -
9170 std::begin(MoveMask);
9172 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9173 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9174 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9175 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9176 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9177 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9178 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9180 assert(BadInputs.size() == 1 && "All sizes handled");
9181 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9182 std::end(MoveMask), -1) -
9183 std::begin(MoveMask);
9184 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9185 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9189 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9192 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9194 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9197 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9198 // cross-half traffic in the final shuffle.
9200 // Munge the mask to be a single-input mask after the unpack merges the
9204 M = 2 * (M % 4) + (M / 8);
9206 return DAG.getVectorShuffle(
9207 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9208 DL, MVT::v8i16, V1, V2),
9209 DAG.getUNDEF(MVT::v8i16), Mask);
9212 /// \brief Generic lowering of 8-lane i16 shuffles.
9214 /// This handles both single-input shuffles and combined shuffle/blends with
9215 /// two inputs. The single input shuffles are immediately delegated to
9216 /// a dedicated lowering routine.
9218 /// The blends are lowered in one of three fundamental ways. If there are few
9219 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9220 /// of the input is significantly cheaper when lowered as an interleaving of
9221 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9222 /// halves of the inputs separately (making them have relatively few inputs)
9223 /// and then concatenate them.
9224 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9225 const X86Subtarget *Subtarget,
9226 SelectionDAG &DAG) {
9228 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9229 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9230 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9231 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9232 ArrayRef<int> OrigMask = SVOp->getMask();
9233 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9234 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9235 MutableArrayRef<int> Mask(MaskStorage);
9237 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9239 // Whenever we can lower this as a zext, that instruction is strictly faster
9240 // than any alternative.
9241 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9242 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9245 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9246 auto isV2 = [](int M) { return M >= 8; };
9248 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9249 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9251 if (NumV2Inputs == 0)
9252 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9254 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9255 "to be V1-input shuffles.");
9257 // Try to use byte shift instructions.
9258 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9259 DL, MVT::v8i16, V1, V2, Mask, DAG))
9262 // There are special ways we can lower some single-element blends.
9263 if (NumV2Inputs == 1)
9264 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9265 Mask, Subtarget, DAG))
9268 // Use dedicated unpack instructions for masks that match their pattern.
9269 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9270 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9271 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9272 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9274 if (Subtarget->hasSSE41())
9275 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9279 // Try to use byte rotation instructions.
9280 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9281 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9284 if (NumV1Inputs + NumV2Inputs <= 4)
9285 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9287 // Check whether an interleaving lowering is likely to be more efficient.
9288 // This isn't perfect but it is a strong heuristic that tends to work well on
9289 // the kinds of shuffles that show up in practice.
9291 // FIXME: Handle 1x, 2x, and 4x interleaving.
9292 if (shouldLowerAsInterleaving(Mask)) {
9293 // FIXME: Figure out whether we should pack these into the low or high
9296 int EMask[8], OMask[8];
9297 for (int i = 0; i < 4; ++i) {
9298 EMask[i] = Mask[2*i];
9299 OMask[i] = Mask[2*i + 1];
9304 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9305 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9307 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9310 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9311 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9313 for (int i = 0; i < 4; ++i) {
9314 LoBlendMask[i] = Mask[i];
9315 HiBlendMask[i] = Mask[i + 4];
9318 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9319 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9320 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9321 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9323 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9324 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9327 /// \brief Check whether a compaction lowering can be done by dropping even
9328 /// elements and compute how many times even elements must be dropped.
9330 /// This handles shuffles which take every Nth element where N is a power of
9331 /// two. Example shuffle masks:
9333 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9334 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9335 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9336 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9337 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9338 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9340 /// Any of these lanes can of course be undef.
9342 /// This routine only supports N <= 3.
9343 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9346 /// \returns N above, or the number of times even elements must be dropped if
9347 /// there is such a number. Otherwise returns zero.
9348 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9349 // Figure out whether we're looping over two inputs or just one.
9350 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9352 // The modulus for the shuffle vector entries is based on whether this is
9353 // a single input or not.
9354 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9355 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9356 "We should only be called with masks with a power-of-2 size!");
9358 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9360 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9361 // and 2^3 simultaneously. This is because we may have ambiguity with
9362 // partially undef inputs.
9363 bool ViableForN[3] = {true, true, true};
9365 for (int i = 0, e = Mask.size(); i < e; ++i) {
9366 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9371 bool IsAnyViable = false;
9372 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9373 if (ViableForN[j]) {
9376 // The shuffle mask must be equal to (i * 2^N) % M.
9377 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9380 ViableForN[j] = false;
9382 // Early exit if we exhaust the possible powers of two.
9387 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9391 // Return 0 as there is no viable power of two.
9395 /// \brief Generic lowering of v16i8 shuffles.
9397 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9398 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9399 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9400 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9402 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9403 const X86Subtarget *Subtarget,
9404 SelectionDAG &DAG) {
9406 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9407 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9408 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9409 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9410 ArrayRef<int> OrigMask = SVOp->getMask();
9411 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9413 // Try to use byte shift instructions.
9414 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9415 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9418 // Try to use byte rotation instructions.
9419 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9420 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9423 // Try to use a zext lowering.
9424 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9425 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9428 int MaskStorage[16] = {
9429 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9430 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9431 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9432 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9433 MutableArrayRef<int> Mask(MaskStorage);
9434 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9435 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9438 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9440 // For single-input shuffles, there are some nicer lowering tricks we can use.
9441 if (NumV2Elements == 0) {
9442 // Check for being able to broadcast a single element.
9443 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9444 Mask, Subtarget, DAG))
9447 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9448 // Notably, this handles splat and partial-splat shuffles more efficiently.
9449 // However, it only makes sense if the pre-duplication shuffle simplifies
9450 // things significantly. Currently, this means we need to be able to
9451 // express the pre-duplication shuffle as an i16 shuffle.
9453 // FIXME: We should check for other patterns which can be widened into an
9454 // i16 shuffle as well.
9455 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9456 for (int i = 0; i < 16; i += 2)
9457 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9462 auto tryToWidenViaDuplication = [&]() -> SDValue {
9463 if (!canWidenViaDuplication(Mask))
9465 SmallVector<int, 4> LoInputs;
9466 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9467 [](int M) { return M >= 0 && M < 8; });
9468 std::sort(LoInputs.begin(), LoInputs.end());
9469 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9471 SmallVector<int, 4> HiInputs;
9472 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9473 [](int M) { return M >= 8; });
9474 std::sort(HiInputs.begin(), HiInputs.end());
9475 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9478 bool TargetLo = LoInputs.size() >= HiInputs.size();
9479 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9480 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9482 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9483 SmallDenseMap<int, int, 8> LaneMap;
9484 for (int I : InPlaceInputs) {
9485 PreDupI16Shuffle[I/2] = I/2;
9488 int j = TargetLo ? 0 : 4, je = j + 4;
9489 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9490 // Check if j is already a shuffle of this input. This happens when
9491 // there are two adjacent bytes after we move the low one.
9492 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9493 // If we haven't yet mapped the input, search for a slot into which
9495 while (j < je && PreDupI16Shuffle[j] != -1)
9499 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9502 // Map this input with the i16 shuffle.
9503 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9506 // Update the lane map based on the mapping we ended up with.
9507 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9510 ISD::BITCAST, DL, MVT::v16i8,
9511 DAG.getVectorShuffle(MVT::v8i16, DL,
9512 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9513 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9515 // Unpack the bytes to form the i16s that will be shuffled into place.
9516 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9517 MVT::v16i8, V1, V1);
9519 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9520 for (int i = 0; i < 16; ++i)
9521 if (Mask[i] != -1) {
9522 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9523 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9524 if (PostDupI16Shuffle[i / 2] == -1)
9525 PostDupI16Shuffle[i / 2] = MappedMask;
9527 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9528 "Conflicting entrties in the original shuffle!");
9531 ISD::BITCAST, DL, MVT::v16i8,
9532 DAG.getVectorShuffle(MVT::v8i16, DL,
9533 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9534 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9536 if (SDValue V = tryToWidenViaDuplication())
9540 // Check whether an interleaving lowering is likely to be more efficient.
9541 // This isn't perfect but it is a strong heuristic that tends to work well on
9542 // the kinds of shuffles that show up in practice.
9544 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9545 if (shouldLowerAsInterleaving(Mask)) {
9546 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9547 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9549 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9550 return (M >= 8 && M < 16) || M >= 24;
9552 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9553 -1, -1, -1, -1, -1, -1, -1, -1};
9554 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9555 -1, -1, -1, -1, -1, -1, -1, -1};
9556 bool UnpackLo = NumLoHalf >= NumHiHalf;
9557 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9558 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9559 for (int i = 0; i < 8; ++i) {
9560 TargetEMask[i] = Mask[2 * i];
9561 TargetOMask[i] = Mask[2 * i + 1];
9564 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9565 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9567 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9568 MVT::v16i8, Evens, Odds);
9571 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9572 // with PSHUFB. It is important to do this before we attempt to generate any
9573 // blends but after all of the single-input lowerings. If the single input
9574 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9575 // want to preserve that and we can DAG combine any longer sequences into
9576 // a PSHUFB in the end. But once we start blending from multiple inputs,
9577 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9578 // and there are *very* few patterns that would actually be faster than the
9579 // PSHUFB approach because of its ability to zero lanes.
9581 // FIXME: The only exceptions to the above are blends which are exact
9582 // interleavings with direct instructions supporting them. We currently don't
9583 // handle those well here.
9584 if (Subtarget->hasSSSE3()) {
9587 for (int i = 0; i < 16; ++i)
9588 if (Mask[i] == -1) {
9589 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9591 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9593 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9595 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9596 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9597 if (isSingleInputShuffleMask(Mask))
9598 return V1; // Single inputs are easy.
9600 // Otherwise, blend the two.
9601 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9602 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9603 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9606 // There are special ways we can lower some single-element blends.
9607 if (NumV2Elements == 1)
9608 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9609 Mask, Subtarget, DAG))
9612 // Check whether a compaction lowering can be done. This handles shuffles
9613 // which take every Nth element for some even N. See the helper function for
9616 // We special case these as they can be particularly efficiently handled with
9617 // the PACKUSB instruction on x86 and they show up in common patterns of
9618 // rearranging bytes to truncate wide elements.
9619 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9620 // NumEvenDrops is the power of two stride of the elements. Another way of
9621 // thinking about it is that we need to drop the even elements this many
9622 // times to get the original input.
9623 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9625 // First we need to zero all the dropped bytes.
9626 assert(NumEvenDrops <= 3 &&
9627 "No support for dropping even elements more than 3 times.");
9628 // We use the mask type to pick which bytes are preserved based on how many
9629 // elements are dropped.
9630 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9631 SDValue ByteClearMask =
9632 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9633 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9634 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9636 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9638 // Now pack things back together.
9639 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9640 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9641 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9642 for (int i = 1; i < NumEvenDrops; ++i) {
9643 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9644 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9650 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9651 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9652 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9653 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9655 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9656 MutableArrayRef<int> V1HalfBlendMask,
9657 MutableArrayRef<int> V2HalfBlendMask) {
9658 for (int i = 0; i < 8; ++i)
9659 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9660 V1HalfBlendMask[i] = HalfMask[i];
9662 } else if (HalfMask[i] >= 16) {
9663 V2HalfBlendMask[i] = HalfMask[i] - 16;
9664 HalfMask[i] = i + 8;
9667 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9668 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9670 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9672 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9673 MutableArrayRef<int> HiBlendMask) {
9675 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9676 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9678 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9679 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9680 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9681 [](int M) { return M >= 0 && M % 2 == 1; })) {
9682 // Use a mask to drop the high bytes.
9683 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9684 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9685 DAG.getConstant(0x00FF, MVT::v8i16));
9687 // This will be a single vector shuffle instead of a blend so nuke V2.
9688 V2 = DAG.getUNDEF(MVT::v8i16);
9690 // Squash the masks to point directly into V1.
9691 for (int &M : LoBlendMask)
9694 for (int &M : HiBlendMask)
9698 // Otherwise just unpack the low half of V into V1 and the high half into
9699 // V2 so that we can blend them as i16s.
9700 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9701 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9702 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9703 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9706 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9707 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9708 return std::make_pair(BlendedLo, BlendedHi);
9710 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9711 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9712 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9714 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9715 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9717 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9720 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9722 /// This routine breaks down the specific type of 128-bit shuffle and
9723 /// dispatches to the lowering routines accordingly.
9724 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9725 MVT VT, const X86Subtarget *Subtarget,
9726 SelectionDAG &DAG) {
9727 switch (VT.SimpleTy) {
9729 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9731 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9733 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9735 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9737 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9739 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9742 llvm_unreachable("Unimplemented!");
9746 /// \brief Helper function to test whether a shuffle mask could be
9747 /// simplified by widening the elements being shuffled.
9749 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9750 /// leaves it in an unspecified state.
9752 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9753 /// shuffle masks. The latter have the special property of a '-2' representing
9754 /// a zero-ed lane of a vector.
9755 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9756 SmallVectorImpl<int> &WidenedMask) {
9757 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9758 // If both elements are undef, its trivial.
9759 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9760 WidenedMask.push_back(SM_SentinelUndef);
9764 // Check for an undef mask and a mask value properly aligned to fit with
9765 // a pair of values. If we find such a case, use the non-undef mask's value.
9766 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9767 WidenedMask.push_back(Mask[i + 1] / 2);
9770 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9771 WidenedMask.push_back(Mask[i] / 2);
9775 // When zeroing, we need to spread the zeroing across both lanes to widen.
9776 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9777 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9778 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9779 WidenedMask.push_back(SM_SentinelZero);
9785 // Finally check if the two mask values are adjacent and aligned with
9787 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9788 WidenedMask.push_back(Mask[i] / 2);
9792 // Otherwise we can't safely widen the elements used in this shuffle.
9795 assert(WidenedMask.size() == Mask.size() / 2 &&
9796 "Incorrect size of mask after widening the elements!");
9801 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9803 /// This routine just extracts two subvectors, shuffles them independently, and
9804 /// then concatenates them back together. This should work effectively with all
9805 /// AVX vector shuffle types.
9806 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9807 SDValue V2, ArrayRef<int> Mask,
9808 SelectionDAG &DAG) {
9809 assert(VT.getSizeInBits() >= 256 &&
9810 "Only for 256-bit or wider vector shuffles!");
9811 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9812 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9814 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9815 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9817 int NumElements = VT.getVectorNumElements();
9818 int SplitNumElements = NumElements / 2;
9819 MVT ScalarVT = VT.getScalarType();
9820 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9822 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9823 DAG.getIntPtrConstant(0));
9824 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9825 DAG.getIntPtrConstant(SplitNumElements));
9826 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9827 DAG.getIntPtrConstant(0));
9828 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9829 DAG.getIntPtrConstant(SplitNumElements));
9831 // Now create two 4-way blends of these half-width vectors.
9832 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9833 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9834 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9835 for (int i = 0; i < SplitNumElements; ++i) {
9836 int M = HalfMask[i];
9837 if (M >= NumElements) {
9838 if (M >= NumElements + SplitNumElements)
9842 V2BlendMask.push_back(M - NumElements);
9843 V1BlendMask.push_back(-1);
9844 BlendMask.push_back(SplitNumElements + i);
9845 } else if (M >= 0) {
9846 if (M >= SplitNumElements)
9850 V2BlendMask.push_back(-1);
9851 V1BlendMask.push_back(M);
9852 BlendMask.push_back(i);
9854 V2BlendMask.push_back(-1);
9855 V1BlendMask.push_back(-1);
9856 BlendMask.push_back(-1);
9860 // Because the lowering happens after all combining takes place, we need to
9861 // manually combine these blend masks as much as possible so that we create
9862 // a minimal number of high-level vector shuffle nodes.
9864 // First try just blending the halves of V1 or V2.
9865 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9866 return DAG.getUNDEF(SplitVT);
9867 if (!UseLoV2 && !UseHiV2)
9868 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9869 if (!UseLoV1 && !UseHiV1)
9870 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9872 SDValue V1Blend, V2Blend;
9873 if (UseLoV1 && UseHiV1) {
9875 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9877 // We only use half of V1 so map the usage down into the final blend mask.
9878 V1Blend = UseLoV1 ? LoV1 : HiV1;
9879 for (int i = 0; i < SplitNumElements; ++i)
9880 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9881 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9883 if (UseLoV2 && UseHiV2) {
9885 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9887 // We only use half of V2 so map the usage down into the final blend mask.
9888 V2Blend = UseLoV2 ? LoV2 : HiV2;
9889 for (int i = 0; i < SplitNumElements; ++i)
9890 if (BlendMask[i] >= SplitNumElements)
9891 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9893 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9895 SDValue Lo = HalfBlend(LoMask);
9896 SDValue Hi = HalfBlend(HiMask);
9897 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9900 /// \brief Either split a vector in halves or decompose the shuffles and the
9903 /// This is provided as a good fallback for many lowerings of non-single-input
9904 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9905 /// between splitting the shuffle into 128-bit components and stitching those
9906 /// back together vs. extracting the single-input shuffles and blending those
9908 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9909 SDValue V2, ArrayRef<int> Mask,
9910 SelectionDAG &DAG) {
9911 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9912 "lower single-input shuffles as it "
9913 "could then recurse on itself.");
9914 int Size = Mask.size();
9916 // If this can be modeled as a broadcast of two elements followed by a blend,
9917 // prefer that lowering. This is especially important because broadcasts can
9918 // often fold with memory operands.
9919 auto DoBothBroadcast = [&] {
9920 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9923 if (V2BroadcastIdx == -1)
9924 V2BroadcastIdx = M - Size;
9925 else if (M - Size != V2BroadcastIdx)
9927 } else if (M >= 0) {
9928 if (V1BroadcastIdx == -1)
9930 else if (M != V1BroadcastIdx)
9935 if (DoBothBroadcast())
9936 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9939 // If the inputs all stem from a single 128-bit lane of each input, then we
9940 // split them rather than blending because the split will decompose to
9941 // unusually few instructions.
9942 int LaneCount = VT.getSizeInBits() / 128;
9943 int LaneSize = Size / LaneCount;
9944 SmallBitVector LaneInputs[2];
9945 LaneInputs[0].resize(LaneCount, false);
9946 LaneInputs[1].resize(LaneCount, false);
9947 for (int i = 0; i < Size; ++i)
9949 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9950 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9951 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9953 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9954 // that the decomposed single-input shuffles don't end up here.
9955 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9958 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9959 /// a permutation and blend of those lanes.
9961 /// This essentially blends the out-of-lane inputs to each lane into the lane
9962 /// from a permuted copy of the vector. This lowering strategy results in four
9963 /// instructions in the worst case for a single-input cross lane shuffle which
9964 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9965 /// of. Special cases for each particular shuffle pattern should be handled
9966 /// prior to trying this lowering.
9967 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9968 SDValue V1, SDValue V2,
9970 SelectionDAG &DAG) {
9971 // FIXME: This should probably be generalized for 512-bit vectors as well.
9972 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9973 int LaneSize = Mask.size() / 2;
9975 // If there are only inputs from one 128-bit lane, splitting will in fact be
9976 // less expensive. The flags track wether the given lane contains an element
9977 // that crosses to another lane.
9978 bool LaneCrossing[2] = {false, false};
9979 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9980 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9981 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9982 if (!LaneCrossing[0] || !LaneCrossing[1])
9983 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9985 if (isSingleInputShuffleMask(Mask)) {
9986 SmallVector<int, 32> FlippedBlendMask;
9987 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9988 FlippedBlendMask.push_back(
9989 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9991 : Mask[i] % LaneSize +
9992 (i / LaneSize) * LaneSize + Size));
9994 // Flip the vector, and blend the results which should now be in-lane. The
9995 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9996 // 5 for the high source. The value 3 selects the high half of source 2 and
9997 // the value 2 selects the low half of source 2. We only use source 2 to
9998 // allow folding it into a memory operand.
9999 unsigned PERMMask = 3 | 2 << 4;
10000 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10001 V1, DAG.getConstant(PERMMask, MVT::i8));
10002 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10005 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10006 // will be handled by the above logic and a blend of the results, much like
10007 // other patterns in AVX.
10008 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10011 /// \brief Handle lowering 2-lane 128-bit shuffles.
10012 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10013 SDValue V2, ArrayRef<int> Mask,
10014 const X86Subtarget *Subtarget,
10015 SelectionDAG &DAG) {
10016 // Blends are faster and handle all the non-lane-crossing cases.
10017 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10021 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10022 VT.getVectorNumElements() / 2);
10023 // Check for patterns which can be matched with a single insert of a 128-bit
10025 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10026 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10027 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10028 DAG.getIntPtrConstant(0));
10029 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10030 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10031 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10033 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10034 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10035 DAG.getIntPtrConstant(0));
10036 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10037 DAG.getIntPtrConstant(2));
10038 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10041 // Otherwise form a 128-bit permutation.
10042 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10043 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10044 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10045 DAG.getConstant(PermMask, MVT::i8));
10048 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10049 /// shuffling each lane.
10051 /// This will only succeed when the result of fixing the 128-bit lanes results
10052 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10053 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10054 /// the lane crosses early and then use simpler shuffles within each lane.
10056 /// FIXME: It might be worthwhile at some point to support this without
10057 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10058 /// in x86 only floating point has interesting non-repeating shuffles, and even
10059 /// those are still *marginally* more expensive.
10060 static SDValue lowerVectorShuffleByMerging128BitLanes(
10061 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10062 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10063 assert(!isSingleInputShuffleMask(Mask) &&
10064 "This is only useful with multiple inputs.");
10066 int Size = Mask.size();
10067 int LaneSize = 128 / VT.getScalarSizeInBits();
10068 int NumLanes = Size / LaneSize;
10069 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10071 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10072 // check whether the in-128-bit lane shuffles share a repeating pattern.
10073 SmallVector<int, 4> Lanes;
10074 Lanes.resize(NumLanes, -1);
10075 SmallVector<int, 4> InLaneMask;
10076 InLaneMask.resize(LaneSize, -1);
10077 for (int i = 0; i < Size; ++i) {
10081 int j = i / LaneSize;
10083 if (Lanes[j] < 0) {
10084 // First entry we've seen for this lane.
10085 Lanes[j] = Mask[i] / LaneSize;
10086 } else if (Lanes[j] != Mask[i] / LaneSize) {
10087 // This doesn't match the lane selected previously!
10091 // Check that within each lane we have a consistent shuffle mask.
10092 int k = i % LaneSize;
10093 if (InLaneMask[k] < 0) {
10094 InLaneMask[k] = Mask[i] % LaneSize;
10095 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10096 // This doesn't fit a repeating in-lane mask.
10101 // First shuffle the lanes into place.
10102 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10103 VT.getSizeInBits() / 64);
10104 SmallVector<int, 8> LaneMask;
10105 LaneMask.resize(NumLanes * 2, -1);
10106 for (int i = 0; i < NumLanes; ++i)
10107 if (Lanes[i] >= 0) {
10108 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10109 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10112 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10113 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10114 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10116 // Cast it back to the type we actually want.
10117 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10119 // Now do a simple shuffle that isn't lane crossing.
10120 SmallVector<int, 8> NewMask;
10121 NewMask.resize(Size, -1);
10122 for (int i = 0; i < Size; ++i)
10124 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10125 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10126 "Must not introduce lane crosses at this point!");
10128 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10131 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10134 /// This returns true if the elements from a particular input are already in the
10135 /// slot required by the given mask and require no permutation.
10136 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10137 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10138 int Size = Mask.size();
10139 for (int i = 0; i < Size; ++i)
10140 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10146 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10148 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10149 /// isn't available.
10150 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10151 const X86Subtarget *Subtarget,
10152 SelectionDAG &DAG) {
10154 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10155 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10156 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10157 ArrayRef<int> Mask = SVOp->getMask();
10158 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10160 SmallVector<int, 4> WidenedMask;
10161 if (canWidenShuffleElements(Mask, WidenedMask))
10162 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10165 if (isSingleInputShuffleMask(Mask)) {
10166 // Check for being able to broadcast a single element.
10167 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10168 Mask, Subtarget, DAG))
10171 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10172 // Non-half-crossing single input shuffles can be lowerid with an
10173 // interleaved permutation.
10174 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10175 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10176 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10177 DAG.getConstant(VPERMILPMask, MVT::i8));
10180 // With AVX2 we have direct support for this permutation.
10181 if (Subtarget->hasAVX2())
10182 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10183 getV4X86ShuffleImm8ForMask(Mask, DAG));
10185 // Otherwise, fall back.
10186 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10190 // X86 has dedicated unpack instructions that can handle specific blend
10191 // operations: UNPCKH and UNPCKL.
10192 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10193 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10194 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10195 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10197 // If we have a single input to the zero element, insert that into V1 if we
10198 // can do so cheaply.
10199 int NumV2Elements =
10200 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10201 if (NumV2Elements == 1 && Mask[0] >= 4)
10202 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10203 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10206 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10210 // Check if the blend happens to exactly fit that of SHUFPD.
10211 if ((Mask[0] == -1 || Mask[0] < 2) &&
10212 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10213 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10214 (Mask[3] == -1 || Mask[3] >= 6)) {
10215 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10216 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10217 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10218 DAG.getConstant(SHUFPDMask, MVT::i8));
10220 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10221 (Mask[1] == -1 || Mask[1] < 2) &&
10222 (Mask[2] == -1 || Mask[2] >= 6) &&
10223 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10224 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10225 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10226 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10227 DAG.getConstant(SHUFPDMask, MVT::i8));
10230 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10231 // shuffle. However, if we have AVX2 and either inputs are already in place,
10232 // we will be able to shuffle even across lanes the other input in a single
10233 // instruction so skip this pattern.
10234 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10235 isShuffleMaskInputInPlace(1, Mask))))
10236 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10237 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10240 // If we have AVX2 then we always want to lower with a blend because an v4 we
10241 // can fully permute the elements.
10242 if (Subtarget->hasAVX2())
10243 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10246 // Otherwise fall back on generic lowering.
10247 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10250 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10252 /// This routine is only called when we have AVX2 and thus a reasonable
10253 /// instruction set for v4i64 shuffling..
10254 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10255 const X86Subtarget *Subtarget,
10256 SelectionDAG &DAG) {
10258 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10259 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10260 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10261 ArrayRef<int> Mask = SVOp->getMask();
10262 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10263 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10265 SmallVector<int, 4> WidenedMask;
10266 if (canWidenShuffleElements(Mask, WidenedMask))
10267 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10270 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10274 // Check for being able to broadcast a single element.
10275 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10276 Mask, Subtarget, DAG))
10279 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10280 // use lower latency instructions that will operate on both 128-bit lanes.
10281 SmallVector<int, 2> RepeatedMask;
10282 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10283 if (isSingleInputShuffleMask(Mask)) {
10284 int PSHUFDMask[] = {-1, -1, -1, -1};
10285 for (int i = 0; i < 2; ++i)
10286 if (RepeatedMask[i] >= 0) {
10287 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10288 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10290 return DAG.getNode(
10291 ISD::BITCAST, DL, MVT::v4i64,
10292 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10293 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10294 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10297 // Use dedicated unpack instructions for masks that match their pattern.
10298 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10299 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10300 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10301 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10304 // AVX2 provides a direct instruction for permuting a single input across
10306 if (isSingleInputShuffleMask(Mask))
10307 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10308 getV4X86ShuffleImm8ForMask(Mask, DAG));
10310 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10311 // shuffle. However, if we have AVX2 and either inputs are already in place,
10312 // we will be able to shuffle even across lanes the other input in a single
10313 // instruction so skip this pattern.
10314 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10315 isShuffleMaskInputInPlace(1, Mask))))
10316 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10317 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10320 // Otherwise fall back on generic blend lowering.
10321 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10325 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10327 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10328 /// isn't available.
10329 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10330 const X86Subtarget *Subtarget,
10331 SelectionDAG &DAG) {
10333 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10334 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10336 ArrayRef<int> Mask = SVOp->getMask();
10337 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10339 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10343 // Check for being able to broadcast a single element.
10344 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10345 Mask, Subtarget, DAG))
10348 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10349 // options to efficiently lower the shuffle.
10350 SmallVector<int, 4> RepeatedMask;
10351 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10352 assert(RepeatedMask.size() == 4 &&
10353 "Repeated masks must be half the mask width!");
10354 if (isSingleInputShuffleMask(Mask))
10355 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10356 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10358 // Use dedicated unpack instructions for masks that match their pattern.
10359 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10360 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10361 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10362 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10364 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10365 // have already handled any direct blends. We also need to squash the
10366 // repeated mask into a simulated v4f32 mask.
10367 for (int i = 0; i < 4; ++i)
10368 if (RepeatedMask[i] >= 8)
10369 RepeatedMask[i] -= 4;
10370 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10373 // If we have a single input shuffle with different shuffle patterns in the
10374 // two 128-bit lanes use the variable mask to VPERMILPS.
10375 if (isSingleInputShuffleMask(Mask)) {
10376 SDValue VPermMask[8];
10377 for (int i = 0; i < 8; ++i)
10378 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10379 : DAG.getConstant(Mask[i], MVT::i32);
10380 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10381 return DAG.getNode(
10382 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10383 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10385 if (Subtarget->hasAVX2())
10386 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10387 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10388 DAG.getNode(ISD::BUILD_VECTOR, DL,
10389 MVT::v8i32, VPermMask)),
10392 // Otherwise, fall back.
10393 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10397 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10399 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10400 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10403 // If we have AVX2 then we always want to lower with a blend because at v8 we
10404 // can fully permute the elements.
10405 if (Subtarget->hasAVX2())
10406 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10409 // Otherwise fall back on generic lowering.
10410 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10413 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10415 /// This routine is only called when we have AVX2 and thus a reasonable
10416 /// instruction set for v8i32 shuffling..
10417 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10418 const X86Subtarget *Subtarget,
10419 SelectionDAG &DAG) {
10421 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10422 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10423 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10424 ArrayRef<int> Mask = SVOp->getMask();
10425 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10426 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10428 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10432 // Check for being able to broadcast a single element.
10433 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10434 Mask, Subtarget, DAG))
10437 // If the shuffle mask is repeated in each 128-bit lane we can use more
10438 // efficient instructions that mirror the shuffles across the two 128-bit
10440 SmallVector<int, 4> RepeatedMask;
10441 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10442 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10443 if (isSingleInputShuffleMask(Mask))
10444 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10445 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10447 // Use dedicated unpack instructions for masks that match their pattern.
10448 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10449 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10450 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10451 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10454 // If the shuffle patterns aren't repeated but it is a single input, directly
10455 // generate a cross-lane VPERMD instruction.
10456 if (isSingleInputShuffleMask(Mask)) {
10457 SDValue VPermMask[8];
10458 for (int i = 0; i < 8; ++i)
10459 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10460 : DAG.getConstant(Mask[i], MVT::i32);
10461 return DAG.getNode(
10462 X86ISD::VPERMV, DL, MVT::v8i32,
10463 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10466 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10468 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10469 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10472 // Otherwise fall back on generic blend lowering.
10473 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10477 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10479 /// This routine is only called when we have AVX2 and thus a reasonable
10480 /// instruction set for v16i16 shuffling..
10481 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10482 const X86Subtarget *Subtarget,
10483 SelectionDAG &DAG) {
10485 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10486 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10487 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10488 ArrayRef<int> Mask = SVOp->getMask();
10489 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10490 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10492 // Check for being able to broadcast a single element.
10493 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10494 Mask, Subtarget, DAG))
10497 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10501 // Use dedicated unpack instructions for masks that match their pattern.
10502 if (isShuffleEquivalent(Mask,
10503 // First 128-bit lane:
10504 0, 16, 1, 17, 2, 18, 3, 19,
10505 // Second 128-bit lane:
10506 8, 24, 9, 25, 10, 26, 11, 27))
10507 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10508 if (isShuffleEquivalent(Mask,
10509 // First 128-bit lane:
10510 4, 20, 5, 21, 6, 22, 7, 23,
10511 // Second 128-bit lane:
10512 12, 28, 13, 29, 14, 30, 15, 31))
10513 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10515 if (isSingleInputShuffleMask(Mask)) {
10516 // There are no generalized cross-lane shuffle operations available on i16
10518 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10519 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10522 SDValue PSHUFBMask[32];
10523 for (int i = 0; i < 16; ++i) {
10524 if (Mask[i] == -1) {
10525 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10529 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10530 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10531 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10532 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10534 return DAG.getNode(
10535 ISD::BITCAST, DL, MVT::v16i16,
10537 X86ISD::PSHUFB, DL, MVT::v32i8,
10538 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10539 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10542 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10544 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10545 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10548 // Otherwise fall back on generic lowering.
10549 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10552 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10554 /// This routine is only called when we have AVX2 and thus a reasonable
10555 /// instruction set for v32i8 shuffling..
10556 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10557 const X86Subtarget *Subtarget,
10558 SelectionDAG &DAG) {
10560 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10561 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10562 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10563 ArrayRef<int> Mask = SVOp->getMask();
10564 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10565 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10567 // Check for being able to broadcast a single element.
10568 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10569 Mask, Subtarget, DAG))
10572 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10576 // Use dedicated unpack instructions for masks that match their pattern.
10577 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10579 if (isShuffleEquivalent(
10581 // First 128-bit lane:
10582 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10583 // Second 128-bit lane:
10584 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10585 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10586 if (isShuffleEquivalent(
10588 // First 128-bit lane:
10589 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10590 // Second 128-bit lane:
10591 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10592 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10594 if (isSingleInputShuffleMask(Mask)) {
10595 // There are no generalized cross-lane shuffle operations available on i8
10597 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10598 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10601 SDValue PSHUFBMask[32];
10602 for (int i = 0; i < 32; ++i)
10605 ? DAG.getUNDEF(MVT::i8)
10606 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10608 return DAG.getNode(
10609 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10610 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10613 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10615 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10616 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10619 // Otherwise fall back on generic lowering.
10620 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10623 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10625 /// This routine either breaks down the specific type of a 256-bit x86 vector
10626 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10627 /// together based on the available instructions.
10628 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10629 MVT VT, const X86Subtarget *Subtarget,
10630 SelectionDAG &DAG) {
10632 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10633 ArrayRef<int> Mask = SVOp->getMask();
10635 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10636 // check for those subtargets here and avoid much of the subtarget querying in
10637 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10638 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10639 // floating point types there eventually, just immediately cast everything to
10640 // a float and operate entirely in that domain.
10641 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10642 int ElementBits = VT.getScalarSizeInBits();
10643 if (ElementBits < 32)
10644 // No floating point type available, decompose into 128-bit vectors.
10645 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10647 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10648 VT.getVectorNumElements());
10649 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10650 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10651 return DAG.getNode(ISD::BITCAST, DL, VT,
10652 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10655 switch (VT.SimpleTy) {
10657 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10659 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10661 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10663 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10665 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10667 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10670 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10674 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10675 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10676 const X86Subtarget *Subtarget,
10677 SelectionDAG &DAG) {
10679 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10680 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10681 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10682 ArrayRef<int> Mask = SVOp->getMask();
10683 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10685 // FIXME: Implement direct support for this type!
10686 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10689 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10690 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10691 const X86Subtarget *Subtarget,
10692 SelectionDAG &DAG) {
10694 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10695 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10697 ArrayRef<int> Mask = SVOp->getMask();
10698 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10700 // FIXME: Implement direct support for this type!
10701 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10704 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10705 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10706 const X86Subtarget *Subtarget,
10707 SelectionDAG &DAG) {
10709 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10710 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10712 ArrayRef<int> Mask = SVOp->getMask();
10713 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10715 // FIXME: Implement direct support for this type!
10716 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10719 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10720 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10721 const X86Subtarget *Subtarget,
10722 SelectionDAG &DAG) {
10724 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10725 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10727 ArrayRef<int> Mask = SVOp->getMask();
10728 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10730 // FIXME: Implement direct support for this type!
10731 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10734 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10735 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10736 const X86Subtarget *Subtarget,
10737 SelectionDAG &DAG) {
10739 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10740 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10741 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10742 ArrayRef<int> Mask = SVOp->getMask();
10743 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10744 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10746 // FIXME: Implement direct support for this type!
10747 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10750 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10751 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10752 const X86Subtarget *Subtarget,
10753 SelectionDAG &DAG) {
10755 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10756 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10757 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10758 ArrayRef<int> Mask = SVOp->getMask();
10759 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10760 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10762 // FIXME: Implement direct support for this type!
10763 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10766 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10768 /// This routine either breaks down the specific type of a 512-bit x86 vector
10769 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10770 /// together based on the available instructions.
10771 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10772 MVT VT, const X86Subtarget *Subtarget,
10773 SelectionDAG &DAG) {
10775 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10776 ArrayRef<int> Mask = SVOp->getMask();
10777 assert(Subtarget->hasAVX512() &&
10778 "Cannot lower 512-bit vectors w/ basic ISA!");
10780 // Check for being able to broadcast a single element.
10781 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10782 Mask, Subtarget, DAG))
10785 // Dispatch to each element type for lowering. If we don't have supprot for
10786 // specific element type shuffles at 512 bits, immediately split them and
10787 // lower them. Each lowering routine of a given type is allowed to assume that
10788 // the requisite ISA extensions for that element type are available.
10789 switch (VT.SimpleTy) {
10791 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10793 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10795 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10797 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10799 if (Subtarget->hasBWI())
10800 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10803 if (Subtarget->hasBWI())
10804 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10808 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10811 // Otherwise fall back on splitting.
10812 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10815 /// \brief Top-level lowering for x86 vector shuffles.
10817 /// This handles decomposition, canonicalization, and lowering of all x86
10818 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10819 /// above in helper routines. The canonicalization attempts to widen shuffles
10820 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10821 /// s.t. only one of the two inputs needs to be tested, etc.
10822 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10823 SelectionDAG &DAG) {
10824 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10825 ArrayRef<int> Mask = SVOp->getMask();
10826 SDValue V1 = Op.getOperand(0);
10827 SDValue V2 = Op.getOperand(1);
10828 MVT VT = Op.getSimpleValueType();
10829 int NumElements = VT.getVectorNumElements();
10832 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10834 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10835 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10836 if (V1IsUndef && V2IsUndef)
10837 return DAG.getUNDEF(VT);
10839 // When we create a shuffle node we put the UNDEF node to second operand,
10840 // but in some cases the first operand may be transformed to UNDEF.
10841 // In this case we should just commute the node.
10843 return DAG.getCommutedVectorShuffle(*SVOp);
10845 // Check for non-undef masks pointing at an undef vector and make the masks
10846 // undef as well. This makes it easier to match the shuffle based solely on
10850 if (M >= NumElements) {
10851 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10852 for (int &M : NewMask)
10853 if (M >= NumElements)
10855 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10858 // Try to collapse shuffles into using a vector type with fewer elements but
10859 // wider element types. We cap this to not form integers or floating point
10860 // elements wider than 64 bits, but it might be interesting to form i128
10861 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10862 SmallVector<int, 16> WidenedMask;
10863 if (VT.getScalarSizeInBits() < 64 &&
10864 canWidenShuffleElements(Mask, WidenedMask)) {
10865 MVT NewEltVT = VT.isFloatingPoint()
10866 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10867 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10868 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10869 // Make sure that the new vector type is legal. For example, v2f64 isn't
10871 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10872 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10873 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10874 return DAG.getNode(ISD::BITCAST, dl, VT,
10875 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10879 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10880 for (int M : SVOp->getMask())
10882 ++NumUndefElements;
10883 else if (M < NumElements)
10888 // Commute the shuffle as needed such that more elements come from V1 than
10889 // V2. This allows us to match the shuffle pattern strictly on how many
10890 // elements come from V1 without handling the symmetric cases.
10891 if (NumV2Elements > NumV1Elements)
10892 return DAG.getCommutedVectorShuffle(*SVOp);
10894 // When the number of V1 and V2 elements are the same, try to minimize the
10895 // number of uses of V2 in the low half of the vector. When that is tied,
10896 // ensure that the sum of indices for V1 is equal to or lower than the sum
10897 // indices for V2. When those are equal, try to ensure that the number of odd
10898 // indices for V1 is lower than the number of odd indices for V2.
10899 if (NumV1Elements == NumV2Elements) {
10900 int LowV1Elements = 0, LowV2Elements = 0;
10901 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10902 if (M >= NumElements)
10906 if (LowV2Elements > LowV1Elements) {
10907 return DAG.getCommutedVectorShuffle(*SVOp);
10908 } else if (LowV2Elements == LowV1Elements) {
10909 int SumV1Indices = 0, SumV2Indices = 0;
10910 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10911 if (SVOp->getMask()[i] >= NumElements)
10913 else if (SVOp->getMask()[i] >= 0)
10915 if (SumV2Indices < SumV1Indices) {
10916 return DAG.getCommutedVectorShuffle(*SVOp);
10917 } else if (SumV2Indices == SumV1Indices) {
10918 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10919 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10920 if (SVOp->getMask()[i] >= NumElements)
10921 NumV2OddIndices += i % 2;
10922 else if (SVOp->getMask()[i] >= 0)
10923 NumV1OddIndices += i % 2;
10924 if (NumV2OddIndices < NumV1OddIndices)
10925 return DAG.getCommutedVectorShuffle(*SVOp);
10930 // For each vector width, delegate to a specialized lowering routine.
10931 if (VT.getSizeInBits() == 128)
10932 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10934 if (VT.getSizeInBits() == 256)
10935 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10937 // Force AVX-512 vectors to be scalarized for now.
10938 // FIXME: Implement AVX-512 support!
10939 if (VT.getSizeInBits() == 512)
10940 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10942 llvm_unreachable("Unimplemented!");
10946 //===----------------------------------------------------------------------===//
10947 // Legacy vector shuffle lowering
10949 // This code is the legacy code handling vector shuffles until the above
10950 // replaces its functionality and performance.
10951 //===----------------------------------------------------------------------===//
10953 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10954 bool hasInt256, unsigned *MaskOut = nullptr) {
10955 MVT EltVT = VT.getVectorElementType();
10957 // There is no blend with immediate in AVX-512.
10958 if (VT.is512BitVector())
10961 if (!hasSSE41 || EltVT == MVT::i8)
10963 if (!hasInt256 && VT == MVT::v16i16)
10966 unsigned MaskValue = 0;
10967 unsigned NumElems = VT.getVectorNumElements();
10968 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10969 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10970 unsigned NumElemsInLane = NumElems / NumLanes;
10972 // Blend for v16i16 should be symetric for the both lanes.
10973 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10975 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10976 int EltIdx = MaskVals[i];
10978 if ((EltIdx < 0 || EltIdx == (int)i) &&
10979 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10982 if (((unsigned)EltIdx == (i + NumElems)) &&
10983 (SndLaneEltIdx < 0 ||
10984 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10985 MaskValue |= (1 << i);
10991 *MaskOut = MaskValue;
10995 // Try to lower a shuffle node into a simple blend instruction.
10996 // This function assumes isBlendMask returns true for this
10997 // SuffleVectorSDNode
10998 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10999 unsigned MaskValue,
11000 const X86Subtarget *Subtarget,
11001 SelectionDAG &DAG) {
11002 MVT VT = SVOp->getSimpleValueType(0);
11003 MVT EltVT = VT.getVectorElementType();
11004 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11005 Subtarget->hasInt256() && "Trying to lower a "
11006 "VECTOR_SHUFFLE to a Blend but "
11007 "with the wrong mask"));
11008 SDValue V1 = SVOp->getOperand(0);
11009 SDValue V2 = SVOp->getOperand(1);
11011 unsigned NumElems = VT.getVectorNumElements();
11013 // Convert i32 vectors to floating point if it is not AVX2.
11014 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11016 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11017 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11019 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11020 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11023 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11024 DAG.getConstant(MaskValue, MVT::i32));
11025 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11028 /// In vector type \p VT, return true if the element at index \p InputIdx
11029 /// falls on a different 128-bit lane than \p OutputIdx.
11030 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11031 unsigned OutputIdx) {
11032 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11033 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11036 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11037 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11038 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11039 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11041 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11042 SelectionDAG &DAG) {
11043 MVT VT = V1.getSimpleValueType();
11044 assert(VT.is128BitVector() || VT.is256BitVector());
11046 MVT EltVT = VT.getVectorElementType();
11047 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11048 unsigned NumElts = VT.getVectorNumElements();
11050 SmallVector<SDValue, 32> PshufbMask;
11051 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11052 int InputIdx = MaskVals[OutputIdx];
11053 unsigned InputByteIdx;
11055 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11056 InputByteIdx = 0x80;
11058 // Cross lane is not allowed.
11059 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11061 InputByteIdx = InputIdx * EltSizeInBytes;
11062 // Index is an byte offset within the 128-bit lane.
11063 InputByteIdx &= 0xf;
11066 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11067 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11068 if (InputByteIdx != 0x80)
11073 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11075 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11076 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11077 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11080 // v8i16 shuffles - Prefer shuffles in the following order:
11081 // 1. [all] pshuflw, pshufhw, optional move
11082 // 2. [ssse3] 1 x pshufb
11083 // 3. [ssse3] 2 x pshufb + 1 x por
11084 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11086 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11087 SelectionDAG &DAG) {
11088 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11089 SDValue V1 = SVOp->getOperand(0);
11090 SDValue V2 = SVOp->getOperand(1);
11092 SmallVector<int, 8> MaskVals;
11094 // Determine if more than 1 of the words in each of the low and high quadwords
11095 // of the result come from the same quadword of one of the two inputs. Undef
11096 // mask values count as coming from any quadword, for better codegen.
11098 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11099 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11100 unsigned LoQuad[] = { 0, 0, 0, 0 };
11101 unsigned HiQuad[] = { 0, 0, 0, 0 };
11102 // Indices of quads used.
11103 std::bitset<4> InputQuads;
11104 for (unsigned i = 0; i < 8; ++i) {
11105 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11106 int EltIdx = SVOp->getMaskElt(i);
11107 MaskVals.push_back(EltIdx);
11115 ++Quad[EltIdx / 4];
11116 InputQuads.set(EltIdx / 4);
11119 int BestLoQuad = -1;
11120 unsigned MaxQuad = 1;
11121 for (unsigned i = 0; i < 4; ++i) {
11122 if (LoQuad[i] > MaxQuad) {
11124 MaxQuad = LoQuad[i];
11128 int BestHiQuad = -1;
11130 for (unsigned i = 0; i < 4; ++i) {
11131 if (HiQuad[i] > MaxQuad) {
11133 MaxQuad = HiQuad[i];
11137 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11138 // of the two input vectors, shuffle them into one input vector so only a
11139 // single pshufb instruction is necessary. If there are more than 2 input
11140 // quads, disable the next transformation since it does not help SSSE3.
11141 bool V1Used = InputQuads[0] || InputQuads[1];
11142 bool V2Used = InputQuads[2] || InputQuads[3];
11143 if (Subtarget->hasSSSE3()) {
11144 if (InputQuads.count() == 2 && V1Used && V2Used) {
11145 BestLoQuad = InputQuads[0] ? 0 : 1;
11146 BestHiQuad = InputQuads[2] ? 2 : 3;
11148 if (InputQuads.count() > 2) {
11154 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11155 // the shuffle mask. If a quad is scored as -1, that means that it contains
11156 // words from all 4 input quadwords.
11158 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11160 BestLoQuad < 0 ? 0 : BestLoQuad,
11161 BestHiQuad < 0 ? 1 : BestHiQuad
11163 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11164 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11165 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11166 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11168 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11169 // source words for the shuffle, to aid later transformations.
11170 bool AllWordsInNewV = true;
11171 bool InOrder[2] = { true, true };
11172 for (unsigned i = 0; i != 8; ++i) {
11173 int idx = MaskVals[i];
11175 InOrder[i/4] = false;
11176 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11178 AllWordsInNewV = false;
11182 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11183 if (AllWordsInNewV) {
11184 for (int i = 0; i != 8; ++i) {
11185 int idx = MaskVals[i];
11188 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11189 if ((idx != i) && idx < 4)
11191 if ((idx != i) && idx > 3)
11200 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11201 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11202 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11203 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11204 unsigned TargetMask = 0;
11205 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11206 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11207 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11208 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11209 getShufflePSHUFLWImmediate(SVOp);
11210 V1 = NewV.getOperand(0);
11211 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11215 // Promote splats to a larger type which usually leads to more efficient code.
11216 // FIXME: Is this true if pshufb is available?
11217 if (SVOp->isSplat())
11218 return PromoteSplat(SVOp, DAG);
11220 // If we have SSSE3, and all words of the result are from 1 input vector,
11221 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11222 // is present, fall back to case 4.
11223 if (Subtarget->hasSSSE3()) {
11224 SmallVector<SDValue,16> pshufbMask;
11226 // If we have elements from both input vectors, set the high bit of the
11227 // shuffle mask element to zero out elements that come from V2 in the V1
11228 // mask, and elements that come from V1 in the V2 mask, so that the two
11229 // results can be OR'd together.
11230 bool TwoInputs = V1Used && V2Used;
11231 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11233 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11235 // Calculate the shuffle mask for the second input, shuffle it, and
11236 // OR it with the first shuffled input.
11237 CommuteVectorShuffleMask(MaskVals, 8);
11238 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11239 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11240 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11243 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11244 // and update MaskVals with new element order.
11245 std::bitset<8> InOrder;
11246 if (BestLoQuad >= 0) {
11247 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11248 for (int i = 0; i != 4; ++i) {
11249 int idx = MaskVals[i];
11252 } else if ((idx / 4) == BestLoQuad) {
11253 MaskV[i] = idx & 3;
11257 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11260 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11261 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11262 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11263 NewV.getOperand(0),
11264 getShufflePSHUFLWImmediate(SVOp), DAG);
11268 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11269 // and update MaskVals with the new element order.
11270 if (BestHiQuad >= 0) {
11271 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11272 for (unsigned i = 4; i != 8; ++i) {
11273 int idx = MaskVals[i];
11276 } else if ((idx / 4) == BestHiQuad) {
11277 MaskV[i] = (idx & 3) + 4;
11281 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11284 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11285 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11286 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11287 NewV.getOperand(0),
11288 getShufflePSHUFHWImmediate(SVOp), DAG);
11292 // In case BestHi & BestLo were both -1, which means each quadword has a word
11293 // from each of the four input quadwords, calculate the InOrder bitvector now
11294 // before falling through to the insert/extract cleanup.
11295 if (BestLoQuad == -1 && BestHiQuad == -1) {
11297 for (int i = 0; i != 8; ++i)
11298 if (MaskVals[i] < 0 || MaskVals[i] == i)
11302 // The other elements are put in the right place using pextrw and pinsrw.
11303 for (unsigned i = 0; i != 8; ++i) {
11306 int EltIdx = MaskVals[i];
11309 SDValue ExtOp = (EltIdx < 8) ?
11310 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11311 DAG.getIntPtrConstant(EltIdx)) :
11312 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11313 DAG.getIntPtrConstant(EltIdx - 8));
11314 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11315 DAG.getIntPtrConstant(i));
11320 /// \brief v16i16 shuffles
11322 /// FIXME: We only support generation of a single pshufb currently. We can
11323 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11324 /// well (e.g 2 x pshufb + 1 x por).
11326 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11327 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11328 SDValue V1 = SVOp->getOperand(0);
11329 SDValue V2 = SVOp->getOperand(1);
11332 if (V2.getOpcode() != ISD::UNDEF)
11335 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11336 return getPSHUFB(MaskVals, V1, dl, DAG);
11339 // v16i8 shuffles - Prefer shuffles in the following order:
11340 // 1. [ssse3] 1 x pshufb
11341 // 2. [ssse3] 2 x pshufb + 1 x por
11342 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11343 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11344 const X86Subtarget* Subtarget,
11345 SelectionDAG &DAG) {
11346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11347 SDValue V1 = SVOp->getOperand(0);
11348 SDValue V2 = SVOp->getOperand(1);
11350 ArrayRef<int> MaskVals = SVOp->getMask();
11352 // Promote splats to a larger type which usually leads to more efficient code.
11353 // FIXME: Is this true if pshufb is available?
11354 if (SVOp->isSplat())
11355 return PromoteSplat(SVOp, DAG);
11357 // If we have SSSE3, case 1 is generated when all result bytes come from
11358 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11359 // present, fall back to case 3.
11361 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11362 if (Subtarget->hasSSSE3()) {
11363 SmallVector<SDValue,16> pshufbMask;
11365 // If all result elements are from one input vector, then only translate
11366 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11368 // Otherwise, we have elements from both input vectors, and must zero out
11369 // elements that come from V2 in the first mask, and V1 in the second mask
11370 // so that we can OR them together.
11371 for (unsigned i = 0; i != 16; ++i) {
11372 int EltIdx = MaskVals[i];
11373 if (EltIdx < 0 || EltIdx >= 16)
11375 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11377 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11378 DAG.getNode(ISD::BUILD_VECTOR, dl,
11379 MVT::v16i8, pshufbMask));
11381 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11382 // the 2nd operand if it's undefined or zero.
11383 if (V2.getOpcode() == ISD::UNDEF ||
11384 ISD::isBuildVectorAllZeros(V2.getNode()))
11387 // Calculate the shuffle mask for the second input, shuffle it, and
11388 // OR it with the first shuffled input.
11389 pshufbMask.clear();
11390 for (unsigned i = 0; i != 16; ++i) {
11391 int EltIdx = MaskVals[i];
11392 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11393 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11395 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11396 DAG.getNode(ISD::BUILD_VECTOR, dl,
11397 MVT::v16i8, pshufbMask));
11398 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11401 // No SSSE3 - Calculate in place words and then fix all out of place words
11402 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11403 // the 16 different words that comprise the two doublequadword input vectors.
11404 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11405 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11407 for (int i = 0; i != 8; ++i) {
11408 int Elt0 = MaskVals[i*2];
11409 int Elt1 = MaskVals[i*2+1];
11411 // This word of the result is all undef, skip it.
11412 if (Elt0 < 0 && Elt1 < 0)
11415 // This word of the result is already in the correct place, skip it.
11416 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11419 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11420 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11423 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11424 // using a single extract together, load it and store it.
11425 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11426 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11427 DAG.getIntPtrConstant(Elt1 / 2));
11428 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11429 DAG.getIntPtrConstant(i));
11433 // If Elt1 is defined, extract it from the appropriate source. If the
11434 // source byte is not also odd, shift the extracted word left 8 bits
11435 // otherwise clear the bottom 8 bits if we need to do an or.
11437 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11438 DAG.getIntPtrConstant(Elt1 / 2));
11439 if ((Elt1 & 1) == 0)
11440 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11442 TLI.getShiftAmountTy(InsElt.getValueType())));
11443 else if (Elt0 >= 0)
11444 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11445 DAG.getConstant(0xFF00, MVT::i16));
11447 // If Elt0 is defined, extract it from the appropriate source. If the
11448 // source byte is not also even, shift the extracted word right 8 bits. If
11449 // Elt1 was also defined, OR the extracted values together before
11450 // inserting them in the result.
11452 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11453 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11454 if ((Elt0 & 1) != 0)
11455 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11457 TLI.getShiftAmountTy(InsElt0.getValueType())));
11458 else if (Elt1 >= 0)
11459 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11460 DAG.getConstant(0x00FF, MVT::i16));
11461 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11464 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11465 DAG.getIntPtrConstant(i));
11467 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11470 // v32i8 shuffles - Translate to VPSHUFB if possible.
11472 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11473 const X86Subtarget *Subtarget,
11474 SelectionDAG &DAG) {
11475 MVT VT = SVOp->getSimpleValueType(0);
11476 SDValue V1 = SVOp->getOperand(0);
11477 SDValue V2 = SVOp->getOperand(1);
11479 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11481 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11482 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11483 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11485 // VPSHUFB may be generated if
11486 // (1) one of input vector is undefined or zeroinitializer.
11487 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11488 // And (2) the mask indexes don't cross the 128-bit lane.
11489 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11490 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11493 if (V1IsAllZero && !V2IsAllZero) {
11494 CommuteVectorShuffleMask(MaskVals, 32);
11497 return getPSHUFB(MaskVals, V1, dl, DAG);
11500 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11501 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11502 /// done when every pair / quad of shuffle mask elements point to elements in
11503 /// the right sequence. e.g.
11504 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11506 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11507 SelectionDAG &DAG) {
11508 MVT VT = SVOp->getSimpleValueType(0);
11510 unsigned NumElems = VT.getVectorNumElements();
11513 switch (VT.SimpleTy) {
11514 default: llvm_unreachable("Unexpected!");
11517 return SDValue(SVOp, 0);
11518 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11519 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11520 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11521 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11522 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11523 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11526 SmallVector<int, 8> MaskVec;
11527 for (unsigned i = 0; i != NumElems; i += Scale) {
11529 for (unsigned j = 0; j != Scale; ++j) {
11530 int EltIdx = SVOp->getMaskElt(i+j);
11534 StartIdx = (EltIdx / Scale);
11535 if (EltIdx != (int)(StartIdx*Scale + j))
11538 MaskVec.push_back(StartIdx);
11541 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11542 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11543 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11546 /// getVZextMovL - Return a zero-extending vector move low node.
11548 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11549 SDValue SrcOp, SelectionDAG &DAG,
11550 const X86Subtarget *Subtarget, SDLoc dl) {
11551 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11552 LoadSDNode *LD = nullptr;
11553 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11554 LD = dyn_cast<LoadSDNode>(SrcOp);
11556 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11558 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11559 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11560 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11561 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11562 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11564 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11565 return DAG.getNode(ISD::BITCAST, dl, VT,
11566 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11567 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11569 SrcOp.getOperand(0)
11575 return DAG.getNode(ISD::BITCAST, dl, VT,
11576 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11577 DAG.getNode(ISD::BITCAST, dl,
11581 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11582 /// which could not be matched by any known target speficic shuffle
11584 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11586 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11587 if (NewOp.getNode())
11590 MVT VT = SVOp->getSimpleValueType(0);
11592 unsigned NumElems = VT.getVectorNumElements();
11593 unsigned NumLaneElems = NumElems / 2;
11596 MVT EltVT = VT.getVectorElementType();
11597 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11600 SmallVector<int, 16> Mask;
11601 for (unsigned l = 0; l < 2; ++l) {
11602 // Build a shuffle mask for the output, discovering on the fly which
11603 // input vectors to use as shuffle operands (recorded in InputUsed).
11604 // If building a suitable shuffle vector proves too hard, then bail
11605 // out with UseBuildVector set.
11606 bool UseBuildVector = false;
11607 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11608 unsigned LaneStart = l * NumLaneElems;
11609 for (unsigned i = 0; i != NumLaneElems; ++i) {
11610 // The mask element. This indexes into the input.
11611 int Idx = SVOp->getMaskElt(i+LaneStart);
11613 // the mask element does not index into any input vector.
11614 Mask.push_back(-1);
11618 // The input vector this mask element indexes into.
11619 int Input = Idx / NumLaneElems;
11621 // Turn the index into an offset from the start of the input vector.
11622 Idx -= Input * NumLaneElems;
11624 // Find or create a shuffle vector operand to hold this input.
11626 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11627 if (InputUsed[OpNo] == Input)
11628 // This input vector is already an operand.
11630 if (InputUsed[OpNo] < 0) {
11631 // Create a new operand for this input vector.
11632 InputUsed[OpNo] = Input;
11637 if (OpNo >= array_lengthof(InputUsed)) {
11638 // More than two input vectors used! Give up on trying to create a
11639 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11640 UseBuildVector = true;
11644 // Add the mask index for the new shuffle vector.
11645 Mask.push_back(Idx + OpNo * NumLaneElems);
11648 if (UseBuildVector) {
11649 SmallVector<SDValue, 16> SVOps;
11650 for (unsigned i = 0; i != NumLaneElems; ++i) {
11651 // The mask element. This indexes into the input.
11652 int Idx = SVOp->getMaskElt(i+LaneStart);
11654 SVOps.push_back(DAG.getUNDEF(EltVT));
11658 // The input vector this mask element indexes into.
11659 int Input = Idx / NumElems;
11661 // Turn the index into an offset from the start of the input vector.
11662 Idx -= Input * NumElems;
11664 // Extract the vector element by hand.
11665 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11666 SVOp->getOperand(Input),
11667 DAG.getIntPtrConstant(Idx)));
11670 // Construct the output using a BUILD_VECTOR.
11671 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11672 } else if (InputUsed[0] < 0) {
11673 // No input vectors were used! The result is undefined.
11674 Output[l] = DAG.getUNDEF(NVT);
11676 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11677 (InputUsed[0] % 2) * NumLaneElems,
11679 // If only one input was used, use an undefined vector for the other.
11680 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11681 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11682 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11683 // At least one input vector was used. Create a new shuffle vector.
11684 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11690 // Concatenate the result back
11691 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11694 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11695 /// 4 elements, and match them with several different shuffle types.
11697 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11698 SDValue V1 = SVOp->getOperand(0);
11699 SDValue V2 = SVOp->getOperand(1);
11701 MVT VT = SVOp->getSimpleValueType(0);
11703 assert(VT.is128BitVector() && "Unsupported vector size");
11705 std::pair<int, int> Locs[4];
11706 int Mask1[] = { -1, -1, -1, -1 };
11707 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11709 unsigned NumHi = 0;
11710 unsigned NumLo = 0;
11711 for (unsigned i = 0; i != 4; ++i) {
11712 int Idx = PermMask[i];
11714 Locs[i] = std::make_pair(-1, -1);
11716 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11718 Locs[i] = std::make_pair(0, NumLo);
11719 Mask1[NumLo] = Idx;
11722 Locs[i] = std::make_pair(1, NumHi);
11724 Mask1[2+NumHi] = Idx;
11730 if (NumLo <= 2 && NumHi <= 2) {
11731 // If no more than two elements come from either vector. This can be
11732 // implemented with two shuffles. First shuffle gather the elements.
11733 // The second shuffle, which takes the first shuffle as both of its
11734 // vector operands, put the elements into the right order.
11735 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11737 int Mask2[] = { -1, -1, -1, -1 };
11739 for (unsigned i = 0; i != 4; ++i)
11740 if (Locs[i].first != -1) {
11741 unsigned Idx = (i < 2) ? 0 : 4;
11742 Idx += Locs[i].first * 2 + Locs[i].second;
11746 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11749 if (NumLo == 3 || NumHi == 3) {
11750 // Otherwise, we must have three elements from one vector, call it X, and
11751 // one element from the other, call it Y. First, use a shufps to build an
11752 // intermediate vector with the one element from Y and the element from X
11753 // that will be in the same half in the final destination (the indexes don't
11754 // matter). Then, use a shufps to build the final vector, taking the half
11755 // containing the element from Y from the intermediate, and the other half
11758 // Normalize it so the 3 elements come from V1.
11759 CommuteVectorShuffleMask(PermMask, 4);
11763 // Find the element from V2.
11765 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11766 int Val = PermMask[HiIndex];
11773 Mask1[0] = PermMask[HiIndex];
11775 Mask1[2] = PermMask[HiIndex^1];
11777 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11779 if (HiIndex >= 2) {
11780 Mask1[0] = PermMask[0];
11781 Mask1[1] = PermMask[1];
11782 Mask1[2] = HiIndex & 1 ? 6 : 4;
11783 Mask1[3] = HiIndex & 1 ? 4 : 6;
11784 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11787 Mask1[0] = HiIndex & 1 ? 2 : 0;
11788 Mask1[1] = HiIndex & 1 ? 0 : 2;
11789 Mask1[2] = PermMask[2];
11790 Mask1[3] = PermMask[3];
11795 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11798 // Break it into (shuffle shuffle_hi, shuffle_lo).
11799 int LoMask[] = { -1, -1, -1, -1 };
11800 int HiMask[] = { -1, -1, -1, -1 };
11802 int *MaskPtr = LoMask;
11803 unsigned MaskIdx = 0;
11804 unsigned LoIdx = 0;
11805 unsigned HiIdx = 2;
11806 for (unsigned i = 0; i != 4; ++i) {
11813 int Idx = PermMask[i];
11815 Locs[i] = std::make_pair(-1, -1);
11816 } else if (Idx < 4) {
11817 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11818 MaskPtr[LoIdx] = Idx;
11821 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11822 MaskPtr[HiIdx] = Idx;
11827 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11828 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11829 int MaskOps[] = { -1, -1, -1, -1 };
11830 for (unsigned i = 0; i != 4; ++i)
11831 if (Locs[i].first != -1)
11832 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11833 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11836 static bool MayFoldVectorLoad(SDValue V) {
11837 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11838 V = V.getOperand(0);
11840 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11841 V = V.getOperand(0);
11842 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11843 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11844 // BUILD_VECTOR (load), undef
11845 V = V.getOperand(0);
11847 return MayFoldLoad(V);
11851 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11852 MVT VT = Op.getSimpleValueType();
11854 // Canonizalize to v2f64.
11855 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11856 return DAG.getNode(ISD::BITCAST, dl, VT,
11857 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11862 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11864 SDValue V1 = Op.getOperand(0);
11865 SDValue V2 = Op.getOperand(1);
11866 MVT VT = Op.getSimpleValueType();
11868 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11870 if (HasSSE2 && VT == MVT::v2f64)
11871 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11873 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11874 return DAG.getNode(ISD::BITCAST, dl, VT,
11875 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11876 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11877 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11881 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11882 SDValue V1 = Op.getOperand(0);
11883 SDValue V2 = Op.getOperand(1);
11884 MVT VT = Op.getSimpleValueType();
11886 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11887 "unsupported shuffle type");
11889 if (V2.getOpcode() == ISD::UNDEF)
11893 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11897 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11898 SDValue V1 = Op.getOperand(0);
11899 SDValue V2 = Op.getOperand(1);
11900 MVT VT = Op.getSimpleValueType();
11901 unsigned NumElems = VT.getVectorNumElements();
11903 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11904 // operand of these instructions is only memory, so check if there's a
11905 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11907 bool CanFoldLoad = false;
11909 // Trivial case, when V2 comes from a load.
11910 if (MayFoldVectorLoad(V2))
11911 CanFoldLoad = true;
11913 // When V1 is a load, it can be folded later into a store in isel, example:
11914 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11916 // (MOVLPSmr addr:$src1, VR128:$src2)
11917 // So, recognize this potential and also use MOVLPS or MOVLPD
11918 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11919 CanFoldLoad = true;
11921 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11923 if (HasSSE2 && NumElems == 2)
11924 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11927 // If we don't care about the second element, proceed to use movss.
11928 if (SVOp->getMaskElt(1) != -1)
11929 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11932 // movl and movlp will both match v2i64, but v2i64 is never matched by
11933 // movl earlier because we make it strict to avoid messing with the movlp load
11934 // folding logic (see the code above getMOVLP call). Match it here then,
11935 // this is horrible, but will stay like this until we move all shuffle
11936 // matching to x86 specific nodes. Note that for the 1st condition all
11937 // types are matched with movsd.
11939 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11940 // as to remove this logic from here, as much as possible
11941 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11942 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11943 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11946 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11948 // Invert the operand order and use SHUFPS to match it.
11949 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11950 getShuffleSHUFImmediate(SVOp), DAG);
11953 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11954 SelectionDAG &DAG) {
11956 MVT VT = Load->getSimpleValueType(0);
11957 MVT EVT = VT.getVectorElementType();
11958 SDValue Addr = Load->getOperand(1);
11959 SDValue NewAddr = DAG.getNode(
11960 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11961 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11964 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11965 DAG.getMachineFunction().getMachineMemOperand(
11966 Load->getMemOperand(), 0, EVT.getStoreSize()));
11970 // It is only safe to call this function if isINSERTPSMask is true for
11971 // this shufflevector mask.
11972 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11973 SelectionDAG &DAG) {
11974 // Generate an insertps instruction when inserting an f32 from memory onto a
11975 // v4f32 or when copying a member from one v4f32 to another.
11976 // We also use it for transferring i32 from one register to another,
11977 // since it simply copies the same bits.
11978 // If we're transferring an i32 from memory to a specific element in a
11979 // register, we output a generic DAG that will match the PINSRD
11981 MVT VT = SVOp->getSimpleValueType(0);
11982 MVT EVT = VT.getVectorElementType();
11983 SDValue V1 = SVOp->getOperand(0);
11984 SDValue V2 = SVOp->getOperand(1);
11985 auto Mask = SVOp->getMask();
11986 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11987 "unsupported vector type for insertps/pinsrd");
11989 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11990 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11991 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11995 unsigned DestIndex;
11999 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
12002 // If we have 1 element from each vector, we have to check if we're
12003 // changing V1's element's place. If so, we're done. Otherwise, we
12004 // should assume we're changing V2's element's place and behave
12006 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12007 assert(DestIndex <= INT32_MAX && "truncated destination index");
12008 if (FromV1 == FromV2 &&
12009 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12013 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12016 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12017 "More than one element from V1 and from V2, or no elements from one "
12018 "of the vectors. This case should not have returned true from "
12023 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12026 // Get an index into the source vector in the range [0,4) (the mask is
12027 // in the range [0,8) because it can address V1 and V2)
12028 unsigned SrcIndex = Mask[DestIndex] % 4;
12029 if (MayFoldLoad(From)) {
12030 // Trivial case, when From comes from a load and is only used by the
12031 // shuffle. Make it use insertps from the vector that we need from that
12034 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12035 if (!NewLoad.getNode())
12038 if (EVT == MVT::f32) {
12039 // Create this as a scalar to vector to match the instruction pattern.
12040 SDValue LoadScalarToVector =
12041 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12042 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12043 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12045 } else { // EVT == MVT::i32
12046 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12047 // instruction, to match the PINSRD instruction, which loads an i32 to a
12048 // certain vector element.
12049 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12050 DAG.getConstant(DestIndex, MVT::i32));
12054 // Vector-element-to-vector
12055 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12056 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12059 // Reduce a vector shuffle to zext.
12060 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12061 SelectionDAG &DAG) {
12062 // PMOVZX is only available from SSE41.
12063 if (!Subtarget->hasSSE41())
12066 MVT VT = Op.getSimpleValueType();
12068 // Only AVX2 support 256-bit vector integer extending.
12069 if (!Subtarget->hasInt256() && VT.is256BitVector())
12072 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12074 SDValue V1 = Op.getOperand(0);
12075 SDValue V2 = Op.getOperand(1);
12076 unsigned NumElems = VT.getVectorNumElements();
12078 // Extending is an unary operation and the element type of the source vector
12079 // won't be equal to or larger than i64.
12080 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12081 VT.getVectorElementType() == MVT::i64)
12084 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12085 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12086 while ((1U << Shift) < NumElems) {
12087 if (SVOp->getMaskElt(1U << Shift) == 1)
12090 // The maximal ratio is 8, i.e. from i8 to i64.
12095 // Check the shuffle mask.
12096 unsigned Mask = (1U << Shift) - 1;
12097 for (unsigned i = 0; i != NumElems; ++i) {
12098 int EltIdx = SVOp->getMaskElt(i);
12099 if ((i & Mask) != 0 && EltIdx != -1)
12101 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12105 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12106 MVT NeVT = MVT::getIntegerVT(NBits);
12107 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12109 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12112 return DAG.getNode(ISD::BITCAST, DL, VT,
12113 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12116 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12117 SelectionDAG &DAG) {
12118 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12119 MVT VT = Op.getSimpleValueType();
12121 SDValue V1 = Op.getOperand(0);
12122 SDValue V2 = Op.getOperand(1);
12124 if (isZeroShuffle(SVOp))
12125 return getZeroVector(VT, Subtarget, DAG, dl);
12127 // Handle splat operations
12128 if (SVOp->isSplat()) {
12129 // Use vbroadcast whenever the splat comes from a foldable load
12130 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12131 if (Broadcast.getNode())
12135 // Check integer expanding shuffles.
12136 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12137 if (NewOp.getNode())
12140 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12142 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12143 VT == MVT::v32i8) {
12144 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12145 if (NewOp.getNode())
12146 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12147 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12148 // FIXME: Figure out a cleaner way to do this.
12149 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12150 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12151 if (NewOp.getNode()) {
12152 MVT NewVT = NewOp.getSimpleValueType();
12153 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12154 NewVT, true, false))
12155 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12158 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12159 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12160 if (NewOp.getNode()) {
12161 MVT NewVT = NewOp.getSimpleValueType();
12162 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12163 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12172 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12173 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12174 SDValue V1 = Op.getOperand(0);
12175 SDValue V2 = Op.getOperand(1);
12176 MVT VT = Op.getSimpleValueType();
12178 unsigned NumElems = VT.getVectorNumElements();
12179 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12180 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12181 bool V1IsSplat = false;
12182 bool V2IsSplat = false;
12183 bool HasSSE2 = Subtarget->hasSSE2();
12184 bool HasFp256 = Subtarget->hasFp256();
12185 bool HasInt256 = Subtarget->hasInt256();
12186 MachineFunction &MF = DAG.getMachineFunction();
12187 bool OptForSize = MF.getFunction()->getAttributes().
12188 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12190 // Check if we should use the experimental vector shuffle lowering. If so,
12191 // delegate completely to that code path.
12192 if (ExperimentalVectorShuffleLowering)
12193 return lowerVectorShuffle(Op, Subtarget, DAG);
12195 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12197 if (V1IsUndef && V2IsUndef)
12198 return DAG.getUNDEF(VT);
12200 // When we create a shuffle node we put the UNDEF node to second operand,
12201 // but in some cases the first operand may be transformed to UNDEF.
12202 // In this case we should just commute the node.
12204 return DAG.getCommutedVectorShuffle(*SVOp);
12206 // Vector shuffle lowering takes 3 steps:
12208 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12209 // narrowing and commutation of operands should be handled.
12210 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12212 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12213 // so the shuffle can be broken into other shuffles and the legalizer can
12214 // try the lowering again.
12216 // The general idea is that no vector_shuffle operation should be left to
12217 // be matched during isel, all of them must be converted to a target specific
12220 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12221 // narrowing and commutation of operands should be handled. The actual code
12222 // doesn't include all of those, work in progress...
12223 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12224 if (NewOp.getNode())
12227 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12229 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12230 // unpckh_undef). Only use pshufd if speed is more important than size.
12231 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12232 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12233 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12234 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12236 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12237 V2IsUndef && MayFoldVectorLoad(V1))
12238 return getMOVDDup(Op, dl, V1, DAG);
12240 if (isMOVHLPS_v_undef_Mask(M, VT))
12241 return getMOVHighToLow(Op, dl, DAG);
12243 // Use to match splats
12244 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12245 (VT == MVT::v2f64 || VT == MVT::v2i64))
12246 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12248 if (isPSHUFDMask(M, VT)) {
12249 // The actual implementation will match the mask in the if above and then
12250 // during isel it can match several different instructions, not only pshufd
12251 // as its name says, sad but true, emulate the behavior for now...
12252 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12253 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12255 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12257 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12258 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12260 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12261 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12264 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12268 if (isPALIGNRMask(M, VT, Subtarget))
12269 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12270 getShufflePALIGNRImmediate(SVOp),
12273 if (isVALIGNMask(M, VT, Subtarget))
12274 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12275 getShuffleVALIGNImmediate(SVOp),
12278 // Check if this can be converted into a logical shift.
12279 bool isLeft = false;
12280 unsigned ShAmt = 0;
12282 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12283 if (isShift && ShVal.hasOneUse()) {
12284 // If the shifted value has multiple uses, it may be cheaper to use
12285 // v_set0 + movlhps or movhlps, etc.
12286 MVT EltVT = VT.getVectorElementType();
12287 ShAmt *= EltVT.getSizeInBits();
12288 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12291 if (isMOVLMask(M, VT)) {
12292 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12293 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12294 if (!isMOVLPMask(M, VT)) {
12295 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12296 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12298 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12299 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12303 // FIXME: fold these into legal mask.
12304 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12305 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12307 if (isMOVHLPSMask(M, VT))
12308 return getMOVHighToLow(Op, dl, DAG);
12310 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12311 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12313 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12314 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12316 if (isMOVLPMask(M, VT))
12317 return getMOVLP(Op, dl, DAG, HasSSE2);
12319 if (ShouldXformToMOVHLPS(M, VT) ||
12320 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12321 return DAG.getCommutedVectorShuffle(*SVOp);
12324 // No better options. Use a vshldq / vsrldq.
12325 MVT EltVT = VT.getVectorElementType();
12326 ShAmt *= EltVT.getSizeInBits();
12327 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12330 bool Commuted = false;
12331 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12332 // 1,1,1,1 -> v8i16 though.
12333 BitVector UndefElements;
12334 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12335 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12337 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12338 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12341 // Canonicalize the splat or undef, if present, to be on the RHS.
12342 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12343 CommuteVectorShuffleMask(M, NumElems);
12345 std::swap(V1IsSplat, V2IsSplat);
12349 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12350 // Shuffling low element of v1 into undef, just return v1.
12353 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12354 // the instruction selector will not match, so get a canonical MOVL with
12355 // swapped operands to undo the commute.
12356 return getMOVL(DAG, dl, VT, V2, V1);
12359 if (isUNPCKLMask(M, VT, HasInt256))
12360 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12362 if (isUNPCKHMask(M, VT, HasInt256))
12363 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12366 // Normalize mask so all entries that point to V2 points to its first
12367 // element then try to match unpck{h|l} again. If match, return a
12368 // new vector_shuffle with the corrected mask.p
12369 SmallVector<int, 8> NewMask(M.begin(), M.end());
12370 NormalizeMask(NewMask, NumElems);
12371 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12372 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12373 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12374 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12378 // Commute is back and try unpck* again.
12379 // FIXME: this seems wrong.
12380 CommuteVectorShuffleMask(M, NumElems);
12382 std::swap(V1IsSplat, V2IsSplat);
12384 if (isUNPCKLMask(M, VT, HasInt256))
12385 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12387 if (isUNPCKHMask(M, VT, HasInt256))
12388 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12391 // Normalize the node to match x86 shuffle ops if needed
12392 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12393 return DAG.getCommutedVectorShuffle(*SVOp);
12395 // The checks below are all present in isShuffleMaskLegal, but they are
12396 // inlined here right now to enable us to directly emit target specific
12397 // nodes, and remove one by one until they don't return Op anymore.
12399 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12400 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12401 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12402 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12405 if (isPSHUFHWMask(M, VT, HasInt256))
12406 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12407 getShufflePSHUFHWImmediate(SVOp),
12410 if (isPSHUFLWMask(M, VT, HasInt256))
12411 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12412 getShufflePSHUFLWImmediate(SVOp),
12415 unsigned MaskValue;
12416 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12418 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12420 if (isSHUFPMask(M, VT))
12421 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12422 getShuffleSHUFImmediate(SVOp), DAG);
12424 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12425 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12426 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12427 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12429 //===--------------------------------------------------------------------===//
12430 // Generate target specific nodes for 128 or 256-bit shuffles only
12431 // supported in the AVX instruction set.
12434 // Handle VMOVDDUPY permutations
12435 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12436 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12438 // Handle VPERMILPS/D* permutations
12439 if (isVPERMILPMask(M, VT)) {
12440 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12441 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12442 getShuffleSHUFImmediate(SVOp), DAG);
12443 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12444 getShuffleSHUFImmediate(SVOp), DAG);
12448 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12449 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12450 Idx*(NumElems/2), DAG, dl);
12452 // Handle VPERM2F128/VPERM2I128 permutations
12453 if (isVPERM2X128Mask(M, VT, HasFp256))
12454 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12455 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12457 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12458 return getINSERTPS(SVOp, dl, DAG);
12461 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12462 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12464 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12465 VT.is512BitVector()) {
12466 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12467 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12468 SmallVector<SDValue, 16> permclMask;
12469 for (unsigned i = 0; i != NumElems; ++i) {
12470 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12473 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12475 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12476 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12477 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12478 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12479 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12482 //===--------------------------------------------------------------------===//
12483 // Since no target specific shuffle was selected for this generic one,
12484 // lower it into other known shuffles. FIXME: this isn't true yet, but
12485 // this is the plan.
12488 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12489 if (VT == MVT::v8i16) {
12490 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12491 if (NewOp.getNode())
12495 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12496 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12497 if (NewOp.getNode())
12501 if (VT == MVT::v16i8) {
12502 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12503 if (NewOp.getNode())
12507 if (VT == MVT::v32i8) {
12508 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12509 if (NewOp.getNode())
12513 // Handle all 128-bit wide vectors with 4 elements, and match them with
12514 // several different shuffle types.
12515 if (NumElems == 4 && VT.is128BitVector())
12516 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12518 // Handle general 256-bit shuffles
12519 if (VT.is256BitVector())
12520 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12525 // This function assumes its argument is a BUILD_VECTOR of constants or
12526 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12528 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12529 unsigned &MaskValue) {
12531 unsigned NumElems = BuildVector->getNumOperands();
12532 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12533 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12534 unsigned NumElemsInLane = NumElems / NumLanes;
12536 // Blend for v16i16 should be symetric for the both lanes.
12537 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12538 SDValue EltCond = BuildVector->getOperand(i);
12539 SDValue SndLaneEltCond =
12540 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12542 int Lane1Cond = -1, Lane2Cond = -1;
12543 if (isa<ConstantSDNode>(EltCond))
12544 Lane1Cond = !isZero(EltCond);
12545 if (isa<ConstantSDNode>(SndLaneEltCond))
12546 Lane2Cond = !isZero(SndLaneEltCond);
12548 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12549 // Lane1Cond != 0, means we want the first argument.
12550 // Lane1Cond == 0, means we want the second argument.
12551 // The encoding of this argument is 0 for the first argument, 1
12552 // for the second. Therefore, invert the condition.
12553 MaskValue |= !Lane1Cond << i;
12554 else if (Lane1Cond < 0)
12555 MaskValue |= !Lane2Cond << i;
12562 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12564 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12565 SelectionDAG &DAG) {
12566 SDValue Cond = Op.getOperand(0);
12567 SDValue LHS = Op.getOperand(1);
12568 SDValue RHS = Op.getOperand(2);
12570 MVT VT = Op.getSimpleValueType();
12571 MVT EltVT = VT.getVectorElementType();
12572 unsigned NumElems = VT.getVectorNumElements();
12574 // There is no blend with immediate in AVX-512.
12575 if (VT.is512BitVector())
12578 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12580 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12583 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12586 // Check the mask for BLEND and build the value.
12587 unsigned MaskValue = 0;
12588 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12591 // Convert i32 vectors to floating point if it is not AVX2.
12592 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12594 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12595 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12597 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12598 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12601 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12602 DAG.getConstant(MaskValue, MVT::i32));
12603 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12606 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12607 // A vselect where all conditions and data are constants can be optimized into
12608 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12609 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12610 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12611 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12614 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12615 if (BlendOp.getNode())
12618 // Some types for vselect were previously set to Expand, not Legal or
12619 // Custom. Return an empty SDValue so we fall-through to Expand, after
12620 // the Custom lowering phase.
12621 MVT VT = Op.getSimpleValueType();
12622 switch (VT.SimpleTy) {
12627 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12632 // We couldn't create a "Blend with immediate" node.
12633 // This node should still be legal, but we'll have to emit a blendv*
12638 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12639 MVT VT = Op.getSimpleValueType();
12642 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12645 if (VT.getSizeInBits() == 8) {
12646 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12647 Op.getOperand(0), Op.getOperand(1));
12648 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12649 DAG.getValueType(VT));
12650 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12653 if (VT.getSizeInBits() == 16) {
12654 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12655 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12657 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12659 DAG.getNode(ISD::BITCAST, dl,
12662 Op.getOperand(1)));
12663 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12664 Op.getOperand(0), Op.getOperand(1));
12665 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12666 DAG.getValueType(VT));
12667 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12670 if (VT == MVT::f32) {
12671 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12672 // the result back to FR32 register. It's only worth matching if the
12673 // result has a single use which is a store or a bitcast to i32. And in
12674 // the case of a store, it's not worth it if the index is a constant 0,
12675 // because a MOVSSmr can be used instead, which is smaller and faster.
12676 if (!Op.hasOneUse())
12678 SDNode *User = *Op.getNode()->use_begin();
12679 if ((User->getOpcode() != ISD::STORE ||
12680 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12681 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12682 (User->getOpcode() != ISD::BITCAST ||
12683 User->getValueType(0) != MVT::i32))
12685 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12686 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12689 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12692 if (VT == MVT::i32 || VT == MVT::i64) {
12693 // ExtractPS/pextrq works with constant index.
12694 if (isa<ConstantSDNode>(Op.getOperand(1)))
12700 /// Extract one bit from mask vector, like v16i1 or v8i1.
12701 /// AVX-512 feature.
12703 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12704 SDValue Vec = Op.getOperand(0);
12706 MVT VecVT = Vec.getSimpleValueType();
12707 SDValue Idx = Op.getOperand(1);
12708 MVT EltVT = Op.getSimpleValueType();
12710 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12712 // variable index can't be handled in mask registers,
12713 // extend vector to VR512
12714 if (!isa<ConstantSDNode>(Idx)) {
12715 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12716 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12717 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12718 ExtVT.getVectorElementType(), Ext, Idx);
12719 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12722 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12723 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12724 unsigned MaxSift = rc->getSize()*8 - 1;
12725 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12726 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12727 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12728 DAG.getConstant(MaxSift, MVT::i8));
12729 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12730 DAG.getIntPtrConstant(0));
12734 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12735 SelectionDAG &DAG) const {
12737 SDValue Vec = Op.getOperand(0);
12738 MVT VecVT = Vec.getSimpleValueType();
12739 SDValue Idx = Op.getOperand(1);
12741 if (Op.getSimpleValueType() == MVT::i1)
12742 return ExtractBitFromMaskVector(Op, DAG);
12744 if (!isa<ConstantSDNode>(Idx)) {
12745 if (VecVT.is512BitVector() ||
12746 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12747 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12750 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12751 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12752 MaskEltVT.getSizeInBits());
12754 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12755 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12756 getZeroVector(MaskVT, Subtarget, DAG, dl),
12757 Idx, DAG.getConstant(0, getPointerTy()));
12758 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12759 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12760 Perm, DAG.getConstant(0, getPointerTy()));
12765 // If this is a 256-bit vector result, first extract the 128-bit vector and
12766 // then extract the element from the 128-bit vector.
12767 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12769 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12770 // Get the 128-bit vector.
12771 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12772 MVT EltVT = VecVT.getVectorElementType();
12774 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12776 //if (IdxVal >= NumElems/2)
12777 // IdxVal -= NumElems/2;
12778 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12779 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12780 DAG.getConstant(IdxVal, MVT::i32));
12783 assert(VecVT.is128BitVector() && "Unexpected vector length");
12785 if (Subtarget->hasSSE41()) {
12786 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12791 MVT VT = Op.getSimpleValueType();
12792 // TODO: handle v16i8.
12793 if (VT.getSizeInBits() == 16) {
12794 SDValue Vec = Op.getOperand(0);
12795 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12797 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12798 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12799 DAG.getNode(ISD::BITCAST, dl,
12801 Op.getOperand(1)));
12802 // Transform it so it match pextrw which produces a 32-bit result.
12803 MVT EltVT = MVT::i32;
12804 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12805 Op.getOperand(0), Op.getOperand(1));
12806 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12807 DAG.getValueType(VT));
12808 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12811 if (VT.getSizeInBits() == 32) {
12812 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12816 // SHUFPS the element to the lowest double word, then movss.
12817 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12818 MVT VVT = Op.getOperand(0).getSimpleValueType();
12819 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12820 DAG.getUNDEF(VVT), Mask);
12821 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12822 DAG.getIntPtrConstant(0));
12825 if (VT.getSizeInBits() == 64) {
12826 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12827 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12828 // to match extract_elt for f64.
12829 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12833 // UNPCKHPD the element to the lowest double word, then movsd.
12834 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12835 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12836 int Mask[2] = { 1, -1 };
12837 MVT VVT = Op.getOperand(0).getSimpleValueType();
12838 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12839 DAG.getUNDEF(VVT), Mask);
12840 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12841 DAG.getIntPtrConstant(0));
12847 /// Insert one bit to mask vector, like v16i1 or v8i1.
12848 /// AVX-512 feature.
12850 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12852 SDValue Vec = Op.getOperand(0);
12853 SDValue Elt = Op.getOperand(1);
12854 SDValue Idx = Op.getOperand(2);
12855 MVT VecVT = Vec.getSimpleValueType();
12857 if (!isa<ConstantSDNode>(Idx)) {
12858 // Non constant index. Extend source and destination,
12859 // insert element and then truncate the result.
12860 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12861 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12862 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12863 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12864 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12865 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12868 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12869 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12870 if (Vec.getOpcode() == ISD::UNDEF)
12871 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12872 DAG.getConstant(IdxVal, MVT::i8));
12873 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12874 unsigned MaxSift = rc->getSize()*8 - 1;
12875 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12876 DAG.getConstant(MaxSift, MVT::i8));
12877 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12878 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12879 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12882 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12883 SelectionDAG &DAG) const {
12884 MVT VT = Op.getSimpleValueType();
12885 MVT EltVT = VT.getVectorElementType();
12887 if (EltVT == MVT::i1)
12888 return InsertBitToMaskVector(Op, DAG);
12891 SDValue N0 = Op.getOperand(0);
12892 SDValue N1 = Op.getOperand(1);
12893 SDValue N2 = Op.getOperand(2);
12894 if (!isa<ConstantSDNode>(N2))
12896 auto *N2C = cast<ConstantSDNode>(N2);
12897 unsigned IdxVal = N2C->getZExtValue();
12899 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12900 // into that, and then insert the subvector back into the result.
12901 if (VT.is256BitVector() || VT.is512BitVector()) {
12902 // Get the desired 128-bit vector half.
12903 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12905 // Insert the element into the desired half.
12906 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12907 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12909 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12910 DAG.getConstant(IdxIn128, MVT::i32));
12912 // Insert the changed part back to the 256-bit vector
12913 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12915 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12917 if (Subtarget->hasSSE41()) {
12918 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12920 if (VT == MVT::v8i16) {
12921 Opc = X86ISD::PINSRW;
12923 assert(VT == MVT::v16i8);
12924 Opc = X86ISD::PINSRB;
12927 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12929 if (N1.getValueType() != MVT::i32)
12930 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12931 if (N2.getValueType() != MVT::i32)
12932 N2 = DAG.getIntPtrConstant(IdxVal);
12933 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12936 if (EltVT == MVT::f32) {
12937 // Bits [7:6] of the constant are the source select. This will always be
12938 // zero here. The DAG Combiner may combine an extract_elt index into
12940 // bits. For example (insert (extract, 3), 2) could be matched by
12942 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12943 // Bits [5:4] of the constant are the destination select. This is the
12944 // value of the incoming immediate.
12945 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12946 // combine either bitwise AND or insert of float 0.0 to set these bits.
12947 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12948 // Create this as a scalar to vector..
12949 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12950 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12953 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12954 // PINSR* works with constant index.
12959 if (EltVT == MVT::i8)
12962 if (EltVT.getSizeInBits() == 16) {
12963 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12964 // as its second argument.
12965 if (N1.getValueType() != MVT::i32)
12966 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12967 if (N2.getValueType() != MVT::i32)
12968 N2 = DAG.getIntPtrConstant(IdxVal);
12969 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12974 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12976 MVT OpVT = Op.getSimpleValueType();
12978 // If this is a 256-bit vector result, first insert into a 128-bit
12979 // vector and then insert into the 256-bit vector.
12980 if (!OpVT.is128BitVector()) {
12981 // Insert into a 128-bit vector.
12982 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12983 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12984 OpVT.getVectorNumElements() / SizeFactor);
12986 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12988 // Insert the 128-bit vector.
12989 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12992 if (OpVT == MVT::v1i64 &&
12993 Op.getOperand(0).getValueType() == MVT::i64)
12994 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12996 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12997 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12998 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12999 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
13002 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
13003 // a simple subregister reference or explicit instructions to grab
13004 // upper bits of a vector.
13005 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13006 SelectionDAG &DAG) {
13008 SDValue In = Op.getOperand(0);
13009 SDValue Idx = Op.getOperand(1);
13010 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13011 MVT ResVT = Op.getSimpleValueType();
13012 MVT InVT = In.getSimpleValueType();
13014 if (Subtarget->hasFp256()) {
13015 if (ResVT.is128BitVector() &&
13016 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13017 isa<ConstantSDNode>(Idx)) {
13018 return Extract128BitVector(In, IdxVal, DAG, dl);
13020 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13021 isa<ConstantSDNode>(Idx)) {
13022 return Extract256BitVector(In, IdxVal, DAG, dl);
13028 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13029 // simple superregister reference or explicit instructions to insert
13030 // the upper bits of a vector.
13031 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13032 SelectionDAG &DAG) {
13033 if (Subtarget->hasFp256()) {
13034 SDLoc dl(Op.getNode());
13035 SDValue Vec = Op.getNode()->getOperand(0);
13036 SDValue SubVec = Op.getNode()->getOperand(1);
13037 SDValue Idx = Op.getNode()->getOperand(2);
13039 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13040 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13041 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13042 isa<ConstantSDNode>(Idx)) {
13043 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13044 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13047 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13048 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13049 isa<ConstantSDNode>(Idx)) {
13050 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13051 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13057 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13058 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13059 // one of the above mentioned nodes. It has to be wrapped because otherwise
13060 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13061 // be used to form addressing mode. These wrapped nodes will be selected
13064 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13065 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13067 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13068 // global base reg.
13069 unsigned char OpFlag = 0;
13070 unsigned WrapperKind = X86ISD::Wrapper;
13071 CodeModel::Model M = DAG.getTarget().getCodeModel();
13073 if (Subtarget->isPICStyleRIPRel() &&
13074 (M == CodeModel::Small || M == CodeModel::Kernel))
13075 WrapperKind = X86ISD::WrapperRIP;
13076 else if (Subtarget->isPICStyleGOT())
13077 OpFlag = X86II::MO_GOTOFF;
13078 else if (Subtarget->isPICStyleStubPIC())
13079 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13081 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13082 CP->getAlignment(),
13083 CP->getOffset(), OpFlag);
13085 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13086 // With PIC, the address is actually $g + Offset.
13088 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13089 DAG.getNode(X86ISD::GlobalBaseReg,
13090 SDLoc(), getPointerTy()),
13097 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13098 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13100 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13101 // global base reg.
13102 unsigned char OpFlag = 0;
13103 unsigned WrapperKind = X86ISD::Wrapper;
13104 CodeModel::Model M = DAG.getTarget().getCodeModel();
13106 if (Subtarget->isPICStyleRIPRel() &&
13107 (M == CodeModel::Small || M == CodeModel::Kernel))
13108 WrapperKind = X86ISD::WrapperRIP;
13109 else if (Subtarget->isPICStyleGOT())
13110 OpFlag = X86II::MO_GOTOFF;
13111 else if (Subtarget->isPICStyleStubPIC())
13112 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13114 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13117 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13119 // With PIC, the address is actually $g + Offset.
13121 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13122 DAG.getNode(X86ISD::GlobalBaseReg,
13123 SDLoc(), getPointerTy()),
13130 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13131 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13133 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13134 // global base reg.
13135 unsigned char OpFlag = 0;
13136 unsigned WrapperKind = X86ISD::Wrapper;
13137 CodeModel::Model M = DAG.getTarget().getCodeModel();
13139 if (Subtarget->isPICStyleRIPRel() &&
13140 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13141 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13142 OpFlag = X86II::MO_GOTPCREL;
13143 WrapperKind = X86ISD::WrapperRIP;
13144 } else if (Subtarget->isPICStyleGOT()) {
13145 OpFlag = X86II::MO_GOT;
13146 } else if (Subtarget->isPICStyleStubPIC()) {
13147 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13148 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13149 OpFlag = X86II::MO_DARWIN_NONLAZY;
13152 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13155 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13157 // With PIC, the address is actually $g + Offset.
13158 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13159 !Subtarget->is64Bit()) {
13160 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13161 DAG.getNode(X86ISD::GlobalBaseReg,
13162 SDLoc(), getPointerTy()),
13166 // For symbols that require a load from a stub to get the address, emit the
13168 if (isGlobalStubReference(OpFlag))
13169 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13170 MachinePointerInfo::getGOT(), false, false, false, 0);
13176 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13177 // Create the TargetBlockAddressAddress node.
13178 unsigned char OpFlags =
13179 Subtarget->ClassifyBlockAddressReference();
13180 CodeModel::Model M = DAG.getTarget().getCodeModel();
13181 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13182 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13184 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13187 if (Subtarget->isPICStyleRIPRel() &&
13188 (M == CodeModel::Small || M == CodeModel::Kernel))
13189 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13191 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13193 // With PIC, the address is actually $g + Offset.
13194 if (isGlobalRelativeToPICBase(OpFlags)) {
13195 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13196 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13204 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13205 int64_t Offset, SelectionDAG &DAG) const {
13206 // Create the TargetGlobalAddress node, folding in the constant
13207 // offset if it is legal.
13208 unsigned char OpFlags =
13209 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13210 CodeModel::Model M = DAG.getTarget().getCodeModel();
13212 if (OpFlags == X86II::MO_NO_FLAG &&
13213 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13214 // A direct static reference to a global.
13215 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13218 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13221 if (Subtarget->isPICStyleRIPRel() &&
13222 (M == CodeModel::Small || M == CodeModel::Kernel))
13223 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13225 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13227 // With PIC, the address is actually $g + Offset.
13228 if (isGlobalRelativeToPICBase(OpFlags)) {
13229 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13230 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13234 // For globals that require a load from a stub to get the address, emit the
13236 if (isGlobalStubReference(OpFlags))
13237 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13238 MachinePointerInfo::getGOT(), false, false, false, 0);
13240 // If there was a non-zero offset that we didn't fold, create an explicit
13241 // addition for it.
13243 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13244 DAG.getConstant(Offset, getPointerTy()));
13250 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13251 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13252 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13253 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13257 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13258 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13259 unsigned char OperandFlags, bool LocalDynamic = false) {
13260 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13261 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13263 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13264 GA->getValueType(0),
13268 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13272 SDValue Ops[] = { Chain, TGA, *InFlag };
13273 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13275 SDValue Ops[] = { Chain, TGA };
13276 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13279 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13280 MFI->setAdjustsStack(true);
13281 MFI->setHasCalls(true);
13283 SDValue Flag = Chain.getValue(1);
13284 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13287 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13289 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13292 SDLoc dl(GA); // ? function entry point might be better
13293 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13294 DAG.getNode(X86ISD::GlobalBaseReg,
13295 SDLoc(), PtrVT), InFlag);
13296 InFlag = Chain.getValue(1);
13298 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13301 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13303 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13305 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13306 X86::RAX, X86II::MO_TLSGD);
13309 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13315 // Get the start address of the TLS block for this module.
13316 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13317 .getInfo<X86MachineFunctionInfo>();
13318 MFI->incNumLocalDynamicTLSAccesses();
13322 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13323 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13326 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13327 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13328 InFlag = Chain.getValue(1);
13329 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13330 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13333 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13337 unsigned char OperandFlags = X86II::MO_DTPOFF;
13338 unsigned WrapperKind = X86ISD::Wrapper;
13339 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13340 GA->getValueType(0),
13341 GA->getOffset(), OperandFlags);
13342 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13344 // Add x@dtpoff with the base.
13345 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13348 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13349 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13350 const EVT PtrVT, TLSModel::Model model,
13351 bool is64Bit, bool isPIC) {
13354 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13355 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13356 is64Bit ? 257 : 256));
13358 SDValue ThreadPointer =
13359 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13360 MachinePointerInfo(Ptr), false, false, false, 0);
13362 unsigned char OperandFlags = 0;
13363 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13365 unsigned WrapperKind = X86ISD::Wrapper;
13366 if (model == TLSModel::LocalExec) {
13367 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13368 } else if (model == TLSModel::InitialExec) {
13370 OperandFlags = X86II::MO_GOTTPOFF;
13371 WrapperKind = X86ISD::WrapperRIP;
13373 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13376 llvm_unreachable("Unexpected model");
13379 // emit "addl x@ntpoff,%eax" (local exec)
13380 // or "addl x@indntpoff,%eax" (initial exec)
13381 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13383 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13384 GA->getOffset(), OperandFlags);
13385 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13387 if (model == TLSModel::InitialExec) {
13388 if (isPIC && !is64Bit) {
13389 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13390 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13394 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13395 MachinePointerInfo::getGOT(), false, false, false, 0);
13398 // The address of the thread local variable is the add of the thread
13399 // pointer with the offset of the variable.
13400 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13404 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13406 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13407 const GlobalValue *GV = GA->getGlobal();
13409 if (Subtarget->isTargetELF()) {
13410 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13413 case TLSModel::GeneralDynamic:
13414 if (Subtarget->is64Bit())
13415 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13416 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13417 case TLSModel::LocalDynamic:
13418 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13419 Subtarget->is64Bit());
13420 case TLSModel::InitialExec:
13421 case TLSModel::LocalExec:
13422 return LowerToTLSExecModel(
13423 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13424 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13426 llvm_unreachable("Unknown TLS model.");
13429 if (Subtarget->isTargetDarwin()) {
13430 // Darwin only has one model of TLS. Lower to that.
13431 unsigned char OpFlag = 0;
13432 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13433 X86ISD::WrapperRIP : X86ISD::Wrapper;
13435 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13436 // global base reg.
13437 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13438 !Subtarget->is64Bit();
13440 OpFlag = X86II::MO_TLVP_PIC_BASE;
13442 OpFlag = X86II::MO_TLVP;
13444 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13445 GA->getValueType(0),
13446 GA->getOffset(), OpFlag);
13447 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13449 // With PIC32, the address is actually $g + Offset.
13451 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13452 DAG.getNode(X86ISD::GlobalBaseReg,
13453 SDLoc(), getPointerTy()),
13456 // Lowering the machine isd will make sure everything is in the right
13458 SDValue Chain = DAG.getEntryNode();
13459 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13460 SDValue Args[] = { Chain, Offset };
13461 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13463 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13464 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13465 MFI->setAdjustsStack(true);
13467 // And our return value (tls address) is in the standard call return value
13469 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13470 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13471 Chain.getValue(1));
13474 if (Subtarget->isTargetKnownWindowsMSVC() ||
13475 Subtarget->isTargetWindowsGNU()) {
13476 // Just use the implicit TLS architecture
13477 // Need to generate someting similar to:
13478 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13480 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13481 // mov rcx, qword [rdx+rcx*8]
13482 // mov eax, .tls$:tlsvar
13483 // [rax+rcx] contains the address
13484 // Windows 64bit: gs:0x58
13485 // Windows 32bit: fs:__tls_array
13488 SDValue Chain = DAG.getEntryNode();
13490 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13491 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13492 // use its literal value of 0x2C.
13493 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13494 ? Type::getInt8PtrTy(*DAG.getContext(),
13496 : Type::getInt32PtrTy(*DAG.getContext(),
13500 Subtarget->is64Bit()
13501 ? DAG.getIntPtrConstant(0x58)
13502 : (Subtarget->isTargetWindowsGNU()
13503 ? DAG.getIntPtrConstant(0x2C)
13504 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13506 SDValue ThreadPointer =
13507 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13508 MachinePointerInfo(Ptr), false, false, false, 0);
13510 // Load the _tls_index variable
13511 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13512 if (Subtarget->is64Bit())
13513 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13514 IDX, MachinePointerInfo(), MVT::i32,
13515 false, false, false, 0);
13517 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13518 false, false, false, 0);
13520 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13522 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13524 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13525 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13526 false, false, false, 0);
13528 // Get the offset of start of .tls section
13529 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13530 GA->getValueType(0),
13531 GA->getOffset(), X86II::MO_SECREL);
13532 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13534 // The address of the thread local variable is the add of the thread
13535 // pointer with the offset of the variable.
13536 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13539 llvm_unreachable("TLS not implemented for this target.");
13542 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13543 /// and take a 2 x i32 value to shift plus a shift amount.
13544 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13545 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13546 MVT VT = Op.getSimpleValueType();
13547 unsigned VTBits = VT.getSizeInBits();
13549 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13550 SDValue ShOpLo = Op.getOperand(0);
13551 SDValue ShOpHi = Op.getOperand(1);
13552 SDValue ShAmt = Op.getOperand(2);
13553 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13554 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13556 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13557 DAG.getConstant(VTBits - 1, MVT::i8));
13558 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13559 DAG.getConstant(VTBits - 1, MVT::i8))
13560 : DAG.getConstant(0, VT);
13562 SDValue Tmp2, Tmp3;
13563 if (Op.getOpcode() == ISD::SHL_PARTS) {
13564 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13565 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13567 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13568 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13571 // If the shift amount is larger or equal than the width of a part we can't
13572 // rely on the results of shld/shrd. Insert a test and select the appropriate
13573 // values for large shift amounts.
13574 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13575 DAG.getConstant(VTBits, MVT::i8));
13576 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13577 AndNode, DAG.getConstant(0, MVT::i8));
13580 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13581 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13582 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13584 if (Op.getOpcode() == ISD::SHL_PARTS) {
13585 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13586 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13588 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13589 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13592 SDValue Ops[2] = { Lo, Hi };
13593 return DAG.getMergeValues(Ops, dl);
13596 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13597 SelectionDAG &DAG) const {
13598 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13601 if (SrcVT.isVector()) {
13602 if (SrcVT.getVectorElementType() == MVT::i1) {
13603 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13604 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13605 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13606 Op.getOperand(0)));
13611 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13612 "Unknown SINT_TO_FP to lower!");
13614 // These are really Legal; return the operand so the caller accepts it as
13616 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13618 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13619 Subtarget->is64Bit()) {
13623 unsigned Size = SrcVT.getSizeInBits()/8;
13624 MachineFunction &MF = DAG.getMachineFunction();
13625 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13626 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13627 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13629 MachinePointerInfo::getFixedStack(SSFI),
13631 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13634 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13636 SelectionDAG &DAG) const {
13640 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13642 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13644 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13646 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13648 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13649 MachineMemOperand *MMO;
13651 int SSFI = FI->getIndex();
13653 DAG.getMachineFunction()
13654 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13655 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13657 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13658 StackSlot = StackSlot.getOperand(1);
13660 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13661 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13663 Tys, Ops, SrcVT, MMO);
13666 Chain = Result.getValue(1);
13667 SDValue InFlag = Result.getValue(2);
13669 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13670 // shouldn't be necessary except that RFP cannot be live across
13671 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13672 MachineFunction &MF = DAG.getMachineFunction();
13673 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13674 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13675 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13676 Tys = DAG.getVTList(MVT::Other);
13678 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13680 MachineMemOperand *MMO =
13681 DAG.getMachineFunction()
13682 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13683 MachineMemOperand::MOStore, SSFISize, SSFISize);
13685 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13686 Ops, Op.getValueType(), MMO);
13687 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13688 MachinePointerInfo::getFixedStack(SSFI),
13689 false, false, false, 0);
13695 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13696 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13697 SelectionDAG &DAG) const {
13698 // This algorithm is not obvious. Here it is what we're trying to output:
13701 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13702 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13704 haddpd %xmm0, %xmm0
13706 pshufd $0x4e, %xmm0, %xmm1
13712 LLVMContext *Context = DAG.getContext();
13714 // Build some magic constants.
13715 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13716 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13717 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13719 SmallVector<Constant*,2> CV1;
13721 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13722 APInt(64, 0x4330000000000000ULL))));
13724 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13725 APInt(64, 0x4530000000000000ULL))));
13726 Constant *C1 = ConstantVector::get(CV1);
13727 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13729 // Load the 64-bit value into an XMM register.
13730 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13732 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13733 MachinePointerInfo::getConstantPool(),
13734 false, false, false, 16);
13735 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13736 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13739 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13740 MachinePointerInfo::getConstantPool(),
13741 false, false, false, 16);
13742 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13743 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13746 if (Subtarget->hasSSE3()) {
13747 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13748 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13750 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13751 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13753 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13754 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13758 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13759 DAG.getIntPtrConstant(0));
13762 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13763 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13764 SelectionDAG &DAG) const {
13766 // FP constant to bias correct the final result.
13767 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13770 // Load the 32-bit value into an XMM register.
13771 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13774 // Zero out the upper parts of the register.
13775 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13777 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13778 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13779 DAG.getIntPtrConstant(0));
13781 // Or the load with the bias.
13782 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13783 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13784 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13785 MVT::v2f64, Load)),
13786 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13787 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13788 MVT::v2f64, Bias)));
13789 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13790 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13791 DAG.getIntPtrConstant(0));
13793 // Subtract the bias.
13794 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13796 // Handle final rounding.
13797 EVT DestVT = Op.getValueType();
13799 if (DestVT.bitsLT(MVT::f64))
13800 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13801 DAG.getIntPtrConstant(0));
13802 if (DestVT.bitsGT(MVT::f64))
13803 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13805 // Handle final rounding.
13809 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13810 const X86Subtarget &Subtarget) {
13811 // The algorithm is the following:
13812 // #ifdef __SSE4_1__
13813 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13814 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13815 // (uint4) 0x53000000, 0xaa);
13817 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13818 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13820 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13821 // return (float4) lo + fhi;
13824 SDValue V = Op->getOperand(0);
13825 EVT VecIntVT = V.getValueType();
13826 bool Is128 = VecIntVT == MVT::v4i32;
13827 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13828 // If we convert to something else than the supported type, e.g., to v4f64,
13830 if (VecFloatVT != Op->getValueType(0))
13833 unsigned NumElts = VecIntVT.getVectorNumElements();
13834 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13835 "Unsupported custom type");
13836 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13838 // In the #idef/#else code, we have in common:
13839 // - The vector of constants:
13845 // Create the splat vector for 0x4b000000.
13846 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13847 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13848 CstLow, CstLow, CstLow, CstLow};
13849 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13850 makeArrayRef(&CstLowArray[0], NumElts));
13851 // Create the splat vector for 0x53000000.
13852 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13853 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13854 CstHigh, CstHigh, CstHigh, CstHigh};
13855 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13856 makeArrayRef(&CstHighArray[0], NumElts));
13858 // Create the right shift.
13859 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13860 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13861 CstShift, CstShift, CstShift, CstShift};
13862 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13863 makeArrayRef(&CstShiftArray[0], NumElts));
13864 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13867 if (Subtarget.hasSSE41()) {
13868 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13869 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13870 SDValue VecCstLowBitcast =
13871 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13872 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13873 // Low will be bitcasted right away, so do not bother bitcasting back to its
13875 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13876 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13877 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13878 // (uint4) 0x53000000, 0xaa);
13879 SDValue VecCstHighBitcast =
13880 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13881 SDValue VecShiftBitcast =
13882 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13883 // High will be bitcasted right away, so do not bother bitcasting back to
13884 // its original type.
13885 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13886 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13888 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13889 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13890 CstMask, CstMask, CstMask);
13891 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13892 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13893 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13895 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13896 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13899 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13900 SDValue CstFAdd = DAG.getConstantFP(
13901 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13902 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13903 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13904 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13905 makeArrayRef(&CstFAddArray[0], NumElts));
13907 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13908 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13910 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13911 // return (float4) lo + fhi;
13912 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13913 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13916 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13917 SelectionDAG &DAG) const {
13918 SDValue N0 = Op.getOperand(0);
13919 MVT SVT = N0.getSimpleValueType();
13922 switch (SVT.SimpleTy) {
13924 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13929 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13930 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13931 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13935 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13937 llvm_unreachable(nullptr);
13940 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13941 SelectionDAG &DAG) const {
13942 SDValue N0 = Op.getOperand(0);
13945 if (Op.getValueType().isVector())
13946 return lowerUINT_TO_FP_vec(Op, DAG);
13948 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13949 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13950 // the optimization here.
13951 if (DAG.SignBitIsZero(N0))
13952 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13954 MVT SrcVT = N0.getSimpleValueType();
13955 MVT DstVT = Op.getSimpleValueType();
13956 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13957 return LowerUINT_TO_FP_i64(Op, DAG);
13958 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13959 return LowerUINT_TO_FP_i32(Op, DAG);
13960 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13963 // Make a 64-bit buffer, and use it to build an FILD.
13964 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13965 if (SrcVT == MVT::i32) {
13966 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13967 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13968 getPointerTy(), StackSlot, WordOff);
13969 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13970 StackSlot, MachinePointerInfo(),
13972 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13973 OffsetSlot, MachinePointerInfo(),
13975 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13979 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13980 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13981 StackSlot, MachinePointerInfo(),
13983 // For i64 source, we need to add the appropriate power of 2 if the input
13984 // was negative. This is the same as the optimization in
13985 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13986 // we must be careful to do the computation in x87 extended precision, not
13987 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13988 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13989 MachineMemOperand *MMO =
13990 DAG.getMachineFunction()
13991 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13992 MachineMemOperand::MOLoad, 8, 8);
13994 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13995 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13996 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13999 APInt FF(32, 0x5F800000ULL);
14001 // Check whether the sign bit is set.
14002 SDValue SignSet = DAG.getSetCC(dl,
14003 getSetCCResultType(*DAG.getContext(), MVT::i64),
14004 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14007 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14008 SDValue FudgePtr = DAG.getConstantPool(
14009 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14012 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14013 SDValue Zero = DAG.getIntPtrConstant(0);
14014 SDValue Four = DAG.getIntPtrConstant(4);
14015 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14017 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14019 // Load the value out, extending it from f32 to f80.
14020 // FIXME: Avoid the extend by constructing the right constant pool?
14021 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14022 FudgePtr, MachinePointerInfo::getConstantPool(),
14023 MVT::f32, false, false, false, 4);
14024 // Extend everything to 80 bits to force it to be done on x87.
14025 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14026 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14029 std::pair<SDValue,SDValue>
14030 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14031 bool IsSigned, bool IsReplace) const {
14034 EVT DstTy = Op.getValueType();
14036 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14037 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14041 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14042 DstTy.getSimpleVT() >= MVT::i16 &&
14043 "Unknown FP_TO_INT to lower!");
14045 // These are really Legal.
14046 if (DstTy == MVT::i32 &&
14047 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14048 return std::make_pair(SDValue(), SDValue());
14049 if (Subtarget->is64Bit() &&
14050 DstTy == MVT::i64 &&
14051 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14052 return std::make_pair(SDValue(), SDValue());
14054 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14055 // stack slot, or into the FTOL runtime function.
14056 MachineFunction &MF = DAG.getMachineFunction();
14057 unsigned MemSize = DstTy.getSizeInBits()/8;
14058 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14059 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14062 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14063 Opc = X86ISD::WIN_FTOL;
14065 switch (DstTy.getSimpleVT().SimpleTy) {
14066 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14067 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14068 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14069 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14072 SDValue Chain = DAG.getEntryNode();
14073 SDValue Value = Op.getOperand(0);
14074 EVT TheVT = Op.getOperand(0).getValueType();
14075 // FIXME This causes a redundant load/store if the SSE-class value is already
14076 // in memory, such as if it is on the callstack.
14077 if (isScalarFPTypeInSSEReg(TheVT)) {
14078 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14079 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14080 MachinePointerInfo::getFixedStack(SSFI),
14082 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14084 Chain, StackSlot, DAG.getValueType(TheVT)
14087 MachineMemOperand *MMO =
14088 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14089 MachineMemOperand::MOLoad, MemSize, MemSize);
14090 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14091 Chain = Value.getValue(1);
14092 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14093 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14096 MachineMemOperand *MMO =
14097 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14098 MachineMemOperand::MOStore, MemSize, MemSize);
14100 if (Opc != X86ISD::WIN_FTOL) {
14101 // Build the FP_TO_INT*_IN_MEM
14102 SDValue Ops[] = { Chain, Value, StackSlot };
14103 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14105 return std::make_pair(FIST, StackSlot);
14107 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14108 DAG.getVTList(MVT::Other, MVT::Glue),
14110 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14111 MVT::i32, ftol.getValue(1));
14112 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14113 MVT::i32, eax.getValue(2));
14114 SDValue Ops[] = { eax, edx };
14115 SDValue pair = IsReplace
14116 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14117 : DAG.getMergeValues(Ops, DL);
14118 return std::make_pair(pair, SDValue());
14122 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14123 const X86Subtarget *Subtarget) {
14124 MVT VT = Op->getSimpleValueType(0);
14125 SDValue In = Op->getOperand(0);
14126 MVT InVT = In.getSimpleValueType();
14129 // Optimize vectors in AVX mode:
14132 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14133 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14134 // Concat upper and lower parts.
14137 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14138 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14139 // Concat upper and lower parts.
14142 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14143 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14144 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14147 if (Subtarget->hasInt256())
14148 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14150 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14151 SDValue Undef = DAG.getUNDEF(InVT);
14152 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14153 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14154 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14156 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14157 VT.getVectorNumElements()/2);
14159 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14160 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14162 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14165 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14166 SelectionDAG &DAG) {
14167 MVT VT = Op->getSimpleValueType(0);
14168 SDValue In = Op->getOperand(0);
14169 MVT InVT = In.getSimpleValueType();
14171 unsigned int NumElts = VT.getVectorNumElements();
14172 if (NumElts != 8 && NumElts != 16)
14175 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14176 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14178 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14179 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14180 // Now we have only mask extension
14181 assert(InVT.getVectorElementType() == MVT::i1);
14182 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14183 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14184 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14185 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14186 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14187 MachinePointerInfo::getConstantPool(),
14188 false, false, false, Alignment);
14190 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14191 if (VT.is512BitVector())
14193 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14196 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14197 SelectionDAG &DAG) {
14198 if (Subtarget->hasFp256()) {
14199 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14207 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14208 SelectionDAG &DAG) {
14210 MVT VT = Op.getSimpleValueType();
14211 SDValue In = Op.getOperand(0);
14212 MVT SVT = In.getSimpleValueType();
14214 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14215 return LowerZERO_EXTEND_AVX512(Op, DAG);
14217 if (Subtarget->hasFp256()) {
14218 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14223 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14224 VT.getVectorNumElements() != SVT.getVectorNumElements());
14228 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14230 MVT VT = Op.getSimpleValueType();
14231 SDValue In = Op.getOperand(0);
14232 MVT InVT = In.getSimpleValueType();
14234 if (VT == MVT::i1) {
14235 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14236 "Invalid scalar TRUNCATE operation");
14237 if (InVT.getSizeInBits() >= 32)
14239 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14240 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14242 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14243 "Invalid TRUNCATE operation");
14245 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14246 if (VT.getVectorElementType().getSizeInBits() >=8)
14247 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14249 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14250 unsigned NumElts = InVT.getVectorNumElements();
14251 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14252 if (InVT.getSizeInBits() < 512) {
14253 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14254 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14258 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14259 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14260 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14261 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14262 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14263 MachinePointerInfo::getConstantPool(),
14264 false, false, false, Alignment);
14265 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14266 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14267 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14270 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14271 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14272 if (Subtarget->hasInt256()) {
14273 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14274 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14275 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14278 DAG.getIntPtrConstant(0));
14281 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14282 DAG.getIntPtrConstant(0));
14283 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14284 DAG.getIntPtrConstant(2));
14285 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14286 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14287 static const int ShufMask[] = {0, 2, 4, 6};
14288 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14291 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14292 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14293 if (Subtarget->hasInt256()) {
14294 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14296 SmallVector<SDValue,32> pshufbMask;
14297 for (unsigned i = 0; i < 2; ++i) {
14298 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14299 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14300 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14301 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14302 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14303 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14304 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14305 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14306 for (unsigned j = 0; j < 8; ++j)
14307 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14309 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14310 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14311 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14313 static const int ShufMask[] = {0, 2, -1, -1};
14314 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14316 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14317 DAG.getIntPtrConstant(0));
14318 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14321 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14322 DAG.getIntPtrConstant(0));
14324 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14325 DAG.getIntPtrConstant(4));
14327 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14328 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14330 // The PSHUFB mask:
14331 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14332 -1, -1, -1, -1, -1, -1, -1, -1};
14334 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14335 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14336 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14338 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14339 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14341 // The MOVLHPS Mask:
14342 static const int ShufMask2[] = {0, 1, 4, 5};
14343 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14344 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14347 // Handle truncation of V256 to V128 using shuffles.
14348 if (!VT.is128BitVector() || !InVT.is256BitVector())
14351 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14353 unsigned NumElems = VT.getVectorNumElements();
14354 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14356 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14357 // Prepare truncation shuffle mask
14358 for (unsigned i = 0; i != NumElems; ++i)
14359 MaskVec[i] = i * 2;
14360 SDValue V = DAG.getVectorShuffle(NVT, DL,
14361 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14362 DAG.getUNDEF(NVT), &MaskVec[0]);
14363 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14364 DAG.getIntPtrConstant(0));
14367 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14368 SelectionDAG &DAG) const {
14369 assert(!Op.getSimpleValueType().isVector());
14371 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14372 /*IsSigned=*/ true, /*IsReplace=*/ false);
14373 SDValue FIST = Vals.first, StackSlot = Vals.second;
14374 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14375 if (!FIST.getNode()) return Op;
14377 if (StackSlot.getNode())
14378 // Load the result.
14379 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14380 FIST, StackSlot, MachinePointerInfo(),
14381 false, false, false, 0);
14383 // The node is the result.
14387 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14388 SelectionDAG &DAG) const {
14389 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14390 /*IsSigned=*/ false, /*IsReplace=*/ false);
14391 SDValue FIST = Vals.first, StackSlot = Vals.second;
14392 assert(FIST.getNode() && "Unexpected failure");
14394 if (StackSlot.getNode())
14395 // Load the result.
14396 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14397 FIST, StackSlot, MachinePointerInfo(),
14398 false, false, false, 0);
14400 // The node is the result.
14404 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14406 MVT VT = Op.getSimpleValueType();
14407 SDValue In = Op.getOperand(0);
14408 MVT SVT = In.getSimpleValueType();
14410 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14412 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14413 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14414 In, DAG.getUNDEF(SVT)));
14417 /// The only differences between FABS and FNEG are the mask and the logic op.
14418 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14419 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14420 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14421 "Wrong opcode for lowering FABS or FNEG.");
14423 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14425 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14426 // into an FNABS. We'll lower the FABS after that if it is still in use.
14428 for (SDNode *User : Op->uses())
14429 if (User->getOpcode() == ISD::FNEG)
14432 SDValue Op0 = Op.getOperand(0);
14433 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14436 MVT VT = Op.getSimpleValueType();
14437 // Assume scalar op for initialization; update for vector if needed.
14438 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14439 // generate a 16-byte vector constant and logic op even for the scalar case.
14440 // Using a 16-byte mask allows folding the load of the mask with
14441 // the logic op, so it can save (~4 bytes) on code size.
14443 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14444 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14445 // decide if we should generate a 16-byte constant mask when we only need 4 or
14446 // 8 bytes for the scalar case.
14447 if (VT.isVector()) {
14448 EltVT = VT.getVectorElementType();
14449 NumElts = VT.getVectorNumElements();
14452 unsigned EltBits = EltVT.getSizeInBits();
14453 LLVMContext *Context = DAG.getContext();
14454 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14456 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14457 Constant *C = ConstantInt::get(*Context, MaskElt);
14458 C = ConstantVector::getSplat(NumElts, C);
14459 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14460 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14461 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14462 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14463 MachinePointerInfo::getConstantPool(),
14464 false, false, false, Alignment);
14466 if (VT.isVector()) {
14467 // For a vector, cast operands to a vector type, perform the logic op,
14468 // and cast the result back to the original value type.
14469 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14470 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14471 SDValue Operand = IsFNABS ?
14472 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14473 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14474 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14475 return DAG.getNode(ISD::BITCAST, dl, VT,
14476 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14479 // If not vector, then scalar.
14480 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14481 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14482 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14485 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14487 LLVMContext *Context = DAG.getContext();
14488 SDValue Op0 = Op.getOperand(0);
14489 SDValue Op1 = Op.getOperand(1);
14491 MVT VT = Op.getSimpleValueType();
14492 MVT SrcVT = Op1.getSimpleValueType();
14494 // If second operand is smaller, extend it first.
14495 if (SrcVT.bitsLT(VT)) {
14496 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14499 // And if it is bigger, shrink it first.
14500 if (SrcVT.bitsGT(VT)) {
14501 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14505 // At this point the operands and the result should have the same
14506 // type, and that won't be f80 since that is not custom lowered.
14508 const fltSemantics &Sem =
14509 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14510 const unsigned SizeInBits = VT.getSizeInBits();
14512 SmallVector<Constant *, 4> CV(
14513 VT == MVT::f64 ? 2 : 4,
14514 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14516 // First, clear all bits but the sign bit from the second operand (sign).
14517 CV[0] = ConstantFP::get(*Context,
14518 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14519 Constant *C = ConstantVector::get(CV);
14520 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14521 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14522 MachinePointerInfo::getConstantPool(),
14523 false, false, false, 16);
14524 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14526 // Next, clear the sign bit from the first operand (magnitude).
14527 CV[0] = ConstantFP::get(
14528 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14529 C = ConstantVector::get(CV);
14530 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14531 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14532 MachinePointerInfo::getConstantPool(),
14533 false, false, false, 16);
14534 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14536 // OR the magnitude value with the sign bit.
14537 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14540 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14541 SDValue N0 = Op.getOperand(0);
14543 MVT VT = Op.getSimpleValueType();
14545 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14546 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14547 DAG.getConstant(1, VT));
14548 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14551 // Check whether an OR'd tree is PTEST-able.
14552 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14553 SelectionDAG &DAG) {
14554 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14556 if (!Subtarget->hasSSE41())
14559 if (!Op->hasOneUse())
14562 SDNode *N = Op.getNode();
14565 SmallVector<SDValue, 8> Opnds;
14566 DenseMap<SDValue, unsigned> VecInMap;
14567 SmallVector<SDValue, 8> VecIns;
14568 EVT VT = MVT::Other;
14570 // Recognize a special case where a vector is casted into wide integer to
14572 Opnds.push_back(N->getOperand(0));
14573 Opnds.push_back(N->getOperand(1));
14575 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14576 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14577 // BFS traverse all OR'd operands.
14578 if (I->getOpcode() == ISD::OR) {
14579 Opnds.push_back(I->getOperand(0));
14580 Opnds.push_back(I->getOperand(1));
14581 // Re-evaluate the number of nodes to be traversed.
14582 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14586 // Quit if a non-EXTRACT_VECTOR_ELT
14587 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14590 // Quit if without a constant index.
14591 SDValue Idx = I->getOperand(1);
14592 if (!isa<ConstantSDNode>(Idx))
14595 SDValue ExtractedFromVec = I->getOperand(0);
14596 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14597 if (M == VecInMap.end()) {
14598 VT = ExtractedFromVec.getValueType();
14599 // Quit if not 128/256-bit vector.
14600 if (!VT.is128BitVector() && !VT.is256BitVector())
14602 // Quit if not the same type.
14603 if (VecInMap.begin() != VecInMap.end() &&
14604 VT != VecInMap.begin()->first.getValueType())
14606 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14607 VecIns.push_back(ExtractedFromVec);
14609 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14612 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14613 "Not extracted from 128-/256-bit vector.");
14615 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14617 for (DenseMap<SDValue, unsigned>::const_iterator
14618 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14619 // Quit if not all elements are used.
14620 if (I->second != FullMask)
14624 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14626 // Cast all vectors into TestVT for PTEST.
14627 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14628 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14630 // If more than one full vectors are evaluated, OR them first before PTEST.
14631 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14632 // Each iteration will OR 2 nodes and append the result until there is only
14633 // 1 node left, i.e. the final OR'd value of all vectors.
14634 SDValue LHS = VecIns[Slot];
14635 SDValue RHS = VecIns[Slot + 1];
14636 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14639 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14640 VecIns.back(), VecIns.back());
14643 /// \brief return true if \c Op has a use that doesn't just read flags.
14644 static bool hasNonFlagsUse(SDValue Op) {
14645 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14647 SDNode *User = *UI;
14648 unsigned UOpNo = UI.getOperandNo();
14649 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14650 // Look pass truncate.
14651 UOpNo = User->use_begin().getOperandNo();
14652 User = *User->use_begin();
14655 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14656 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14662 /// Emit nodes that will be selected as "test Op0,Op0", or something
14664 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14665 SelectionDAG &DAG) const {
14666 if (Op.getValueType() == MVT::i1)
14667 // KORTEST instruction should be selected
14668 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14669 DAG.getConstant(0, Op.getValueType()));
14671 // CF and OF aren't always set the way we want. Determine which
14672 // of these we need.
14673 bool NeedCF = false;
14674 bool NeedOF = false;
14677 case X86::COND_A: case X86::COND_AE:
14678 case X86::COND_B: case X86::COND_BE:
14681 case X86::COND_G: case X86::COND_GE:
14682 case X86::COND_L: case X86::COND_LE:
14683 case X86::COND_O: case X86::COND_NO: {
14684 // Check if we really need to set the
14685 // Overflow flag. If NoSignedWrap is present
14686 // that is not actually needed.
14687 switch (Op->getOpcode()) {
14692 const BinaryWithFlagsSDNode *BinNode =
14693 cast<BinaryWithFlagsSDNode>(Op.getNode());
14694 if (BinNode->hasNoSignedWrap())
14704 // See if we can use the EFLAGS value from the operand instead of
14705 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14706 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14707 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14708 // Emit a CMP with 0, which is the TEST pattern.
14709 //if (Op.getValueType() == MVT::i1)
14710 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14711 // DAG.getConstant(0, MVT::i1));
14712 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14713 DAG.getConstant(0, Op.getValueType()));
14715 unsigned Opcode = 0;
14716 unsigned NumOperands = 0;
14718 // Truncate operations may prevent the merge of the SETCC instruction
14719 // and the arithmetic instruction before it. Attempt to truncate the operands
14720 // of the arithmetic instruction and use a reduced bit-width instruction.
14721 bool NeedTruncation = false;
14722 SDValue ArithOp = Op;
14723 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14724 SDValue Arith = Op->getOperand(0);
14725 // Both the trunc and the arithmetic op need to have one user each.
14726 if (Arith->hasOneUse())
14727 switch (Arith.getOpcode()) {
14734 NeedTruncation = true;
14740 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14741 // which may be the result of a CAST. We use the variable 'Op', which is the
14742 // non-casted variable when we check for possible users.
14743 switch (ArithOp.getOpcode()) {
14745 // Due to an isel shortcoming, be conservative if this add is likely to be
14746 // selected as part of a load-modify-store instruction. When the root node
14747 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14748 // uses of other nodes in the match, such as the ADD in this case. This
14749 // leads to the ADD being left around and reselected, with the result being
14750 // two adds in the output. Alas, even if none our users are stores, that
14751 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14752 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14753 // climbing the DAG back to the root, and it doesn't seem to be worth the
14755 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14756 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14757 if (UI->getOpcode() != ISD::CopyToReg &&
14758 UI->getOpcode() != ISD::SETCC &&
14759 UI->getOpcode() != ISD::STORE)
14762 if (ConstantSDNode *C =
14763 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14764 // An add of one will be selected as an INC.
14765 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14766 Opcode = X86ISD::INC;
14771 // An add of negative one (subtract of one) will be selected as a DEC.
14772 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14773 Opcode = X86ISD::DEC;
14779 // Otherwise use a regular EFLAGS-setting add.
14780 Opcode = X86ISD::ADD;
14785 // If we have a constant logical shift that's only used in a comparison
14786 // against zero turn it into an equivalent AND. This allows turning it into
14787 // a TEST instruction later.
14788 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14789 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14790 EVT VT = Op.getValueType();
14791 unsigned BitWidth = VT.getSizeInBits();
14792 unsigned ShAmt = Op->getConstantOperandVal(1);
14793 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14795 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14796 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14797 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14798 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14800 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14801 DAG.getConstant(Mask, VT));
14802 DAG.ReplaceAllUsesWith(Op, New);
14808 // If the primary and result isn't used, don't bother using X86ISD::AND,
14809 // because a TEST instruction will be better.
14810 if (!hasNonFlagsUse(Op))
14816 // Due to the ISEL shortcoming noted above, be conservative if this op is
14817 // likely to be selected as part of a load-modify-store instruction.
14818 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14819 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14820 if (UI->getOpcode() == ISD::STORE)
14823 // Otherwise use a regular EFLAGS-setting instruction.
14824 switch (ArithOp.getOpcode()) {
14825 default: llvm_unreachable("unexpected operator!");
14826 case ISD::SUB: Opcode = X86ISD::SUB; break;
14827 case ISD::XOR: Opcode = X86ISD::XOR; break;
14828 case ISD::AND: Opcode = X86ISD::AND; break;
14830 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14831 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14832 if (EFLAGS.getNode())
14835 Opcode = X86ISD::OR;
14849 return SDValue(Op.getNode(), 1);
14855 // If we found that truncation is beneficial, perform the truncation and
14857 if (NeedTruncation) {
14858 EVT VT = Op.getValueType();
14859 SDValue WideVal = Op->getOperand(0);
14860 EVT WideVT = WideVal.getValueType();
14861 unsigned ConvertedOp = 0;
14862 // Use a target machine opcode to prevent further DAGCombine
14863 // optimizations that may separate the arithmetic operations
14864 // from the setcc node.
14865 switch (WideVal.getOpcode()) {
14867 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14868 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14869 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14870 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14871 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14875 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14876 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14877 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14878 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14879 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14885 // Emit a CMP with 0, which is the TEST pattern.
14886 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14887 DAG.getConstant(0, Op.getValueType()));
14889 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14890 SmallVector<SDValue, 4> Ops;
14891 for (unsigned i = 0; i != NumOperands; ++i)
14892 Ops.push_back(Op.getOperand(i));
14894 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14895 DAG.ReplaceAllUsesWith(Op, New);
14896 return SDValue(New.getNode(), 1);
14899 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14901 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14902 SDLoc dl, SelectionDAG &DAG) const {
14903 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14904 if (C->getAPIntValue() == 0)
14905 return EmitTest(Op0, X86CC, dl, DAG);
14907 if (Op0.getValueType() == MVT::i1)
14908 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14911 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14912 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14913 // Do the comparison at i32 if it's smaller, besides the Atom case.
14914 // This avoids subregister aliasing issues. Keep the smaller reference
14915 // if we're optimizing for size, however, as that'll allow better folding
14916 // of memory operations.
14917 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14918 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14919 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14920 !Subtarget->isAtom()) {
14921 unsigned ExtendOp =
14922 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14923 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14924 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14926 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14927 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14928 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14930 return SDValue(Sub.getNode(), 1);
14932 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14935 /// Convert a comparison if required by the subtarget.
14936 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14937 SelectionDAG &DAG) const {
14938 // If the subtarget does not support the FUCOMI instruction, floating-point
14939 // comparisons have to be converted.
14940 if (Subtarget->hasCMov() ||
14941 Cmp.getOpcode() != X86ISD::CMP ||
14942 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14943 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14946 // The instruction selector will select an FUCOM instruction instead of
14947 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14948 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14949 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14951 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14952 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14953 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14954 DAG.getConstant(8, MVT::i8));
14955 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14956 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14959 /// The minimum architected relative accuracy is 2^-12. We need one
14960 /// Newton-Raphson step to have a good float result (24 bits of precision).
14961 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14962 DAGCombinerInfo &DCI,
14963 unsigned &RefinementSteps,
14964 bool &UseOneConstNR) const {
14965 // FIXME: We should use instruction latency models to calculate the cost of
14966 // each potential sequence, but this is very hard to do reliably because
14967 // at least Intel's Core* chips have variable timing based on the number of
14968 // significant digits in the divisor and/or sqrt operand.
14969 if (!Subtarget->useSqrtEst())
14972 EVT VT = Op.getValueType();
14974 // SSE1 has rsqrtss and rsqrtps.
14975 // TODO: Add support for AVX512 (v16f32).
14976 // It is likely not profitable to do this for f64 because a double-precision
14977 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14978 // instructions: convert to single, rsqrtss, convert back to double, refine
14979 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14980 // along with FMA, this could be a throughput win.
14981 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14982 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14983 RefinementSteps = 1;
14984 UseOneConstNR = false;
14985 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14990 /// The minimum architected relative accuracy is 2^-12. We need one
14991 /// Newton-Raphson step to have a good float result (24 bits of precision).
14992 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14993 DAGCombinerInfo &DCI,
14994 unsigned &RefinementSteps) const {
14995 // FIXME: We should use instruction latency models to calculate the cost of
14996 // each potential sequence, but this is very hard to do reliably because
14997 // at least Intel's Core* chips have variable timing based on the number of
14998 // significant digits in the divisor.
14999 if (!Subtarget->useReciprocalEst())
15002 EVT VT = Op.getValueType();
15004 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15005 // TODO: Add support for AVX512 (v16f32).
15006 // It is likely not profitable to do this for f64 because a double-precision
15007 // reciprocal estimate with refinement on x86 prior to FMA requires
15008 // 15 instructions: convert to single, rcpss, convert back to double, refine
15009 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15010 // along with FMA, this could be a throughput win.
15011 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15012 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15013 RefinementSteps = ReciprocalEstimateRefinementSteps;
15014 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15019 static bool isAllOnes(SDValue V) {
15020 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15021 return C && C->isAllOnesValue();
15024 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15025 /// if it's possible.
15026 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15027 SDLoc dl, SelectionDAG &DAG) const {
15028 SDValue Op0 = And.getOperand(0);
15029 SDValue Op1 = And.getOperand(1);
15030 if (Op0.getOpcode() == ISD::TRUNCATE)
15031 Op0 = Op0.getOperand(0);
15032 if (Op1.getOpcode() == ISD::TRUNCATE)
15033 Op1 = Op1.getOperand(0);
15036 if (Op1.getOpcode() == ISD::SHL)
15037 std::swap(Op0, Op1);
15038 if (Op0.getOpcode() == ISD::SHL) {
15039 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15040 if (And00C->getZExtValue() == 1) {
15041 // If we looked past a truncate, check that it's only truncating away
15043 unsigned BitWidth = Op0.getValueSizeInBits();
15044 unsigned AndBitWidth = And.getValueSizeInBits();
15045 if (BitWidth > AndBitWidth) {
15047 DAG.computeKnownBits(Op0, Zeros, Ones);
15048 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15052 RHS = Op0.getOperand(1);
15054 } else if (Op1.getOpcode() == ISD::Constant) {
15055 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15056 uint64_t AndRHSVal = AndRHS->getZExtValue();
15057 SDValue AndLHS = Op0;
15059 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15060 LHS = AndLHS.getOperand(0);
15061 RHS = AndLHS.getOperand(1);
15064 // Use BT if the immediate can't be encoded in a TEST instruction.
15065 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15067 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15071 if (LHS.getNode()) {
15072 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15073 // instruction. Since the shift amount is in-range-or-undefined, we know
15074 // that doing a bittest on the i32 value is ok. We extend to i32 because
15075 // the encoding for the i16 version is larger than the i32 version.
15076 // Also promote i16 to i32 for performance / code size reason.
15077 if (LHS.getValueType() == MVT::i8 ||
15078 LHS.getValueType() == MVT::i16)
15079 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15081 // If the operand types disagree, extend the shift amount to match. Since
15082 // BT ignores high bits (like shifts) we can use anyextend.
15083 if (LHS.getValueType() != RHS.getValueType())
15084 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15086 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15087 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15088 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15089 DAG.getConstant(Cond, MVT::i8), BT);
15095 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15097 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15102 // SSE Condition code mapping:
15111 switch (SetCCOpcode) {
15112 default: llvm_unreachable("Unexpected SETCC condition");
15114 case ISD::SETEQ: SSECC = 0; break;
15116 case ISD::SETGT: Swap = true; // Fallthrough
15118 case ISD::SETOLT: SSECC = 1; break;
15120 case ISD::SETGE: Swap = true; // Fallthrough
15122 case ISD::SETOLE: SSECC = 2; break;
15123 case ISD::SETUO: SSECC = 3; break;
15125 case ISD::SETNE: SSECC = 4; break;
15126 case ISD::SETULE: Swap = true; // Fallthrough
15127 case ISD::SETUGE: SSECC = 5; break;
15128 case ISD::SETULT: Swap = true; // Fallthrough
15129 case ISD::SETUGT: SSECC = 6; break;
15130 case ISD::SETO: SSECC = 7; break;
15132 case ISD::SETONE: SSECC = 8; break;
15135 std::swap(Op0, Op1);
15140 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15141 // ones, and then concatenate the result back.
15142 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15143 MVT VT = Op.getSimpleValueType();
15145 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15146 "Unsupported value type for operation");
15148 unsigned NumElems = VT.getVectorNumElements();
15150 SDValue CC = Op.getOperand(2);
15152 // Extract the LHS vectors
15153 SDValue LHS = Op.getOperand(0);
15154 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15155 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15157 // Extract the RHS vectors
15158 SDValue RHS = Op.getOperand(1);
15159 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15160 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15162 // Issue the operation on the smaller types and concatenate the result back
15163 MVT EltVT = VT.getVectorElementType();
15164 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15165 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15166 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15167 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15170 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15171 const X86Subtarget *Subtarget) {
15172 SDValue Op0 = Op.getOperand(0);
15173 SDValue Op1 = Op.getOperand(1);
15174 SDValue CC = Op.getOperand(2);
15175 MVT VT = Op.getSimpleValueType();
15178 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15179 Op.getValueType().getScalarType() == MVT::i1 &&
15180 "Cannot set masked compare for this operation");
15182 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15184 bool Unsigned = false;
15187 switch (SetCCOpcode) {
15188 default: llvm_unreachable("Unexpected SETCC condition");
15189 case ISD::SETNE: SSECC = 4; break;
15190 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15191 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15192 case ISD::SETLT: Swap = true; //fall-through
15193 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15194 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15195 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15196 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15197 case ISD::SETULE: Unsigned = true; //fall-through
15198 case ISD::SETLE: SSECC = 2; break;
15202 std::swap(Op0, Op1);
15204 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15205 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15206 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15207 DAG.getConstant(SSECC, MVT::i8));
15210 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15211 /// operand \p Op1. If non-trivial (for example because it's not constant)
15212 /// return an empty value.
15213 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15215 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15219 MVT VT = Op1.getSimpleValueType();
15220 MVT EVT = VT.getVectorElementType();
15221 unsigned n = VT.getVectorNumElements();
15222 SmallVector<SDValue, 8> ULTOp1;
15224 for (unsigned i = 0; i < n; ++i) {
15225 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15226 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15229 // Avoid underflow.
15230 APInt Val = Elt->getAPIntValue();
15234 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15237 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15240 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15241 SelectionDAG &DAG) {
15242 SDValue Op0 = Op.getOperand(0);
15243 SDValue Op1 = Op.getOperand(1);
15244 SDValue CC = Op.getOperand(2);
15245 MVT VT = Op.getSimpleValueType();
15246 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15247 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15252 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15253 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15256 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15257 unsigned Opc = X86ISD::CMPP;
15258 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15259 assert(VT.getVectorNumElements() <= 16);
15260 Opc = X86ISD::CMPM;
15262 // In the two special cases we can't handle, emit two comparisons.
15265 unsigned CombineOpc;
15266 if (SetCCOpcode == ISD::SETUEQ) {
15267 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15269 assert(SetCCOpcode == ISD::SETONE);
15270 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15273 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15274 DAG.getConstant(CC0, MVT::i8));
15275 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15276 DAG.getConstant(CC1, MVT::i8));
15277 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15279 // Handle all other FP comparisons here.
15280 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15281 DAG.getConstant(SSECC, MVT::i8));
15284 // Break 256-bit integer vector compare into smaller ones.
15285 if (VT.is256BitVector() && !Subtarget->hasInt256())
15286 return Lower256IntVSETCC(Op, DAG);
15288 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15289 EVT OpVT = Op1.getValueType();
15290 if (Subtarget->hasAVX512()) {
15291 if (Op1.getValueType().is512BitVector() ||
15292 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15293 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15294 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15296 // In AVX-512 architecture setcc returns mask with i1 elements,
15297 // But there is no compare instruction for i8 and i16 elements in KNL.
15298 // We are not talking about 512-bit operands in this case, these
15299 // types are illegal.
15301 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15302 OpVT.getVectorElementType().getSizeInBits() >= 8))
15303 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15304 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15307 // We are handling one of the integer comparisons here. Since SSE only has
15308 // GT and EQ comparisons for integer, swapping operands and multiple
15309 // operations may be required for some comparisons.
15311 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15312 bool Subus = false;
15314 switch (SetCCOpcode) {
15315 default: llvm_unreachable("Unexpected SETCC condition");
15316 case ISD::SETNE: Invert = true;
15317 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15318 case ISD::SETLT: Swap = true;
15319 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15320 case ISD::SETGE: Swap = true;
15321 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15322 Invert = true; break;
15323 case ISD::SETULT: Swap = true;
15324 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15325 FlipSigns = true; break;
15326 case ISD::SETUGE: Swap = true;
15327 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15328 FlipSigns = true; Invert = true; break;
15331 // Special case: Use min/max operations for SETULE/SETUGE
15332 MVT VET = VT.getVectorElementType();
15334 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15335 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15338 switch (SetCCOpcode) {
15340 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15341 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15344 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15347 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15348 if (!MinMax && hasSubus) {
15349 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15351 // t = psubus Op0, Op1
15352 // pcmpeq t, <0..0>
15353 switch (SetCCOpcode) {
15355 case ISD::SETULT: {
15356 // If the comparison is against a constant we can turn this into a
15357 // setule. With psubus, setule does not require a swap. This is
15358 // beneficial because the constant in the register is no longer
15359 // destructed as the destination so it can be hoisted out of a loop.
15360 // Only do this pre-AVX since vpcmp* is no longer destructive.
15361 if (Subtarget->hasAVX())
15363 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15364 if (ULEOp1.getNode()) {
15366 Subus = true; Invert = false; Swap = false;
15370 // Psubus is better than flip-sign because it requires no inversion.
15371 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15372 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15376 Opc = X86ISD::SUBUS;
15382 std::swap(Op0, Op1);
15384 // Check that the operation in question is available (most are plain SSE2,
15385 // but PCMPGTQ and PCMPEQQ have different requirements).
15386 if (VT == MVT::v2i64) {
15387 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15388 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15390 // First cast everything to the right type.
15391 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15392 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15394 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15395 // bits of the inputs before performing those operations. The lower
15396 // compare is always unsigned.
15399 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15401 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15402 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15403 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15404 Sign, Zero, Sign, Zero);
15406 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15407 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15409 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15410 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15411 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15413 // Create masks for only the low parts/high parts of the 64 bit integers.
15414 static const int MaskHi[] = { 1, 1, 3, 3 };
15415 static const int MaskLo[] = { 0, 0, 2, 2 };
15416 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15417 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15418 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15420 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15421 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15424 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15426 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15429 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15430 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15431 // pcmpeqd + pshufd + pand.
15432 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15434 // First cast everything to the right type.
15435 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15436 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15439 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15441 // Make sure the lower and upper halves are both all-ones.
15442 static const int Mask[] = { 1, 0, 3, 2 };
15443 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15444 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15447 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15449 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15453 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15454 // bits of the inputs before performing those operations.
15456 EVT EltVT = VT.getVectorElementType();
15457 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15458 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15459 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15462 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15464 // If the logical-not of the result is required, perform that now.
15466 Result = DAG.getNOT(dl, Result, VT);
15469 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15472 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15473 getZeroVector(VT, Subtarget, DAG, dl));
15478 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15480 MVT VT = Op.getSimpleValueType();
15482 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15484 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15485 && "SetCC type must be 8-bit or 1-bit integer");
15486 SDValue Op0 = Op.getOperand(0);
15487 SDValue Op1 = Op.getOperand(1);
15489 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15491 // Optimize to BT if possible.
15492 // Lower (X & (1 << N)) == 0 to BT(X, N).
15493 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15494 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15495 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15496 Op1.getOpcode() == ISD::Constant &&
15497 cast<ConstantSDNode>(Op1)->isNullValue() &&
15498 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15499 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15500 if (NewSetCC.getNode()) {
15502 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15507 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15509 if (Op1.getOpcode() == ISD::Constant &&
15510 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15511 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15512 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15514 // If the input is a setcc, then reuse the input setcc or use a new one with
15515 // the inverted condition.
15516 if (Op0.getOpcode() == X86ISD::SETCC) {
15517 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15518 bool Invert = (CC == ISD::SETNE) ^
15519 cast<ConstantSDNode>(Op1)->isNullValue();
15523 CCode = X86::GetOppositeBranchCondition(CCode);
15524 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15525 DAG.getConstant(CCode, MVT::i8),
15526 Op0.getOperand(1));
15528 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15532 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15533 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15534 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15536 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15537 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15540 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15541 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15542 if (X86CC == X86::COND_INVALID)
15545 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15546 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15547 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15548 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15550 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15554 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15555 static bool isX86LogicalCmp(SDValue Op) {
15556 unsigned Opc = Op.getNode()->getOpcode();
15557 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15558 Opc == X86ISD::SAHF)
15560 if (Op.getResNo() == 1 &&
15561 (Opc == X86ISD::ADD ||
15562 Opc == X86ISD::SUB ||
15563 Opc == X86ISD::ADC ||
15564 Opc == X86ISD::SBB ||
15565 Opc == X86ISD::SMUL ||
15566 Opc == X86ISD::UMUL ||
15567 Opc == X86ISD::INC ||
15568 Opc == X86ISD::DEC ||
15569 Opc == X86ISD::OR ||
15570 Opc == X86ISD::XOR ||
15571 Opc == X86ISD::AND))
15574 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15580 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15581 if (V.getOpcode() != ISD::TRUNCATE)
15584 SDValue VOp0 = V.getOperand(0);
15585 unsigned InBits = VOp0.getValueSizeInBits();
15586 unsigned Bits = V.getValueSizeInBits();
15587 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15590 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15591 bool addTest = true;
15592 SDValue Cond = Op.getOperand(0);
15593 SDValue Op1 = Op.getOperand(1);
15594 SDValue Op2 = Op.getOperand(2);
15596 EVT VT = Op1.getValueType();
15599 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15600 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15601 // sequence later on.
15602 if (Cond.getOpcode() == ISD::SETCC &&
15603 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15604 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15605 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15606 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15607 int SSECC = translateX86FSETCC(
15608 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15611 if (Subtarget->hasAVX512()) {
15612 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15613 DAG.getConstant(SSECC, MVT::i8));
15614 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15616 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15617 DAG.getConstant(SSECC, MVT::i8));
15618 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15619 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15620 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15624 if (Cond.getOpcode() == ISD::SETCC) {
15625 SDValue NewCond = LowerSETCC(Cond, DAG);
15626 if (NewCond.getNode())
15630 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15631 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15632 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15633 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15634 if (Cond.getOpcode() == X86ISD::SETCC &&
15635 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15636 isZero(Cond.getOperand(1).getOperand(1))) {
15637 SDValue Cmp = Cond.getOperand(1);
15639 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15641 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15642 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15643 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15645 SDValue CmpOp0 = Cmp.getOperand(0);
15646 // Apply further optimizations for special cases
15647 // (select (x != 0), -1, 0) -> neg & sbb
15648 // (select (x == 0), 0, -1) -> neg & sbb
15649 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15650 if (YC->isNullValue() &&
15651 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15652 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15653 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15654 DAG.getConstant(0, CmpOp0.getValueType()),
15656 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15657 DAG.getConstant(X86::COND_B, MVT::i8),
15658 SDValue(Neg.getNode(), 1));
15662 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15663 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15664 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15666 SDValue Res = // Res = 0 or -1.
15667 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15668 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15670 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15671 Res = DAG.getNOT(DL, Res, Res.getValueType());
15673 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15674 if (!N2C || !N2C->isNullValue())
15675 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15680 // Look past (and (setcc_carry (cmp ...)), 1).
15681 if (Cond.getOpcode() == ISD::AND &&
15682 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15683 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15684 if (C && C->getAPIntValue() == 1)
15685 Cond = Cond.getOperand(0);
15688 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15689 // setting operand in place of the X86ISD::SETCC.
15690 unsigned CondOpcode = Cond.getOpcode();
15691 if (CondOpcode == X86ISD::SETCC ||
15692 CondOpcode == X86ISD::SETCC_CARRY) {
15693 CC = Cond.getOperand(0);
15695 SDValue Cmp = Cond.getOperand(1);
15696 unsigned Opc = Cmp.getOpcode();
15697 MVT VT = Op.getSimpleValueType();
15699 bool IllegalFPCMov = false;
15700 if (VT.isFloatingPoint() && !VT.isVector() &&
15701 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15702 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15704 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15705 Opc == X86ISD::BT) { // FIXME
15709 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15710 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15711 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15712 Cond.getOperand(0).getValueType() != MVT::i8)) {
15713 SDValue LHS = Cond.getOperand(0);
15714 SDValue RHS = Cond.getOperand(1);
15715 unsigned X86Opcode;
15718 switch (CondOpcode) {
15719 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15720 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15721 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15722 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15723 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15724 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15725 default: llvm_unreachable("unexpected overflowing operator");
15727 if (CondOpcode == ISD::UMULO)
15728 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15731 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15733 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15735 if (CondOpcode == ISD::UMULO)
15736 Cond = X86Op.getValue(2);
15738 Cond = X86Op.getValue(1);
15740 CC = DAG.getConstant(X86Cond, MVT::i8);
15745 // Look pass the truncate if the high bits are known zero.
15746 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15747 Cond = Cond.getOperand(0);
15749 // We know the result of AND is compared against zero. Try to match
15751 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15752 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15753 if (NewSetCC.getNode()) {
15754 CC = NewSetCC.getOperand(0);
15755 Cond = NewSetCC.getOperand(1);
15762 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15763 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15766 // a < b ? -1 : 0 -> RES = ~setcc_carry
15767 // a < b ? 0 : -1 -> RES = setcc_carry
15768 // a >= b ? -1 : 0 -> RES = setcc_carry
15769 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15770 if (Cond.getOpcode() == X86ISD::SUB) {
15771 Cond = ConvertCmpIfNecessary(Cond, DAG);
15772 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15774 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15775 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15776 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15777 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15778 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15779 return DAG.getNOT(DL, Res, Res.getValueType());
15784 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15785 // widen the cmov and push the truncate through. This avoids introducing a new
15786 // branch during isel and doesn't add any extensions.
15787 if (Op.getValueType() == MVT::i8 &&
15788 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15789 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15790 if (T1.getValueType() == T2.getValueType() &&
15791 // Blacklist CopyFromReg to avoid partial register stalls.
15792 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15793 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15794 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15795 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15799 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15800 // condition is true.
15801 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15802 SDValue Ops[] = { Op2, Op1, CC, Cond };
15803 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15806 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15807 SelectionDAG &DAG) {
15808 MVT VT = Op->getSimpleValueType(0);
15809 SDValue In = Op->getOperand(0);
15810 MVT InVT = In.getSimpleValueType();
15811 MVT VTElt = VT.getVectorElementType();
15812 MVT InVTElt = InVT.getVectorElementType();
15816 if ((InVTElt == MVT::i1) &&
15817 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15818 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15820 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15821 VTElt.getSizeInBits() <= 16)) ||
15823 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15824 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15826 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15827 VTElt.getSizeInBits() >= 32))))
15828 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15830 unsigned int NumElts = VT.getVectorNumElements();
15832 if (NumElts != 8 && NumElts != 16)
15835 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15836 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15837 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15838 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15841 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15842 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15844 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15845 Constant *C = ConstantInt::get(*DAG.getContext(),
15846 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15848 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15849 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15850 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15851 MachinePointerInfo::getConstantPool(),
15852 false, false, false, Alignment);
15853 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15854 if (VT.is512BitVector())
15856 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15859 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15860 SelectionDAG &DAG) {
15861 MVT VT = Op->getSimpleValueType(0);
15862 SDValue In = Op->getOperand(0);
15863 MVT InVT = In.getSimpleValueType();
15866 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15867 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15869 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15870 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15871 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15874 if (Subtarget->hasInt256())
15875 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15877 // Optimize vectors in AVX mode
15878 // Sign extend v8i16 to v8i32 and
15881 // Divide input vector into two parts
15882 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15883 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15884 // concat the vectors to original VT
15886 unsigned NumElems = InVT.getVectorNumElements();
15887 SDValue Undef = DAG.getUNDEF(InVT);
15889 SmallVector<int,8> ShufMask1(NumElems, -1);
15890 for (unsigned i = 0; i != NumElems/2; ++i)
15893 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15895 SmallVector<int,8> ShufMask2(NumElems, -1);
15896 for (unsigned i = 0; i != NumElems/2; ++i)
15897 ShufMask2[i] = i + NumElems/2;
15899 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15901 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15902 VT.getVectorNumElements()/2);
15904 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15905 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15907 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15910 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15911 // may emit an illegal shuffle but the expansion is still better than scalar
15912 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15913 // we'll emit a shuffle and a arithmetic shift.
15914 // TODO: It is possible to support ZExt by zeroing the undef values during
15915 // the shuffle phase or after the shuffle.
15916 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15917 SelectionDAG &DAG) {
15918 MVT RegVT = Op.getSimpleValueType();
15919 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15920 assert(RegVT.isInteger() &&
15921 "We only custom lower integer vector sext loads.");
15923 // Nothing useful we can do without SSE2 shuffles.
15924 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15926 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15928 EVT MemVT = Ld->getMemoryVT();
15929 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15930 unsigned RegSz = RegVT.getSizeInBits();
15932 ISD::LoadExtType Ext = Ld->getExtensionType();
15934 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15935 && "Only anyext and sext are currently implemented.");
15936 assert(MemVT != RegVT && "Cannot extend to the same type");
15937 assert(MemVT.isVector() && "Must load a vector from memory");
15939 unsigned NumElems = RegVT.getVectorNumElements();
15940 unsigned MemSz = MemVT.getSizeInBits();
15941 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15943 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15944 // The only way in which we have a legal 256-bit vector result but not the
15945 // integer 256-bit operations needed to directly lower a sextload is if we
15946 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15947 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15948 // correctly legalized. We do this late to allow the canonical form of
15949 // sextload to persist throughout the rest of the DAG combiner -- it wants
15950 // to fold together any extensions it can, and so will fuse a sign_extend
15951 // of an sextload into a sextload targeting a wider value.
15953 if (MemSz == 128) {
15954 // Just switch this to a normal load.
15955 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15956 "it must be a legal 128-bit vector "
15958 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15959 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15960 Ld->isInvariant(), Ld->getAlignment());
15962 assert(MemSz < 128 &&
15963 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15964 // Do an sext load to a 128-bit vector type. We want to use the same
15965 // number of elements, but elements half as wide. This will end up being
15966 // recursively lowered by this routine, but will succeed as we definitely
15967 // have all the necessary features if we're using AVX1.
15969 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15970 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15972 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15973 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15974 Ld->isNonTemporal(), Ld->isInvariant(),
15975 Ld->getAlignment());
15978 // Replace chain users with the new chain.
15979 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15980 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15982 // Finally, do a normal sign-extend to the desired register.
15983 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15986 // All sizes must be a power of two.
15987 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15988 "Non-power-of-two elements are not custom lowered!");
15990 // Attempt to load the original value using scalar loads.
15991 // Find the largest scalar type that divides the total loaded size.
15992 MVT SclrLoadTy = MVT::i8;
15993 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15994 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15995 MVT Tp = (MVT::SimpleValueType)tp;
15996 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16001 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16002 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16004 SclrLoadTy = MVT::f64;
16006 // Calculate the number of scalar loads that we need to perform
16007 // in order to load our vector from memory.
16008 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16010 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16011 "Can only lower sext loads with a single scalar load!");
16013 unsigned loadRegZize = RegSz;
16014 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16017 // Represent our vector as a sequence of elements which are the
16018 // largest scalar that we can load.
16019 EVT LoadUnitVecVT = EVT::getVectorVT(
16020 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16022 // Represent the data using the same element type that is stored in
16023 // memory. In practice, we ''widen'' MemVT.
16025 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16026 loadRegZize / MemVT.getScalarType().getSizeInBits());
16028 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16029 "Invalid vector type");
16031 // We can't shuffle using an illegal type.
16032 assert(TLI.isTypeLegal(WideVecVT) &&
16033 "We only lower types that form legal widened vector types");
16035 SmallVector<SDValue, 8> Chains;
16036 SDValue Ptr = Ld->getBasePtr();
16037 SDValue Increment =
16038 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16039 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16041 for (unsigned i = 0; i < NumLoads; ++i) {
16042 // Perform a single load.
16043 SDValue ScalarLoad =
16044 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16045 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16046 Ld->getAlignment());
16047 Chains.push_back(ScalarLoad.getValue(1));
16048 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16049 // another round of DAGCombining.
16051 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16053 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16054 ScalarLoad, DAG.getIntPtrConstant(i));
16056 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16059 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16061 // Bitcast the loaded value to a vector of the original element type, in
16062 // the size of the target vector type.
16063 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16064 unsigned SizeRatio = RegSz / MemSz;
16066 if (Ext == ISD::SEXTLOAD) {
16067 // If we have SSE4.1, we can directly emit a VSEXT node.
16068 if (Subtarget->hasSSE41()) {
16069 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16070 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16074 // Otherwise we'll shuffle the small elements in the high bits of the
16075 // larger type and perform an arithmetic shift. If the shift is not legal
16076 // it's better to scalarize.
16077 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16078 "We can't implement a sext load without an arithmetic right shift!");
16080 // Redistribute the loaded elements into the different locations.
16081 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16082 for (unsigned i = 0; i != NumElems; ++i)
16083 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16085 SDValue Shuff = DAG.getVectorShuffle(
16086 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16088 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16090 // Build the arithmetic shift.
16091 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16092 MemVT.getVectorElementType().getSizeInBits();
16094 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16096 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16100 // Redistribute the loaded elements into the different locations.
16101 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16102 for (unsigned i = 0; i != NumElems; ++i)
16103 ShuffleVec[i * SizeRatio] = i;
16105 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16106 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16108 // Bitcast to the requested type.
16109 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16110 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16114 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16115 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16116 // from the AND / OR.
16117 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16118 Opc = Op.getOpcode();
16119 if (Opc != ISD::OR && Opc != ISD::AND)
16121 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16122 Op.getOperand(0).hasOneUse() &&
16123 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16124 Op.getOperand(1).hasOneUse());
16127 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16128 // 1 and that the SETCC node has a single use.
16129 static bool isXor1OfSetCC(SDValue Op) {
16130 if (Op.getOpcode() != ISD::XOR)
16132 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16133 if (N1C && N1C->getAPIntValue() == 1) {
16134 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16135 Op.getOperand(0).hasOneUse();
16140 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16141 bool addTest = true;
16142 SDValue Chain = Op.getOperand(0);
16143 SDValue Cond = Op.getOperand(1);
16144 SDValue Dest = Op.getOperand(2);
16147 bool Inverted = false;
16149 if (Cond.getOpcode() == ISD::SETCC) {
16150 // Check for setcc([su]{add,sub,mul}o == 0).
16151 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16152 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16153 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16154 Cond.getOperand(0).getResNo() == 1 &&
16155 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16156 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16157 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16158 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16159 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16160 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16162 Cond = Cond.getOperand(0);
16164 SDValue NewCond = LowerSETCC(Cond, DAG);
16165 if (NewCond.getNode())
16170 // FIXME: LowerXALUO doesn't handle these!!
16171 else if (Cond.getOpcode() == X86ISD::ADD ||
16172 Cond.getOpcode() == X86ISD::SUB ||
16173 Cond.getOpcode() == X86ISD::SMUL ||
16174 Cond.getOpcode() == X86ISD::UMUL)
16175 Cond = LowerXALUO(Cond, DAG);
16178 // Look pass (and (setcc_carry (cmp ...)), 1).
16179 if (Cond.getOpcode() == ISD::AND &&
16180 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16181 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16182 if (C && C->getAPIntValue() == 1)
16183 Cond = Cond.getOperand(0);
16186 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16187 // setting operand in place of the X86ISD::SETCC.
16188 unsigned CondOpcode = Cond.getOpcode();
16189 if (CondOpcode == X86ISD::SETCC ||
16190 CondOpcode == X86ISD::SETCC_CARRY) {
16191 CC = Cond.getOperand(0);
16193 SDValue Cmp = Cond.getOperand(1);
16194 unsigned Opc = Cmp.getOpcode();
16195 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16196 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16200 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16204 // These can only come from an arithmetic instruction with overflow,
16205 // e.g. SADDO, UADDO.
16206 Cond = Cond.getNode()->getOperand(1);
16212 CondOpcode = Cond.getOpcode();
16213 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16214 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16215 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16216 Cond.getOperand(0).getValueType() != MVT::i8)) {
16217 SDValue LHS = Cond.getOperand(0);
16218 SDValue RHS = Cond.getOperand(1);
16219 unsigned X86Opcode;
16222 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16223 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16225 switch (CondOpcode) {
16226 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16228 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16230 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16233 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16234 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16238 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16241 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16242 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16243 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16244 default: llvm_unreachable("unexpected overflowing operator");
16247 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16248 if (CondOpcode == ISD::UMULO)
16249 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16252 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16254 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16256 if (CondOpcode == ISD::UMULO)
16257 Cond = X86Op.getValue(2);
16259 Cond = X86Op.getValue(1);
16261 CC = DAG.getConstant(X86Cond, MVT::i8);
16265 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16266 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16267 if (CondOpc == ISD::OR) {
16268 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16269 // two branches instead of an explicit OR instruction with a
16271 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16272 isX86LogicalCmp(Cmp)) {
16273 CC = Cond.getOperand(0).getOperand(0);
16274 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16275 Chain, Dest, CC, Cmp);
16276 CC = Cond.getOperand(1).getOperand(0);
16280 } else { // ISD::AND
16281 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16282 // two branches instead of an explicit AND instruction with a
16283 // separate test. However, we only do this if this block doesn't
16284 // have a fall-through edge, because this requires an explicit
16285 // jmp when the condition is false.
16286 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16287 isX86LogicalCmp(Cmp) &&
16288 Op.getNode()->hasOneUse()) {
16289 X86::CondCode CCode =
16290 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16291 CCode = X86::GetOppositeBranchCondition(CCode);
16292 CC = DAG.getConstant(CCode, MVT::i8);
16293 SDNode *User = *Op.getNode()->use_begin();
16294 // Look for an unconditional branch following this conditional branch.
16295 // We need this because we need to reverse the successors in order
16296 // to implement FCMP_OEQ.
16297 if (User->getOpcode() == ISD::BR) {
16298 SDValue FalseBB = User->getOperand(1);
16300 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16301 assert(NewBR == User);
16305 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16306 Chain, Dest, CC, Cmp);
16307 X86::CondCode CCode =
16308 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16309 CCode = X86::GetOppositeBranchCondition(CCode);
16310 CC = DAG.getConstant(CCode, MVT::i8);
16316 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16317 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16318 // It should be transformed during dag combiner except when the condition
16319 // is set by a arithmetics with overflow node.
16320 X86::CondCode CCode =
16321 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16322 CCode = X86::GetOppositeBranchCondition(CCode);
16323 CC = DAG.getConstant(CCode, MVT::i8);
16324 Cond = Cond.getOperand(0).getOperand(1);
16326 } else if (Cond.getOpcode() == ISD::SETCC &&
16327 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16328 // For FCMP_OEQ, we can emit
16329 // two branches instead of an explicit AND instruction with a
16330 // separate test. However, we only do this if this block doesn't
16331 // have a fall-through edge, because this requires an explicit
16332 // jmp when the condition is false.
16333 if (Op.getNode()->hasOneUse()) {
16334 SDNode *User = *Op.getNode()->use_begin();
16335 // Look for an unconditional branch following this conditional branch.
16336 // We need this because we need to reverse the successors in order
16337 // to implement FCMP_OEQ.
16338 if (User->getOpcode() == ISD::BR) {
16339 SDValue FalseBB = User->getOperand(1);
16341 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16342 assert(NewBR == User);
16346 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16347 Cond.getOperand(0), Cond.getOperand(1));
16348 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16349 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16350 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16351 Chain, Dest, CC, Cmp);
16352 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16357 } else if (Cond.getOpcode() == ISD::SETCC &&
16358 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16359 // For FCMP_UNE, we can emit
16360 // two branches instead of an explicit AND instruction with a
16361 // separate test. However, we only do this if this block doesn't
16362 // have a fall-through edge, because this requires an explicit
16363 // jmp when the condition is false.
16364 if (Op.getNode()->hasOneUse()) {
16365 SDNode *User = *Op.getNode()->use_begin();
16366 // Look for an unconditional branch following this conditional branch.
16367 // We need this because we need to reverse the successors in order
16368 // to implement FCMP_UNE.
16369 if (User->getOpcode() == ISD::BR) {
16370 SDValue FalseBB = User->getOperand(1);
16372 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16373 assert(NewBR == User);
16376 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16377 Cond.getOperand(0), Cond.getOperand(1));
16378 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16379 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16380 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16381 Chain, Dest, CC, Cmp);
16382 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16392 // Look pass the truncate if the high bits are known zero.
16393 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16394 Cond = Cond.getOperand(0);
16396 // We know the result of AND is compared against zero. Try to match
16398 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16399 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16400 if (NewSetCC.getNode()) {
16401 CC = NewSetCC.getOperand(0);
16402 Cond = NewSetCC.getOperand(1);
16409 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16410 CC = DAG.getConstant(X86Cond, MVT::i8);
16411 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16413 Cond = ConvertCmpIfNecessary(Cond, DAG);
16414 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16415 Chain, Dest, CC, Cond);
16418 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16419 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16420 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16421 // that the guard pages used by the OS virtual memory manager are allocated in
16422 // correct sequence.
16424 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16425 SelectionDAG &DAG) const {
16426 MachineFunction &MF = DAG.getMachineFunction();
16427 bool SplitStack = MF.shouldSplitStack();
16428 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16434 SDNode* Node = Op.getNode();
16436 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16437 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16438 " not tell us which reg is the stack pointer!");
16439 EVT VT = Node->getValueType(0);
16440 SDValue Tmp1 = SDValue(Node, 0);
16441 SDValue Tmp2 = SDValue(Node, 1);
16442 SDValue Tmp3 = Node->getOperand(2);
16443 SDValue Chain = Tmp1.getOperand(0);
16445 // Chain the dynamic stack allocation so that it doesn't modify the stack
16446 // pointer when other instructions are using the stack.
16447 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16450 SDValue Size = Tmp2.getOperand(1);
16451 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16452 Chain = SP.getValue(1);
16453 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16454 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16455 unsigned StackAlign = TFI.getStackAlignment();
16456 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16457 if (Align > StackAlign)
16458 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16459 DAG.getConstant(-(uint64_t)Align, VT));
16460 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16462 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16463 DAG.getIntPtrConstant(0, true), SDValue(),
16466 SDValue Ops[2] = { Tmp1, Tmp2 };
16467 return DAG.getMergeValues(Ops, dl);
16471 SDValue Chain = Op.getOperand(0);
16472 SDValue Size = Op.getOperand(1);
16473 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16474 EVT VT = Op.getNode()->getValueType(0);
16476 bool Is64Bit = Subtarget->is64Bit();
16477 EVT SPTy = getPointerTy();
16480 MachineRegisterInfo &MRI = MF.getRegInfo();
16483 // The 64 bit implementation of segmented stacks needs to clobber both r10
16484 // r11. This makes it impossible to use it along with nested parameters.
16485 const Function *F = MF.getFunction();
16487 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16489 if (I->hasNestAttr())
16490 report_fatal_error("Cannot use segmented stacks with functions that "
16491 "have nested arguments.");
16494 const TargetRegisterClass *AddrRegClass =
16495 getRegClassFor(getPointerTy());
16496 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16497 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16498 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16499 DAG.getRegister(Vreg, SPTy));
16500 SDValue Ops1[2] = { Value, Chain };
16501 return DAG.getMergeValues(Ops1, dl);
16504 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16506 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16507 Flag = Chain.getValue(1);
16508 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16510 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16512 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16513 DAG.getSubtarget().getRegisterInfo());
16514 unsigned SPReg = RegInfo->getStackRegister();
16515 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16516 Chain = SP.getValue(1);
16519 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16520 DAG.getConstant(-(uint64_t)Align, VT));
16521 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16524 SDValue Ops1[2] = { SP, Chain };
16525 return DAG.getMergeValues(Ops1, dl);
16529 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16530 MachineFunction &MF = DAG.getMachineFunction();
16531 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16533 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16536 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16537 // vastart just stores the address of the VarArgsFrameIndex slot into the
16538 // memory location argument.
16539 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16541 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16542 MachinePointerInfo(SV), false, false, 0);
16546 // gp_offset (0 - 6 * 8)
16547 // fp_offset (48 - 48 + 8 * 16)
16548 // overflow_arg_area (point to parameters coming in memory).
16550 SmallVector<SDValue, 8> MemOps;
16551 SDValue FIN = Op.getOperand(1);
16553 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16554 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16556 FIN, MachinePointerInfo(SV), false, false, 0);
16557 MemOps.push_back(Store);
16560 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16561 FIN, DAG.getIntPtrConstant(4));
16562 Store = DAG.getStore(Op.getOperand(0), DL,
16563 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16565 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16566 MemOps.push_back(Store);
16568 // Store ptr to overflow_arg_area
16569 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16570 FIN, DAG.getIntPtrConstant(4));
16571 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16573 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16574 MachinePointerInfo(SV, 8),
16576 MemOps.push_back(Store);
16578 // Store ptr to reg_save_area.
16579 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16580 FIN, DAG.getIntPtrConstant(8));
16581 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16583 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16584 MachinePointerInfo(SV, 16), false, false, 0);
16585 MemOps.push_back(Store);
16586 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16589 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16590 assert(Subtarget->is64Bit() &&
16591 "LowerVAARG only handles 64-bit va_arg!");
16592 assert((Subtarget->isTargetLinux() ||
16593 Subtarget->isTargetDarwin()) &&
16594 "Unhandled target in LowerVAARG");
16595 assert(Op.getNode()->getNumOperands() == 4);
16596 SDValue Chain = Op.getOperand(0);
16597 SDValue SrcPtr = Op.getOperand(1);
16598 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16599 unsigned Align = Op.getConstantOperandVal(3);
16602 EVT ArgVT = Op.getNode()->getValueType(0);
16603 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16604 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16607 // Decide which area this value should be read from.
16608 // TODO: Implement the AMD64 ABI in its entirety. This simple
16609 // selection mechanism works only for the basic types.
16610 if (ArgVT == MVT::f80) {
16611 llvm_unreachable("va_arg for f80 not yet implemented");
16612 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16613 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16614 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16615 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16617 llvm_unreachable("Unhandled argument type in LowerVAARG");
16620 if (ArgMode == 2) {
16621 // Sanity Check: Make sure using fp_offset makes sense.
16622 assert(!DAG.getTarget().Options.UseSoftFloat &&
16623 !(DAG.getMachineFunction()
16624 .getFunction()->getAttributes()
16625 .hasAttribute(AttributeSet::FunctionIndex,
16626 Attribute::NoImplicitFloat)) &&
16627 Subtarget->hasSSE1());
16630 // Insert VAARG_64 node into the DAG
16631 // VAARG_64 returns two values: Variable Argument Address, Chain
16632 SmallVector<SDValue, 11> InstOps;
16633 InstOps.push_back(Chain);
16634 InstOps.push_back(SrcPtr);
16635 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16636 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16637 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16638 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16639 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16640 VTs, InstOps, MVT::i64,
16641 MachinePointerInfo(SV),
16643 /*Volatile=*/false,
16645 /*WriteMem=*/true);
16646 Chain = VAARG.getValue(1);
16648 // Load the next argument and return it
16649 return DAG.getLoad(ArgVT, dl,
16652 MachinePointerInfo(),
16653 false, false, false, 0);
16656 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16657 SelectionDAG &DAG) {
16658 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16659 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16660 SDValue Chain = Op.getOperand(0);
16661 SDValue DstPtr = Op.getOperand(1);
16662 SDValue SrcPtr = Op.getOperand(2);
16663 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16664 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16667 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16668 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16670 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16673 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16674 // amount is a constant. Takes immediate version of shift as input.
16675 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16676 SDValue SrcOp, uint64_t ShiftAmt,
16677 SelectionDAG &DAG) {
16678 MVT ElementType = VT.getVectorElementType();
16680 // Fold this packed shift into its first operand if ShiftAmt is 0.
16684 // Check for ShiftAmt >= element width
16685 if (ShiftAmt >= ElementType.getSizeInBits()) {
16686 if (Opc == X86ISD::VSRAI)
16687 ShiftAmt = ElementType.getSizeInBits() - 1;
16689 return DAG.getConstant(0, VT);
16692 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16693 && "Unknown target vector shift-by-constant node");
16695 // Fold this packed vector shift into a build vector if SrcOp is a
16696 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16697 if (VT == SrcOp.getSimpleValueType() &&
16698 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16699 SmallVector<SDValue, 8> Elts;
16700 unsigned NumElts = SrcOp->getNumOperands();
16701 ConstantSDNode *ND;
16704 default: llvm_unreachable(nullptr);
16705 case X86ISD::VSHLI:
16706 for (unsigned i=0; i!=NumElts; ++i) {
16707 SDValue CurrentOp = SrcOp->getOperand(i);
16708 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16709 Elts.push_back(CurrentOp);
16712 ND = cast<ConstantSDNode>(CurrentOp);
16713 const APInt &C = ND->getAPIntValue();
16714 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16717 case X86ISD::VSRLI:
16718 for (unsigned i=0; i!=NumElts; ++i) {
16719 SDValue CurrentOp = SrcOp->getOperand(i);
16720 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16721 Elts.push_back(CurrentOp);
16724 ND = cast<ConstantSDNode>(CurrentOp);
16725 const APInt &C = ND->getAPIntValue();
16726 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16729 case X86ISD::VSRAI:
16730 for (unsigned i=0; i!=NumElts; ++i) {
16731 SDValue CurrentOp = SrcOp->getOperand(i);
16732 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16733 Elts.push_back(CurrentOp);
16736 ND = cast<ConstantSDNode>(CurrentOp);
16737 const APInt &C = ND->getAPIntValue();
16738 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16743 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16746 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16749 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16750 // may or may not be a constant. Takes immediate version of shift as input.
16751 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16752 SDValue SrcOp, SDValue ShAmt,
16753 SelectionDAG &DAG) {
16754 MVT SVT = ShAmt.getSimpleValueType();
16755 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16757 // Catch shift-by-constant.
16758 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16759 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16760 CShAmt->getZExtValue(), DAG);
16762 // Change opcode to non-immediate version
16764 default: llvm_unreachable("Unknown target vector shift node");
16765 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16766 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16767 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16770 const X86Subtarget &Subtarget =
16771 DAG.getTarget().getSubtarget<X86Subtarget>();
16772 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16773 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16774 // Let the shuffle legalizer expand this shift amount node.
16775 SDValue Op0 = ShAmt.getOperand(0);
16776 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16777 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16779 // Need to build a vector containing shift amount.
16780 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16781 SmallVector<SDValue, 4> ShOps;
16782 ShOps.push_back(ShAmt);
16783 if (SVT == MVT::i32) {
16784 ShOps.push_back(DAG.getConstant(0, SVT));
16785 ShOps.push_back(DAG.getUNDEF(SVT));
16787 ShOps.push_back(DAG.getUNDEF(SVT));
16789 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16790 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16793 // The return type has to be a 128-bit type with the same element
16794 // type as the input type.
16795 MVT EltVT = VT.getVectorElementType();
16796 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16798 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16799 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16802 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16803 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16804 /// necessary casting for \p Mask when lowering masking intrinsics.
16805 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16806 SDValue PreservedSrc,
16807 const X86Subtarget *Subtarget,
16808 SelectionDAG &DAG) {
16809 EVT VT = Op.getValueType();
16810 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16811 MVT::i1, VT.getVectorNumElements());
16812 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16813 Mask.getValueType().getSizeInBits());
16816 assert(MaskVT.isSimple() && "invalid mask type");
16818 if (isAllOnes(Mask))
16821 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16822 // are extracted by EXTRACT_SUBVECTOR.
16823 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16824 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16825 DAG.getIntPtrConstant(0));
16827 switch (Op.getOpcode()) {
16829 case X86ISD::PCMPEQM:
16830 case X86ISD::PCMPGTM:
16832 case X86ISD::CMPMU:
16833 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16835 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16836 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16837 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16840 /// \brief Creates an SDNode for a predicated scalar operation.
16841 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16842 /// The mask is comming as MVT::i8 and it should be truncated
16843 /// to MVT::i1 while lowering masking intrinsics.
16844 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16845 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16846 /// a scalar instruction.
16847 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16848 SDValue PreservedSrc,
16849 const X86Subtarget *Subtarget,
16850 SelectionDAG &DAG) {
16851 if (isAllOnes(Mask))
16854 EVT VT = Op.getValueType();
16856 // The mask should be of type MVT::i1
16857 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16859 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16860 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16861 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16864 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16866 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16867 case Intrinsic::x86_fma_vfmadd_ps:
16868 case Intrinsic::x86_fma_vfmadd_pd:
16869 case Intrinsic::x86_fma_vfmadd_ps_256:
16870 case Intrinsic::x86_fma_vfmadd_pd_256:
16871 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16872 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16873 return X86ISD::FMADD;
16874 case Intrinsic::x86_fma_vfmsub_ps:
16875 case Intrinsic::x86_fma_vfmsub_pd:
16876 case Intrinsic::x86_fma_vfmsub_ps_256:
16877 case Intrinsic::x86_fma_vfmsub_pd_256:
16878 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16879 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16880 return X86ISD::FMSUB;
16881 case Intrinsic::x86_fma_vfnmadd_ps:
16882 case Intrinsic::x86_fma_vfnmadd_pd:
16883 case Intrinsic::x86_fma_vfnmadd_ps_256:
16884 case Intrinsic::x86_fma_vfnmadd_pd_256:
16885 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16886 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16887 return X86ISD::FNMADD;
16888 case Intrinsic::x86_fma_vfnmsub_ps:
16889 case Intrinsic::x86_fma_vfnmsub_pd:
16890 case Intrinsic::x86_fma_vfnmsub_ps_256:
16891 case Intrinsic::x86_fma_vfnmsub_pd_256:
16892 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16893 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16894 return X86ISD::FNMSUB;
16895 case Intrinsic::x86_fma_vfmaddsub_ps:
16896 case Intrinsic::x86_fma_vfmaddsub_pd:
16897 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16898 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16899 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16900 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16901 return X86ISD::FMADDSUB;
16902 case Intrinsic::x86_fma_vfmsubadd_ps:
16903 case Intrinsic::x86_fma_vfmsubadd_pd:
16904 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16905 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16906 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16907 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16908 return X86ISD::FMSUBADD;
16912 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16913 SelectionDAG &DAG) {
16915 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16916 EVT VT = Op.getValueType();
16917 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16919 switch(IntrData->Type) {
16920 case INTR_TYPE_1OP:
16921 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16922 case INTR_TYPE_2OP:
16923 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16925 case INTR_TYPE_3OP:
16926 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16927 Op.getOperand(2), Op.getOperand(3));
16928 case INTR_TYPE_1OP_MASK_RM: {
16929 SDValue Src = Op.getOperand(1);
16930 SDValue Src0 = Op.getOperand(2);
16931 SDValue Mask = Op.getOperand(3);
16932 SDValue RoundingMode = Op.getOperand(4);
16933 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16935 Mask, Src0, Subtarget, DAG);
16937 case INTR_TYPE_SCALAR_MASK_RM: {
16938 SDValue Src1 = Op.getOperand(1);
16939 SDValue Src2 = Op.getOperand(2);
16940 SDValue Src0 = Op.getOperand(3);
16941 SDValue Mask = Op.getOperand(4);
16942 SDValue RoundingMode = Op.getOperand(5);
16943 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16945 Mask, Src0, Subtarget, DAG);
16947 case INTR_TYPE_2OP_MASK: {
16948 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16950 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16953 case CMP_MASK_CC: {
16954 // Comparison intrinsics with masks.
16955 // Example of transformation:
16956 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16957 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16959 // (v8i1 (insert_subvector undef,
16960 // (v2i1 (and (PCMPEQM %a, %b),
16961 // (extract_subvector
16962 // (v8i1 (bitcast %mask)), 0))), 0))))
16963 EVT VT = Op.getOperand(1).getValueType();
16964 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16965 VT.getVectorNumElements());
16966 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16967 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16968 Mask.getValueType().getSizeInBits());
16970 if (IntrData->Type == CMP_MASK_CC) {
16971 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16972 Op.getOperand(2), Op.getOperand(3));
16974 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16975 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16978 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16979 DAG.getTargetConstant(0, MaskVT),
16981 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16982 DAG.getUNDEF(BitcastVT), CmpMask,
16983 DAG.getIntPtrConstant(0));
16984 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16986 case COMI: { // Comparison intrinsics
16987 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16988 SDValue LHS = Op.getOperand(1);
16989 SDValue RHS = Op.getOperand(2);
16990 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16991 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16992 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16993 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16994 DAG.getConstant(X86CC, MVT::i8), Cond);
16995 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16998 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16999 Op.getOperand(1), Op.getOperand(2), DAG);
17001 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
17002 Op.getSimpleValueType(),
17004 Op.getOperand(2), DAG),
17005 Op.getOperand(4), Op.getOperand(3), Subtarget,
17007 case COMPRESS_EXPAND_IN_REG: {
17008 SDValue Mask = Op.getOperand(3);
17009 SDValue DataToCompress = Op.getOperand(1);
17010 SDValue PassThru = Op.getOperand(2);
17011 if (isAllOnes(Mask)) // return data as is
17012 return Op.getOperand(1);
17013 EVT VT = Op.getValueType();
17014 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17015 VT.getVectorNumElements());
17016 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17017 Mask.getValueType().getSizeInBits());
17019 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17020 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17021 DAG.getIntPtrConstant(0));
17023 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17027 SDValue Mask = Op.getOperand(3);
17028 EVT VT = Op.getValueType();
17029 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17030 VT.getVectorNumElements());
17031 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17032 Mask.getValueType().getSizeInBits());
17034 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17035 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17036 DAG.getIntPtrConstant(0));
17037 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17046 default: return SDValue(); // Don't custom lower most intrinsics.
17048 case Intrinsic::x86_avx512_mask_valign_q_512:
17049 case Intrinsic::x86_avx512_mask_valign_d_512:
17050 // Vector source operands are swapped.
17051 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17052 Op.getValueType(), Op.getOperand(2),
17055 Op.getOperand(5), Op.getOperand(4),
17058 // ptest and testp intrinsics. The intrinsic these come from are designed to
17059 // return an integer value, not just an instruction so lower it to the ptest
17060 // or testp pattern and a setcc for the result.
17061 case Intrinsic::x86_sse41_ptestz:
17062 case Intrinsic::x86_sse41_ptestc:
17063 case Intrinsic::x86_sse41_ptestnzc:
17064 case Intrinsic::x86_avx_ptestz_256:
17065 case Intrinsic::x86_avx_ptestc_256:
17066 case Intrinsic::x86_avx_ptestnzc_256:
17067 case Intrinsic::x86_avx_vtestz_ps:
17068 case Intrinsic::x86_avx_vtestc_ps:
17069 case Intrinsic::x86_avx_vtestnzc_ps:
17070 case Intrinsic::x86_avx_vtestz_pd:
17071 case Intrinsic::x86_avx_vtestc_pd:
17072 case Intrinsic::x86_avx_vtestnzc_pd:
17073 case Intrinsic::x86_avx_vtestz_ps_256:
17074 case Intrinsic::x86_avx_vtestc_ps_256:
17075 case Intrinsic::x86_avx_vtestnzc_ps_256:
17076 case Intrinsic::x86_avx_vtestz_pd_256:
17077 case Intrinsic::x86_avx_vtestc_pd_256:
17078 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17079 bool IsTestPacked = false;
17082 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17083 case Intrinsic::x86_avx_vtestz_ps:
17084 case Intrinsic::x86_avx_vtestz_pd:
17085 case Intrinsic::x86_avx_vtestz_ps_256:
17086 case Intrinsic::x86_avx_vtestz_pd_256:
17087 IsTestPacked = true; // Fallthrough
17088 case Intrinsic::x86_sse41_ptestz:
17089 case Intrinsic::x86_avx_ptestz_256:
17091 X86CC = X86::COND_E;
17093 case Intrinsic::x86_avx_vtestc_ps:
17094 case Intrinsic::x86_avx_vtestc_pd:
17095 case Intrinsic::x86_avx_vtestc_ps_256:
17096 case Intrinsic::x86_avx_vtestc_pd_256:
17097 IsTestPacked = true; // Fallthrough
17098 case Intrinsic::x86_sse41_ptestc:
17099 case Intrinsic::x86_avx_ptestc_256:
17101 X86CC = X86::COND_B;
17103 case Intrinsic::x86_avx_vtestnzc_ps:
17104 case Intrinsic::x86_avx_vtestnzc_pd:
17105 case Intrinsic::x86_avx_vtestnzc_ps_256:
17106 case Intrinsic::x86_avx_vtestnzc_pd_256:
17107 IsTestPacked = true; // Fallthrough
17108 case Intrinsic::x86_sse41_ptestnzc:
17109 case Intrinsic::x86_avx_ptestnzc_256:
17111 X86CC = X86::COND_A;
17115 SDValue LHS = Op.getOperand(1);
17116 SDValue RHS = Op.getOperand(2);
17117 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17118 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17119 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17120 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17121 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17123 case Intrinsic::x86_avx512_kortestz_w:
17124 case Intrinsic::x86_avx512_kortestc_w: {
17125 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17126 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17127 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17128 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17129 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17130 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17131 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17134 case Intrinsic::x86_sse42_pcmpistria128:
17135 case Intrinsic::x86_sse42_pcmpestria128:
17136 case Intrinsic::x86_sse42_pcmpistric128:
17137 case Intrinsic::x86_sse42_pcmpestric128:
17138 case Intrinsic::x86_sse42_pcmpistrio128:
17139 case Intrinsic::x86_sse42_pcmpestrio128:
17140 case Intrinsic::x86_sse42_pcmpistris128:
17141 case Intrinsic::x86_sse42_pcmpestris128:
17142 case Intrinsic::x86_sse42_pcmpistriz128:
17143 case Intrinsic::x86_sse42_pcmpestriz128: {
17147 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17148 case Intrinsic::x86_sse42_pcmpistria128:
17149 Opcode = X86ISD::PCMPISTRI;
17150 X86CC = X86::COND_A;
17152 case Intrinsic::x86_sse42_pcmpestria128:
17153 Opcode = X86ISD::PCMPESTRI;
17154 X86CC = X86::COND_A;
17156 case Intrinsic::x86_sse42_pcmpistric128:
17157 Opcode = X86ISD::PCMPISTRI;
17158 X86CC = X86::COND_B;
17160 case Intrinsic::x86_sse42_pcmpestric128:
17161 Opcode = X86ISD::PCMPESTRI;
17162 X86CC = X86::COND_B;
17164 case Intrinsic::x86_sse42_pcmpistrio128:
17165 Opcode = X86ISD::PCMPISTRI;
17166 X86CC = X86::COND_O;
17168 case Intrinsic::x86_sse42_pcmpestrio128:
17169 Opcode = X86ISD::PCMPESTRI;
17170 X86CC = X86::COND_O;
17172 case Intrinsic::x86_sse42_pcmpistris128:
17173 Opcode = X86ISD::PCMPISTRI;
17174 X86CC = X86::COND_S;
17176 case Intrinsic::x86_sse42_pcmpestris128:
17177 Opcode = X86ISD::PCMPESTRI;
17178 X86CC = X86::COND_S;
17180 case Intrinsic::x86_sse42_pcmpistriz128:
17181 Opcode = X86ISD::PCMPISTRI;
17182 X86CC = X86::COND_E;
17184 case Intrinsic::x86_sse42_pcmpestriz128:
17185 Opcode = X86ISD::PCMPESTRI;
17186 X86CC = X86::COND_E;
17189 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17190 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17191 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17192 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17193 DAG.getConstant(X86CC, MVT::i8),
17194 SDValue(PCMP.getNode(), 1));
17195 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17198 case Intrinsic::x86_sse42_pcmpistri128:
17199 case Intrinsic::x86_sse42_pcmpestri128: {
17201 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17202 Opcode = X86ISD::PCMPISTRI;
17204 Opcode = X86ISD::PCMPESTRI;
17206 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17207 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17208 return DAG.getNode(Opcode, dl, VTs, NewOps);
17211 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17212 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17213 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17214 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17215 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17216 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17217 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17218 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17219 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17220 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17221 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17222 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17223 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17224 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17225 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17226 dl, Op.getValueType(),
17230 Op.getOperand(4), Op.getOperand(1),
17236 case Intrinsic::x86_fma_vfmadd_ps:
17237 case Intrinsic::x86_fma_vfmadd_pd:
17238 case Intrinsic::x86_fma_vfmsub_ps:
17239 case Intrinsic::x86_fma_vfmsub_pd:
17240 case Intrinsic::x86_fma_vfnmadd_ps:
17241 case Intrinsic::x86_fma_vfnmadd_pd:
17242 case Intrinsic::x86_fma_vfnmsub_ps:
17243 case Intrinsic::x86_fma_vfnmsub_pd:
17244 case Intrinsic::x86_fma_vfmaddsub_ps:
17245 case Intrinsic::x86_fma_vfmaddsub_pd:
17246 case Intrinsic::x86_fma_vfmsubadd_ps:
17247 case Intrinsic::x86_fma_vfmsubadd_pd:
17248 case Intrinsic::x86_fma_vfmadd_ps_256:
17249 case Intrinsic::x86_fma_vfmadd_pd_256:
17250 case Intrinsic::x86_fma_vfmsub_ps_256:
17251 case Intrinsic::x86_fma_vfmsub_pd_256:
17252 case Intrinsic::x86_fma_vfnmadd_ps_256:
17253 case Intrinsic::x86_fma_vfnmadd_pd_256:
17254 case Intrinsic::x86_fma_vfnmsub_ps_256:
17255 case Intrinsic::x86_fma_vfnmsub_pd_256:
17256 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17257 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17258 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17259 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17260 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17261 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17265 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17266 SDValue Src, SDValue Mask, SDValue Base,
17267 SDValue Index, SDValue ScaleOp, SDValue Chain,
17268 const X86Subtarget * Subtarget) {
17270 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17271 assert(C && "Invalid scale type");
17272 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17273 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17274 Index.getSimpleValueType().getVectorNumElements());
17276 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17278 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17280 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17281 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17282 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17283 SDValue Segment = DAG.getRegister(0, MVT::i32);
17284 if (Src.getOpcode() == ISD::UNDEF)
17285 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17286 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17287 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17288 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17289 return DAG.getMergeValues(RetOps, dl);
17292 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17293 SDValue Src, SDValue Mask, SDValue Base,
17294 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17296 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17297 assert(C && "Invalid scale type");
17298 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17299 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17300 SDValue Segment = DAG.getRegister(0, MVT::i32);
17301 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17302 Index.getSimpleValueType().getVectorNumElements());
17304 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17306 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17308 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17309 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17310 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17311 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17312 return SDValue(Res, 1);
17315 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17316 SDValue Mask, SDValue Base, SDValue Index,
17317 SDValue ScaleOp, SDValue Chain) {
17319 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17320 assert(C && "Invalid scale type");
17321 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17322 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17323 SDValue Segment = DAG.getRegister(0, MVT::i32);
17325 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17327 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17329 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17331 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17332 //SDVTList VTs = DAG.getVTList(MVT::Other);
17333 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17334 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17335 return SDValue(Res, 0);
17338 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17339 // read performance monitor counters (x86_rdpmc).
17340 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17341 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17342 SmallVectorImpl<SDValue> &Results) {
17343 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17344 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17347 // The ECX register is used to select the index of the performance counter
17349 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17351 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17353 // Reads the content of a 64-bit performance counter and returns it in the
17354 // registers EDX:EAX.
17355 if (Subtarget->is64Bit()) {
17356 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17357 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17360 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17361 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17364 Chain = HI.getValue(1);
17366 if (Subtarget->is64Bit()) {
17367 // The EAX register is loaded with the low-order 32 bits. The EDX register
17368 // is loaded with the supported high-order bits of the counter.
17369 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17370 DAG.getConstant(32, MVT::i8));
17371 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17372 Results.push_back(Chain);
17376 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17377 SDValue Ops[] = { LO, HI };
17378 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17379 Results.push_back(Pair);
17380 Results.push_back(Chain);
17383 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17384 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17385 // also used to custom lower READCYCLECOUNTER nodes.
17386 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17387 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17388 SmallVectorImpl<SDValue> &Results) {
17389 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17390 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17393 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17394 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17395 // and the EAX register is loaded with the low-order 32 bits.
17396 if (Subtarget->is64Bit()) {
17397 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17398 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17401 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17402 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17405 SDValue Chain = HI.getValue(1);
17407 if (Opcode == X86ISD::RDTSCP_DAG) {
17408 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17410 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17411 // the ECX register. Add 'ecx' explicitly to the chain.
17412 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17414 // Explicitly store the content of ECX at the location passed in input
17415 // to the 'rdtscp' intrinsic.
17416 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17417 MachinePointerInfo(), false, false, 0);
17420 if (Subtarget->is64Bit()) {
17421 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17422 // the EAX register is loaded with the low-order 32 bits.
17423 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17424 DAG.getConstant(32, MVT::i8));
17425 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17426 Results.push_back(Chain);
17430 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17431 SDValue Ops[] = { LO, HI };
17432 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17433 Results.push_back(Pair);
17434 Results.push_back(Chain);
17437 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17438 SelectionDAG &DAG) {
17439 SmallVector<SDValue, 2> Results;
17441 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17443 return DAG.getMergeValues(Results, DL);
17447 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17448 SelectionDAG &DAG) {
17449 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17451 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17456 switch(IntrData->Type) {
17458 llvm_unreachable("Unknown Intrinsic Type");
17462 // Emit the node with the right value type.
17463 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17464 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17466 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17467 // Otherwise return the value from Rand, which is always 0, casted to i32.
17468 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17469 DAG.getConstant(1, Op->getValueType(1)),
17470 DAG.getConstant(X86::COND_B, MVT::i32),
17471 SDValue(Result.getNode(), 1) };
17472 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17473 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17476 // Return { result, isValid, chain }.
17477 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17478 SDValue(Result.getNode(), 2));
17481 //gather(v1, mask, index, base, scale);
17482 SDValue Chain = Op.getOperand(0);
17483 SDValue Src = Op.getOperand(2);
17484 SDValue Base = Op.getOperand(3);
17485 SDValue Index = Op.getOperand(4);
17486 SDValue Mask = Op.getOperand(5);
17487 SDValue Scale = Op.getOperand(6);
17488 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17492 //scatter(base, mask, index, v1, scale);
17493 SDValue Chain = Op.getOperand(0);
17494 SDValue Base = Op.getOperand(2);
17495 SDValue Mask = Op.getOperand(3);
17496 SDValue Index = Op.getOperand(4);
17497 SDValue Src = Op.getOperand(5);
17498 SDValue Scale = Op.getOperand(6);
17499 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17502 SDValue Hint = Op.getOperand(6);
17504 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17505 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17506 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17507 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17508 SDValue Chain = Op.getOperand(0);
17509 SDValue Mask = Op.getOperand(2);
17510 SDValue Index = Op.getOperand(3);
17511 SDValue Base = Op.getOperand(4);
17512 SDValue Scale = Op.getOperand(5);
17513 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17515 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17517 SmallVector<SDValue, 2> Results;
17518 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17519 return DAG.getMergeValues(Results, dl);
17521 // Read Performance Monitoring Counters.
17523 SmallVector<SDValue, 2> Results;
17524 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17525 return DAG.getMergeValues(Results, dl);
17527 // XTEST intrinsics.
17529 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17530 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17531 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17532 DAG.getConstant(X86::COND_NE, MVT::i8),
17534 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17535 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17536 Ret, SDValue(InTrans.getNode(), 1));
17540 SmallVector<SDValue, 2> Results;
17541 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17542 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17543 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17544 DAG.getConstant(-1, MVT::i8));
17545 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17546 Op.getOperand(4), GenCF.getValue(1));
17547 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17548 Op.getOperand(5), MachinePointerInfo(),
17550 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17551 DAG.getConstant(X86::COND_B, MVT::i8),
17553 Results.push_back(SetCC);
17554 Results.push_back(Store);
17555 return DAG.getMergeValues(Results, dl);
17557 case COMPRESS_TO_MEM: {
17559 SDValue Mask = Op.getOperand(4);
17560 SDValue DataToCompress = Op.getOperand(3);
17561 SDValue Addr = Op.getOperand(2);
17562 SDValue Chain = Op.getOperand(0);
17564 if (isAllOnes(Mask)) // return just a store
17565 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17566 MachinePointerInfo(), false, false, 0);
17568 EVT VT = DataToCompress.getValueType();
17569 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17570 VT.getVectorNumElements());
17571 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17572 Mask.getValueType().getSizeInBits());
17573 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17574 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17575 DAG.getIntPtrConstant(0));
17577 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17578 DataToCompress, DAG.getUNDEF(VT));
17579 return DAG.getStore(Chain, dl, Compressed, Addr,
17580 MachinePointerInfo(), false, false, 0);
17582 case EXPAND_FROM_MEM: {
17584 SDValue Mask = Op.getOperand(4);
17585 SDValue PathThru = Op.getOperand(3);
17586 SDValue Addr = Op.getOperand(2);
17587 SDValue Chain = Op.getOperand(0);
17588 EVT VT = Op.getValueType();
17590 if (isAllOnes(Mask)) // return just a load
17591 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17593 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17594 VT.getVectorNumElements());
17595 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17596 Mask.getValueType().getSizeInBits());
17597 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17598 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17599 DAG.getIntPtrConstant(0));
17601 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17602 false, false, false, 0);
17604 SmallVector<SDValue, 2> Results;
17605 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17607 Results.push_back(Chain);
17608 return DAG.getMergeValues(Results, dl);
17613 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17614 SelectionDAG &DAG) const {
17615 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17616 MFI->setReturnAddressIsTaken(true);
17618 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17621 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17623 EVT PtrVT = getPointerTy();
17626 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17628 DAG.getSubtarget().getRegisterInfo());
17629 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17630 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17631 DAG.getNode(ISD::ADD, dl, PtrVT,
17632 FrameAddr, Offset),
17633 MachinePointerInfo(), false, false, false, 0);
17636 // Just load the return address.
17637 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17638 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17639 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17642 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17643 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17644 MFI->setFrameAddressIsTaken(true);
17646 EVT VT = Op.getValueType();
17647 SDLoc dl(Op); // FIXME probably not meaningful
17648 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17649 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17650 DAG.getSubtarget().getRegisterInfo());
17651 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17652 DAG.getMachineFunction());
17653 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17654 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17655 "Invalid Frame Register!");
17656 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17658 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17659 MachinePointerInfo(),
17660 false, false, false, 0);
17664 // FIXME? Maybe this could be a TableGen attribute on some registers and
17665 // this table could be generated automatically from RegInfo.
17666 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17668 unsigned Reg = StringSwitch<unsigned>(RegName)
17669 .Case("esp", X86::ESP)
17670 .Case("rsp", X86::RSP)
17674 report_fatal_error("Invalid register name global variable");
17677 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17678 SelectionDAG &DAG) const {
17679 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17680 DAG.getSubtarget().getRegisterInfo());
17681 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17684 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17685 SDValue Chain = Op.getOperand(0);
17686 SDValue Offset = Op.getOperand(1);
17687 SDValue Handler = Op.getOperand(2);
17690 EVT PtrVT = getPointerTy();
17691 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17692 DAG.getSubtarget().getRegisterInfo());
17693 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17694 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17695 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17696 "Invalid Frame Register!");
17697 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17698 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17700 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17701 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17702 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17703 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17705 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17707 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17708 DAG.getRegister(StoreAddrReg, PtrVT));
17711 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17712 SelectionDAG &DAG) const {
17714 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17715 DAG.getVTList(MVT::i32, MVT::Other),
17716 Op.getOperand(0), Op.getOperand(1));
17719 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17720 SelectionDAG &DAG) const {
17722 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17723 Op.getOperand(0), Op.getOperand(1));
17726 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17727 return Op.getOperand(0);
17730 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17731 SelectionDAG &DAG) const {
17732 SDValue Root = Op.getOperand(0);
17733 SDValue Trmp = Op.getOperand(1); // trampoline
17734 SDValue FPtr = Op.getOperand(2); // nested function
17735 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17738 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17739 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17741 if (Subtarget->is64Bit()) {
17742 SDValue OutChains[6];
17744 // Large code-model.
17745 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17746 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17748 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17749 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17751 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17753 // Load the pointer to the nested function into R11.
17754 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17755 SDValue Addr = Trmp;
17756 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17757 Addr, MachinePointerInfo(TrmpAddr),
17760 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17761 DAG.getConstant(2, MVT::i64));
17762 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17763 MachinePointerInfo(TrmpAddr, 2),
17766 // Load the 'nest' parameter value into R10.
17767 // R10 is specified in X86CallingConv.td
17768 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17769 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17770 DAG.getConstant(10, MVT::i64));
17771 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17772 Addr, MachinePointerInfo(TrmpAddr, 10),
17775 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17776 DAG.getConstant(12, MVT::i64));
17777 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17778 MachinePointerInfo(TrmpAddr, 12),
17781 // Jump to the nested function.
17782 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17783 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17784 DAG.getConstant(20, MVT::i64));
17785 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17786 Addr, MachinePointerInfo(TrmpAddr, 20),
17789 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17790 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17791 DAG.getConstant(22, MVT::i64));
17792 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17793 MachinePointerInfo(TrmpAddr, 22),
17796 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17798 const Function *Func =
17799 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17800 CallingConv::ID CC = Func->getCallingConv();
17805 llvm_unreachable("Unsupported calling convention");
17806 case CallingConv::C:
17807 case CallingConv::X86_StdCall: {
17808 // Pass 'nest' parameter in ECX.
17809 // Must be kept in sync with X86CallingConv.td
17810 NestReg = X86::ECX;
17812 // Check that ECX wasn't needed by an 'inreg' parameter.
17813 FunctionType *FTy = Func->getFunctionType();
17814 const AttributeSet &Attrs = Func->getAttributes();
17816 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17817 unsigned InRegCount = 0;
17820 for (FunctionType::param_iterator I = FTy->param_begin(),
17821 E = FTy->param_end(); I != E; ++I, ++Idx)
17822 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17823 // FIXME: should only count parameters that are lowered to integers.
17824 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17826 if (InRegCount > 2) {
17827 report_fatal_error("Nest register in use - reduce number of inreg"
17833 case CallingConv::X86_FastCall:
17834 case CallingConv::X86_ThisCall:
17835 case CallingConv::Fast:
17836 // Pass 'nest' parameter in EAX.
17837 // Must be kept in sync with X86CallingConv.td
17838 NestReg = X86::EAX;
17842 SDValue OutChains[4];
17843 SDValue Addr, Disp;
17845 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17846 DAG.getConstant(10, MVT::i32));
17847 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17849 // This is storing the opcode for MOV32ri.
17850 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17851 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17852 OutChains[0] = DAG.getStore(Root, dl,
17853 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17854 Trmp, MachinePointerInfo(TrmpAddr),
17857 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17858 DAG.getConstant(1, MVT::i32));
17859 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17860 MachinePointerInfo(TrmpAddr, 1),
17863 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17864 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17865 DAG.getConstant(5, MVT::i32));
17866 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17867 MachinePointerInfo(TrmpAddr, 5),
17870 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17871 DAG.getConstant(6, MVT::i32));
17872 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17873 MachinePointerInfo(TrmpAddr, 6),
17876 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17880 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17881 SelectionDAG &DAG) const {
17883 The rounding mode is in bits 11:10 of FPSR, and has the following
17885 00 Round to nearest
17890 FLT_ROUNDS, on the other hand, expects the following:
17897 To perform the conversion, we do:
17898 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17901 MachineFunction &MF = DAG.getMachineFunction();
17902 const TargetMachine &TM = MF.getTarget();
17903 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17904 unsigned StackAlignment = TFI.getStackAlignment();
17905 MVT VT = Op.getSimpleValueType();
17908 // Save FP Control Word to stack slot
17909 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17910 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17912 MachineMemOperand *MMO =
17913 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17914 MachineMemOperand::MOStore, 2, 2);
17916 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17917 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17918 DAG.getVTList(MVT::Other),
17919 Ops, MVT::i16, MMO);
17921 // Load FP Control Word from stack slot
17922 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17923 MachinePointerInfo(), false, false, false, 0);
17925 // Transform as necessary
17927 DAG.getNode(ISD::SRL, DL, MVT::i16,
17928 DAG.getNode(ISD::AND, DL, MVT::i16,
17929 CWD, DAG.getConstant(0x800, MVT::i16)),
17930 DAG.getConstant(11, MVT::i8));
17932 DAG.getNode(ISD::SRL, DL, MVT::i16,
17933 DAG.getNode(ISD::AND, DL, MVT::i16,
17934 CWD, DAG.getConstant(0x400, MVT::i16)),
17935 DAG.getConstant(9, MVT::i8));
17938 DAG.getNode(ISD::AND, DL, MVT::i16,
17939 DAG.getNode(ISD::ADD, DL, MVT::i16,
17940 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17941 DAG.getConstant(1, MVT::i16)),
17942 DAG.getConstant(3, MVT::i16));
17944 return DAG.getNode((VT.getSizeInBits() < 16 ?
17945 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17948 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17949 MVT VT = Op.getSimpleValueType();
17951 unsigned NumBits = VT.getSizeInBits();
17954 Op = Op.getOperand(0);
17955 if (VT == MVT::i8) {
17956 // Zero extend to i32 since there is not an i8 bsr.
17958 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17961 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17962 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17963 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17965 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17968 DAG.getConstant(NumBits+NumBits-1, OpVT),
17969 DAG.getConstant(X86::COND_E, MVT::i8),
17972 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17974 // Finally xor with NumBits-1.
17975 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17978 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17982 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17983 MVT VT = Op.getSimpleValueType();
17985 unsigned NumBits = VT.getSizeInBits();
17988 Op = Op.getOperand(0);
17989 if (VT == MVT::i8) {
17990 // Zero extend to i32 since there is not an i8 bsr.
17992 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17995 // Issue a bsr (scan bits in reverse).
17996 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17997 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17999 // And xor with NumBits-1.
18000 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18003 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18007 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18008 MVT VT = Op.getSimpleValueType();
18009 unsigned NumBits = VT.getSizeInBits();
18011 Op = Op.getOperand(0);
18013 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18014 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18015 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18017 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18020 DAG.getConstant(NumBits, VT),
18021 DAG.getConstant(X86::COND_E, MVT::i8),
18024 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18027 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18028 // ones, and then concatenate the result back.
18029 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18030 MVT VT = Op.getSimpleValueType();
18032 assert(VT.is256BitVector() && VT.isInteger() &&
18033 "Unsupported value type for operation");
18035 unsigned NumElems = VT.getVectorNumElements();
18038 // Extract the LHS vectors
18039 SDValue LHS = Op.getOperand(0);
18040 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18041 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18043 // Extract the RHS vectors
18044 SDValue RHS = Op.getOperand(1);
18045 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18046 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18048 MVT EltVT = VT.getVectorElementType();
18049 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18051 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18052 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18053 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18056 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18057 assert(Op.getSimpleValueType().is256BitVector() &&
18058 Op.getSimpleValueType().isInteger() &&
18059 "Only handle AVX 256-bit vector integer operation");
18060 return Lower256IntArith(Op, DAG);
18063 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18064 assert(Op.getSimpleValueType().is256BitVector() &&
18065 Op.getSimpleValueType().isInteger() &&
18066 "Only handle AVX 256-bit vector integer operation");
18067 return Lower256IntArith(Op, DAG);
18070 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18071 SelectionDAG &DAG) {
18073 MVT VT = Op.getSimpleValueType();
18075 // Decompose 256-bit ops into smaller 128-bit ops.
18076 if (VT.is256BitVector() && !Subtarget->hasInt256())
18077 return Lower256IntArith(Op, DAG);
18079 SDValue A = Op.getOperand(0);
18080 SDValue B = Op.getOperand(1);
18082 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18083 if (VT == MVT::v4i32) {
18084 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18085 "Should not custom lower when pmuldq is available!");
18087 // Extract the odd parts.
18088 static const int UnpackMask[] = { 1, -1, 3, -1 };
18089 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18090 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18092 // Multiply the even parts.
18093 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18094 // Now multiply odd parts.
18095 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18097 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18098 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18100 // Merge the two vectors back together with a shuffle. This expands into 2
18102 static const int ShufMask[] = { 0, 4, 2, 6 };
18103 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18106 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18107 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18109 // Ahi = psrlqi(a, 32);
18110 // Bhi = psrlqi(b, 32);
18112 // AloBlo = pmuludq(a, b);
18113 // AloBhi = pmuludq(a, Bhi);
18114 // AhiBlo = pmuludq(Ahi, b);
18116 // AloBhi = psllqi(AloBhi, 32);
18117 // AhiBlo = psllqi(AhiBlo, 32);
18118 // return AloBlo + AloBhi + AhiBlo;
18120 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18121 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18123 // Bit cast to 32-bit vectors for MULUDQ
18124 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18125 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18126 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18127 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18128 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18129 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18131 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18132 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18133 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18135 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18136 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18138 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18139 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18142 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18143 assert(Subtarget->isTargetWin64() && "Unexpected target");
18144 EVT VT = Op.getValueType();
18145 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18146 "Unexpected return type for lowering");
18150 switch (Op->getOpcode()) {
18151 default: llvm_unreachable("Unexpected request for libcall!");
18152 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18153 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18154 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18155 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18156 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18157 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18161 SDValue InChain = DAG.getEntryNode();
18163 TargetLowering::ArgListTy Args;
18164 TargetLowering::ArgListEntry Entry;
18165 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18166 EVT ArgVT = Op->getOperand(i).getValueType();
18167 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18168 "Unexpected argument type for lowering");
18169 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18170 Entry.Node = StackPtr;
18171 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18173 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18174 Entry.Ty = PointerType::get(ArgTy,0);
18175 Entry.isSExt = false;
18176 Entry.isZExt = false;
18177 Args.push_back(Entry);
18180 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18183 TargetLowering::CallLoweringInfo CLI(DAG);
18184 CLI.setDebugLoc(dl).setChain(InChain)
18185 .setCallee(getLibcallCallingConv(LC),
18186 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18187 Callee, std::move(Args), 0)
18188 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18190 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18191 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18194 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18195 SelectionDAG &DAG) {
18196 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18197 EVT VT = Op0.getValueType();
18200 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18201 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18203 // PMULxD operations multiply each even value (starting at 0) of LHS with
18204 // the related value of RHS and produce a widen result.
18205 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18206 // => <2 x i64> <ae|cg>
18208 // In other word, to have all the results, we need to perform two PMULxD:
18209 // 1. one with the even values.
18210 // 2. one with the odd values.
18211 // To achieve #2, with need to place the odd values at an even position.
18213 // Place the odd value at an even position (basically, shift all values 1
18214 // step to the left):
18215 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18216 // <a|b|c|d> => <b|undef|d|undef>
18217 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18218 // <e|f|g|h> => <f|undef|h|undef>
18219 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18221 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18223 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18224 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18226 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18227 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18228 // => <2 x i64> <ae|cg>
18229 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18230 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18231 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18232 // => <2 x i64> <bf|dh>
18233 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18234 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18236 // Shuffle it back into the right order.
18237 SDValue Highs, Lows;
18238 if (VT == MVT::v8i32) {
18239 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18240 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18241 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18242 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18244 const int HighMask[] = {1, 5, 3, 7};
18245 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18246 const int LowMask[] = {0, 4, 2, 6};
18247 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18250 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18251 // unsigned multiply.
18252 if (IsSigned && !Subtarget->hasSSE41()) {
18254 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18255 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18256 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18257 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18258 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18260 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18261 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18264 // The first result of MUL_LOHI is actually the low value, followed by the
18266 SDValue Ops[] = {Lows, Highs};
18267 return DAG.getMergeValues(Ops, dl);
18270 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18271 const X86Subtarget *Subtarget) {
18272 MVT VT = Op.getSimpleValueType();
18274 SDValue R = Op.getOperand(0);
18275 SDValue Amt = Op.getOperand(1);
18277 // Optimize shl/srl/sra with constant shift amount.
18278 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18279 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18280 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18282 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18283 (Subtarget->hasInt256() &&
18284 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18285 (Subtarget->hasAVX512() &&
18286 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18287 if (Op.getOpcode() == ISD::SHL)
18288 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18290 if (Op.getOpcode() == ISD::SRL)
18291 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18293 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18294 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18298 if (VT == MVT::v16i8) {
18299 if (Op.getOpcode() == ISD::SHL) {
18300 // Make a large shift.
18301 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18302 MVT::v8i16, R, ShiftAmt,
18304 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18305 // Zero out the rightmost bits.
18306 SmallVector<SDValue, 16> V(16,
18307 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18309 return DAG.getNode(ISD::AND, dl, VT, SHL,
18310 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18312 if (Op.getOpcode() == ISD::SRL) {
18313 // Make a large shift.
18314 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18315 MVT::v8i16, R, ShiftAmt,
18317 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18318 // Zero out the leftmost bits.
18319 SmallVector<SDValue, 16> V(16,
18320 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18322 return DAG.getNode(ISD::AND, dl, VT, SRL,
18323 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18325 if (Op.getOpcode() == ISD::SRA) {
18326 if (ShiftAmt == 7) {
18327 // R s>> 7 === R s< 0
18328 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18329 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18332 // R s>> a === ((R u>> a) ^ m) - m
18333 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18334 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18336 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18337 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18338 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18341 llvm_unreachable("Unknown shift opcode.");
18344 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18345 if (Op.getOpcode() == ISD::SHL) {
18346 // Make a large shift.
18347 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18348 MVT::v16i16, R, ShiftAmt,
18350 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18351 // Zero out the rightmost bits.
18352 SmallVector<SDValue, 32> V(32,
18353 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18355 return DAG.getNode(ISD::AND, dl, VT, SHL,
18356 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18358 if (Op.getOpcode() == ISD::SRL) {
18359 // Make a large shift.
18360 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18361 MVT::v16i16, R, ShiftAmt,
18363 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18364 // Zero out the leftmost bits.
18365 SmallVector<SDValue, 32> V(32,
18366 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18368 return DAG.getNode(ISD::AND, dl, VT, SRL,
18369 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18371 if (Op.getOpcode() == ISD::SRA) {
18372 if (ShiftAmt == 7) {
18373 // R s>> 7 === R s< 0
18374 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18375 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18378 // R s>> a === ((R u>> a) ^ m) - m
18379 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18380 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18382 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18383 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18384 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18387 llvm_unreachable("Unknown shift opcode.");
18392 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18393 if (!Subtarget->is64Bit() &&
18394 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18395 Amt.getOpcode() == ISD::BITCAST &&
18396 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18397 Amt = Amt.getOperand(0);
18398 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18399 VT.getVectorNumElements();
18400 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18401 uint64_t ShiftAmt = 0;
18402 for (unsigned i = 0; i != Ratio; ++i) {
18403 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18407 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18409 // Check remaining shift amounts.
18410 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18411 uint64_t ShAmt = 0;
18412 for (unsigned j = 0; j != Ratio; ++j) {
18413 ConstantSDNode *C =
18414 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18418 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18420 if (ShAmt != ShiftAmt)
18423 switch (Op.getOpcode()) {
18425 llvm_unreachable("Unknown shift opcode!");
18427 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18430 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18433 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18441 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18442 const X86Subtarget* Subtarget) {
18443 MVT VT = Op.getSimpleValueType();
18445 SDValue R = Op.getOperand(0);
18446 SDValue Amt = Op.getOperand(1);
18448 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18449 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18450 (Subtarget->hasInt256() &&
18451 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18452 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18453 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18455 EVT EltVT = VT.getVectorElementType();
18457 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18458 // Check if this build_vector node is doing a splat.
18459 // If so, then set BaseShAmt equal to the splat value.
18460 BaseShAmt = BV->getSplatValue();
18461 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18462 BaseShAmt = SDValue();
18464 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18465 Amt = Amt.getOperand(0);
18467 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18468 if (SVN && SVN->isSplat()) {
18469 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18470 SDValue InVec = Amt.getOperand(0);
18471 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18472 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18473 "Unexpected shuffle index found!");
18474 BaseShAmt = InVec.getOperand(SplatIdx);
18475 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18476 if (ConstantSDNode *C =
18477 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18478 if (C->getZExtValue() == SplatIdx)
18479 BaseShAmt = InVec.getOperand(1);
18484 // Avoid introducing an extract element from a shuffle.
18485 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18486 DAG.getIntPtrConstant(SplatIdx));
18490 if (BaseShAmt.getNode()) {
18491 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18492 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18493 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18494 else if (EltVT.bitsLT(MVT::i32))
18495 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18497 switch (Op.getOpcode()) {
18499 llvm_unreachable("Unknown shift opcode!");
18501 switch (VT.SimpleTy) {
18502 default: return SDValue();
18511 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18514 switch (VT.SimpleTy) {
18515 default: return SDValue();
18522 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18525 switch (VT.SimpleTy) {
18526 default: return SDValue();
18535 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18541 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18542 if (!Subtarget->is64Bit() &&
18543 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18544 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18545 Amt.getOpcode() == ISD::BITCAST &&
18546 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18547 Amt = Amt.getOperand(0);
18548 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18549 VT.getVectorNumElements();
18550 std::vector<SDValue> Vals(Ratio);
18551 for (unsigned i = 0; i != Ratio; ++i)
18552 Vals[i] = Amt.getOperand(i);
18553 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18554 for (unsigned j = 0; j != Ratio; ++j)
18555 if (Vals[j] != Amt.getOperand(i + j))
18558 switch (Op.getOpcode()) {
18560 llvm_unreachable("Unknown shift opcode!");
18562 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18564 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18566 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18573 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18574 SelectionDAG &DAG) {
18575 MVT VT = Op.getSimpleValueType();
18577 SDValue R = Op.getOperand(0);
18578 SDValue Amt = Op.getOperand(1);
18581 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18582 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18584 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18588 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18592 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18594 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18595 if (Subtarget->hasInt256()) {
18596 if (Op.getOpcode() == ISD::SRL &&
18597 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18598 VT == MVT::v4i64 || VT == MVT::v8i32))
18600 if (Op.getOpcode() == ISD::SHL &&
18601 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18602 VT == MVT::v4i64 || VT == MVT::v8i32))
18604 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18608 // If possible, lower this packed shift into a vector multiply instead of
18609 // expanding it into a sequence of scalar shifts.
18610 // Do this only if the vector shift count is a constant build_vector.
18611 if (Op.getOpcode() == ISD::SHL &&
18612 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18613 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18614 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18615 SmallVector<SDValue, 8> Elts;
18616 EVT SVT = VT.getScalarType();
18617 unsigned SVTBits = SVT.getSizeInBits();
18618 const APInt &One = APInt(SVTBits, 1);
18619 unsigned NumElems = VT.getVectorNumElements();
18621 for (unsigned i=0; i !=NumElems; ++i) {
18622 SDValue Op = Amt->getOperand(i);
18623 if (Op->getOpcode() == ISD::UNDEF) {
18624 Elts.push_back(Op);
18628 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18629 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18630 uint64_t ShAmt = C.getZExtValue();
18631 if (ShAmt >= SVTBits) {
18632 Elts.push_back(DAG.getUNDEF(SVT));
18635 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18637 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18638 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18641 // Lower SHL with variable shift amount.
18642 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18643 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18645 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18646 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18647 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18648 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18651 // If possible, lower this shift as a sequence of two shifts by
18652 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18654 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18656 // Could be rewritten as:
18657 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18659 // The advantage is that the two shifts from the example would be
18660 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18661 // the vector shift into four scalar shifts plus four pairs of vector
18663 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18664 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18665 unsigned TargetOpcode = X86ISD::MOVSS;
18666 bool CanBeSimplified;
18667 // The splat value for the first packed shift (the 'X' from the example).
18668 SDValue Amt1 = Amt->getOperand(0);
18669 // The splat value for the second packed shift (the 'Y' from the example).
18670 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18671 Amt->getOperand(2);
18673 // See if it is possible to replace this node with a sequence of
18674 // two shifts followed by a MOVSS/MOVSD
18675 if (VT == MVT::v4i32) {
18676 // Check if it is legal to use a MOVSS.
18677 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18678 Amt2 == Amt->getOperand(3);
18679 if (!CanBeSimplified) {
18680 // Otherwise, check if we can still simplify this node using a MOVSD.
18681 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18682 Amt->getOperand(2) == Amt->getOperand(3);
18683 TargetOpcode = X86ISD::MOVSD;
18684 Amt2 = Amt->getOperand(2);
18687 // Do similar checks for the case where the machine value type
18689 CanBeSimplified = Amt1 == Amt->getOperand(1);
18690 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18691 CanBeSimplified = Amt2 == Amt->getOperand(i);
18693 if (!CanBeSimplified) {
18694 TargetOpcode = X86ISD::MOVSD;
18695 CanBeSimplified = true;
18696 Amt2 = Amt->getOperand(4);
18697 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18698 CanBeSimplified = Amt1 == Amt->getOperand(i);
18699 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18700 CanBeSimplified = Amt2 == Amt->getOperand(j);
18704 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18705 isa<ConstantSDNode>(Amt2)) {
18706 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18707 EVT CastVT = MVT::v4i32;
18709 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18710 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18712 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18713 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18714 if (TargetOpcode == X86ISD::MOVSD)
18715 CastVT = MVT::v2i64;
18716 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18717 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18718 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18720 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18724 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18725 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18728 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18729 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18731 // Turn 'a' into a mask suitable for VSELECT
18732 SDValue VSelM = DAG.getConstant(0x80, VT);
18733 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18734 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18736 SDValue CM1 = DAG.getConstant(0x0f, VT);
18737 SDValue CM2 = DAG.getConstant(0x3f, VT);
18739 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18740 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18741 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18742 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18743 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18746 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18747 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18748 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18750 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18751 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18752 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18753 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18754 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18757 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18758 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18759 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18761 // return VSELECT(r, r+r, a);
18762 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18763 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18767 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18768 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18769 // solution better.
18770 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18771 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18773 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18774 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18775 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18776 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18777 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18780 // Decompose 256-bit shifts into smaller 128-bit shifts.
18781 if (VT.is256BitVector()) {
18782 unsigned NumElems = VT.getVectorNumElements();
18783 MVT EltVT = VT.getVectorElementType();
18784 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18786 // Extract the two vectors
18787 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18788 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18790 // Recreate the shift amount vectors
18791 SDValue Amt1, Amt2;
18792 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18793 // Constant shift amount
18794 SmallVector<SDValue, 4> Amt1Csts;
18795 SmallVector<SDValue, 4> Amt2Csts;
18796 for (unsigned i = 0; i != NumElems/2; ++i)
18797 Amt1Csts.push_back(Amt->getOperand(i));
18798 for (unsigned i = NumElems/2; i != NumElems; ++i)
18799 Amt2Csts.push_back(Amt->getOperand(i));
18801 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18802 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18804 // Variable shift amount
18805 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18806 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18809 // Issue new vector shifts for the smaller types
18810 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18811 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18813 // Concatenate the result back
18814 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18820 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18821 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18822 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18823 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18824 // has only one use.
18825 SDNode *N = Op.getNode();
18826 SDValue LHS = N->getOperand(0);
18827 SDValue RHS = N->getOperand(1);
18828 unsigned BaseOp = 0;
18831 switch (Op.getOpcode()) {
18832 default: llvm_unreachable("Unknown ovf instruction!");
18834 // A subtract of one will be selected as a INC. Note that INC doesn't
18835 // set CF, so we can't do this for UADDO.
18836 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18838 BaseOp = X86ISD::INC;
18839 Cond = X86::COND_O;
18842 BaseOp = X86ISD::ADD;
18843 Cond = X86::COND_O;
18846 BaseOp = X86ISD::ADD;
18847 Cond = X86::COND_B;
18850 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18851 // set CF, so we can't do this for USUBO.
18852 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18854 BaseOp = X86ISD::DEC;
18855 Cond = X86::COND_O;
18858 BaseOp = X86ISD::SUB;
18859 Cond = X86::COND_O;
18862 BaseOp = X86ISD::SUB;
18863 Cond = X86::COND_B;
18866 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18867 Cond = X86::COND_O;
18869 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18870 if (N->getValueType(0) == MVT::i8) {
18871 BaseOp = X86ISD::UMUL8;
18872 Cond = X86::COND_O;
18875 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18877 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18880 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18881 DAG.getConstant(X86::COND_O, MVT::i32),
18882 SDValue(Sum.getNode(), 2));
18884 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18888 // Also sets EFLAGS.
18889 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18890 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18893 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18894 DAG.getConstant(Cond, MVT::i32),
18895 SDValue(Sum.getNode(), 1));
18897 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18900 // Sign extension of the low part of vector elements. This may be used either
18901 // when sign extend instructions are not available or if the vector element
18902 // sizes already match the sign-extended size. If the vector elements are in
18903 // their pre-extended size and sign extend instructions are available, that will
18904 // be handled by LowerSIGN_EXTEND.
18905 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18906 SelectionDAG &DAG) const {
18908 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18909 MVT VT = Op.getSimpleValueType();
18911 if (!Subtarget->hasSSE2() || !VT.isVector())
18914 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18915 ExtraVT.getScalarType().getSizeInBits();
18917 switch (VT.SimpleTy) {
18918 default: return SDValue();
18921 if (!Subtarget->hasFp256())
18923 if (!Subtarget->hasInt256()) {
18924 // needs to be split
18925 unsigned NumElems = VT.getVectorNumElements();
18927 // Extract the LHS vectors
18928 SDValue LHS = Op.getOperand(0);
18929 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18930 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18932 MVT EltVT = VT.getVectorElementType();
18933 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18935 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18936 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18937 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18939 SDValue Extra = DAG.getValueType(ExtraVT);
18941 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18942 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18944 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18949 SDValue Op0 = Op.getOperand(0);
18951 // This is a sign extension of some low part of vector elements without
18952 // changing the size of the vector elements themselves:
18953 // Shift-Left + Shift-Right-Algebraic.
18954 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18956 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18962 /// Returns true if the operand type is exactly twice the native width, and
18963 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18964 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18965 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18966 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18967 const X86Subtarget &Subtarget =
18968 getTargetMachine().getSubtarget<X86Subtarget>();
18969 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18972 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18973 else if (OpWidth == 128)
18974 return Subtarget.hasCmpxchg16b();
18979 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18980 return needsCmpXchgNb(SI->getValueOperand()->getType());
18983 // Note: this turns large loads into lock cmpxchg8b/16b.
18984 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18985 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18986 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18987 return needsCmpXchgNb(PTy->getElementType());
18990 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18991 const X86Subtarget &Subtarget =
18992 getTargetMachine().getSubtarget<X86Subtarget>();
18993 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18994 const Type *MemType = AI->getType();
18996 // If the operand is too big, we must see if cmpxchg8/16b is available
18997 // and default to library calls otherwise.
18998 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18999 return needsCmpXchgNb(MemType);
19001 AtomicRMWInst::BinOp Op = AI->getOperation();
19004 llvm_unreachable("Unknown atomic operation");
19005 case AtomicRMWInst::Xchg:
19006 case AtomicRMWInst::Add:
19007 case AtomicRMWInst::Sub:
19008 // It's better to use xadd, xsub or xchg for these in all cases.
19010 case AtomicRMWInst::Or:
19011 case AtomicRMWInst::And:
19012 case AtomicRMWInst::Xor:
19013 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19014 // prefix to a normal instruction for these operations.
19015 return !AI->use_empty();
19016 case AtomicRMWInst::Nand:
19017 case AtomicRMWInst::Max:
19018 case AtomicRMWInst::Min:
19019 case AtomicRMWInst::UMax:
19020 case AtomicRMWInst::UMin:
19021 // These always require a non-trivial set of data operations on x86. We must
19022 // use a cmpxchg loop.
19027 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19028 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19029 // no-sse2). There isn't any reason to disable it if the target processor
19031 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19035 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19036 const X86Subtarget &Subtarget =
19037 getTargetMachine().getSubtarget<X86Subtarget>();
19038 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19039 const Type *MemType = AI->getType();
19040 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19041 // there is no benefit in turning such RMWs into loads, and it is actually
19042 // harmful as it introduces a mfence.
19043 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19046 auto Builder = IRBuilder<>(AI);
19047 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19048 auto SynchScope = AI->getSynchScope();
19049 // We must restrict the ordering to avoid generating loads with Release or
19050 // ReleaseAcquire orderings.
19051 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19052 auto Ptr = AI->getPointerOperand();
19054 // Before the load we need a fence. Here is an example lifted from
19055 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19058 // x.store(1, relaxed);
19059 // r1 = y.fetch_add(0, release);
19061 // y.fetch_add(42, acquire);
19062 // r2 = x.load(relaxed);
19063 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19064 // lowered to just a load without a fence. A mfence flushes the store buffer,
19065 // making the optimization clearly correct.
19066 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19067 // otherwise, we might be able to be more agressive on relaxed idempotent
19068 // rmw. In practice, they do not look useful, so we don't try to be
19069 // especially clever.
19070 if (SynchScope == SingleThread) {
19071 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19072 // the IR level, so we must wrap it in an intrinsic.
19074 } else if (hasMFENCE(Subtarget)) {
19075 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19076 Intrinsic::x86_sse2_mfence);
19077 Builder.CreateCall(MFence);
19079 // FIXME: it might make sense to use a locked operation here but on a
19080 // different cache-line to prevent cache-line bouncing. In practice it
19081 // is probably a small win, and x86 processors without mfence are rare
19082 // enough that we do not bother.
19086 // Finally we can emit the atomic load.
19087 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19088 AI->getType()->getPrimitiveSizeInBits());
19089 Loaded->setAtomic(Order, SynchScope);
19090 AI->replaceAllUsesWith(Loaded);
19091 AI->eraseFromParent();
19095 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19096 SelectionDAG &DAG) {
19098 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19099 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19100 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19101 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19103 // The only fence that needs an instruction is a sequentially-consistent
19104 // cross-thread fence.
19105 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19106 if (hasMFENCE(*Subtarget))
19107 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19109 SDValue Chain = Op.getOperand(0);
19110 SDValue Zero = DAG.getConstant(0, MVT::i32);
19112 DAG.getRegister(X86::ESP, MVT::i32), // Base
19113 DAG.getTargetConstant(1, MVT::i8), // Scale
19114 DAG.getRegister(0, MVT::i32), // Index
19115 DAG.getTargetConstant(0, MVT::i32), // Disp
19116 DAG.getRegister(0, MVT::i32), // Segment.
19120 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19121 return SDValue(Res, 0);
19124 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19125 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19128 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19129 SelectionDAG &DAG) {
19130 MVT T = Op.getSimpleValueType();
19134 switch(T.SimpleTy) {
19135 default: llvm_unreachable("Invalid value type!");
19136 case MVT::i8: Reg = X86::AL; size = 1; break;
19137 case MVT::i16: Reg = X86::AX; size = 2; break;
19138 case MVT::i32: Reg = X86::EAX; size = 4; break;
19140 assert(Subtarget->is64Bit() && "Node not type legal!");
19141 Reg = X86::RAX; size = 8;
19144 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19145 Op.getOperand(2), SDValue());
19146 SDValue Ops[] = { cpIn.getValue(0),
19149 DAG.getTargetConstant(size, MVT::i8),
19150 cpIn.getValue(1) };
19151 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19152 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19153 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19157 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19158 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19159 MVT::i32, cpOut.getValue(2));
19160 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19161 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19163 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19164 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19165 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19169 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19170 SelectionDAG &DAG) {
19171 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19172 MVT DstVT = Op.getSimpleValueType();
19174 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19175 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19176 if (DstVT != MVT::f64)
19177 // This conversion needs to be expanded.
19180 SDValue InVec = Op->getOperand(0);
19182 unsigned NumElts = SrcVT.getVectorNumElements();
19183 EVT SVT = SrcVT.getVectorElementType();
19185 // Widen the vector in input in the case of MVT::v2i32.
19186 // Example: from MVT::v2i32 to MVT::v4i32.
19187 SmallVector<SDValue, 16> Elts;
19188 for (unsigned i = 0, e = NumElts; i != e; ++i)
19189 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19190 DAG.getIntPtrConstant(i)));
19192 // Explicitly mark the extra elements as Undef.
19193 SDValue Undef = DAG.getUNDEF(SVT);
19194 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19195 Elts.push_back(Undef);
19197 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19198 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19199 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19200 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19201 DAG.getIntPtrConstant(0));
19204 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19205 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19206 assert((DstVT == MVT::i64 ||
19207 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19208 "Unexpected custom BITCAST");
19209 // i64 <=> MMX conversions are Legal.
19210 if (SrcVT==MVT::i64 && DstVT.isVector())
19212 if (DstVT==MVT::i64 && SrcVT.isVector())
19214 // MMX <=> MMX conversions are Legal.
19215 if (SrcVT.isVector() && DstVT.isVector())
19217 // All other conversions need to be expanded.
19221 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19222 SelectionDAG &DAG) {
19223 SDNode *Node = Op.getNode();
19226 Op = Op.getOperand(0);
19227 EVT VT = Op.getValueType();
19228 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19229 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19231 unsigned NumElts = VT.getVectorNumElements();
19232 EVT EltVT = VT.getVectorElementType();
19233 unsigned Len = EltVT.getSizeInBits();
19235 // This is the vectorized version of the "best" algorithm from
19236 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19237 // with a minor tweak to use a series of adds + shifts instead of vector
19238 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19240 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19241 // v8i32 => Always profitable
19243 // FIXME: There a couple of possible improvements:
19245 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19246 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19248 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19249 "CTPOP not implemented for this vector element type.");
19251 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19252 // extra legalization.
19253 bool NeedsBitcast = EltVT == MVT::i32;
19254 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19256 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19257 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19258 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19260 // v = v - ((v >> 1) & 0x55555555...)
19261 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19262 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19263 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19265 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19267 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19268 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19270 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19272 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19273 if (VT != And.getValueType())
19274 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19275 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19277 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19278 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19279 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19280 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19281 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19283 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19284 if (NeedsBitcast) {
19285 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19286 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19287 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19290 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19291 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19292 if (VT != AndRHS.getValueType()) {
19293 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19294 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19296 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19298 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19299 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19300 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19301 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19302 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19304 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19305 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19306 if (NeedsBitcast) {
19307 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19308 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19310 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19311 if (VT != And.getValueType())
19312 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19314 // The algorithm mentioned above uses:
19315 // v = (v * 0x01010101...) >> (Len - 8)
19317 // Change it to use vector adds + vector shifts which yield faster results on
19318 // Haswell than using vector integer multiplication.
19320 // For i32 elements:
19321 // v = v + (v >> 8)
19322 // v = v + (v >> 16)
19324 // For i64 elements:
19325 // v = v + (v >> 8)
19326 // v = v + (v >> 16)
19327 // v = v + (v >> 32)
19330 SmallVector<SDValue, 8> Csts;
19331 for (unsigned i = 8; i <= Len/2; i *= 2) {
19332 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19333 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19334 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19335 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19339 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19340 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19341 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19342 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19343 if (NeedsBitcast) {
19344 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19345 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19347 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19348 if (VT != And.getValueType())
19349 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19354 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19355 SDNode *Node = Op.getNode();
19357 EVT T = Node->getValueType(0);
19358 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19359 DAG.getConstant(0, T), Node->getOperand(2));
19360 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19361 cast<AtomicSDNode>(Node)->getMemoryVT(),
19362 Node->getOperand(0),
19363 Node->getOperand(1), negOp,
19364 cast<AtomicSDNode>(Node)->getMemOperand(),
19365 cast<AtomicSDNode>(Node)->getOrdering(),
19366 cast<AtomicSDNode>(Node)->getSynchScope());
19369 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19370 SDNode *Node = Op.getNode();
19372 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19374 // Convert seq_cst store -> xchg
19375 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19376 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19377 // (The only way to get a 16-byte store is cmpxchg16b)
19378 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19379 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19380 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19381 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19382 cast<AtomicSDNode>(Node)->getMemoryVT(),
19383 Node->getOperand(0),
19384 Node->getOperand(1), Node->getOperand(2),
19385 cast<AtomicSDNode>(Node)->getMemOperand(),
19386 cast<AtomicSDNode>(Node)->getOrdering(),
19387 cast<AtomicSDNode>(Node)->getSynchScope());
19388 return Swap.getValue(1);
19390 // Other atomic stores have a simple pattern.
19394 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19395 EVT VT = Op.getNode()->getSimpleValueType(0);
19397 // Let legalize expand this if it isn't a legal type yet.
19398 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19401 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19404 bool ExtraOp = false;
19405 switch (Op.getOpcode()) {
19406 default: llvm_unreachable("Invalid code");
19407 case ISD::ADDC: Opc = X86ISD::ADD; break;
19408 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19409 case ISD::SUBC: Opc = X86ISD::SUB; break;
19410 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19414 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19416 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19417 Op.getOperand(1), Op.getOperand(2));
19420 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19421 SelectionDAG &DAG) {
19422 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19424 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19425 // which returns the values as { float, float } (in XMM0) or
19426 // { double, double } (which is returned in XMM0, XMM1).
19428 SDValue Arg = Op.getOperand(0);
19429 EVT ArgVT = Arg.getValueType();
19430 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19432 TargetLowering::ArgListTy Args;
19433 TargetLowering::ArgListEntry Entry;
19437 Entry.isSExt = false;
19438 Entry.isZExt = false;
19439 Args.push_back(Entry);
19441 bool isF64 = ArgVT == MVT::f64;
19442 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19443 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19444 // the results are returned via SRet in memory.
19445 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19446 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19447 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19449 Type *RetTy = isF64
19450 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19451 : (Type*)VectorType::get(ArgTy, 4);
19453 TargetLowering::CallLoweringInfo CLI(DAG);
19454 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19455 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19457 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19460 // Returned in xmm0 and xmm1.
19461 return CallResult.first;
19463 // Returned in bits 0:31 and 32:64 xmm0.
19464 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19465 CallResult.first, DAG.getIntPtrConstant(0));
19466 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19467 CallResult.first, DAG.getIntPtrConstant(1));
19468 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19469 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19472 /// LowerOperation - Provide custom lowering hooks for some operations.
19474 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19475 switch (Op.getOpcode()) {
19476 default: llvm_unreachable("Should not custom lower this!");
19477 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19478 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19479 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19480 return LowerCMP_SWAP(Op, Subtarget, DAG);
19481 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19482 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19483 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19484 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19485 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19486 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19487 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19488 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19489 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19490 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19491 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19492 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19493 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19494 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19495 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19496 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19497 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19498 case ISD::SHL_PARTS:
19499 case ISD::SRA_PARTS:
19500 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19501 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19502 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19503 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19504 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19505 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19506 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19507 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19508 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19509 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19510 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19512 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19513 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19514 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19515 case ISD::SETCC: return LowerSETCC(Op, DAG);
19516 case ISD::SELECT: return LowerSELECT(Op, DAG);
19517 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19518 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19519 case ISD::VASTART: return LowerVASTART(Op, DAG);
19520 case ISD::VAARG: return LowerVAARG(Op, DAG);
19521 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19522 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19523 case ISD::INTRINSIC_VOID:
19524 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19525 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19526 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19527 case ISD::FRAME_TO_ARGS_OFFSET:
19528 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19529 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19530 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19531 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19532 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19533 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19534 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19535 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19536 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19537 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19538 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19539 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19540 case ISD::UMUL_LOHI:
19541 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19544 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19550 case ISD::UMULO: return LowerXALUO(Op, DAG);
19551 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19552 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19556 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19557 case ISD::ADD: return LowerADD(Op, DAG);
19558 case ISD::SUB: return LowerSUB(Op, DAG);
19559 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19563 /// ReplaceNodeResults - Replace a node with an illegal result type
19564 /// with a new node built out of custom code.
19565 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19566 SmallVectorImpl<SDValue>&Results,
19567 SelectionDAG &DAG) const {
19569 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19570 switch (N->getOpcode()) {
19572 llvm_unreachable("Do not know how to custom type legalize this operation!");
19573 case ISD::SIGN_EXTEND_INREG:
19578 // We don't want to expand or promote these.
19585 case ISD::UDIVREM: {
19586 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19587 Results.push_back(V);
19590 case ISD::FP_TO_SINT:
19591 case ISD::FP_TO_UINT: {
19592 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19594 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19597 std::pair<SDValue,SDValue> Vals =
19598 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19599 SDValue FIST = Vals.first, StackSlot = Vals.second;
19600 if (FIST.getNode()) {
19601 EVT VT = N->getValueType(0);
19602 // Return a load from the stack slot.
19603 if (StackSlot.getNode())
19604 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19605 MachinePointerInfo(),
19606 false, false, false, 0));
19608 Results.push_back(FIST);
19612 case ISD::UINT_TO_FP: {
19613 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19614 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19615 N->getValueType(0) != MVT::v2f32)
19617 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19619 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19621 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19622 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19623 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19624 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19625 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19626 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19629 case ISD::FP_ROUND: {
19630 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19632 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19633 Results.push_back(V);
19636 case ISD::INTRINSIC_W_CHAIN: {
19637 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19639 default : llvm_unreachable("Do not know how to custom type "
19640 "legalize this intrinsic operation!");
19641 case Intrinsic::x86_rdtsc:
19642 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19644 case Intrinsic::x86_rdtscp:
19645 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19647 case Intrinsic::x86_rdpmc:
19648 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19651 case ISD::READCYCLECOUNTER: {
19652 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19655 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19656 EVT T = N->getValueType(0);
19657 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19658 bool Regs64bit = T == MVT::i128;
19659 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19660 SDValue cpInL, cpInH;
19661 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19662 DAG.getConstant(0, HalfT));
19663 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19664 DAG.getConstant(1, HalfT));
19665 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19666 Regs64bit ? X86::RAX : X86::EAX,
19668 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19669 Regs64bit ? X86::RDX : X86::EDX,
19670 cpInH, cpInL.getValue(1));
19671 SDValue swapInL, swapInH;
19672 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19673 DAG.getConstant(0, HalfT));
19674 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19675 DAG.getConstant(1, HalfT));
19676 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19677 Regs64bit ? X86::RBX : X86::EBX,
19678 swapInL, cpInH.getValue(1));
19679 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19680 Regs64bit ? X86::RCX : X86::ECX,
19681 swapInH, swapInL.getValue(1));
19682 SDValue Ops[] = { swapInH.getValue(0),
19684 swapInH.getValue(1) };
19685 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19686 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19687 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19688 X86ISD::LCMPXCHG8_DAG;
19689 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19690 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19691 Regs64bit ? X86::RAX : X86::EAX,
19692 HalfT, Result.getValue(1));
19693 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19694 Regs64bit ? X86::RDX : X86::EDX,
19695 HalfT, cpOutL.getValue(2));
19696 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19698 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19699 MVT::i32, cpOutH.getValue(2));
19701 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19702 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19703 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19705 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19706 Results.push_back(Success);
19707 Results.push_back(EFLAGS.getValue(1));
19710 case ISD::ATOMIC_SWAP:
19711 case ISD::ATOMIC_LOAD_ADD:
19712 case ISD::ATOMIC_LOAD_SUB:
19713 case ISD::ATOMIC_LOAD_AND:
19714 case ISD::ATOMIC_LOAD_OR:
19715 case ISD::ATOMIC_LOAD_XOR:
19716 case ISD::ATOMIC_LOAD_NAND:
19717 case ISD::ATOMIC_LOAD_MIN:
19718 case ISD::ATOMIC_LOAD_MAX:
19719 case ISD::ATOMIC_LOAD_UMIN:
19720 case ISD::ATOMIC_LOAD_UMAX:
19721 case ISD::ATOMIC_LOAD: {
19722 // Delegate to generic TypeLegalization. Situations we can really handle
19723 // should have already been dealt with by AtomicExpandPass.cpp.
19726 case ISD::BITCAST: {
19727 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19728 EVT DstVT = N->getValueType(0);
19729 EVT SrcVT = N->getOperand(0)->getValueType(0);
19731 if (SrcVT != MVT::f64 ||
19732 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19735 unsigned NumElts = DstVT.getVectorNumElements();
19736 EVT SVT = DstVT.getVectorElementType();
19737 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19738 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19739 MVT::v2f64, N->getOperand(0));
19740 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19742 if (ExperimentalVectorWideningLegalization) {
19743 // If we are legalizing vectors by widening, we already have the desired
19744 // legal vector type, just return it.
19745 Results.push_back(ToVecInt);
19749 SmallVector<SDValue, 8> Elts;
19750 for (unsigned i = 0, e = NumElts; i != e; ++i)
19751 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19752 ToVecInt, DAG.getIntPtrConstant(i)));
19754 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19759 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19761 default: return nullptr;
19762 case X86ISD::BSF: return "X86ISD::BSF";
19763 case X86ISD::BSR: return "X86ISD::BSR";
19764 case X86ISD::SHLD: return "X86ISD::SHLD";
19765 case X86ISD::SHRD: return "X86ISD::SHRD";
19766 case X86ISD::FAND: return "X86ISD::FAND";
19767 case X86ISD::FANDN: return "X86ISD::FANDN";
19768 case X86ISD::FOR: return "X86ISD::FOR";
19769 case X86ISD::FXOR: return "X86ISD::FXOR";
19770 case X86ISD::FSRL: return "X86ISD::FSRL";
19771 case X86ISD::FILD: return "X86ISD::FILD";
19772 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19773 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19774 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19775 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19776 case X86ISD::FLD: return "X86ISD::FLD";
19777 case X86ISD::FST: return "X86ISD::FST";
19778 case X86ISD::CALL: return "X86ISD::CALL";
19779 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19780 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19781 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19782 case X86ISD::BT: return "X86ISD::BT";
19783 case X86ISD::CMP: return "X86ISD::CMP";
19784 case X86ISD::COMI: return "X86ISD::COMI";
19785 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19786 case X86ISD::CMPM: return "X86ISD::CMPM";
19787 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19788 case X86ISD::SETCC: return "X86ISD::SETCC";
19789 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19790 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19791 case X86ISD::CMOV: return "X86ISD::CMOV";
19792 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19793 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19794 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19795 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19796 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19797 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19798 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19799 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19800 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19801 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19802 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19803 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19804 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19805 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19806 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19807 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19808 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19809 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19810 case X86ISD::HADD: return "X86ISD::HADD";
19811 case X86ISD::HSUB: return "X86ISD::HSUB";
19812 case X86ISD::FHADD: return "X86ISD::FHADD";
19813 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19814 case X86ISD::UMAX: return "X86ISD::UMAX";
19815 case X86ISD::UMIN: return "X86ISD::UMIN";
19816 case X86ISD::SMAX: return "X86ISD::SMAX";
19817 case X86ISD::SMIN: return "X86ISD::SMIN";
19818 case X86ISD::FMAX: return "X86ISD::FMAX";
19819 case X86ISD::FMIN: return "X86ISD::FMIN";
19820 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19821 case X86ISD::FMINC: return "X86ISD::FMINC";
19822 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19823 case X86ISD::FRCP: return "X86ISD::FRCP";
19824 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19825 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19826 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19827 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19828 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19829 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19830 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19831 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19832 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19833 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19834 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19835 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19836 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19837 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19838 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19839 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19840 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19841 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19842 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19843 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19844 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19845 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19846 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19847 case X86ISD::VSHL: return "X86ISD::VSHL";
19848 case X86ISD::VSRL: return "X86ISD::VSRL";
19849 case X86ISD::VSRA: return "X86ISD::VSRA";
19850 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19851 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19852 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19853 case X86ISD::CMPP: return "X86ISD::CMPP";
19854 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19855 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19856 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19857 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19858 case X86ISD::ADD: return "X86ISD::ADD";
19859 case X86ISD::SUB: return "X86ISD::SUB";
19860 case X86ISD::ADC: return "X86ISD::ADC";
19861 case X86ISD::SBB: return "X86ISD::SBB";
19862 case X86ISD::SMUL: return "X86ISD::SMUL";
19863 case X86ISD::UMUL: return "X86ISD::UMUL";
19864 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19865 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19866 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19867 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19868 case X86ISD::INC: return "X86ISD::INC";
19869 case X86ISD::DEC: return "X86ISD::DEC";
19870 case X86ISD::OR: return "X86ISD::OR";
19871 case X86ISD::XOR: return "X86ISD::XOR";
19872 case X86ISD::AND: return "X86ISD::AND";
19873 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19874 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19875 case X86ISD::PTEST: return "X86ISD::PTEST";
19876 case X86ISD::TESTP: return "X86ISD::TESTP";
19877 case X86ISD::TESTM: return "X86ISD::TESTM";
19878 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19879 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19880 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19881 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19882 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19883 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19884 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19885 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19886 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19887 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19888 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19889 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19890 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19891 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19892 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19893 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19894 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19895 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19896 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19897 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19898 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19899 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19900 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19901 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19902 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19903 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19904 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19905 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19906 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19907 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19908 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19909 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19910 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19911 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19912 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19913 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19914 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19915 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19916 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19917 case X86ISD::SAHF: return "X86ISD::SAHF";
19918 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19919 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19920 case X86ISD::FMADD: return "X86ISD::FMADD";
19921 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19922 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19923 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19924 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19925 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19926 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19927 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19928 case X86ISD::XTEST: return "X86ISD::XTEST";
19929 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19930 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19934 // isLegalAddressingMode - Return true if the addressing mode represented
19935 // by AM is legal for this target, for a load/store of the specified type.
19936 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19938 // X86 supports extremely general addressing modes.
19939 CodeModel::Model M = getTargetMachine().getCodeModel();
19940 Reloc::Model R = getTargetMachine().getRelocationModel();
19942 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19943 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19948 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19950 // If a reference to this global requires an extra load, we can't fold it.
19951 if (isGlobalStubReference(GVFlags))
19954 // If BaseGV requires a register for the PIC base, we cannot also have a
19955 // BaseReg specified.
19956 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19959 // If lower 4G is not available, then we must use rip-relative addressing.
19960 if ((M != CodeModel::Small || R != Reloc::Static) &&
19961 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19965 switch (AM.Scale) {
19971 // These scales always work.
19976 // These scales are formed with basereg+scalereg. Only accept if there is
19981 default: // Other stuff never works.
19988 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19989 unsigned Bits = Ty->getScalarSizeInBits();
19991 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19992 // particularly cheaper than those without.
19996 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19997 // variable shifts just as cheap as scalar ones.
19998 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20001 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20002 // fully general vector.
20006 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20007 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20009 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20010 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20011 return NumBits1 > NumBits2;
20014 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20015 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20018 if (!isTypeLegal(EVT::getEVT(Ty1)))
20021 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20023 // Assuming the caller doesn't have a zeroext or signext return parameter,
20024 // truncation all the way down to i1 is valid.
20028 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20029 return isInt<32>(Imm);
20032 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20033 // Can also use sub to handle negated immediates.
20034 return isInt<32>(Imm);
20037 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20038 if (!VT1.isInteger() || !VT2.isInteger())
20040 unsigned NumBits1 = VT1.getSizeInBits();
20041 unsigned NumBits2 = VT2.getSizeInBits();
20042 return NumBits1 > NumBits2;
20045 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20046 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20047 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20050 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20051 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20052 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20055 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20056 EVT VT1 = Val.getValueType();
20057 if (isZExtFree(VT1, VT2))
20060 if (Val.getOpcode() != ISD::LOAD)
20063 if (!VT1.isSimple() || !VT1.isInteger() ||
20064 !VT2.isSimple() || !VT2.isInteger())
20067 switch (VT1.getSimpleVT().SimpleTy) {
20072 // X86 has 8, 16, and 32-bit zero-extending loads.
20080 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20081 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20084 VT = VT.getScalarType();
20086 if (!VT.isSimple())
20089 switch (VT.getSimpleVT().SimpleTy) {
20100 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20101 // i16 instructions are longer (0x66 prefix) and potentially slower.
20102 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20105 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20106 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20107 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20108 /// are assumed to be legal.
20110 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20112 if (!VT.isSimple())
20115 MVT SVT = VT.getSimpleVT();
20117 // Very little shuffling can be done for 64-bit vectors right now.
20118 if (VT.getSizeInBits() == 64)
20121 // If this is a single-input shuffle with no 128 bit lane crossings we can
20122 // lower it into pshufb.
20123 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20124 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20125 bool isLegal = true;
20126 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20127 if (M[I] >= (int)SVT.getVectorNumElements() ||
20128 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20137 // FIXME: blends, shifts.
20138 return (SVT.getVectorNumElements() == 2 ||
20139 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20140 isMOVLMask(M, SVT) ||
20141 isCommutedMOVLMask(M, SVT) ||
20142 isMOVHLPSMask(M, SVT) ||
20143 isSHUFPMask(M, SVT) ||
20144 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20145 isPSHUFDMask(M, SVT) ||
20146 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20147 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20148 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20149 isPALIGNRMask(M, SVT, Subtarget) ||
20150 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20151 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20152 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20153 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20154 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20155 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20159 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20161 if (!VT.isSimple())
20164 MVT SVT = VT.getSimpleVT();
20165 unsigned NumElts = SVT.getVectorNumElements();
20166 // FIXME: This collection of masks seems suspect.
20169 if (NumElts == 4 && SVT.is128BitVector()) {
20170 return (isMOVLMask(Mask, SVT) ||
20171 isCommutedMOVLMask(Mask, SVT, true) ||
20172 isSHUFPMask(Mask, SVT) ||
20173 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20174 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20175 Subtarget->hasInt256()));
20180 //===----------------------------------------------------------------------===//
20181 // X86 Scheduler Hooks
20182 //===----------------------------------------------------------------------===//
20184 /// Utility function to emit xbegin specifying the start of an RTM region.
20185 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20186 const TargetInstrInfo *TII) {
20187 DebugLoc DL = MI->getDebugLoc();
20189 const BasicBlock *BB = MBB->getBasicBlock();
20190 MachineFunction::iterator I = MBB;
20193 // For the v = xbegin(), we generate
20204 MachineBasicBlock *thisMBB = MBB;
20205 MachineFunction *MF = MBB->getParent();
20206 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20207 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20208 MF->insert(I, mainMBB);
20209 MF->insert(I, sinkMBB);
20211 // Transfer the remainder of BB and its successor edges to sinkMBB.
20212 sinkMBB->splice(sinkMBB->begin(), MBB,
20213 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20214 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20218 // # fallthrough to mainMBB
20219 // # abortion to sinkMBB
20220 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20221 thisMBB->addSuccessor(mainMBB);
20222 thisMBB->addSuccessor(sinkMBB);
20226 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20227 mainMBB->addSuccessor(sinkMBB);
20230 // EAX is live into the sinkMBB
20231 sinkMBB->addLiveIn(X86::EAX);
20232 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20233 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20236 MI->eraseFromParent();
20240 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20241 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20242 // in the .td file.
20243 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20244 const TargetInstrInfo *TII) {
20246 switch (MI->getOpcode()) {
20247 default: llvm_unreachable("illegal opcode!");
20248 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20249 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20250 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20251 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20252 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20253 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20254 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20255 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20258 DebugLoc dl = MI->getDebugLoc();
20259 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20261 unsigned NumArgs = MI->getNumOperands();
20262 for (unsigned i = 1; i < NumArgs; ++i) {
20263 MachineOperand &Op = MI->getOperand(i);
20264 if (!(Op.isReg() && Op.isImplicit()))
20265 MIB.addOperand(Op);
20267 if (MI->hasOneMemOperand())
20268 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20270 BuildMI(*BB, MI, dl,
20271 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20272 .addReg(X86::XMM0);
20274 MI->eraseFromParent();
20278 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20279 // defs in an instruction pattern
20280 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20281 const TargetInstrInfo *TII) {
20283 switch (MI->getOpcode()) {
20284 default: llvm_unreachable("illegal opcode!");
20285 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20286 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20287 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20288 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20289 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20290 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20291 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20292 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20295 DebugLoc dl = MI->getDebugLoc();
20296 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20298 unsigned NumArgs = MI->getNumOperands(); // remove the results
20299 for (unsigned i = 1; i < NumArgs; ++i) {
20300 MachineOperand &Op = MI->getOperand(i);
20301 if (!(Op.isReg() && Op.isImplicit()))
20302 MIB.addOperand(Op);
20304 if (MI->hasOneMemOperand())
20305 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20307 BuildMI(*BB, MI, dl,
20308 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20311 MI->eraseFromParent();
20315 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20316 const TargetInstrInfo *TII,
20317 const X86Subtarget* Subtarget) {
20318 DebugLoc dl = MI->getDebugLoc();
20320 // Address into RAX/EAX, other two args into ECX, EDX.
20321 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20322 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20323 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20324 for (int i = 0; i < X86::AddrNumOperands; ++i)
20325 MIB.addOperand(MI->getOperand(i));
20327 unsigned ValOps = X86::AddrNumOperands;
20328 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20329 .addReg(MI->getOperand(ValOps).getReg());
20330 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20331 .addReg(MI->getOperand(ValOps+1).getReg());
20333 // The instruction doesn't actually take any operands though.
20334 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20336 MI->eraseFromParent(); // The pseudo is gone now.
20340 MachineBasicBlock *
20341 X86TargetLowering::EmitVAARG64WithCustomInserter(
20343 MachineBasicBlock *MBB) const {
20344 // Emit va_arg instruction on X86-64.
20346 // Operands to this pseudo-instruction:
20347 // 0 ) Output : destination address (reg)
20348 // 1-5) Input : va_list address (addr, i64mem)
20349 // 6 ) ArgSize : Size (in bytes) of vararg type
20350 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20351 // 8 ) Align : Alignment of type
20352 // 9 ) EFLAGS (implicit-def)
20354 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20355 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20357 unsigned DestReg = MI->getOperand(0).getReg();
20358 MachineOperand &Base = MI->getOperand(1);
20359 MachineOperand &Scale = MI->getOperand(2);
20360 MachineOperand &Index = MI->getOperand(3);
20361 MachineOperand &Disp = MI->getOperand(4);
20362 MachineOperand &Segment = MI->getOperand(5);
20363 unsigned ArgSize = MI->getOperand(6).getImm();
20364 unsigned ArgMode = MI->getOperand(7).getImm();
20365 unsigned Align = MI->getOperand(8).getImm();
20367 // Memory Reference
20368 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20369 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20370 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20372 // Machine Information
20373 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20374 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20375 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20376 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20377 DebugLoc DL = MI->getDebugLoc();
20379 // struct va_list {
20382 // i64 overflow_area (address)
20383 // i64 reg_save_area (address)
20385 // sizeof(va_list) = 24
20386 // alignment(va_list) = 8
20388 unsigned TotalNumIntRegs = 6;
20389 unsigned TotalNumXMMRegs = 8;
20390 bool UseGPOffset = (ArgMode == 1);
20391 bool UseFPOffset = (ArgMode == 2);
20392 unsigned MaxOffset = TotalNumIntRegs * 8 +
20393 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20395 /* Align ArgSize to a multiple of 8 */
20396 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20397 bool NeedsAlign = (Align > 8);
20399 MachineBasicBlock *thisMBB = MBB;
20400 MachineBasicBlock *overflowMBB;
20401 MachineBasicBlock *offsetMBB;
20402 MachineBasicBlock *endMBB;
20404 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20405 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20406 unsigned OffsetReg = 0;
20408 if (!UseGPOffset && !UseFPOffset) {
20409 // If we only pull from the overflow region, we don't create a branch.
20410 // We don't need to alter control flow.
20411 OffsetDestReg = 0; // unused
20412 OverflowDestReg = DestReg;
20414 offsetMBB = nullptr;
20415 overflowMBB = thisMBB;
20418 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20419 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20420 // If not, pull from overflow_area. (branch to overflowMBB)
20425 // offsetMBB overflowMBB
20430 // Registers for the PHI in endMBB
20431 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20432 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20434 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20435 MachineFunction *MF = MBB->getParent();
20436 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20437 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20438 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20440 MachineFunction::iterator MBBIter = MBB;
20443 // Insert the new basic blocks
20444 MF->insert(MBBIter, offsetMBB);
20445 MF->insert(MBBIter, overflowMBB);
20446 MF->insert(MBBIter, endMBB);
20448 // Transfer the remainder of MBB and its successor edges to endMBB.
20449 endMBB->splice(endMBB->begin(), thisMBB,
20450 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20451 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20453 // Make offsetMBB and overflowMBB successors of thisMBB
20454 thisMBB->addSuccessor(offsetMBB);
20455 thisMBB->addSuccessor(overflowMBB);
20457 // endMBB is a successor of both offsetMBB and overflowMBB
20458 offsetMBB->addSuccessor(endMBB);
20459 overflowMBB->addSuccessor(endMBB);
20461 // Load the offset value into a register
20462 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20463 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20467 .addDisp(Disp, UseFPOffset ? 4 : 0)
20468 .addOperand(Segment)
20469 .setMemRefs(MMOBegin, MMOEnd);
20471 // Check if there is enough room left to pull this argument.
20472 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20474 .addImm(MaxOffset + 8 - ArgSizeA8);
20476 // Branch to "overflowMBB" if offset >= max
20477 // Fall through to "offsetMBB" otherwise
20478 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20479 .addMBB(overflowMBB);
20482 // In offsetMBB, emit code to use the reg_save_area.
20484 assert(OffsetReg != 0);
20486 // Read the reg_save_area address.
20487 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20488 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20493 .addOperand(Segment)
20494 .setMemRefs(MMOBegin, MMOEnd);
20496 // Zero-extend the offset
20497 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20498 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20501 .addImm(X86::sub_32bit);
20503 // Add the offset to the reg_save_area to get the final address.
20504 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20505 .addReg(OffsetReg64)
20506 .addReg(RegSaveReg);
20508 // Compute the offset for the next argument
20509 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20510 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20512 .addImm(UseFPOffset ? 16 : 8);
20514 // Store it back into the va_list.
20515 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20519 .addDisp(Disp, UseFPOffset ? 4 : 0)
20520 .addOperand(Segment)
20521 .addReg(NextOffsetReg)
20522 .setMemRefs(MMOBegin, MMOEnd);
20525 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20530 // Emit code to use overflow area
20533 // Load the overflow_area address into a register.
20534 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20535 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20540 .addOperand(Segment)
20541 .setMemRefs(MMOBegin, MMOEnd);
20543 // If we need to align it, do so. Otherwise, just copy the address
20544 // to OverflowDestReg.
20546 // Align the overflow address
20547 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20548 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20550 // aligned_addr = (addr + (align-1)) & ~(align-1)
20551 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20552 .addReg(OverflowAddrReg)
20555 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20557 .addImm(~(uint64_t)(Align-1));
20559 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20560 .addReg(OverflowAddrReg);
20563 // Compute the next overflow address after this argument.
20564 // (the overflow address should be kept 8-byte aligned)
20565 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20566 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20567 .addReg(OverflowDestReg)
20568 .addImm(ArgSizeA8);
20570 // Store the new overflow address.
20571 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20576 .addOperand(Segment)
20577 .addReg(NextAddrReg)
20578 .setMemRefs(MMOBegin, MMOEnd);
20580 // If we branched, emit the PHI to the front of endMBB.
20582 BuildMI(*endMBB, endMBB->begin(), DL,
20583 TII->get(X86::PHI), DestReg)
20584 .addReg(OffsetDestReg).addMBB(offsetMBB)
20585 .addReg(OverflowDestReg).addMBB(overflowMBB);
20588 // Erase the pseudo instruction
20589 MI->eraseFromParent();
20594 MachineBasicBlock *
20595 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20597 MachineBasicBlock *MBB) const {
20598 // Emit code to save XMM registers to the stack. The ABI says that the
20599 // number of registers to save is given in %al, so it's theoretically
20600 // possible to do an indirect jump trick to avoid saving all of them,
20601 // however this code takes a simpler approach and just executes all
20602 // of the stores if %al is non-zero. It's less code, and it's probably
20603 // easier on the hardware branch predictor, and stores aren't all that
20604 // expensive anyway.
20606 // Create the new basic blocks. One block contains all the XMM stores,
20607 // and one block is the final destination regardless of whether any
20608 // stores were performed.
20609 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20610 MachineFunction *F = MBB->getParent();
20611 MachineFunction::iterator MBBIter = MBB;
20613 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20614 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20615 F->insert(MBBIter, XMMSaveMBB);
20616 F->insert(MBBIter, EndMBB);
20618 // Transfer the remainder of MBB and its successor edges to EndMBB.
20619 EndMBB->splice(EndMBB->begin(), MBB,
20620 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20621 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20623 // The original block will now fall through to the XMM save block.
20624 MBB->addSuccessor(XMMSaveMBB);
20625 // The XMMSaveMBB will fall through to the end block.
20626 XMMSaveMBB->addSuccessor(EndMBB);
20628 // Now add the instructions.
20629 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20630 DebugLoc DL = MI->getDebugLoc();
20632 unsigned CountReg = MI->getOperand(0).getReg();
20633 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20634 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20636 if (!Subtarget->isTargetWin64()) {
20637 // If %al is 0, branch around the XMM save block.
20638 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20639 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20640 MBB->addSuccessor(EndMBB);
20643 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20644 // that was just emitted, but clearly shouldn't be "saved".
20645 assert((MI->getNumOperands() <= 3 ||
20646 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20647 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20648 && "Expected last argument to be EFLAGS");
20649 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20650 // In the XMM save block, save all the XMM argument registers.
20651 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20652 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20653 MachineMemOperand *MMO =
20654 F->getMachineMemOperand(
20655 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20656 MachineMemOperand::MOStore,
20657 /*Size=*/16, /*Align=*/16);
20658 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20659 .addFrameIndex(RegSaveFrameIndex)
20660 .addImm(/*Scale=*/1)
20661 .addReg(/*IndexReg=*/0)
20662 .addImm(/*Disp=*/Offset)
20663 .addReg(/*Segment=*/0)
20664 .addReg(MI->getOperand(i).getReg())
20665 .addMemOperand(MMO);
20668 MI->eraseFromParent(); // The pseudo instruction is gone now.
20673 // The EFLAGS operand of SelectItr might be missing a kill marker
20674 // because there were multiple uses of EFLAGS, and ISel didn't know
20675 // which to mark. Figure out whether SelectItr should have had a
20676 // kill marker, and set it if it should. Returns the correct kill
20678 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20679 MachineBasicBlock* BB,
20680 const TargetRegisterInfo* TRI) {
20681 // Scan forward through BB for a use/def of EFLAGS.
20682 MachineBasicBlock::iterator miI(std::next(SelectItr));
20683 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20684 const MachineInstr& mi = *miI;
20685 if (mi.readsRegister(X86::EFLAGS))
20687 if (mi.definesRegister(X86::EFLAGS))
20688 break; // Should have kill-flag - update below.
20691 // If we hit the end of the block, check whether EFLAGS is live into a
20693 if (miI == BB->end()) {
20694 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20695 sEnd = BB->succ_end();
20696 sItr != sEnd; ++sItr) {
20697 MachineBasicBlock* succ = *sItr;
20698 if (succ->isLiveIn(X86::EFLAGS))
20703 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20704 // out. SelectMI should have a kill flag on EFLAGS.
20705 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20709 MachineBasicBlock *
20710 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20711 MachineBasicBlock *BB) const {
20712 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20713 DebugLoc DL = MI->getDebugLoc();
20715 // To "insert" a SELECT_CC instruction, we actually have to insert the
20716 // diamond control-flow pattern. The incoming instruction knows the
20717 // destination vreg to set, the condition code register to branch on, the
20718 // true/false values to select between, and a branch opcode to use.
20719 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20720 MachineFunction::iterator It = BB;
20726 // cmpTY ccX, r1, r2
20728 // fallthrough --> copy0MBB
20729 MachineBasicBlock *thisMBB = BB;
20730 MachineFunction *F = BB->getParent();
20731 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20732 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20733 F->insert(It, copy0MBB);
20734 F->insert(It, sinkMBB);
20736 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20737 // live into the sink and copy blocks.
20738 const TargetRegisterInfo *TRI =
20739 BB->getParent()->getSubtarget().getRegisterInfo();
20740 if (!MI->killsRegister(X86::EFLAGS) &&
20741 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20742 copy0MBB->addLiveIn(X86::EFLAGS);
20743 sinkMBB->addLiveIn(X86::EFLAGS);
20746 // Transfer the remainder of BB and its successor edges to sinkMBB.
20747 sinkMBB->splice(sinkMBB->begin(), BB,
20748 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20749 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20751 // Add the true and fallthrough blocks as its successors.
20752 BB->addSuccessor(copy0MBB);
20753 BB->addSuccessor(sinkMBB);
20755 // Create the conditional branch instruction.
20757 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20758 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20761 // %FalseValue = ...
20762 // # fallthrough to sinkMBB
20763 copy0MBB->addSuccessor(sinkMBB);
20766 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20768 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20769 TII->get(X86::PHI), MI->getOperand(0).getReg())
20770 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20771 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20773 MI->eraseFromParent(); // The pseudo instruction is gone now.
20777 MachineBasicBlock *
20778 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20779 MachineBasicBlock *BB) const {
20780 MachineFunction *MF = BB->getParent();
20781 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20782 DebugLoc DL = MI->getDebugLoc();
20783 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20785 assert(MF->shouldSplitStack());
20787 const bool Is64Bit = Subtarget->is64Bit();
20788 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20790 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20791 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20794 // ... [Till the alloca]
20795 // If stacklet is not large enough, jump to mallocMBB
20798 // Allocate by subtracting from RSP
20799 // Jump to continueMBB
20802 // Allocate by call to runtime
20806 // [rest of original BB]
20809 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20810 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20811 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20813 MachineRegisterInfo &MRI = MF->getRegInfo();
20814 const TargetRegisterClass *AddrRegClass =
20815 getRegClassFor(getPointerTy());
20817 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20818 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20819 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20820 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20821 sizeVReg = MI->getOperand(1).getReg(),
20822 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20824 MachineFunction::iterator MBBIter = BB;
20827 MF->insert(MBBIter, bumpMBB);
20828 MF->insert(MBBIter, mallocMBB);
20829 MF->insert(MBBIter, continueMBB);
20831 continueMBB->splice(continueMBB->begin(), BB,
20832 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20833 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20835 // Add code to the main basic block to check if the stack limit has been hit,
20836 // and if so, jump to mallocMBB otherwise to bumpMBB.
20837 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20838 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20839 .addReg(tmpSPVReg).addReg(sizeVReg);
20840 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20841 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20842 .addReg(SPLimitVReg);
20843 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20845 // bumpMBB simply decreases the stack pointer, since we know the current
20846 // stacklet has enough space.
20847 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20848 .addReg(SPLimitVReg);
20849 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20850 .addReg(SPLimitVReg);
20851 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20853 // Calls into a routine in libgcc to allocate more space from the heap.
20854 const uint32_t *RegMask = MF->getTarget()
20855 .getSubtargetImpl()
20856 ->getRegisterInfo()
20857 ->getCallPreservedMask(CallingConv::C);
20859 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20861 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20862 .addExternalSymbol("__morestack_allocate_stack_space")
20863 .addRegMask(RegMask)
20864 .addReg(X86::RDI, RegState::Implicit)
20865 .addReg(X86::RAX, RegState::ImplicitDefine);
20866 } else if (Is64Bit) {
20867 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20869 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20870 .addExternalSymbol("__morestack_allocate_stack_space")
20871 .addRegMask(RegMask)
20872 .addReg(X86::EDI, RegState::Implicit)
20873 .addReg(X86::EAX, RegState::ImplicitDefine);
20875 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20877 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20878 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20879 .addExternalSymbol("__morestack_allocate_stack_space")
20880 .addRegMask(RegMask)
20881 .addReg(X86::EAX, RegState::ImplicitDefine);
20885 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20888 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20889 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20890 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20892 // Set up the CFG correctly.
20893 BB->addSuccessor(bumpMBB);
20894 BB->addSuccessor(mallocMBB);
20895 mallocMBB->addSuccessor(continueMBB);
20896 bumpMBB->addSuccessor(continueMBB);
20898 // Take care of the PHI nodes.
20899 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20900 MI->getOperand(0).getReg())
20901 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20902 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20904 // Delete the original pseudo instruction.
20905 MI->eraseFromParent();
20908 return continueMBB;
20911 MachineBasicBlock *
20912 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20913 MachineBasicBlock *BB) const {
20914 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20915 DebugLoc DL = MI->getDebugLoc();
20917 assert(!Subtarget->isTargetMachO());
20919 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20920 // non-trivial part is impdef of ESP.
20922 if (Subtarget->isTargetWin64()) {
20923 if (Subtarget->isTargetCygMing()) {
20924 // ___chkstk(Mingw64):
20925 // Clobbers R10, R11, RAX and EFLAGS.
20927 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20928 .addExternalSymbol("___chkstk")
20929 .addReg(X86::RAX, RegState::Implicit)
20930 .addReg(X86::RSP, RegState::Implicit)
20931 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20932 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20933 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20935 // __chkstk(MSVCRT): does not update stack pointer.
20936 // Clobbers R10, R11 and EFLAGS.
20937 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20938 .addExternalSymbol("__chkstk")
20939 .addReg(X86::RAX, RegState::Implicit)
20940 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20941 // RAX has the offset to be subtracted from RSP.
20942 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20947 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20948 Subtarget->isTargetWindowsItanium())
20952 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20953 .addExternalSymbol(StackProbeSymbol)
20954 .addReg(X86::EAX, RegState::Implicit)
20955 .addReg(X86::ESP, RegState::Implicit)
20956 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20957 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20958 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20961 MI->eraseFromParent(); // The pseudo instruction is gone now.
20965 MachineBasicBlock *
20966 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20967 MachineBasicBlock *BB) const {
20968 // This is pretty easy. We're taking the value that we received from
20969 // our load from the relocation, sticking it in either RDI (x86-64)
20970 // or EAX and doing an indirect call. The return value will then
20971 // be in the normal return register.
20972 MachineFunction *F = BB->getParent();
20973 const X86InstrInfo *TII =
20974 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20975 DebugLoc DL = MI->getDebugLoc();
20977 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20978 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20980 // Get a register mask for the lowered call.
20981 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20982 // proper register mask.
20983 const uint32_t *RegMask = F->getTarget()
20984 .getSubtargetImpl()
20985 ->getRegisterInfo()
20986 ->getCallPreservedMask(CallingConv::C);
20987 if (Subtarget->is64Bit()) {
20988 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20989 TII->get(X86::MOV64rm), X86::RDI)
20991 .addImm(0).addReg(0)
20992 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20993 MI->getOperand(3).getTargetFlags())
20995 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20996 addDirectMem(MIB, X86::RDI);
20997 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20998 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20999 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21000 TII->get(X86::MOV32rm), X86::EAX)
21002 .addImm(0).addReg(0)
21003 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21004 MI->getOperand(3).getTargetFlags())
21006 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21007 addDirectMem(MIB, X86::EAX);
21008 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21010 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21011 TII->get(X86::MOV32rm), X86::EAX)
21012 .addReg(TII->getGlobalBaseReg(F))
21013 .addImm(0).addReg(0)
21014 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21015 MI->getOperand(3).getTargetFlags())
21017 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21018 addDirectMem(MIB, X86::EAX);
21019 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21022 MI->eraseFromParent(); // The pseudo instruction is gone now.
21026 MachineBasicBlock *
21027 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21028 MachineBasicBlock *MBB) const {
21029 DebugLoc DL = MI->getDebugLoc();
21030 MachineFunction *MF = MBB->getParent();
21031 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21032 MachineRegisterInfo &MRI = MF->getRegInfo();
21034 const BasicBlock *BB = MBB->getBasicBlock();
21035 MachineFunction::iterator I = MBB;
21038 // Memory Reference
21039 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21040 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21043 unsigned MemOpndSlot = 0;
21045 unsigned CurOp = 0;
21047 DstReg = MI->getOperand(CurOp++).getReg();
21048 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21049 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21050 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21051 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21053 MemOpndSlot = CurOp;
21055 MVT PVT = getPointerTy();
21056 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21057 "Invalid Pointer Size!");
21059 // For v = setjmp(buf), we generate
21062 // buf[LabelOffset] = restoreMBB
21063 // SjLjSetup restoreMBB
21069 // v = phi(main, restore)
21072 // if base pointer being used, load it from frame
21075 MachineBasicBlock *thisMBB = MBB;
21076 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21077 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21078 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21079 MF->insert(I, mainMBB);
21080 MF->insert(I, sinkMBB);
21081 MF->push_back(restoreMBB);
21083 MachineInstrBuilder MIB;
21085 // Transfer the remainder of BB and its successor edges to sinkMBB.
21086 sinkMBB->splice(sinkMBB->begin(), MBB,
21087 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21088 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21091 unsigned PtrStoreOpc = 0;
21092 unsigned LabelReg = 0;
21093 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21094 Reloc::Model RM = MF->getTarget().getRelocationModel();
21095 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21096 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21098 // Prepare IP either in reg or imm.
21099 if (!UseImmLabel) {
21100 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21101 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21102 LabelReg = MRI.createVirtualRegister(PtrRC);
21103 if (Subtarget->is64Bit()) {
21104 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21108 .addMBB(restoreMBB)
21111 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21112 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21113 .addReg(XII->getGlobalBaseReg(MF))
21116 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21120 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21122 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21123 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21124 if (i == X86::AddrDisp)
21125 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21127 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21130 MIB.addReg(LabelReg);
21132 MIB.addMBB(restoreMBB);
21133 MIB.setMemRefs(MMOBegin, MMOEnd);
21135 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21136 .addMBB(restoreMBB);
21138 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21139 MF->getSubtarget().getRegisterInfo());
21140 MIB.addRegMask(RegInfo->getNoPreservedMask());
21141 thisMBB->addSuccessor(mainMBB);
21142 thisMBB->addSuccessor(restoreMBB);
21146 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21147 mainMBB->addSuccessor(sinkMBB);
21150 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21151 TII->get(X86::PHI), DstReg)
21152 .addReg(mainDstReg).addMBB(mainMBB)
21153 .addReg(restoreDstReg).addMBB(restoreMBB);
21156 if (RegInfo->hasBasePointer(*MF)) {
21157 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21158 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21159 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21160 X86FI->setRestoreBasePointer(MF);
21161 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21162 unsigned BasePtr = RegInfo->getBaseRegister();
21163 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21164 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21165 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21166 .setMIFlag(MachineInstr::FrameSetup);
21168 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21169 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21170 restoreMBB->addSuccessor(sinkMBB);
21172 MI->eraseFromParent();
21176 MachineBasicBlock *
21177 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21178 MachineBasicBlock *MBB) const {
21179 DebugLoc DL = MI->getDebugLoc();
21180 MachineFunction *MF = MBB->getParent();
21181 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21182 MachineRegisterInfo &MRI = MF->getRegInfo();
21184 // Memory Reference
21185 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21186 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21188 MVT PVT = getPointerTy();
21189 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21190 "Invalid Pointer Size!");
21192 const TargetRegisterClass *RC =
21193 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21194 unsigned Tmp = MRI.createVirtualRegister(RC);
21195 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21196 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21197 MF->getSubtarget().getRegisterInfo());
21198 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21199 unsigned SP = RegInfo->getStackRegister();
21201 MachineInstrBuilder MIB;
21203 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21204 const int64_t SPOffset = 2 * PVT.getStoreSize();
21206 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21207 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21210 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21211 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21212 MIB.addOperand(MI->getOperand(i));
21213 MIB.setMemRefs(MMOBegin, MMOEnd);
21215 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21216 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21217 if (i == X86::AddrDisp)
21218 MIB.addDisp(MI->getOperand(i), LabelOffset);
21220 MIB.addOperand(MI->getOperand(i));
21222 MIB.setMemRefs(MMOBegin, MMOEnd);
21224 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21225 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21226 if (i == X86::AddrDisp)
21227 MIB.addDisp(MI->getOperand(i), SPOffset);
21229 MIB.addOperand(MI->getOperand(i));
21231 MIB.setMemRefs(MMOBegin, MMOEnd);
21233 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21235 MI->eraseFromParent();
21239 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21240 // accumulator loops. Writing back to the accumulator allows the coalescer
21241 // to remove extra copies in the loop.
21242 MachineBasicBlock *
21243 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21244 MachineBasicBlock *MBB) const {
21245 MachineOperand &AddendOp = MI->getOperand(3);
21247 // Bail out early if the addend isn't a register - we can't switch these.
21248 if (!AddendOp.isReg())
21251 MachineFunction &MF = *MBB->getParent();
21252 MachineRegisterInfo &MRI = MF.getRegInfo();
21254 // Check whether the addend is defined by a PHI:
21255 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21256 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21257 if (!AddendDef.isPHI())
21260 // Look for the following pattern:
21262 // %addend = phi [%entry, 0], [%loop, %result]
21264 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21268 // %addend = phi [%entry, 0], [%loop, %result]
21270 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21272 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21273 assert(AddendDef.getOperand(i).isReg());
21274 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21275 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21276 if (&PHISrcInst == MI) {
21277 // Found a matching instruction.
21278 unsigned NewFMAOpc = 0;
21279 switch (MI->getOpcode()) {
21280 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21281 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21282 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21283 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21284 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21285 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21286 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21287 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21288 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21289 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21290 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21291 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21292 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21293 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21294 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21295 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21296 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21297 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21298 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21299 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21301 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21302 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21303 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21304 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21305 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21306 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21307 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21308 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21309 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21310 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21311 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21312 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21313 default: llvm_unreachable("Unrecognized FMA variant.");
21316 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21317 MachineInstrBuilder MIB =
21318 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21319 .addOperand(MI->getOperand(0))
21320 .addOperand(MI->getOperand(3))
21321 .addOperand(MI->getOperand(2))
21322 .addOperand(MI->getOperand(1));
21323 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21324 MI->eraseFromParent();
21331 MachineBasicBlock *
21332 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21333 MachineBasicBlock *BB) const {
21334 switch (MI->getOpcode()) {
21335 default: llvm_unreachable("Unexpected instr type to insert");
21336 case X86::TAILJMPd64:
21337 case X86::TAILJMPr64:
21338 case X86::TAILJMPm64:
21339 llvm_unreachable("TAILJMP64 would not be touched here.");
21340 case X86::TCRETURNdi64:
21341 case X86::TCRETURNri64:
21342 case X86::TCRETURNmi64:
21344 case X86::WIN_ALLOCA:
21345 return EmitLoweredWinAlloca(MI, BB);
21346 case X86::SEG_ALLOCA_32:
21347 case X86::SEG_ALLOCA_64:
21348 return EmitLoweredSegAlloca(MI, BB);
21349 case X86::TLSCall_32:
21350 case X86::TLSCall_64:
21351 return EmitLoweredTLSCall(MI, BB);
21352 case X86::CMOV_GR8:
21353 case X86::CMOV_FR32:
21354 case X86::CMOV_FR64:
21355 case X86::CMOV_V4F32:
21356 case X86::CMOV_V2F64:
21357 case X86::CMOV_V2I64:
21358 case X86::CMOV_V8F32:
21359 case X86::CMOV_V4F64:
21360 case X86::CMOV_V4I64:
21361 case X86::CMOV_V16F32:
21362 case X86::CMOV_V8F64:
21363 case X86::CMOV_V8I64:
21364 case X86::CMOV_GR16:
21365 case X86::CMOV_GR32:
21366 case X86::CMOV_RFP32:
21367 case X86::CMOV_RFP64:
21368 case X86::CMOV_RFP80:
21369 return EmitLoweredSelect(MI, BB);
21371 case X86::FP32_TO_INT16_IN_MEM:
21372 case X86::FP32_TO_INT32_IN_MEM:
21373 case X86::FP32_TO_INT64_IN_MEM:
21374 case X86::FP64_TO_INT16_IN_MEM:
21375 case X86::FP64_TO_INT32_IN_MEM:
21376 case X86::FP64_TO_INT64_IN_MEM:
21377 case X86::FP80_TO_INT16_IN_MEM:
21378 case X86::FP80_TO_INT32_IN_MEM:
21379 case X86::FP80_TO_INT64_IN_MEM: {
21380 MachineFunction *F = BB->getParent();
21381 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21382 DebugLoc DL = MI->getDebugLoc();
21384 // Change the floating point control register to use "round towards zero"
21385 // mode when truncating to an integer value.
21386 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21387 addFrameReference(BuildMI(*BB, MI, DL,
21388 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21390 // Load the old value of the high byte of the control word...
21392 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21393 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21396 // Set the high part to be round to zero...
21397 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21400 // Reload the modified control word now...
21401 addFrameReference(BuildMI(*BB, MI, DL,
21402 TII->get(X86::FLDCW16m)), CWFrameIdx);
21404 // Restore the memory image of control word to original value
21405 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21408 // Get the X86 opcode to use.
21410 switch (MI->getOpcode()) {
21411 default: llvm_unreachable("illegal opcode!");
21412 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21413 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21414 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21415 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21416 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21417 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21418 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21419 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21420 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21424 MachineOperand &Op = MI->getOperand(0);
21426 AM.BaseType = X86AddressMode::RegBase;
21427 AM.Base.Reg = Op.getReg();
21429 AM.BaseType = X86AddressMode::FrameIndexBase;
21430 AM.Base.FrameIndex = Op.getIndex();
21432 Op = MI->getOperand(1);
21434 AM.Scale = Op.getImm();
21435 Op = MI->getOperand(2);
21437 AM.IndexReg = Op.getImm();
21438 Op = MI->getOperand(3);
21439 if (Op.isGlobal()) {
21440 AM.GV = Op.getGlobal();
21442 AM.Disp = Op.getImm();
21444 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21445 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21447 // Reload the original control word now.
21448 addFrameReference(BuildMI(*BB, MI, DL,
21449 TII->get(X86::FLDCW16m)), CWFrameIdx);
21451 MI->eraseFromParent(); // The pseudo instruction is gone now.
21454 // String/text processing lowering.
21455 case X86::PCMPISTRM128REG:
21456 case X86::VPCMPISTRM128REG:
21457 case X86::PCMPISTRM128MEM:
21458 case X86::VPCMPISTRM128MEM:
21459 case X86::PCMPESTRM128REG:
21460 case X86::VPCMPESTRM128REG:
21461 case X86::PCMPESTRM128MEM:
21462 case X86::VPCMPESTRM128MEM:
21463 assert(Subtarget->hasSSE42() &&
21464 "Target must have SSE4.2 or AVX features enabled");
21465 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21467 // String/text processing lowering.
21468 case X86::PCMPISTRIREG:
21469 case X86::VPCMPISTRIREG:
21470 case X86::PCMPISTRIMEM:
21471 case X86::VPCMPISTRIMEM:
21472 case X86::PCMPESTRIREG:
21473 case X86::VPCMPESTRIREG:
21474 case X86::PCMPESTRIMEM:
21475 case X86::VPCMPESTRIMEM:
21476 assert(Subtarget->hasSSE42() &&
21477 "Target must have SSE4.2 or AVX features enabled");
21478 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21480 // Thread synchronization.
21482 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21487 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21489 case X86::VASTART_SAVE_XMM_REGS:
21490 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21492 case X86::VAARG_64:
21493 return EmitVAARG64WithCustomInserter(MI, BB);
21495 case X86::EH_SjLj_SetJmp32:
21496 case X86::EH_SjLj_SetJmp64:
21497 return emitEHSjLjSetJmp(MI, BB);
21499 case X86::EH_SjLj_LongJmp32:
21500 case X86::EH_SjLj_LongJmp64:
21501 return emitEHSjLjLongJmp(MI, BB);
21503 case TargetOpcode::STATEPOINT:
21504 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21505 // this point in the process. We diverge later.
21506 return emitPatchPoint(MI, BB);
21508 case TargetOpcode::STACKMAP:
21509 case TargetOpcode::PATCHPOINT:
21510 return emitPatchPoint(MI, BB);
21512 case X86::VFMADDPDr213r:
21513 case X86::VFMADDPSr213r:
21514 case X86::VFMADDSDr213r:
21515 case X86::VFMADDSSr213r:
21516 case X86::VFMSUBPDr213r:
21517 case X86::VFMSUBPSr213r:
21518 case X86::VFMSUBSDr213r:
21519 case X86::VFMSUBSSr213r:
21520 case X86::VFNMADDPDr213r:
21521 case X86::VFNMADDPSr213r:
21522 case X86::VFNMADDSDr213r:
21523 case X86::VFNMADDSSr213r:
21524 case X86::VFNMSUBPDr213r:
21525 case X86::VFNMSUBPSr213r:
21526 case X86::VFNMSUBSDr213r:
21527 case X86::VFNMSUBSSr213r:
21528 case X86::VFMADDSUBPDr213r:
21529 case X86::VFMADDSUBPSr213r:
21530 case X86::VFMSUBADDPDr213r:
21531 case X86::VFMSUBADDPSr213r:
21532 case X86::VFMADDPDr213rY:
21533 case X86::VFMADDPSr213rY:
21534 case X86::VFMSUBPDr213rY:
21535 case X86::VFMSUBPSr213rY:
21536 case X86::VFNMADDPDr213rY:
21537 case X86::VFNMADDPSr213rY:
21538 case X86::VFNMSUBPDr213rY:
21539 case X86::VFNMSUBPSr213rY:
21540 case X86::VFMADDSUBPDr213rY:
21541 case X86::VFMADDSUBPSr213rY:
21542 case X86::VFMSUBADDPDr213rY:
21543 case X86::VFMSUBADDPSr213rY:
21544 return emitFMA3Instr(MI, BB);
21548 //===----------------------------------------------------------------------===//
21549 // X86 Optimization Hooks
21550 //===----------------------------------------------------------------------===//
21552 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21555 const SelectionDAG &DAG,
21556 unsigned Depth) const {
21557 unsigned BitWidth = KnownZero.getBitWidth();
21558 unsigned Opc = Op.getOpcode();
21559 assert((Opc >= ISD::BUILTIN_OP_END ||
21560 Opc == ISD::INTRINSIC_WO_CHAIN ||
21561 Opc == ISD::INTRINSIC_W_CHAIN ||
21562 Opc == ISD::INTRINSIC_VOID) &&
21563 "Should use MaskedValueIsZero if you don't know whether Op"
21564 " is a target node!");
21566 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21580 // These nodes' second result is a boolean.
21581 if (Op.getResNo() == 0)
21584 case X86ISD::SETCC:
21585 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21587 case ISD::INTRINSIC_WO_CHAIN: {
21588 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21589 unsigned NumLoBits = 0;
21592 case Intrinsic::x86_sse_movmsk_ps:
21593 case Intrinsic::x86_avx_movmsk_ps_256:
21594 case Intrinsic::x86_sse2_movmsk_pd:
21595 case Intrinsic::x86_avx_movmsk_pd_256:
21596 case Intrinsic::x86_mmx_pmovmskb:
21597 case Intrinsic::x86_sse2_pmovmskb_128:
21598 case Intrinsic::x86_avx2_pmovmskb: {
21599 // High bits of movmskp{s|d}, pmovmskb are known zero.
21601 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21602 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21603 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21604 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21605 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21606 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21607 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21608 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21610 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21619 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21621 const SelectionDAG &,
21622 unsigned Depth) const {
21623 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21624 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21625 return Op.getValueType().getScalarType().getSizeInBits();
21631 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21632 /// node is a GlobalAddress + offset.
21633 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21634 const GlobalValue* &GA,
21635 int64_t &Offset) const {
21636 if (N->getOpcode() == X86ISD::Wrapper) {
21637 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21638 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21639 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21643 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21646 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21647 /// same as extracting the high 128-bit part of 256-bit vector and then
21648 /// inserting the result into the low part of a new 256-bit vector
21649 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21650 EVT VT = SVOp->getValueType(0);
21651 unsigned NumElems = VT.getVectorNumElements();
21653 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21654 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21655 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21656 SVOp->getMaskElt(j) >= 0)
21662 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21663 /// same as extracting the low 128-bit part of 256-bit vector and then
21664 /// inserting the result into the high part of a new 256-bit vector
21665 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21666 EVT VT = SVOp->getValueType(0);
21667 unsigned NumElems = VT.getVectorNumElements();
21669 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21670 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21671 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21672 SVOp->getMaskElt(j) >= 0)
21678 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21679 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21680 TargetLowering::DAGCombinerInfo &DCI,
21681 const X86Subtarget* Subtarget) {
21683 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21684 SDValue V1 = SVOp->getOperand(0);
21685 SDValue V2 = SVOp->getOperand(1);
21686 EVT VT = SVOp->getValueType(0);
21687 unsigned NumElems = VT.getVectorNumElements();
21689 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21690 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21694 // V UNDEF BUILD_VECTOR UNDEF
21696 // CONCAT_VECTOR CONCAT_VECTOR
21699 // RESULT: V + zero extended
21701 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21702 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21703 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21706 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21709 // To match the shuffle mask, the first half of the mask should
21710 // be exactly the first vector, and all the rest a splat with the
21711 // first element of the second one.
21712 for (unsigned i = 0; i != NumElems/2; ++i)
21713 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21714 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21717 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21718 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21719 if (Ld->hasNUsesOfValue(1, 0)) {
21720 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21721 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21723 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21725 Ld->getPointerInfo(),
21726 Ld->getAlignment(),
21727 false/*isVolatile*/, true/*ReadMem*/,
21728 false/*WriteMem*/);
21730 // Make sure the newly-created LOAD is in the same position as Ld in
21731 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21732 // and update uses of Ld's output chain to use the TokenFactor.
21733 if (Ld->hasAnyUseOfValue(1)) {
21734 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21735 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21736 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21737 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21738 SDValue(ResNode.getNode(), 1));
21741 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21745 // Emit a zeroed vector and insert the desired subvector on its
21747 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21748 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21749 return DCI.CombineTo(N, InsV);
21752 //===--------------------------------------------------------------------===//
21753 // Combine some shuffles into subvector extracts and inserts:
21756 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21757 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21758 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21759 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21760 return DCI.CombineTo(N, InsV);
21763 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21764 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21765 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21766 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21767 return DCI.CombineTo(N, InsV);
21773 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21776 /// This is the leaf of the recursive combinine below. When we have found some
21777 /// chain of single-use x86 shuffle instructions and accumulated the combined
21778 /// shuffle mask represented by them, this will try to pattern match that mask
21779 /// into either a single instruction if there is a special purpose instruction
21780 /// for this operation, or into a PSHUFB instruction which is a fully general
21781 /// instruction but should only be used to replace chains over a certain depth.
21782 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21783 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21784 TargetLowering::DAGCombinerInfo &DCI,
21785 const X86Subtarget *Subtarget) {
21786 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21788 // Find the operand that enters the chain. Note that multiple uses are OK
21789 // here, we're not going to remove the operand we find.
21790 SDValue Input = Op.getOperand(0);
21791 while (Input.getOpcode() == ISD::BITCAST)
21792 Input = Input.getOperand(0);
21794 MVT VT = Input.getSimpleValueType();
21795 MVT RootVT = Root.getSimpleValueType();
21798 // Just remove no-op shuffle masks.
21799 if (Mask.size() == 1) {
21800 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21805 // Use the float domain if the operand type is a floating point type.
21806 bool FloatDomain = VT.isFloatingPoint();
21808 // For floating point shuffles, we don't have free copies in the shuffle
21809 // instructions or the ability to load as part of the instruction, so
21810 // canonicalize their shuffles to UNPCK or MOV variants.
21812 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21813 // vectors because it can have a load folded into it that UNPCK cannot. This
21814 // doesn't preclude something switching to the shorter encoding post-RA.
21816 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21817 bool Lo = Mask.equals(0, 0);
21820 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21821 // is no slower than UNPCKLPD but has the option to fold the input operand
21822 // into even an unaligned memory load.
21823 if (Lo && Subtarget->hasSSE3()) {
21824 Shuffle = X86ISD::MOVDDUP;
21825 ShuffleVT = MVT::v2f64;
21827 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21828 // than the UNPCK variants.
21829 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21830 ShuffleVT = MVT::v4f32;
21832 if (Depth == 1 && Root->getOpcode() == Shuffle)
21833 return false; // Nothing to do!
21834 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21835 DCI.AddToWorklist(Op.getNode());
21836 if (Shuffle == X86ISD::MOVDDUP)
21837 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21839 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21840 DCI.AddToWorklist(Op.getNode());
21841 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21845 if (Subtarget->hasSSE3() &&
21846 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21847 bool Lo = Mask.equals(0, 0, 2, 2);
21848 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21849 MVT ShuffleVT = MVT::v4f32;
21850 if (Depth == 1 && Root->getOpcode() == Shuffle)
21851 return false; // Nothing to do!
21852 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21853 DCI.AddToWorklist(Op.getNode());
21854 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21855 DCI.AddToWorklist(Op.getNode());
21856 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21860 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21861 bool Lo = Mask.equals(0, 0, 1, 1);
21862 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21863 MVT ShuffleVT = MVT::v4f32;
21864 if (Depth == 1 && Root->getOpcode() == Shuffle)
21865 return false; // Nothing to do!
21866 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21867 DCI.AddToWorklist(Op.getNode());
21868 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21869 DCI.AddToWorklist(Op.getNode());
21870 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21876 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21877 // variants as none of these have single-instruction variants that are
21878 // superior to the UNPCK formulation.
21879 if (!FloatDomain &&
21880 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21881 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21882 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21883 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21885 bool Lo = Mask[0] == 0;
21886 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21887 if (Depth == 1 && Root->getOpcode() == Shuffle)
21888 return false; // Nothing to do!
21890 switch (Mask.size()) {
21892 ShuffleVT = MVT::v8i16;
21895 ShuffleVT = MVT::v16i8;
21898 llvm_unreachable("Impossible mask size!");
21900 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21901 DCI.AddToWorklist(Op.getNode());
21902 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21903 DCI.AddToWorklist(Op.getNode());
21904 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21909 // Don't try to re-form single instruction chains under any circumstances now
21910 // that we've done encoding canonicalization for them.
21914 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21915 // can replace them with a single PSHUFB instruction profitably. Intel's
21916 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21917 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21918 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21919 SmallVector<SDValue, 16> PSHUFBMask;
21920 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21921 int Ratio = 16 / Mask.size();
21922 for (unsigned i = 0; i < 16; ++i) {
21923 if (Mask[i / Ratio] == SM_SentinelUndef) {
21924 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21927 int M = Mask[i / Ratio] != SM_SentinelZero
21928 ? Ratio * Mask[i / Ratio] + i % Ratio
21930 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21932 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21933 DCI.AddToWorklist(Op.getNode());
21934 SDValue PSHUFBMaskOp =
21935 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21936 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21937 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21938 DCI.AddToWorklist(Op.getNode());
21939 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21944 // Failed to find any combines.
21948 /// \brief Fully generic combining of x86 shuffle instructions.
21950 /// This should be the last combine run over the x86 shuffle instructions. Once
21951 /// they have been fully optimized, this will recursively consider all chains
21952 /// of single-use shuffle instructions, build a generic model of the cumulative
21953 /// shuffle operation, and check for simpler instructions which implement this
21954 /// operation. We use this primarily for two purposes:
21956 /// 1) Collapse generic shuffles to specialized single instructions when
21957 /// equivalent. In most cases, this is just an encoding size win, but
21958 /// sometimes we will collapse multiple generic shuffles into a single
21959 /// special-purpose shuffle.
21960 /// 2) Look for sequences of shuffle instructions with 3 or more total
21961 /// instructions, and replace them with the slightly more expensive SSSE3
21962 /// PSHUFB instruction if available. We do this as the last combining step
21963 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21964 /// a suitable short sequence of other instructions. The PHUFB will either
21965 /// use a register or have to read from memory and so is slightly (but only
21966 /// slightly) more expensive than the other shuffle instructions.
21968 /// Because this is inherently a quadratic operation (for each shuffle in
21969 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21970 /// This should never be an issue in practice as the shuffle lowering doesn't
21971 /// produce sequences of more than 8 instructions.
21973 /// FIXME: We will currently miss some cases where the redundant shuffling
21974 /// would simplify under the threshold for PSHUFB formation because of
21975 /// combine-ordering. To fix this, we should do the redundant instruction
21976 /// combining in this recursive walk.
21977 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21978 ArrayRef<int> RootMask,
21979 int Depth, bool HasPSHUFB,
21981 TargetLowering::DAGCombinerInfo &DCI,
21982 const X86Subtarget *Subtarget) {
21983 // Bound the depth of our recursive combine because this is ultimately
21984 // quadratic in nature.
21988 // Directly rip through bitcasts to find the underlying operand.
21989 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21990 Op = Op.getOperand(0);
21992 MVT VT = Op.getSimpleValueType();
21993 if (!VT.isVector())
21994 return false; // Bail if we hit a non-vector.
21995 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21996 // version should be added.
21997 if (VT.getSizeInBits() != 128)
22000 assert(Root.getSimpleValueType().isVector() &&
22001 "Shuffles operate on vector types!");
22002 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22003 "Can only combine shuffles of the same vector register size.");
22005 if (!isTargetShuffle(Op.getOpcode()))
22007 SmallVector<int, 16> OpMask;
22009 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22010 // We only can combine unary shuffles which we can decode the mask for.
22011 if (!HaveMask || !IsUnary)
22014 assert(VT.getVectorNumElements() == OpMask.size() &&
22015 "Different mask size from vector size!");
22016 assert(((RootMask.size() > OpMask.size() &&
22017 RootMask.size() % OpMask.size() == 0) ||
22018 (OpMask.size() > RootMask.size() &&
22019 OpMask.size() % RootMask.size() == 0) ||
22020 OpMask.size() == RootMask.size()) &&
22021 "The smaller number of elements must divide the larger.");
22022 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22023 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22024 assert(((RootRatio == 1 && OpRatio == 1) ||
22025 (RootRatio == 1) != (OpRatio == 1)) &&
22026 "Must not have a ratio for both incoming and op masks!");
22028 SmallVector<int, 16> Mask;
22029 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22031 // Merge this shuffle operation's mask into our accumulated mask. Note that
22032 // this shuffle's mask will be the first applied to the input, followed by the
22033 // root mask to get us all the way to the root value arrangement. The reason
22034 // for this order is that we are recursing up the operation chain.
22035 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22036 int RootIdx = i / RootRatio;
22037 if (RootMask[RootIdx] < 0) {
22038 // This is a zero or undef lane, we're done.
22039 Mask.push_back(RootMask[RootIdx]);
22043 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22044 int OpIdx = RootMaskedIdx / OpRatio;
22045 if (OpMask[OpIdx] < 0) {
22046 // The incoming lanes are zero or undef, it doesn't matter which ones we
22048 Mask.push_back(OpMask[OpIdx]);
22052 // Ok, we have non-zero lanes, map them through.
22053 Mask.push_back(OpMask[OpIdx] * OpRatio +
22054 RootMaskedIdx % OpRatio);
22057 // See if we can recurse into the operand to combine more things.
22058 switch (Op.getOpcode()) {
22059 case X86ISD::PSHUFB:
22061 case X86ISD::PSHUFD:
22062 case X86ISD::PSHUFHW:
22063 case X86ISD::PSHUFLW:
22064 if (Op.getOperand(0).hasOneUse() &&
22065 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22066 HasPSHUFB, DAG, DCI, Subtarget))
22070 case X86ISD::UNPCKL:
22071 case X86ISD::UNPCKH:
22072 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22073 // We can't check for single use, we have to check that this shuffle is the only user.
22074 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22075 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22076 HasPSHUFB, DAG, DCI, Subtarget))
22081 // Minor canonicalization of the accumulated shuffle mask to make it easier
22082 // to match below. All this does is detect masks with squential pairs of
22083 // elements, and shrink them to the half-width mask. It does this in a loop
22084 // so it will reduce the size of the mask to the minimal width mask which
22085 // performs an equivalent shuffle.
22086 SmallVector<int, 16> WidenedMask;
22087 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22088 Mask = std::move(WidenedMask);
22089 WidenedMask.clear();
22092 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22096 /// \brief Get the PSHUF-style mask from PSHUF node.
22098 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22099 /// PSHUF-style masks that can be reused with such instructions.
22100 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22101 SmallVector<int, 4> Mask;
22103 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22107 switch (N.getOpcode()) {
22108 case X86ISD::PSHUFD:
22110 case X86ISD::PSHUFLW:
22113 case X86ISD::PSHUFHW:
22114 Mask.erase(Mask.begin(), Mask.begin() + 4);
22115 for (int &M : Mask)
22119 llvm_unreachable("No valid shuffle instruction found!");
22123 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22125 /// We walk up the chain and look for a combinable shuffle, skipping over
22126 /// shuffles that we could hoist this shuffle's transformation past without
22127 /// altering anything.
22129 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22131 TargetLowering::DAGCombinerInfo &DCI) {
22132 assert(N.getOpcode() == X86ISD::PSHUFD &&
22133 "Called with something other than an x86 128-bit half shuffle!");
22136 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22137 // of the shuffles in the chain so that we can form a fresh chain to replace
22139 SmallVector<SDValue, 8> Chain;
22140 SDValue V = N.getOperand(0);
22141 for (; V.hasOneUse(); V = V.getOperand(0)) {
22142 switch (V.getOpcode()) {
22144 return SDValue(); // Nothing combined!
22147 // Skip bitcasts as we always know the type for the target specific
22151 case X86ISD::PSHUFD:
22152 // Found another dword shuffle.
22155 case X86ISD::PSHUFLW:
22156 // Check that the low words (being shuffled) are the identity in the
22157 // dword shuffle, and the high words are self-contained.
22158 if (Mask[0] != 0 || Mask[1] != 1 ||
22159 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22162 Chain.push_back(V);
22165 case X86ISD::PSHUFHW:
22166 // Check that the high words (being shuffled) are the identity in the
22167 // dword shuffle, and the low words are self-contained.
22168 if (Mask[2] != 2 || Mask[3] != 3 ||
22169 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22172 Chain.push_back(V);
22175 case X86ISD::UNPCKL:
22176 case X86ISD::UNPCKH:
22177 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22178 // shuffle into a preceding word shuffle.
22179 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22182 // Search for a half-shuffle which we can combine with.
22183 unsigned CombineOp =
22184 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22185 if (V.getOperand(0) != V.getOperand(1) ||
22186 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22188 Chain.push_back(V);
22189 V = V.getOperand(0);
22191 switch (V.getOpcode()) {
22193 return SDValue(); // Nothing to combine.
22195 case X86ISD::PSHUFLW:
22196 case X86ISD::PSHUFHW:
22197 if (V.getOpcode() == CombineOp)
22200 Chain.push_back(V);
22204 V = V.getOperand(0);
22208 } while (V.hasOneUse());
22211 // Break out of the loop if we break out of the switch.
22215 if (!V.hasOneUse())
22216 // We fell out of the loop without finding a viable combining instruction.
22219 // Merge this node's mask and our incoming mask.
22220 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22221 for (int &M : Mask)
22223 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22224 getV4X86ShuffleImm8ForMask(Mask, DAG));
22226 // Rebuild the chain around this new shuffle.
22227 while (!Chain.empty()) {
22228 SDValue W = Chain.pop_back_val();
22230 if (V.getValueType() != W.getOperand(0).getValueType())
22231 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22233 switch (W.getOpcode()) {
22235 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22237 case X86ISD::UNPCKL:
22238 case X86ISD::UNPCKH:
22239 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22242 case X86ISD::PSHUFD:
22243 case X86ISD::PSHUFLW:
22244 case X86ISD::PSHUFHW:
22245 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22249 if (V.getValueType() != N.getValueType())
22250 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22252 // Return the new chain to replace N.
22256 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22258 /// We walk up the chain, skipping shuffles of the other half and looking
22259 /// through shuffles which switch halves trying to find a shuffle of the same
22260 /// pair of dwords.
22261 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22263 TargetLowering::DAGCombinerInfo &DCI) {
22265 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22266 "Called with something other than an x86 128-bit half shuffle!");
22268 unsigned CombineOpcode = N.getOpcode();
22270 // Walk up a single-use chain looking for a combinable shuffle.
22271 SDValue V = N.getOperand(0);
22272 for (; V.hasOneUse(); V = V.getOperand(0)) {
22273 switch (V.getOpcode()) {
22275 return false; // Nothing combined!
22278 // Skip bitcasts as we always know the type for the target specific
22282 case X86ISD::PSHUFLW:
22283 case X86ISD::PSHUFHW:
22284 if (V.getOpcode() == CombineOpcode)
22287 // Other-half shuffles are no-ops.
22290 // Break out of the loop if we break out of the switch.
22294 if (!V.hasOneUse())
22295 // We fell out of the loop without finding a viable combining instruction.
22298 // Combine away the bottom node as its shuffle will be accumulated into
22299 // a preceding shuffle.
22300 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22302 // Record the old value.
22305 // Merge this node's mask and our incoming mask (adjusted to account for all
22306 // the pshufd instructions encountered).
22307 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22308 for (int &M : Mask)
22310 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22311 getV4X86ShuffleImm8ForMask(Mask, DAG));
22313 // Check that the shuffles didn't cancel each other out. If not, we need to
22314 // combine to the new one.
22316 // Replace the combinable shuffle with the combined one, updating all users
22317 // so that we re-evaluate the chain here.
22318 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22323 /// \brief Try to combine x86 target specific shuffles.
22324 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22325 TargetLowering::DAGCombinerInfo &DCI,
22326 const X86Subtarget *Subtarget) {
22328 MVT VT = N.getSimpleValueType();
22329 SmallVector<int, 4> Mask;
22331 switch (N.getOpcode()) {
22332 case X86ISD::PSHUFD:
22333 case X86ISD::PSHUFLW:
22334 case X86ISD::PSHUFHW:
22335 Mask = getPSHUFShuffleMask(N);
22336 assert(Mask.size() == 4);
22342 // Nuke no-op shuffles that show up after combining.
22343 if (isNoopShuffleMask(Mask))
22344 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22346 // Look for simplifications involving one or two shuffle instructions.
22347 SDValue V = N.getOperand(0);
22348 switch (N.getOpcode()) {
22351 case X86ISD::PSHUFLW:
22352 case X86ISD::PSHUFHW:
22353 assert(VT == MVT::v8i16);
22356 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22357 return SDValue(); // We combined away this shuffle, so we're done.
22359 // See if this reduces to a PSHUFD which is no more expensive and can
22360 // combine with more operations. Note that it has to at least flip the
22361 // dwords as otherwise it would have been removed as a no-op.
22362 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22363 int DMask[] = {0, 1, 2, 3};
22364 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22365 DMask[DOffset + 0] = DOffset + 1;
22366 DMask[DOffset + 1] = DOffset + 0;
22367 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22368 DCI.AddToWorklist(V.getNode());
22369 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22370 getV4X86ShuffleImm8ForMask(DMask, DAG));
22371 DCI.AddToWorklist(V.getNode());
22372 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22375 // Look for shuffle patterns which can be implemented as a single unpack.
22376 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22377 // only works when we have a PSHUFD followed by two half-shuffles.
22378 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22379 (V.getOpcode() == X86ISD::PSHUFLW ||
22380 V.getOpcode() == X86ISD::PSHUFHW) &&
22381 V.getOpcode() != N.getOpcode() &&
22383 SDValue D = V.getOperand(0);
22384 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22385 D = D.getOperand(0);
22386 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22387 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22388 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22389 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22390 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22392 for (int i = 0; i < 4; ++i) {
22393 WordMask[i + NOffset] = Mask[i] + NOffset;
22394 WordMask[i + VOffset] = VMask[i] + VOffset;
22396 // Map the word mask through the DWord mask.
22398 for (int i = 0; i < 8; ++i)
22399 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22400 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22401 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22402 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22403 std::begin(UnpackLoMask)) ||
22404 std::equal(std::begin(MappedMask), std::end(MappedMask),
22405 std::begin(UnpackHiMask))) {
22406 // We can replace all three shuffles with an unpack.
22407 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22408 DCI.AddToWorklist(V.getNode());
22409 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22411 DL, MVT::v8i16, V, V);
22418 case X86ISD::PSHUFD:
22419 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22428 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22430 /// We combine this directly on the abstract vector shuffle nodes so it is
22431 /// easier to generically match. We also insert dummy vector shuffle nodes for
22432 /// the operands which explicitly discard the lanes which are unused by this
22433 /// operation to try to flow through the rest of the combiner the fact that
22434 /// they're unused.
22435 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22437 EVT VT = N->getValueType(0);
22439 // We only handle target-independent shuffles.
22440 // FIXME: It would be easy and harmless to use the target shuffle mask
22441 // extraction tool to support more.
22442 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22445 auto *SVN = cast<ShuffleVectorSDNode>(N);
22446 ArrayRef<int> Mask = SVN->getMask();
22447 SDValue V1 = N->getOperand(0);
22448 SDValue V2 = N->getOperand(1);
22450 // We require the first shuffle operand to be the SUB node, and the second to
22451 // be the ADD node.
22452 // FIXME: We should support the commuted patterns.
22453 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22456 // If there are other uses of these operations we can't fold them.
22457 if (!V1->hasOneUse() || !V2->hasOneUse())
22460 // Ensure that both operations have the same operands. Note that we can
22461 // commute the FADD operands.
22462 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22463 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22464 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22467 // We're looking for blends between FADD and FSUB nodes. We insist on these
22468 // nodes being lined up in a specific expected pattern.
22469 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22470 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22471 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22474 // Only specific types are legal at this point, assert so we notice if and
22475 // when these change.
22476 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22477 VT == MVT::v4f64) &&
22478 "Unknown vector type encountered!");
22480 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22483 /// PerformShuffleCombine - Performs several different shuffle combines.
22484 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22485 TargetLowering::DAGCombinerInfo &DCI,
22486 const X86Subtarget *Subtarget) {
22488 SDValue N0 = N->getOperand(0);
22489 SDValue N1 = N->getOperand(1);
22490 EVT VT = N->getValueType(0);
22492 // Don't create instructions with illegal types after legalize types has run.
22493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22494 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22497 // If we have legalized the vector types, look for blends of FADD and FSUB
22498 // nodes that we can fuse into an ADDSUB node.
22499 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22500 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22503 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22504 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22505 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22506 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22508 // During Type Legalization, when promoting illegal vector types,
22509 // the backend might introduce new shuffle dag nodes and bitcasts.
22511 // This code performs the following transformation:
22512 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22513 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22515 // We do this only if both the bitcast and the BINOP dag nodes have
22516 // one use. Also, perform this transformation only if the new binary
22517 // operation is legal. This is to avoid introducing dag nodes that
22518 // potentially need to be further expanded (or custom lowered) into a
22519 // less optimal sequence of dag nodes.
22520 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22521 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22522 N0.getOpcode() == ISD::BITCAST) {
22523 SDValue BC0 = N0.getOperand(0);
22524 EVT SVT = BC0.getValueType();
22525 unsigned Opcode = BC0.getOpcode();
22526 unsigned NumElts = VT.getVectorNumElements();
22528 if (BC0.hasOneUse() && SVT.isVector() &&
22529 SVT.getVectorNumElements() * 2 == NumElts &&
22530 TLI.isOperationLegal(Opcode, VT)) {
22531 bool CanFold = false;
22543 unsigned SVTNumElts = SVT.getVectorNumElements();
22544 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22545 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22546 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22547 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22548 CanFold = SVOp->getMaskElt(i) < 0;
22551 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22552 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22553 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22554 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22559 // Only handle 128 wide vector from here on.
22560 if (!VT.is128BitVector())
22563 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22564 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22565 // consecutive, non-overlapping, and in the right order.
22566 SmallVector<SDValue, 16> Elts;
22567 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22568 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22570 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22574 if (isTargetShuffle(N->getOpcode())) {
22576 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22577 if (Shuffle.getNode())
22580 // Try recursively combining arbitrary sequences of x86 shuffle
22581 // instructions into higher-order shuffles. We do this after combining
22582 // specific PSHUF instruction sequences into their minimal form so that we
22583 // can evaluate how many specialized shuffle instructions are involved in
22584 // a particular chain.
22585 SmallVector<int, 1> NonceMask; // Just a placeholder.
22586 NonceMask.push_back(0);
22587 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22588 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22590 return SDValue(); // This routine will use CombineTo to replace N.
22596 /// PerformTruncateCombine - Converts truncate operation to
22597 /// a sequence of vector shuffle operations.
22598 /// It is possible when we truncate 256-bit vector to 128-bit vector
22599 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22600 TargetLowering::DAGCombinerInfo &DCI,
22601 const X86Subtarget *Subtarget) {
22605 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22606 /// specific shuffle of a load can be folded into a single element load.
22607 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22608 /// shuffles have been custom lowered so we need to handle those here.
22609 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22610 TargetLowering::DAGCombinerInfo &DCI) {
22611 if (DCI.isBeforeLegalizeOps())
22614 SDValue InVec = N->getOperand(0);
22615 SDValue EltNo = N->getOperand(1);
22617 if (!isa<ConstantSDNode>(EltNo))
22620 EVT OriginalVT = InVec.getValueType();
22622 if (InVec.getOpcode() == ISD::BITCAST) {
22623 // Don't duplicate a load with other uses.
22624 if (!InVec.hasOneUse())
22626 EVT BCVT = InVec.getOperand(0).getValueType();
22627 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22629 InVec = InVec.getOperand(0);
22632 EVT CurrentVT = InVec.getValueType();
22634 if (!isTargetShuffle(InVec.getOpcode()))
22637 // Don't duplicate a load with other uses.
22638 if (!InVec.hasOneUse())
22641 SmallVector<int, 16> ShuffleMask;
22643 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22644 ShuffleMask, UnaryShuffle))
22647 // Select the input vector, guarding against out of range extract vector.
22648 unsigned NumElems = CurrentVT.getVectorNumElements();
22649 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22650 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22651 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22652 : InVec.getOperand(1);
22654 // If inputs to shuffle are the same for both ops, then allow 2 uses
22655 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22657 if (LdNode.getOpcode() == ISD::BITCAST) {
22658 // Don't duplicate a load with other uses.
22659 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22662 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22663 LdNode = LdNode.getOperand(0);
22666 if (!ISD::isNormalLoad(LdNode.getNode()))
22669 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22671 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22674 EVT EltVT = N->getValueType(0);
22675 // If there's a bitcast before the shuffle, check if the load type and
22676 // alignment is valid.
22677 unsigned Align = LN0->getAlignment();
22678 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22679 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22680 EltVT.getTypeForEVT(*DAG.getContext()));
22682 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22685 // All checks match so transform back to vector_shuffle so that DAG combiner
22686 // can finish the job
22689 // Create shuffle node taking into account the case that its a unary shuffle
22690 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22691 : InVec.getOperand(1);
22692 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22693 InVec.getOperand(0), Shuffle,
22695 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22696 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22700 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22701 /// generation and convert it from being a bunch of shuffles and extracts
22702 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22703 /// storing the value and loading scalars back, while for x64 we should
22704 /// use 64-bit extracts and shifts.
22705 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22706 TargetLowering::DAGCombinerInfo &DCI) {
22707 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22708 if (NewOp.getNode())
22711 SDValue InputVector = N->getOperand(0);
22713 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22714 // from mmx to v2i32 has a single usage.
22715 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22716 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22717 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22718 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22719 N->getValueType(0),
22720 InputVector.getNode()->getOperand(0));
22722 // Only operate on vectors of 4 elements, where the alternative shuffling
22723 // gets to be more expensive.
22724 if (InputVector.getValueType() != MVT::v4i32)
22727 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22728 // single use which is a sign-extend or zero-extend, and all elements are
22730 SmallVector<SDNode *, 4> Uses;
22731 unsigned ExtractedElements = 0;
22732 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22733 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22734 if (UI.getUse().getResNo() != InputVector.getResNo())
22737 SDNode *Extract = *UI;
22738 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22741 if (Extract->getValueType(0) != MVT::i32)
22743 if (!Extract->hasOneUse())
22745 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22746 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22748 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22751 // Record which element was extracted.
22752 ExtractedElements |=
22753 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22755 Uses.push_back(Extract);
22758 // If not all the elements were used, this may not be worthwhile.
22759 if (ExtractedElements != 15)
22762 // Ok, we've now decided to do the transformation.
22763 // If 64-bit shifts are legal, use the extract-shift sequence,
22764 // otherwise bounce the vector off the cache.
22765 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22767 SDLoc dl(InputVector);
22769 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22770 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22771 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22772 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22773 DAG.getConstant(0, VecIdxTy));
22774 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22775 DAG.getConstant(1, VecIdxTy));
22777 SDValue ShAmt = DAG.getConstant(32,
22778 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22779 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22780 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22781 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22782 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22783 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22784 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22786 // Store the value to a temporary stack slot.
22787 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22788 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22789 MachinePointerInfo(), false, false, 0);
22791 EVT ElementType = InputVector.getValueType().getVectorElementType();
22792 unsigned EltSize = ElementType.getSizeInBits() / 8;
22794 // Replace each use (extract) with a load of the appropriate element.
22795 for (unsigned i = 0; i < 4; ++i) {
22796 uint64_t Offset = EltSize * i;
22797 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22799 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22800 StackPtr, OffsetVal);
22802 // Load the scalar.
22803 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22804 ScalarAddr, MachinePointerInfo(),
22805 false, false, false, 0);
22810 // Replace the extracts
22811 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22812 UE = Uses.end(); UI != UE; ++UI) {
22813 SDNode *Extract = *UI;
22815 SDValue Idx = Extract->getOperand(1);
22816 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22817 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22820 // The replacement was made in place; don't return anything.
22824 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22825 static std::pair<unsigned, bool>
22826 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22827 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22828 if (!VT.isVector())
22829 return std::make_pair(0, false);
22831 bool NeedSplit = false;
22832 switch (VT.getSimpleVT().SimpleTy) {
22833 default: return std::make_pair(0, false);
22836 if (!Subtarget->hasVLX())
22837 return std::make_pair(0, false);
22841 if (!Subtarget->hasBWI())
22842 return std::make_pair(0, false);
22846 if (!Subtarget->hasAVX512())
22847 return std::make_pair(0, false);
22852 if (!Subtarget->hasAVX2())
22854 if (!Subtarget->hasAVX())
22855 return std::make_pair(0, false);
22860 if (!Subtarget->hasSSE2())
22861 return std::make_pair(0, false);
22864 // SSE2 has only a small subset of the operations.
22865 bool hasUnsigned = Subtarget->hasSSE41() ||
22866 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22867 bool hasSigned = Subtarget->hasSSE41() ||
22868 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22870 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22873 // Check for x CC y ? x : y.
22874 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22875 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22880 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22883 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22886 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22889 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22891 // Check for x CC y ? y : x -- a min/max with reversed arms.
22892 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22893 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22898 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22901 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22904 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22907 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22911 return std::make_pair(Opc, NeedSplit);
22915 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22916 const X86Subtarget *Subtarget) {
22918 SDValue Cond = N->getOperand(0);
22919 SDValue LHS = N->getOperand(1);
22920 SDValue RHS = N->getOperand(2);
22922 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22923 SDValue CondSrc = Cond->getOperand(0);
22924 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22925 Cond = CondSrc->getOperand(0);
22928 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22931 // A vselect where all conditions and data are constants can be optimized into
22932 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22933 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22934 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22937 unsigned MaskValue = 0;
22938 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22941 MVT VT = N->getSimpleValueType(0);
22942 unsigned NumElems = VT.getVectorNumElements();
22943 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22944 for (unsigned i = 0; i < NumElems; ++i) {
22945 // Be sure we emit undef where we can.
22946 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22947 ShuffleMask[i] = -1;
22949 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22952 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22953 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22955 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22958 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22960 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22961 TargetLowering::DAGCombinerInfo &DCI,
22962 const X86Subtarget *Subtarget) {
22964 SDValue Cond = N->getOperand(0);
22965 // Get the LHS/RHS of the select.
22966 SDValue LHS = N->getOperand(1);
22967 SDValue RHS = N->getOperand(2);
22968 EVT VT = LHS.getValueType();
22969 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22971 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22972 // instructions match the semantics of the common C idiom x<y?x:y but not
22973 // x<=y?x:y, because of how they handle negative zero (which can be
22974 // ignored in unsafe-math mode).
22975 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22976 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22977 (Subtarget->hasSSE2() ||
22978 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22979 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22981 unsigned Opcode = 0;
22982 // Check for x CC y ? x : y.
22983 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22984 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22988 // Converting this to a min would handle NaNs incorrectly, and swapping
22989 // the operands would cause it to handle comparisons between positive
22990 // and negative zero incorrectly.
22991 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22992 if (!DAG.getTarget().Options.UnsafeFPMath &&
22993 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22995 std::swap(LHS, RHS);
22997 Opcode = X86ISD::FMIN;
23000 // Converting this to a min would handle comparisons between positive
23001 // and negative zero incorrectly.
23002 if (!DAG.getTarget().Options.UnsafeFPMath &&
23003 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23005 Opcode = X86ISD::FMIN;
23008 // Converting this to a min would handle both negative zeros and NaNs
23009 // incorrectly, but we can swap the operands to fix both.
23010 std::swap(LHS, RHS);
23014 Opcode = X86ISD::FMIN;
23018 // Converting this to a max would handle comparisons between positive
23019 // and negative zero incorrectly.
23020 if (!DAG.getTarget().Options.UnsafeFPMath &&
23021 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23023 Opcode = X86ISD::FMAX;
23026 // Converting this to a max would handle NaNs incorrectly, and swapping
23027 // the operands would cause it to handle comparisons between positive
23028 // and negative zero incorrectly.
23029 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23030 if (!DAG.getTarget().Options.UnsafeFPMath &&
23031 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23033 std::swap(LHS, RHS);
23035 Opcode = X86ISD::FMAX;
23038 // Converting this to a max would handle both negative zeros and NaNs
23039 // incorrectly, but we can swap the operands to fix both.
23040 std::swap(LHS, RHS);
23044 Opcode = X86ISD::FMAX;
23047 // Check for x CC y ? y : x -- a min/max with reversed arms.
23048 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23049 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23053 // Converting this to a min would handle comparisons between positive
23054 // and negative zero incorrectly, and swapping the operands would
23055 // cause it to handle NaNs incorrectly.
23056 if (!DAG.getTarget().Options.UnsafeFPMath &&
23057 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23058 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23060 std::swap(LHS, RHS);
23062 Opcode = X86ISD::FMIN;
23065 // Converting this to a min would handle NaNs incorrectly.
23066 if (!DAG.getTarget().Options.UnsafeFPMath &&
23067 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23069 Opcode = X86ISD::FMIN;
23072 // Converting this to a min would handle both negative zeros and NaNs
23073 // incorrectly, but we can swap the operands to fix both.
23074 std::swap(LHS, RHS);
23078 Opcode = X86ISD::FMIN;
23082 // Converting this to a max would handle NaNs incorrectly.
23083 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23085 Opcode = X86ISD::FMAX;
23088 // Converting this to a max would handle comparisons between positive
23089 // and negative zero incorrectly, and swapping the operands would
23090 // cause it to handle NaNs incorrectly.
23091 if (!DAG.getTarget().Options.UnsafeFPMath &&
23092 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23093 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23095 std::swap(LHS, RHS);
23097 Opcode = X86ISD::FMAX;
23100 // Converting this to a max would handle both negative zeros and NaNs
23101 // incorrectly, but we can swap the operands to fix both.
23102 std::swap(LHS, RHS);
23106 Opcode = X86ISD::FMAX;
23112 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23115 EVT CondVT = Cond.getValueType();
23116 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23117 CondVT.getVectorElementType() == MVT::i1) {
23118 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23119 // lowering on KNL. In this case we convert it to
23120 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23121 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23122 // Since SKX these selects have a proper lowering.
23123 EVT OpVT = LHS.getValueType();
23124 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23125 (OpVT.getVectorElementType() == MVT::i8 ||
23126 OpVT.getVectorElementType() == MVT::i16) &&
23127 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23128 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23129 DCI.AddToWorklist(Cond.getNode());
23130 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23133 // If this is a select between two integer constants, try to do some
23135 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23136 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23137 // Don't do this for crazy integer types.
23138 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23139 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23140 // so that TrueC (the true value) is larger than FalseC.
23141 bool NeedsCondInvert = false;
23143 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23144 // Efficiently invertible.
23145 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23146 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23147 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23148 NeedsCondInvert = true;
23149 std::swap(TrueC, FalseC);
23152 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23153 if (FalseC->getAPIntValue() == 0 &&
23154 TrueC->getAPIntValue().isPowerOf2()) {
23155 if (NeedsCondInvert) // Invert the condition if needed.
23156 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23157 DAG.getConstant(1, Cond.getValueType()));
23159 // Zero extend the condition if needed.
23160 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23162 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23163 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23164 DAG.getConstant(ShAmt, MVT::i8));
23167 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23168 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23169 if (NeedsCondInvert) // Invert the condition if needed.
23170 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23171 DAG.getConstant(1, Cond.getValueType()));
23173 // Zero extend the condition if needed.
23174 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23175 FalseC->getValueType(0), Cond);
23176 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23177 SDValue(FalseC, 0));
23180 // Optimize cases that will turn into an LEA instruction. This requires
23181 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23182 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23183 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23184 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23186 bool isFastMultiplier = false;
23188 switch ((unsigned char)Diff) {
23190 case 1: // result = add base, cond
23191 case 2: // result = lea base( , cond*2)
23192 case 3: // result = lea base(cond, cond*2)
23193 case 4: // result = lea base( , cond*4)
23194 case 5: // result = lea base(cond, cond*4)
23195 case 8: // result = lea base( , cond*8)
23196 case 9: // result = lea base(cond, cond*8)
23197 isFastMultiplier = true;
23202 if (isFastMultiplier) {
23203 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23204 if (NeedsCondInvert) // Invert the condition if needed.
23205 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23206 DAG.getConstant(1, Cond.getValueType()));
23208 // Zero extend the condition if needed.
23209 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23211 // Scale the condition by the difference.
23213 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23214 DAG.getConstant(Diff, Cond.getValueType()));
23216 // Add the base if non-zero.
23217 if (FalseC->getAPIntValue() != 0)
23218 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23219 SDValue(FalseC, 0));
23226 // Canonicalize max and min:
23227 // (x > y) ? x : y -> (x >= y) ? x : y
23228 // (x < y) ? x : y -> (x <= y) ? x : y
23229 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23230 // the need for an extra compare
23231 // against zero. e.g.
23232 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23234 // testl %edi, %edi
23236 // cmovgl %edi, %eax
23240 // cmovsl %eax, %edi
23241 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23242 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23243 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23244 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23249 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23250 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23251 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23252 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23257 // Early exit check
23258 if (!TLI.isTypeLegal(VT))
23261 // Match VSELECTs into subs with unsigned saturation.
23262 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23263 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23264 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23265 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23266 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23268 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23269 // left side invert the predicate to simplify logic below.
23271 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23273 CC = ISD::getSetCCInverse(CC, true);
23274 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23278 if (Other.getNode() && Other->getNumOperands() == 2 &&
23279 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23280 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23281 SDValue CondRHS = Cond->getOperand(1);
23283 // Look for a general sub with unsigned saturation first.
23284 // x >= y ? x-y : 0 --> subus x, y
23285 // x > y ? x-y : 0 --> subus x, y
23286 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23287 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23288 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23290 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23291 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23292 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23293 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23294 // If the RHS is a constant we have to reverse the const
23295 // canonicalization.
23296 // x > C-1 ? x+-C : 0 --> subus x, C
23297 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23298 CondRHSConst->getAPIntValue() ==
23299 (-OpRHSConst->getAPIntValue() - 1))
23300 return DAG.getNode(
23301 X86ISD::SUBUS, DL, VT, OpLHS,
23302 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23304 // Another special case: If C was a sign bit, the sub has been
23305 // canonicalized into a xor.
23306 // FIXME: Would it be better to use computeKnownBits to determine
23307 // whether it's safe to decanonicalize the xor?
23308 // x s< 0 ? x^C : 0 --> subus x, C
23309 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23310 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23311 OpRHSConst->getAPIntValue().isSignBit())
23312 // Note that we have to rebuild the RHS constant here to ensure we
23313 // don't rely on particular values of undef lanes.
23314 return DAG.getNode(
23315 X86ISD::SUBUS, DL, VT, OpLHS,
23316 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23321 // Try to match a min/max vector operation.
23322 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23323 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23324 unsigned Opc = ret.first;
23325 bool NeedSplit = ret.second;
23327 if (Opc && NeedSplit) {
23328 unsigned NumElems = VT.getVectorNumElements();
23329 // Extract the LHS vectors
23330 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23331 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23333 // Extract the RHS vectors
23334 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23335 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23337 // Create min/max for each subvector
23338 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23339 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23341 // Merge the result
23342 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23344 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23347 // Simplify vector selection if condition value type matches vselect
23349 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23350 assert(Cond.getValueType().isVector() &&
23351 "vector select expects a vector selector!");
23353 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23354 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23356 // Try invert the condition if true value is not all 1s and false value
23358 if (!TValIsAllOnes && !FValIsAllZeros &&
23359 // Check if the selector will be produced by CMPP*/PCMP*
23360 Cond.getOpcode() == ISD::SETCC &&
23361 // Check if SETCC has already been promoted
23362 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23363 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23364 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23366 if (TValIsAllZeros || FValIsAllOnes) {
23367 SDValue CC = Cond.getOperand(2);
23368 ISD::CondCode NewCC =
23369 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23370 Cond.getOperand(0).getValueType().isInteger());
23371 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23372 std::swap(LHS, RHS);
23373 TValIsAllOnes = FValIsAllOnes;
23374 FValIsAllZeros = TValIsAllZeros;
23378 if (TValIsAllOnes || FValIsAllZeros) {
23381 if (TValIsAllOnes && FValIsAllZeros)
23383 else if (TValIsAllOnes)
23384 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23385 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23386 else if (FValIsAllZeros)
23387 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23388 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23390 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23394 // If we know that this node is legal then we know that it is going to be
23395 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23396 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23397 // to simplify previous instructions.
23398 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23399 !DCI.isBeforeLegalize() &&
23400 // We explicitly check against v8i16 and v16i16 because, although
23401 // they're marked as Custom, they might only be legal when Cond is a
23402 // build_vector of constants. This will be taken care in a later
23404 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23405 VT != MVT::v8i16) &&
23406 // Don't optimize vector of constants. Those are handled by
23407 // the generic code and all the bits must be properly set for
23408 // the generic optimizer.
23409 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23410 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23412 // Don't optimize vector selects that map to mask-registers.
23416 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23417 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23419 APInt KnownZero, KnownOne;
23420 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23421 DCI.isBeforeLegalizeOps());
23422 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23423 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23425 // If we changed the computation somewhere in the DAG, this change
23426 // will affect all users of Cond.
23427 // Make sure it is fine and update all the nodes so that we do not
23428 // use the generic VSELECT anymore. Otherwise, we may perform
23429 // wrong optimizations as we messed up with the actual expectation
23430 // for the vector boolean values.
23431 if (Cond != TLO.Old) {
23432 // Check all uses of that condition operand to check whether it will be
23433 // consumed by non-BLEND instructions, which may depend on all bits are
23435 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23437 if (I->getOpcode() != ISD::VSELECT)
23438 // TODO: Add other opcodes eventually lowered into BLEND.
23441 // Update all the users of the condition, before committing the change,
23442 // so that the VSELECT optimizations that expect the correct vector
23443 // boolean value will not be triggered.
23444 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23446 DAG.ReplaceAllUsesOfValueWith(
23448 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23449 Cond, I->getOperand(1), I->getOperand(2)));
23450 DCI.CommitTargetLoweringOpt(TLO);
23453 // At this point, only Cond is changed. Change the condition
23454 // just for N to keep the opportunity to optimize all other
23455 // users their own way.
23456 DAG.ReplaceAllUsesOfValueWith(
23458 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23459 TLO.New, N->getOperand(1), N->getOperand(2)));
23464 // We should generate an X86ISD::BLENDI from a vselect if its argument
23465 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23466 // constants. This specific pattern gets generated when we split a
23467 // selector for a 512 bit vector in a machine without AVX512 (but with
23468 // 256-bit vectors), during legalization:
23470 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23472 // Iff we find this pattern and the build_vectors are built from
23473 // constants, we translate the vselect into a shuffle_vector that we
23474 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23475 if ((N->getOpcode() == ISD::VSELECT ||
23476 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23477 !DCI.isBeforeLegalize()) {
23478 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23479 if (Shuffle.getNode())
23486 // Check whether a boolean test is testing a boolean value generated by
23487 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23490 // Simplify the following patterns:
23491 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23492 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23493 // to (Op EFLAGS Cond)
23495 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23496 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23497 // to (Op EFLAGS !Cond)
23499 // where Op could be BRCOND or CMOV.
23501 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23502 // Quit if not CMP and SUB with its value result used.
23503 if (Cmp.getOpcode() != X86ISD::CMP &&
23504 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23507 // Quit if not used as a boolean value.
23508 if (CC != X86::COND_E && CC != X86::COND_NE)
23511 // Check CMP operands. One of them should be 0 or 1 and the other should be
23512 // an SetCC or extended from it.
23513 SDValue Op1 = Cmp.getOperand(0);
23514 SDValue Op2 = Cmp.getOperand(1);
23517 const ConstantSDNode* C = nullptr;
23518 bool needOppositeCond = (CC == X86::COND_E);
23519 bool checkAgainstTrue = false; // Is it a comparison against 1?
23521 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23523 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23525 else // Quit if all operands are not constants.
23528 if (C->getZExtValue() == 1) {
23529 needOppositeCond = !needOppositeCond;
23530 checkAgainstTrue = true;
23531 } else if (C->getZExtValue() != 0)
23532 // Quit if the constant is neither 0 or 1.
23535 bool truncatedToBoolWithAnd = false;
23536 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23537 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23538 SetCC.getOpcode() == ISD::TRUNCATE ||
23539 SetCC.getOpcode() == ISD::AND) {
23540 if (SetCC.getOpcode() == ISD::AND) {
23542 ConstantSDNode *CS;
23543 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23544 CS->getZExtValue() == 1)
23546 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23547 CS->getZExtValue() == 1)
23551 SetCC = SetCC.getOperand(OpIdx);
23552 truncatedToBoolWithAnd = true;
23554 SetCC = SetCC.getOperand(0);
23557 switch (SetCC.getOpcode()) {
23558 case X86ISD::SETCC_CARRY:
23559 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23560 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23561 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23562 // truncated to i1 using 'and'.
23563 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23565 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23566 "Invalid use of SETCC_CARRY!");
23568 case X86ISD::SETCC:
23569 // Set the condition code or opposite one if necessary.
23570 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23571 if (needOppositeCond)
23572 CC = X86::GetOppositeBranchCondition(CC);
23573 return SetCC.getOperand(1);
23574 case X86ISD::CMOV: {
23575 // Check whether false/true value has canonical one, i.e. 0 or 1.
23576 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23577 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23578 // Quit if true value is not a constant.
23581 // Quit if false value is not a constant.
23583 SDValue Op = SetCC.getOperand(0);
23584 // Skip 'zext' or 'trunc' node.
23585 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23586 Op.getOpcode() == ISD::TRUNCATE)
23587 Op = Op.getOperand(0);
23588 // A special case for rdrand/rdseed, where 0 is set if false cond is
23590 if ((Op.getOpcode() != X86ISD::RDRAND &&
23591 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23594 // Quit if false value is not the constant 0 or 1.
23595 bool FValIsFalse = true;
23596 if (FVal && FVal->getZExtValue() != 0) {
23597 if (FVal->getZExtValue() != 1)
23599 // If FVal is 1, opposite cond is needed.
23600 needOppositeCond = !needOppositeCond;
23601 FValIsFalse = false;
23603 // Quit if TVal is not the constant opposite of FVal.
23604 if (FValIsFalse && TVal->getZExtValue() != 1)
23606 if (!FValIsFalse && TVal->getZExtValue() != 0)
23608 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23609 if (needOppositeCond)
23610 CC = X86::GetOppositeBranchCondition(CC);
23611 return SetCC.getOperand(3);
23618 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23619 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23620 TargetLowering::DAGCombinerInfo &DCI,
23621 const X86Subtarget *Subtarget) {
23624 // If the flag operand isn't dead, don't touch this CMOV.
23625 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23628 SDValue FalseOp = N->getOperand(0);
23629 SDValue TrueOp = N->getOperand(1);
23630 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23631 SDValue Cond = N->getOperand(3);
23633 if (CC == X86::COND_E || CC == X86::COND_NE) {
23634 switch (Cond.getOpcode()) {
23638 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23639 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23640 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23646 Flags = checkBoolTestSetCCCombine(Cond, CC);
23647 if (Flags.getNode() &&
23648 // Extra check as FCMOV only supports a subset of X86 cond.
23649 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23650 SDValue Ops[] = { FalseOp, TrueOp,
23651 DAG.getConstant(CC, MVT::i8), Flags };
23652 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23655 // If this is a select between two integer constants, try to do some
23656 // optimizations. Note that the operands are ordered the opposite of SELECT
23658 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23659 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23660 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23661 // larger than FalseC (the false value).
23662 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23663 CC = X86::GetOppositeBranchCondition(CC);
23664 std::swap(TrueC, FalseC);
23665 std::swap(TrueOp, FalseOp);
23668 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23669 // This is efficient for any integer data type (including i8/i16) and
23671 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23672 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23673 DAG.getConstant(CC, MVT::i8), Cond);
23675 // Zero extend the condition if needed.
23676 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23678 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23679 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23680 DAG.getConstant(ShAmt, MVT::i8));
23681 if (N->getNumValues() == 2) // Dead flag value?
23682 return DCI.CombineTo(N, Cond, SDValue());
23686 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23687 // for any integer data type, including i8/i16.
23688 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23689 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23690 DAG.getConstant(CC, MVT::i8), Cond);
23692 // Zero extend the condition if needed.
23693 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23694 FalseC->getValueType(0), Cond);
23695 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23696 SDValue(FalseC, 0));
23698 if (N->getNumValues() == 2) // Dead flag value?
23699 return DCI.CombineTo(N, Cond, SDValue());
23703 // Optimize cases that will turn into an LEA instruction. This requires
23704 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23705 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23706 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23707 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23709 bool isFastMultiplier = false;
23711 switch ((unsigned char)Diff) {
23713 case 1: // result = add base, cond
23714 case 2: // result = lea base( , cond*2)
23715 case 3: // result = lea base(cond, cond*2)
23716 case 4: // result = lea base( , cond*4)
23717 case 5: // result = lea base(cond, cond*4)
23718 case 8: // result = lea base( , cond*8)
23719 case 9: // result = lea base(cond, cond*8)
23720 isFastMultiplier = true;
23725 if (isFastMultiplier) {
23726 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23727 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23728 DAG.getConstant(CC, MVT::i8), Cond);
23729 // Zero extend the condition if needed.
23730 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23732 // Scale the condition by the difference.
23734 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23735 DAG.getConstant(Diff, Cond.getValueType()));
23737 // Add the base if non-zero.
23738 if (FalseC->getAPIntValue() != 0)
23739 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23740 SDValue(FalseC, 0));
23741 if (N->getNumValues() == 2) // Dead flag value?
23742 return DCI.CombineTo(N, Cond, SDValue());
23749 // Handle these cases:
23750 // (select (x != c), e, c) -> select (x != c), e, x),
23751 // (select (x == c), c, e) -> select (x == c), x, e)
23752 // where the c is an integer constant, and the "select" is the combination
23753 // of CMOV and CMP.
23755 // The rationale for this change is that the conditional-move from a constant
23756 // needs two instructions, however, conditional-move from a register needs
23757 // only one instruction.
23759 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23760 // some instruction-combining opportunities. This opt needs to be
23761 // postponed as late as possible.
23763 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23764 // the DCI.xxxx conditions are provided to postpone the optimization as
23765 // late as possible.
23767 ConstantSDNode *CmpAgainst = nullptr;
23768 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23769 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23770 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23772 if (CC == X86::COND_NE &&
23773 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23774 CC = X86::GetOppositeBranchCondition(CC);
23775 std::swap(TrueOp, FalseOp);
23778 if (CC == X86::COND_E &&
23779 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23780 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23781 DAG.getConstant(CC, MVT::i8), Cond };
23782 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23790 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23791 const X86Subtarget *Subtarget) {
23792 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23794 default: return SDValue();
23795 // SSE/AVX/AVX2 blend intrinsics.
23796 case Intrinsic::x86_avx2_pblendvb:
23797 case Intrinsic::x86_avx2_pblendw:
23798 case Intrinsic::x86_avx2_pblendd_128:
23799 case Intrinsic::x86_avx2_pblendd_256:
23800 // Don't try to simplify this intrinsic if we don't have AVX2.
23801 if (!Subtarget->hasAVX2())
23804 case Intrinsic::x86_avx_blend_pd_256:
23805 case Intrinsic::x86_avx_blend_ps_256:
23806 case Intrinsic::x86_avx_blendv_pd_256:
23807 case Intrinsic::x86_avx_blendv_ps_256:
23808 // Don't try to simplify this intrinsic if we don't have AVX.
23809 if (!Subtarget->hasAVX())
23812 case Intrinsic::x86_sse41_pblendw:
23813 case Intrinsic::x86_sse41_blendpd:
23814 case Intrinsic::x86_sse41_blendps:
23815 case Intrinsic::x86_sse41_blendvps:
23816 case Intrinsic::x86_sse41_blendvpd:
23817 case Intrinsic::x86_sse41_pblendvb: {
23818 SDValue Op0 = N->getOperand(1);
23819 SDValue Op1 = N->getOperand(2);
23820 SDValue Mask = N->getOperand(3);
23822 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23823 if (!Subtarget->hasSSE41())
23826 // fold (blend A, A, Mask) -> A
23829 // fold (blend A, B, allZeros) -> A
23830 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23832 // fold (blend A, B, allOnes) -> B
23833 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23836 // Simplify the case where the mask is a constant i32 value.
23837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23838 if (C->isNullValue())
23840 if (C->isAllOnesValue())
23847 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23848 case Intrinsic::x86_sse2_psrai_w:
23849 case Intrinsic::x86_sse2_psrai_d:
23850 case Intrinsic::x86_avx2_psrai_w:
23851 case Intrinsic::x86_avx2_psrai_d:
23852 case Intrinsic::x86_sse2_psra_w:
23853 case Intrinsic::x86_sse2_psra_d:
23854 case Intrinsic::x86_avx2_psra_w:
23855 case Intrinsic::x86_avx2_psra_d: {
23856 SDValue Op0 = N->getOperand(1);
23857 SDValue Op1 = N->getOperand(2);
23858 EVT VT = Op0.getValueType();
23859 assert(VT.isVector() && "Expected a vector type!");
23861 if (isa<BuildVectorSDNode>(Op1))
23862 Op1 = Op1.getOperand(0);
23864 if (!isa<ConstantSDNode>(Op1))
23867 EVT SVT = VT.getVectorElementType();
23868 unsigned SVTBits = SVT.getSizeInBits();
23870 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23871 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23872 uint64_t ShAmt = C.getZExtValue();
23874 // Don't try to convert this shift into a ISD::SRA if the shift
23875 // count is bigger than or equal to the element size.
23876 if (ShAmt >= SVTBits)
23879 // Trivial case: if the shift count is zero, then fold this
23880 // into the first operand.
23884 // Replace this packed shift intrinsic with a target independent
23886 SDValue Splat = DAG.getConstant(C, VT);
23887 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23892 /// PerformMulCombine - Optimize a single multiply with constant into two
23893 /// in order to implement it with two cheaper instructions, e.g.
23894 /// LEA + SHL, LEA + LEA.
23895 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23896 TargetLowering::DAGCombinerInfo &DCI) {
23897 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23900 EVT VT = N->getValueType(0);
23901 if (VT != MVT::i64)
23904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23907 uint64_t MulAmt = C->getZExtValue();
23908 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23911 uint64_t MulAmt1 = 0;
23912 uint64_t MulAmt2 = 0;
23913 if ((MulAmt % 9) == 0) {
23915 MulAmt2 = MulAmt / 9;
23916 } else if ((MulAmt % 5) == 0) {
23918 MulAmt2 = MulAmt / 5;
23919 } else if ((MulAmt % 3) == 0) {
23921 MulAmt2 = MulAmt / 3;
23924 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23927 if (isPowerOf2_64(MulAmt2) &&
23928 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23929 // If second multiplifer is pow2, issue it first. We want the multiply by
23930 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23932 std::swap(MulAmt1, MulAmt2);
23935 if (isPowerOf2_64(MulAmt1))
23936 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23937 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23939 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23940 DAG.getConstant(MulAmt1, VT));
23942 if (isPowerOf2_64(MulAmt2))
23943 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23944 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23946 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23947 DAG.getConstant(MulAmt2, VT));
23949 // Do not add new nodes to DAG combiner worklist.
23950 DCI.CombineTo(N, NewMul, false);
23955 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23956 SDValue N0 = N->getOperand(0);
23957 SDValue N1 = N->getOperand(1);
23958 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23959 EVT VT = N0.getValueType();
23961 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23962 // since the result of setcc_c is all zero's or all ones.
23963 if (VT.isInteger() && !VT.isVector() &&
23964 N1C && N0.getOpcode() == ISD::AND &&
23965 N0.getOperand(1).getOpcode() == ISD::Constant) {
23966 SDValue N00 = N0.getOperand(0);
23967 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23968 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23969 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23970 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23971 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23972 APInt ShAmt = N1C->getAPIntValue();
23973 Mask = Mask.shl(ShAmt);
23975 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23976 N00, DAG.getConstant(Mask, VT));
23980 // Hardware support for vector shifts is sparse which makes us scalarize the
23981 // vector operations in many cases. Also, on sandybridge ADD is faster than
23983 // (shl V, 1) -> add V,V
23984 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23985 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23986 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23987 // We shift all of the values by one. In many cases we do not have
23988 // hardware support for this operation. This is better expressed as an ADD
23990 if (N1SplatC->getZExtValue() == 1)
23991 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23997 /// \brief Returns a vector of 0s if the node in input is a vector logical
23998 /// shift by a constant amount which is known to be bigger than or equal
23999 /// to the vector element size in bits.
24000 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24001 const X86Subtarget *Subtarget) {
24002 EVT VT = N->getValueType(0);
24004 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24005 (!Subtarget->hasInt256() ||
24006 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24009 SDValue Amt = N->getOperand(1);
24011 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24012 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24013 APInt ShiftAmt = AmtSplat->getAPIntValue();
24014 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24016 // SSE2/AVX2 logical shifts always return a vector of 0s
24017 // if the shift amount is bigger than or equal to
24018 // the element size. The constant shift amount will be
24019 // encoded as a 8-bit immediate.
24020 if (ShiftAmt.trunc(8).uge(MaxAmount))
24021 return getZeroVector(VT, Subtarget, DAG, DL);
24027 /// PerformShiftCombine - Combine shifts.
24028 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24029 TargetLowering::DAGCombinerInfo &DCI,
24030 const X86Subtarget *Subtarget) {
24031 if (N->getOpcode() == ISD::SHL) {
24032 SDValue V = PerformSHLCombine(N, DAG);
24033 if (V.getNode()) return V;
24036 if (N->getOpcode() != ISD::SRA) {
24037 // Try to fold this logical shift into a zero vector.
24038 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24039 if (V.getNode()) return V;
24045 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24046 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24047 // and friends. Likewise for OR -> CMPNEQSS.
24048 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24049 TargetLowering::DAGCombinerInfo &DCI,
24050 const X86Subtarget *Subtarget) {
24053 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24054 // we're requiring SSE2 for both.
24055 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24056 SDValue N0 = N->getOperand(0);
24057 SDValue N1 = N->getOperand(1);
24058 SDValue CMP0 = N0->getOperand(1);
24059 SDValue CMP1 = N1->getOperand(1);
24062 // The SETCCs should both refer to the same CMP.
24063 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24066 SDValue CMP00 = CMP0->getOperand(0);
24067 SDValue CMP01 = CMP0->getOperand(1);
24068 EVT VT = CMP00.getValueType();
24070 if (VT == MVT::f32 || VT == MVT::f64) {
24071 bool ExpectingFlags = false;
24072 // Check for any users that want flags:
24073 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24074 !ExpectingFlags && UI != UE; ++UI)
24075 switch (UI->getOpcode()) {
24080 ExpectingFlags = true;
24082 case ISD::CopyToReg:
24083 case ISD::SIGN_EXTEND:
24084 case ISD::ZERO_EXTEND:
24085 case ISD::ANY_EXTEND:
24089 if (!ExpectingFlags) {
24090 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24091 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24093 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24094 X86::CondCode tmp = cc0;
24099 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24100 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24101 // FIXME: need symbolic constants for these magic numbers.
24102 // See X86ATTInstPrinter.cpp:printSSECC().
24103 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24104 if (Subtarget->hasAVX512()) {
24105 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24106 CMP01, DAG.getConstant(x86cc, MVT::i8));
24107 if (N->getValueType(0) != MVT::i1)
24108 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24112 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24113 CMP00.getValueType(), CMP00, CMP01,
24114 DAG.getConstant(x86cc, MVT::i8));
24116 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24117 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24119 if (is64BitFP && !Subtarget->is64Bit()) {
24120 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24121 // 64-bit integer, since that's not a legal type. Since
24122 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24123 // bits, but can do this little dance to extract the lowest 32 bits
24124 // and work with those going forward.
24125 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24127 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24129 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24130 Vector32, DAG.getIntPtrConstant(0));
24134 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24135 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24136 DAG.getConstant(1, IntVT));
24137 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24138 return OneBitOfTruth;
24146 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24147 /// so it can be folded inside ANDNP.
24148 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24149 EVT VT = N->getValueType(0);
24151 // Match direct AllOnes for 128 and 256-bit vectors
24152 if (ISD::isBuildVectorAllOnes(N))
24155 // Look through a bit convert.
24156 if (N->getOpcode() == ISD::BITCAST)
24157 N = N->getOperand(0).getNode();
24159 // Sometimes the operand may come from a insert_subvector building a 256-bit
24161 if (VT.is256BitVector() &&
24162 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24163 SDValue V1 = N->getOperand(0);
24164 SDValue V2 = N->getOperand(1);
24166 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24167 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24168 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24169 ISD::isBuildVectorAllOnes(V2.getNode()))
24176 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24177 // register. In most cases we actually compare or select YMM-sized registers
24178 // and mixing the two types creates horrible code. This method optimizes
24179 // some of the transition sequences.
24180 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24181 TargetLowering::DAGCombinerInfo &DCI,
24182 const X86Subtarget *Subtarget) {
24183 EVT VT = N->getValueType(0);
24184 if (!VT.is256BitVector())
24187 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24188 N->getOpcode() == ISD::ZERO_EXTEND ||
24189 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24191 SDValue Narrow = N->getOperand(0);
24192 EVT NarrowVT = Narrow->getValueType(0);
24193 if (!NarrowVT.is128BitVector())
24196 if (Narrow->getOpcode() != ISD::XOR &&
24197 Narrow->getOpcode() != ISD::AND &&
24198 Narrow->getOpcode() != ISD::OR)
24201 SDValue N0 = Narrow->getOperand(0);
24202 SDValue N1 = Narrow->getOperand(1);
24205 // The Left side has to be a trunc.
24206 if (N0.getOpcode() != ISD::TRUNCATE)
24209 // The type of the truncated inputs.
24210 EVT WideVT = N0->getOperand(0)->getValueType(0);
24214 // The right side has to be a 'trunc' or a constant vector.
24215 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24216 ConstantSDNode *RHSConstSplat = nullptr;
24217 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24218 RHSConstSplat = RHSBV->getConstantSplatNode();
24219 if (!RHSTrunc && !RHSConstSplat)
24222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24224 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24227 // Set N0 and N1 to hold the inputs to the new wide operation.
24228 N0 = N0->getOperand(0);
24229 if (RHSConstSplat) {
24230 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24231 SDValue(RHSConstSplat, 0));
24232 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24233 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24234 } else if (RHSTrunc) {
24235 N1 = N1->getOperand(0);
24238 // Generate the wide operation.
24239 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24240 unsigned Opcode = N->getOpcode();
24242 case ISD::ANY_EXTEND:
24244 case ISD::ZERO_EXTEND: {
24245 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24246 APInt Mask = APInt::getAllOnesValue(InBits);
24247 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24248 return DAG.getNode(ISD::AND, DL, VT,
24249 Op, DAG.getConstant(Mask, VT));
24251 case ISD::SIGN_EXTEND:
24252 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24253 Op, DAG.getValueType(NarrowVT));
24255 llvm_unreachable("Unexpected opcode");
24259 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24260 TargetLowering::DAGCombinerInfo &DCI,
24261 const X86Subtarget *Subtarget) {
24262 EVT VT = N->getValueType(0);
24263 if (DCI.isBeforeLegalizeOps())
24266 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24270 // Create BEXTR instructions
24271 // BEXTR is ((X >> imm) & (2**size-1))
24272 if (VT == MVT::i32 || VT == MVT::i64) {
24273 SDValue N0 = N->getOperand(0);
24274 SDValue N1 = N->getOperand(1);
24277 // Check for BEXTR.
24278 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24279 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24280 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24281 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24282 if (MaskNode && ShiftNode) {
24283 uint64_t Mask = MaskNode->getZExtValue();
24284 uint64_t Shift = ShiftNode->getZExtValue();
24285 if (isMask_64(Mask)) {
24286 uint64_t MaskSize = CountPopulation_64(Mask);
24287 if (Shift + MaskSize <= VT.getSizeInBits())
24288 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24289 DAG.getConstant(Shift | (MaskSize << 8), VT));
24297 // Want to form ANDNP nodes:
24298 // 1) In the hopes of then easily combining them with OR and AND nodes
24299 // to form PBLEND/PSIGN.
24300 // 2) To match ANDN packed intrinsics
24301 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24304 SDValue N0 = N->getOperand(0);
24305 SDValue N1 = N->getOperand(1);
24308 // Check LHS for vnot
24309 if (N0.getOpcode() == ISD::XOR &&
24310 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24311 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24312 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24314 // Check RHS for vnot
24315 if (N1.getOpcode() == ISD::XOR &&
24316 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24317 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24318 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24323 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24324 TargetLowering::DAGCombinerInfo &DCI,
24325 const X86Subtarget *Subtarget) {
24326 if (DCI.isBeforeLegalizeOps())
24329 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24333 SDValue N0 = N->getOperand(0);
24334 SDValue N1 = N->getOperand(1);
24335 EVT VT = N->getValueType(0);
24337 // look for psign/blend
24338 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24339 if (!Subtarget->hasSSSE3() ||
24340 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24343 // Canonicalize pandn to RHS
24344 if (N0.getOpcode() == X86ISD::ANDNP)
24346 // or (and (m, y), (pandn m, x))
24347 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24348 SDValue Mask = N1.getOperand(0);
24349 SDValue X = N1.getOperand(1);
24351 if (N0.getOperand(0) == Mask)
24352 Y = N0.getOperand(1);
24353 if (N0.getOperand(1) == Mask)
24354 Y = N0.getOperand(0);
24356 // Check to see if the mask appeared in both the AND and ANDNP and
24360 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24361 // Look through mask bitcast.
24362 if (Mask.getOpcode() == ISD::BITCAST)
24363 Mask = Mask.getOperand(0);
24364 if (X.getOpcode() == ISD::BITCAST)
24365 X = X.getOperand(0);
24366 if (Y.getOpcode() == ISD::BITCAST)
24367 Y = Y.getOperand(0);
24369 EVT MaskVT = Mask.getValueType();
24371 // Validate that the Mask operand is a vector sra node.
24372 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24373 // there is no psrai.b
24374 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24375 unsigned SraAmt = ~0;
24376 if (Mask.getOpcode() == ISD::SRA) {
24377 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24378 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24379 SraAmt = AmtConst->getZExtValue();
24380 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24381 SDValue SraC = Mask.getOperand(1);
24382 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24384 if ((SraAmt + 1) != EltBits)
24389 // Now we know we at least have a plendvb with the mask val. See if
24390 // we can form a psignb/w/d.
24391 // psign = x.type == y.type == mask.type && y = sub(0, x);
24392 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24393 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24394 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24395 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24396 "Unsupported VT for PSIGN");
24397 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24398 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24400 // PBLENDVB only available on SSE 4.1
24401 if (!Subtarget->hasSSE41())
24404 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24406 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24407 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24408 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24409 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24410 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24414 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24417 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24418 MachineFunction &MF = DAG.getMachineFunction();
24419 bool OptForSize = MF.getFunction()->getAttributes().
24420 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24422 // SHLD/SHRD instructions have lower register pressure, but on some
24423 // platforms they have higher latency than the equivalent
24424 // series of shifts/or that would otherwise be generated.
24425 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24426 // have higher latencies and we are not optimizing for size.
24427 if (!OptForSize && Subtarget->isSHLDSlow())
24430 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24432 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24434 if (!N0.hasOneUse() || !N1.hasOneUse())
24437 SDValue ShAmt0 = N0.getOperand(1);
24438 if (ShAmt0.getValueType() != MVT::i8)
24440 SDValue ShAmt1 = N1.getOperand(1);
24441 if (ShAmt1.getValueType() != MVT::i8)
24443 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24444 ShAmt0 = ShAmt0.getOperand(0);
24445 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24446 ShAmt1 = ShAmt1.getOperand(0);
24449 unsigned Opc = X86ISD::SHLD;
24450 SDValue Op0 = N0.getOperand(0);
24451 SDValue Op1 = N1.getOperand(0);
24452 if (ShAmt0.getOpcode() == ISD::SUB) {
24453 Opc = X86ISD::SHRD;
24454 std::swap(Op0, Op1);
24455 std::swap(ShAmt0, ShAmt1);
24458 unsigned Bits = VT.getSizeInBits();
24459 if (ShAmt1.getOpcode() == ISD::SUB) {
24460 SDValue Sum = ShAmt1.getOperand(0);
24461 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24462 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24463 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24464 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24465 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24466 return DAG.getNode(Opc, DL, VT,
24468 DAG.getNode(ISD::TRUNCATE, DL,
24471 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24472 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24474 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24475 return DAG.getNode(Opc, DL, VT,
24476 N0.getOperand(0), N1.getOperand(0),
24477 DAG.getNode(ISD::TRUNCATE, DL,
24484 // Generate NEG and CMOV for integer abs.
24485 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24486 EVT VT = N->getValueType(0);
24488 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24489 // 8-bit integer abs to NEG and CMOV.
24490 if (VT.isInteger() && VT.getSizeInBits() == 8)
24493 SDValue N0 = N->getOperand(0);
24494 SDValue N1 = N->getOperand(1);
24497 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24498 // and change it to SUB and CMOV.
24499 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24500 N0.getOpcode() == ISD::ADD &&
24501 N0.getOperand(1) == N1 &&
24502 N1.getOpcode() == ISD::SRA &&
24503 N1.getOperand(0) == N0.getOperand(0))
24504 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24505 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24506 // Generate SUB & CMOV.
24507 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24508 DAG.getConstant(0, VT), N0.getOperand(0));
24510 SDValue Ops[] = { N0.getOperand(0), Neg,
24511 DAG.getConstant(X86::COND_GE, MVT::i8),
24512 SDValue(Neg.getNode(), 1) };
24513 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24518 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24519 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24520 TargetLowering::DAGCombinerInfo &DCI,
24521 const X86Subtarget *Subtarget) {
24522 if (DCI.isBeforeLegalizeOps())
24525 if (Subtarget->hasCMov()) {
24526 SDValue RV = performIntegerAbsCombine(N, DAG);
24534 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24535 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24536 TargetLowering::DAGCombinerInfo &DCI,
24537 const X86Subtarget *Subtarget) {
24538 LoadSDNode *Ld = cast<LoadSDNode>(N);
24539 EVT RegVT = Ld->getValueType(0);
24540 EVT MemVT = Ld->getMemoryVT();
24542 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24544 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24545 // into two 16-byte operations.
24546 ISD::LoadExtType Ext = Ld->getExtensionType();
24547 unsigned Alignment = Ld->getAlignment();
24548 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24549 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24550 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24551 unsigned NumElems = RegVT.getVectorNumElements();
24555 SDValue Ptr = Ld->getBasePtr();
24556 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24558 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24560 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24561 Ld->getPointerInfo(), Ld->isVolatile(),
24562 Ld->isNonTemporal(), Ld->isInvariant(),
24564 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24565 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24566 Ld->getPointerInfo(), Ld->isVolatile(),
24567 Ld->isNonTemporal(), Ld->isInvariant(),
24568 std::min(16U, Alignment));
24569 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24571 Load2.getValue(1));
24573 SDValue NewVec = DAG.getUNDEF(RegVT);
24574 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24575 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24576 return DCI.CombineTo(N, NewVec, TF, true);
24582 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24583 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24584 const X86Subtarget *Subtarget) {
24585 StoreSDNode *St = cast<StoreSDNode>(N);
24586 EVT VT = St->getValue().getValueType();
24587 EVT StVT = St->getMemoryVT();
24589 SDValue StoredVal = St->getOperand(1);
24590 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24592 // If we are saving a concatenation of two XMM registers and 32-byte stores
24593 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24594 unsigned Alignment = St->getAlignment();
24595 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24596 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24597 StVT == VT && !IsAligned) {
24598 unsigned NumElems = VT.getVectorNumElements();
24602 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24603 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24605 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24606 SDValue Ptr0 = St->getBasePtr();
24607 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24609 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24610 St->getPointerInfo(), St->isVolatile(),
24611 St->isNonTemporal(), Alignment);
24612 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24613 St->getPointerInfo(), St->isVolatile(),
24614 St->isNonTemporal(),
24615 std::min(16U, Alignment));
24616 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24619 // Optimize trunc store (of multiple scalars) to shuffle and store.
24620 // First, pack all of the elements in one place. Next, store to memory
24621 // in fewer chunks.
24622 if (St->isTruncatingStore() && VT.isVector()) {
24623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24624 unsigned NumElems = VT.getVectorNumElements();
24625 assert(StVT != VT && "Cannot truncate to the same type");
24626 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24627 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24629 // From, To sizes and ElemCount must be pow of two
24630 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24631 // We are going to use the original vector elt for storing.
24632 // Accumulated smaller vector elements must be a multiple of the store size.
24633 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24635 unsigned SizeRatio = FromSz / ToSz;
24637 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24639 // Create a type on which we perform the shuffle
24640 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24641 StVT.getScalarType(), NumElems*SizeRatio);
24643 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24645 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24646 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24647 for (unsigned i = 0; i != NumElems; ++i)
24648 ShuffleVec[i] = i * SizeRatio;
24650 // Can't shuffle using an illegal type.
24651 if (!TLI.isTypeLegal(WideVecVT))
24654 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24655 DAG.getUNDEF(WideVecVT),
24657 // At this point all of the data is stored at the bottom of the
24658 // register. We now need to save it to mem.
24660 // Find the largest store unit
24661 MVT StoreType = MVT::i8;
24662 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24663 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24664 MVT Tp = (MVT::SimpleValueType)tp;
24665 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24669 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24670 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24671 (64 <= NumElems * ToSz))
24672 StoreType = MVT::f64;
24674 // Bitcast the original vector into a vector of store-size units
24675 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24676 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24677 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24678 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24679 SmallVector<SDValue, 8> Chains;
24680 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24681 TLI.getPointerTy());
24682 SDValue Ptr = St->getBasePtr();
24684 // Perform one or more big stores into memory.
24685 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24686 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24687 StoreType, ShuffWide,
24688 DAG.getIntPtrConstant(i));
24689 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24690 St->getPointerInfo(), St->isVolatile(),
24691 St->isNonTemporal(), St->getAlignment());
24692 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24693 Chains.push_back(Ch);
24696 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24699 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24700 // the FP state in cases where an emms may be missing.
24701 // A preferable solution to the general problem is to figure out the right
24702 // places to insert EMMS. This qualifies as a quick hack.
24704 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24705 if (VT.getSizeInBits() != 64)
24708 const Function *F = DAG.getMachineFunction().getFunction();
24709 bool NoImplicitFloatOps = F->getAttributes().
24710 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24711 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24712 && Subtarget->hasSSE2();
24713 if ((VT.isVector() ||
24714 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24715 isa<LoadSDNode>(St->getValue()) &&
24716 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24717 St->getChain().hasOneUse() && !St->isVolatile()) {
24718 SDNode* LdVal = St->getValue().getNode();
24719 LoadSDNode *Ld = nullptr;
24720 int TokenFactorIndex = -1;
24721 SmallVector<SDValue, 8> Ops;
24722 SDNode* ChainVal = St->getChain().getNode();
24723 // Must be a store of a load. We currently handle two cases: the load
24724 // is a direct child, and it's under an intervening TokenFactor. It is
24725 // possible to dig deeper under nested TokenFactors.
24726 if (ChainVal == LdVal)
24727 Ld = cast<LoadSDNode>(St->getChain());
24728 else if (St->getValue().hasOneUse() &&
24729 ChainVal->getOpcode() == ISD::TokenFactor) {
24730 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24731 if (ChainVal->getOperand(i).getNode() == LdVal) {
24732 TokenFactorIndex = i;
24733 Ld = cast<LoadSDNode>(St->getValue());
24735 Ops.push_back(ChainVal->getOperand(i));
24739 if (!Ld || !ISD::isNormalLoad(Ld))
24742 // If this is not the MMX case, i.e. we are just turning i64 load/store
24743 // into f64 load/store, avoid the transformation if there are multiple
24744 // uses of the loaded value.
24745 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24750 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24751 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24753 if (Subtarget->is64Bit() || F64IsLegal) {
24754 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24755 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24756 Ld->getPointerInfo(), Ld->isVolatile(),
24757 Ld->isNonTemporal(), Ld->isInvariant(),
24758 Ld->getAlignment());
24759 SDValue NewChain = NewLd.getValue(1);
24760 if (TokenFactorIndex != -1) {
24761 Ops.push_back(NewChain);
24762 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24764 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24765 St->getPointerInfo(),
24766 St->isVolatile(), St->isNonTemporal(),
24767 St->getAlignment());
24770 // Otherwise, lower to two pairs of 32-bit loads / stores.
24771 SDValue LoAddr = Ld->getBasePtr();
24772 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24773 DAG.getConstant(4, MVT::i32));
24775 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24776 Ld->getPointerInfo(),
24777 Ld->isVolatile(), Ld->isNonTemporal(),
24778 Ld->isInvariant(), Ld->getAlignment());
24779 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24780 Ld->getPointerInfo().getWithOffset(4),
24781 Ld->isVolatile(), Ld->isNonTemporal(),
24783 MinAlign(Ld->getAlignment(), 4));
24785 SDValue NewChain = LoLd.getValue(1);
24786 if (TokenFactorIndex != -1) {
24787 Ops.push_back(LoLd);
24788 Ops.push_back(HiLd);
24789 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24792 LoAddr = St->getBasePtr();
24793 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24794 DAG.getConstant(4, MVT::i32));
24796 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24797 St->getPointerInfo(),
24798 St->isVolatile(), St->isNonTemporal(),
24799 St->getAlignment());
24800 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24801 St->getPointerInfo().getWithOffset(4),
24803 St->isNonTemporal(),
24804 MinAlign(St->getAlignment(), 4));
24805 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24810 /// Return 'true' if this vector operation is "horizontal"
24811 /// and return the operands for the horizontal operation in LHS and RHS. A
24812 /// horizontal operation performs the binary operation on successive elements
24813 /// of its first operand, then on successive elements of its second operand,
24814 /// returning the resulting values in a vector. For example, if
24815 /// A = < float a0, float a1, float a2, float a3 >
24817 /// B = < float b0, float b1, float b2, float b3 >
24818 /// then the result of doing a horizontal operation on A and B is
24819 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24820 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24821 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24822 /// set to A, RHS to B, and the routine returns 'true'.
24823 /// Note that the binary operation should have the property that if one of the
24824 /// operands is UNDEF then the result is UNDEF.
24825 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24826 // Look for the following pattern: if
24827 // A = < float a0, float a1, float a2, float a3 >
24828 // B = < float b0, float b1, float b2, float b3 >
24830 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24831 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24832 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24833 // which is A horizontal-op B.
24835 // At least one of the operands should be a vector shuffle.
24836 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24837 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24840 MVT VT = LHS.getSimpleValueType();
24842 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24843 "Unsupported vector type for horizontal add/sub");
24845 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24846 // operate independently on 128-bit lanes.
24847 unsigned NumElts = VT.getVectorNumElements();
24848 unsigned NumLanes = VT.getSizeInBits()/128;
24849 unsigned NumLaneElts = NumElts / NumLanes;
24850 assert((NumLaneElts % 2 == 0) &&
24851 "Vector type should have an even number of elements in each lane");
24852 unsigned HalfLaneElts = NumLaneElts/2;
24854 // View LHS in the form
24855 // LHS = VECTOR_SHUFFLE A, B, LMask
24856 // If LHS is not a shuffle then pretend it is the shuffle
24857 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24858 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24861 SmallVector<int, 16> LMask(NumElts);
24862 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24863 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24864 A = LHS.getOperand(0);
24865 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24866 B = LHS.getOperand(1);
24867 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24868 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24870 if (LHS.getOpcode() != ISD::UNDEF)
24872 for (unsigned i = 0; i != NumElts; ++i)
24876 // Likewise, view RHS in the form
24877 // RHS = VECTOR_SHUFFLE C, D, RMask
24879 SmallVector<int, 16> RMask(NumElts);
24880 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24881 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24882 C = RHS.getOperand(0);
24883 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24884 D = RHS.getOperand(1);
24885 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24886 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24888 if (RHS.getOpcode() != ISD::UNDEF)
24890 for (unsigned i = 0; i != NumElts; ++i)
24894 // Check that the shuffles are both shuffling the same vectors.
24895 if (!(A == C && B == D) && !(A == D && B == C))
24898 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24899 if (!A.getNode() && !B.getNode())
24902 // If A and B occur in reverse order in RHS, then "swap" them (which means
24903 // rewriting the mask).
24905 CommuteVectorShuffleMask(RMask, NumElts);
24907 // At this point LHS and RHS are equivalent to
24908 // LHS = VECTOR_SHUFFLE A, B, LMask
24909 // RHS = VECTOR_SHUFFLE A, B, RMask
24910 // Check that the masks correspond to performing a horizontal operation.
24911 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24912 for (unsigned i = 0; i != NumLaneElts; ++i) {
24913 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24915 // Ignore any UNDEF components.
24916 if (LIdx < 0 || RIdx < 0 ||
24917 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24918 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24921 // Check that successive elements are being operated on. If not, this is
24922 // not a horizontal operation.
24923 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24924 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24925 if (!(LIdx == Index && RIdx == Index + 1) &&
24926 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24931 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24932 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24936 /// Do target-specific dag combines on floating point adds.
24937 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24938 const X86Subtarget *Subtarget) {
24939 EVT VT = N->getValueType(0);
24940 SDValue LHS = N->getOperand(0);
24941 SDValue RHS = N->getOperand(1);
24943 // Try to synthesize horizontal adds from adds of shuffles.
24944 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24945 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24946 isHorizontalBinOp(LHS, RHS, true))
24947 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24951 /// Do target-specific dag combines on floating point subs.
24952 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24953 const X86Subtarget *Subtarget) {
24954 EVT VT = N->getValueType(0);
24955 SDValue LHS = N->getOperand(0);
24956 SDValue RHS = N->getOperand(1);
24958 // Try to synthesize horizontal subs from subs of shuffles.
24959 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24960 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24961 isHorizontalBinOp(LHS, RHS, false))
24962 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24966 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24967 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24968 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24969 // F[X]OR(0.0, x) -> x
24970 // F[X]OR(x, 0.0) -> x
24971 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24972 if (C->getValueAPF().isPosZero())
24973 return N->getOperand(1);
24974 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24975 if (C->getValueAPF().isPosZero())
24976 return N->getOperand(0);
24980 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24981 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24982 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24984 // Only perform optimizations if UnsafeMath is used.
24985 if (!DAG.getTarget().Options.UnsafeFPMath)
24988 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24989 // into FMINC and FMAXC, which are Commutative operations.
24990 unsigned NewOp = 0;
24991 switch (N->getOpcode()) {
24992 default: llvm_unreachable("unknown opcode");
24993 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24994 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24997 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24998 N->getOperand(0), N->getOperand(1));
25001 /// Do target-specific dag combines on X86ISD::FAND nodes.
25002 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25003 // FAND(0.0, x) -> 0.0
25004 // FAND(x, 0.0) -> 0.0
25005 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25006 if (C->getValueAPF().isPosZero())
25007 return N->getOperand(0);
25008 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25009 if (C->getValueAPF().isPosZero())
25010 return N->getOperand(1);
25014 /// Do target-specific dag combines on X86ISD::FANDN nodes
25015 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25016 // FANDN(x, 0.0) -> 0.0
25017 // FANDN(0.0, x) -> x
25018 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25019 if (C->getValueAPF().isPosZero())
25020 return N->getOperand(1);
25021 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25022 if (C->getValueAPF().isPosZero())
25023 return N->getOperand(1);
25027 static SDValue PerformBTCombine(SDNode *N,
25029 TargetLowering::DAGCombinerInfo &DCI) {
25030 // BT ignores high bits in the bit index operand.
25031 SDValue Op1 = N->getOperand(1);
25032 if (Op1.hasOneUse()) {
25033 unsigned BitWidth = Op1.getValueSizeInBits();
25034 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25035 APInt KnownZero, KnownOne;
25036 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25037 !DCI.isBeforeLegalizeOps());
25038 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25039 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25040 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25041 DCI.CommitTargetLoweringOpt(TLO);
25046 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25047 SDValue Op = N->getOperand(0);
25048 if (Op.getOpcode() == ISD::BITCAST)
25049 Op = Op.getOperand(0);
25050 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25051 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25052 VT.getVectorElementType().getSizeInBits() ==
25053 OpVT.getVectorElementType().getSizeInBits()) {
25054 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25059 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25060 const X86Subtarget *Subtarget) {
25061 EVT VT = N->getValueType(0);
25062 if (!VT.isVector())
25065 SDValue N0 = N->getOperand(0);
25066 SDValue N1 = N->getOperand(1);
25067 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25070 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25071 // both SSE and AVX2 since there is no sign-extended shift right
25072 // operation on a vector with 64-bit elements.
25073 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25074 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25075 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25076 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25077 SDValue N00 = N0.getOperand(0);
25079 // EXTLOAD has a better solution on AVX2,
25080 // it may be replaced with X86ISD::VSEXT node.
25081 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25082 if (!ISD::isNormalLoad(N00.getNode()))
25085 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25086 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25088 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25094 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25095 TargetLowering::DAGCombinerInfo &DCI,
25096 const X86Subtarget *Subtarget) {
25097 SDValue N0 = N->getOperand(0);
25098 EVT VT = N->getValueType(0);
25100 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25101 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25102 // This exposes the sext to the sdivrem lowering, so that it directly extends
25103 // from AH (which we otherwise need to do contortions to access).
25104 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25105 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25107 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25108 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25109 N0.getOperand(0), N0.getOperand(1));
25110 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25111 return R.getValue(1);
25114 if (!DCI.isBeforeLegalizeOps())
25117 if (!Subtarget->hasFp256())
25120 if (VT.isVector() && VT.getSizeInBits() == 256) {
25121 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25129 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25130 const X86Subtarget* Subtarget) {
25132 EVT VT = N->getValueType(0);
25134 // Let legalize expand this if it isn't a legal type yet.
25135 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25138 EVT ScalarVT = VT.getScalarType();
25139 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25140 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25143 SDValue A = N->getOperand(0);
25144 SDValue B = N->getOperand(1);
25145 SDValue C = N->getOperand(2);
25147 bool NegA = (A.getOpcode() == ISD::FNEG);
25148 bool NegB = (B.getOpcode() == ISD::FNEG);
25149 bool NegC = (C.getOpcode() == ISD::FNEG);
25151 // Negative multiplication when NegA xor NegB
25152 bool NegMul = (NegA != NegB);
25154 A = A.getOperand(0);
25156 B = B.getOperand(0);
25158 C = C.getOperand(0);
25162 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25164 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25166 return DAG.getNode(Opcode, dl, VT, A, B, C);
25169 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25170 TargetLowering::DAGCombinerInfo &DCI,
25171 const X86Subtarget *Subtarget) {
25172 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25173 // (and (i32 x86isd::setcc_carry), 1)
25174 // This eliminates the zext. This transformation is necessary because
25175 // ISD::SETCC is always legalized to i8.
25177 SDValue N0 = N->getOperand(0);
25178 EVT VT = N->getValueType(0);
25180 if (N0.getOpcode() == ISD::AND &&
25182 N0.getOperand(0).hasOneUse()) {
25183 SDValue N00 = N0.getOperand(0);
25184 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25185 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25186 if (!C || C->getZExtValue() != 1)
25188 return DAG.getNode(ISD::AND, dl, VT,
25189 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25190 N00.getOperand(0), N00.getOperand(1)),
25191 DAG.getConstant(1, VT));
25195 if (N0.getOpcode() == ISD::TRUNCATE &&
25197 N0.getOperand(0).hasOneUse()) {
25198 SDValue N00 = N0.getOperand(0);
25199 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25200 return DAG.getNode(ISD::AND, dl, VT,
25201 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25202 N00.getOperand(0), N00.getOperand(1)),
25203 DAG.getConstant(1, VT));
25206 if (VT.is256BitVector()) {
25207 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25212 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25213 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25214 // This exposes the zext to the udivrem lowering, so that it directly extends
25215 // from AH (which we otherwise need to do contortions to access).
25216 if (N0.getOpcode() == ISD::UDIVREM &&
25217 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25218 (VT == MVT::i32 || VT == MVT::i64)) {
25219 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25220 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25221 N0.getOperand(0), N0.getOperand(1));
25222 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25223 return R.getValue(1);
25229 // Optimize x == -y --> x+y == 0
25230 // x != -y --> x+y != 0
25231 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25232 const X86Subtarget* Subtarget) {
25233 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25234 SDValue LHS = N->getOperand(0);
25235 SDValue RHS = N->getOperand(1);
25236 EVT VT = N->getValueType(0);
25239 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25240 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25241 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25242 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25243 LHS.getValueType(), RHS, LHS.getOperand(1));
25244 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25245 addV, DAG.getConstant(0, addV.getValueType()), CC);
25247 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25248 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25249 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25250 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25251 RHS.getValueType(), LHS, RHS.getOperand(1));
25252 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25253 addV, DAG.getConstant(0, addV.getValueType()), CC);
25256 if (VT.getScalarType() == MVT::i1) {
25257 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25258 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25259 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25260 if (!IsSEXT0 && !IsVZero0)
25262 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25263 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25264 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25266 if (!IsSEXT1 && !IsVZero1)
25269 if (IsSEXT0 && IsVZero1) {
25270 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25271 if (CC == ISD::SETEQ)
25272 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25273 return LHS.getOperand(0);
25275 if (IsSEXT1 && IsVZero0) {
25276 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25277 if (CC == ISD::SETEQ)
25278 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25279 return RHS.getOperand(0);
25286 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25287 const X86Subtarget *Subtarget) {
25289 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25290 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25291 "X86insertps is only defined for v4x32");
25293 SDValue Ld = N->getOperand(1);
25294 if (MayFoldLoad(Ld)) {
25295 // Extract the countS bits from the immediate so we can get the proper
25296 // address when narrowing the vector load to a specific element.
25297 // When the second source op is a memory address, interps doesn't use
25298 // countS and just gets an f32 from that address.
25299 unsigned DestIndex =
25300 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25301 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25305 // Create this as a scalar to vector to match the instruction pattern.
25306 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25307 // countS bits are ignored when loading from memory on insertps, which
25308 // means we don't need to explicitly set them to 0.
25309 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25310 LoadScalarToVector, N->getOperand(2));
25313 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25314 // as "sbb reg,reg", since it can be extended without zext and produces
25315 // an all-ones bit which is more useful than 0/1 in some cases.
25316 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25319 return DAG.getNode(ISD::AND, DL, VT,
25320 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25321 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25322 DAG.getConstant(1, VT));
25323 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25324 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25325 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25326 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25329 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25330 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25331 TargetLowering::DAGCombinerInfo &DCI,
25332 const X86Subtarget *Subtarget) {
25334 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25335 SDValue EFLAGS = N->getOperand(1);
25337 if (CC == X86::COND_A) {
25338 // Try to convert COND_A into COND_B in an attempt to facilitate
25339 // materializing "setb reg".
25341 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25342 // cannot take an immediate as its first operand.
25344 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25345 EFLAGS.getValueType().isInteger() &&
25346 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25347 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25348 EFLAGS.getNode()->getVTList(),
25349 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25350 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25351 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25355 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25356 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25358 if (CC == X86::COND_B)
25359 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25363 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25364 if (Flags.getNode()) {
25365 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25366 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25372 // Optimize branch condition evaluation.
25374 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25375 TargetLowering::DAGCombinerInfo &DCI,
25376 const X86Subtarget *Subtarget) {
25378 SDValue Chain = N->getOperand(0);
25379 SDValue Dest = N->getOperand(1);
25380 SDValue EFLAGS = N->getOperand(3);
25381 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25385 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25386 if (Flags.getNode()) {
25387 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25388 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25395 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25396 SelectionDAG &DAG) {
25397 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25398 // optimize away operation when it's from a constant.
25400 // The general transformation is:
25401 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25402 // AND(VECTOR_CMP(x,y), constant2)
25403 // constant2 = UNARYOP(constant)
25405 // Early exit if this isn't a vector operation, the operand of the
25406 // unary operation isn't a bitwise AND, or if the sizes of the operations
25407 // aren't the same.
25408 EVT VT = N->getValueType(0);
25409 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25410 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25411 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25414 // Now check that the other operand of the AND is a constant. We could
25415 // make the transformation for non-constant splats as well, but it's unclear
25416 // that would be a benefit as it would not eliminate any operations, just
25417 // perform one more step in scalar code before moving to the vector unit.
25418 if (BuildVectorSDNode *BV =
25419 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25420 // Bail out if the vector isn't a constant.
25421 if (!BV->isConstant())
25424 // Everything checks out. Build up the new and improved node.
25426 EVT IntVT = BV->getValueType(0);
25427 // Create a new constant of the appropriate type for the transformed
25429 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25430 // The AND node needs bitcasts to/from an integer vector type around it.
25431 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25432 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25433 N->getOperand(0)->getOperand(0), MaskConst);
25434 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25441 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25442 const X86TargetLowering *XTLI) {
25443 // First try to optimize away the conversion entirely when it's
25444 // conditionally from a constant. Vectors only.
25445 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25446 if (Res != SDValue())
25449 // Now move on to more general possibilities.
25450 SDValue Op0 = N->getOperand(0);
25451 EVT InVT = Op0->getValueType(0);
25453 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25454 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25456 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25457 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25458 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25461 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25462 // a 32-bit target where SSE doesn't support i64->FP operations.
25463 if (Op0.getOpcode() == ISD::LOAD) {
25464 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25465 EVT VT = Ld->getValueType(0);
25466 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25467 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25468 !XTLI->getSubtarget()->is64Bit() &&
25470 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25471 Ld->getChain(), Op0, DAG);
25472 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25479 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25480 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25481 X86TargetLowering::DAGCombinerInfo &DCI) {
25482 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25483 // the result is either zero or one (depending on the input carry bit).
25484 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25485 if (X86::isZeroNode(N->getOperand(0)) &&
25486 X86::isZeroNode(N->getOperand(1)) &&
25487 // We don't have a good way to replace an EFLAGS use, so only do this when
25489 SDValue(N, 1).use_empty()) {
25491 EVT VT = N->getValueType(0);
25492 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25493 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25494 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25495 DAG.getConstant(X86::COND_B,MVT::i8),
25497 DAG.getConstant(1, VT));
25498 return DCI.CombineTo(N, Res1, CarryOut);
25504 // fold (add Y, (sete X, 0)) -> adc 0, Y
25505 // (add Y, (setne X, 0)) -> sbb -1, Y
25506 // (sub (sete X, 0), Y) -> sbb 0, Y
25507 // (sub (setne X, 0), Y) -> adc -1, Y
25508 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25511 // Look through ZExts.
25512 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25513 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25516 SDValue SetCC = Ext.getOperand(0);
25517 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25520 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25521 if (CC != X86::COND_E && CC != X86::COND_NE)
25524 SDValue Cmp = SetCC.getOperand(1);
25525 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25526 !X86::isZeroNode(Cmp.getOperand(1)) ||
25527 !Cmp.getOperand(0).getValueType().isInteger())
25530 SDValue CmpOp0 = Cmp.getOperand(0);
25531 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25532 DAG.getConstant(1, CmpOp0.getValueType()));
25534 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25535 if (CC == X86::COND_NE)
25536 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25537 DL, OtherVal.getValueType(), OtherVal,
25538 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25539 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25540 DL, OtherVal.getValueType(), OtherVal,
25541 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25544 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25545 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25546 const X86Subtarget *Subtarget) {
25547 EVT VT = N->getValueType(0);
25548 SDValue Op0 = N->getOperand(0);
25549 SDValue Op1 = N->getOperand(1);
25551 // Try to synthesize horizontal adds from adds of shuffles.
25552 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25553 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25554 isHorizontalBinOp(Op0, Op1, true))
25555 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25557 return OptimizeConditionalInDecrement(N, DAG);
25560 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25561 const X86Subtarget *Subtarget) {
25562 SDValue Op0 = N->getOperand(0);
25563 SDValue Op1 = N->getOperand(1);
25565 // X86 can't encode an immediate LHS of a sub. See if we can push the
25566 // negation into a preceding instruction.
25567 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25568 // If the RHS of the sub is a XOR with one use and a constant, invert the
25569 // immediate. Then add one to the LHS of the sub so we can turn
25570 // X-Y -> X+~Y+1, saving one register.
25571 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25572 isa<ConstantSDNode>(Op1.getOperand(1))) {
25573 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25574 EVT VT = Op0.getValueType();
25575 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25577 DAG.getConstant(~XorC, VT));
25578 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25579 DAG.getConstant(C->getAPIntValue()+1, VT));
25583 // Try to synthesize horizontal adds from adds of shuffles.
25584 EVT VT = N->getValueType(0);
25585 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25586 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25587 isHorizontalBinOp(Op0, Op1, true))
25588 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25590 return OptimizeConditionalInDecrement(N, DAG);
25593 /// performVZEXTCombine - Performs build vector combines
25594 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25595 TargetLowering::DAGCombinerInfo &DCI,
25596 const X86Subtarget *Subtarget) {
25598 MVT VT = N->getSimpleValueType(0);
25599 SDValue Op = N->getOperand(0);
25600 MVT OpVT = Op.getSimpleValueType();
25601 MVT OpEltVT = OpVT.getVectorElementType();
25602 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25604 // (vzext (bitcast (vzext (x)) -> (vzext x)
25606 while (V.getOpcode() == ISD::BITCAST)
25607 V = V.getOperand(0);
25609 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25610 MVT InnerVT = V.getSimpleValueType();
25611 MVT InnerEltVT = InnerVT.getVectorElementType();
25613 // If the element sizes match exactly, we can just do one larger vzext. This
25614 // is always an exact type match as vzext operates on integer types.
25615 if (OpEltVT == InnerEltVT) {
25616 assert(OpVT == InnerVT && "Types must match for vzext!");
25617 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25620 // The only other way we can combine them is if only a single element of the
25621 // inner vzext is used in the input to the outer vzext.
25622 if (InnerEltVT.getSizeInBits() < InputBits)
25625 // In this case, the inner vzext is completely dead because we're going to
25626 // only look at bits inside of the low element. Just do the outer vzext on
25627 // a bitcast of the input to the inner.
25628 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25629 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25632 // Check if we can bypass extracting and re-inserting an element of an input
25633 // vector. Essentialy:
25634 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25635 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25636 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25637 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25638 SDValue ExtractedV = V.getOperand(0);
25639 SDValue OrigV = ExtractedV.getOperand(0);
25640 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25641 if (ExtractIdx->getZExtValue() == 0) {
25642 MVT OrigVT = OrigV.getSimpleValueType();
25643 // Extract a subvector if necessary...
25644 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25645 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25646 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25647 OrigVT.getVectorNumElements() / Ratio);
25648 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25649 DAG.getIntPtrConstant(0));
25651 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25652 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25659 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25660 DAGCombinerInfo &DCI) const {
25661 SelectionDAG &DAG = DCI.DAG;
25662 switch (N->getOpcode()) {
25664 case ISD::EXTRACT_VECTOR_ELT:
25665 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25668 case X86ISD::SHRUNKBLEND:
25669 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25670 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25671 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25672 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25673 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25674 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25677 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25678 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25679 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25680 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25681 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25682 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25683 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25684 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25685 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25687 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25689 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25690 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25691 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25692 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25693 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25694 case ISD::ANY_EXTEND:
25695 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25696 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25697 case ISD::SIGN_EXTEND_INREG:
25698 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25699 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25700 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25701 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25702 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25703 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25704 case X86ISD::SHUFP: // Handle all target specific shuffles
25705 case X86ISD::PALIGNR:
25706 case X86ISD::UNPCKH:
25707 case X86ISD::UNPCKL:
25708 case X86ISD::MOVHLPS:
25709 case X86ISD::MOVLHPS:
25710 case X86ISD::PSHUFB:
25711 case X86ISD::PSHUFD:
25712 case X86ISD::PSHUFHW:
25713 case X86ISD::PSHUFLW:
25714 case X86ISD::MOVSS:
25715 case X86ISD::MOVSD:
25716 case X86ISD::VPERMILPI:
25717 case X86ISD::VPERM2X128:
25718 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25719 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25720 case ISD::INTRINSIC_WO_CHAIN:
25721 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25722 case X86ISD::INSERTPS:
25723 return PerformINSERTPSCombine(N, DAG, Subtarget);
25724 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25730 /// isTypeDesirableForOp - Return true if the target has native support for
25731 /// the specified value type and it is 'desirable' to use the type for the
25732 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25733 /// instruction encodings are longer and some i16 instructions are slow.
25734 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25735 if (!isTypeLegal(VT))
25737 if (VT != MVT::i16)
25744 case ISD::SIGN_EXTEND:
25745 case ISD::ZERO_EXTEND:
25746 case ISD::ANY_EXTEND:
25759 /// IsDesirableToPromoteOp - This method query the target whether it is
25760 /// beneficial for dag combiner to promote the specified node. If true, it
25761 /// should return the desired promotion type by reference.
25762 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25763 EVT VT = Op.getValueType();
25764 if (VT != MVT::i16)
25767 bool Promote = false;
25768 bool Commute = false;
25769 switch (Op.getOpcode()) {
25772 LoadSDNode *LD = cast<LoadSDNode>(Op);
25773 // If the non-extending load has a single use and it's not live out, then it
25774 // might be folded.
25775 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25776 Op.hasOneUse()*/) {
25777 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25778 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25779 // The only case where we'd want to promote LOAD (rather then it being
25780 // promoted as an operand is when it's only use is liveout.
25781 if (UI->getOpcode() != ISD::CopyToReg)
25788 case ISD::SIGN_EXTEND:
25789 case ISD::ZERO_EXTEND:
25790 case ISD::ANY_EXTEND:
25795 SDValue N0 = Op.getOperand(0);
25796 // Look out for (store (shl (load), x)).
25797 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25810 SDValue N0 = Op.getOperand(0);
25811 SDValue N1 = Op.getOperand(1);
25812 if (!Commute && MayFoldLoad(N1))
25814 // Avoid disabling potential load folding opportunities.
25815 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25817 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25827 //===----------------------------------------------------------------------===//
25828 // X86 Inline Assembly Support
25829 //===----------------------------------------------------------------------===//
25832 // Helper to match a string separated by whitespace.
25833 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25834 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25836 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25837 StringRef piece(*args[i]);
25838 if (!s.startswith(piece)) // Check if the piece matches.
25841 s = s.substr(piece.size());
25842 StringRef::size_type pos = s.find_first_not_of(" \t");
25843 if (pos == 0) // We matched a prefix.
25851 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25854 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25856 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25857 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25858 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25859 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25861 if (AsmPieces.size() == 3)
25863 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25870 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25871 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25873 std::string AsmStr = IA->getAsmString();
25875 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25876 if (!Ty || Ty->getBitWidth() % 16 != 0)
25879 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25880 SmallVector<StringRef, 4> AsmPieces;
25881 SplitString(AsmStr, AsmPieces, ";\n");
25883 switch (AsmPieces.size()) {
25884 default: return false;
25886 // FIXME: this should verify that we are targeting a 486 or better. If not,
25887 // we will turn this bswap into something that will be lowered to logical
25888 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25889 // lower so don't worry about this.
25891 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25892 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25893 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25894 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25895 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25896 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25897 // No need to check constraints, nothing other than the equivalent of
25898 // "=r,0" would be valid here.
25899 return IntrinsicLowering::LowerToByteSwap(CI);
25902 // rorw $$8, ${0:w} --> llvm.bswap.i16
25903 if (CI->getType()->isIntegerTy(16) &&
25904 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25905 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25906 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25908 const std::string &ConstraintsStr = IA->getConstraintString();
25909 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25910 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25911 if (clobbersFlagRegisters(AsmPieces))
25912 return IntrinsicLowering::LowerToByteSwap(CI);
25916 if (CI->getType()->isIntegerTy(32) &&
25917 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25918 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25919 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25920 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25922 const std::string &ConstraintsStr = IA->getConstraintString();
25923 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25924 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25925 if (clobbersFlagRegisters(AsmPieces))
25926 return IntrinsicLowering::LowerToByteSwap(CI);
25929 if (CI->getType()->isIntegerTy(64)) {
25930 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25931 if (Constraints.size() >= 2 &&
25932 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25933 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25934 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25935 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25936 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25937 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25938 return IntrinsicLowering::LowerToByteSwap(CI);
25946 /// getConstraintType - Given a constraint letter, return the type of
25947 /// constraint it is for this target.
25948 X86TargetLowering::ConstraintType
25949 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25950 if (Constraint.size() == 1) {
25951 switch (Constraint[0]) {
25962 return C_RegisterClass;
25986 return TargetLowering::getConstraintType(Constraint);
25989 /// Examine constraint type and operand type and determine a weight value.
25990 /// This object must already have been set up with the operand type
25991 /// and the current alternative constraint selected.
25992 TargetLowering::ConstraintWeight
25993 X86TargetLowering::getSingleConstraintMatchWeight(
25994 AsmOperandInfo &info, const char *constraint) const {
25995 ConstraintWeight weight = CW_Invalid;
25996 Value *CallOperandVal = info.CallOperandVal;
25997 // If we don't have a value, we can't do a match,
25998 // but allow it at the lowest weight.
25999 if (!CallOperandVal)
26001 Type *type = CallOperandVal->getType();
26002 // Look at the constraint type.
26003 switch (*constraint) {
26005 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26016 if (CallOperandVal->getType()->isIntegerTy())
26017 weight = CW_SpecificReg;
26022 if (type->isFloatingPointTy())
26023 weight = CW_SpecificReg;
26026 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26027 weight = CW_SpecificReg;
26031 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26032 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26033 weight = CW_Register;
26036 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26037 if (C->getZExtValue() <= 31)
26038 weight = CW_Constant;
26042 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26043 if (C->getZExtValue() <= 63)
26044 weight = CW_Constant;
26048 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26049 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26050 weight = CW_Constant;
26054 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26055 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26056 weight = CW_Constant;
26060 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26061 if (C->getZExtValue() <= 3)
26062 weight = CW_Constant;
26066 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26067 if (C->getZExtValue() <= 0xff)
26068 weight = CW_Constant;
26073 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26074 weight = CW_Constant;
26078 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26079 if ((C->getSExtValue() >= -0x80000000LL) &&
26080 (C->getSExtValue() <= 0x7fffffffLL))
26081 weight = CW_Constant;
26085 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26086 if (C->getZExtValue() <= 0xffffffff)
26087 weight = CW_Constant;
26094 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26095 /// with another that has more specific requirements based on the type of the
26096 /// corresponding operand.
26097 const char *X86TargetLowering::
26098 LowerXConstraint(EVT ConstraintVT) const {
26099 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26100 // 'f' like normal targets.
26101 if (ConstraintVT.isFloatingPoint()) {
26102 if (Subtarget->hasSSE2())
26104 if (Subtarget->hasSSE1())
26108 return TargetLowering::LowerXConstraint(ConstraintVT);
26111 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26112 /// vector. If it is invalid, don't add anything to Ops.
26113 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26114 std::string &Constraint,
26115 std::vector<SDValue>&Ops,
26116 SelectionDAG &DAG) const {
26119 // Only support length 1 constraints for now.
26120 if (Constraint.length() > 1) return;
26122 char ConstraintLetter = Constraint[0];
26123 switch (ConstraintLetter) {
26126 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26127 if (C->getZExtValue() <= 31) {
26128 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26134 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26135 if (C->getZExtValue() <= 63) {
26136 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26143 if (isInt<8>(C->getSExtValue())) {
26144 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26151 if (C->getZExtValue() <= 255) {
26152 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26158 // 32-bit signed value
26159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26160 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26161 C->getSExtValue())) {
26162 // Widen to 64 bits here to get it sign extended.
26163 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26166 // FIXME gcc accepts some relocatable values here too, but only in certain
26167 // memory models; it's complicated.
26172 // 32-bit unsigned value
26173 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26174 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26175 C->getZExtValue())) {
26176 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26180 // FIXME gcc accepts some relocatable values here too, but only in certain
26181 // memory models; it's complicated.
26185 // Literal immediates are always ok.
26186 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26187 // Widen to 64 bits here to get it sign extended.
26188 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26192 // In any sort of PIC mode addresses need to be computed at runtime by
26193 // adding in a register or some sort of table lookup. These can't
26194 // be used as immediates.
26195 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26198 // If we are in non-pic codegen mode, we allow the address of a global (with
26199 // an optional displacement) to be used with 'i'.
26200 GlobalAddressSDNode *GA = nullptr;
26201 int64_t Offset = 0;
26203 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26205 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26206 Offset += GA->getOffset();
26208 } else if (Op.getOpcode() == ISD::ADD) {
26209 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26210 Offset += C->getZExtValue();
26211 Op = Op.getOperand(0);
26214 } else if (Op.getOpcode() == ISD::SUB) {
26215 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26216 Offset += -C->getZExtValue();
26217 Op = Op.getOperand(0);
26222 // Otherwise, this isn't something we can handle, reject it.
26226 const GlobalValue *GV = GA->getGlobal();
26227 // If we require an extra load to get this address, as in PIC mode, we
26228 // can't accept it.
26229 if (isGlobalStubReference(
26230 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26233 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26234 GA->getValueType(0), Offset);
26239 if (Result.getNode()) {
26240 Ops.push_back(Result);
26243 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26246 std::pair<unsigned, const TargetRegisterClass*>
26247 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26249 // First, see if this is a constraint that directly corresponds to an LLVM
26251 if (Constraint.size() == 1) {
26252 // GCC Constraint Letters
26253 switch (Constraint[0]) {
26255 // TODO: Slight differences here in allocation order and leaving
26256 // RIP in the class. Do they matter any more here than they do
26257 // in the normal allocation?
26258 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26259 if (Subtarget->is64Bit()) {
26260 if (VT == MVT::i32 || VT == MVT::f32)
26261 return std::make_pair(0U, &X86::GR32RegClass);
26262 if (VT == MVT::i16)
26263 return std::make_pair(0U, &X86::GR16RegClass);
26264 if (VT == MVT::i8 || VT == MVT::i1)
26265 return std::make_pair(0U, &X86::GR8RegClass);
26266 if (VT == MVT::i64 || VT == MVT::f64)
26267 return std::make_pair(0U, &X86::GR64RegClass);
26270 // 32-bit fallthrough
26271 case 'Q': // Q_REGS
26272 if (VT == MVT::i32 || VT == MVT::f32)
26273 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26274 if (VT == MVT::i16)
26275 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26276 if (VT == MVT::i8 || VT == MVT::i1)
26277 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26278 if (VT == MVT::i64)
26279 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26281 case 'r': // GENERAL_REGS
26282 case 'l': // INDEX_REGS
26283 if (VT == MVT::i8 || VT == MVT::i1)
26284 return std::make_pair(0U, &X86::GR8RegClass);
26285 if (VT == MVT::i16)
26286 return std::make_pair(0U, &X86::GR16RegClass);
26287 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26288 return std::make_pair(0U, &X86::GR32RegClass);
26289 return std::make_pair(0U, &X86::GR64RegClass);
26290 case 'R': // LEGACY_REGS
26291 if (VT == MVT::i8 || VT == MVT::i1)
26292 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26293 if (VT == MVT::i16)
26294 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26295 if (VT == MVT::i32 || !Subtarget->is64Bit())
26296 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26297 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26298 case 'f': // FP Stack registers.
26299 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26300 // value to the correct fpstack register class.
26301 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26302 return std::make_pair(0U, &X86::RFP32RegClass);
26303 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26304 return std::make_pair(0U, &X86::RFP64RegClass);
26305 return std::make_pair(0U, &X86::RFP80RegClass);
26306 case 'y': // MMX_REGS if MMX allowed.
26307 if (!Subtarget->hasMMX()) break;
26308 return std::make_pair(0U, &X86::VR64RegClass);
26309 case 'Y': // SSE_REGS if SSE2 allowed
26310 if (!Subtarget->hasSSE2()) break;
26312 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26313 if (!Subtarget->hasSSE1()) break;
26315 switch (VT.SimpleTy) {
26317 // Scalar SSE types.
26320 return std::make_pair(0U, &X86::FR32RegClass);
26323 return std::make_pair(0U, &X86::FR64RegClass);
26331 return std::make_pair(0U, &X86::VR128RegClass);
26339 return std::make_pair(0U, &X86::VR256RegClass);
26344 return std::make_pair(0U, &X86::VR512RegClass);
26350 // Use the default implementation in TargetLowering to convert the register
26351 // constraint into a member of a register class.
26352 std::pair<unsigned, const TargetRegisterClass*> Res;
26353 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26355 // Not found as a standard register?
26357 // Map st(0) -> st(7) -> ST0
26358 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26359 tolower(Constraint[1]) == 's' &&
26360 tolower(Constraint[2]) == 't' &&
26361 Constraint[3] == '(' &&
26362 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26363 Constraint[5] == ')' &&
26364 Constraint[6] == '}') {
26366 Res.first = X86::FP0+Constraint[4]-'0';
26367 Res.second = &X86::RFP80RegClass;
26371 // GCC allows "st(0)" to be called just plain "st".
26372 if (StringRef("{st}").equals_lower(Constraint)) {
26373 Res.first = X86::FP0;
26374 Res.second = &X86::RFP80RegClass;
26379 if (StringRef("{flags}").equals_lower(Constraint)) {
26380 Res.first = X86::EFLAGS;
26381 Res.second = &X86::CCRRegClass;
26385 // 'A' means EAX + EDX.
26386 if (Constraint == "A") {
26387 Res.first = X86::EAX;
26388 Res.second = &X86::GR32_ADRegClass;
26394 // Otherwise, check to see if this is a register class of the wrong value
26395 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26396 // turn into {ax},{dx}.
26397 if (Res.second->hasType(VT))
26398 return Res; // Correct type already, nothing to do.
26400 // All of the single-register GCC register classes map their values onto
26401 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26402 // really want an 8-bit or 32-bit register, map to the appropriate register
26403 // class and return the appropriate register.
26404 if (Res.second == &X86::GR16RegClass) {
26405 if (VT == MVT::i8 || VT == MVT::i1) {
26406 unsigned DestReg = 0;
26407 switch (Res.first) {
26409 case X86::AX: DestReg = X86::AL; break;
26410 case X86::DX: DestReg = X86::DL; break;
26411 case X86::CX: DestReg = X86::CL; break;
26412 case X86::BX: DestReg = X86::BL; break;
26415 Res.first = DestReg;
26416 Res.second = &X86::GR8RegClass;
26418 } else if (VT == MVT::i32 || VT == MVT::f32) {
26419 unsigned DestReg = 0;
26420 switch (Res.first) {
26422 case X86::AX: DestReg = X86::EAX; break;
26423 case X86::DX: DestReg = X86::EDX; break;
26424 case X86::CX: DestReg = X86::ECX; break;
26425 case X86::BX: DestReg = X86::EBX; break;
26426 case X86::SI: DestReg = X86::ESI; break;
26427 case X86::DI: DestReg = X86::EDI; break;
26428 case X86::BP: DestReg = X86::EBP; break;
26429 case X86::SP: DestReg = X86::ESP; break;
26432 Res.first = DestReg;
26433 Res.second = &X86::GR32RegClass;
26435 } else if (VT == MVT::i64 || VT == MVT::f64) {
26436 unsigned DestReg = 0;
26437 switch (Res.first) {
26439 case X86::AX: DestReg = X86::RAX; break;
26440 case X86::DX: DestReg = X86::RDX; break;
26441 case X86::CX: DestReg = X86::RCX; break;
26442 case X86::BX: DestReg = X86::RBX; break;
26443 case X86::SI: DestReg = X86::RSI; break;
26444 case X86::DI: DestReg = X86::RDI; break;
26445 case X86::BP: DestReg = X86::RBP; break;
26446 case X86::SP: DestReg = X86::RSP; break;
26449 Res.first = DestReg;
26450 Res.second = &X86::GR64RegClass;
26453 } else if (Res.second == &X86::FR32RegClass ||
26454 Res.second == &X86::FR64RegClass ||
26455 Res.second == &X86::VR128RegClass ||
26456 Res.second == &X86::VR256RegClass ||
26457 Res.second == &X86::FR32XRegClass ||
26458 Res.second == &X86::FR64XRegClass ||
26459 Res.second == &X86::VR128XRegClass ||
26460 Res.second == &X86::VR256XRegClass ||
26461 Res.second == &X86::VR512RegClass) {
26462 // Handle references to XMM physical registers that got mapped into the
26463 // wrong class. This can happen with constraints like {xmm0} where the
26464 // target independent register mapper will just pick the first match it can
26465 // find, ignoring the required type.
26467 if (VT == MVT::f32 || VT == MVT::i32)
26468 Res.second = &X86::FR32RegClass;
26469 else if (VT == MVT::f64 || VT == MVT::i64)
26470 Res.second = &X86::FR64RegClass;
26471 else if (X86::VR128RegClass.hasType(VT))
26472 Res.second = &X86::VR128RegClass;
26473 else if (X86::VR256RegClass.hasType(VT))
26474 Res.second = &X86::VR256RegClass;
26475 else if (X86::VR512RegClass.hasType(VT))
26476 Res.second = &X86::VR512RegClass;
26482 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26484 // Scaling factors are not free at all.
26485 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26486 // will take 2 allocations in the out of order engine instead of 1
26487 // for plain addressing mode, i.e. inst (reg1).
26489 // vaddps (%rsi,%drx), %ymm0, %ymm1
26490 // Requires two allocations (one for the load, one for the computation)
26492 // vaddps (%rsi), %ymm0, %ymm1
26493 // Requires just 1 allocation, i.e., freeing allocations for other operations
26494 // and having less micro operations to execute.
26496 // For some X86 architectures, this is even worse because for instance for
26497 // stores, the complex addressing mode forces the instruction to use the
26498 // "load" ports instead of the dedicated "store" port.
26499 // E.g., on Haswell:
26500 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26501 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26502 if (isLegalAddressingMode(AM, Ty))
26503 // Scale represents reg2 * scale, thus account for 1
26504 // as soon as we use a second register.
26505 return AM.Scale != 0;
26509 bool X86TargetLowering::isTargetFTOL() const {
26510 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();