1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!Subtarget->useSoftFloat()) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!Subtarget->useSoftFloat()) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!Subtarget->useSoftFloat()) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
835 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
836 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
837 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
845 // Only provide customized ctpop vector bit twiddling for vector types we
846 // know to perform better than using the popcnt instructions on each vector
847 // element. If popcnt isn't supported, always provide the custom version.
848 if (!Subtarget->hasPOPCNT()) {
849 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
853 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
854 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
855 MVT VT = (MVT::SimpleValueType)i;
856 // Do not attempt to custom lower non-power-of-2 vectors
857 if (!isPowerOf2_32(VT.getVectorNumElements()))
859 // Do not attempt to custom lower non-128-bit vectors
860 if (!VT.is128BitVector())
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::VSELECT, VT, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
868 // We support custom legalizing of sext and anyext loads for specific
869 // memory vector types which we can load as a scalar (or sequence of
870 // scalars) and extend in-register to a legal 128-bit vector type. For sext
871 // loads these must work with a single scalar load.
872 for (MVT VT : MVT::integer_vector_valuetypes()) {
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
889 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to promote non-128-bit vectors
903 if (!VT.is128BitVector())
906 setOperationAction(ISD::AND, VT, Promote);
907 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
908 setOperationAction(ISD::OR, VT, Promote);
909 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
910 setOperationAction(ISD::XOR, VT, Promote);
911 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
912 setOperationAction(ISD::LOAD, VT, Promote);
913 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
914 setOperationAction(ISD::SELECT, VT, Promote);
915 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
918 // Custom lower v2i64 and v2f64 selects.
919 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
920 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
921 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
922 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
924 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 // FIXME: Do we need to handle scalar-to-vector here?
955 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
957 // We directly match byte blends in the backend as they match the VSELECT
959 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
961 // SSE41 brings specific instructions for doing vector sign extend even in
962 // cases where we don't have SRA.
963 for (MVT VT : MVT::integer_vector_valuetypes()) {
964 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
965 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
966 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
969 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
970 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
971 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
972 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
973 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
974 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
977 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
978 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
979 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
980 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
981 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
984 // i8 and i16 vectors are custom because the source register and source
985 // source memory operand types are not the same width. f32 vectors are
986 // custom since the immediate controlling the insert encodes additional
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
994 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
998 // FIXME: these should be Legal, but that's only for the case where
999 // the index is constant. For now custom expand to deal with that.
1000 if (Subtarget->is64Bit()) {
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1006 if (Subtarget->hasSSE2()) {
1007 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1008 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1010 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1011 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1013 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1014 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1016 // In the customized shift lowering, the legal cases in AVX2 will be
1018 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1019 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1021 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1022 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1024 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1027 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1028 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1029 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1030 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1031 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1032 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1033 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1035 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1036 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1037 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1039 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1047 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1049 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1050 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1052 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1058 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1060 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1061 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1062 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1063 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1065 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1066 // even though v8i16 is a legal type.
1067 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1068 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1071 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1072 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1073 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1075 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1076 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1078 for (MVT VT : MVT::fp_vector_valuetypes())
1079 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1081 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1084 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1085 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1087 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1088 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1090 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1091 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1092 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1093 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1095 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1096 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1097 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1099 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1100 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1101 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1103 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1104 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1105 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1106 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1107 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1108 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1109 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1110 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1112 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1113 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1114 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1115 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1116 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FMA, MVT::f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::f64, Legal);
1121 if (Subtarget->hasInt256()) {
1122 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1123 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1124 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1125 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1127 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1128 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1129 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1130 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1132 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1133 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1134 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1135 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1137 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1139 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1140 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1142 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1143 // when we have a 256bit-wide blend with immediate.
1144 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1146 // Only provide customized ctpop vector bit twiddling for vector types we
1147 // know to perform better than using the popcnt instructions on each
1148 // vector element. If popcnt isn't supported, always provide the custom
1150 if (!Subtarget->hasPOPCNT())
1151 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1153 // Custom CTPOP always performs better on natively supported v8i32
1154 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1156 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1157 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1158 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1159 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1160 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1161 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1162 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1164 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1165 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1166 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1167 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1168 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1169 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1171 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1172 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1173 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1174 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1177 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1181 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1182 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1183 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1184 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1187 // In the customized shift lowering, the legal cases in AVX2 will be
1189 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1190 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1192 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1195 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1197 // Custom lower several nodes for 256-bit types.
1198 for (MVT VT : MVT::vector_valuetypes()) {
1199 if (VT.getScalarSizeInBits() >= 32) {
1200 setOperationAction(ISD::MLOAD, VT, Legal);
1201 setOperationAction(ISD::MSTORE, VT, Legal);
1203 // Extract subvector is special because the value type
1204 // (result) is 128-bit but the source is 256-bit wide.
1205 if (VT.is128BitVector()) {
1206 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1208 // Do not attempt to custom lower other non-256-bit vectors
1209 if (!VT.is256BitVector())
1212 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1213 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1214 setOperationAction(ISD::VSELECT, VT, Custom);
1215 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1216 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1217 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1218 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1219 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1222 if (Subtarget->hasInt256())
1223 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1226 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1227 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1228 MVT VT = (MVT::SimpleValueType)i;
1230 // Do not attempt to promote non-256-bit vectors
1231 if (!VT.is256BitVector())
1234 setOperationAction(ISD::AND, VT, Promote);
1235 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1236 setOperationAction(ISD::OR, VT, Promote);
1237 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1238 setOperationAction(ISD::XOR, VT, Promote);
1239 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1240 setOperationAction(ISD::LOAD, VT, Promote);
1241 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1242 setOperationAction(ISD::SELECT, VT, Promote);
1243 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1247 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1248 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1249 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1250 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1251 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1253 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1254 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1255 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1257 for (MVT VT : MVT::fp_vector_valuetypes())
1258 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1260 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1261 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1262 setOperationAction(ISD::XOR, MVT::i1, Legal);
1263 setOperationAction(ISD::OR, MVT::i1, Legal);
1264 setOperationAction(ISD::AND, MVT::i1, Legal);
1265 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1266 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1267 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1268 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1269 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1271 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1272 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1273 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1274 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1275 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1276 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1278 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1279 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1280 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1281 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1282 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1283 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1284 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1285 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1287 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1288 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1289 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1290 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1291 if (Subtarget->is64Bit()) {
1292 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1293 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1294 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1295 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1297 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1298 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1299 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1300 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1301 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1302 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1303 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1304 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1305 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1306 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1307 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1308 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1309 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1310 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1311 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1312 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1314 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1315 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1316 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1317 if (Subtarget->hasDQI()) {
1318 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1319 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1321 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1322 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1323 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1324 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1325 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1326 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1327 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1328 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1329 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1330 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1331 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1332 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1333 if (Subtarget->hasDQI()) {
1334 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1335 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1337 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1339 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1341 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1343 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1348 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1349 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1350 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1351 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1352 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1354 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1355 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1357 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1359 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1360 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1361 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1362 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1363 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1364 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1365 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1366 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1367 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1368 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1371 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1372 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1374 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1375 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1377 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1379 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1380 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1382 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1383 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1385 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1386 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1388 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1389 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1390 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1391 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1392 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1393 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1395 if (Subtarget->hasCDI()) {
1396 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1397 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1401 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1402 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1404 // Custom lower several nodes.
1405 for (MVT VT : MVT::vector_valuetypes()) {
1406 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1408 setOperationAction(ISD::AND, VT, Legal);
1409 setOperationAction(ISD::OR, VT, Legal);
1410 setOperationAction(ISD::XOR, VT, Legal);
1412 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1413 setOperationAction(ISD::MGATHER, VT, Custom);
1414 setOperationAction(ISD::MSCATTER, VT, Custom);
1416 // Extract subvector is special because the value type
1417 // (result) is 256/128-bit but the source is 512-bit wide.
1418 if (VT.is128BitVector() || VT.is256BitVector()) {
1419 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1421 if (VT.getVectorElementType() == MVT::i1)
1422 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1424 // Do not attempt to custom lower other non-512-bit vectors
1425 if (!VT.is512BitVector())
1428 if (EltSize >= 32) {
1429 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1430 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1431 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1432 setOperationAction(ISD::VSELECT, VT, Legal);
1433 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1434 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1435 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1436 setOperationAction(ISD::MLOAD, VT, Legal);
1437 setOperationAction(ISD::MSTORE, VT, Legal);
1440 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1441 MVT VT = (MVT::SimpleValueType)i;
1443 // Do not attempt to promote non-512-bit vectors.
1444 if (!VT.is512BitVector())
1447 setOperationAction(ISD::SELECT, VT, Promote);
1448 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1452 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1453 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1454 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1456 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1457 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1459 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1460 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1463 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1464 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1465 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1466 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1467 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1468 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1470 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1471 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1475 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1476 const MVT VT = (MVT::SimpleValueType)i;
1478 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1480 // Do not attempt to promote non-512-bit vectors.
1481 if (!VT.is512BitVector())
1485 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1486 setOperationAction(ISD::VSELECT, VT, Legal);
1491 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1492 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1493 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1495 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1496 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1497 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1498 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1499 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1500 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1501 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1502 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1507 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1510 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1511 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1514 // We want to custom lower some of our intrinsics.
1515 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1516 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1517 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1518 if (!Subtarget->is64Bit())
1519 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1521 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1522 // handle type legalization for these operations here.
1524 // FIXME: We really should do custom legalization for addition and
1525 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1526 // than generic legalization for 64-bit multiplication-with-overflow, though.
1527 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1528 // Add/Sub/Mul with overflow operations are custom lowered.
1530 setOperationAction(ISD::SADDO, VT, Custom);
1531 setOperationAction(ISD::UADDO, VT, Custom);
1532 setOperationAction(ISD::SSUBO, VT, Custom);
1533 setOperationAction(ISD::USUBO, VT, Custom);
1534 setOperationAction(ISD::SMULO, VT, Custom);
1535 setOperationAction(ISD::UMULO, VT, Custom);
1539 if (!Subtarget->is64Bit()) {
1540 // These libcalls are not available in 32-bit.
1541 setLibcallName(RTLIB::SHL_I128, nullptr);
1542 setLibcallName(RTLIB::SRL_I128, nullptr);
1543 setLibcallName(RTLIB::SRA_I128, nullptr);
1546 // Combine sin / cos into one node or libcall if possible.
1547 if (Subtarget->hasSinCos()) {
1548 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1549 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1550 if (Subtarget->isTargetDarwin()) {
1551 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1552 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1553 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1554 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1558 if (Subtarget->isTargetWin64()) {
1559 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1560 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1561 setOperationAction(ISD::SREM, MVT::i128, Custom);
1562 setOperationAction(ISD::UREM, MVT::i128, Custom);
1563 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1564 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1567 // We have target-specific dag combine patterns for the following nodes:
1568 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1569 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1570 setTargetDAGCombine(ISD::BITCAST);
1571 setTargetDAGCombine(ISD::VSELECT);
1572 setTargetDAGCombine(ISD::SELECT);
1573 setTargetDAGCombine(ISD::SHL);
1574 setTargetDAGCombine(ISD::SRA);
1575 setTargetDAGCombine(ISD::SRL);
1576 setTargetDAGCombine(ISD::OR);
1577 setTargetDAGCombine(ISD::AND);
1578 setTargetDAGCombine(ISD::ADD);
1579 setTargetDAGCombine(ISD::FADD);
1580 setTargetDAGCombine(ISD::FSUB);
1581 setTargetDAGCombine(ISD::FMA);
1582 setTargetDAGCombine(ISD::SUB);
1583 setTargetDAGCombine(ISD::LOAD);
1584 setTargetDAGCombine(ISD::MLOAD);
1585 setTargetDAGCombine(ISD::STORE);
1586 setTargetDAGCombine(ISD::MSTORE);
1587 setTargetDAGCombine(ISD::ZERO_EXTEND);
1588 setTargetDAGCombine(ISD::ANY_EXTEND);
1589 setTargetDAGCombine(ISD::SIGN_EXTEND);
1590 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1591 setTargetDAGCombine(ISD::SINT_TO_FP);
1592 setTargetDAGCombine(ISD::SETCC);
1593 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1594 setTargetDAGCombine(ISD::BUILD_VECTOR);
1595 setTargetDAGCombine(ISD::MUL);
1596 setTargetDAGCombine(ISD::XOR);
1598 computeRegisterProperties(Subtarget->getRegisterInfo());
1600 // On Darwin, -Os means optimize for size without hurting performance,
1601 // do not reduce the limit.
1602 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1603 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1604 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1605 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1606 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1607 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1608 setPrefLoopAlignment(4); // 2^4 bytes.
1610 // Predictable cmov don't hurt on atom because it's in-order.
1611 PredictableSelectIsExpensive = !Subtarget->isAtom();
1612 EnableExtLdPromotion = true;
1613 setPrefFunctionAlignment(4); // 2^4 bytes.
1615 verifyIntrinsicTables();
1618 // This has so far only been implemented for 64-bit MachO.
1619 bool X86TargetLowering::useLoadStackGuardNode() const {
1620 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1623 TargetLoweringBase::LegalizeTypeAction
1624 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1625 if (ExperimentalVectorWideningLegalization &&
1626 VT.getVectorNumElements() != 1 &&
1627 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1628 return TypeWidenVector;
1630 return TargetLoweringBase::getPreferredVectorAction(VT);
1633 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1635 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1637 const unsigned NumElts = VT.getVectorNumElements();
1638 const EVT EltVT = VT.getVectorElementType();
1639 if (VT.is512BitVector()) {
1640 if (Subtarget->hasAVX512())
1641 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1642 EltVT == MVT::f32 || EltVT == MVT::f64)
1644 case 8: return MVT::v8i1;
1645 case 16: return MVT::v16i1;
1647 if (Subtarget->hasBWI())
1648 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1650 case 32: return MVT::v32i1;
1651 case 64: return MVT::v64i1;
1655 if (VT.is256BitVector() || VT.is128BitVector()) {
1656 if (Subtarget->hasVLX())
1657 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1658 EltVT == MVT::f32 || EltVT == MVT::f64)
1660 case 2: return MVT::v2i1;
1661 case 4: return MVT::v4i1;
1662 case 8: return MVT::v8i1;
1664 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1665 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1667 case 8: return MVT::v8i1;
1668 case 16: return MVT::v16i1;
1669 case 32: return MVT::v32i1;
1673 return VT.changeVectorElementTypeToInteger();
1676 /// Helper for getByValTypeAlignment to determine
1677 /// the desired ByVal argument alignment.
1678 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1681 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1682 if (VTy->getBitWidth() == 128)
1684 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1685 unsigned EltAlign = 0;
1686 getMaxByValAlign(ATy->getElementType(), EltAlign);
1687 if (EltAlign > MaxAlign)
1688 MaxAlign = EltAlign;
1689 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1690 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1691 unsigned EltAlign = 0;
1692 getMaxByValAlign(STy->getElementType(i), EltAlign);
1693 if (EltAlign > MaxAlign)
1694 MaxAlign = EltAlign;
1701 /// Return the desired alignment for ByVal aggregate
1702 /// function arguments in the caller parameter area. For X86, aggregates
1703 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1704 /// are at 4-byte boundaries.
1705 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1706 if (Subtarget->is64Bit()) {
1707 // Max of 8 and alignment of type.
1708 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1715 if (Subtarget->hasSSE1())
1716 getMaxByValAlign(Ty, Align);
1720 /// Returns the target specific optimal type for load
1721 /// and store operations as a result of memset, memcpy, and memmove
1722 /// lowering. If DstAlign is zero that means it's safe to destination
1723 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1724 /// means there isn't a need to check it against alignment requirement,
1725 /// probably because the source does not need to be loaded. If 'IsMemset' is
1726 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1727 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1728 /// source is constant so it does not need to be loaded.
1729 /// It returns EVT::Other if the type should be determined using generic
1730 /// target-independent logic.
1732 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1733 unsigned DstAlign, unsigned SrcAlign,
1734 bool IsMemset, bool ZeroMemset,
1736 MachineFunction &MF) const {
1737 const Function *F = MF.getFunction();
1738 if ((!IsMemset || ZeroMemset) &&
1739 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1741 (Subtarget->isUnalignedMemAccessFast() ||
1742 ((DstAlign == 0 || DstAlign >= 16) &&
1743 (SrcAlign == 0 || SrcAlign >= 16)))) {
1745 if (Subtarget->hasInt256())
1747 if (Subtarget->hasFp256())
1750 if (Subtarget->hasSSE2())
1752 if (Subtarget->hasSSE1())
1754 } else if (!MemcpyStrSrc && Size >= 8 &&
1755 !Subtarget->is64Bit() &&
1756 Subtarget->hasSSE2()) {
1757 // Do not use f64 to lower memcpy if source is string constant. It's
1758 // better to use i32 to avoid the loads.
1762 if (Subtarget->is64Bit() && Size >= 8)
1767 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1769 return X86ScalarSSEf32;
1770 else if (VT == MVT::f64)
1771 return X86ScalarSSEf64;
1776 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1781 *Fast = Subtarget->isUnalignedMemAccessFast();
1785 /// Return the entry encoding for a jump table in the
1786 /// current function. The returned value is a member of the
1787 /// MachineJumpTableInfo::JTEntryKind enum.
1788 unsigned X86TargetLowering::getJumpTableEncoding() const {
1789 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1791 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1792 Subtarget->isPICStyleGOT())
1793 return MachineJumpTableInfo::EK_Custom32;
1795 // Otherwise, use the normal jump table encoding heuristics.
1796 return TargetLowering::getJumpTableEncoding();
1799 bool X86TargetLowering::useSoftFloat() const {
1800 return Subtarget->useSoftFloat();
1804 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1805 const MachineBasicBlock *MBB,
1806 unsigned uid,MCContext &Ctx) const{
1807 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1808 Subtarget->isPICStyleGOT());
1809 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1811 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1812 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1815 /// Returns relocation base for the given PIC jumptable.
1816 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1817 SelectionDAG &DAG) const {
1818 if (!Subtarget->is64Bit())
1819 // This doesn't have SDLoc associated with it, but is not really the
1820 // same as a Register.
1821 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1825 /// This returns the relocation base for the given PIC jumptable,
1826 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1827 const MCExpr *X86TargetLowering::
1828 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1829 MCContext &Ctx) const {
1830 // X86-64 uses RIP relative addressing based on the jump table label.
1831 if (Subtarget->isPICStyleRIPRel())
1832 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1834 // Otherwise, the reference is relative to the PIC base.
1835 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1838 std::pair<const TargetRegisterClass *, uint8_t>
1839 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1841 const TargetRegisterClass *RRC = nullptr;
1843 switch (VT.SimpleTy) {
1845 return TargetLowering::findRepresentativeClass(TRI, VT);
1846 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1847 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1850 RRC = &X86::VR64RegClass;
1852 case MVT::f32: case MVT::f64:
1853 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1854 case MVT::v4f32: case MVT::v2f64:
1855 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1857 RRC = &X86::VR128RegClass;
1860 return std::make_pair(RRC, Cost);
1863 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1864 unsigned &Offset) const {
1865 if (!Subtarget->isTargetLinux())
1868 if (Subtarget->is64Bit()) {
1869 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1871 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1883 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1884 unsigned DestAS) const {
1885 assert(SrcAS != DestAS && "Expected different address spaces!");
1887 return SrcAS < 256 && DestAS < 256;
1890 //===----------------------------------------------------------------------===//
1891 // Return Value Calling Convention Implementation
1892 //===----------------------------------------------------------------------===//
1894 #include "X86GenCallingConv.inc"
1897 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1898 MachineFunction &MF, bool isVarArg,
1899 const SmallVectorImpl<ISD::OutputArg> &Outs,
1900 LLVMContext &Context) const {
1901 SmallVector<CCValAssign, 16> RVLocs;
1902 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1903 return CCInfo.CheckReturn(Outs, RetCC_X86);
1906 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1907 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1912 X86TargetLowering::LowerReturn(SDValue Chain,
1913 CallingConv::ID CallConv, bool isVarArg,
1914 const SmallVectorImpl<ISD::OutputArg> &Outs,
1915 const SmallVectorImpl<SDValue> &OutVals,
1916 SDLoc dl, SelectionDAG &DAG) const {
1917 MachineFunction &MF = DAG.getMachineFunction();
1918 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1920 SmallVector<CCValAssign, 16> RVLocs;
1921 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1922 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1925 SmallVector<SDValue, 6> RetOps;
1926 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1927 // Operand #1 = Bytes To Pop
1928 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1931 // Copy the result values into the output registers.
1932 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1933 CCValAssign &VA = RVLocs[i];
1934 assert(VA.isRegLoc() && "Can only return in registers!");
1935 SDValue ValToCopy = OutVals[i];
1936 EVT ValVT = ValToCopy.getValueType();
1938 // Promote values to the appropriate types.
1939 if (VA.getLocInfo() == CCValAssign::SExt)
1940 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1941 else if (VA.getLocInfo() == CCValAssign::ZExt)
1942 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1943 else if (VA.getLocInfo() == CCValAssign::AExt) {
1944 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1945 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1947 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1949 else if (VA.getLocInfo() == CCValAssign::BCvt)
1950 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1952 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1953 "Unexpected FP-extend for return value.");
1955 // If this is x86-64, and we disabled SSE, we can't return FP values,
1956 // or SSE or MMX vectors.
1957 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1958 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1959 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1960 report_fatal_error("SSE register return with SSE disabled");
1962 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1963 // llvm-gcc has never done it right and no one has noticed, so this
1964 // should be OK for now.
1965 if (ValVT == MVT::f64 &&
1966 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1967 report_fatal_error("SSE2 register return with SSE2 disabled");
1969 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1970 // the RET instruction and handled by the FP Stackifier.
1971 if (VA.getLocReg() == X86::FP0 ||
1972 VA.getLocReg() == X86::FP1) {
1973 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1974 // change the value to the FP stack register class.
1975 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1976 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1977 RetOps.push_back(ValToCopy);
1978 // Don't emit a copytoreg.
1982 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1983 // which is returned in RAX / RDX.
1984 if (Subtarget->is64Bit()) {
1985 if (ValVT == MVT::x86mmx) {
1986 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1987 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1988 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1990 // If we don't have SSE2 available, convert to v4f32 so the generated
1991 // register is legal.
1992 if (!Subtarget->hasSSE2())
1993 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1998 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1999 Flag = Chain.getValue(1);
2000 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2003 // All x86 ABIs require that for returning structs by value we copy
2004 // the sret argument into %rax/%eax (depending on ABI) for the return.
2005 // We saved the argument into a virtual register in the entry block,
2006 // so now we copy the value out and into %rax/%eax.
2008 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2009 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2010 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2011 // either case FuncInfo->setSRetReturnReg() will have been called.
2012 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2013 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2016 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2017 X86::RAX : X86::EAX;
2018 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2019 Flag = Chain.getValue(1);
2021 // RAX/EAX now acts like a return value.
2022 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2025 RetOps[0] = Chain; // Update chain.
2027 // Add the flag if we have it.
2029 RetOps.push_back(Flag);
2031 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2034 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2035 if (N->getNumValues() != 1)
2037 if (!N->hasNUsesOfValue(1, 0))
2040 SDValue TCChain = Chain;
2041 SDNode *Copy = *N->use_begin();
2042 if (Copy->getOpcode() == ISD::CopyToReg) {
2043 // If the copy has a glue operand, we conservatively assume it isn't safe to
2044 // perform a tail call.
2045 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2047 TCChain = Copy->getOperand(0);
2048 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2051 bool HasRet = false;
2052 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2054 if (UI->getOpcode() != X86ISD::RET_FLAG)
2056 // If we are returning more than one value, we can definitely
2057 // not make a tail call see PR19530
2058 if (UI->getNumOperands() > 4)
2060 if (UI->getNumOperands() == 4 &&
2061 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2074 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2075 ISD::NodeType ExtendKind) const {
2077 // TODO: Is this also valid on 32-bit?
2078 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2079 ReturnMVT = MVT::i8;
2081 ReturnMVT = MVT::i32;
2083 EVT MinVT = getRegisterType(Context, ReturnMVT);
2084 return VT.bitsLT(MinVT) ? MinVT : VT;
2087 /// Lower the result values of a call into the
2088 /// appropriate copies out of appropriate physical registers.
2091 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2092 CallingConv::ID CallConv, bool isVarArg,
2093 const SmallVectorImpl<ISD::InputArg> &Ins,
2094 SDLoc dl, SelectionDAG &DAG,
2095 SmallVectorImpl<SDValue> &InVals) const {
2097 // Assign locations to each value returned by this call.
2098 SmallVector<CCValAssign, 16> RVLocs;
2099 bool Is64Bit = Subtarget->is64Bit();
2100 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2102 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2104 // Copy all of the result registers out of their specified physreg.
2105 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2106 CCValAssign &VA = RVLocs[i];
2107 EVT CopyVT = VA.getLocVT();
2109 // If this is x86-64, and we disabled SSE, we can't return FP values
2110 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2111 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2112 report_fatal_error("SSE register return with SSE disabled");
2115 // If we prefer to use the value in xmm registers, copy it out as f80 and
2116 // use a truncate to move it from fp stack reg to xmm reg.
2117 bool RoundAfterCopy = false;
2118 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2119 isScalarFPTypeInSSEReg(VA.getValVT())) {
2121 RoundAfterCopy = (CopyVT != VA.getLocVT());
2124 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2125 CopyVT, InFlag).getValue(1);
2126 SDValue Val = Chain.getValue(0);
2129 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2130 // This truncation won't change the value.
2131 DAG.getIntPtrConstant(1, dl));
2133 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2134 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2136 InFlag = Chain.getValue(2);
2137 InVals.push_back(Val);
2143 //===----------------------------------------------------------------------===//
2144 // C & StdCall & Fast Calling Convention implementation
2145 //===----------------------------------------------------------------------===//
2146 // StdCall calling convention seems to be standard for many Windows' API
2147 // routines and around. It differs from C calling convention just a little:
2148 // callee should clean up the stack, not caller. Symbols should be also
2149 // decorated in some fancy way :) It doesn't support any vector arguments.
2150 // For info on fast calling convention see Fast Calling Convention (tail call)
2151 // implementation LowerX86_32FastCCCallTo.
2153 /// CallIsStructReturn - Determines whether a call uses struct return
2155 enum StructReturnType {
2160 static StructReturnType
2161 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2163 return NotStructReturn;
2165 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2166 if (!Flags.isSRet())
2167 return NotStructReturn;
2168 if (Flags.isInReg())
2169 return RegStructReturn;
2170 return StackStructReturn;
2173 /// Determines whether a function uses struct return semantics.
2174 static StructReturnType
2175 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2177 return NotStructReturn;
2179 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2180 if (!Flags.isSRet())
2181 return NotStructReturn;
2182 if (Flags.isInReg())
2183 return RegStructReturn;
2184 return StackStructReturn;
2187 /// Make a copy of an aggregate at address specified by "Src" to address
2188 /// "Dst" with size and alignment information specified by the specific
2189 /// parameter attribute. The copy will be passed as a byval function parameter.
2191 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2192 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2194 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2196 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2197 /*isVolatile*/false, /*AlwaysInline=*/true,
2198 /*isTailCall*/false,
2199 MachinePointerInfo(), MachinePointerInfo());
2202 /// Return true if the calling convention is one that
2203 /// supports tail call optimization.
2204 static bool IsTailCallConvention(CallingConv::ID CC) {
2205 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2206 CC == CallingConv::HiPE);
2209 /// \brief Return true if the calling convention is a C calling convention.
2210 static bool IsCCallConvention(CallingConv::ID CC) {
2211 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2212 CC == CallingConv::X86_64_SysV);
2215 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2216 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2220 CallingConv::ID CalleeCC = CS.getCallingConv();
2221 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2227 /// Return true if the function is being made into
2228 /// a tailcall target by changing its ABI.
2229 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2230 bool GuaranteedTailCallOpt) {
2231 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2235 X86TargetLowering::LowerMemArgument(SDValue Chain,
2236 CallingConv::ID CallConv,
2237 const SmallVectorImpl<ISD::InputArg> &Ins,
2238 SDLoc dl, SelectionDAG &DAG,
2239 const CCValAssign &VA,
2240 MachineFrameInfo *MFI,
2242 // Create the nodes corresponding to a load from this parameter slot.
2243 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2244 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2245 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2246 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2249 // If value is passed by pointer we have address passed instead of the value
2251 bool ExtendedInMem = VA.isExtInLoc() &&
2252 VA.getValVT().getScalarType() == MVT::i1;
2254 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2255 ValVT = VA.getLocVT();
2257 ValVT = VA.getValVT();
2259 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2260 // changed with more analysis.
2261 // In case of tail call optimization mark all arguments mutable. Since they
2262 // could be overwritten by lowering of arguments in case of a tail call.
2263 if (Flags.isByVal()) {
2264 unsigned Bytes = Flags.getByValSize();
2265 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2266 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2267 return DAG.getFrameIndex(FI, getPointerTy());
2269 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2270 VA.getLocMemOffset(), isImmutable);
2271 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2272 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2273 MachinePointerInfo::getFixedStack(FI),
2274 false, false, false, 0);
2275 return ExtendedInMem ?
2276 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2280 // FIXME: Get this from tablegen.
2281 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2282 const X86Subtarget *Subtarget) {
2283 assert(Subtarget->is64Bit());
2285 if (Subtarget->isCallingConvWin64(CallConv)) {
2286 static const MCPhysReg GPR64ArgRegsWin64[] = {
2287 X86::RCX, X86::RDX, X86::R8, X86::R9
2289 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2292 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2293 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2295 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2298 // FIXME: Get this from tablegen.
2299 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2300 CallingConv::ID CallConv,
2301 const X86Subtarget *Subtarget) {
2302 assert(Subtarget->is64Bit());
2303 if (Subtarget->isCallingConvWin64(CallConv)) {
2304 // The XMM registers which might contain var arg parameters are shadowed
2305 // in their paired GPR. So we only need to save the GPR to their home
2307 // TODO: __vectorcall will change this.
2311 const Function *Fn = MF.getFunction();
2312 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2313 bool isSoftFloat = Subtarget->useSoftFloat();
2314 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2315 "SSE register cannot be used when SSE is disabled!");
2316 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2317 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2321 static const MCPhysReg XMMArgRegs64Bit[] = {
2322 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2323 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2325 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2329 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2330 CallingConv::ID CallConv,
2332 const SmallVectorImpl<ISD::InputArg> &Ins,
2335 SmallVectorImpl<SDValue> &InVals)
2337 MachineFunction &MF = DAG.getMachineFunction();
2338 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2339 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2341 const Function* Fn = MF.getFunction();
2342 if (Fn->hasExternalLinkage() &&
2343 Subtarget->isTargetCygMing() &&
2344 Fn->getName() == "main")
2345 FuncInfo->setForceFramePointer(true);
2347 MachineFrameInfo *MFI = MF.getFrameInfo();
2348 bool Is64Bit = Subtarget->is64Bit();
2349 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2351 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2352 "Var args not supported with calling convention fastcc, ghc or hipe");
2354 // Assign locations to all of the incoming arguments.
2355 SmallVector<CCValAssign, 16> ArgLocs;
2356 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2358 // Allocate shadow area for Win64
2360 CCInfo.AllocateStack(32, 8);
2362 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2364 unsigned LastVal = ~0U;
2366 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2367 CCValAssign &VA = ArgLocs[i];
2368 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2370 assert(VA.getValNo() != LastVal &&
2371 "Don't support value assigned to multiple locs yet");
2373 LastVal = VA.getValNo();
2375 if (VA.isRegLoc()) {
2376 EVT RegVT = VA.getLocVT();
2377 const TargetRegisterClass *RC;
2378 if (RegVT == MVT::i32)
2379 RC = &X86::GR32RegClass;
2380 else if (Is64Bit && RegVT == MVT::i64)
2381 RC = &X86::GR64RegClass;
2382 else if (RegVT == MVT::f32)
2383 RC = &X86::FR32RegClass;
2384 else if (RegVT == MVT::f64)
2385 RC = &X86::FR64RegClass;
2386 else if (RegVT.is512BitVector())
2387 RC = &X86::VR512RegClass;
2388 else if (RegVT.is256BitVector())
2389 RC = &X86::VR256RegClass;
2390 else if (RegVT.is128BitVector())
2391 RC = &X86::VR128RegClass;
2392 else if (RegVT == MVT::x86mmx)
2393 RC = &X86::VR64RegClass;
2394 else if (RegVT == MVT::i1)
2395 RC = &X86::VK1RegClass;
2396 else if (RegVT == MVT::v8i1)
2397 RC = &X86::VK8RegClass;
2398 else if (RegVT == MVT::v16i1)
2399 RC = &X86::VK16RegClass;
2400 else if (RegVT == MVT::v32i1)
2401 RC = &X86::VK32RegClass;
2402 else if (RegVT == MVT::v64i1)
2403 RC = &X86::VK64RegClass;
2405 llvm_unreachable("Unknown argument type!");
2407 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2408 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2410 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2411 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2413 if (VA.getLocInfo() == CCValAssign::SExt)
2414 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2415 DAG.getValueType(VA.getValVT()));
2416 else if (VA.getLocInfo() == CCValAssign::ZExt)
2417 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2418 DAG.getValueType(VA.getValVT()));
2419 else if (VA.getLocInfo() == CCValAssign::BCvt)
2420 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2422 if (VA.isExtInLoc()) {
2423 // Handle MMX values passed in XMM regs.
2424 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2425 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2427 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2430 assert(VA.isMemLoc());
2431 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2434 // If value is passed via pointer - do a load.
2435 if (VA.getLocInfo() == CCValAssign::Indirect)
2436 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2437 MachinePointerInfo(), false, false, false, 0);
2439 InVals.push_back(ArgValue);
2442 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2443 // All x86 ABIs require that for returning structs by value we copy the
2444 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2445 // the argument into a virtual register so that we can access it from the
2447 if (Ins[i].Flags.isSRet()) {
2448 unsigned Reg = FuncInfo->getSRetReturnReg();
2450 MVT PtrTy = getPointerTy();
2451 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2452 FuncInfo->setSRetReturnReg(Reg);
2454 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2455 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2460 unsigned StackSize = CCInfo.getNextStackOffset();
2461 // Align stack specially for tail calls.
2462 if (FuncIsMadeTailCallSafe(CallConv,
2463 MF.getTarget().Options.GuaranteedTailCallOpt))
2464 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2466 // If the function takes variable number of arguments, make a frame index for
2467 // the start of the first vararg value... for expansion of llvm.va_start. We
2468 // can skip this if there are no va_start calls.
2469 if (MFI->hasVAStart() &&
2470 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2471 CallConv != CallingConv::X86_ThisCall))) {
2472 FuncInfo->setVarArgsFrameIndex(
2473 MFI->CreateFixedObject(1, StackSize, true));
2476 MachineModuleInfo &MMI = MF.getMMI();
2477 const Function *WinEHParent = nullptr;
2478 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2479 WinEHParent = MMI.getWinEHParent(Fn);
2480 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2481 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2483 // Figure out if XMM registers are in use.
2484 assert(!(Subtarget->useSoftFloat() &&
2485 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2486 "SSE register cannot be used when SSE is disabled!");
2488 // 64-bit calling conventions support varargs and register parameters, so we
2489 // have to do extra work to spill them in the prologue.
2490 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2491 // Find the first unallocated argument registers.
2492 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2493 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2494 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2495 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2496 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2497 "SSE register cannot be used when SSE is disabled!");
2499 // Gather all the live in physical registers.
2500 SmallVector<SDValue, 6> LiveGPRs;
2501 SmallVector<SDValue, 8> LiveXMMRegs;
2503 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2504 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2506 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2508 if (!ArgXMMs.empty()) {
2509 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2510 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2511 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2512 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2513 LiveXMMRegs.push_back(
2514 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2519 // Get to the caller-allocated home save location. Add 8 to account
2520 // for the return address.
2521 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2522 FuncInfo->setRegSaveFrameIndex(
2523 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2524 // Fixup to set vararg frame on shadow area (4 x i64).
2526 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2528 // For X86-64, if there are vararg parameters that are passed via
2529 // registers, then we must store them to their spots on the stack so
2530 // they may be loaded by deferencing the result of va_next.
2531 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2532 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2533 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2534 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2537 // Store the integer parameter registers.
2538 SmallVector<SDValue, 8> MemOps;
2539 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2541 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2542 for (SDValue Val : LiveGPRs) {
2543 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2544 DAG.getIntPtrConstant(Offset, dl));
2546 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2547 MachinePointerInfo::getFixedStack(
2548 FuncInfo->getRegSaveFrameIndex(), Offset),
2550 MemOps.push_back(Store);
2554 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2555 // Now store the XMM (fp + vector) parameter registers.
2556 SmallVector<SDValue, 12> SaveXMMOps;
2557 SaveXMMOps.push_back(Chain);
2558 SaveXMMOps.push_back(ALVal);
2559 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2560 FuncInfo->getRegSaveFrameIndex(), dl));
2561 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2562 FuncInfo->getVarArgsFPOffset(), dl));
2563 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2565 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2566 MVT::Other, SaveXMMOps));
2569 if (!MemOps.empty())
2570 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2571 } else if (IsWinEHOutlined) {
2572 // Get to the caller-allocated home save location. Add 8 to account
2573 // for the return address.
2574 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2575 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2576 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2578 MMI.getWinEHFuncInfo(Fn)
2579 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2580 FuncInfo->getRegSaveFrameIndex();
2582 // Store the second integer parameter (rdx) into rsp+16 relative to the
2583 // stack pointer at the entry of the function.
2585 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2586 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2587 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2588 Chain = DAG.getStore(
2589 Val.getValue(1), dl, Val, RSFIN,
2590 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2591 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2594 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2595 // Find the largest legal vector type.
2596 MVT VecVT = MVT::Other;
2597 // FIXME: Only some x86_32 calling conventions support AVX512.
2598 if (Subtarget->hasAVX512() &&
2599 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2600 CallConv == CallingConv::Intel_OCL_BI)))
2601 VecVT = MVT::v16f32;
2602 else if (Subtarget->hasAVX())
2604 else if (Subtarget->hasSSE2())
2607 // We forward some GPRs and some vector types.
2608 SmallVector<MVT, 2> RegParmTypes;
2609 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2610 RegParmTypes.push_back(IntVT);
2611 if (VecVT != MVT::Other)
2612 RegParmTypes.push_back(VecVT);
2614 // Compute the set of forwarded registers. The rest are scratch.
2615 SmallVectorImpl<ForwardedRegister> &Forwards =
2616 FuncInfo->getForwardedMustTailRegParms();
2617 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2619 // Conservatively forward AL on x86_64, since it might be used for varargs.
2620 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2621 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2622 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2625 // Copy all forwards from physical to virtual registers.
2626 for (ForwardedRegister &F : Forwards) {
2627 // FIXME: Can we use a less constrained schedule?
2628 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2629 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2630 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2634 // Some CCs need callee pop.
2635 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2636 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2637 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2639 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2640 // If this is an sret function, the return should pop the hidden pointer.
2641 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2642 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2643 argsAreStructReturn(Ins) == StackStructReturn)
2644 FuncInfo->setBytesToPopOnReturn(4);
2648 // RegSaveFrameIndex is X86-64 only.
2649 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2650 if (CallConv == CallingConv::X86_FastCall ||
2651 CallConv == CallingConv::X86_ThisCall)
2652 // fastcc functions can't have varargs.
2653 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2656 FuncInfo->setArgumentStackSize(StackSize);
2658 if (IsWinEHParent) {
2659 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2660 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2661 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2662 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2663 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2664 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2665 /*isVolatile=*/true,
2666 /*isNonTemporal=*/false, /*Alignment=*/0);
2673 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2674 SDValue StackPtr, SDValue Arg,
2675 SDLoc dl, SelectionDAG &DAG,
2676 const CCValAssign &VA,
2677 ISD::ArgFlagsTy Flags) const {
2678 unsigned LocMemOffset = VA.getLocMemOffset();
2679 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2680 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2681 if (Flags.isByVal())
2682 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2684 return DAG.getStore(Chain, dl, Arg, PtrOff,
2685 MachinePointerInfo::getStack(LocMemOffset),
2689 /// Emit a load of return address if tail call
2690 /// optimization is performed and it is required.
2692 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2693 SDValue &OutRetAddr, SDValue Chain,
2694 bool IsTailCall, bool Is64Bit,
2695 int FPDiff, SDLoc dl) const {
2696 // Adjust the Return address stack slot.
2697 EVT VT = getPointerTy();
2698 OutRetAddr = getReturnAddressFrameIndex(DAG);
2700 // Load the "old" Return address.
2701 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2702 false, false, false, 0);
2703 return SDValue(OutRetAddr.getNode(), 1);
2706 /// Emit a store of the return address if tail call
2707 /// optimization is performed and it is required (FPDiff!=0).
2708 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2709 SDValue Chain, SDValue RetAddrFrIdx,
2710 EVT PtrVT, unsigned SlotSize,
2711 int FPDiff, SDLoc dl) {
2712 // Store the return address to the appropriate stack slot.
2713 if (!FPDiff) return Chain;
2714 // Calculate the new stack slot for the return address.
2715 int NewReturnAddrFI =
2716 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2718 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2719 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2720 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2726 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2727 SmallVectorImpl<SDValue> &InVals) const {
2728 SelectionDAG &DAG = CLI.DAG;
2730 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2731 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2732 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2733 SDValue Chain = CLI.Chain;
2734 SDValue Callee = CLI.Callee;
2735 CallingConv::ID CallConv = CLI.CallConv;
2736 bool &isTailCall = CLI.IsTailCall;
2737 bool isVarArg = CLI.IsVarArg;
2739 MachineFunction &MF = DAG.getMachineFunction();
2740 bool Is64Bit = Subtarget->is64Bit();
2741 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2742 StructReturnType SR = callIsStructReturn(Outs);
2743 bool IsSibcall = false;
2744 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2746 if (MF.getTarget().Options.DisableTailCalls)
2749 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2751 // Force this to be a tail call. The verifier rules are enough to ensure
2752 // that we can lower this successfully without moving the return address
2755 } else if (isTailCall) {
2756 // Check if it's really possible to do a tail call.
2757 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2758 isVarArg, SR != NotStructReturn,
2759 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2760 Outs, OutVals, Ins, DAG);
2762 // Sibcalls are automatically detected tailcalls which do not require
2764 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2771 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2772 "Var args not supported with calling convention fastcc, ghc or hipe");
2774 // Analyze operands of the call, assigning locations to each operand.
2775 SmallVector<CCValAssign, 16> ArgLocs;
2776 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2778 // Allocate shadow area for Win64
2780 CCInfo.AllocateStack(32, 8);
2782 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2784 // Get a count of how many bytes are to be pushed on the stack.
2785 unsigned NumBytes = CCInfo.getNextStackOffset();
2787 // This is a sibcall. The memory operands are available in caller's
2788 // own caller's stack.
2790 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2791 IsTailCallConvention(CallConv))
2792 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2795 if (isTailCall && !IsSibcall && !IsMustTail) {
2796 // Lower arguments at fp - stackoffset + fpdiff.
2797 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2799 FPDiff = NumBytesCallerPushed - NumBytes;
2801 // Set the delta of movement of the returnaddr stackslot.
2802 // But only set if delta is greater than previous delta.
2803 if (FPDiff < X86Info->getTCReturnAddrDelta())
2804 X86Info->setTCReturnAddrDelta(FPDiff);
2807 unsigned NumBytesToPush = NumBytes;
2808 unsigned NumBytesToPop = NumBytes;
2810 // If we have an inalloca argument, all stack space has already been allocated
2811 // for us and be right at the top of the stack. We don't support multiple
2812 // arguments passed in memory when using inalloca.
2813 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2815 if (!ArgLocs.back().isMemLoc())
2816 report_fatal_error("cannot use inalloca attribute on a register "
2818 if (ArgLocs.back().getLocMemOffset() != 0)
2819 report_fatal_error("any parameter with the inalloca attribute must be "
2820 "the only memory argument");
2824 Chain = DAG.getCALLSEQ_START(
2825 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2827 SDValue RetAddrFrIdx;
2828 // Load return address for tail calls.
2829 if (isTailCall && FPDiff)
2830 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2831 Is64Bit, FPDiff, dl);
2833 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2834 SmallVector<SDValue, 8> MemOpChains;
2837 // Walk the register/memloc assignments, inserting copies/loads. In the case
2838 // of tail call optimization arguments are handle later.
2839 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2841 // Skip inalloca arguments, they have already been written.
2842 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2843 if (Flags.isInAlloca())
2846 CCValAssign &VA = ArgLocs[i];
2847 EVT RegVT = VA.getLocVT();
2848 SDValue Arg = OutVals[i];
2849 bool isByVal = Flags.isByVal();
2851 // Promote the value if needed.
2852 switch (VA.getLocInfo()) {
2853 default: llvm_unreachable("Unknown loc info!");
2854 case CCValAssign::Full: break;
2855 case CCValAssign::SExt:
2856 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2858 case CCValAssign::ZExt:
2859 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2861 case CCValAssign::AExt:
2862 if (Arg.getValueType().isVector() &&
2863 Arg.getValueType().getScalarType() == MVT::i1)
2864 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2865 else if (RegVT.is128BitVector()) {
2866 // Special case: passing MMX values in XMM registers.
2867 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2868 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2869 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2871 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2873 case CCValAssign::BCvt:
2874 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2876 case CCValAssign::Indirect: {
2877 // Store the argument.
2878 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2879 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2880 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2881 MachinePointerInfo::getFixedStack(FI),
2888 if (VA.isRegLoc()) {
2889 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2890 if (isVarArg && IsWin64) {
2891 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2892 // shadow reg if callee is a varargs function.
2893 unsigned ShadowReg = 0;
2894 switch (VA.getLocReg()) {
2895 case X86::XMM0: ShadowReg = X86::RCX; break;
2896 case X86::XMM1: ShadowReg = X86::RDX; break;
2897 case X86::XMM2: ShadowReg = X86::R8; break;
2898 case X86::XMM3: ShadowReg = X86::R9; break;
2901 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2903 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2904 assert(VA.isMemLoc());
2905 if (!StackPtr.getNode())
2906 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2908 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2909 dl, DAG, VA, Flags));
2913 if (!MemOpChains.empty())
2914 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2916 if (Subtarget->isPICStyleGOT()) {
2917 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2920 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2921 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2923 // If we are tail calling and generating PIC/GOT style code load the
2924 // address of the callee into ECX. The value in ecx is used as target of
2925 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2926 // for tail calls on PIC/GOT architectures. Normally we would just put the
2927 // address of GOT into ebx and then call target@PLT. But for tail calls
2928 // ebx would be restored (since ebx is callee saved) before jumping to the
2931 // Note: The actual moving to ECX is done further down.
2932 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2933 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2934 !G->getGlobal()->hasProtectedVisibility())
2935 Callee = LowerGlobalAddress(Callee, DAG);
2936 else if (isa<ExternalSymbolSDNode>(Callee))
2937 Callee = LowerExternalSymbol(Callee, DAG);
2941 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2942 // From AMD64 ABI document:
2943 // For calls that may call functions that use varargs or stdargs
2944 // (prototype-less calls or calls to functions containing ellipsis (...) in
2945 // the declaration) %al is used as hidden argument to specify the number
2946 // of SSE registers used. The contents of %al do not need to match exactly
2947 // the number of registers, but must be an ubound on the number of SSE
2948 // registers used and is in the range 0 - 8 inclusive.
2950 // Count the number of XMM registers allocated.
2951 static const MCPhysReg XMMArgRegs[] = {
2952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2956 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2957 && "SSE registers cannot be used when SSE is disabled");
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2960 DAG.getConstant(NumXMMRegs, dl,
2964 if (isVarArg && IsMustTail) {
2965 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2966 for (const auto &F : Forwards) {
2967 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2968 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2972 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2973 // don't need this because the eligibility check rejects calls that require
2974 // shuffling arguments passed in memory.
2975 if (!IsSibcall && isTailCall) {
2976 // Force all the incoming stack arguments to be loaded from the stack
2977 // before any new outgoing arguments are stored to the stack, because the
2978 // outgoing stack slots may alias the incoming argument stack slots, and
2979 // the alias isn't otherwise explicit. This is slightly more conservative
2980 // than necessary, because it means that each store effectively depends
2981 // on every argument instead of just those arguments it would clobber.
2982 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2984 SmallVector<SDValue, 8> MemOpChains2;
2987 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2988 CCValAssign &VA = ArgLocs[i];
2991 assert(VA.isMemLoc());
2992 SDValue Arg = OutVals[i];
2993 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2994 // Skip inalloca arguments. They don't require any work.
2995 if (Flags.isInAlloca())
2997 // Create frame index.
2998 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2999 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3000 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3001 FIN = DAG.getFrameIndex(FI, getPointerTy());
3003 if (Flags.isByVal()) {
3004 // Copy relative to framepointer.
3005 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3006 if (!StackPtr.getNode())
3007 StackPtr = DAG.getCopyFromReg(Chain, dl,
3008 RegInfo->getStackRegister(),
3010 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3012 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3016 // Store relative to framepointer.
3017 MemOpChains2.push_back(
3018 DAG.getStore(ArgChain, dl, Arg, FIN,
3019 MachinePointerInfo::getFixedStack(FI),
3024 if (!MemOpChains2.empty())
3025 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3027 // Store the return address to the appropriate stack slot.
3028 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3029 getPointerTy(), RegInfo->getSlotSize(),
3033 // Build a sequence of copy-to-reg nodes chained together with token chain
3034 // and flag operands which copy the outgoing args into registers.
3036 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3037 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3038 RegsToPass[i].second, InFlag);
3039 InFlag = Chain.getValue(1);
3042 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3043 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3044 // In the 64-bit large code model, we have to make all calls
3045 // through a register, since the call instruction's 32-bit
3046 // pc-relative offset may not be large enough to hold the whole
3048 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3049 // If the callee is a GlobalAddress node (quite common, every direct call
3050 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3052 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3054 // We should use extra load for direct calls to dllimported functions in
3056 const GlobalValue *GV = G->getGlobal();
3057 if (!GV->hasDLLImportStorageClass()) {
3058 unsigned char OpFlags = 0;
3059 bool ExtraLoad = false;
3060 unsigned WrapperKind = ISD::DELETED_NODE;
3062 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3063 // external symbols most go through the PLT in PIC mode. If the symbol
3064 // has hidden or protected visibility, or if it is static or local, then
3065 // we don't need to use the PLT - we can directly call it.
3066 if (Subtarget->isTargetELF() &&
3067 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3068 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3069 OpFlags = X86II::MO_PLT;
3070 } else if (Subtarget->isPICStyleStubAny() &&
3071 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3072 (!Subtarget->getTargetTriple().isMacOSX() ||
3073 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3074 // PC-relative references to external symbols should go through $stub,
3075 // unless we're building with the leopard linker or later, which
3076 // automatically synthesizes these stubs.
3077 OpFlags = X86II::MO_DARWIN_STUB;
3078 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3079 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3080 // If the function is marked as non-lazy, generate an indirect call
3081 // which loads from the GOT directly. This avoids runtime overhead
3082 // at the cost of eager binding (and one extra byte of encoding).
3083 OpFlags = X86II::MO_GOTPCREL;
3084 WrapperKind = X86ISD::WrapperRIP;
3088 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3089 G->getOffset(), OpFlags);
3091 // Add a wrapper if needed.
3092 if (WrapperKind != ISD::DELETED_NODE)
3093 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3094 // Add extra indirection if needed.
3096 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3097 MachinePointerInfo::getGOT(),
3098 false, false, false, 0);
3100 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3101 unsigned char OpFlags = 0;
3103 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3104 // external symbols should go through the PLT.
3105 if (Subtarget->isTargetELF() &&
3106 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3107 OpFlags = X86II::MO_PLT;
3108 } else if (Subtarget->isPICStyleStubAny() &&
3109 (!Subtarget->getTargetTriple().isMacOSX() ||
3110 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3111 // PC-relative references to external symbols should go through $stub,
3112 // unless we're building with the leopard linker or later, which
3113 // automatically synthesizes these stubs.
3114 OpFlags = X86II::MO_DARWIN_STUB;
3117 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3119 } else if (Subtarget->isTarget64BitILP32() &&
3120 Callee->getValueType(0) == MVT::i32) {
3121 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3122 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3125 // Returns a chain & a flag for retval copy to use.
3126 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3127 SmallVector<SDValue, 8> Ops;
3129 if (!IsSibcall && isTailCall) {
3130 Chain = DAG.getCALLSEQ_END(Chain,
3131 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3132 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3133 InFlag = Chain.getValue(1);
3136 Ops.push_back(Chain);
3137 Ops.push_back(Callee);
3140 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3142 // Add argument registers to the end of the list so that they are known live
3144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3145 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3146 RegsToPass[i].second.getValueType()));
3148 // Add a register mask operand representing the call-preserved registers.
3149 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3150 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3151 assert(Mask && "Missing call preserved mask for calling convention");
3152 Ops.push_back(DAG.getRegisterMask(Mask));
3154 if (InFlag.getNode())
3155 Ops.push_back(InFlag);
3159 //// If this is the first return lowered for this function, add the regs
3160 //// to the liveout set for the function.
3161 // This isn't right, although it's probably harmless on x86; liveouts
3162 // should be computed from returns not tail calls. Consider a void
3163 // function making a tail call to a function returning int.
3164 MF.getFrameInfo()->setHasTailCall();
3165 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3168 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3169 InFlag = Chain.getValue(1);
3171 // Create the CALLSEQ_END node.
3172 unsigned NumBytesForCalleeToPop;
3173 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3174 DAG.getTarget().Options.GuaranteedTailCallOpt))
3175 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3176 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3177 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3178 SR == StackStructReturn)
3179 // If this is a call to a struct-return function, the callee
3180 // pops the hidden struct pointer, so we have to push it back.
3181 // This is common for Darwin/X86, Linux & Mingw32 targets.
3182 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3183 NumBytesForCalleeToPop = 4;
3185 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3187 // Returns a flag for retval copy to use.
3189 Chain = DAG.getCALLSEQ_END(Chain,
3190 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3191 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3194 InFlag = Chain.getValue(1);
3197 // Handle result values, copying them out of physregs into vregs that we
3199 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3200 Ins, dl, DAG, InVals);
3203 //===----------------------------------------------------------------------===//
3204 // Fast Calling Convention (tail call) implementation
3205 //===----------------------------------------------------------------------===//
3207 // Like std call, callee cleans arguments, convention except that ECX is
3208 // reserved for storing the tail called function address. Only 2 registers are
3209 // free for argument passing (inreg). Tail call optimization is performed
3211 // * tailcallopt is enabled
3212 // * caller/callee are fastcc
3213 // On X86_64 architecture with GOT-style position independent code only local
3214 // (within module) calls are supported at the moment.
3215 // To keep the stack aligned according to platform abi the function
3216 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3217 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3218 // If a tail called function callee has more arguments than the caller the
3219 // caller needs to make sure that there is room to move the RETADDR to. This is
3220 // achieved by reserving an area the size of the argument delta right after the
3221 // original RETADDR, but before the saved framepointer or the spilled registers
3222 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3234 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3235 /// for a 16 byte align requirement.
3237 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3238 SelectionDAG& DAG) const {
3239 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3240 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3241 unsigned StackAlignment = TFI.getStackAlignment();
3242 uint64_t AlignMask = StackAlignment - 1;
3243 int64_t Offset = StackSize;
3244 unsigned SlotSize = RegInfo->getSlotSize();
3245 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3246 // Number smaller than 12 so just add the difference.
3247 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3249 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3250 Offset = ((~AlignMask) & Offset) + StackAlignment +
3251 (StackAlignment-SlotSize);
3256 /// MatchingStackOffset - Return true if the given stack call argument is
3257 /// already available in the same position (relatively) of the caller's
3258 /// incoming argument stack.
3260 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3261 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3262 const X86InstrInfo *TII) {
3263 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3265 if (Arg.getOpcode() == ISD::CopyFromReg) {
3266 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3267 if (!TargetRegisterInfo::isVirtualRegister(VR))
3269 MachineInstr *Def = MRI->getVRegDef(VR);
3272 if (!Flags.isByVal()) {
3273 if (!TII->isLoadFromStackSlot(Def, FI))
3276 unsigned Opcode = Def->getOpcode();
3277 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3278 Opcode == X86::LEA64_32r) &&
3279 Def->getOperand(1).isFI()) {
3280 FI = Def->getOperand(1).getIndex();
3281 Bytes = Flags.getByValSize();
3285 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3286 if (Flags.isByVal())
3287 // ByVal argument is passed in as a pointer but it's now being
3288 // dereferenced. e.g.
3289 // define @foo(%struct.X* %A) {
3290 // tail call @bar(%struct.X* byval %A)
3293 SDValue Ptr = Ld->getBasePtr();
3294 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3297 FI = FINode->getIndex();
3298 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3299 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3300 FI = FINode->getIndex();
3301 Bytes = Flags.getByValSize();
3305 assert(FI != INT_MAX);
3306 if (!MFI->isFixedObjectIndex(FI))
3308 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3311 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3312 /// for tail call optimization. Targets which want to do tail call
3313 /// optimization should implement this function.
3315 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3316 CallingConv::ID CalleeCC,
3318 bool isCalleeStructRet,
3319 bool isCallerStructRet,
3321 const SmallVectorImpl<ISD::OutputArg> &Outs,
3322 const SmallVectorImpl<SDValue> &OutVals,
3323 const SmallVectorImpl<ISD::InputArg> &Ins,
3324 SelectionDAG &DAG) const {
3325 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3328 // If -tailcallopt is specified, make fastcc functions tail-callable.
3329 const MachineFunction &MF = DAG.getMachineFunction();
3330 const Function *CallerF = MF.getFunction();
3332 // If the function return type is x86_fp80 and the callee return type is not,
3333 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3334 // perform a tailcall optimization here.
3335 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3338 CallingConv::ID CallerCC = CallerF->getCallingConv();
3339 bool CCMatch = CallerCC == CalleeCC;
3340 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3341 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3343 // Win64 functions have extra shadow space for argument homing. Don't do the
3344 // sibcall if the caller and callee have mismatched expectations for this
3346 if (IsCalleeWin64 != IsCallerWin64)
3349 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3350 if (IsTailCallConvention(CalleeCC) && CCMatch)
3355 // Look for obvious safe cases to perform tail call optimization that do not
3356 // require ABI changes. This is what gcc calls sibcall.
3358 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3359 // emit a special epilogue.
3360 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3361 if (RegInfo->needsStackRealignment(MF))
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3449 // If the callee takes no arguments then go on to check the results of the
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3458 // Allocate shadow area for Win64
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, unsigned TargetMask,
3570 SelectionDAG &DAG) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::PSHUFD:
3574 case X86ISD::PSHUFHW:
3575 case X86ISD::PSHUFLW:
3576 case X86ISD::VPERMILPI:
3577 case X86ISD::VPERMI:
3578 return DAG.getNode(Opc, dl, VT, V1,
3579 DAG.getConstant(TargetMask, dl, MVT::i8));
3583 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3584 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3586 default: llvm_unreachable("Unknown x86 shuffle node");
3587 case X86ISD::MOVLHPS:
3588 case X86ISD::MOVLHPD:
3589 case X86ISD::MOVHLPS:
3590 case X86ISD::MOVLPS:
3591 case X86ISD::MOVLPD:
3594 case X86ISD::UNPCKL:
3595 case X86ISD::UNPCKH:
3596 return DAG.getNode(Opc, dl, VT, V1, V2);
3600 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3601 MachineFunction &MF = DAG.getMachineFunction();
3602 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3603 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3604 int ReturnAddrIndex = FuncInfo->getRAIndex();
3606 if (ReturnAddrIndex == 0) {
3607 // Set up a frame object for the return address.
3608 unsigned SlotSize = RegInfo->getSlotSize();
3609 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3612 FuncInfo->setRAIndex(ReturnAddrIndex);
3615 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3618 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3619 bool hasSymbolicDisplacement) {
3620 // Offset should fit into 32 bit immediate field.
3621 if (!isInt<32>(Offset))
3624 // If we don't have a symbolic displacement - we don't have any extra
3626 if (!hasSymbolicDisplacement)
3629 // FIXME: Some tweaks might be needed for medium code model.
3630 if (M != CodeModel::Small && M != CodeModel::Kernel)
3633 // For small code model we assume that latest object is 16MB before end of 31
3634 // bits boundary. We may also accept pretty large negative constants knowing
3635 // that all objects are in the positive half of address space.
3636 if (M == CodeModel::Small && Offset < 16*1024*1024)
3639 // For kernel code model we know that all object resist in the negative half
3640 // of 32bits address space. We may not accept negative offsets, since they may
3641 // be just off and we may accept pretty large positive ones.
3642 if (M == CodeModel::Kernel && Offset >= 0)
3648 /// isCalleePop - Determines whether the callee is required to pop its
3649 /// own arguments. Callee pop is necessary to support tail calls.
3650 bool X86::isCalleePop(CallingConv::ID CallingConv,
3651 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3652 switch (CallingConv) {
3655 case CallingConv::X86_StdCall:
3656 case CallingConv::X86_FastCall:
3657 case CallingConv::X86_ThisCall:
3659 case CallingConv::Fast:
3660 case CallingConv::GHC:
3661 case CallingConv::HiPE:
3668 /// \brief Return true if the condition is an unsigned comparison operation.
3669 static bool isX86CCUnsigned(unsigned X86CC) {
3671 default: llvm_unreachable("Invalid integer condition!");
3672 case X86::COND_E: return true;
3673 case X86::COND_G: return false;
3674 case X86::COND_GE: return false;
3675 case X86::COND_L: return false;
3676 case X86::COND_LE: return false;
3677 case X86::COND_NE: return true;
3678 case X86::COND_B: return true;
3679 case X86::COND_A: return true;
3680 case X86::COND_BE: return true;
3681 case X86::COND_AE: return true;
3683 llvm_unreachable("covered switch fell through?!");
3686 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3687 /// specific condition code, returning the condition code and the LHS/RHS of the
3688 /// comparison to make.
3689 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3690 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3692 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3693 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3694 // X > -1 -> X == 0, jump !sign.
3695 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3696 return X86::COND_NS;
3698 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3699 // X < 0 -> X == 0, jump on sign.
3702 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3704 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3705 return X86::COND_LE;
3709 switch (SetCCOpcode) {
3710 default: llvm_unreachable("Invalid integer condition!");
3711 case ISD::SETEQ: return X86::COND_E;
3712 case ISD::SETGT: return X86::COND_G;
3713 case ISD::SETGE: return X86::COND_GE;
3714 case ISD::SETLT: return X86::COND_L;
3715 case ISD::SETLE: return X86::COND_LE;
3716 case ISD::SETNE: return X86::COND_NE;
3717 case ISD::SETULT: return X86::COND_B;
3718 case ISD::SETUGT: return X86::COND_A;
3719 case ISD::SETULE: return X86::COND_BE;
3720 case ISD::SETUGE: return X86::COND_AE;
3724 // First determine if it is required or is profitable to flip the operands.
3726 // If LHS is a foldable load, but RHS is not, flip the condition.
3727 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3728 !ISD::isNON_EXTLoad(RHS.getNode())) {
3729 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3730 std::swap(LHS, RHS);
3733 switch (SetCCOpcode) {
3739 std::swap(LHS, RHS);
3743 // On a floating point condition, the flags are set as follows:
3745 // 0 | 0 | 0 | X > Y
3746 // 0 | 0 | 1 | X < Y
3747 // 1 | 0 | 0 | X == Y
3748 // 1 | 1 | 1 | unordered
3749 switch (SetCCOpcode) {
3750 default: llvm_unreachable("Condcode should be pre-legalized away");
3752 case ISD::SETEQ: return X86::COND_E;
3753 case ISD::SETOLT: // flipped
3755 case ISD::SETGT: return X86::COND_A;
3756 case ISD::SETOLE: // flipped
3758 case ISD::SETGE: return X86::COND_AE;
3759 case ISD::SETUGT: // flipped
3761 case ISD::SETLT: return X86::COND_B;
3762 case ISD::SETUGE: // flipped
3764 case ISD::SETLE: return X86::COND_BE;
3766 case ISD::SETNE: return X86::COND_NE;
3767 case ISD::SETUO: return X86::COND_P;
3768 case ISD::SETO: return X86::COND_NP;
3770 case ISD::SETUNE: return X86::COND_INVALID;
3774 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3775 /// code. Current x86 isa includes the following FP cmov instructions:
3776 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3777 static bool hasFPCMov(unsigned X86CC) {
3793 /// isFPImmLegal - Returns true if the target can instruction select the
3794 /// specified FP immediate natively. If false, the legalizer will
3795 /// materialize the FP immediate as a load from a constant pool.
3796 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3797 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3798 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3804 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3805 ISD::LoadExtType ExtTy,
3807 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3808 // relocation target a movq or addq instruction: don't let the load shrink.
3809 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3810 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3811 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3812 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3816 /// \brief Returns true if it is beneficial to convert a load of a constant
3817 /// to just the constant itself.
3818 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3820 assert(Ty->isIntegerTy());
3822 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3823 if (BitSize == 0 || BitSize > 64)
3828 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3829 unsigned Index) const {
3830 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3833 return (Index == 0 || Index == ResVT.getVectorNumElements());
3836 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3837 // Speculate cttz only if we can directly use TZCNT.
3838 return Subtarget->hasBMI();
3841 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3842 // Speculate ctlz only if we can directly use LZCNT.
3843 return Subtarget->hasLZCNT();
3846 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3847 /// the specified range (L, H].
3848 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3849 return (Val < 0) || (Val >= Low && Val < Hi);
3852 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3853 /// specified value.
3854 static bool isUndefOrEqual(int Val, int CmpVal) {
3855 return (Val < 0 || Val == CmpVal);
3858 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3859 /// from position Pos and ending in Pos+Size, falls within the specified
3860 /// sequential range (Low, Low+Size]. or is undef.
3861 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3862 unsigned Pos, unsigned Size, int Low) {
3863 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3864 if (!isUndefOrEqual(Mask[i], Low))
3869 /// isVEXTRACTIndex - Return true if the specified
3870 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3871 /// suitable for instruction that extract 128 or 256 bit vectors
3872 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3873 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3874 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3877 // The index should be aligned on a vecWidth-bit boundary.
3879 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3881 MVT VT = N->getSimpleValueType(0);
3882 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3883 bool Result = (Index * ElSize) % vecWidth == 0;
3888 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3889 /// operand specifies a subvector insert that is suitable for input to
3890 /// insertion of 128 or 256-bit subvectors
3891 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3892 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3893 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3895 // The index should be aligned on a vecWidth-bit boundary.
3897 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3899 MVT VT = N->getSimpleValueType(0);
3900 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3901 bool Result = (Index * ElSize) % vecWidth == 0;
3906 bool X86::isVINSERT128Index(SDNode *N) {
3907 return isVINSERTIndex(N, 128);
3910 bool X86::isVINSERT256Index(SDNode *N) {
3911 return isVINSERTIndex(N, 256);
3914 bool X86::isVEXTRACT128Index(SDNode *N) {
3915 return isVEXTRACTIndex(N, 128);
3918 bool X86::isVEXTRACT256Index(SDNode *N) {
3919 return isVEXTRACTIndex(N, 256);
3922 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3923 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3924 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3925 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3928 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3930 MVT VecVT = N->getOperand(0).getSimpleValueType();
3931 MVT ElVT = VecVT.getVectorElementType();
3933 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3934 return Index / NumElemsPerChunk;
3937 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3938 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3939 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3940 llvm_unreachable("Illegal insert subvector for VINSERT");
3943 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3945 MVT VecVT = N->getSimpleValueType(0);
3946 MVT ElVT = VecVT.getVectorElementType();
3948 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3949 return Index / NumElemsPerChunk;
3952 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3953 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3954 /// and VINSERTI128 instructions.
3955 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3956 return getExtractVEXTRACTImmediate(N, 128);
3959 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3960 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3961 /// and VINSERTI64x4 instructions.
3962 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3963 return getExtractVEXTRACTImmediate(N, 256);
3966 /// getInsertVINSERT128Immediate - Return the appropriate immediate
3967 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3968 /// and VINSERTI128 instructions.
3969 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
3970 return getInsertVINSERTImmediate(N, 128);
3973 /// getInsertVINSERT256Immediate - Return the appropriate immediate
3974 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
3975 /// and VINSERTI64x4 instructions.
3976 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
3977 return getInsertVINSERTImmediate(N, 256);
3980 /// isZero - Returns true if Elt is a constant integer zero
3981 static bool isZero(SDValue V) {
3982 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
3983 return C && C->isNullValue();
3986 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3988 bool X86::isZeroNode(SDValue Elt) {
3991 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
3992 return CFP->getValueAPF().isPosZero();
3996 /// getZeroVector - Returns a vector of specified type with all zero elements.
3998 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
3999 SelectionDAG &DAG, SDLoc dl) {
4000 assert(VT.isVector() && "Expected a vector type");
4002 // Always build SSE zero vectors as <4 x i32> bitcasted
4003 // to their dest type. This ensures they get CSE'd.
4005 if (VT.is128BitVector()) { // SSE
4006 if (Subtarget->hasSSE2()) { // SSE2
4007 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4008 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4010 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4011 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4013 } else if (VT.is256BitVector()) { // AVX
4014 if (Subtarget->hasInt256()) { // AVX2
4015 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4016 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4017 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4019 // 256-bit logic and arithmetic instructions in AVX are all
4020 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4021 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4022 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4023 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4025 } else if (VT.is512BitVector()) { // AVX-512
4026 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4027 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4028 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4029 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4030 } else if (VT.getScalarType() == MVT::i1) {
4032 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4033 && "Unexpected vector type");
4034 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4035 && "Unexpected vector type");
4036 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4037 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4038 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4040 llvm_unreachable("Unexpected vector type");
4042 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4045 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4046 SelectionDAG &DAG, SDLoc dl,
4047 unsigned vectorWidth) {
4048 assert((vectorWidth == 128 || vectorWidth == 256) &&
4049 "Unsupported vector width");
4050 EVT VT = Vec.getValueType();
4051 EVT ElVT = VT.getVectorElementType();
4052 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4053 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4054 VT.getVectorNumElements()/Factor);
4056 // Extract from UNDEF is UNDEF.
4057 if (Vec.getOpcode() == ISD::UNDEF)
4058 return DAG.getUNDEF(ResultVT);
4060 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4061 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4063 // This is the index of the first element of the vectorWidth-bit chunk
4065 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4068 // If the input is a buildvector just emit a smaller one.
4069 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4070 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4071 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4074 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4075 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4078 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4079 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4080 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4081 /// instructions or a simple subregister reference. Idx is an index in the
4082 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4083 /// lowering EXTRACT_VECTOR_ELT operations easier.
4084 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4085 SelectionDAG &DAG, SDLoc dl) {
4086 assert((Vec.getValueType().is256BitVector() ||
4087 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4088 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4091 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4092 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4093 SelectionDAG &DAG, SDLoc dl) {
4094 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4095 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4098 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4099 unsigned IdxVal, SelectionDAG &DAG,
4100 SDLoc dl, unsigned vectorWidth) {
4101 assert((vectorWidth == 128 || vectorWidth == 256) &&
4102 "Unsupported vector width");
4103 // Inserting UNDEF is Result
4104 if (Vec.getOpcode() == ISD::UNDEF)
4106 EVT VT = Vec.getValueType();
4107 EVT ElVT = VT.getVectorElementType();
4108 EVT ResultVT = Result.getValueType();
4110 // Insert the relevant vectorWidth bits.
4111 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4113 // This is the index of the first element of the vectorWidth-bit chunk
4115 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4118 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4119 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4122 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4123 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4124 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4125 /// simple superregister reference. Idx is an index in the 128 bits
4126 /// we want. It need not be aligned to a 128-bit boundary. That makes
4127 /// lowering INSERT_VECTOR_ELT operations easier.
4128 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4129 SelectionDAG &DAG, SDLoc dl) {
4130 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4132 // For insertion into the zero index (low half) of a 256-bit vector, it is
4133 // more efficient to generate a blend with immediate instead of an insert*128.
4134 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4135 // extend the subvector to the size of the result vector. Make sure that
4136 // we are not recursing on that node by checking for undef here.
4137 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4138 Result.getOpcode() != ISD::UNDEF) {
4139 EVT ResultVT = Result.getValueType();
4140 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4141 SDValue Undef = DAG.getUNDEF(ResultVT);
4142 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4145 // The blend instruction, and therefore its mask, depend on the data type.
4146 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4147 if (ScalarType.isFloatingPoint()) {
4148 // Choose either vblendps (float) or vblendpd (double).
4149 unsigned ScalarSize = ScalarType.getSizeInBits();
4150 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4151 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4152 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4153 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4156 const X86Subtarget &Subtarget =
4157 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4159 // AVX2 is needed for 256-bit integer blend support.
4160 // Integers must be cast to 32-bit because there is only vpblendd;
4161 // vpblendw can't be used for this because it has a handicapped mask.
4163 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4164 // is still more efficient than using the wrong domain vinsertf128 that
4165 // will be created by InsertSubVector().
4166 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4168 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4169 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4170 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4171 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4178 SelectionDAG &DAG, SDLoc dl) {
4179 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4180 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4183 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4184 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4185 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4186 /// large BUILD_VECTORS.
4187 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4188 unsigned NumElems, SelectionDAG &DAG,
4190 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4191 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4194 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4195 unsigned NumElems, SelectionDAG &DAG,
4197 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4198 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4201 /// getOnesVector - Returns a vector of specified type with all bits set.
4202 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4203 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4204 /// Then bitcast to their original type, ensuring they get CSE'd.
4205 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4207 assert(VT.isVector() && "Expected a vector type");
4209 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4211 if (VT.is256BitVector()) {
4212 if (HasInt256) { // AVX2
4213 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4214 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4216 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4217 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4219 } else if (VT.is128BitVector()) {
4220 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4222 llvm_unreachable("Unexpected vector type");
4224 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4227 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4228 /// operation of specified width.
4229 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4231 unsigned NumElems = VT.getVectorNumElements();
4232 SmallVector<int, 8> Mask;
4233 Mask.push_back(NumElems);
4234 for (unsigned i = 1; i != NumElems; ++i)
4236 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4239 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4240 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4242 unsigned NumElems = VT.getVectorNumElements();
4243 SmallVector<int, 8> Mask;
4244 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4246 Mask.push_back(i + NumElems);
4248 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4251 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4252 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4254 unsigned NumElems = VT.getVectorNumElements();
4255 SmallVector<int, 8> Mask;
4256 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4257 Mask.push_back(i + Half);
4258 Mask.push_back(i + NumElems + Half);
4260 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4263 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4264 /// vector of zero or undef vector. This produces a shuffle where the low
4265 /// element of V2 is swizzled into the zero/undef vector, landing at element
4266 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4267 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4269 const X86Subtarget *Subtarget,
4270 SelectionDAG &DAG) {
4271 MVT VT = V2.getSimpleValueType();
4273 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4274 unsigned NumElems = VT.getVectorNumElements();
4275 SmallVector<int, 16> MaskVec;
4276 for (unsigned i = 0; i != NumElems; ++i)
4277 // If this is the insertion idx, put the low elt of V2 here.
4278 MaskVec.push_back(i == Idx ? NumElems : i);
4279 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4282 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4283 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4284 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4285 /// shuffles which use a single input multiple times, and in those cases it will
4286 /// adjust the mask to only have indices within that single input.
4287 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4288 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4289 unsigned NumElems = VT.getVectorNumElements();
4293 bool IsFakeUnary = false;
4294 switch(N->getOpcode()) {
4295 case X86ISD::BLENDI:
4296 ImmN = N->getOperand(N->getNumOperands()-1);
4297 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4300 ImmN = N->getOperand(N->getNumOperands()-1);
4301 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4304 case X86ISD::UNPCKH:
4305 DecodeUNPCKHMask(VT, Mask);
4306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4308 case X86ISD::UNPCKL:
4309 DecodeUNPCKLMask(VT, Mask);
4310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4312 case X86ISD::MOVHLPS:
4313 DecodeMOVHLPSMask(NumElems, Mask);
4314 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4316 case X86ISD::MOVLHPS:
4317 DecodeMOVLHPSMask(NumElems, Mask);
4318 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4320 case X86ISD::PALIGNR:
4321 ImmN = N->getOperand(N->getNumOperands()-1);
4322 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4324 case X86ISD::PSHUFD:
4325 case X86ISD::VPERMILPI:
4326 ImmN = N->getOperand(N->getNumOperands()-1);
4327 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4330 case X86ISD::PSHUFHW:
4331 ImmN = N->getOperand(N->getNumOperands()-1);
4332 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4335 case X86ISD::PSHUFLW:
4336 ImmN = N->getOperand(N->getNumOperands()-1);
4337 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4340 case X86ISD::PSHUFB: {
4342 SDValue MaskNode = N->getOperand(1);
4343 while (MaskNode->getOpcode() == ISD::BITCAST)
4344 MaskNode = MaskNode->getOperand(0);
4346 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4347 // If we have a build-vector, then things are easy.
4348 EVT VT = MaskNode.getValueType();
4349 assert(VT.isVector() &&
4350 "Can't produce a non-vector with a build_vector!");
4351 if (!VT.isInteger())
4354 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4356 SmallVector<uint64_t, 32> RawMask;
4357 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4358 SDValue Op = MaskNode->getOperand(i);
4359 if (Op->getOpcode() == ISD::UNDEF) {
4360 RawMask.push_back((uint64_t)SM_SentinelUndef);
4363 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4366 APInt MaskElement = CN->getAPIntValue();
4368 // We now have to decode the element which could be any integer size and
4369 // extract each byte of it.
4370 for (int j = 0; j < NumBytesPerElement; ++j) {
4371 // Note that this is x86 and so always little endian: the low byte is
4372 // the first byte of the mask.
4373 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4374 MaskElement = MaskElement.lshr(8);
4377 DecodePSHUFBMask(RawMask, Mask);
4381 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4385 SDValue Ptr = MaskLoad->getBasePtr();
4386 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4387 Ptr->getOpcode() == X86ISD::WrapperRIP)
4388 Ptr = Ptr->getOperand(0);
4390 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4391 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4394 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4395 DecodePSHUFBMask(C, Mask);
4403 case X86ISD::VPERMI:
4404 ImmN = N->getOperand(N->getNumOperands()-1);
4405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4410 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4412 case X86ISD::VPERM2X128:
4413 ImmN = N->getOperand(N->getNumOperands()-1);
4414 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4415 if (Mask.empty()) return false;
4417 case X86ISD::MOVSLDUP:
4418 DecodeMOVSLDUPMask(VT, Mask);
4421 case X86ISD::MOVSHDUP:
4422 DecodeMOVSHDUPMask(VT, Mask);
4425 case X86ISD::MOVDDUP:
4426 DecodeMOVDDUPMask(VT, Mask);
4429 case X86ISD::MOVLHPD:
4430 case X86ISD::MOVLPD:
4431 case X86ISD::MOVLPS:
4432 // Not yet implemented
4434 default: llvm_unreachable("unknown target shuffle node");
4437 // If we have a fake unary shuffle, the shuffle mask is spread across two
4438 // inputs that are actually the same node. Re-map the mask to always point
4439 // into the first input.
4442 if (M >= (int)Mask.size())
4448 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4449 /// element of the result of the vector shuffle.
4450 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4453 return SDValue(); // Limit search depth.
4455 SDValue V = SDValue(N, 0);
4456 EVT VT = V.getValueType();
4457 unsigned Opcode = V.getOpcode();
4459 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4460 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4461 int Elt = SV->getMaskElt(Index);
4464 return DAG.getUNDEF(VT.getVectorElementType());
4466 unsigned NumElems = VT.getVectorNumElements();
4467 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4468 : SV->getOperand(1);
4469 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4472 // Recurse into target specific vector shuffles to find scalars.
4473 if (isTargetShuffle(Opcode)) {
4474 MVT ShufVT = V.getSimpleValueType();
4475 unsigned NumElems = ShufVT.getVectorNumElements();
4476 SmallVector<int, 16> ShuffleMask;
4479 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4482 int Elt = ShuffleMask[Index];
4484 return DAG.getUNDEF(ShufVT.getVectorElementType());
4486 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4488 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4492 // Actual nodes that may contain scalar elements
4493 if (Opcode == ISD::BITCAST) {
4494 V = V.getOperand(0);
4495 EVT SrcVT = V.getValueType();
4496 unsigned NumElems = VT.getVectorNumElements();
4498 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4502 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4503 return (Index == 0) ? V.getOperand(0)
4504 : DAG.getUNDEF(VT.getVectorElementType());
4506 if (V.getOpcode() == ISD::BUILD_VECTOR)
4507 return V.getOperand(Index);
4512 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4514 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4515 unsigned NumNonZero, unsigned NumZero,
4517 const X86Subtarget* Subtarget,
4518 const TargetLowering &TLI) {
4526 // SSE4.1 - use PINSRB to insert each byte directly.
4527 if (Subtarget->hasSSE41()) {
4528 for (unsigned i = 0; i < 16; ++i) {
4529 bool isNonZero = (NonZeros & (1 << i)) != 0;
4533 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4535 V = DAG.getUNDEF(MVT::v16i8);
4538 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4539 MVT::v16i8, V, Op.getOperand(i),
4540 DAG.getIntPtrConstant(i, dl));
4547 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4548 for (unsigned i = 0; i < 16; ++i) {
4549 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4550 if (ThisIsNonZero && First) {
4552 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4554 V = DAG.getUNDEF(MVT::v8i16);
4559 SDValue ThisElt, LastElt;
4560 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4561 if (LastIsNonZero) {
4562 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4563 MVT::i16, Op.getOperand(i-1));
4565 if (ThisIsNonZero) {
4566 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4567 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4568 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4570 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4574 if (ThisElt.getNode())
4575 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4576 DAG.getIntPtrConstant(i/2, dl));
4580 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4583 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4585 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4586 unsigned NumNonZero, unsigned NumZero,
4588 const X86Subtarget* Subtarget,
4589 const TargetLowering &TLI) {
4596 for (unsigned i = 0; i < 8; ++i) {
4597 bool isNonZero = (NonZeros & (1 << i)) != 0;
4601 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4603 V = DAG.getUNDEF(MVT::v8i16);
4606 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4607 MVT::v8i16, V, Op.getOperand(i),
4608 DAG.getIntPtrConstant(i, dl));
4615 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4616 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4617 const X86Subtarget *Subtarget,
4618 const TargetLowering &TLI) {
4619 // Find all zeroable elements.
4620 std::bitset<4> Zeroable;
4621 for (int i=0; i < 4; ++i) {
4622 SDValue Elt = Op->getOperand(i);
4623 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4625 assert(Zeroable.size() - Zeroable.count() > 1 &&
4626 "We expect at least two non-zero elements!");
4628 // We only know how to deal with build_vector nodes where elements are either
4629 // zeroable or extract_vector_elt with constant index.
4630 SDValue FirstNonZero;
4631 unsigned FirstNonZeroIdx;
4632 for (unsigned i=0; i < 4; ++i) {
4635 SDValue Elt = Op->getOperand(i);
4636 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4637 !isa<ConstantSDNode>(Elt.getOperand(1)))
4639 // Make sure that this node is extracting from a 128-bit vector.
4640 MVT VT = Elt.getOperand(0).getSimpleValueType();
4641 if (!VT.is128BitVector())
4643 if (!FirstNonZero.getNode()) {
4645 FirstNonZeroIdx = i;
4649 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4650 SDValue V1 = FirstNonZero.getOperand(0);
4651 MVT VT = V1.getSimpleValueType();
4653 // See if this build_vector can be lowered as a blend with zero.
4655 unsigned EltMaskIdx, EltIdx;
4657 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4658 if (Zeroable[EltIdx]) {
4659 // The zero vector will be on the right hand side.
4660 Mask[EltIdx] = EltIdx+4;
4664 Elt = Op->getOperand(EltIdx);
4665 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4666 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4667 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4669 Mask[EltIdx] = EltIdx;
4673 // Let the shuffle legalizer deal with blend operations.
4674 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4675 if (V1.getSimpleValueType() != VT)
4676 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4677 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4680 // See if we can lower this build_vector to a INSERTPS.
4681 if (!Subtarget->hasSSE41())
4684 SDValue V2 = Elt.getOperand(0);
4685 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4688 bool CanFold = true;
4689 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4693 SDValue Current = Op->getOperand(i);
4694 SDValue SrcVector = Current->getOperand(0);
4697 CanFold = SrcVector == V1 &&
4698 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4704 assert(V1.getNode() && "Expected at least two non-zero elements!");
4705 if (V1.getSimpleValueType() != MVT::v4f32)
4706 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4707 if (V2.getSimpleValueType() != MVT::v4f32)
4708 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4710 // Ok, we can emit an INSERTPS instruction.
4711 unsigned ZMask = Zeroable.to_ulong();
4713 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4714 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4716 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4717 DAG.getIntPtrConstant(InsertPSMask, DL));
4718 return DAG.getNode(ISD::BITCAST, DL, VT, Result);
4721 /// Return a vector logical shift node.
4722 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4723 unsigned NumBits, SelectionDAG &DAG,
4724 const TargetLowering &TLI, SDLoc dl) {
4725 assert(VT.is128BitVector() && "Unknown type for VShift");
4726 MVT ShVT = MVT::v2i64;
4727 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4728 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4729 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4730 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4731 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4732 return DAG.getNode(ISD::BITCAST, dl, VT,
4733 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4737 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4739 // Check if the scalar load can be widened into a vector load. And if
4740 // the address is "base + cst" see if the cst can be "absorbed" into
4741 // the shuffle mask.
4742 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4743 SDValue Ptr = LD->getBasePtr();
4744 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4746 EVT PVT = LD->getValueType(0);
4747 if (PVT != MVT::i32 && PVT != MVT::f32)
4752 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4753 FI = FINode->getIndex();
4755 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4756 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4757 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4758 Offset = Ptr.getConstantOperandVal(1);
4759 Ptr = Ptr.getOperand(0);
4764 // FIXME: 256-bit vector instructions don't require a strict alignment,
4765 // improve this code to support it better.
4766 unsigned RequiredAlign = VT.getSizeInBits()/8;
4767 SDValue Chain = LD->getChain();
4768 // Make sure the stack object alignment is at least 16 or 32.
4769 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4770 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4771 if (MFI->isFixedObjectIndex(FI)) {
4772 // Can't change the alignment. FIXME: It's possible to compute
4773 // the exact stack offset and reference FI + adjust offset instead.
4774 // If someone *really* cares about this. That's the way to implement it.
4777 MFI->setObjectAlignment(FI, RequiredAlign);
4781 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4782 // Ptr + (Offset & ~15).
4785 if ((Offset % RequiredAlign) & 3)
4787 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4790 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4791 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4794 int EltNo = (Offset - StartOffset) >> 2;
4795 unsigned NumElems = VT.getVectorNumElements();
4797 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4798 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4799 LD->getPointerInfo().getWithOffset(StartOffset),
4800 false, false, false, 0);
4802 SmallVector<int, 8> Mask(NumElems, EltNo);
4804 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4810 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4811 /// elements can be replaced by a single large load which has the same value as
4812 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4814 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4816 /// FIXME: we'd also like to handle the case where the last elements are zero
4817 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4818 /// There's even a handy isZeroNode for that purpose.
4819 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4820 SDLoc &DL, SelectionDAG &DAG,
4821 bool isAfterLegalize) {
4822 unsigned NumElems = Elts.size();
4824 LoadSDNode *LDBase = nullptr;
4825 unsigned LastLoadedElt = -1U;
4827 // For each element in the initializer, see if we've found a load or an undef.
4828 // If we don't find an initial load element, or later load elements are
4829 // non-consecutive, bail out.
4830 for (unsigned i = 0; i < NumElems; ++i) {
4831 SDValue Elt = Elts[i];
4832 // Look through a bitcast.
4833 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4834 Elt = Elt.getOperand(0);
4835 if (!Elt.getNode() ||
4836 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4839 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4841 LDBase = cast<LoadSDNode>(Elt.getNode());
4845 if (Elt.getOpcode() == ISD::UNDEF)
4848 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4849 EVT LdVT = Elt.getValueType();
4850 // Each loaded element must be the correct fractional portion of the
4851 // requested vector load.
4852 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4854 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4859 // If we have found an entire vector of loads and undefs, then return a large
4860 // load of the entire vector width starting at the base pointer. If we found
4861 // consecutive loads for the low half, generate a vzext_load node.
4862 if (LastLoadedElt == NumElems - 1) {
4863 assert(LDBase && "Did not find base load for merging consecutive loads");
4864 EVT EltVT = LDBase->getValueType(0);
4865 // Ensure that the input vector size for the merged loads matches the
4866 // cumulative size of the input elements.
4867 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4870 if (isAfterLegalize &&
4871 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4874 SDValue NewLd = SDValue();
4876 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4877 LDBase->getPointerInfo(), LDBase->isVolatile(),
4878 LDBase->isNonTemporal(), LDBase->isInvariant(),
4879 LDBase->getAlignment());
4881 if (LDBase->hasAnyUseOfValue(1)) {
4882 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4884 SDValue(NewLd.getNode(), 1));
4885 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4886 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4887 SDValue(NewLd.getNode(), 1));
4893 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4894 //of a v4i32 / v4f32. It's probably worth generalizing.
4895 EVT EltVT = VT.getVectorElementType();
4896 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4897 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4898 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4899 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4901 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4902 LDBase->getPointerInfo(),
4903 LDBase->getAlignment(),
4904 false/*isVolatile*/, true/*ReadMem*/,
4907 // Make sure the newly-created LOAD is in the same position as LDBase in
4908 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4909 // update uses of LDBase's output chain to use the TokenFactor.
4910 if (LDBase->hasAnyUseOfValue(1)) {
4911 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4912 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4913 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4914 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4915 SDValue(ResNode.getNode(), 1));
4918 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4923 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4924 /// to generate a splat value for the following cases:
4925 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4926 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4927 /// a scalar load, or a constant.
4928 /// The VBROADCAST node is returned when a pattern is found,
4929 /// or SDValue() otherwise.
4930 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4931 SelectionDAG &DAG) {
4932 // VBROADCAST requires AVX.
4933 // TODO: Splats could be generated for non-AVX CPUs using SSE
4934 // instructions, but there's less potential gain for only 128-bit vectors.
4935 if (!Subtarget->hasAVX())
4938 MVT VT = Op.getSimpleValueType();
4941 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4942 "Unsupported vector type for broadcast.");
4947 switch (Op.getOpcode()) {
4949 // Unknown pattern found.
4952 case ISD::BUILD_VECTOR: {
4953 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4954 BitVector UndefElements;
4955 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4957 // We need a splat of a single value to use broadcast, and it doesn't
4958 // make any sense if the value is only in one element of the vector.
4959 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4963 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4964 Ld.getOpcode() == ISD::ConstantFP);
4966 // Make sure that all of the users of a non-constant load are from the
4967 // BUILD_VECTOR node.
4968 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4973 case ISD::VECTOR_SHUFFLE: {
4974 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4976 // Shuffles must have a splat mask where the first element is
4978 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4981 SDValue Sc = Op.getOperand(0);
4982 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4983 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4985 if (!Subtarget->hasInt256())
4988 // Use the register form of the broadcast instruction available on AVX2.
4989 if (VT.getSizeInBits() >= 256)
4990 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4991 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4994 Ld = Sc.getOperand(0);
4995 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4996 Ld.getOpcode() == ISD::ConstantFP);
4998 // The scalar_to_vector node and the suspected
4999 // load node must have exactly one user.
5000 // Constants may have multiple users.
5002 // AVX-512 has register version of the broadcast
5003 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5004 Ld.getValueType().getSizeInBits() >= 32;
5005 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5012 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5013 bool IsGE256 = (VT.getSizeInBits() >= 256);
5015 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5016 // instruction to save 8 or more bytes of constant pool data.
5017 // TODO: If multiple splats are generated to load the same constant,
5018 // it may be detrimental to overall size. There needs to be a way to detect
5019 // that condition to know if this is truly a size win.
5020 const Function *F = DAG.getMachineFunction().getFunction();
5021 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5023 // Handle broadcasting a single constant scalar from the constant pool
5025 // On Sandybridge (no AVX2), it is still better to load a constant vector
5026 // from the constant pool and not to broadcast it from a scalar.
5027 // But override that restriction when optimizing for size.
5028 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5029 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5030 EVT CVT = Ld.getValueType();
5031 assert(!CVT.isVector() && "Must not broadcast a vector type");
5033 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5034 // For size optimization, also splat v2f64 and v2i64, and for size opt
5035 // with AVX2, also splat i8 and i16.
5036 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5037 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5038 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5039 const Constant *C = nullptr;
5040 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5041 C = CI->getConstantIntValue();
5042 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5043 C = CF->getConstantFPValue();
5045 assert(C && "Invalid constant type");
5047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5048 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5049 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5050 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5051 MachinePointerInfo::getConstantPool(),
5052 false, false, false, Alignment);
5054 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5058 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5060 // Handle AVX2 in-register broadcasts.
5061 if (!IsLoad && Subtarget->hasInt256() &&
5062 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5063 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5065 // The scalar source must be a normal load.
5069 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5070 (Subtarget->hasVLX() && ScalarSize == 64))
5071 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5073 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5074 // double since there is no vbroadcastsd xmm
5075 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5076 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5077 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5080 // Unsupported broadcast.
5084 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5085 /// underlying vector and index.
5087 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5089 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5091 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5092 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5095 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5097 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5099 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5100 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5103 // In this case the vector is the extract_subvector expression and the index
5104 // is 2, as specified by the shuffle.
5105 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5106 SDValue ShuffleVec = SVOp->getOperand(0);
5107 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5108 assert(ShuffleVecVT.getVectorElementType() ==
5109 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5111 int ShuffleIdx = SVOp->getMaskElt(Idx);
5112 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5113 ExtractedFromVec = ShuffleVec;
5119 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5120 MVT VT = Op.getSimpleValueType();
5122 // Skip if insert_vec_elt is not supported.
5123 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5124 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5128 unsigned NumElems = Op.getNumOperands();
5132 SmallVector<unsigned, 4> InsertIndices;
5133 SmallVector<int, 8> Mask(NumElems, -1);
5135 for (unsigned i = 0; i != NumElems; ++i) {
5136 unsigned Opc = Op.getOperand(i).getOpcode();
5138 if (Opc == ISD::UNDEF)
5141 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5142 // Quit if more than 1 elements need inserting.
5143 if (InsertIndices.size() > 1)
5146 InsertIndices.push_back(i);
5150 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5151 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5152 // Quit if non-constant index.
5153 if (!isa<ConstantSDNode>(ExtIdx))
5155 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5157 // Quit if extracted from vector of different type.
5158 if (ExtractedFromVec.getValueType() != VT)
5161 if (!VecIn1.getNode())
5162 VecIn1 = ExtractedFromVec;
5163 else if (VecIn1 != ExtractedFromVec) {
5164 if (!VecIn2.getNode())
5165 VecIn2 = ExtractedFromVec;
5166 else if (VecIn2 != ExtractedFromVec)
5167 // Quit if more than 2 vectors to shuffle
5171 if (ExtractedFromVec == VecIn1)
5173 else if (ExtractedFromVec == VecIn2)
5174 Mask[i] = Idx + NumElems;
5177 if (!VecIn1.getNode())
5180 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5181 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5182 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5183 unsigned Idx = InsertIndices[i];
5184 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5185 DAG.getIntPtrConstant(Idx, DL));
5191 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5193 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5195 MVT VT = Op.getSimpleValueType();
5196 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5197 "Unexpected type in LowerBUILD_VECTORvXi1!");
5200 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5201 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5202 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5203 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5206 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5207 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5208 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5209 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5212 bool AllContants = true;
5213 uint64_t Immediate = 0;
5214 int NonConstIdx = -1;
5215 bool IsSplat = true;
5216 unsigned NumNonConsts = 0;
5217 unsigned NumConsts = 0;
5218 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5219 SDValue In = Op.getOperand(idx);
5220 if (In.getOpcode() == ISD::UNDEF)
5222 if (!isa<ConstantSDNode>(In)) {
5223 AllContants = false;
5228 if (cast<ConstantSDNode>(In)->getZExtValue())
5229 Immediate |= (1ULL << idx);
5231 if (In != Op.getOperand(0))
5236 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5237 DAG.getConstant(Immediate, dl, MVT::i16));
5238 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5239 DAG.getIntPtrConstant(0, dl));
5242 if (NumNonConsts == 1 && NonConstIdx != 0) {
5245 SDValue VecAsImm = DAG.getConstant(Immediate, dl,
5246 MVT::getIntegerVT(VT.getSizeInBits()));
5247 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5250 DstVec = DAG.getUNDEF(VT);
5251 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5252 Op.getOperand(NonConstIdx),
5253 DAG.getIntPtrConstant(NonConstIdx, dl));
5255 if (!IsSplat && (NonConstIdx != 0))
5256 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5257 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5260 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5261 DAG.getConstant(-1, dl, SelectVT),
5262 DAG.getConstant(0, dl, SelectVT));
5264 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5265 DAG.getConstant((Immediate | 1), dl, SelectVT),
5266 DAG.getConstant(Immediate, dl, SelectVT));
5267 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5270 /// \brief Return true if \p N implements a horizontal binop and return the
5271 /// operands for the horizontal binop into V0 and V1.
5273 /// This is a helper function of LowerToHorizontalOp().
5274 /// This function checks that the build_vector \p N in input implements a
5275 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5276 /// operation to match.
5277 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5278 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5279 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5282 /// This function only analyzes elements of \p N whose indices are
5283 /// in range [BaseIdx, LastIdx).
5284 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5286 unsigned BaseIdx, unsigned LastIdx,
5287 SDValue &V0, SDValue &V1) {
5288 EVT VT = N->getValueType(0);
5290 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5291 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5292 "Invalid Vector in input!");
5294 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5295 bool CanFold = true;
5296 unsigned ExpectedVExtractIdx = BaseIdx;
5297 unsigned NumElts = LastIdx - BaseIdx;
5298 V0 = DAG.getUNDEF(VT);
5299 V1 = DAG.getUNDEF(VT);
5301 // Check if N implements a horizontal binop.
5302 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5303 SDValue Op = N->getOperand(i + BaseIdx);
5306 if (Op->getOpcode() == ISD::UNDEF) {
5307 // Update the expected vector extract index.
5308 if (i * 2 == NumElts)
5309 ExpectedVExtractIdx = BaseIdx;
5310 ExpectedVExtractIdx += 2;
5314 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5319 SDValue Op0 = Op.getOperand(0);
5320 SDValue Op1 = Op.getOperand(1);
5322 // Try to match the following pattern:
5323 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5324 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5325 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5326 Op0.getOperand(0) == Op1.getOperand(0) &&
5327 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5328 isa<ConstantSDNode>(Op1.getOperand(1)));
5332 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5333 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5335 if (i * 2 < NumElts) {
5336 if (V0.getOpcode() == ISD::UNDEF) {
5337 V0 = Op0.getOperand(0);
5338 if (V0.getValueType() != VT)
5342 if (V1.getOpcode() == ISD::UNDEF) {
5343 V1 = Op0.getOperand(0);
5344 if (V1.getValueType() != VT)
5347 if (i * 2 == NumElts)
5348 ExpectedVExtractIdx = BaseIdx;
5351 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5352 if (I0 == ExpectedVExtractIdx)
5353 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5354 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5355 // Try to match the following dag sequence:
5356 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5357 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5361 ExpectedVExtractIdx += 2;
5367 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5368 /// a concat_vector.
5370 /// This is a helper function of LowerToHorizontalOp().
5371 /// This function expects two 256-bit vectors called V0 and V1.
5372 /// At first, each vector is split into two separate 128-bit vectors.
5373 /// Then, the resulting 128-bit vectors are used to implement two
5374 /// horizontal binary operations.
5376 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5378 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5379 /// the two new horizontal binop.
5380 /// When Mode is set, the first horizontal binop dag node would take as input
5381 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5382 /// horizontal binop dag node would take as input the lower 128-bit of V1
5383 /// and the upper 128-bit of V1.
5385 /// HADD V0_LO, V0_HI
5386 /// HADD V1_LO, V1_HI
5388 /// Otherwise, the first horizontal binop dag node takes as input the lower
5389 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5390 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5392 /// HADD V0_LO, V1_LO
5393 /// HADD V0_HI, V1_HI
5395 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5396 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5397 /// the upper 128-bits of the result.
5398 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5399 SDLoc DL, SelectionDAG &DAG,
5400 unsigned X86Opcode, bool Mode,
5401 bool isUndefLO, bool isUndefHI) {
5402 EVT VT = V0.getValueType();
5403 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5404 "Invalid nodes in input!");
5406 unsigned NumElts = VT.getVectorNumElements();
5407 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5408 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5409 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5410 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5411 EVT NewVT = V0_LO.getValueType();
5413 SDValue LO = DAG.getUNDEF(NewVT);
5414 SDValue HI = DAG.getUNDEF(NewVT);
5417 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5418 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5419 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5420 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5421 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5423 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5424 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5425 V1_LO->getOpcode() != ISD::UNDEF))
5426 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5428 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5429 V1_HI->getOpcode() != ISD::UNDEF))
5430 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5433 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5436 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5438 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5439 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5440 EVT VT = BV->getValueType(0);
5441 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5442 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5446 unsigned NumElts = VT.getVectorNumElements();
5447 SDValue InVec0 = DAG.getUNDEF(VT);
5448 SDValue InVec1 = DAG.getUNDEF(VT);
5450 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5451 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5453 // Odd-numbered elements in the input build vector are obtained from
5454 // adding two integer/float elements.
5455 // Even-numbered elements in the input build vector are obtained from
5456 // subtracting two integer/float elements.
5457 unsigned ExpectedOpcode = ISD::FSUB;
5458 unsigned NextExpectedOpcode = ISD::FADD;
5459 bool AddFound = false;
5460 bool SubFound = false;
5462 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5463 SDValue Op = BV->getOperand(i);
5465 // Skip 'undef' values.
5466 unsigned Opcode = Op.getOpcode();
5467 if (Opcode == ISD::UNDEF) {
5468 std::swap(ExpectedOpcode, NextExpectedOpcode);
5472 // Early exit if we found an unexpected opcode.
5473 if (Opcode != ExpectedOpcode)
5476 SDValue Op0 = Op.getOperand(0);
5477 SDValue Op1 = Op.getOperand(1);
5479 // Try to match the following pattern:
5480 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5481 // Early exit if we cannot match that sequence.
5482 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5483 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5484 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5485 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5486 Op0.getOperand(1) != Op1.getOperand(1))
5489 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5493 // We found a valid add/sub node. Update the information accordingly.
5499 // Update InVec0 and InVec1.
5500 if (InVec0.getOpcode() == ISD::UNDEF) {
5501 InVec0 = Op0.getOperand(0);
5502 if (InVec0.getValueType() != VT)
5505 if (InVec1.getOpcode() == ISD::UNDEF) {
5506 InVec1 = Op1.getOperand(0);
5507 if (InVec1.getValueType() != VT)
5511 // Make sure that operands in input to each add/sub node always
5512 // come from a same pair of vectors.
5513 if (InVec0 != Op0.getOperand(0)) {
5514 if (ExpectedOpcode == ISD::FSUB)
5517 // FADD is commutable. Try to commute the operands
5518 // and then test again.
5519 std::swap(Op0, Op1);
5520 if (InVec0 != Op0.getOperand(0))
5524 if (InVec1 != Op1.getOperand(0))
5527 // Update the pair of expected opcodes.
5528 std::swap(ExpectedOpcode, NextExpectedOpcode);
5531 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5532 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5533 InVec1.getOpcode() != ISD::UNDEF)
5534 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5539 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5540 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5541 const X86Subtarget *Subtarget,
5542 SelectionDAG &DAG) {
5543 EVT VT = BV->getValueType(0);
5544 unsigned NumElts = VT.getVectorNumElements();
5545 unsigned NumUndefsLO = 0;
5546 unsigned NumUndefsHI = 0;
5547 unsigned Half = NumElts/2;
5549 // Count the number of UNDEF operands in the build_vector in input.
5550 for (unsigned i = 0, e = Half; i != e; ++i)
5551 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5554 for (unsigned i = Half, e = NumElts; i != e; ++i)
5555 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5558 // Early exit if this is either a build_vector of all UNDEFs or all the
5559 // operands but one are UNDEF.
5560 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5564 SDValue InVec0, InVec1;
5565 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5566 // Try to match an SSE3 float HADD/HSUB.
5567 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5568 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5570 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5571 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5572 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5573 // Try to match an SSSE3 integer HADD/HSUB.
5574 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5575 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5577 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5578 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5581 if (!Subtarget->hasAVX())
5584 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5585 // Try to match an AVX horizontal add/sub of packed single/double
5586 // precision floating point values from 256-bit vectors.
5587 SDValue InVec2, InVec3;
5588 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5589 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5590 ((InVec0.getOpcode() == ISD::UNDEF ||
5591 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5592 ((InVec1.getOpcode() == ISD::UNDEF ||
5593 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5594 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5596 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5597 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5598 ((InVec0.getOpcode() == ISD::UNDEF ||
5599 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5600 ((InVec1.getOpcode() == ISD::UNDEF ||
5601 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5602 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5603 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5604 // Try to match an AVX2 horizontal add/sub of signed integers.
5605 SDValue InVec2, InVec3;
5607 bool CanFold = true;
5609 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5610 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5611 ((InVec0.getOpcode() == ISD::UNDEF ||
5612 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5613 ((InVec1.getOpcode() == ISD::UNDEF ||
5614 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5615 X86Opcode = X86ISD::HADD;
5616 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5617 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5618 ((InVec0.getOpcode() == ISD::UNDEF ||
5619 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5620 ((InVec1.getOpcode() == ISD::UNDEF ||
5621 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5622 X86Opcode = X86ISD::HSUB;
5627 // Fold this build_vector into a single horizontal add/sub.
5628 // Do this only if the target has AVX2.
5629 if (Subtarget->hasAVX2())
5630 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5632 // Do not try to expand this build_vector into a pair of horizontal
5633 // add/sub if we can emit a pair of scalar add/sub.
5634 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5637 // Convert this build_vector into a pair of horizontal binop followed by
5639 bool isUndefLO = NumUndefsLO == Half;
5640 bool isUndefHI = NumUndefsHI == Half;
5641 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5642 isUndefLO, isUndefHI);
5646 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5647 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5649 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5650 X86Opcode = X86ISD::HADD;
5651 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5652 X86Opcode = X86ISD::HSUB;
5653 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5654 X86Opcode = X86ISD::FHADD;
5655 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5656 X86Opcode = X86ISD::FHSUB;
5660 // Don't try to expand this build_vector into a pair of horizontal add/sub
5661 // if we can simply emit a pair of scalar add/sub.
5662 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5665 // Convert this build_vector into two horizontal add/sub followed by
5667 bool isUndefLO = NumUndefsLO == Half;
5668 bool isUndefHI = NumUndefsHI == Half;
5669 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5670 isUndefLO, isUndefHI);
5677 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5680 MVT VT = Op.getSimpleValueType();
5681 MVT ExtVT = VT.getVectorElementType();
5682 unsigned NumElems = Op.getNumOperands();
5684 // Generate vectors for predicate vectors.
5685 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5686 return LowerBUILD_VECTORvXi1(Op, DAG);
5688 // Vectors containing all zeros can be matched by pxor and xorps later
5689 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5690 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5691 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5692 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5695 return getZeroVector(VT, Subtarget, DAG, dl);
5698 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5699 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5700 // vpcmpeqd on 256-bit vectors.
5701 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5702 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5705 if (!VT.is512BitVector())
5706 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5709 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5710 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5712 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5713 return HorizontalOp;
5714 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5717 unsigned EVTBits = ExtVT.getSizeInBits();
5719 unsigned NumZero = 0;
5720 unsigned NumNonZero = 0;
5721 unsigned NonZeros = 0;
5722 bool IsAllConstants = true;
5723 SmallSet<SDValue, 8> Values;
5724 for (unsigned i = 0; i < NumElems; ++i) {
5725 SDValue Elt = Op.getOperand(i);
5726 if (Elt.getOpcode() == ISD::UNDEF)
5729 if (Elt.getOpcode() != ISD::Constant &&
5730 Elt.getOpcode() != ISD::ConstantFP)
5731 IsAllConstants = false;
5732 if (X86::isZeroNode(Elt))
5735 NonZeros |= (1 << i);
5740 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5741 if (NumNonZero == 0)
5742 return DAG.getUNDEF(VT);
5744 // Special case for single non-zero, non-undef, element.
5745 if (NumNonZero == 1) {
5746 unsigned Idx = countTrailingZeros(NonZeros);
5747 SDValue Item = Op.getOperand(Idx);
5749 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5750 // the value are obviously zero, truncate the value to i32 and do the
5751 // insertion that way. Only do this if the value is non-constant or if the
5752 // value is a constant being inserted into element 0. It is cheaper to do
5753 // a constant pool load than it is to do a movd + shuffle.
5754 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5755 (!IsAllConstants || Idx == 0)) {
5756 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5758 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5759 EVT VecVT = MVT::v4i32;
5761 // Truncate the value (which may itself be a constant) to i32, and
5762 // convert it to a vector with movd (S2V+shuffle to zero extend).
5763 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5764 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5766 ISD::BITCAST, dl, VT,
5767 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5771 // If we have a constant or non-constant insertion into the low element of
5772 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5773 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5774 // depending on what the source datatype is.
5777 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5779 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5780 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5781 if (VT.is512BitVector()) {
5782 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5783 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5784 Item, DAG.getIntPtrConstant(0, dl));
5786 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5787 "Expected an SSE value type!");
5788 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5789 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5790 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5793 // We can't directly insert an i8 or i16 into a vector, so zero extend
5795 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5796 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5797 if (VT.is256BitVector()) {
5798 if (Subtarget->hasAVX()) {
5799 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5800 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5802 // Without AVX, we need to extend to a 128-bit vector and then
5803 // insert into the 256-bit vector.
5804 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5805 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5806 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5809 assert(VT.is128BitVector() && "Expected an SSE value type!");
5810 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5811 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5813 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5817 // Is it a vector logical left shift?
5818 if (NumElems == 2 && Idx == 1 &&
5819 X86::isZeroNode(Op.getOperand(0)) &&
5820 !X86::isZeroNode(Op.getOperand(1))) {
5821 unsigned NumBits = VT.getSizeInBits();
5822 return getVShift(true, VT,
5823 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5824 VT, Op.getOperand(1)),
5825 NumBits/2, DAG, *this, dl);
5828 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5831 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5832 // is a non-constant being inserted into an element other than the low one,
5833 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5834 // movd/movss) to move this into the low element, then shuffle it into
5836 if (EVTBits == 32) {
5837 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5838 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5842 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5843 if (Values.size() == 1) {
5844 if (EVTBits == 32) {
5845 // Instead of a shuffle like this:
5846 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5847 // Check if it's possible to issue this instead.
5848 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5849 unsigned Idx = countTrailingZeros(NonZeros);
5850 SDValue Item = Op.getOperand(Idx);
5851 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5852 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5857 // A vector full of immediates; various special cases are already
5858 // handled, so this is best done with a single constant-pool load.
5862 // For AVX-length vectors, see if we can use a vector load to get all of the
5863 // elements, otherwise build the individual 128-bit pieces and use
5864 // shuffles to put them in place.
5865 if (VT.is256BitVector() || VT.is512BitVector()) {
5866 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5868 // Check for a build vector of consecutive loads.
5869 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5872 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5874 // Build both the lower and upper subvector.
5875 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5876 makeArrayRef(&V[0], NumElems/2));
5877 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5878 makeArrayRef(&V[NumElems / 2], NumElems/2));
5880 // Recreate the wider vector with the lower and upper part.
5881 if (VT.is256BitVector())
5882 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5883 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5886 // Let legalizer expand 2-wide build_vectors.
5887 if (EVTBits == 64) {
5888 if (NumNonZero == 1) {
5889 // One half is zero or undef.
5890 unsigned Idx = countTrailingZeros(NonZeros);
5891 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5892 Op.getOperand(Idx));
5893 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5898 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5899 if (EVTBits == 8 && NumElems == 16)
5900 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5904 if (EVTBits == 16 && NumElems == 8)
5905 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5909 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5910 if (EVTBits == 32 && NumElems == 4)
5911 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5914 // If element VT is == 32 bits, turn it into a number of shuffles.
5915 SmallVector<SDValue, 8> V(NumElems);
5916 if (NumElems == 4 && NumZero > 0) {
5917 for (unsigned i = 0; i < 4; ++i) {
5918 bool isZero = !(NonZeros & (1 << i));
5920 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5922 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5925 for (unsigned i = 0; i < 2; ++i) {
5926 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5929 V[i] = V[i*2]; // Must be a zero vector.
5932 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5935 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5938 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5943 bool Reverse1 = (NonZeros & 0x3) == 2;
5944 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5948 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5949 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5951 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5954 if (Values.size() > 1 && VT.is128BitVector()) {
5955 // Check for a build vector of consecutive loads.
5956 for (unsigned i = 0; i < NumElems; ++i)
5957 V[i] = Op.getOperand(i);
5959 // Check for elements which are consecutive loads.
5960 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5963 // Check for a build vector from mostly shuffle plus few inserting.
5964 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
5967 // For SSE 4.1, use insertps to put the high elements into the low element.
5968 if (Subtarget->hasSSE41()) {
5970 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5971 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5973 Result = DAG.getUNDEF(VT);
5975 for (unsigned i = 1; i < NumElems; ++i) {
5976 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5977 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5978 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
5983 // Otherwise, expand into a number of unpckl*, start by extending each of
5984 // our (non-undef) elements to the full vector width with the element in the
5985 // bottom slot of the vector (which generates no code for SSE).
5986 for (unsigned i = 0; i < NumElems; ++i) {
5987 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5988 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5990 V[i] = DAG.getUNDEF(VT);
5993 // Next, we iteratively mix elements, e.g. for v4f32:
5994 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5995 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5996 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5997 unsigned EltStride = NumElems >> 1;
5998 while (EltStride != 0) {
5999 for (unsigned i = 0; i < EltStride; ++i) {
6000 // If V[i+EltStride] is undef and this is the first round of mixing,
6001 // then it is safe to just drop this shuffle: V[i] is already in the
6002 // right place, the one element (since it's the first round) being
6003 // inserted as undef can be dropped. This isn't safe for successive
6004 // rounds because they will permute elements within both vectors.
6005 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6006 EltStride == NumElems/2)
6009 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6018 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6019 // to create 256-bit vectors from two other 128-bit ones.
6020 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6022 MVT ResVT = Op.getSimpleValueType();
6024 assert((ResVT.is256BitVector() ||
6025 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6027 SDValue V1 = Op.getOperand(0);
6028 SDValue V2 = Op.getOperand(1);
6029 unsigned NumElems = ResVT.getVectorNumElements();
6030 if (ResVT.is256BitVector())
6031 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6033 if (Op.getNumOperands() == 4) {
6034 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6035 ResVT.getVectorNumElements()/2);
6036 SDValue V3 = Op.getOperand(2);
6037 SDValue V4 = Op.getOperand(3);
6038 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6039 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6041 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6044 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6045 const X86Subtarget *Subtarget,
6046 SelectionDAG & DAG) {
6048 MVT ResVT = Op.getSimpleValueType();
6049 unsigned NumOfOperands = Op.getNumOperands();
6051 assert(isPowerOf2_32(NumOfOperands) &&
6052 "Unexpected number of operands in CONCAT_VECTORS");
6054 if (NumOfOperands > 2) {
6055 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6056 ResVT.getVectorNumElements()/2);
6057 SmallVector<SDValue, 2> Ops;
6058 for (unsigned i = 0; i < NumOfOperands/2; i++)
6059 Ops.push_back(Op.getOperand(i));
6060 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6062 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6063 Ops.push_back(Op.getOperand(i));
6064 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6065 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6068 SDValue V1 = Op.getOperand(0);
6069 SDValue V2 = Op.getOperand(1);
6070 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6071 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6073 if (IsZeroV1 && IsZeroV2)
6074 return getZeroVector(ResVT, Subtarget, DAG, dl);
6076 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6077 SDValue Undef = DAG.getUNDEF(ResVT);
6078 unsigned NumElems = ResVT.getVectorNumElements();
6079 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6081 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6082 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6086 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6087 // Zero the upper bits of V1
6088 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6089 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6092 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6095 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6096 const X86Subtarget *Subtarget,
6097 SelectionDAG &DAG) {
6098 MVT VT = Op.getSimpleValueType();
6099 if (VT.getVectorElementType() == MVT::i1)
6100 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6102 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6103 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6104 Op.getNumOperands() == 4)));
6106 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6107 // from two other 128-bit ones.
6109 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6110 return LowerAVXCONCAT_VECTORS(Op, DAG);
6114 //===----------------------------------------------------------------------===//
6115 // Vector shuffle lowering
6117 // This is an experimental code path for lowering vector shuffles on x86. It is
6118 // designed to handle arbitrary vector shuffles and blends, gracefully
6119 // degrading performance as necessary. It works hard to recognize idiomatic
6120 // shuffles and lower them to optimal instruction patterns without leaving
6121 // a framework that allows reasonably efficient handling of all vector shuffle
6123 //===----------------------------------------------------------------------===//
6125 /// \brief Tiny helper function to identify a no-op mask.
6127 /// This is a somewhat boring predicate function. It checks whether the mask
6128 /// array input, which is assumed to be a single-input shuffle mask of the kind
6129 /// used by the X86 shuffle instructions (not a fully general
6130 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6131 /// in-place shuffle are 'no-op's.
6132 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6133 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6134 if (Mask[i] != -1 && Mask[i] != i)
6139 /// \brief Helper function to classify a mask as a single-input mask.
6141 /// This isn't a generic single-input test because in the vector shuffle
6142 /// lowering we canonicalize single inputs to be the first input operand. This
6143 /// means we can more quickly test for a single input by only checking whether
6144 /// an input from the second operand exists. We also assume that the size of
6145 /// mask corresponds to the size of the input vectors which isn't true in the
6146 /// fully general case.
6147 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6149 if (M >= (int)Mask.size())
6154 /// \brief Test whether there are elements crossing 128-bit lanes in this
6157 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6158 /// and we routinely test for these.
6159 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6160 int LaneSize = 128 / VT.getScalarSizeInBits();
6161 int Size = Mask.size();
6162 for (int i = 0; i < Size; ++i)
6163 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6168 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6170 /// This checks a shuffle mask to see if it is performing the same
6171 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6172 /// that it is also not lane-crossing. It may however involve a blend from the
6173 /// same lane of a second vector.
6175 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6176 /// non-trivial to compute in the face of undef lanes. The representation is
6177 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6178 /// entries from both V1 and V2 inputs to the wider mask.
6180 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6181 SmallVectorImpl<int> &RepeatedMask) {
6182 int LaneSize = 128 / VT.getScalarSizeInBits();
6183 RepeatedMask.resize(LaneSize, -1);
6184 int Size = Mask.size();
6185 for (int i = 0; i < Size; ++i) {
6188 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6189 // This entry crosses lanes, so there is no way to model this shuffle.
6192 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6193 if (RepeatedMask[i % LaneSize] == -1)
6194 // This is the first non-undef entry in this slot of a 128-bit lane.
6195 RepeatedMask[i % LaneSize] =
6196 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6197 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6198 // Found a mismatch with the repeated mask.
6204 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6207 /// This is a fast way to test a shuffle mask against a fixed pattern:
6209 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6211 /// It returns true if the mask is exactly as wide as the argument list, and
6212 /// each element of the mask is either -1 (signifying undef) or the value given
6213 /// in the argument.
6214 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6215 ArrayRef<int> ExpectedMask) {
6216 if (Mask.size() != ExpectedMask.size())
6219 int Size = Mask.size();
6221 // If the values are build vectors, we can look through them to find
6222 // equivalent inputs that make the shuffles equivalent.
6223 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6224 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6226 for (int i = 0; i < Size; ++i)
6227 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6228 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6229 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6230 if (!MaskBV || !ExpectedBV ||
6231 MaskBV->getOperand(Mask[i] % Size) !=
6232 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6239 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6241 /// This helper function produces an 8-bit shuffle immediate corresponding to
6242 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6243 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6246 /// NB: We rely heavily on "undef" masks preserving the input lane.
6247 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6248 SelectionDAG &DAG) {
6249 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6250 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6251 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6252 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6253 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6256 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6257 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6258 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6259 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6260 return DAG.getConstant(Imm, DL, MVT::i8);
6263 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6265 /// This is used as a fallback approach when first class blend instructions are
6266 /// unavailable. Currently it is only suitable for integer vectors, but could
6267 /// be generalized for floating point vectors if desirable.
6268 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6269 SDValue V2, ArrayRef<int> Mask,
6270 SelectionDAG &DAG) {
6271 assert(VT.isInteger() && "Only supports integer vector types!");
6272 MVT EltVT = VT.getScalarType();
6273 int NumEltBits = EltVT.getSizeInBits();
6274 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6275 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6277 SmallVector<SDValue, 16> MaskOps;
6278 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6279 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6280 return SDValue(); // Shuffled input!
6281 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6284 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6285 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6286 // We have to cast V2 around.
6287 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6288 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6289 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6290 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6291 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6292 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6295 /// \brief Try to emit a blend instruction for a shuffle.
6297 /// This doesn't do any checks for the availability of instructions for blending
6298 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6299 /// be matched in the backend with the type given. What it does check for is
6300 /// that the shuffle mask is in fact a blend.
6301 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6302 SDValue V2, ArrayRef<int> Mask,
6303 const X86Subtarget *Subtarget,
6304 SelectionDAG &DAG) {
6305 unsigned BlendMask = 0;
6306 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6307 if (Mask[i] >= Size) {
6308 if (Mask[i] != i + Size)
6309 return SDValue(); // Shuffled V2 input!
6310 BlendMask |= 1u << i;
6313 if (Mask[i] >= 0 && Mask[i] != i)
6314 return SDValue(); // Shuffled V1 input!
6316 switch (VT.SimpleTy) {
6321 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6322 DAG.getConstant(BlendMask, DL, MVT::i8));
6326 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6330 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6331 // that instruction.
6332 if (Subtarget->hasAVX2()) {
6333 // Scale the blend by the number of 32-bit dwords per element.
6334 int Scale = VT.getScalarSizeInBits() / 32;
6336 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6337 if (Mask[i] >= Size)
6338 for (int j = 0; j < Scale; ++j)
6339 BlendMask |= 1u << (i * Scale + j);
6341 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6342 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6343 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6344 return DAG.getNode(ISD::BITCAST, DL, VT,
6345 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6346 DAG.getConstant(BlendMask, DL, MVT::i8)));
6350 // For integer shuffles we need to expand the mask and cast the inputs to
6351 // v8i16s prior to blending.
6352 int Scale = 8 / VT.getVectorNumElements();
6354 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6355 if (Mask[i] >= Size)
6356 for (int j = 0; j < Scale; ++j)
6357 BlendMask |= 1u << (i * Scale + j);
6359 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6361 return DAG.getNode(ISD::BITCAST, DL, VT,
6362 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6363 DAG.getConstant(BlendMask, DL, MVT::i8)));
6367 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6368 SmallVector<int, 8> RepeatedMask;
6369 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6370 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6371 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6373 for (int i = 0; i < 8; ++i)
6374 if (RepeatedMask[i] >= 16)
6375 BlendMask |= 1u << i;
6376 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6377 DAG.getConstant(BlendMask, DL, MVT::i8));
6383 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6384 "256-bit byte-blends require AVX2 support!");
6386 // Scale the blend by the number of bytes per element.
6387 int Scale = VT.getScalarSizeInBits() / 8;
6389 // This form of blend is always done on bytes. Compute the byte vector
6391 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6393 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6394 // mix of LLVM's code generator and the x86 backend. We tell the code
6395 // generator that boolean values in the elements of an x86 vector register
6396 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6397 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6398 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6399 // of the element (the remaining are ignored) and 0 in that high bit would
6400 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6401 // the LLVM model for boolean values in vector elements gets the relevant
6402 // bit set, it is set backwards and over constrained relative to x86's
6404 SmallVector<SDValue, 32> VSELECTMask;
6405 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6406 for (int j = 0; j < Scale; ++j)
6407 VSELECTMask.push_back(
6408 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6409 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6412 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6413 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6415 ISD::BITCAST, DL, VT,
6416 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6417 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6422 llvm_unreachable("Not a supported integer vector type!");
6426 /// \brief Try to lower as a blend of elements from two inputs followed by
6427 /// a single-input permutation.
6429 /// This matches the pattern where we can blend elements from two inputs and
6430 /// then reduce the shuffle to a single-input permutation.
6431 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6434 SelectionDAG &DAG) {
6435 // We build up the blend mask while checking whether a blend is a viable way
6436 // to reduce the shuffle.
6437 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6438 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6440 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6444 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6446 if (BlendMask[Mask[i] % Size] == -1)
6447 BlendMask[Mask[i] % Size] = Mask[i];
6448 else if (BlendMask[Mask[i] % Size] != Mask[i])
6449 return SDValue(); // Can't blend in the needed input!
6451 PermuteMask[i] = Mask[i] % Size;
6454 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6455 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6458 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6459 /// blends and permutes.
6461 /// This matches the extremely common pattern for handling combined
6462 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6463 /// operations. It will try to pick the best arrangement of shuffles and
6465 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6469 SelectionDAG &DAG) {
6470 // Shuffle the input elements into the desired positions in V1 and V2 and
6471 // blend them together.
6472 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6473 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6474 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6475 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6476 if (Mask[i] >= 0 && Mask[i] < Size) {
6477 V1Mask[i] = Mask[i];
6479 } else if (Mask[i] >= Size) {
6480 V2Mask[i] = Mask[i] - Size;
6481 BlendMask[i] = i + Size;
6484 // Try to lower with the simpler initial blend strategy unless one of the
6485 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6486 // shuffle may be able to fold with a load or other benefit. However, when
6487 // we'll have to do 2x as many shuffles in order to achieve this, blending
6488 // first is a better strategy.
6489 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6490 if (SDValue BlendPerm =
6491 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6494 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6495 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6496 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6499 /// \brief Try to lower a vector shuffle as a byte rotation.
6501 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6502 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6503 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6504 /// try to generically lower a vector shuffle through such an pattern. It
6505 /// does not check for the profitability of lowering either as PALIGNR or
6506 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6507 /// This matches shuffle vectors that look like:
6509 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6511 /// Essentially it concatenates V1 and V2, shifts right by some number of
6512 /// elements, and takes the low elements as the result. Note that while this is
6513 /// specified as a *right shift* because x86 is little-endian, it is a *left
6514 /// rotate* of the vector lanes.
6515 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6518 const X86Subtarget *Subtarget,
6519 SelectionDAG &DAG) {
6520 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6522 int NumElts = Mask.size();
6523 int NumLanes = VT.getSizeInBits() / 128;
6524 int NumLaneElts = NumElts / NumLanes;
6526 // We need to detect various ways of spelling a rotation:
6527 // [11, 12, 13, 14, 15, 0, 1, 2]
6528 // [-1, 12, 13, 14, -1, -1, 1, -1]
6529 // [-1, -1, -1, -1, -1, -1, 1, 2]
6530 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6531 // [-1, 4, 5, 6, -1, -1, 9, -1]
6532 // [-1, 4, 5, 6, -1, -1, -1, -1]
6535 for (int l = 0; l < NumElts; l += NumLaneElts) {
6536 for (int i = 0; i < NumLaneElts; ++i) {
6537 if (Mask[l + i] == -1)
6539 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6541 // Get the mod-Size index and lane correct it.
6542 int LaneIdx = (Mask[l + i] % NumElts) - l;
6543 // Make sure it was in this lane.
6544 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6547 // Determine where a rotated vector would have started.
6548 int StartIdx = i - LaneIdx;
6550 // The identity rotation isn't interesting, stop.
6553 // If we found the tail of a vector the rotation must be the missing
6554 // front. If we found the head of a vector, it must be how much of the
6556 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6559 Rotation = CandidateRotation;
6560 else if (Rotation != CandidateRotation)
6561 // The rotations don't match, so we can't match this mask.
6564 // Compute which value this mask is pointing at.
6565 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6567 // Compute which of the two target values this index should be assigned
6568 // to. This reflects whether the high elements are remaining or the low
6569 // elements are remaining.
6570 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6572 // Either set up this value if we've not encountered it before, or check
6573 // that it remains consistent.
6576 else if (TargetV != MaskV)
6577 // This may be a rotation, but it pulls from the inputs in some
6578 // unsupported interleaving.
6583 // Check that we successfully analyzed the mask, and normalize the results.
6584 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6585 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6591 // The actual rotate instruction rotates bytes, so we need to scale the
6592 // rotation based on how many bytes are in the vector lane.
6593 int Scale = 16 / NumLaneElts;
6595 // SSSE3 targets can use the palignr instruction.
6596 if (Subtarget->hasSSSE3()) {
6597 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6598 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6599 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6600 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6602 return DAG.getNode(ISD::BITCAST, DL, VT,
6603 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6604 DAG.getConstant(Rotation * Scale, DL,
6608 assert(VT.getSizeInBits() == 128 &&
6609 "Rotate-based lowering only supports 128-bit lowering!");
6610 assert(Mask.size() <= 16 &&
6611 "Can shuffle at most 16 bytes in a 128-bit vector!");
6613 // Default SSE2 implementation
6614 int LoByteShift = 16 - Rotation * Scale;
6615 int HiByteShift = Rotation * Scale;
6617 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6618 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6619 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6621 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6622 DAG.getConstant(LoByteShift, DL, MVT::i8));
6623 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6624 DAG.getConstant(HiByteShift, DL, MVT::i8));
6625 return DAG.getNode(ISD::BITCAST, DL, VT,
6626 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6629 /// \brief Compute whether each element of a shuffle is zeroable.
6631 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6632 /// Either it is an undef element in the shuffle mask, the element of the input
6633 /// referenced is undef, or the element of the input referenced is known to be
6634 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6635 /// as many lanes with this technique as possible to simplify the remaining
6637 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6638 SDValue V1, SDValue V2) {
6639 SmallBitVector Zeroable(Mask.size(), false);
6641 while (V1.getOpcode() == ISD::BITCAST)
6642 V1 = V1->getOperand(0);
6643 while (V2.getOpcode() == ISD::BITCAST)
6644 V2 = V2->getOperand(0);
6646 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6647 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6649 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6651 // Handle the easy cases.
6652 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6657 // If this is an index into a build_vector node (which has the same number
6658 // of elements), dig out the input value and use it.
6659 SDValue V = M < Size ? V1 : V2;
6660 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6663 SDValue Input = V.getOperand(M % Size);
6664 // The UNDEF opcode check really should be dead code here, but not quite
6665 // worth asserting on (it isn't invalid, just unexpected).
6666 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6673 /// \brief Try to emit a bitmask instruction for a shuffle.
6675 /// This handles cases where we can model a blend exactly as a bitmask due to
6676 /// one of the inputs being zeroable.
6677 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6678 SDValue V2, ArrayRef<int> Mask,
6679 SelectionDAG &DAG) {
6680 MVT EltVT = VT.getScalarType();
6681 int NumEltBits = EltVT.getSizeInBits();
6682 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6683 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6684 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6686 if (EltVT.isFloatingPoint()) {
6687 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6688 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6690 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6691 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6693 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6696 if (Mask[i] % Size != i)
6697 return SDValue(); // Not a blend.
6699 V = Mask[i] < Size ? V1 : V2;
6700 else if (V != (Mask[i] < Size ? V1 : V2))
6701 return SDValue(); // Can only let one input through the mask.
6703 VMaskOps[i] = AllOnes;
6706 return SDValue(); // No non-zeroable elements!
6708 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6709 V = DAG.getNode(VT.isFloatingPoint()
6710 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6715 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6717 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6718 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6719 /// matches elements from one of the input vectors shuffled to the left or
6720 /// right with zeroable elements 'shifted in'. It handles both the strictly
6721 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6724 /// PSHL : (little-endian) left bit shift.
6725 /// [ zz, 0, zz, 2 ]
6726 /// [ -1, 4, zz, -1 ]
6727 /// PSRL : (little-endian) right bit shift.
6729 /// [ -1, -1, 7, zz]
6730 /// PSLLDQ : (little-endian) left byte shift
6731 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6732 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6733 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6734 /// PSRLDQ : (little-endian) right byte shift
6735 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6736 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6737 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6738 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6739 SDValue V2, ArrayRef<int> Mask,
6740 SelectionDAG &DAG) {
6741 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6743 int Size = Mask.size();
6744 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6746 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6747 for (int i = 0; i < Size; i += Scale)
6748 for (int j = 0; j < Shift; ++j)
6749 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6755 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6756 for (int i = 0; i != Size; i += Scale) {
6757 unsigned Pos = Left ? i + Shift : i;
6758 unsigned Low = Left ? i : i + Shift;
6759 unsigned Len = Scale - Shift;
6760 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6761 Low + (V == V1 ? 0 : Size)))
6765 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6766 bool ByteShift = ShiftEltBits > 64;
6767 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6768 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6769 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6771 // Normalize the scale for byte shifts to still produce an i64 element
6773 Scale = ByteShift ? Scale / 2 : Scale;
6775 // We need to round trip through the appropriate type for the shift.
6776 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6777 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6778 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6779 "Illegal integer vector type");
6780 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6782 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6783 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6784 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6787 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6788 // keep doubling the size of the integer elements up to that. We can
6789 // then shift the elements of the integer vector by whole multiples of
6790 // their width within the elements of the larger integer vector. Test each
6791 // multiple to see if we can find a match with the moved element indices
6792 // and that the shifted in elements are all zeroable.
6793 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6794 for (int Shift = 1; Shift != Scale; ++Shift)
6795 for (bool Left : {true, false})
6796 if (CheckZeros(Shift, Scale, Left))
6797 for (SDValue V : {V1, V2})
6798 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6805 /// \brief Lower a vector shuffle as a zero or any extension.
6807 /// Given a specific number of elements, element bit width, and extension
6808 /// stride, produce either a zero or any extension based on the available
6809 /// features of the subtarget.
6810 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6811 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6812 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6813 assert(Scale > 1 && "Need a scale to extend.");
6814 int NumElements = VT.getVectorNumElements();
6815 int EltBits = VT.getScalarSizeInBits();
6816 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6817 "Only 8, 16, and 32 bit elements can be extended.");
6818 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6820 // Found a valid zext mask! Try various lowering strategies based on the
6821 // input type and available ISA extensions.
6822 if (Subtarget->hasSSE41()) {
6823 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6824 NumElements / Scale);
6825 return DAG.getNode(ISD::BITCAST, DL, VT,
6826 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6829 // For any extends we can cheat for larger element sizes and use shuffle
6830 // instructions that can fold with a load and/or copy.
6831 if (AnyExt && EltBits == 32) {
6832 int PSHUFDMask[4] = {0, -1, 1, -1};
6834 ISD::BITCAST, DL, VT,
6835 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6836 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6837 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6839 if (AnyExt && EltBits == 16 && Scale > 2) {
6840 int PSHUFDMask[4] = {0, -1, 0, -1};
6841 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6842 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6843 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6844 int PSHUFHWMask[4] = {1, -1, -1, -1};
6846 ISD::BITCAST, DL, VT,
6847 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6848 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6849 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6852 // If this would require more than 2 unpack instructions to expand, use
6853 // pshufb when available. We can only use more than 2 unpack instructions
6854 // when zero extending i8 elements which also makes it easier to use pshufb.
6855 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6856 assert(NumElements == 16 && "Unexpected byte vector width!");
6857 SDValue PSHUFBMask[16];
6858 for (int i = 0; i < 16; ++i)
6860 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6861 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6862 return DAG.getNode(ISD::BITCAST, DL, VT,
6863 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6864 DAG.getNode(ISD::BUILD_VECTOR, DL,
6865 MVT::v16i8, PSHUFBMask)));
6868 // Otherwise emit a sequence of unpacks.
6870 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6871 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6872 : getZeroVector(InputVT, Subtarget, DAG, DL);
6873 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6874 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6878 } while (Scale > 1);
6879 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6882 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6884 /// This routine will try to do everything in its power to cleverly lower
6885 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6886 /// check for the profitability of this lowering, it tries to aggressively
6887 /// match this pattern. It will use all of the micro-architectural details it
6888 /// can to emit an efficient lowering. It handles both blends with all-zero
6889 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6890 /// masking out later).
6892 /// The reason we have dedicated lowering for zext-style shuffles is that they
6893 /// are both incredibly common and often quite performance sensitive.
6894 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6895 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6896 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6897 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6899 int Bits = VT.getSizeInBits();
6900 int NumElements = VT.getVectorNumElements();
6901 assert(VT.getScalarSizeInBits() <= 32 &&
6902 "Exceeds 32-bit integer zero extension limit");
6903 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6905 // Define a helper function to check a particular ext-scale and lower to it if
6907 auto Lower = [&](int Scale) -> SDValue {
6910 for (int i = 0; i < NumElements; ++i) {
6912 continue; // Valid anywhere but doesn't tell us anything.
6913 if (i % Scale != 0) {
6914 // Each of the extended elements need to be zeroable.
6918 // We no longer are in the anyext case.
6923 // Each of the base elements needs to be consecutive indices into the
6924 // same input vector.
6925 SDValue V = Mask[i] < NumElements ? V1 : V2;
6928 else if (InputV != V)
6929 return SDValue(); // Flip-flopping inputs.
6931 if (Mask[i] % NumElements != i / Scale)
6932 return SDValue(); // Non-consecutive strided elements.
6935 // If we fail to find an input, we have a zero-shuffle which should always
6936 // have already been handled.
6937 // FIXME: Maybe handle this here in case during blending we end up with one?
6941 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6942 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6945 // The widest scale possible for extending is to a 64-bit integer.
6946 assert(Bits % 64 == 0 &&
6947 "The number of bits in a vector must be divisible by 64 on x86!");
6948 int NumExtElements = Bits / 64;
6950 // Each iteration, try extending the elements half as much, but into twice as
6952 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6953 assert(NumElements % NumExtElements == 0 &&
6954 "The input vector size must be divisible by the extended size.");
6955 if (SDValue V = Lower(NumElements / NumExtElements))
6959 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6963 // Returns one of the source operands if the shuffle can be reduced to a
6964 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6965 auto CanZExtLowHalf = [&]() {
6966 for (int i = NumElements / 2; i != NumElements; ++i)
6969 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6971 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6976 if (SDValue V = CanZExtLowHalf()) {
6977 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6978 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6979 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6982 // No viable ext lowering found.
6986 /// \brief Try to get a scalar value for a specific element of a vector.
6988 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6989 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6990 SelectionDAG &DAG) {
6991 MVT VT = V.getSimpleValueType();
6992 MVT EltVT = VT.getVectorElementType();
6993 while (V.getOpcode() == ISD::BITCAST)
6994 V = V.getOperand(0);
6995 // If the bitcasts shift the element size, we can't extract an equivalent
6997 MVT NewVT = V.getSimpleValueType();
6998 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7001 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7002 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7003 // Ensure the scalar operand is the same size as the destination.
7004 // FIXME: Add support for scalar truncation where possible.
7005 SDValue S = V.getOperand(Idx);
7006 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7007 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7013 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7015 /// This is particularly important because the set of instructions varies
7016 /// significantly based on whether the operand is a load or not.
7017 static bool isShuffleFoldableLoad(SDValue V) {
7018 while (V.getOpcode() == ISD::BITCAST)
7019 V = V.getOperand(0);
7021 return ISD::isNON_EXTLoad(V.getNode());
7024 /// \brief Try to lower insertion of a single element into a zero vector.
7026 /// This is a common pattern that we have especially efficient patterns to lower
7027 /// across all subtarget feature sets.
7028 static SDValue lowerVectorShuffleAsElementInsertion(
7029 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7030 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7031 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7033 MVT EltVT = VT.getVectorElementType();
7035 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7036 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7038 bool IsV1Zeroable = true;
7039 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7040 if (i != V2Index && !Zeroable[i]) {
7041 IsV1Zeroable = false;
7045 // Check for a single input from a SCALAR_TO_VECTOR node.
7046 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7047 // all the smarts here sunk into that routine. However, the current
7048 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7049 // vector shuffle lowering is dead.
7050 if (SDValue V2S = getScalarValueForVectorElement(
7051 V2, Mask[V2Index] - Mask.size(), DAG)) {
7052 // We need to zext the scalar if it is smaller than an i32.
7053 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7054 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7055 // Using zext to expand a narrow element won't work for non-zero
7060 // Zero-extend directly to i32.
7062 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7064 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7065 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7066 EltVT == MVT::i16) {
7067 // Either not inserting from the low element of the input or the input
7068 // element size is too small to use VZEXT_MOVL to clear the high bits.
7072 if (!IsV1Zeroable) {
7073 // If V1 can't be treated as a zero vector we have fewer options to lower
7074 // this. We can't support integer vectors or non-zero targets cheaply, and
7075 // the V1 elements can't be permuted in any way.
7076 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7077 if (!VT.isFloatingPoint() || V2Index != 0)
7079 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7080 V1Mask[V2Index] = -1;
7081 if (!isNoopShuffleMask(V1Mask))
7083 // This is essentially a special case blend operation, but if we have
7084 // general purpose blend operations, they are always faster. Bail and let
7085 // the rest of the lowering handle these as blends.
7086 if (Subtarget->hasSSE41())
7089 // Otherwise, use MOVSD or MOVSS.
7090 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7091 "Only two types of floating point element types to handle!");
7092 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7096 // This lowering only works for the low element with floating point vectors.
7097 if (VT.isFloatingPoint() && V2Index != 0)
7100 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7102 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7105 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7106 // the desired position. Otherwise it is more efficient to do a vector
7107 // shift left. We know that we can do a vector shift left because all
7108 // the inputs are zero.
7109 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7110 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7111 V2Shuffle[V2Index] = 0;
7112 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7114 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7116 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7118 V2Index * EltVT.getSizeInBits()/8, DL,
7119 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7120 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7126 /// \brief Try to lower broadcast of a single element.
7128 /// For convenience, this code also bundles all of the subtarget feature set
7129 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7130 /// a convenient way to factor it out.
7131 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7133 const X86Subtarget *Subtarget,
7134 SelectionDAG &DAG) {
7135 if (!Subtarget->hasAVX())
7137 if (VT.isInteger() && !Subtarget->hasAVX2())
7140 // Check that the mask is a broadcast.
7141 int BroadcastIdx = -1;
7143 if (M >= 0 && BroadcastIdx == -1)
7145 else if (M >= 0 && M != BroadcastIdx)
7148 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7149 "a sorted mask where the broadcast "
7152 // Go up the chain of (vector) values to find a scalar load that we can
7153 // combine with the broadcast.
7155 switch (V.getOpcode()) {
7156 case ISD::CONCAT_VECTORS: {
7157 int OperandSize = Mask.size() / V.getNumOperands();
7158 V = V.getOperand(BroadcastIdx / OperandSize);
7159 BroadcastIdx %= OperandSize;
7163 case ISD::INSERT_SUBVECTOR: {
7164 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7165 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7169 int BeginIdx = (int)ConstantIdx->getZExtValue();
7171 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7172 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7173 BroadcastIdx -= BeginIdx;
7184 // Check if this is a broadcast of a scalar. We special case lowering
7185 // for scalars so that we can more effectively fold with loads.
7186 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7187 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7188 V = V.getOperand(BroadcastIdx);
7190 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7191 // Only AVX2 has register broadcasts.
7192 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7194 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7195 // We can't broadcast from a vector register without AVX2, and we can only
7196 // broadcast from the zero-element of a vector register.
7200 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7203 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7204 // INSERTPS when the V1 elements are already in the correct locations
7205 // because otherwise we can just always use two SHUFPS instructions which
7206 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7207 // perform INSERTPS if a single V1 element is out of place and all V2
7208 // elements are zeroable.
7209 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7211 SelectionDAG &DAG) {
7212 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7213 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7214 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7215 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7217 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7220 int V1DstIndex = -1;
7221 int V2DstIndex = -1;
7222 bool V1UsedInPlace = false;
7224 for (int i = 0; i < 4; ++i) {
7225 // Synthesize a zero mask from the zeroable elements (includes undefs).
7231 // Flag if we use any V1 inputs in place.
7233 V1UsedInPlace = true;
7237 // We can only insert a single non-zeroable element.
7238 if (V1DstIndex != -1 || V2DstIndex != -1)
7242 // V1 input out of place for insertion.
7245 // V2 input for insertion.
7250 // Don't bother if we have no (non-zeroable) element for insertion.
7251 if (V1DstIndex == -1 && V2DstIndex == -1)
7254 // Determine element insertion src/dst indices. The src index is from the
7255 // start of the inserted vector, not the start of the concatenated vector.
7256 unsigned V2SrcIndex = 0;
7257 if (V1DstIndex != -1) {
7258 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7259 // and don't use the original V2 at all.
7260 V2SrcIndex = Mask[V1DstIndex];
7261 V2DstIndex = V1DstIndex;
7264 V2SrcIndex = Mask[V2DstIndex] - 4;
7267 // If no V1 inputs are used in place, then the result is created only from
7268 // the zero mask and the V2 insertion - so remove V1 dependency.
7270 V1 = DAG.getUNDEF(MVT::v4f32);
7272 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7273 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7275 // Insert the V2 element into the desired position.
7277 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7278 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7281 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7282 /// UNPCK instruction.
7284 /// This specifically targets cases where we end up with alternating between
7285 /// the two inputs, and so can permute them into something that feeds a single
7286 /// UNPCK instruction. Note that this routine only targets integer vectors
7287 /// because for floating point vectors we have a generalized SHUFPS lowering
7288 /// strategy that handles everything that doesn't *exactly* match an unpack,
7289 /// making this clever lowering unnecessary.
7290 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7291 SDValue V2, ArrayRef<int> Mask,
7292 SelectionDAG &DAG) {
7293 assert(!VT.isFloatingPoint() &&
7294 "This routine only supports integer vectors.");
7295 assert(!isSingleInputShuffleMask(Mask) &&
7296 "This routine should only be used when blending two inputs.");
7297 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7299 int Size = Mask.size();
7301 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7302 return M >= 0 && M % Size < Size / 2;
7304 int NumHiInputs = std::count_if(
7305 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7307 bool UnpackLo = NumLoInputs >= NumHiInputs;
7309 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7310 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7311 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7313 for (int i = 0; i < Size; ++i) {
7317 // Each element of the unpack contains Scale elements from this mask.
7318 int UnpackIdx = i / Scale;
7320 // We only handle the case where V1 feeds the first slots of the unpack.
7321 // We rely on canonicalization to ensure this is the case.
7322 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7325 // Setup the mask for this input. The indexing is tricky as we have to
7326 // handle the unpack stride.
7327 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7328 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7332 // If we will have to shuffle both inputs to use the unpack, check whether
7333 // we can just unpack first and shuffle the result. If so, skip this unpack.
7334 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7335 !isNoopShuffleMask(V2Mask))
7338 // Shuffle the inputs into place.
7339 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7340 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7342 // Cast the inputs to the type we will use to unpack them.
7343 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7344 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7346 // Unpack the inputs and cast the result back to the desired type.
7347 return DAG.getNode(ISD::BITCAST, DL, VT,
7348 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7349 DL, UnpackVT, V1, V2));
7352 // We try each unpack from the largest to the smallest to try and find one
7353 // that fits this mask.
7354 int OrigNumElements = VT.getVectorNumElements();
7355 int OrigScalarSize = VT.getScalarSizeInBits();
7356 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7357 int Scale = ScalarSize / OrigScalarSize;
7358 int NumElements = OrigNumElements / Scale;
7359 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7360 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7364 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7366 if (NumLoInputs == 0 || NumHiInputs == 0) {
7367 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7368 "We have to have *some* inputs!");
7369 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7371 // FIXME: We could consider the total complexity of the permute of each
7372 // possible unpacking. Or at the least we should consider how many
7373 // half-crossings are created.
7374 // FIXME: We could consider commuting the unpacks.
7376 SmallVector<int, 32> PermMask;
7377 PermMask.assign(Size, -1);
7378 for (int i = 0; i < Size; ++i) {
7382 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7385 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7387 return DAG.getVectorShuffle(
7388 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7390 DAG.getUNDEF(VT), PermMask);
7396 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7398 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7399 /// support for floating point shuffles but not integer shuffles. These
7400 /// instructions will incur a domain crossing penalty on some chips though so
7401 /// it is better to avoid lowering through this for integer vectors where
7403 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7404 const X86Subtarget *Subtarget,
7405 SelectionDAG &DAG) {
7407 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7408 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7409 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7410 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7411 ArrayRef<int> Mask = SVOp->getMask();
7412 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7414 if (isSingleInputShuffleMask(Mask)) {
7415 // Use low duplicate instructions for masks that match their pattern.
7416 if (Subtarget->hasSSE3())
7417 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7418 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7420 // Straight shuffle of a single input vector. Simulate this by using the
7421 // single input as both of the "inputs" to this instruction..
7422 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7424 if (Subtarget->hasAVX()) {
7425 // If we have AVX, we can use VPERMILPS which will allow folding a load
7426 // into the shuffle.
7427 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7428 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7431 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7432 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7434 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7435 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7437 // If we have a single input, insert that into V1 if we can do so cheaply.
7438 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7439 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7440 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7442 // Try inverting the insertion since for v2 masks it is easy to do and we
7443 // can't reliably sort the mask one way or the other.
7444 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7445 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7446 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7447 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7451 // Try to use one of the special instruction patterns to handle two common
7452 // blend patterns if a zero-blend above didn't work.
7453 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7454 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7455 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7456 // We can either use a special instruction to load over the low double or
7457 // to move just the low double.
7459 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7461 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7463 if (Subtarget->hasSSE41())
7464 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7468 // Use dedicated unpack instructions for masks that match their pattern.
7469 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7470 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7471 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7472 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7474 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7475 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7476 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7479 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7481 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7482 /// the integer unit to minimize domain crossing penalties. However, for blends
7483 /// it falls back to the floating point shuffle operation with appropriate bit
7485 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7486 const X86Subtarget *Subtarget,
7487 SelectionDAG &DAG) {
7489 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7490 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7491 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7493 ArrayRef<int> Mask = SVOp->getMask();
7494 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7496 if (isSingleInputShuffleMask(Mask)) {
7497 // Check for being able to broadcast a single element.
7498 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7499 Mask, Subtarget, DAG))
7502 // Straight shuffle of a single input vector. For everything from SSE2
7503 // onward this has a single fast instruction with no scary immediates.
7504 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7505 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7506 int WidenedMask[4] = {
7507 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7508 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7510 ISD::BITCAST, DL, MVT::v2i64,
7511 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7512 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7514 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7515 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7516 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7517 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7519 // If we have a blend of two PACKUS operations an the blend aligns with the
7520 // low and half halves, we can just merge the PACKUS operations. This is
7521 // particularly important as it lets us merge shuffles that this routine itself
7523 auto GetPackNode = [](SDValue V) {
7524 while (V.getOpcode() == ISD::BITCAST)
7525 V = V.getOperand(0);
7527 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7529 if (SDValue V1Pack = GetPackNode(V1))
7530 if (SDValue V2Pack = GetPackNode(V2))
7531 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7532 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7533 Mask[0] == 0 ? V1Pack.getOperand(0)
7534 : V1Pack.getOperand(1),
7535 Mask[1] == 2 ? V2Pack.getOperand(0)
7536 : V2Pack.getOperand(1)));
7538 // Try to use shift instructions.
7540 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7543 // When loading a scalar and then shuffling it into a vector we can often do
7544 // the insertion cheaply.
7545 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7546 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7548 // Try inverting the insertion since for v2 masks it is easy to do and we
7549 // can't reliably sort the mask one way or the other.
7550 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7551 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7552 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7555 // We have different paths for blend lowering, but they all must use the
7556 // *exact* same predicate.
7557 bool IsBlendSupported = Subtarget->hasSSE41();
7558 if (IsBlendSupported)
7559 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7563 // Use dedicated unpack instructions for masks that match their pattern.
7564 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7565 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7566 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7567 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7569 // Try to use byte rotation instructions.
7570 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7571 if (Subtarget->hasSSSE3())
7572 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7573 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7576 // If we have direct support for blends, we should lower by decomposing into
7577 // a permute. That will be faster than the domain cross.
7578 if (IsBlendSupported)
7579 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7582 // We implement this with SHUFPD which is pretty lame because it will likely
7583 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7584 // However, all the alternatives are still more cycles and newer chips don't
7585 // have this problem. It would be really nice if x86 had better shuffles here.
7586 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7587 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7588 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7589 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7592 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7594 /// This is used to disable more specialized lowerings when the shufps lowering
7595 /// will happen to be efficient.
7596 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7597 // This routine only handles 128-bit shufps.
7598 assert(Mask.size() == 4 && "Unsupported mask size!");
7600 // To lower with a single SHUFPS we need to have the low half and high half
7601 // each requiring a single input.
7602 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7604 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7610 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7612 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7613 /// It makes no assumptions about whether this is the *best* lowering, it simply
7615 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7616 ArrayRef<int> Mask, SDValue V1,
7617 SDValue V2, SelectionDAG &DAG) {
7618 SDValue LowV = V1, HighV = V2;
7619 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7622 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7624 if (NumV2Elements == 1) {
7626 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7629 // Compute the index adjacent to V2Index and in the same half by toggling
7631 int V2AdjIndex = V2Index ^ 1;
7633 if (Mask[V2AdjIndex] == -1) {
7634 // Handles all the cases where we have a single V2 element and an undef.
7635 // This will only ever happen in the high lanes because we commute the
7636 // vector otherwise.
7638 std::swap(LowV, HighV);
7639 NewMask[V2Index] -= 4;
7641 // Handle the case where the V2 element ends up adjacent to a V1 element.
7642 // To make this work, blend them together as the first step.
7643 int V1Index = V2AdjIndex;
7644 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7645 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7646 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7648 // Now proceed to reconstruct the final blend as we have the necessary
7649 // high or low half formed.
7656 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7657 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7659 } else if (NumV2Elements == 2) {
7660 if (Mask[0] < 4 && Mask[1] < 4) {
7661 // Handle the easy case where we have V1 in the low lanes and V2 in the
7665 } else if (Mask[2] < 4 && Mask[3] < 4) {
7666 // We also handle the reversed case because this utility may get called
7667 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7668 // arrange things in the right direction.
7674 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7675 // trying to place elements directly, just blend them and set up the final
7676 // shuffle to place them.
7678 // The first two blend mask elements are for V1, the second two are for
7680 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7681 Mask[2] < 4 ? Mask[2] : Mask[3],
7682 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7683 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7684 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7685 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7687 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7690 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7691 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7692 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7693 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7696 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7697 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7700 /// \brief Lower 4-lane 32-bit floating point shuffles.
7702 /// Uses instructions exclusively from the floating point unit to minimize
7703 /// domain crossing penalties, as these are sufficient to implement all v4f32
7705 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7706 const X86Subtarget *Subtarget,
7707 SelectionDAG &DAG) {
7709 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7710 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7711 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7713 ArrayRef<int> Mask = SVOp->getMask();
7714 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7717 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7719 if (NumV2Elements == 0) {
7720 // Check for being able to broadcast a single element.
7721 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7722 Mask, Subtarget, DAG))
7725 // Use even/odd duplicate instructions for masks that match their pattern.
7726 if (Subtarget->hasSSE3()) {
7727 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7728 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7729 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7730 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7733 if (Subtarget->hasAVX()) {
7734 // If we have AVX, we can use VPERMILPS which will allow folding a load
7735 // into the shuffle.
7736 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7737 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7740 // Otherwise, use a straight shuffle of a single input vector. We pass the
7741 // input vector to both operands to simulate this with a SHUFPS.
7742 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7743 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7746 // There are special ways we can lower some single-element blends. However, we
7747 // have custom ways we can lower more complex single-element blends below that
7748 // we defer to if both this and BLENDPS fail to match, so restrict this to
7749 // when the V2 input is targeting element 0 of the mask -- that is the fast
7751 if (NumV2Elements == 1 && Mask[0] >= 4)
7752 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7753 Mask, Subtarget, DAG))
7756 if (Subtarget->hasSSE41()) {
7757 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7761 // Use INSERTPS if we can complete the shuffle efficiently.
7762 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7765 if (!isSingleSHUFPSMask(Mask))
7766 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7767 DL, MVT::v4f32, V1, V2, Mask, DAG))
7771 // Use dedicated unpack instructions for masks that match their pattern.
7772 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7773 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7774 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7775 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7776 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7777 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7778 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7779 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7781 // Otherwise fall back to a SHUFPS lowering strategy.
7782 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7785 /// \brief Lower 4-lane i32 vector shuffles.
7787 /// We try to handle these with integer-domain shuffles where we can, but for
7788 /// blends we use the floating point domain blend instructions.
7789 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7790 const X86Subtarget *Subtarget,
7791 SelectionDAG &DAG) {
7793 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7794 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7795 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7796 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7797 ArrayRef<int> Mask = SVOp->getMask();
7798 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7800 // Whenever we can lower this as a zext, that instruction is strictly faster
7801 // than any alternative. It also allows us to fold memory operands into the
7802 // shuffle in many cases.
7803 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7804 Mask, Subtarget, DAG))
7808 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7810 if (NumV2Elements == 0) {
7811 // Check for being able to broadcast a single element.
7812 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7813 Mask, Subtarget, DAG))
7816 // Straight shuffle of a single input vector. For everything from SSE2
7817 // onward this has a single fast instruction with no scary immediates.
7818 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7819 // but we aren't actually going to use the UNPCK instruction because doing
7820 // so prevents folding a load into this instruction or making a copy.
7821 const int UnpackLoMask[] = {0, 0, 1, 1};
7822 const int UnpackHiMask[] = {2, 2, 3, 3};
7823 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7824 Mask = UnpackLoMask;
7825 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7826 Mask = UnpackHiMask;
7828 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7829 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7832 // Try to use shift instructions.
7834 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7837 // There are special ways we can lower some single-element blends.
7838 if (NumV2Elements == 1)
7839 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7840 Mask, Subtarget, DAG))
7843 // We have different paths for blend lowering, but they all must use the
7844 // *exact* same predicate.
7845 bool IsBlendSupported = Subtarget->hasSSE41();
7846 if (IsBlendSupported)
7847 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7851 if (SDValue Masked =
7852 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7855 // Use dedicated unpack instructions for masks that match their pattern.
7856 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7857 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7858 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7859 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7860 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7861 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7862 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7863 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7865 // Try to use byte rotation instructions.
7866 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7867 if (Subtarget->hasSSSE3())
7868 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7869 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7872 // If we have direct support for blends, we should lower by decomposing into
7873 // a permute. That will be faster than the domain cross.
7874 if (IsBlendSupported)
7875 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7878 // Try to lower by permuting the inputs into an unpack instruction.
7879 if (SDValue Unpack =
7880 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7883 // We implement this with SHUFPS because it can blend from two vectors.
7884 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7885 // up the inputs, bypassing domain shift penalties that we would encur if we
7886 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7888 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7889 DAG.getVectorShuffle(
7891 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7892 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7895 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7896 /// shuffle lowering, and the most complex part.
7898 /// The lowering strategy is to try to form pairs of input lanes which are
7899 /// targeted at the same half of the final vector, and then use a dword shuffle
7900 /// to place them onto the right half, and finally unpack the paired lanes into
7901 /// their final position.
7903 /// The exact breakdown of how to form these dword pairs and align them on the
7904 /// correct sides is really tricky. See the comments within the function for
7905 /// more of the details.
7907 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7908 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7909 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7910 /// vector, form the analogous 128-bit 8-element Mask.
7911 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7912 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7913 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7914 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7915 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7917 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7918 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7919 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7921 SmallVector<int, 4> LoInputs;
7922 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7923 [](int M) { return M >= 0; });
7924 std::sort(LoInputs.begin(), LoInputs.end());
7925 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7926 SmallVector<int, 4> HiInputs;
7927 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7928 [](int M) { return M >= 0; });
7929 std::sort(HiInputs.begin(), HiInputs.end());
7930 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7932 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7933 int NumHToL = LoInputs.size() - NumLToL;
7935 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7936 int NumHToH = HiInputs.size() - NumLToH;
7937 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7938 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7939 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7940 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7942 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7943 // such inputs we can swap two of the dwords across the half mark and end up
7944 // with <=2 inputs to each half in each half. Once there, we can fall through
7945 // to the generic code below. For example:
7947 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7948 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7950 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7951 // and an existing 2-into-2 on the other half. In this case we may have to
7952 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7953 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7954 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7955 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7956 // half than the one we target for fixing) will be fixed when we re-enter this
7957 // path. We will also combine away any sequence of PSHUFD instructions that
7958 // result into a single instruction. Here is an example of the tricky case:
7960 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7961 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7963 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7965 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7966 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7968 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7969 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7971 // The result is fine to be handled by the generic logic.
7972 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7973 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7974 int AOffset, int BOffset) {
7975 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7976 "Must call this with A having 3 or 1 inputs from the A half.");
7977 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7978 "Must call this with B having 1 or 3 inputs from the B half.");
7979 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7980 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7982 // Compute the index of dword with only one word among the three inputs in
7983 // a half by taking the sum of the half with three inputs and subtracting
7984 // the sum of the actual three inputs. The difference is the remaining
7987 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7988 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7989 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7990 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7991 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7992 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7993 int TripleNonInputIdx =
7994 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7995 TripleDWord = TripleNonInputIdx / 2;
7997 // We use xor with one to compute the adjacent DWord to whichever one the
7999 OneInputDWord = (OneInput / 2) ^ 1;
8001 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8002 // and BToA inputs. If there is also such a problem with the BToB and AToB
8003 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8004 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8005 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8006 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8007 // Compute how many inputs will be flipped by swapping these DWords. We
8009 // to balance this to ensure we don't form a 3-1 shuffle in the other
8011 int NumFlippedAToBInputs =
8012 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8013 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8014 int NumFlippedBToBInputs =
8015 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8016 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8017 if ((NumFlippedAToBInputs == 1 &&
8018 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8019 (NumFlippedBToBInputs == 1 &&
8020 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8021 // We choose whether to fix the A half or B half based on whether that
8022 // half has zero flipped inputs. At zero, we may not be able to fix it
8023 // with that half. We also bias towards fixing the B half because that
8024 // will more commonly be the high half, and we have to bias one way.
8025 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8026 ArrayRef<int> Inputs) {
8027 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8028 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8029 PinnedIdx ^ 1) != Inputs.end();
8030 // Determine whether the free index is in the flipped dword or the
8031 // unflipped dword based on where the pinned index is. We use this bit
8032 // in an xor to conditionally select the adjacent dword.
8033 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8034 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8035 FixFreeIdx) != Inputs.end();
8036 if (IsFixIdxInput == IsFixFreeIdxInput)
8038 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8039 FixFreeIdx) != Inputs.end();
8040 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8041 "We need to be changing the number of flipped inputs!");
8042 int PSHUFHalfMask[] = {0, 1, 2, 3};
8043 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8044 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8046 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8049 if (M != -1 && M == FixIdx)
8051 else if (M != -1 && M == FixFreeIdx)
8054 if (NumFlippedBToBInputs != 0) {
8056 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8057 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8059 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8061 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8062 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8067 int PSHUFDMask[] = {0, 1, 2, 3};
8068 PSHUFDMask[ADWord] = BDWord;
8069 PSHUFDMask[BDWord] = ADWord;
8070 V = DAG.getNode(ISD::BITCAST, DL, VT,
8071 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8072 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8073 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8076 // Adjust the mask to match the new locations of A and B.
8078 if (M != -1 && M/2 == ADWord)
8079 M = 2 * BDWord + M % 2;
8080 else if (M != -1 && M/2 == BDWord)
8081 M = 2 * ADWord + M % 2;
8083 // Recurse back into this routine to re-compute state now that this isn't
8084 // a 3 and 1 problem.
8085 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8088 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8089 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8090 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8091 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8093 // At this point there are at most two inputs to the low and high halves from
8094 // each half. That means the inputs can always be grouped into dwords and
8095 // those dwords can then be moved to the correct half with a dword shuffle.
8096 // We use at most one low and one high word shuffle to collect these paired
8097 // inputs into dwords, and finally a dword shuffle to place them.
8098 int PSHUFLMask[4] = {-1, -1, -1, -1};
8099 int PSHUFHMask[4] = {-1, -1, -1, -1};
8100 int PSHUFDMask[4] = {-1, -1, -1, -1};
8102 // First fix the masks for all the inputs that are staying in their
8103 // original halves. This will then dictate the targets of the cross-half
8105 auto fixInPlaceInputs =
8106 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8107 MutableArrayRef<int> SourceHalfMask,
8108 MutableArrayRef<int> HalfMask, int HalfOffset) {
8109 if (InPlaceInputs.empty())
8111 if (InPlaceInputs.size() == 1) {
8112 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8113 InPlaceInputs[0] - HalfOffset;
8114 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8117 if (IncomingInputs.empty()) {
8118 // Just fix all of the in place inputs.
8119 for (int Input : InPlaceInputs) {
8120 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8121 PSHUFDMask[Input / 2] = Input / 2;
8126 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8127 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8128 InPlaceInputs[0] - HalfOffset;
8129 // Put the second input next to the first so that they are packed into
8130 // a dword. We find the adjacent index by toggling the low bit.
8131 int AdjIndex = InPlaceInputs[0] ^ 1;
8132 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8133 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8134 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8136 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8137 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8139 // Now gather the cross-half inputs and place them into a free dword of
8140 // their target half.
8141 // FIXME: This operation could almost certainly be simplified dramatically to
8142 // look more like the 3-1 fixing operation.
8143 auto moveInputsToRightHalf = [&PSHUFDMask](
8144 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8145 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8146 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8148 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8149 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8151 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8153 int LowWord = Word & ~1;
8154 int HighWord = Word | 1;
8155 return isWordClobbered(SourceHalfMask, LowWord) ||
8156 isWordClobbered(SourceHalfMask, HighWord);
8159 if (IncomingInputs.empty())
8162 if (ExistingInputs.empty()) {
8163 // Map any dwords with inputs from them into the right half.
8164 for (int Input : IncomingInputs) {
8165 // If the source half mask maps over the inputs, turn those into
8166 // swaps and use the swapped lane.
8167 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8168 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8169 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8170 Input - SourceOffset;
8171 // We have to swap the uses in our half mask in one sweep.
8172 for (int &M : HalfMask)
8173 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8175 else if (M == Input)
8176 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8178 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8179 Input - SourceOffset &&
8180 "Previous placement doesn't match!");
8182 // Note that this correctly re-maps both when we do a swap and when
8183 // we observe the other side of the swap above. We rely on that to
8184 // avoid swapping the members of the input list directly.
8185 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8188 // Map the input's dword into the correct half.
8189 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8190 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8192 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8194 "Previous placement doesn't match!");
8197 // And just directly shift any other-half mask elements to be same-half
8198 // as we will have mirrored the dword containing the element into the
8199 // same position within that half.
8200 for (int &M : HalfMask)
8201 if (M >= SourceOffset && M < SourceOffset + 4) {
8202 M = M - SourceOffset + DestOffset;
8203 assert(M >= 0 && "This should never wrap below zero!");
8208 // Ensure we have the input in a viable dword of its current half. This
8209 // is particularly tricky because the original position may be clobbered
8210 // by inputs being moved and *staying* in that half.
8211 if (IncomingInputs.size() == 1) {
8212 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8213 int InputFixed = std::find(std::begin(SourceHalfMask),
8214 std::end(SourceHalfMask), -1) -
8215 std::begin(SourceHalfMask) + SourceOffset;
8216 SourceHalfMask[InputFixed - SourceOffset] =
8217 IncomingInputs[0] - SourceOffset;
8218 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8220 IncomingInputs[0] = InputFixed;
8222 } else if (IncomingInputs.size() == 2) {
8223 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8224 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8225 // We have two non-adjacent or clobbered inputs we need to extract from
8226 // the source half. To do this, we need to map them into some adjacent
8227 // dword slot in the source mask.
8228 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8229 IncomingInputs[1] - SourceOffset};
8231 // If there is a free slot in the source half mask adjacent to one of
8232 // the inputs, place the other input in it. We use (Index XOR 1) to
8233 // compute an adjacent index.
8234 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8235 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8236 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8237 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8238 InputsFixed[1] = InputsFixed[0] ^ 1;
8239 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8240 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8241 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8242 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8243 InputsFixed[0] = InputsFixed[1] ^ 1;
8244 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8245 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8246 // The two inputs are in the same DWord but it is clobbered and the
8247 // adjacent DWord isn't used at all. Move both inputs to the free
8249 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8250 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8251 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8252 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8254 // The only way we hit this point is if there is no clobbering
8255 // (because there are no off-half inputs to this half) and there is no
8256 // free slot adjacent to one of the inputs. In this case, we have to
8257 // swap an input with a non-input.
8258 for (int i = 0; i < 4; ++i)
8259 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8260 "We can't handle any clobbers here!");
8261 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8262 "Cannot have adjacent inputs here!");
8264 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8265 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8267 // We also have to update the final source mask in this case because
8268 // it may need to undo the above swap.
8269 for (int &M : FinalSourceHalfMask)
8270 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8271 M = InputsFixed[1] + SourceOffset;
8272 else if (M == InputsFixed[1] + SourceOffset)
8273 M = (InputsFixed[0] ^ 1) + SourceOffset;
8275 InputsFixed[1] = InputsFixed[0] ^ 1;
8278 // Point everything at the fixed inputs.
8279 for (int &M : HalfMask)
8280 if (M == IncomingInputs[0])
8281 M = InputsFixed[0] + SourceOffset;
8282 else if (M == IncomingInputs[1])
8283 M = InputsFixed[1] + SourceOffset;
8285 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8286 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8289 llvm_unreachable("Unhandled input size!");
8292 // Now hoist the DWord down to the right half.
8293 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8294 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8295 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8296 for (int &M : HalfMask)
8297 for (int Input : IncomingInputs)
8299 M = FreeDWord * 2 + Input % 2;
8301 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8302 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8303 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8304 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8306 // Now enact all the shuffles we've computed to move the inputs into their
8308 if (!isNoopShuffleMask(PSHUFLMask))
8309 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8310 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8311 if (!isNoopShuffleMask(PSHUFHMask))
8312 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8313 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8314 if (!isNoopShuffleMask(PSHUFDMask))
8315 V = DAG.getNode(ISD::BITCAST, DL, VT,
8316 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8317 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8318 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8321 // At this point, each half should contain all its inputs, and we can then
8322 // just shuffle them into their final position.
8323 assert(std::count_if(LoMask.begin(), LoMask.end(),
8324 [](int M) { return M >= 4; }) == 0 &&
8325 "Failed to lift all the high half inputs to the low mask!");
8326 assert(std::count_if(HiMask.begin(), HiMask.end(),
8327 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8328 "Failed to lift all the low half inputs to the high mask!");
8330 // Do a half shuffle for the low mask.
8331 if (!isNoopShuffleMask(LoMask))
8332 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8333 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8335 // Do a half shuffle with the high mask after shifting its values down.
8336 for (int &M : HiMask)
8339 if (!isNoopShuffleMask(HiMask))
8340 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8341 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8346 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8347 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8348 SDValue V2, ArrayRef<int> Mask,
8349 SelectionDAG &DAG, bool &V1InUse,
8351 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8357 int Size = Mask.size();
8358 int Scale = 16 / Size;
8359 for (int i = 0; i < 16; ++i) {
8360 if (Mask[i / Scale] == -1) {
8361 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8363 const int ZeroMask = 0x80;
8364 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8366 int V2Idx = Mask[i / Scale] < Size
8368 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8369 if (Zeroable[i / Scale])
8370 V1Idx = V2Idx = ZeroMask;
8371 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8372 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8373 V1InUse |= (ZeroMask != V1Idx);
8374 V2InUse |= (ZeroMask != V2Idx);
8379 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8380 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8381 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8383 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8384 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8385 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8387 // If we need shuffled inputs from both, blend the two.
8389 if (V1InUse && V2InUse)
8390 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8392 V = V1InUse ? V1 : V2;
8394 // Cast the result back to the correct type.
8395 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8398 /// \brief Generic lowering of 8-lane i16 shuffles.
8400 /// This handles both single-input shuffles and combined shuffle/blends with
8401 /// two inputs. The single input shuffles are immediately delegated to
8402 /// a dedicated lowering routine.
8404 /// The blends are lowered in one of three fundamental ways. If there are few
8405 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8406 /// of the input is significantly cheaper when lowered as an interleaving of
8407 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8408 /// halves of the inputs separately (making them have relatively few inputs)
8409 /// and then concatenate them.
8410 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8411 const X86Subtarget *Subtarget,
8412 SelectionDAG &DAG) {
8414 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8415 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8416 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8417 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8418 ArrayRef<int> OrigMask = SVOp->getMask();
8419 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8420 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8421 MutableArrayRef<int> Mask(MaskStorage);
8423 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8425 // Whenever we can lower this as a zext, that instruction is strictly faster
8426 // than any alternative.
8427 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8428 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8431 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8433 auto isV2 = [](int M) { return M >= 8; };
8435 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8437 if (NumV2Inputs == 0) {
8438 // Check for being able to broadcast a single element.
8439 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8440 Mask, Subtarget, DAG))
8443 // Try to use shift instructions.
8445 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8448 // Use dedicated unpack instructions for masks that match their pattern.
8449 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8450 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8451 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8452 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8454 // Try to use byte rotation instructions.
8455 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8456 Mask, Subtarget, DAG))
8459 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8463 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8464 "All single-input shuffles should be canonicalized to be V1-input "
8467 // Try to use shift instructions.
8469 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8472 // There are special ways we can lower some single-element blends.
8473 if (NumV2Inputs == 1)
8474 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8475 Mask, Subtarget, DAG))
8478 // We have different paths for blend lowering, but they all must use the
8479 // *exact* same predicate.
8480 bool IsBlendSupported = Subtarget->hasSSE41();
8481 if (IsBlendSupported)
8482 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8486 if (SDValue Masked =
8487 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8490 // Use dedicated unpack instructions for masks that match their pattern.
8491 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8492 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8493 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8494 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8496 // Try to use byte rotation instructions.
8497 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8498 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8501 if (SDValue BitBlend =
8502 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8505 if (SDValue Unpack =
8506 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8509 // If we can't directly blend but can use PSHUFB, that will be better as it
8510 // can both shuffle and set up the inefficient blend.
8511 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8512 bool V1InUse, V2InUse;
8513 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8517 // We can always bit-blend if we have to so the fallback strategy is to
8518 // decompose into single-input permutes and blends.
8519 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8523 /// \brief Check whether a compaction lowering can be done by dropping even
8524 /// elements and compute how many times even elements must be dropped.
8526 /// This handles shuffles which take every Nth element where N is a power of
8527 /// two. Example shuffle masks:
8529 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8530 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8531 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8532 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8533 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8534 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8536 /// Any of these lanes can of course be undef.
8538 /// This routine only supports N <= 3.
8539 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8542 /// \returns N above, or the number of times even elements must be dropped if
8543 /// there is such a number. Otherwise returns zero.
8544 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8545 // Figure out whether we're looping over two inputs or just one.
8546 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8548 // The modulus for the shuffle vector entries is based on whether this is
8549 // a single input or not.
8550 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8551 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8552 "We should only be called with masks with a power-of-2 size!");
8554 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8556 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8557 // and 2^3 simultaneously. This is because we may have ambiguity with
8558 // partially undef inputs.
8559 bool ViableForN[3] = {true, true, true};
8561 for (int i = 0, e = Mask.size(); i < e; ++i) {
8562 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8567 bool IsAnyViable = false;
8568 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8569 if (ViableForN[j]) {
8572 // The shuffle mask must be equal to (i * 2^N) % M.
8573 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8576 ViableForN[j] = false;
8578 // Early exit if we exhaust the possible powers of two.
8583 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8587 // Return 0 as there is no viable power of two.
8591 /// \brief Generic lowering of v16i8 shuffles.
8593 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8594 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8595 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8596 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8598 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8599 const X86Subtarget *Subtarget,
8600 SelectionDAG &DAG) {
8602 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8603 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8604 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8605 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8606 ArrayRef<int> Mask = SVOp->getMask();
8607 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8609 // Try to use shift instructions.
8611 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8614 // Try to use byte rotation instructions.
8615 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8616 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8619 // Try to use a zext lowering.
8620 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8621 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8625 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8627 // For single-input shuffles, there are some nicer lowering tricks we can use.
8628 if (NumV2Elements == 0) {
8629 // Check for being able to broadcast a single element.
8630 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8631 Mask, Subtarget, DAG))
8634 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8635 // Notably, this handles splat and partial-splat shuffles more efficiently.
8636 // However, it only makes sense if the pre-duplication shuffle simplifies
8637 // things significantly. Currently, this means we need to be able to
8638 // express the pre-duplication shuffle as an i16 shuffle.
8640 // FIXME: We should check for other patterns which can be widened into an
8641 // i16 shuffle as well.
8642 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8643 for (int i = 0; i < 16; i += 2)
8644 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8649 auto tryToWidenViaDuplication = [&]() -> SDValue {
8650 if (!canWidenViaDuplication(Mask))
8652 SmallVector<int, 4> LoInputs;
8653 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8654 [](int M) { return M >= 0 && M < 8; });
8655 std::sort(LoInputs.begin(), LoInputs.end());
8656 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8658 SmallVector<int, 4> HiInputs;
8659 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8660 [](int M) { return M >= 8; });
8661 std::sort(HiInputs.begin(), HiInputs.end());
8662 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8665 bool TargetLo = LoInputs.size() >= HiInputs.size();
8666 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8667 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8669 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8670 SmallDenseMap<int, int, 8> LaneMap;
8671 for (int I : InPlaceInputs) {
8672 PreDupI16Shuffle[I/2] = I/2;
8675 int j = TargetLo ? 0 : 4, je = j + 4;
8676 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8677 // Check if j is already a shuffle of this input. This happens when
8678 // there are two adjacent bytes after we move the low one.
8679 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8680 // If we haven't yet mapped the input, search for a slot into which
8682 while (j < je && PreDupI16Shuffle[j] != -1)
8686 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8689 // Map this input with the i16 shuffle.
8690 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8693 // Update the lane map based on the mapping we ended up with.
8694 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8697 ISD::BITCAST, DL, MVT::v16i8,
8698 DAG.getVectorShuffle(MVT::v8i16, DL,
8699 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8700 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8702 // Unpack the bytes to form the i16s that will be shuffled into place.
8703 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8704 MVT::v16i8, V1, V1);
8706 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8707 for (int i = 0; i < 16; ++i)
8708 if (Mask[i] != -1) {
8709 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8710 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8711 if (PostDupI16Shuffle[i / 2] == -1)
8712 PostDupI16Shuffle[i / 2] = MappedMask;
8714 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8715 "Conflicting entrties in the original shuffle!");
8718 ISD::BITCAST, DL, MVT::v16i8,
8719 DAG.getVectorShuffle(MVT::v8i16, DL,
8720 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8721 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8723 if (SDValue V = tryToWidenViaDuplication())
8727 // Use dedicated unpack instructions for masks that match their pattern.
8728 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8729 0, 16, 1, 17, 2, 18, 3, 19,
8731 4, 20, 5, 21, 6, 22, 7, 23}))
8732 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8733 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8734 8, 24, 9, 25, 10, 26, 11, 27,
8736 12, 28, 13, 29, 14, 30, 15, 31}))
8737 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8739 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8740 // with PSHUFB. It is important to do this before we attempt to generate any
8741 // blends but after all of the single-input lowerings. If the single input
8742 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8743 // want to preserve that and we can DAG combine any longer sequences into
8744 // a PSHUFB in the end. But once we start blending from multiple inputs,
8745 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8746 // and there are *very* few patterns that would actually be faster than the
8747 // PSHUFB approach because of its ability to zero lanes.
8749 // FIXME: The only exceptions to the above are blends which are exact
8750 // interleavings with direct instructions supporting them. We currently don't
8751 // handle those well here.
8752 if (Subtarget->hasSSSE3()) {
8753 bool V1InUse = false;
8754 bool V2InUse = false;
8756 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8757 DAG, V1InUse, V2InUse);
8759 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8760 // do so. This avoids using them to handle blends-with-zero which is
8761 // important as a single pshufb is significantly faster for that.
8762 if (V1InUse && V2InUse) {
8763 if (Subtarget->hasSSE41())
8764 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8765 Mask, Subtarget, DAG))
8768 // We can use an unpack to do the blending rather than an or in some
8769 // cases. Even though the or may be (very minorly) more efficient, we
8770 // preference this lowering because there are common cases where part of
8771 // the complexity of the shuffles goes away when we do the final blend as
8773 // FIXME: It might be worth trying to detect if the unpack-feeding
8774 // shuffles will both be pshufb, in which case we shouldn't bother with
8776 if (SDValue Unpack =
8777 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8784 // There are special ways we can lower some single-element blends.
8785 if (NumV2Elements == 1)
8786 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8787 Mask, Subtarget, DAG))
8790 if (SDValue BitBlend =
8791 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8794 // Check whether a compaction lowering can be done. This handles shuffles
8795 // which take every Nth element for some even N. See the helper function for
8798 // We special case these as they can be particularly efficiently handled with
8799 // the PACKUSB instruction on x86 and they show up in common patterns of
8800 // rearranging bytes to truncate wide elements.
8801 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8802 // NumEvenDrops is the power of two stride of the elements. Another way of
8803 // thinking about it is that we need to drop the even elements this many
8804 // times to get the original input.
8805 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8807 // First we need to zero all the dropped bytes.
8808 assert(NumEvenDrops <= 3 &&
8809 "No support for dropping even elements more than 3 times.");
8810 // We use the mask type to pick which bytes are preserved based on how many
8811 // elements are dropped.
8812 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8813 SDValue ByteClearMask =
8814 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8815 DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8816 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8818 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8820 // Now pack things back together.
8821 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8822 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8823 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8824 for (int i = 1; i < NumEvenDrops; ++i) {
8825 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8826 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8832 // Handle multi-input cases by blending single-input shuffles.
8833 if (NumV2Elements > 0)
8834 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8837 // The fallback path for single-input shuffles widens this into two v8i16
8838 // vectors with unpacks, shuffles those, and then pulls them back together
8842 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8843 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8844 for (int i = 0; i < 16; ++i)
8846 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8848 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8850 SDValue VLoHalf, VHiHalf;
8851 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8852 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8854 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8855 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8856 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8857 [](int M) { return M >= 0 && M % 2 == 1; })) {
8858 // Use a mask to drop the high bytes.
8859 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8860 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8861 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8863 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8864 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8866 // Squash the masks to point directly into VLoHalf.
8867 for (int &M : LoBlendMask)
8870 for (int &M : HiBlendMask)
8874 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8875 // VHiHalf so that we can blend them as i16s.
8876 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8877 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8878 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8879 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8882 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8883 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8885 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8888 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8890 /// This routine breaks down the specific type of 128-bit shuffle and
8891 /// dispatches to the lowering routines accordingly.
8892 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8893 MVT VT, const X86Subtarget *Subtarget,
8894 SelectionDAG &DAG) {
8895 switch (VT.SimpleTy) {
8897 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8899 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8901 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8903 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8905 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8907 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8910 llvm_unreachable("Unimplemented!");
8914 /// \brief Helper function to test whether a shuffle mask could be
8915 /// simplified by widening the elements being shuffled.
8917 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8918 /// leaves it in an unspecified state.
8920 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8921 /// shuffle masks. The latter have the special property of a '-2' representing
8922 /// a zero-ed lane of a vector.
8923 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8924 SmallVectorImpl<int> &WidenedMask) {
8925 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8926 // If both elements are undef, its trivial.
8927 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8928 WidenedMask.push_back(SM_SentinelUndef);
8932 // Check for an undef mask and a mask value properly aligned to fit with
8933 // a pair of values. If we find such a case, use the non-undef mask's value.
8934 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8935 WidenedMask.push_back(Mask[i + 1] / 2);
8938 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8939 WidenedMask.push_back(Mask[i] / 2);
8943 // When zeroing, we need to spread the zeroing across both lanes to widen.
8944 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8945 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8946 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8947 WidenedMask.push_back(SM_SentinelZero);
8953 // Finally check if the two mask values are adjacent and aligned with
8955 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8956 WidenedMask.push_back(Mask[i] / 2);
8960 // Otherwise we can't safely widen the elements used in this shuffle.
8963 assert(WidenedMask.size() == Mask.size() / 2 &&
8964 "Incorrect size of mask after widening the elements!");
8969 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8971 /// This routine just extracts two subvectors, shuffles them independently, and
8972 /// then concatenates them back together. This should work effectively with all
8973 /// AVX vector shuffle types.
8974 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8975 SDValue V2, ArrayRef<int> Mask,
8976 SelectionDAG &DAG) {
8977 assert(VT.getSizeInBits() >= 256 &&
8978 "Only for 256-bit or wider vector shuffles!");
8979 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8980 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8982 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8983 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8985 int NumElements = VT.getVectorNumElements();
8986 int SplitNumElements = NumElements / 2;
8987 MVT ScalarVT = VT.getScalarType();
8988 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8990 // Rather than splitting build-vectors, just build two narrower build
8991 // vectors. This helps shuffling with splats and zeros.
8992 auto SplitVector = [&](SDValue V) {
8993 while (V.getOpcode() == ISD::BITCAST)
8994 V = V->getOperand(0);
8996 MVT OrigVT = V.getSimpleValueType();
8997 int OrigNumElements = OrigVT.getVectorNumElements();
8998 int OrigSplitNumElements = OrigNumElements / 2;
8999 MVT OrigScalarVT = OrigVT.getScalarType();
9000 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9004 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9006 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9007 DAG.getIntPtrConstant(0, DL));
9008 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9009 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9012 SmallVector<SDValue, 16> LoOps, HiOps;
9013 for (int i = 0; i < OrigSplitNumElements; ++i) {
9014 LoOps.push_back(BV->getOperand(i));
9015 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9017 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9018 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9020 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
9021 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
9024 SDValue LoV1, HiV1, LoV2, HiV2;
9025 std::tie(LoV1, HiV1) = SplitVector(V1);
9026 std::tie(LoV2, HiV2) = SplitVector(V2);
9028 // Now create two 4-way blends of these half-width vectors.
9029 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9030 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9031 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9032 for (int i = 0; i < SplitNumElements; ++i) {
9033 int M = HalfMask[i];
9034 if (M >= NumElements) {
9035 if (M >= NumElements + SplitNumElements)
9039 V2BlendMask.push_back(M - NumElements);
9040 V1BlendMask.push_back(-1);
9041 BlendMask.push_back(SplitNumElements + i);
9042 } else if (M >= 0) {
9043 if (M >= SplitNumElements)
9047 V2BlendMask.push_back(-1);
9048 V1BlendMask.push_back(M);
9049 BlendMask.push_back(i);
9051 V2BlendMask.push_back(-1);
9052 V1BlendMask.push_back(-1);
9053 BlendMask.push_back(-1);
9057 // Because the lowering happens after all combining takes place, we need to
9058 // manually combine these blend masks as much as possible so that we create
9059 // a minimal number of high-level vector shuffle nodes.
9061 // First try just blending the halves of V1 or V2.
9062 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9063 return DAG.getUNDEF(SplitVT);
9064 if (!UseLoV2 && !UseHiV2)
9065 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9066 if (!UseLoV1 && !UseHiV1)
9067 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9069 SDValue V1Blend, V2Blend;
9070 if (UseLoV1 && UseHiV1) {
9072 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9074 // We only use half of V1 so map the usage down into the final blend mask.
9075 V1Blend = UseLoV1 ? LoV1 : HiV1;
9076 for (int i = 0; i < SplitNumElements; ++i)
9077 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9078 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9080 if (UseLoV2 && UseHiV2) {
9082 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9084 // We only use half of V2 so map the usage down into the final blend mask.
9085 V2Blend = UseLoV2 ? LoV2 : HiV2;
9086 for (int i = 0; i < SplitNumElements; ++i)
9087 if (BlendMask[i] >= SplitNumElements)
9088 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9090 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9092 SDValue Lo = HalfBlend(LoMask);
9093 SDValue Hi = HalfBlend(HiMask);
9094 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9097 /// \brief Either split a vector in halves or decompose the shuffles and the
9100 /// This is provided as a good fallback for many lowerings of non-single-input
9101 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9102 /// between splitting the shuffle into 128-bit components and stitching those
9103 /// back together vs. extracting the single-input shuffles and blending those
9105 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9106 SDValue V2, ArrayRef<int> Mask,
9107 SelectionDAG &DAG) {
9108 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9109 "lower single-input shuffles as it "
9110 "could then recurse on itself.");
9111 int Size = Mask.size();
9113 // If this can be modeled as a broadcast of two elements followed by a blend,
9114 // prefer that lowering. This is especially important because broadcasts can
9115 // often fold with memory operands.
9116 auto DoBothBroadcast = [&] {
9117 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9120 if (V2BroadcastIdx == -1)
9121 V2BroadcastIdx = M - Size;
9122 else if (M - Size != V2BroadcastIdx)
9124 } else if (M >= 0) {
9125 if (V1BroadcastIdx == -1)
9127 else if (M != V1BroadcastIdx)
9132 if (DoBothBroadcast())
9133 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9136 // If the inputs all stem from a single 128-bit lane of each input, then we
9137 // split them rather than blending because the split will decompose to
9138 // unusually few instructions.
9139 int LaneCount = VT.getSizeInBits() / 128;
9140 int LaneSize = Size / LaneCount;
9141 SmallBitVector LaneInputs[2];
9142 LaneInputs[0].resize(LaneCount, false);
9143 LaneInputs[1].resize(LaneCount, false);
9144 for (int i = 0; i < Size; ++i)
9146 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9147 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9148 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9150 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9151 // that the decomposed single-input shuffles don't end up here.
9152 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9155 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9156 /// a permutation and blend of those lanes.
9158 /// This essentially blends the out-of-lane inputs to each lane into the lane
9159 /// from a permuted copy of the vector. This lowering strategy results in four
9160 /// instructions in the worst case for a single-input cross lane shuffle which
9161 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9162 /// of. Special cases for each particular shuffle pattern should be handled
9163 /// prior to trying this lowering.
9164 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9165 SDValue V1, SDValue V2,
9167 SelectionDAG &DAG) {
9168 // FIXME: This should probably be generalized for 512-bit vectors as well.
9169 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9170 int LaneSize = Mask.size() / 2;
9172 // If there are only inputs from one 128-bit lane, splitting will in fact be
9173 // less expensive. The flags track whether the given lane contains an element
9174 // that crosses to another lane.
9175 bool LaneCrossing[2] = {false, false};
9176 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9177 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9178 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9179 if (!LaneCrossing[0] || !LaneCrossing[1])
9180 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9182 if (isSingleInputShuffleMask(Mask)) {
9183 SmallVector<int, 32> FlippedBlendMask;
9184 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9185 FlippedBlendMask.push_back(
9186 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9188 : Mask[i] % LaneSize +
9189 (i / LaneSize) * LaneSize + Size));
9191 // Flip the vector, and blend the results which should now be in-lane. The
9192 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9193 // 5 for the high source. The value 3 selects the high half of source 2 and
9194 // the value 2 selects the low half of source 2. We only use source 2 to
9195 // allow folding it into a memory operand.
9196 unsigned PERMMask = 3 | 2 << 4;
9197 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9198 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9199 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9202 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9203 // will be handled by the above logic and a blend of the results, much like
9204 // other patterns in AVX.
9205 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9208 /// \brief Handle lowering 2-lane 128-bit shuffles.
9209 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9210 SDValue V2, ArrayRef<int> Mask,
9211 const X86Subtarget *Subtarget,
9212 SelectionDAG &DAG) {
9213 // TODO: If minimizing size and one of the inputs is a zero vector and the
9214 // the zero vector has only one use, we could use a VPERM2X128 to save the
9215 // instruction bytes needed to explicitly generate the zero vector.
9217 // Blends are faster and handle all the non-lane-crossing cases.
9218 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9222 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9223 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9225 // If either input operand is a zero vector, use VPERM2X128 because its mask
9226 // allows us to replace the zero input with an implicit zero.
9227 if (!IsV1Zero && !IsV2Zero) {
9228 // Check for patterns which can be matched with a single insert of a 128-bit
9230 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9231 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9232 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9233 VT.getVectorNumElements() / 2);
9234 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9235 DAG.getIntPtrConstant(0, DL));
9236 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9237 OnlyUsesV1 ? V1 : V2,
9238 DAG.getIntPtrConstant(0, DL));
9239 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9243 // Otherwise form a 128-bit permutation. After accounting for undefs,
9244 // convert the 64-bit shuffle mask selection values into 128-bit
9245 // selection bits by dividing the indexes by 2 and shifting into positions
9246 // defined by a vperm2*128 instruction's immediate control byte.
9248 // The immediate permute control byte looks like this:
9249 // [1:0] - select 128 bits from sources for low half of destination
9251 // [3] - zero low half of destination
9252 // [5:4] - select 128 bits from sources for high half of destination
9254 // [7] - zero high half of destination
9256 int MaskLO = Mask[0];
9257 if (MaskLO == SM_SentinelUndef)
9258 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9260 int MaskHI = Mask[2];
9261 if (MaskHI == SM_SentinelUndef)
9262 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9264 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9266 // If either input is a zero vector, replace it with an undef input.
9267 // Shuffle mask values < 4 are selecting elements of V1.
9268 // Shuffle mask values >= 4 are selecting elements of V2.
9269 // Adjust each half of the permute mask by clearing the half that was
9270 // selecting the zero vector and setting the zero mask bit.
9272 V1 = DAG.getUNDEF(VT);
9274 PermMask = (PermMask & 0xf0) | 0x08;
9276 PermMask = (PermMask & 0x0f) | 0x80;
9279 V2 = DAG.getUNDEF(VT);
9281 PermMask = (PermMask & 0xf0) | 0x08;
9283 PermMask = (PermMask & 0x0f) | 0x80;
9286 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9287 DAG.getConstant(PermMask, DL, MVT::i8));
9290 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9291 /// shuffling each lane.
9293 /// This will only succeed when the result of fixing the 128-bit lanes results
9294 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9295 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9296 /// the lane crosses early and then use simpler shuffles within each lane.
9298 /// FIXME: It might be worthwhile at some point to support this without
9299 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9300 /// in x86 only floating point has interesting non-repeating shuffles, and even
9301 /// those are still *marginally* more expensive.
9302 static SDValue lowerVectorShuffleByMerging128BitLanes(
9303 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9304 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9305 assert(!isSingleInputShuffleMask(Mask) &&
9306 "This is only useful with multiple inputs.");
9308 int Size = Mask.size();
9309 int LaneSize = 128 / VT.getScalarSizeInBits();
9310 int NumLanes = Size / LaneSize;
9311 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9313 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9314 // check whether the in-128-bit lane shuffles share a repeating pattern.
9315 SmallVector<int, 4> Lanes;
9316 Lanes.resize(NumLanes, -1);
9317 SmallVector<int, 4> InLaneMask;
9318 InLaneMask.resize(LaneSize, -1);
9319 for (int i = 0; i < Size; ++i) {
9323 int j = i / LaneSize;
9326 // First entry we've seen for this lane.
9327 Lanes[j] = Mask[i] / LaneSize;
9328 } else if (Lanes[j] != Mask[i] / LaneSize) {
9329 // This doesn't match the lane selected previously!
9333 // Check that within each lane we have a consistent shuffle mask.
9334 int k = i % LaneSize;
9335 if (InLaneMask[k] < 0) {
9336 InLaneMask[k] = Mask[i] % LaneSize;
9337 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9338 // This doesn't fit a repeating in-lane mask.
9343 // First shuffle the lanes into place.
9344 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9345 VT.getSizeInBits() / 64);
9346 SmallVector<int, 8> LaneMask;
9347 LaneMask.resize(NumLanes * 2, -1);
9348 for (int i = 0; i < NumLanes; ++i)
9349 if (Lanes[i] >= 0) {
9350 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9351 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9354 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9355 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9356 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9358 // Cast it back to the type we actually want.
9359 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9361 // Now do a simple shuffle that isn't lane crossing.
9362 SmallVector<int, 8> NewMask;
9363 NewMask.resize(Size, -1);
9364 for (int i = 0; i < Size; ++i)
9366 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9367 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9368 "Must not introduce lane crosses at this point!");
9370 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9373 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9376 /// This returns true if the elements from a particular input are already in the
9377 /// slot required by the given mask and require no permutation.
9378 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9379 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9380 int Size = Mask.size();
9381 for (int i = 0; i < Size; ++i)
9382 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9388 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9390 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9391 /// isn't available.
9392 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9393 const X86Subtarget *Subtarget,
9394 SelectionDAG &DAG) {
9396 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9397 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9399 ArrayRef<int> Mask = SVOp->getMask();
9400 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9402 SmallVector<int, 4> WidenedMask;
9403 if (canWidenShuffleElements(Mask, WidenedMask))
9404 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9407 if (isSingleInputShuffleMask(Mask)) {
9408 // Check for being able to broadcast a single element.
9409 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9410 Mask, Subtarget, DAG))
9413 // Use low duplicate instructions for masks that match their pattern.
9414 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9415 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9417 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9418 // Non-half-crossing single input shuffles can be lowerid with an
9419 // interleaved permutation.
9420 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9421 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9422 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9423 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9426 // With AVX2 we have direct support for this permutation.
9427 if (Subtarget->hasAVX2())
9428 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9429 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9431 // Otherwise, fall back.
9432 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9436 // X86 has dedicated unpack instructions that can handle specific blend
9437 // operations: UNPCKH and UNPCKL.
9438 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9439 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9440 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9441 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9442 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9443 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9444 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9445 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9447 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9451 // Check if the blend happens to exactly fit that of SHUFPD.
9452 if ((Mask[0] == -1 || Mask[0] < 2) &&
9453 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9454 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9455 (Mask[3] == -1 || Mask[3] >= 6)) {
9456 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9457 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9458 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9459 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9461 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9462 (Mask[1] == -1 || Mask[1] < 2) &&
9463 (Mask[2] == -1 || Mask[2] >= 6) &&
9464 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9465 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9466 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9467 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9468 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9471 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9472 // shuffle. However, if we have AVX2 and either inputs are already in place,
9473 // we will be able to shuffle even across lanes the other input in a single
9474 // instruction so skip this pattern.
9475 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9476 isShuffleMaskInputInPlace(1, Mask))))
9477 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9478 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9481 // If we have AVX2 then we always want to lower with a blend because an v4 we
9482 // can fully permute the elements.
9483 if (Subtarget->hasAVX2())
9484 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9487 // Otherwise fall back on generic lowering.
9488 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9491 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9493 /// This routine is only called when we have AVX2 and thus a reasonable
9494 /// instruction set for v4i64 shuffling..
9495 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9496 const X86Subtarget *Subtarget,
9497 SelectionDAG &DAG) {
9499 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9500 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9502 ArrayRef<int> Mask = SVOp->getMask();
9503 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9504 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9506 SmallVector<int, 4> WidenedMask;
9507 if (canWidenShuffleElements(Mask, WidenedMask))
9508 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9511 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9515 // Check for being able to broadcast a single element.
9516 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9517 Mask, Subtarget, DAG))
9520 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9521 // use lower latency instructions that will operate on both 128-bit lanes.
9522 SmallVector<int, 2> RepeatedMask;
9523 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9524 if (isSingleInputShuffleMask(Mask)) {
9525 int PSHUFDMask[] = {-1, -1, -1, -1};
9526 for (int i = 0; i < 2; ++i)
9527 if (RepeatedMask[i] >= 0) {
9528 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9529 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9532 ISD::BITCAST, DL, MVT::v4i64,
9533 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9534 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9535 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9539 // AVX2 provides a direct instruction for permuting a single input across
9541 if (isSingleInputShuffleMask(Mask))
9542 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9543 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9545 // Try to use shift instructions.
9547 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9550 // Use dedicated unpack instructions for masks that match their pattern.
9551 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9552 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9553 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9554 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9555 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9556 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9557 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9558 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9560 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9561 // shuffle. However, if we have AVX2 and either inputs are already in place,
9562 // we will be able to shuffle even across lanes the other input in a single
9563 // instruction so skip this pattern.
9564 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9565 isShuffleMaskInputInPlace(1, Mask))))
9566 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9567 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9570 // Otherwise fall back on generic blend lowering.
9571 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9575 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9577 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9578 /// isn't available.
9579 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9580 const X86Subtarget *Subtarget,
9581 SelectionDAG &DAG) {
9583 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9584 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9585 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9586 ArrayRef<int> Mask = SVOp->getMask();
9587 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9589 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9593 // Check for being able to broadcast a single element.
9594 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9595 Mask, Subtarget, DAG))
9598 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9599 // options to efficiently lower the shuffle.
9600 SmallVector<int, 4> RepeatedMask;
9601 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9602 assert(RepeatedMask.size() == 4 &&
9603 "Repeated masks must be half the mask width!");
9605 // Use even/odd duplicate instructions for masks that match their pattern.
9606 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9607 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9608 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9609 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9611 if (isSingleInputShuffleMask(Mask))
9612 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9613 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9615 // Use dedicated unpack instructions for masks that match their pattern.
9616 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9617 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9618 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9619 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9620 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9621 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9622 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9623 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9625 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9626 // have already handled any direct blends. We also need to squash the
9627 // repeated mask into a simulated v4f32 mask.
9628 for (int i = 0; i < 4; ++i)
9629 if (RepeatedMask[i] >= 8)
9630 RepeatedMask[i] -= 4;
9631 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9634 // If we have a single input shuffle with different shuffle patterns in the
9635 // two 128-bit lanes use the variable mask to VPERMILPS.
9636 if (isSingleInputShuffleMask(Mask)) {
9637 SDValue VPermMask[8];
9638 for (int i = 0; i < 8; ++i)
9639 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9640 : DAG.getConstant(Mask[i], DL, MVT::i32);
9641 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9643 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9644 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9646 if (Subtarget->hasAVX2())
9647 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9648 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9649 DAG.getNode(ISD::BUILD_VECTOR, DL,
9650 MVT::v8i32, VPermMask)),
9653 // Otherwise, fall back.
9654 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9658 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9660 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9661 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9664 // If we have AVX2 then we always want to lower with a blend because at v8 we
9665 // can fully permute the elements.
9666 if (Subtarget->hasAVX2())
9667 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9670 // Otherwise fall back on generic lowering.
9671 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9674 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9676 /// This routine is only called when we have AVX2 and thus a reasonable
9677 /// instruction set for v8i32 shuffling..
9678 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9679 const X86Subtarget *Subtarget,
9680 SelectionDAG &DAG) {
9682 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9683 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9684 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9685 ArrayRef<int> Mask = SVOp->getMask();
9686 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9687 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9689 // Whenever we can lower this as a zext, that instruction is strictly faster
9690 // than any alternative. It also allows us to fold memory operands into the
9691 // shuffle in many cases.
9692 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9693 Mask, Subtarget, DAG))
9696 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9700 // Check for being able to broadcast a single element.
9701 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9702 Mask, Subtarget, DAG))
9705 // If the shuffle mask is repeated in each 128-bit lane we can use more
9706 // efficient instructions that mirror the shuffles across the two 128-bit
9708 SmallVector<int, 4> RepeatedMask;
9709 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9710 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9711 if (isSingleInputShuffleMask(Mask))
9712 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9713 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9715 // Use dedicated unpack instructions for masks that match their pattern.
9716 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9717 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9718 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9719 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9720 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9721 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9722 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9723 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9726 // Try to use shift instructions.
9728 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9731 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9732 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9735 // If the shuffle patterns aren't repeated but it is a single input, directly
9736 // generate a cross-lane VPERMD instruction.
9737 if (isSingleInputShuffleMask(Mask)) {
9738 SDValue VPermMask[8];
9739 for (int i = 0; i < 8; ++i)
9740 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9741 : DAG.getConstant(Mask[i], DL, MVT::i32);
9743 X86ISD::VPERMV, DL, MVT::v8i32,
9744 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9747 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9749 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9750 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9753 // Otherwise fall back on generic blend lowering.
9754 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9758 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9760 /// This routine is only called when we have AVX2 and thus a reasonable
9761 /// instruction set for v16i16 shuffling..
9762 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9763 const X86Subtarget *Subtarget,
9764 SelectionDAG &DAG) {
9766 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9767 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9768 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9769 ArrayRef<int> Mask = SVOp->getMask();
9770 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9771 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9773 // Whenever we can lower this as a zext, that instruction is strictly faster
9774 // than any alternative. It also allows us to fold memory operands into the
9775 // shuffle in many cases.
9776 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9777 Mask, Subtarget, DAG))
9780 // Check for being able to broadcast a single element.
9781 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9782 Mask, Subtarget, DAG))
9785 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9789 // Use dedicated unpack instructions for masks that match their pattern.
9790 if (isShuffleEquivalent(V1, V2, Mask,
9791 {// First 128-bit lane:
9792 0, 16, 1, 17, 2, 18, 3, 19,
9793 // Second 128-bit lane:
9794 8, 24, 9, 25, 10, 26, 11, 27}))
9795 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9796 if (isShuffleEquivalent(V1, V2, Mask,
9797 {// First 128-bit lane:
9798 4, 20, 5, 21, 6, 22, 7, 23,
9799 // Second 128-bit lane:
9800 12, 28, 13, 29, 14, 30, 15, 31}))
9801 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9803 // Try to use shift instructions.
9805 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9808 // Try to use byte rotation instructions.
9809 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9810 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9813 if (isSingleInputShuffleMask(Mask)) {
9814 // There are no generalized cross-lane shuffle operations available on i16
9816 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9817 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9820 SmallVector<int, 8> RepeatedMask;
9821 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9822 // As this is a single-input shuffle, the repeated mask should be
9823 // a strictly valid v8i16 mask that we can pass through to the v8i16
9824 // lowering to handle even the v16 case.
9825 return lowerV8I16GeneralSingleInputVectorShuffle(
9826 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9829 SDValue PSHUFBMask[32];
9830 for (int i = 0; i < 16; ++i) {
9831 if (Mask[i] == -1) {
9832 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9836 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9837 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9838 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9839 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9842 ISD::BITCAST, DL, MVT::v16i16,
9844 X86ISD::PSHUFB, DL, MVT::v32i8,
9845 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9846 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9849 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9851 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9852 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9855 // Otherwise fall back on generic lowering.
9856 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9859 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9861 /// This routine is only called when we have AVX2 and thus a reasonable
9862 /// instruction set for v32i8 shuffling..
9863 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9864 const X86Subtarget *Subtarget,
9865 SelectionDAG &DAG) {
9867 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9868 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9869 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9870 ArrayRef<int> Mask = SVOp->getMask();
9871 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9872 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9874 // Whenever we can lower this as a zext, that instruction is strictly faster
9875 // than any alternative. It also allows us to fold memory operands into the
9876 // shuffle in many cases.
9877 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9878 Mask, Subtarget, DAG))
9881 // Check for being able to broadcast a single element.
9882 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9883 Mask, Subtarget, DAG))
9886 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9890 // Use dedicated unpack instructions for masks that match their pattern.
9891 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9893 if (isShuffleEquivalent(
9895 {// First 128-bit lane:
9896 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9897 // Second 128-bit lane:
9898 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9899 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9900 if (isShuffleEquivalent(
9902 {// First 128-bit lane:
9903 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9904 // Second 128-bit lane:
9905 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9906 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9908 // Try to use shift instructions.
9910 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9913 // Try to use byte rotation instructions.
9914 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9915 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9918 if (isSingleInputShuffleMask(Mask)) {
9919 // There are no generalized cross-lane shuffle operations available on i8
9921 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9922 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9925 SDValue PSHUFBMask[32];
9926 for (int i = 0; i < 32; ++i)
9929 ? DAG.getUNDEF(MVT::i8)
9930 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
9934 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9935 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9938 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9940 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9941 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9944 // Otherwise fall back on generic lowering.
9945 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9948 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9950 /// This routine either breaks down the specific type of a 256-bit x86 vector
9951 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9952 /// together based on the available instructions.
9953 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9954 MVT VT, const X86Subtarget *Subtarget,
9955 SelectionDAG &DAG) {
9957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9958 ArrayRef<int> Mask = SVOp->getMask();
9960 // If we have a single input to the zero element, insert that into V1 if we
9961 // can do so cheaply.
9962 int NumElts = VT.getVectorNumElements();
9963 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
9964 return M >= NumElts;
9967 if (NumV2Elements == 1 && Mask[0] >= NumElts)
9968 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9969 DL, VT, V1, V2, Mask, Subtarget, DAG))
9972 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9973 // check for those subtargets here and avoid much of the subtarget querying in
9974 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9975 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9976 // floating point types there eventually, just immediately cast everything to
9977 // a float and operate entirely in that domain.
9978 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9979 int ElementBits = VT.getScalarSizeInBits();
9980 if (ElementBits < 32)
9981 // No floating point type available, decompose into 128-bit vectors.
9982 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9984 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9985 VT.getVectorNumElements());
9986 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9987 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9988 return DAG.getNode(ISD::BITCAST, DL, VT,
9989 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9992 switch (VT.SimpleTy) {
9994 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9996 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9998 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10000 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10002 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10004 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10007 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10011 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10012 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10013 const X86Subtarget *Subtarget,
10014 SelectionDAG &DAG) {
10016 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10017 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10019 ArrayRef<int> Mask = SVOp->getMask();
10020 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10022 // X86 has dedicated unpack instructions that can handle specific blend
10023 // operations: UNPCKH and UNPCKL.
10024 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10025 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10026 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10027 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10029 // FIXME: Implement direct support for this type!
10030 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10033 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10034 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10035 const X86Subtarget *Subtarget,
10036 SelectionDAG &DAG) {
10038 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10039 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10040 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10041 ArrayRef<int> Mask = SVOp->getMask();
10042 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10044 // Use dedicated unpack instructions for masks that match their pattern.
10045 if (isShuffleEquivalent(V1, V2, Mask,
10046 {// First 128-bit lane.
10047 0, 16, 1, 17, 4, 20, 5, 21,
10048 // Second 128-bit lane.
10049 8, 24, 9, 25, 12, 28, 13, 29}))
10050 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10051 if (isShuffleEquivalent(V1, V2, Mask,
10052 {// First 128-bit lane.
10053 2, 18, 3, 19, 6, 22, 7, 23,
10054 // Second 128-bit lane.
10055 10, 26, 11, 27, 14, 30, 15, 31}))
10056 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10058 // FIXME: Implement direct support for this type!
10059 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10062 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10063 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10064 const X86Subtarget *Subtarget,
10065 SelectionDAG &DAG) {
10067 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10068 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10069 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10070 ArrayRef<int> Mask = SVOp->getMask();
10071 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10073 // X86 has dedicated unpack instructions that can handle specific blend
10074 // operations: UNPCKH and UNPCKL.
10075 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10076 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10077 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10078 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10080 // FIXME: Implement direct support for this type!
10081 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10084 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10085 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10086 const X86Subtarget *Subtarget,
10087 SelectionDAG &DAG) {
10089 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10090 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10092 ArrayRef<int> Mask = SVOp->getMask();
10093 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10095 // Use dedicated unpack instructions for masks that match their pattern.
10096 if (isShuffleEquivalent(V1, V2, Mask,
10097 {// First 128-bit lane.
10098 0, 16, 1, 17, 4, 20, 5, 21,
10099 // Second 128-bit lane.
10100 8, 24, 9, 25, 12, 28, 13, 29}))
10101 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10102 if (isShuffleEquivalent(V1, V2, Mask,
10103 {// First 128-bit lane.
10104 2, 18, 3, 19, 6, 22, 7, 23,
10105 // Second 128-bit lane.
10106 10, 26, 11, 27, 14, 30, 15, 31}))
10107 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10109 // FIXME: Implement direct support for this type!
10110 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10113 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10114 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10115 const X86Subtarget *Subtarget,
10116 SelectionDAG &DAG) {
10118 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10119 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10120 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10121 ArrayRef<int> Mask = SVOp->getMask();
10122 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10123 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10125 // FIXME: Implement direct support for this type!
10126 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10129 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10130 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10131 const X86Subtarget *Subtarget,
10132 SelectionDAG &DAG) {
10134 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10135 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10136 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10137 ArrayRef<int> Mask = SVOp->getMask();
10138 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10139 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10141 // FIXME: Implement direct support for this type!
10142 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10145 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10147 /// This routine either breaks down the specific type of a 512-bit x86 vector
10148 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10149 /// together based on the available instructions.
10150 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10151 MVT VT, const X86Subtarget *Subtarget,
10152 SelectionDAG &DAG) {
10154 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10155 ArrayRef<int> Mask = SVOp->getMask();
10156 assert(Subtarget->hasAVX512() &&
10157 "Cannot lower 512-bit vectors w/ basic ISA!");
10159 // Check for being able to broadcast a single element.
10160 if (SDValue Broadcast =
10161 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10164 // Dispatch to each element type for lowering. If we don't have supprot for
10165 // specific element type shuffles at 512 bits, immediately split them and
10166 // lower them. Each lowering routine of a given type is allowed to assume that
10167 // the requisite ISA extensions for that element type are available.
10168 switch (VT.SimpleTy) {
10170 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10172 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10174 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10176 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10178 if (Subtarget->hasBWI())
10179 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10182 if (Subtarget->hasBWI())
10183 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10187 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10190 // Otherwise fall back on splitting.
10191 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10194 /// \brief Top-level lowering for x86 vector shuffles.
10196 /// This handles decomposition, canonicalization, and lowering of all x86
10197 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10198 /// above in helper routines. The canonicalization attempts to widen shuffles
10199 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10200 /// s.t. only one of the two inputs needs to be tested, etc.
10201 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10202 SelectionDAG &DAG) {
10203 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10204 ArrayRef<int> Mask = SVOp->getMask();
10205 SDValue V1 = Op.getOperand(0);
10206 SDValue V2 = Op.getOperand(1);
10207 MVT VT = Op.getSimpleValueType();
10208 int NumElements = VT.getVectorNumElements();
10211 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10213 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10214 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10215 if (V1IsUndef && V2IsUndef)
10216 return DAG.getUNDEF(VT);
10218 // When we create a shuffle node we put the UNDEF node to second operand,
10219 // but in some cases the first operand may be transformed to UNDEF.
10220 // In this case we should just commute the node.
10222 return DAG.getCommutedVectorShuffle(*SVOp);
10224 // Check for non-undef masks pointing at an undef vector and make the masks
10225 // undef as well. This makes it easier to match the shuffle based solely on
10229 if (M >= NumElements) {
10230 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10231 for (int &M : NewMask)
10232 if (M >= NumElements)
10234 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10237 // We actually see shuffles that are entirely re-arrangements of a set of
10238 // zero inputs. This mostly happens while decomposing complex shuffles into
10239 // simple ones. Directly lower these as a buildvector of zeros.
10240 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10241 if (Zeroable.all())
10242 return getZeroVector(VT, Subtarget, DAG, dl);
10244 // Try to collapse shuffles into using a vector type with fewer elements but
10245 // wider element types. We cap this to not form integers or floating point
10246 // elements wider than 64 bits, but it might be interesting to form i128
10247 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10248 SmallVector<int, 16> WidenedMask;
10249 if (VT.getScalarSizeInBits() < 64 &&
10250 canWidenShuffleElements(Mask, WidenedMask)) {
10251 MVT NewEltVT = VT.isFloatingPoint()
10252 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10253 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10254 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10255 // Make sure that the new vector type is legal. For example, v2f64 isn't
10257 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10258 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10259 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10260 return DAG.getNode(ISD::BITCAST, dl, VT,
10261 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10265 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10266 for (int M : SVOp->getMask())
10268 ++NumUndefElements;
10269 else if (M < NumElements)
10274 // Commute the shuffle as needed such that more elements come from V1 than
10275 // V2. This allows us to match the shuffle pattern strictly on how many
10276 // elements come from V1 without handling the symmetric cases.
10277 if (NumV2Elements > NumV1Elements)
10278 return DAG.getCommutedVectorShuffle(*SVOp);
10280 // When the number of V1 and V2 elements are the same, try to minimize the
10281 // number of uses of V2 in the low half of the vector. When that is tied,
10282 // ensure that the sum of indices for V1 is equal to or lower than the sum
10283 // indices for V2. When those are equal, try to ensure that the number of odd
10284 // indices for V1 is lower than the number of odd indices for V2.
10285 if (NumV1Elements == NumV2Elements) {
10286 int LowV1Elements = 0, LowV2Elements = 0;
10287 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10288 if (M >= NumElements)
10292 if (LowV2Elements > LowV1Elements) {
10293 return DAG.getCommutedVectorShuffle(*SVOp);
10294 } else if (LowV2Elements == LowV1Elements) {
10295 int SumV1Indices = 0, SumV2Indices = 0;
10296 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10297 if (SVOp->getMask()[i] >= NumElements)
10299 else if (SVOp->getMask()[i] >= 0)
10301 if (SumV2Indices < SumV1Indices) {
10302 return DAG.getCommutedVectorShuffle(*SVOp);
10303 } else if (SumV2Indices == SumV1Indices) {
10304 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10305 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10306 if (SVOp->getMask()[i] >= NumElements)
10307 NumV2OddIndices += i % 2;
10308 else if (SVOp->getMask()[i] >= 0)
10309 NumV1OddIndices += i % 2;
10310 if (NumV2OddIndices < NumV1OddIndices)
10311 return DAG.getCommutedVectorShuffle(*SVOp);
10316 // For each vector width, delegate to a specialized lowering routine.
10317 if (VT.getSizeInBits() == 128)
10318 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10320 if (VT.getSizeInBits() == 256)
10321 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10323 // Force AVX-512 vectors to be scalarized for now.
10324 // FIXME: Implement AVX-512 support!
10325 if (VT.getSizeInBits() == 512)
10326 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10328 llvm_unreachable("Unimplemented!");
10331 // This function assumes its argument is a BUILD_VECTOR of constants or
10332 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10334 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10335 unsigned &MaskValue) {
10337 unsigned NumElems = BuildVector->getNumOperands();
10338 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10339 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10340 unsigned NumElemsInLane = NumElems / NumLanes;
10342 // Blend for v16i16 should be symetric for the both lanes.
10343 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10344 SDValue EltCond = BuildVector->getOperand(i);
10345 SDValue SndLaneEltCond =
10346 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10348 int Lane1Cond = -1, Lane2Cond = -1;
10349 if (isa<ConstantSDNode>(EltCond))
10350 Lane1Cond = !isZero(EltCond);
10351 if (isa<ConstantSDNode>(SndLaneEltCond))
10352 Lane2Cond = !isZero(SndLaneEltCond);
10354 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10355 // Lane1Cond != 0, means we want the first argument.
10356 // Lane1Cond == 0, means we want the second argument.
10357 // The encoding of this argument is 0 for the first argument, 1
10358 // for the second. Therefore, invert the condition.
10359 MaskValue |= !Lane1Cond << i;
10360 else if (Lane1Cond < 0)
10361 MaskValue |= !Lane2Cond << i;
10368 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10369 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10370 const X86Subtarget *Subtarget,
10371 SelectionDAG &DAG) {
10372 SDValue Cond = Op.getOperand(0);
10373 SDValue LHS = Op.getOperand(1);
10374 SDValue RHS = Op.getOperand(2);
10376 MVT VT = Op.getSimpleValueType();
10378 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10380 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10382 // Only non-legal VSELECTs reach this lowering, convert those into generic
10383 // shuffles and re-use the shuffle lowering path for blends.
10384 SmallVector<int, 32> Mask;
10385 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10386 SDValue CondElt = CondBV->getOperand(i);
10388 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10390 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10393 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10394 // A vselect where all conditions and data are constants can be optimized into
10395 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10396 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10397 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10398 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10401 // Try to lower this to a blend-style vector shuffle. This can handle all
10402 // constant condition cases.
10403 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10406 // Variable blends are only legal from SSE4.1 onward.
10407 if (!Subtarget->hasSSE41())
10410 // Only some types will be legal on some subtargets. If we can emit a legal
10411 // VSELECT-matching blend, return Op, and but if we need to expand, return
10413 switch (Op.getSimpleValueType().SimpleTy) {
10415 // Most of the vector types have blends past SSE4.1.
10419 // The byte blends for AVX vectors were introduced only in AVX2.
10420 if (Subtarget->hasAVX2())
10427 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10428 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10431 // FIXME: We should custom lower this by fixing the condition and using i8
10437 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10438 MVT VT = Op.getSimpleValueType();
10441 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10444 if (VT.getSizeInBits() == 8) {
10445 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10446 Op.getOperand(0), Op.getOperand(1));
10447 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10448 DAG.getValueType(VT));
10449 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10452 if (VT.getSizeInBits() == 16) {
10453 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10454 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10456 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10457 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10458 DAG.getNode(ISD::BITCAST, dl,
10461 Op.getOperand(1)));
10462 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10463 Op.getOperand(0), Op.getOperand(1));
10464 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10465 DAG.getValueType(VT));
10466 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10469 if (VT == MVT::f32) {
10470 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10471 // the result back to FR32 register. It's only worth matching if the
10472 // result has a single use which is a store or a bitcast to i32. And in
10473 // the case of a store, it's not worth it if the index is a constant 0,
10474 // because a MOVSSmr can be used instead, which is smaller and faster.
10475 if (!Op.hasOneUse())
10477 SDNode *User = *Op.getNode()->use_begin();
10478 if ((User->getOpcode() != ISD::STORE ||
10479 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10480 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10481 (User->getOpcode() != ISD::BITCAST ||
10482 User->getValueType(0) != MVT::i32))
10484 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10485 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10488 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10491 if (VT == MVT::i32 || VT == MVT::i64) {
10492 // ExtractPS/pextrq works with constant index.
10493 if (isa<ConstantSDNode>(Op.getOperand(1)))
10499 /// Extract one bit from mask vector, like v16i1 or v8i1.
10500 /// AVX-512 feature.
10502 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10503 SDValue Vec = Op.getOperand(0);
10505 MVT VecVT = Vec.getSimpleValueType();
10506 SDValue Idx = Op.getOperand(1);
10507 MVT EltVT = Op.getSimpleValueType();
10509 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10510 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10511 "Unexpected vector type in ExtractBitFromMaskVector");
10513 // variable index can't be handled in mask registers,
10514 // extend vector to VR512
10515 if (!isa<ConstantSDNode>(Idx)) {
10516 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10517 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10518 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10519 ExtVT.getVectorElementType(), Ext, Idx);
10520 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10523 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10524 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10525 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10526 rc = getRegClassFor(MVT::v16i1);
10527 unsigned MaxSift = rc->getSize()*8 - 1;
10528 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10529 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10530 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10531 DAG.getConstant(MaxSift, dl, MVT::i8));
10532 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10533 DAG.getIntPtrConstant(0, dl));
10537 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10538 SelectionDAG &DAG) const {
10540 SDValue Vec = Op.getOperand(0);
10541 MVT VecVT = Vec.getSimpleValueType();
10542 SDValue Idx = Op.getOperand(1);
10544 if (Op.getSimpleValueType() == MVT::i1)
10545 return ExtractBitFromMaskVector(Op, DAG);
10547 if (!isa<ConstantSDNode>(Idx)) {
10548 if (VecVT.is512BitVector() ||
10549 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10550 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10553 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10554 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10555 MaskEltVT.getSizeInBits());
10557 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10558 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10559 getZeroVector(MaskVT, Subtarget, DAG, dl),
10560 Idx, DAG.getConstant(0, dl, getPointerTy()));
10561 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10562 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10563 Perm, DAG.getConstant(0, dl, getPointerTy()));
10568 // If this is a 256-bit vector result, first extract the 128-bit vector and
10569 // then extract the element from the 128-bit vector.
10570 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10572 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10573 // Get the 128-bit vector.
10574 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10575 MVT EltVT = VecVT.getVectorElementType();
10577 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10579 //if (IdxVal >= NumElems/2)
10580 // IdxVal -= NumElems/2;
10581 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10582 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10583 DAG.getConstant(IdxVal, dl, MVT::i32));
10586 assert(VecVT.is128BitVector() && "Unexpected vector length");
10588 if (Subtarget->hasSSE41()) {
10589 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10594 MVT VT = Op.getSimpleValueType();
10595 // TODO: handle v16i8.
10596 if (VT.getSizeInBits() == 16) {
10597 SDValue Vec = Op.getOperand(0);
10598 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10600 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10601 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10602 DAG.getNode(ISD::BITCAST, dl,
10604 Op.getOperand(1)));
10605 // Transform it so it match pextrw which produces a 32-bit result.
10606 MVT EltVT = MVT::i32;
10607 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10608 Op.getOperand(0), Op.getOperand(1));
10609 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10610 DAG.getValueType(VT));
10611 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10614 if (VT.getSizeInBits() == 32) {
10615 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10619 // SHUFPS the element to the lowest double word, then movss.
10620 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10621 MVT VVT = Op.getOperand(0).getSimpleValueType();
10622 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10623 DAG.getUNDEF(VVT), Mask);
10624 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10625 DAG.getIntPtrConstant(0, dl));
10628 if (VT.getSizeInBits() == 64) {
10629 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10630 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10631 // to match extract_elt for f64.
10632 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10636 // UNPCKHPD the element to the lowest double word, then movsd.
10637 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10638 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10639 int Mask[2] = { 1, -1 };
10640 MVT VVT = Op.getOperand(0).getSimpleValueType();
10641 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10642 DAG.getUNDEF(VVT), Mask);
10643 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10644 DAG.getIntPtrConstant(0, dl));
10650 /// Insert one bit to mask vector, like v16i1 or v8i1.
10651 /// AVX-512 feature.
10653 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10655 SDValue Vec = Op.getOperand(0);
10656 SDValue Elt = Op.getOperand(1);
10657 SDValue Idx = Op.getOperand(2);
10658 MVT VecVT = Vec.getSimpleValueType();
10660 if (!isa<ConstantSDNode>(Idx)) {
10661 // Non constant index. Extend source and destination,
10662 // insert element and then truncate the result.
10663 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10664 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10665 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10666 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10667 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10668 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10671 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10672 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10673 if (Vec.getOpcode() == ISD::UNDEF)
10674 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10675 DAG.getConstant(IdxVal, dl, MVT::i8));
10676 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10677 unsigned MaxSift = rc->getSize()*8 - 1;
10678 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10679 DAG.getConstant(MaxSift, dl, MVT::i8));
10680 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10681 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10682 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10685 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10686 SelectionDAG &DAG) const {
10687 MVT VT = Op.getSimpleValueType();
10688 MVT EltVT = VT.getVectorElementType();
10690 if (EltVT == MVT::i1)
10691 return InsertBitToMaskVector(Op, DAG);
10694 SDValue N0 = Op.getOperand(0);
10695 SDValue N1 = Op.getOperand(1);
10696 SDValue N2 = Op.getOperand(2);
10697 if (!isa<ConstantSDNode>(N2))
10699 auto *N2C = cast<ConstantSDNode>(N2);
10700 unsigned IdxVal = N2C->getZExtValue();
10702 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10703 // into that, and then insert the subvector back into the result.
10704 if (VT.is256BitVector() || VT.is512BitVector()) {
10705 // With a 256-bit vector, we can insert into the zero element efficiently
10706 // using a blend if we have AVX or AVX2 and the right data type.
10707 if (VT.is256BitVector() && IdxVal == 0) {
10708 // TODO: It is worthwhile to cast integer to floating point and back
10709 // and incur a domain crossing penalty if that's what we'll end up
10710 // doing anyway after extracting to a 128-bit vector.
10711 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10712 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10713 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10714 N2 = DAG.getIntPtrConstant(1, dl);
10715 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10719 // Get the desired 128-bit vector chunk.
10720 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10722 // Insert the element into the desired chunk.
10723 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10724 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10726 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10727 DAG.getConstant(IdxIn128, dl, MVT::i32));
10729 // Insert the changed part back into the bigger vector
10730 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10732 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10734 if (Subtarget->hasSSE41()) {
10735 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10737 if (VT == MVT::v8i16) {
10738 Opc = X86ISD::PINSRW;
10740 assert(VT == MVT::v16i8);
10741 Opc = X86ISD::PINSRB;
10744 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10746 if (N1.getValueType() != MVT::i32)
10747 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10748 if (N2.getValueType() != MVT::i32)
10749 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10750 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10753 if (EltVT == MVT::f32) {
10754 // Bits [7:6] of the constant are the source select. This will always be
10755 // zero here. The DAG Combiner may combine an extract_elt index into
10756 // these bits. For example (insert (extract, 3), 2) could be matched by
10757 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10758 // Bits [5:4] of the constant are the destination select. This is the
10759 // value of the incoming immediate.
10760 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10761 // combine either bitwise AND or insert of float 0.0 to set these bits.
10763 const Function *F = DAG.getMachineFunction().getFunction();
10764 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10765 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10766 // If this is an insertion of 32-bits into the low 32-bits of
10767 // a vector, we prefer to generate a blend with immediate rather
10768 // than an insertps. Blends are simpler operations in hardware and so
10769 // will always have equal or better performance than insertps.
10770 // But if optimizing for size and there's a load folding opportunity,
10771 // generate insertps because blendps does not have a 32-bit memory
10773 N2 = DAG.getIntPtrConstant(1, dl);
10774 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10775 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10777 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10778 // Create this as a scalar to vector..
10779 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10780 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10783 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10784 // PINSR* works with constant index.
10789 if (EltVT == MVT::i8)
10792 if (EltVT.getSizeInBits() == 16) {
10793 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10794 // as its second argument.
10795 if (N1.getValueType() != MVT::i32)
10796 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10797 if (N2.getValueType() != MVT::i32)
10798 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10799 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10804 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10806 MVT OpVT = Op.getSimpleValueType();
10808 // If this is a 256-bit vector result, first insert into a 128-bit
10809 // vector and then insert into the 256-bit vector.
10810 if (!OpVT.is128BitVector()) {
10811 // Insert into a 128-bit vector.
10812 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10813 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10814 OpVT.getVectorNumElements() / SizeFactor);
10816 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10818 // Insert the 128-bit vector.
10819 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10822 if (OpVT == MVT::v1i64 &&
10823 Op.getOperand(0).getValueType() == MVT::i64)
10824 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10826 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10827 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10828 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10829 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10832 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10833 // a simple subregister reference or explicit instructions to grab
10834 // upper bits of a vector.
10835 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10836 SelectionDAG &DAG) {
10838 SDValue In = Op.getOperand(0);
10839 SDValue Idx = Op.getOperand(1);
10840 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10841 MVT ResVT = Op.getSimpleValueType();
10842 MVT InVT = In.getSimpleValueType();
10844 if (Subtarget->hasFp256()) {
10845 if (ResVT.is128BitVector() &&
10846 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10847 isa<ConstantSDNode>(Idx)) {
10848 return Extract128BitVector(In, IdxVal, DAG, dl);
10850 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10851 isa<ConstantSDNode>(Idx)) {
10852 return Extract256BitVector(In, IdxVal, DAG, dl);
10858 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10859 // simple superregister reference or explicit instructions to insert
10860 // the upper bits of a vector.
10861 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10862 SelectionDAG &DAG) {
10863 if (!Subtarget->hasAVX())
10867 SDValue Vec = Op.getOperand(0);
10868 SDValue SubVec = Op.getOperand(1);
10869 SDValue Idx = Op.getOperand(2);
10871 if (!isa<ConstantSDNode>(Idx))
10874 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10875 MVT OpVT = Op.getSimpleValueType();
10876 MVT SubVecVT = SubVec.getSimpleValueType();
10878 // Fold two 16-byte subvector loads into one 32-byte load:
10879 // (insert_subvector (insert_subvector undef, (load addr), 0),
10880 // (load addr + 16), Elts/2)
10882 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10883 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10884 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10885 !Subtarget->isUnalignedMem32Slow()) {
10886 SDValue SubVec2 = Vec.getOperand(1);
10887 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10888 if (Idx2->getZExtValue() == 0) {
10889 SDValue Ops[] = { SubVec2, SubVec };
10890 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10897 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10898 SubVecVT.is128BitVector())
10899 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10901 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10902 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10904 if (OpVT.getVectorElementType() == MVT::i1) {
10905 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10907 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10908 SDValue Undef = DAG.getUNDEF(OpVT);
10909 unsigned NumElems = OpVT.getVectorNumElements();
10910 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10912 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10913 // Zero upper bits of the Vec
10914 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10915 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10917 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10919 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10920 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10923 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10925 // Zero upper bits of the Vec2
10926 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10927 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10928 // Zero lower bits of the Vec
10929 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10930 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10931 // Merge them together
10932 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10938 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10939 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10940 // one of the above mentioned nodes. It has to be wrapped because otherwise
10941 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10942 // be used to form addressing mode. These wrapped nodes will be selected
10945 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10946 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10948 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10949 // global base reg.
10950 unsigned char OpFlag = 0;
10951 unsigned WrapperKind = X86ISD::Wrapper;
10952 CodeModel::Model M = DAG.getTarget().getCodeModel();
10954 if (Subtarget->isPICStyleRIPRel() &&
10955 (M == CodeModel::Small || M == CodeModel::Kernel))
10956 WrapperKind = X86ISD::WrapperRIP;
10957 else if (Subtarget->isPICStyleGOT())
10958 OpFlag = X86II::MO_GOTOFF;
10959 else if (Subtarget->isPICStyleStubPIC())
10960 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10962 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10963 CP->getAlignment(),
10964 CP->getOffset(), OpFlag);
10966 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10967 // With PIC, the address is actually $g + Offset.
10969 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10970 DAG.getNode(X86ISD::GlobalBaseReg,
10971 SDLoc(), getPointerTy()),
10978 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10979 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10981 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10982 // global base reg.
10983 unsigned char OpFlag = 0;
10984 unsigned WrapperKind = X86ISD::Wrapper;
10985 CodeModel::Model M = DAG.getTarget().getCodeModel();
10987 if (Subtarget->isPICStyleRIPRel() &&
10988 (M == CodeModel::Small || M == CodeModel::Kernel))
10989 WrapperKind = X86ISD::WrapperRIP;
10990 else if (Subtarget->isPICStyleGOT())
10991 OpFlag = X86II::MO_GOTOFF;
10992 else if (Subtarget->isPICStyleStubPIC())
10993 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10995 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10998 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11000 // With PIC, the address is actually $g + Offset.
11002 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11003 DAG.getNode(X86ISD::GlobalBaseReg,
11004 SDLoc(), getPointerTy()),
11011 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11012 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11014 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11015 // global base reg.
11016 unsigned char OpFlag = 0;
11017 unsigned WrapperKind = X86ISD::Wrapper;
11018 CodeModel::Model M = DAG.getTarget().getCodeModel();
11020 if (Subtarget->isPICStyleRIPRel() &&
11021 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11022 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11023 OpFlag = X86II::MO_GOTPCREL;
11024 WrapperKind = X86ISD::WrapperRIP;
11025 } else if (Subtarget->isPICStyleGOT()) {
11026 OpFlag = X86II::MO_GOT;
11027 } else if (Subtarget->isPICStyleStubPIC()) {
11028 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11029 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11030 OpFlag = X86II::MO_DARWIN_NONLAZY;
11033 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11036 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11038 // With PIC, the address is actually $g + Offset.
11039 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11040 !Subtarget->is64Bit()) {
11041 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11042 DAG.getNode(X86ISD::GlobalBaseReg,
11043 SDLoc(), getPointerTy()),
11047 // For symbols that require a load from a stub to get the address, emit the
11049 if (isGlobalStubReference(OpFlag))
11050 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11051 MachinePointerInfo::getGOT(), false, false, false, 0);
11057 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11058 // Create the TargetBlockAddressAddress node.
11059 unsigned char OpFlags =
11060 Subtarget->ClassifyBlockAddressReference();
11061 CodeModel::Model M = DAG.getTarget().getCodeModel();
11062 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11063 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11065 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11068 if (Subtarget->isPICStyleRIPRel() &&
11069 (M == CodeModel::Small || M == CodeModel::Kernel))
11070 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11072 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11074 // With PIC, the address is actually $g + Offset.
11075 if (isGlobalRelativeToPICBase(OpFlags)) {
11076 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11077 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11085 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11086 int64_t Offset, SelectionDAG &DAG) const {
11087 // Create the TargetGlobalAddress node, folding in the constant
11088 // offset if it is legal.
11089 unsigned char OpFlags =
11090 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11091 CodeModel::Model M = DAG.getTarget().getCodeModel();
11093 if (OpFlags == X86II::MO_NO_FLAG &&
11094 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11095 // A direct static reference to a global.
11096 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11099 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11102 if (Subtarget->isPICStyleRIPRel() &&
11103 (M == CodeModel::Small || M == CodeModel::Kernel))
11104 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11106 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11108 // With PIC, the address is actually $g + Offset.
11109 if (isGlobalRelativeToPICBase(OpFlags)) {
11110 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11111 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11115 // For globals that require a load from a stub to get the address, emit the
11117 if (isGlobalStubReference(OpFlags))
11118 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11119 MachinePointerInfo::getGOT(), false, false, false, 0);
11121 // If there was a non-zero offset that we didn't fold, create an explicit
11122 // addition for it.
11124 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11125 DAG.getConstant(Offset, dl, getPointerTy()));
11131 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11132 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11133 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11134 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11138 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11139 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11140 unsigned char OperandFlags, bool LocalDynamic = false) {
11141 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11142 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11144 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11145 GA->getValueType(0),
11149 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11153 SDValue Ops[] = { Chain, TGA, *InFlag };
11154 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11156 SDValue Ops[] = { Chain, TGA };
11157 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11160 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11161 MFI->setAdjustsStack(true);
11162 MFI->setHasCalls(true);
11164 SDValue Flag = Chain.getValue(1);
11165 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11168 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11170 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11173 SDLoc dl(GA); // ? function entry point might be better
11174 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11175 DAG.getNode(X86ISD::GlobalBaseReg,
11176 SDLoc(), PtrVT), InFlag);
11177 InFlag = Chain.getValue(1);
11179 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11182 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11184 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11186 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11187 X86::RAX, X86II::MO_TLSGD);
11190 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11196 // Get the start address of the TLS block for this module.
11197 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11198 .getInfo<X86MachineFunctionInfo>();
11199 MFI->incNumLocalDynamicTLSAccesses();
11203 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11204 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11207 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11208 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11209 InFlag = Chain.getValue(1);
11210 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11211 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11214 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11218 unsigned char OperandFlags = X86II::MO_DTPOFF;
11219 unsigned WrapperKind = X86ISD::Wrapper;
11220 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11221 GA->getValueType(0),
11222 GA->getOffset(), OperandFlags);
11223 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11225 // Add x@dtpoff with the base.
11226 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11229 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11230 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11231 const EVT PtrVT, TLSModel::Model model,
11232 bool is64Bit, bool isPIC) {
11235 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11236 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11237 is64Bit ? 257 : 256));
11239 SDValue ThreadPointer =
11240 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11241 MachinePointerInfo(Ptr), false, false, false, 0);
11243 unsigned char OperandFlags = 0;
11244 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11246 unsigned WrapperKind = X86ISD::Wrapper;
11247 if (model == TLSModel::LocalExec) {
11248 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11249 } else if (model == TLSModel::InitialExec) {
11251 OperandFlags = X86II::MO_GOTTPOFF;
11252 WrapperKind = X86ISD::WrapperRIP;
11254 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11257 llvm_unreachable("Unexpected model");
11260 // emit "addl x@ntpoff,%eax" (local exec)
11261 // or "addl x@indntpoff,%eax" (initial exec)
11262 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11264 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11265 GA->getOffset(), OperandFlags);
11266 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11268 if (model == TLSModel::InitialExec) {
11269 if (isPIC && !is64Bit) {
11270 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11271 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11275 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11276 MachinePointerInfo::getGOT(), false, false, false, 0);
11279 // The address of the thread local variable is the add of the thread
11280 // pointer with the offset of the variable.
11281 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11285 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11287 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11288 const GlobalValue *GV = GA->getGlobal();
11290 if (Subtarget->isTargetELF()) {
11291 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11294 case TLSModel::GeneralDynamic:
11295 if (Subtarget->is64Bit())
11296 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11297 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11298 case TLSModel::LocalDynamic:
11299 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11300 Subtarget->is64Bit());
11301 case TLSModel::InitialExec:
11302 case TLSModel::LocalExec:
11303 return LowerToTLSExecModel(
11304 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11305 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11307 llvm_unreachable("Unknown TLS model.");
11310 if (Subtarget->isTargetDarwin()) {
11311 // Darwin only has one model of TLS. Lower to that.
11312 unsigned char OpFlag = 0;
11313 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11314 X86ISD::WrapperRIP : X86ISD::Wrapper;
11316 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11317 // global base reg.
11318 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11319 !Subtarget->is64Bit();
11321 OpFlag = X86II::MO_TLVP_PIC_BASE;
11323 OpFlag = X86II::MO_TLVP;
11325 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11326 GA->getValueType(0),
11327 GA->getOffset(), OpFlag);
11328 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11330 // With PIC32, the address is actually $g + Offset.
11332 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11333 DAG.getNode(X86ISD::GlobalBaseReg,
11334 SDLoc(), getPointerTy()),
11337 // Lowering the machine isd will make sure everything is in the right
11339 SDValue Chain = DAG.getEntryNode();
11340 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11341 SDValue Args[] = { Chain, Offset };
11342 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11344 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11345 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11346 MFI->setAdjustsStack(true);
11348 // And our return value (tls address) is in the standard call return value
11350 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11351 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11352 Chain.getValue(1));
11355 if (Subtarget->isTargetKnownWindowsMSVC() ||
11356 Subtarget->isTargetWindowsGNU()) {
11357 // Just use the implicit TLS architecture
11358 // Need to generate someting similar to:
11359 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11361 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11362 // mov rcx, qword [rdx+rcx*8]
11363 // mov eax, .tls$:tlsvar
11364 // [rax+rcx] contains the address
11365 // Windows 64bit: gs:0x58
11366 // Windows 32bit: fs:__tls_array
11369 SDValue Chain = DAG.getEntryNode();
11371 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11372 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11373 // use its literal value of 0x2C.
11374 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11375 ? Type::getInt8PtrTy(*DAG.getContext(),
11377 : Type::getInt32PtrTy(*DAG.getContext(),
11381 Subtarget->is64Bit()
11382 ? DAG.getIntPtrConstant(0x58, dl)
11383 : (Subtarget->isTargetWindowsGNU()
11384 ? DAG.getIntPtrConstant(0x2C, dl)
11385 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11387 SDValue ThreadPointer =
11388 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11389 MachinePointerInfo(Ptr), false, false, false, 0);
11391 // Load the _tls_index variable
11392 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11393 if (Subtarget->is64Bit())
11394 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11395 IDX, MachinePointerInfo(), MVT::i32,
11396 false, false, false, 0);
11398 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11399 false, false, false, 0);
11401 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11403 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11405 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11406 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11407 false, false, false, 0);
11409 // Get the offset of start of .tls section
11410 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11411 GA->getValueType(0),
11412 GA->getOffset(), X86II::MO_SECREL);
11413 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11415 // The address of the thread local variable is the add of the thread
11416 // pointer with the offset of the variable.
11417 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11420 llvm_unreachable("TLS not implemented for this target.");
11423 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11424 /// and take a 2 x i32 value to shift plus a shift amount.
11425 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11426 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11427 MVT VT = Op.getSimpleValueType();
11428 unsigned VTBits = VT.getSizeInBits();
11430 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11431 SDValue ShOpLo = Op.getOperand(0);
11432 SDValue ShOpHi = Op.getOperand(1);
11433 SDValue ShAmt = Op.getOperand(2);
11434 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11435 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11437 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11438 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11439 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11440 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11441 : DAG.getConstant(0, dl, VT);
11443 SDValue Tmp2, Tmp3;
11444 if (Op.getOpcode() == ISD::SHL_PARTS) {
11445 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11446 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11448 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11449 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11452 // If the shift amount is larger or equal than the width of a part we can't
11453 // rely on the results of shld/shrd. Insert a test and select the appropriate
11454 // values for large shift amounts.
11455 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11456 DAG.getConstant(VTBits, dl, MVT::i8));
11457 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11458 AndNode, DAG.getConstant(0, dl, MVT::i8));
11461 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11462 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11463 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11465 if (Op.getOpcode() == ISD::SHL_PARTS) {
11466 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11467 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11469 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11470 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11473 SDValue Ops[2] = { Lo, Hi };
11474 return DAG.getMergeValues(Ops, dl);
11477 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11478 SelectionDAG &DAG) const {
11479 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11482 if (SrcVT.isVector()) {
11483 if (SrcVT.getVectorElementType() == MVT::i1) {
11484 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11485 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11486 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11487 Op.getOperand(0)));
11492 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11493 "Unknown SINT_TO_FP to lower!");
11495 // These are really Legal; return the operand so the caller accepts it as
11497 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11499 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11500 Subtarget->is64Bit()) {
11504 unsigned Size = SrcVT.getSizeInBits()/8;
11505 MachineFunction &MF = DAG.getMachineFunction();
11506 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11507 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11508 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11510 MachinePointerInfo::getFixedStack(SSFI),
11512 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11515 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11517 SelectionDAG &DAG) const {
11521 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11523 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11525 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11527 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11529 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11530 MachineMemOperand *MMO;
11532 int SSFI = FI->getIndex();
11534 DAG.getMachineFunction()
11535 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11536 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11538 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11539 StackSlot = StackSlot.getOperand(1);
11541 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11542 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11544 Tys, Ops, SrcVT, MMO);
11547 Chain = Result.getValue(1);
11548 SDValue InFlag = Result.getValue(2);
11550 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11551 // shouldn't be necessary except that RFP cannot be live across
11552 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11553 MachineFunction &MF = DAG.getMachineFunction();
11554 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11555 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11556 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11557 Tys = DAG.getVTList(MVT::Other);
11559 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11561 MachineMemOperand *MMO =
11562 DAG.getMachineFunction()
11563 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11564 MachineMemOperand::MOStore, SSFISize, SSFISize);
11566 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11567 Ops, Op.getValueType(), MMO);
11568 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11569 MachinePointerInfo::getFixedStack(SSFI),
11570 false, false, false, 0);
11576 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11577 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11578 SelectionDAG &DAG) const {
11579 // This algorithm is not obvious. Here it is what we're trying to output:
11582 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11583 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11585 haddpd %xmm0, %xmm0
11587 pshufd $0x4e, %xmm0, %xmm1
11593 LLVMContext *Context = DAG.getContext();
11595 // Build some magic constants.
11596 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11597 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11598 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11600 SmallVector<Constant*,2> CV1;
11602 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11603 APInt(64, 0x4330000000000000ULL))));
11605 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11606 APInt(64, 0x4530000000000000ULL))));
11607 Constant *C1 = ConstantVector::get(CV1);
11608 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11610 // Load the 64-bit value into an XMM register.
11611 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11613 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11614 MachinePointerInfo::getConstantPool(),
11615 false, false, false, 16);
11616 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11617 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11620 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11621 MachinePointerInfo::getConstantPool(),
11622 false, false, false, 16);
11623 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11624 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11627 if (Subtarget->hasSSE3()) {
11628 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11629 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11631 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11632 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11634 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11635 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11639 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11640 DAG.getIntPtrConstant(0, dl));
11643 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11644 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11645 SelectionDAG &DAG) const {
11647 // FP constant to bias correct the final result.
11648 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11651 // Load the 32-bit value into an XMM register.
11652 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11655 // Zero out the upper parts of the register.
11656 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11658 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11659 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11660 DAG.getIntPtrConstant(0, dl));
11662 // Or the load with the bias.
11663 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11664 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11665 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11666 MVT::v2f64, Load)),
11667 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11668 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11669 MVT::v2f64, Bias)));
11670 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11671 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11672 DAG.getIntPtrConstant(0, dl));
11674 // Subtract the bias.
11675 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11677 // Handle final rounding.
11678 EVT DestVT = Op.getValueType();
11680 if (DestVT.bitsLT(MVT::f64))
11681 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11682 DAG.getIntPtrConstant(0, dl));
11683 if (DestVT.bitsGT(MVT::f64))
11684 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11686 // Handle final rounding.
11690 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11691 const X86Subtarget &Subtarget) {
11692 // The algorithm is the following:
11693 // #ifdef __SSE4_1__
11694 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11695 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11696 // (uint4) 0x53000000, 0xaa);
11698 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11699 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11701 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11702 // return (float4) lo + fhi;
11705 SDValue V = Op->getOperand(0);
11706 EVT VecIntVT = V.getValueType();
11707 bool Is128 = VecIntVT == MVT::v4i32;
11708 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11709 // If we convert to something else than the supported type, e.g., to v4f64,
11711 if (VecFloatVT != Op->getValueType(0))
11714 unsigned NumElts = VecIntVT.getVectorNumElements();
11715 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11716 "Unsupported custom type");
11717 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11719 // In the #idef/#else code, we have in common:
11720 // - The vector of constants:
11726 // Create the splat vector for 0x4b000000.
11727 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11728 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11729 CstLow, CstLow, CstLow, CstLow};
11730 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11731 makeArrayRef(&CstLowArray[0], NumElts));
11732 // Create the splat vector for 0x53000000.
11733 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11734 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11735 CstHigh, CstHigh, CstHigh, CstHigh};
11736 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11737 makeArrayRef(&CstHighArray[0], NumElts));
11739 // Create the right shift.
11740 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11741 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11742 CstShift, CstShift, CstShift, CstShift};
11743 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11744 makeArrayRef(&CstShiftArray[0], NumElts));
11745 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11748 if (Subtarget.hasSSE41()) {
11749 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11750 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11751 SDValue VecCstLowBitcast =
11752 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11753 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11754 // Low will be bitcasted right away, so do not bother bitcasting back to its
11756 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11757 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11758 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11759 // (uint4) 0x53000000, 0xaa);
11760 SDValue VecCstHighBitcast =
11761 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11762 SDValue VecShiftBitcast =
11763 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11764 // High will be bitcasted right away, so do not bother bitcasting back to
11765 // its original type.
11766 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11767 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11769 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11770 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11771 CstMask, CstMask, CstMask);
11772 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11773 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11774 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11776 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11777 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11780 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11781 SDValue CstFAdd = DAG.getConstantFP(
11782 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11783 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11784 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11785 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11786 makeArrayRef(&CstFAddArray[0], NumElts));
11788 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11789 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11791 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11792 // return (float4) lo + fhi;
11793 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11794 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11797 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11798 SelectionDAG &DAG) const {
11799 SDValue N0 = Op.getOperand(0);
11800 MVT SVT = N0.getSimpleValueType();
11803 switch (SVT.SimpleTy) {
11805 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11810 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11811 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11812 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11816 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11819 if (Subtarget->hasAVX512())
11820 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11821 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11823 llvm_unreachable(nullptr);
11826 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11827 SelectionDAG &DAG) const {
11828 SDValue N0 = Op.getOperand(0);
11831 if (Op.getValueType().isVector())
11832 return lowerUINT_TO_FP_vec(Op, DAG);
11834 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11835 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11836 // the optimization here.
11837 if (DAG.SignBitIsZero(N0))
11838 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11840 MVT SrcVT = N0.getSimpleValueType();
11841 MVT DstVT = Op.getSimpleValueType();
11842 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11843 return LowerUINT_TO_FP_i64(Op, DAG);
11844 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11845 return LowerUINT_TO_FP_i32(Op, DAG);
11846 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11849 // Make a 64-bit buffer, and use it to build an FILD.
11850 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11851 if (SrcVT == MVT::i32) {
11852 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11853 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11854 getPointerTy(), StackSlot, WordOff);
11855 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11856 StackSlot, MachinePointerInfo(),
11858 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11859 OffsetSlot, MachinePointerInfo(),
11861 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11865 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11866 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11867 StackSlot, MachinePointerInfo(),
11869 // For i64 source, we need to add the appropriate power of 2 if the input
11870 // was negative. This is the same as the optimization in
11871 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11872 // we must be careful to do the computation in x87 extended precision, not
11873 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11874 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11875 MachineMemOperand *MMO =
11876 DAG.getMachineFunction()
11877 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11878 MachineMemOperand::MOLoad, 8, 8);
11880 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11881 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11882 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11885 APInt FF(32, 0x5F800000ULL);
11887 // Check whether the sign bit is set.
11888 SDValue SignSet = DAG.getSetCC(dl,
11889 getSetCCResultType(*DAG.getContext(), MVT::i64),
11891 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11893 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11894 SDValue FudgePtr = DAG.getConstantPool(
11895 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11898 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11899 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11900 SDValue Four = DAG.getIntPtrConstant(4, dl);
11901 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11903 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11905 // Load the value out, extending it from f32 to f80.
11906 // FIXME: Avoid the extend by constructing the right constant pool?
11907 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11908 FudgePtr, MachinePointerInfo::getConstantPool(),
11909 MVT::f32, false, false, false, 4);
11910 // Extend everything to 80 bits to force it to be done on x87.
11911 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11912 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11913 DAG.getIntPtrConstant(0, dl));
11916 std::pair<SDValue,SDValue>
11917 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11918 bool IsSigned, bool IsReplace) const {
11921 EVT DstTy = Op.getValueType();
11923 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11924 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11928 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11929 DstTy.getSimpleVT() >= MVT::i16 &&
11930 "Unknown FP_TO_INT to lower!");
11932 // These are really Legal.
11933 if (DstTy == MVT::i32 &&
11934 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11935 return std::make_pair(SDValue(), SDValue());
11936 if (Subtarget->is64Bit() &&
11937 DstTy == MVT::i64 &&
11938 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11939 return std::make_pair(SDValue(), SDValue());
11941 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11942 // stack slot, or into the FTOL runtime function.
11943 MachineFunction &MF = DAG.getMachineFunction();
11944 unsigned MemSize = DstTy.getSizeInBits()/8;
11945 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11946 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11949 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11950 Opc = X86ISD::WIN_FTOL;
11952 switch (DstTy.getSimpleVT().SimpleTy) {
11953 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11954 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11955 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11956 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11959 SDValue Chain = DAG.getEntryNode();
11960 SDValue Value = Op.getOperand(0);
11961 EVT TheVT = Op.getOperand(0).getValueType();
11962 // FIXME This causes a redundant load/store if the SSE-class value is already
11963 // in memory, such as if it is on the callstack.
11964 if (isScalarFPTypeInSSEReg(TheVT)) {
11965 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11966 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11967 MachinePointerInfo::getFixedStack(SSFI),
11969 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11971 Chain, StackSlot, DAG.getValueType(TheVT)
11974 MachineMemOperand *MMO =
11975 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11976 MachineMemOperand::MOLoad, MemSize, MemSize);
11977 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11978 Chain = Value.getValue(1);
11979 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11980 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11983 MachineMemOperand *MMO =
11984 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11985 MachineMemOperand::MOStore, MemSize, MemSize);
11987 if (Opc != X86ISD::WIN_FTOL) {
11988 // Build the FP_TO_INT*_IN_MEM
11989 SDValue Ops[] = { Chain, Value, StackSlot };
11990 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11992 return std::make_pair(FIST, StackSlot);
11994 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11995 DAG.getVTList(MVT::Other, MVT::Glue),
11997 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11998 MVT::i32, ftol.getValue(1));
11999 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12000 MVT::i32, eax.getValue(2));
12001 SDValue Ops[] = { eax, edx };
12002 SDValue pair = IsReplace
12003 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12004 : DAG.getMergeValues(Ops, DL);
12005 return std::make_pair(pair, SDValue());
12009 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12010 const X86Subtarget *Subtarget) {
12011 MVT VT = Op->getSimpleValueType(0);
12012 SDValue In = Op->getOperand(0);
12013 MVT InVT = In.getSimpleValueType();
12016 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12017 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12019 // Optimize vectors in AVX mode:
12022 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12023 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12024 // Concat upper and lower parts.
12027 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12028 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12029 // Concat upper and lower parts.
12032 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12033 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12034 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12037 if (Subtarget->hasInt256())
12038 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12040 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12041 SDValue Undef = DAG.getUNDEF(InVT);
12042 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12043 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12044 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12046 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12047 VT.getVectorNumElements()/2);
12049 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12050 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12052 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12055 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12056 SelectionDAG &DAG) {
12057 MVT VT = Op->getSimpleValueType(0);
12058 SDValue In = Op->getOperand(0);
12059 MVT InVT = In.getSimpleValueType();
12061 unsigned int NumElts = VT.getVectorNumElements();
12062 if (NumElts != 8 && NumElts != 16)
12065 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12066 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12068 assert(InVT.getVectorElementType() == MVT::i1);
12069 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12071 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12073 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12075 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12076 if (VT.is512BitVector())
12078 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12081 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12082 SelectionDAG &DAG) {
12083 if (Subtarget->hasFp256()) {
12084 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12092 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12093 SelectionDAG &DAG) {
12095 MVT VT = Op.getSimpleValueType();
12096 SDValue In = Op.getOperand(0);
12097 MVT SVT = In.getSimpleValueType();
12099 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12100 return LowerZERO_EXTEND_AVX512(Op, DAG);
12102 if (Subtarget->hasFp256()) {
12103 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12108 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12109 VT.getVectorNumElements() != SVT.getVectorNumElements());
12113 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12115 MVT VT = Op.getSimpleValueType();
12116 SDValue In = Op.getOperand(0);
12117 MVT InVT = In.getSimpleValueType();
12119 if (VT == MVT::i1) {
12120 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12121 "Invalid scalar TRUNCATE operation");
12122 if (InVT.getSizeInBits() >= 32)
12124 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12125 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12127 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12128 "Invalid TRUNCATE operation");
12130 // move vector to mask - truncate solution for SKX
12131 if (VT.getVectorElementType() == MVT::i1) {
12132 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12133 Subtarget->hasBWI())
12134 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12135 if ((InVT.is256BitVector() || InVT.is128BitVector())
12136 && InVT.getScalarSizeInBits() <= 16 &&
12137 Subtarget->hasBWI() && Subtarget->hasVLX())
12138 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12139 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12140 Subtarget->hasDQI())
12141 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12142 if ((InVT.is256BitVector() || InVT.is128BitVector())
12143 && InVT.getScalarSizeInBits() >= 32 &&
12144 Subtarget->hasDQI() && Subtarget->hasVLX())
12145 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12147 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12148 if (VT.getVectorElementType().getSizeInBits() >=8)
12149 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12151 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12152 unsigned NumElts = InVT.getVectorNumElements();
12153 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12154 if (InVT.getSizeInBits() < 512) {
12155 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12156 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12161 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12162 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12163 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12166 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12167 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12168 if (Subtarget->hasInt256()) {
12169 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12170 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12171 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12173 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12174 DAG.getIntPtrConstant(0, DL));
12177 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12178 DAG.getIntPtrConstant(0, DL));
12179 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12180 DAG.getIntPtrConstant(2, DL));
12181 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12182 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12183 static const int ShufMask[] = {0, 2, 4, 6};
12184 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12187 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12188 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12189 if (Subtarget->hasInt256()) {
12190 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12192 SmallVector<SDValue,32> pshufbMask;
12193 for (unsigned i = 0; i < 2; ++i) {
12194 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12195 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12196 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12197 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12198 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12199 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12200 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12201 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12202 for (unsigned j = 0; j < 8; ++j)
12203 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12205 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12206 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12207 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12209 static const int ShufMask[] = {0, 2, -1, -1};
12210 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12212 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12213 DAG.getIntPtrConstant(0, DL));
12214 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12217 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12218 DAG.getIntPtrConstant(0, DL));
12220 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12221 DAG.getIntPtrConstant(4, DL));
12223 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12224 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12226 // The PSHUFB mask:
12227 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12228 -1, -1, -1, -1, -1, -1, -1, -1};
12230 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12231 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12232 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12234 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12235 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12237 // The MOVLHPS Mask:
12238 static const int ShufMask2[] = {0, 1, 4, 5};
12239 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12240 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12243 // Handle truncation of V256 to V128 using shuffles.
12244 if (!VT.is128BitVector() || !InVT.is256BitVector())
12247 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12249 unsigned NumElems = VT.getVectorNumElements();
12250 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12252 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12253 // Prepare truncation shuffle mask
12254 for (unsigned i = 0; i != NumElems; ++i)
12255 MaskVec[i] = i * 2;
12256 SDValue V = DAG.getVectorShuffle(NVT, DL,
12257 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12258 DAG.getUNDEF(NVT), &MaskVec[0]);
12259 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12260 DAG.getIntPtrConstant(0, DL));
12263 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12264 SelectionDAG &DAG) const {
12265 assert(!Op.getSimpleValueType().isVector());
12267 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12268 /*IsSigned=*/ true, /*IsReplace=*/ false);
12269 SDValue FIST = Vals.first, StackSlot = Vals.second;
12270 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12271 if (!FIST.getNode()) return Op;
12273 if (StackSlot.getNode())
12274 // Load the result.
12275 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12276 FIST, StackSlot, MachinePointerInfo(),
12277 false, false, false, 0);
12279 // The node is the result.
12283 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12284 SelectionDAG &DAG) const {
12285 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12286 /*IsSigned=*/ false, /*IsReplace=*/ false);
12287 SDValue FIST = Vals.first, StackSlot = Vals.second;
12288 assert(FIST.getNode() && "Unexpected failure");
12290 if (StackSlot.getNode())
12291 // Load the result.
12292 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12293 FIST, StackSlot, MachinePointerInfo(),
12294 false, false, false, 0);
12296 // The node is the result.
12300 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12302 MVT VT = Op.getSimpleValueType();
12303 SDValue In = Op.getOperand(0);
12304 MVT SVT = In.getSimpleValueType();
12306 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12308 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12309 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12310 In, DAG.getUNDEF(SVT)));
12313 /// The only differences between FABS and FNEG are the mask and the logic op.
12314 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12315 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12316 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12317 "Wrong opcode for lowering FABS or FNEG.");
12319 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12321 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12322 // into an FNABS. We'll lower the FABS after that if it is still in use.
12324 for (SDNode *User : Op->uses())
12325 if (User->getOpcode() == ISD::FNEG)
12328 SDValue Op0 = Op.getOperand(0);
12329 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12332 MVT VT = Op.getSimpleValueType();
12333 // Assume scalar op for initialization; update for vector if needed.
12334 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12335 // generate a 16-byte vector constant and logic op even for the scalar case.
12336 // Using a 16-byte mask allows folding the load of the mask with
12337 // the logic op, so it can save (~4 bytes) on code size.
12339 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12340 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12341 // decide if we should generate a 16-byte constant mask when we only need 4 or
12342 // 8 bytes for the scalar case.
12343 if (VT.isVector()) {
12344 EltVT = VT.getVectorElementType();
12345 NumElts = VT.getVectorNumElements();
12348 unsigned EltBits = EltVT.getSizeInBits();
12349 LLVMContext *Context = DAG.getContext();
12350 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12352 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12353 Constant *C = ConstantInt::get(*Context, MaskElt);
12354 C = ConstantVector::getSplat(NumElts, C);
12355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12356 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12357 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12358 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12359 MachinePointerInfo::getConstantPool(),
12360 false, false, false, Alignment);
12362 if (VT.isVector()) {
12363 // For a vector, cast operands to a vector type, perform the logic op,
12364 // and cast the result back to the original value type.
12365 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12366 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12367 SDValue Operand = IsFNABS ?
12368 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12369 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12370 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12371 return DAG.getNode(ISD::BITCAST, dl, VT,
12372 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12375 // If not vector, then scalar.
12376 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12377 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12378 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12381 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12382 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12383 LLVMContext *Context = DAG.getContext();
12384 SDValue Op0 = Op.getOperand(0);
12385 SDValue Op1 = Op.getOperand(1);
12387 MVT VT = Op.getSimpleValueType();
12388 MVT SrcVT = Op1.getSimpleValueType();
12390 // If second operand is smaller, extend it first.
12391 if (SrcVT.bitsLT(VT)) {
12392 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12395 // And if it is bigger, shrink it first.
12396 if (SrcVT.bitsGT(VT)) {
12397 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12401 // At this point the operands and the result should have the same
12402 // type, and that won't be f80 since that is not custom lowered.
12404 const fltSemantics &Sem =
12405 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12406 const unsigned SizeInBits = VT.getSizeInBits();
12408 SmallVector<Constant *, 4> CV(
12409 VT == MVT::f64 ? 2 : 4,
12410 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12412 // First, clear all bits but the sign bit from the second operand (sign).
12413 CV[0] = ConstantFP::get(*Context,
12414 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12415 Constant *C = ConstantVector::get(CV);
12416 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12417 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12418 MachinePointerInfo::getConstantPool(),
12419 false, false, false, 16);
12420 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12422 // Next, clear the sign bit from the first operand (magnitude).
12423 // If it's a constant, we can clear it here.
12424 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12425 APFloat APF = Op0CN->getValueAPF();
12426 // If the magnitude is a positive zero, the sign bit alone is enough.
12427 if (APF.isPosZero())
12430 CV[0] = ConstantFP::get(*Context, APF);
12432 CV[0] = ConstantFP::get(
12434 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12436 C = ConstantVector::get(CV);
12437 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12438 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12439 MachinePointerInfo::getConstantPool(),
12440 false, false, false, 16);
12441 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12442 if (!isa<ConstantFPSDNode>(Op0))
12443 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12445 // OR the magnitude value with the sign bit.
12446 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12449 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12450 SDValue N0 = Op.getOperand(0);
12452 MVT VT = Op.getSimpleValueType();
12454 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12455 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12456 DAG.getConstant(1, dl, VT));
12457 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12460 // Check whether an OR'd tree is PTEST-able.
12461 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12462 SelectionDAG &DAG) {
12463 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12465 if (!Subtarget->hasSSE41())
12468 if (!Op->hasOneUse())
12471 SDNode *N = Op.getNode();
12474 SmallVector<SDValue, 8> Opnds;
12475 DenseMap<SDValue, unsigned> VecInMap;
12476 SmallVector<SDValue, 8> VecIns;
12477 EVT VT = MVT::Other;
12479 // Recognize a special case where a vector is casted into wide integer to
12481 Opnds.push_back(N->getOperand(0));
12482 Opnds.push_back(N->getOperand(1));
12484 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12485 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12486 // BFS traverse all OR'd operands.
12487 if (I->getOpcode() == ISD::OR) {
12488 Opnds.push_back(I->getOperand(0));
12489 Opnds.push_back(I->getOperand(1));
12490 // Re-evaluate the number of nodes to be traversed.
12491 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12495 // Quit if a non-EXTRACT_VECTOR_ELT
12496 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12499 // Quit if without a constant index.
12500 SDValue Idx = I->getOperand(1);
12501 if (!isa<ConstantSDNode>(Idx))
12504 SDValue ExtractedFromVec = I->getOperand(0);
12505 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12506 if (M == VecInMap.end()) {
12507 VT = ExtractedFromVec.getValueType();
12508 // Quit if not 128/256-bit vector.
12509 if (!VT.is128BitVector() && !VT.is256BitVector())
12511 // Quit if not the same type.
12512 if (VecInMap.begin() != VecInMap.end() &&
12513 VT != VecInMap.begin()->first.getValueType())
12515 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12516 VecIns.push_back(ExtractedFromVec);
12518 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12521 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12522 "Not extracted from 128-/256-bit vector.");
12524 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12526 for (DenseMap<SDValue, unsigned>::const_iterator
12527 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12528 // Quit if not all elements are used.
12529 if (I->second != FullMask)
12533 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12535 // Cast all vectors into TestVT for PTEST.
12536 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12537 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12539 // If more than one full vectors are evaluated, OR them first before PTEST.
12540 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12541 // Each iteration will OR 2 nodes and append the result until there is only
12542 // 1 node left, i.e. the final OR'd value of all vectors.
12543 SDValue LHS = VecIns[Slot];
12544 SDValue RHS = VecIns[Slot + 1];
12545 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12548 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12549 VecIns.back(), VecIns.back());
12552 /// \brief return true if \c Op has a use that doesn't just read flags.
12553 static bool hasNonFlagsUse(SDValue Op) {
12554 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12556 SDNode *User = *UI;
12557 unsigned UOpNo = UI.getOperandNo();
12558 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12559 // Look pass truncate.
12560 UOpNo = User->use_begin().getOperandNo();
12561 User = *User->use_begin();
12564 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12565 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12571 /// Emit nodes that will be selected as "test Op0,Op0", or something
12573 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12574 SelectionDAG &DAG) const {
12575 if (Op.getValueType() == MVT::i1) {
12576 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12577 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12578 DAG.getConstant(0, dl, MVT::i8));
12580 // CF and OF aren't always set the way we want. Determine which
12581 // of these we need.
12582 bool NeedCF = false;
12583 bool NeedOF = false;
12586 case X86::COND_A: case X86::COND_AE:
12587 case X86::COND_B: case X86::COND_BE:
12590 case X86::COND_G: case X86::COND_GE:
12591 case X86::COND_L: case X86::COND_LE:
12592 case X86::COND_O: case X86::COND_NO: {
12593 // Check if we really need to set the
12594 // Overflow flag. If NoSignedWrap is present
12595 // that is not actually needed.
12596 switch (Op->getOpcode()) {
12601 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12602 if (BinNode->Flags.hasNoSignedWrap())
12612 // See if we can use the EFLAGS value from the operand instead of
12613 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12614 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12615 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12616 // Emit a CMP with 0, which is the TEST pattern.
12617 //if (Op.getValueType() == MVT::i1)
12618 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12619 // DAG.getConstant(0, MVT::i1));
12620 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12621 DAG.getConstant(0, dl, Op.getValueType()));
12623 unsigned Opcode = 0;
12624 unsigned NumOperands = 0;
12626 // Truncate operations may prevent the merge of the SETCC instruction
12627 // and the arithmetic instruction before it. Attempt to truncate the operands
12628 // of the arithmetic instruction and use a reduced bit-width instruction.
12629 bool NeedTruncation = false;
12630 SDValue ArithOp = Op;
12631 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12632 SDValue Arith = Op->getOperand(0);
12633 // Both the trunc and the arithmetic op need to have one user each.
12634 if (Arith->hasOneUse())
12635 switch (Arith.getOpcode()) {
12642 NeedTruncation = true;
12648 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12649 // which may be the result of a CAST. We use the variable 'Op', which is the
12650 // non-casted variable when we check for possible users.
12651 switch (ArithOp.getOpcode()) {
12653 // Due to an isel shortcoming, be conservative if this add is likely to be
12654 // selected as part of a load-modify-store instruction. When the root node
12655 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12656 // uses of other nodes in the match, such as the ADD in this case. This
12657 // leads to the ADD being left around and reselected, with the result being
12658 // two adds in the output. Alas, even if none our users are stores, that
12659 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12660 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12661 // climbing the DAG back to the root, and it doesn't seem to be worth the
12663 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12664 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12665 if (UI->getOpcode() != ISD::CopyToReg &&
12666 UI->getOpcode() != ISD::SETCC &&
12667 UI->getOpcode() != ISD::STORE)
12670 if (ConstantSDNode *C =
12671 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12672 // An add of one will be selected as an INC.
12673 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12674 Opcode = X86ISD::INC;
12679 // An add of negative one (subtract of one) will be selected as a DEC.
12680 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12681 Opcode = X86ISD::DEC;
12687 // Otherwise use a regular EFLAGS-setting add.
12688 Opcode = X86ISD::ADD;
12693 // If we have a constant logical shift that's only used in a comparison
12694 // against zero turn it into an equivalent AND. This allows turning it into
12695 // a TEST instruction later.
12696 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12697 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12698 EVT VT = Op.getValueType();
12699 unsigned BitWidth = VT.getSizeInBits();
12700 unsigned ShAmt = Op->getConstantOperandVal(1);
12701 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12703 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12704 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12705 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12706 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12708 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12709 DAG.getConstant(Mask, dl, VT));
12710 DAG.ReplaceAllUsesWith(Op, New);
12716 // If the primary and result isn't used, don't bother using X86ISD::AND,
12717 // because a TEST instruction will be better.
12718 if (!hasNonFlagsUse(Op))
12724 // Due to the ISEL shortcoming noted above, be conservative if this op is
12725 // likely to be selected as part of a load-modify-store instruction.
12726 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12727 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12728 if (UI->getOpcode() == ISD::STORE)
12731 // Otherwise use a regular EFLAGS-setting instruction.
12732 switch (ArithOp.getOpcode()) {
12733 default: llvm_unreachable("unexpected operator!");
12734 case ISD::SUB: Opcode = X86ISD::SUB; break;
12735 case ISD::XOR: Opcode = X86ISD::XOR; break;
12736 case ISD::AND: Opcode = X86ISD::AND; break;
12738 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12739 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12740 if (EFLAGS.getNode())
12743 Opcode = X86ISD::OR;
12757 return SDValue(Op.getNode(), 1);
12763 // If we found that truncation is beneficial, perform the truncation and
12765 if (NeedTruncation) {
12766 EVT VT = Op.getValueType();
12767 SDValue WideVal = Op->getOperand(0);
12768 EVT WideVT = WideVal.getValueType();
12769 unsigned ConvertedOp = 0;
12770 // Use a target machine opcode to prevent further DAGCombine
12771 // optimizations that may separate the arithmetic operations
12772 // from the setcc node.
12773 switch (WideVal.getOpcode()) {
12775 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12776 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12777 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12778 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12779 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12783 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12784 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12785 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12786 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12787 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12793 // Emit a CMP with 0, which is the TEST pattern.
12794 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12795 DAG.getConstant(0, dl, Op.getValueType()));
12797 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12798 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12800 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12801 DAG.ReplaceAllUsesWith(Op, New);
12802 return SDValue(New.getNode(), 1);
12805 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12807 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12808 SDLoc dl, SelectionDAG &DAG) const {
12809 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12810 if (C->getAPIntValue() == 0)
12811 return EmitTest(Op0, X86CC, dl, DAG);
12813 if (Op0.getValueType() == MVT::i1)
12814 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12817 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12818 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12819 // Do the comparison at i32 if it's smaller, besides the Atom case.
12820 // This avoids subregister aliasing issues. Keep the smaller reference
12821 // if we're optimizing for size, however, as that'll allow better folding
12822 // of memory operations.
12823 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12824 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12825 Attribute::MinSize) &&
12826 !Subtarget->isAtom()) {
12827 unsigned ExtendOp =
12828 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12829 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12830 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12832 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12833 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12834 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12836 return SDValue(Sub.getNode(), 1);
12838 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12841 /// Convert a comparison if required by the subtarget.
12842 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12843 SelectionDAG &DAG) const {
12844 // If the subtarget does not support the FUCOMI instruction, floating-point
12845 // comparisons have to be converted.
12846 if (Subtarget->hasCMov() ||
12847 Cmp.getOpcode() != X86ISD::CMP ||
12848 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12849 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12852 // The instruction selector will select an FUCOM instruction instead of
12853 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12854 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12855 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12857 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12858 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12859 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12860 DAG.getConstant(8, dl, MVT::i8));
12861 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12862 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12865 /// The minimum architected relative accuracy is 2^-12. We need one
12866 /// Newton-Raphson step to have a good float result (24 bits of precision).
12867 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12868 DAGCombinerInfo &DCI,
12869 unsigned &RefinementSteps,
12870 bool &UseOneConstNR) const {
12871 // FIXME: We should use instruction latency models to calculate the cost of
12872 // each potential sequence, but this is very hard to do reliably because
12873 // at least Intel's Core* chips have variable timing based on the number of
12874 // significant digits in the divisor and/or sqrt operand.
12875 if (!Subtarget->useSqrtEst())
12878 EVT VT = Op.getValueType();
12880 // SSE1 has rsqrtss and rsqrtps.
12881 // TODO: Add support for AVX512 (v16f32).
12882 // It is likely not profitable to do this for f64 because a double-precision
12883 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12884 // instructions: convert to single, rsqrtss, convert back to double, refine
12885 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12886 // along with FMA, this could be a throughput win.
12887 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12888 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12889 RefinementSteps = 1;
12890 UseOneConstNR = false;
12891 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12896 /// The minimum architected relative accuracy is 2^-12. We need one
12897 /// Newton-Raphson step to have a good float result (24 bits of precision).
12898 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12899 DAGCombinerInfo &DCI,
12900 unsigned &RefinementSteps) const {
12901 // FIXME: We should use instruction latency models to calculate the cost of
12902 // each potential sequence, but this is very hard to do reliably because
12903 // at least Intel's Core* chips have variable timing based on the number of
12904 // significant digits in the divisor.
12905 if (!Subtarget->useReciprocalEst())
12908 EVT VT = Op.getValueType();
12910 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12911 // TODO: Add support for AVX512 (v16f32).
12912 // It is likely not profitable to do this for f64 because a double-precision
12913 // reciprocal estimate with refinement on x86 prior to FMA requires
12914 // 15 instructions: convert to single, rcpss, convert back to double, refine
12915 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12916 // along with FMA, this could be a throughput win.
12917 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12918 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12919 RefinementSteps = ReciprocalEstimateRefinementSteps;
12920 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12925 /// If we have at least two divisions that use the same divisor, convert to
12926 /// multplication by a reciprocal. This may need to be adjusted for a given
12927 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12928 /// This is because we still need one division to calculate the reciprocal and
12929 /// then we need two multiplies by that reciprocal as replacements for the
12930 /// original divisions.
12931 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12932 return NumUsers > 1;
12935 static bool isAllOnes(SDValue V) {
12936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12937 return C && C->isAllOnesValue();
12940 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12941 /// if it's possible.
12942 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12943 SDLoc dl, SelectionDAG &DAG) const {
12944 SDValue Op0 = And.getOperand(0);
12945 SDValue Op1 = And.getOperand(1);
12946 if (Op0.getOpcode() == ISD::TRUNCATE)
12947 Op0 = Op0.getOperand(0);
12948 if (Op1.getOpcode() == ISD::TRUNCATE)
12949 Op1 = Op1.getOperand(0);
12952 if (Op1.getOpcode() == ISD::SHL)
12953 std::swap(Op0, Op1);
12954 if (Op0.getOpcode() == ISD::SHL) {
12955 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12956 if (And00C->getZExtValue() == 1) {
12957 // If we looked past a truncate, check that it's only truncating away
12959 unsigned BitWidth = Op0.getValueSizeInBits();
12960 unsigned AndBitWidth = And.getValueSizeInBits();
12961 if (BitWidth > AndBitWidth) {
12963 DAG.computeKnownBits(Op0, Zeros, Ones);
12964 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12968 RHS = Op0.getOperand(1);
12970 } else if (Op1.getOpcode() == ISD::Constant) {
12971 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12972 uint64_t AndRHSVal = AndRHS->getZExtValue();
12973 SDValue AndLHS = Op0;
12975 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12976 LHS = AndLHS.getOperand(0);
12977 RHS = AndLHS.getOperand(1);
12980 // Use BT if the immediate can't be encoded in a TEST instruction.
12981 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12983 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
12987 if (LHS.getNode()) {
12988 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12989 // instruction. Since the shift amount is in-range-or-undefined, we know
12990 // that doing a bittest on the i32 value is ok. We extend to i32 because
12991 // the encoding for the i16 version is larger than the i32 version.
12992 // Also promote i16 to i32 for performance / code size reason.
12993 if (LHS.getValueType() == MVT::i8 ||
12994 LHS.getValueType() == MVT::i16)
12995 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12997 // If the operand types disagree, extend the shift amount to match. Since
12998 // BT ignores high bits (like shifts) we can use anyextend.
12999 if (LHS.getValueType() != RHS.getValueType())
13000 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13002 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13003 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13004 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13005 DAG.getConstant(Cond, dl, MVT::i8), BT);
13011 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13013 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13018 // SSE Condition code mapping:
13027 switch (SetCCOpcode) {
13028 default: llvm_unreachable("Unexpected SETCC condition");
13030 case ISD::SETEQ: SSECC = 0; break;
13032 case ISD::SETGT: Swap = true; // Fallthrough
13034 case ISD::SETOLT: SSECC = 1; break;
13036 case ISD::SETGE: Swap = true; // Fallthrough
13038 case ISD::SETOLE: SSECC = 2; break;
13039 case ISD::SETUO: SSECC = 3; break;
13041 case ISD::SETNE: SSECC = 4; break;
13042 case ISD::SETULE: Swap = true; // Fallthrough
13043 case ISD::SETUGE: SSECC = 5; break;
13044 case ISD::SETULT: Swap = true; // Fallthrough
13045 case ISD::SETUGT: SSECC = 6; break;
13046 case ISD::SETO: SSECC = 7; break;
13048 case ISD::SETONE: SSECC = 8; break;
13051 std::swap(Op0, Op1);
13056 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13057 // ones, and then concatenate the result back.
13058 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13059 MVT VT = Op.getSimpleValueType();
13061 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13062 "Unsupported value type for operation");
13064 unsigned NumElems = VT.getVectorNumElements();
13066 SDValue CC = Op.getOperand(2);
13068 // Extract the LHS vectors
13069 SDValue LHS = Op.getOperand(0);
13070 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13071 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13073 // Extract the RHS vectors
13074 SDValue RHS = Op.getOperand(1);
13075 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13076 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13078 // Issue the operation on the smaller types and concatenate the result back
13079 MVT EltVT = VT.getVectorElementType();
13080 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13081 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13082 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13083 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13086 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13087 SDValue Op0 = Op.getOperand(0);
13088 SDValue Op1 = Op.getOperand(1);
13089 SDValue CC = Op.getOperand(2);
13090 MVT VT = Op.getSimpleValueType();
13093 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13094 "Unexpected type for boolean compare operation");
13095 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13096 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13097 DAG.getConstant(-1, dl, VT));
13098 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13099 DAG.getConstant(-1, dl, VT));
13100 switch (SetCCOpcode) {
13101 default: llvm_unreachable("Unexpected SETCC condition");
13103 // (x != y) -> ~(x ^ y)
13104 return DAG.getNode(ISD::XOR, dl, VT,
13105 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13106 DAG.getConstant(-1, dl, VT));
13108 // (x == y) -> (x ^ y)
13109 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13112 // (x > y) -> (x & ~y)
13113 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13116 // (x < y) -> (~x & y)
13117 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13120 // (x <= y) -> (~x | y)
13121 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13124 // (x >=y) -> (x | ~y)
13125 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13129 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13130 const X86Subtarget *Subtarget) {
13131 SDValue Op0 = Op.getOperand(0);
13132 SDValue Op1 = Op.getOperand(1);
13133 SDValue CC = Op.getOperand(2);
13134 MVT VT = Op.getSimpleValueType();
13137 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13138 Op.getValueType().getScalarType() == MVT::i1 &&
13139 "Cannot set masked compare for this operation");
13141 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13143 bool Unsigned = false;
13146 switch (SetCCOpcode) {
13147 default: llvm_unreachable("Unexpected SETCC condition");
13148 case ISD::SETNE: SSECC = 4; break;
13149 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13150 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13151 case ISD::SETLT: Swap = true; //fall-through
13152 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13153 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13154 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13155 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13156 case ISD::SETULE: Unsigned = true; //fall-through
13157 case ISD::SETLE: SSECC = 2; break;
13161 std::swap(Op0, Op1);
13163 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13164 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13165 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13166 DAG.getConstant(SSECC, dl, MVT::i8));
13169 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13170 /// operand \p Op1. If non-trivial (for example because it's not constant)
13171 /// return an empty value.
13172 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13174 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13178 MVT VT = Op1.getSimpleValueType();
13179 MVT EVT = VT.getVectorElementType();
13180 unsigned n = VT.getVectorNumElements();
13181 SmallVector<SDValue, 8> ULTOp1;
13183 for (unsigned i = 0; i < n; ++i) {
13184 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13185 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13188 // Avoid underflow.
13189 APInt Val = Elt->getAPIntValue();
13193 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13196 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13199 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13200 SelectionDAG &DAG) {
13201 SDValue Op0 = Op.getOperand(0);
13202 SDValue Op1 = Op.getOperand(1);
13203 SDValue CC = Op.getOperand(2);
13204 MVT VT = Op.getSimpleValueType();
13205 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13206 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13211 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13212 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13215 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13216 unsigned Opc = X86ISD::CMPP;
13217 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13218 assert(VT.getVectorNumElements() <= 16);
13219 Opc = X86ISD::CMPM;
13221 // In the two special cases we can't handle, emit two comparisons.
13224 unsigned CombineOpc;
13225 if (SetCCOpcode == ISD::SETUEQ) {
13226 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13228 assert(SetCCOpcode == ISD::SETONE);
13229 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13232 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13233 DAG.getConstant(CC0, dl, MVT::i8));
13234 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13235 DAG.getConstant(CC1, dl, MVT::i8));
13236 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13238 // Handle all other FP comparisons here.
13239 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13240 DAG.getConstant(SSECC, dl, MVT::i8));
13243 // Break 256-bit integer vector compare into smaller ones.
13244 if (VT.is256BitVector() && !Subtarget->hasInt256())
13245 return Lower256IntVSETCC(Op, DAG);
13247 EVT OpVT = Op1.getValueType();
13248 if (OpVT.getVectorElementType() == MVT::i1)
13249 return LowerBoolVSETCC_AVX512(Op, DAG);
13251 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13252 if (Subtarget->hasAVX512()) {
13253 if (Op1.getValueType().is512BitVector() ||
13254 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13255 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13256 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13258 // In AVX-512 architecture setcc returns mask with i1 elements,
13259 // But there is no compare instruction for i8 and i16 elements in KNL.
13260 // We are not talking about 512-bit operands in this case, these
13261 // types are illegal.
13263 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13264 OpVT.getVectorElementType().getSizeInBits() >= 8))
13265 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13266 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13269 // We are handling one of the integer comparisons here. Since SSE only has
13270 // GT and EQ comparisons for integer, swapping operands and multiple
13271 // operations may be required for some comparisons.
13273 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13274 bool Subus = false;
13276 switch (SetCCOpcode) {
13277 default: llvm_unreachable("Unexpected SETCC condition");
13278 case ISD::SETNE: Invert = true;
13279 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13280 case ISD::SETLT: Swap = true;
13281 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13282 case ISD::SETGE: Swap = true;
13283 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13284 Invert = true; break;
13285 case ISD::SETULT: Swap = true;
13286 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13287 FlipSigns = true; break;
13288 case ISD::SETUGE: Swap = true;
13289 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13290 FlipSigns = true; Invert = true; break;
13293 // Special case: Use min/max operations for SETULE/SETUGE
13294 MVT VET = VT.getVectorElementType();
13296 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13297 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13300 switch (SetCCOpcode) {
13302 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13303 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13306 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13309 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13310 if (!MinMax && hasSubus) {
13311 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13313 // t = psubus Op0, Op1
13314 // pcmpeq t, <0..0>
13315 switch (SetCCOpcode) {
13317 case ISD::SETULT: {
13318 // If the comparison is against a constant we can turn this into a
13319 // setule. With psubus, setule does not require a swap. This is
13320 // beneficial because the constant in the register is no longer
13321 // destructed as the destination so it can be hoisted out of a loop.
13322 // Only do this pre-AVX since vpcmp* is no longer destructive.
13323 if (Subtarget->hasAVX())
13325 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13326 if (ULEOp1.getNode()) {
13328 Subus = true; Invert = false; Swap = false;
13332 // Psubus is better than flip-sign because it requires no inversion.
13333 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13334 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13338 Opc = X86ISD::SUBUS;
13344 std::swap(Op0, Op1);
13346 // Check that the operation in question is available (most are plain SSE2,
13347 // but PCMPGTQ and PCMPEQQ have different requirements).
13348 if (VT == MVT::v2i64) {
13349 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13350 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13352 // First cast everything to the right type.
13353 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13354 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13356 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13357 // bits of the inputs before performing those operations. The lower
13358 // compare is always unsigned.
13361 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13363 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13364 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13365 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13366 Sign, Zero, Sign, Zero);
13368 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13369 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13371 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13372 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13373 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13375 // Create masks for only the low parts/high parts of the 64 bit integers.
13376 static const int MaskHi[] = { 1, 1, 3, 3 };
13377 static const int MaskLo[] = { 0, 0, 2, 2 };
13378 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13379 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13380 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13382 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13383 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13386 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13388 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13391 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13392 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13393 // pcmpeqd + pshufd + pand.
13394 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13396 // First cast everything to the right type.
13397 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13398 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13401 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13403 // Make sure the lower and upper halves are both all-ones.
13404 static const int Mask[] = { 1, 0, 3, 2 };
13405 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13406 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13409 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13411 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13415 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13416 // bits of the inputs before performing those operations.
13418 EVT EltVT = VT.getVectorElementType();
13419 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13421 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13422 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13425 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13427 // If the logical-not of the result is required, perform that now.
13429 Result = DAG.getNOT(dl, Result, VT);
13432 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13435 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13436 getZeroVector(VT, Subtarget, DAG, dl));
13441 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13443 MVT VT = Op.getSimpleValueType();
13445 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13447 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13448 && "SetCC type must be 8-bit or 1-bit integer");
13449 SDValue Op0 = Op.getOperand(0);
13450 SDValue Op1 = Op.getOperand(1);
13452 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13454 // Optimize to BT if possible.
13455 // Lower (X & (1 << N)) == 0 to BT(X, N).
13456 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13457 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13458 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13459 Op1.getOpcode() == ISD::Constant &&
13460 cast<ConstantSDNode>(Op1)->isNullValue() &&
13461 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13462 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13463 if (NewSetCC.getNode()) {
13465 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13470 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13472 if (Op1.getOpcode() == ISD::Constant &&
13473 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13474 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13475 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13477 // If the input is a setcc, then reuse the input setcc or use a new one with
13478 // the inverted condition.
13479 if (Op0.getOpcode() == X86ISD::SETCC) {
13480 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13481 bool Invert = (CC == ISD::SETNE) ^
13482 cast<ConstantSDNode>(Op1)->isNullValue();
13486 CCode = X86::GetOppositeBranchCondition(CCode);
13487 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13488 DAG.getConstant(CCode, dl, MVT::i8),
13489 Op0.getOperand(1));
13491 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13495 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13496 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13497 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13499 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13500 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13503 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13504 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13505 if (X86CC == X86::COND_INVALID)
13508 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13509 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13510 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13511 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13513 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13517 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13518 static bool isX86LogicalCmp(SDValue Op) {
13519 unsigned Opc = Op.getNode()->getOpcode();
13520 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13521 Opc == X86ISD::SAHF)
13523 if (Op.getResNo() == 1 &&
13524 (Opc == X86ISD::ADD ||
13525 Opc == X86ISD::SUB ||
13526 Opc == X86ISD::ADC ||
13527 Opc == X86ISD::SBB ||
13528 Opc == X86ISD::SMUL ||
13529 Opc == X86ISD::UMUL ||
13530 Opc == X86ISD::INC ||
13531 Opc == X86ISD::DEC ||
13532 Opc == X86ISD::OR ||
13533 Opc == X86ISD::XOR ||
13534 Opc == X86ISD::AND))
13537 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13543 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13544 if (V.getOpcode() != ISD::TRUNCATE)
13547 SDValue VOp0 = V.getOperand(0);
13548 unsigned InBits = VOp0.getValueSizeInBits();
13549 unsigned Bits = V.getValueSizeInBits();
13550 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13553 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13554 bool addTest = true;
13555 SDValue Cond = Op.getOperand(0);
13556 SDValue Op1 = Op.getOperand(1);
13557 SDValue Op2 = Op.getOperand(2);
13559 EVT VT = Op1.getValueType();
13562 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13563 // are available or VBLENDV if AVX is available.
13564 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13565 if (Cond.getOpcode() == ISD::SETCC &&
13566 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13567 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13568 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13569 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13570 int SSECC = translateX86FSETCC(
13571 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13574 if (Subtarget->hasAVX512()) {
13575 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13576 DAG.getConstant(SSECC, DL, MVT::i8));
13577 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13580 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13581 DAG.getConstant(SSECC, DL, MVT::i8));
13583 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13584 // of 3 logic instructions for size savings and potentially speed.
13585 // Unfortunately, there is no scalar form of VBLENDV.
13587 // If either operand is a constant, don't try this. We can expect to
13588 // optimize away at least one of the logic instructions later in that
13589 // case, so that sequence would be faster than a variable blend.
13591 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13592 // uses XMM0 as the selection register. That may need just as many
13593 // instructions as the AND/ANDN/OR sequence due to register moves, so
13596 if (Subtarget->hasAVX() &&
13597 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13599 // Convert to vectors, do a VSELECT, and convert back to scalar.
13600 // All of the conversions should be optimized away.
13602 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13603 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13604 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13605 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13607 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13608 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13610 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13612 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13613 VSel, DAG.getIntPtrConstant(0, DL));
13615 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13616 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13617 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13621 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13622 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13623 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13624 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13625 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13626 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13627 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13629 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13632 if (Cond.getOpcode() == ISD::SETCC) {
13633 SDValue NewCond = LowerSETCC(Cond, DAG);
13634 if (NewCond.getNode())
13638 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13639 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13640 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13641 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13642 if (Cond.getOpcode() == X86ISD::SETCC &&
13643 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13644 isZero(Cond.getOperand(1).getOperand(1))) {
13645 SDValue Cmp = Cond.getOperand(1);
13647 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13649 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13650 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13651 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13653 SDValue CmpOp0 = Cmp.getOperand(0);
13654 // Apply further optimizations for special cases
13655 // (select (x != 0), -1, 0) -> neg & sbb
13656 // (select (x == 0), 0, -1) -> neg & sbb
13657 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13658 if (YC->isNullValue() &&
13659 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13660 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13661 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13662 DAG.getConstant(0, DL,
13663 CmpOp0.getValueType()),
13665 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13666 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13667 SDValue(Neg.getNode(), 1));
13671 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13672 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13673 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13675 SDValue Res = // Res = 0 or -1.
13676 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13677 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13679 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13680 Res = DAG.getNOT(DL, Res, Res.getValueType());
13682 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13683 if (!N2C || !N2C->isNullValue())
13684 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13689 // Look past (and (setcc_carry (cmp ...)), 1).
13690 if (Cond.getOpcode() == ISD::AND &&
13691 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13692 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13693 if (C && C->getAPIntValue() == 1)
13694 Cond = Cond.getOperand(0);
13697 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13698 // setting operand in place of the X86ISD::SETCC.
13699 unsigned CondOpcode = Cond.getOpcode();
13700 if (CondOpcode == X86ISD::SETCC ||
13701 CondOpcode == X86ISD::SETCC_CARRY) {
13702 CC = Cond.getOperand(0);
13704 SDValue Cmp = Cond.getOperand(1);
13705 unsigned Opc = Cmp.getOpcode();
13706 MVT VT = Op.getSimpleValueType();
13708 bool IllegalFPCMov = false;
13709 if (VT.isFloatingPoint() && !VT.isVector() &&
13710 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13711 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13713 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13714 Opc == X86ISD::BT) { // FIXME
13718 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13719 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13720 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13721 Cond.getOperand(0).getValueType() != MVT::i8)) {
13722 SDValue LHS = Cond.getOperand(0);
13723 SDValue RHS = Cond.getOperand(1);
13724 unsigned X86Opcode;
13727 switch (CondOpcode) {
13728 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13729 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13730 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13731 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13732 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13733 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13734 default: llvm_unreachable("unexpected overflowing operator");
13736 if (CondOpcode == ISD::UMULO)
13737 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13740 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13742 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13744 if (CondOpcode == ISD::UMULO)
13745 Cond = X86Op.getValue(2);
13747 Cond = X86Op.getValue(1);
13749 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13754 // Look pass the truncate if the high bits are known zero.
13755 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13756 Cond = Cond.getOperand(0);
13758 // We know the result of AND is compared against zero. Try to match
13760 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13761 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13762 if (NewSetCC.getNode()) {
13763 CC = NewSetCC.getOperand(0);
13764 Cond = NewSetCC.getOperand(1);
13771 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13772 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13775 // a < b ? -1 : 0 -> RES = ~setcc_carry
13776 // a < b ? 0 : -1 -> RES = setcc_carry
13777 // a >= b ? -1 : 0 -> RES = setcc_carry
13778 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13779 if (Cond.getOpcode() == X86ISD::SUB) {
13780 Cond = ConvertCmpIfNecessary(Cond, DAG);
13781 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13783 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13784 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13785 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13786 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13788 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13789 return DAG.getNOT(DL, Res, Res.getValueType());
13794 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13795 // widen the cmov and push the truncate through. This avoids introducing a new
13796 // branch during isel and doesn't add any extensions.
13797 if (Op.getValueType() == MVT::i8 &&
13798 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13799 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13800 if (T1.getValueType() == T2.getValueType() &&
13801 // Blacklist CopyFromReg to avoid partial register stalls.
13802 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13803 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13804 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13805 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13809 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13810 // condition is true.
13811 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13812 SDValue Ops[] = { Op2, Op1, CC, Cond };
13813 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13816 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13817 SelectionDAG &DAG) {
13818 MVT VT = Op->getSimpleValueType(0);
13819 SDValue In = Op->getOperand(0);
13820 MVT InVT = In.getSimpleValueType();
13821 MVT VTElt = VT.getVectorElementType();
13822 MVT InVTElt = InVT.getVectorElementType();
13826 if ((InVTElt == MVT::i1) &&
13827 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13828 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13830 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13831 VTElt.getSizeInBits() <= 16)) ||
13833 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13834 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13836 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13837 VTElt.getSizeInBits() >= 32))))
13838 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13840 unsigned int NumElts = VT.getVectorNumElements();
13842 if (NumElts != 8 && NumElts != 16)
13845 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13846 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13847 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13848 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13851 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13852 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13854 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
13857 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
13859 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
13860 if (VT.is512BitVector())
13862 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
13865 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13866 SelectionDAG &DAG) {
13867 MVT VT = Op->getSimpleValueType(0);
13868 SDValue In = Op->getOperand(0);
13869 MVT InVT = In.getSimpleValueType();
13872 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13873 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13875 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13876 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13877 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13880 if (Subtarget->hasInt256())
13881 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13883 // Optimize vectors in AVX mode
13884 // Sign extend v8i16 to v8i32 and
13887 // Divide input vector into two parts
13888 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13889 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13890 // concat the vectors to original VT
13892 unsigned NumElems = InVT.getVectorNumElements();
13893 SDValue Undef = DAG.getUNDEF(InVT);
13895 SmallVector<int,8> ShufMask1(NumElems, -1);
13896 for (unsigned i = 0; i != NumElems/2; ++i)
13899 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13901 SmallVector<int,8> ShufMask2(NumElems, -1);
13902 for (unsigned i = 0; i != NumElems/2; ++i)
13903 ShufMask2[i] = i + NumElems/2;
13905 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13907 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13908 VT.getVectorNumElements()/2);
13910 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13911 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13913 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13916 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13917 // may emit an illegal shuffle but the expansion is still better than scalar
13918 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13919 // we'll emit a shuffle and a arithmetic shift.
13920 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13921 // TODO: It is possible to support ZExt by zeroing the undef values during
13922 // the shuffle phase or after the shuffle.
13923 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13924 SelectionDAG &DAG) {
13925 MVT RegVT = Op.getSimpleValueType();
13926 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13927 assert(RegVT.isInteger() &&
13928 "We only custom lower integer vector sext loads.");
13930 // Nothing useful we can do without SSE2 shuffles.
13931 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13933 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13935 EVT MemVT = Ld->getMemoryVT();
13936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13937 unsigned RegSz = RegVT.getSizeInBits();
13939 ISD::LoadExtType Ext = Ld->getExtensionType();
13941 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13942 && "Only anyext and sext are currently implemented.");
13943 assert(MemVT != RegVT && "Cannot extend to the same type");
13944 assert(MemVT.isVector() && "Must load a vector from memory");
13946 unsigned NumElems = RegVT.getVectorNumElements();
13947 unsigned MemSz = MemVT.getSizeInBits();
13948 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13950 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13951 // The only way in which we have a legal 256-bit vector result but not the
13952 // integer 256-bit operations needed to directly lower a sextload is if we
13953 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13954 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13955 // correctly legalized. We do this late to allow the canonical form of
13956 // sextload to persist throughout the rest of the DAG combiner -- it wants
13957 // to fold together any extensions it can, and so will fuse a sign_extend
13958 // of an sextload into a sextload targeting a wider value.
13960 if (MemSz == 128) {
13961 // Just switch this to a normal load.
13962 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13963 "it must be a legal 128-bit vector "
13965 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13966 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13967 Ld->isInvariant(), Ld->getAlignment());
13969 assert(MemSz < 128 &&
13970 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13971 // Do an sext load to a 128-bit vector type. We want to use the same
13972 // number of elements, but elements half as wide. This will end up being
13973 // recursively lowered by this routine, but will succeed as we definitely
13974 // have all the necessary features if we're using AVX1.
13976 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13977 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13979 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13980 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13981 Ld->isNonTemporal(), Ld->isInvariant(),
13982 Ld->getAlignment());
13985 // Replace chain users with the new chain.
13986 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13987 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13989 // Finally, do a normal sign-extend to the desired register.
13990 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13993 // All sizes must be a power of two.
13994 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13995 "Non-power-of-two elements are not custom lowered!");
13997 // Attempt to load the original value using scalar loads.
13998 // Find the largest scalar type that divides the total loaded size.
13999 MVT SclrLoadTy = MVT::i8;
14000 for (MVT Tp : MVT::integer_valuetypes()) {
14001 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14006 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14007 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14009 SclrLoadTy = MVT::f64;
14011 // Calculate the number of scalar loads that we need to perform
14012 // in order to load our vector from memory.
14013 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14015 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14016 "Can only lower sext loads with a single scalar load!");
14018 unsigned loadRegZize = RegSz;
14019 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14022 // Represent our vector as a sequence of elements which are the
14023 // largest scalar that we can load.
14024 EVT LoadUnitVecVT = EVT::getVectorVT(
14025 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14027 // Represent the data using the same element type that is stored in
14028 // memory. In practice, we ''widen'' MemVT.
14030 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14031 loadRegZize / MemVT.getScalarType().getSizeInBits());
14033 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14034 "Invalid vector type");
14036 // We can't shuffle using an illegal type.
14037 assert(TLI.isTypeLegal(WideVecVT) &&
14038 "We only lower types that form legal widened vector types");
14040 SmallVector<SDValue, 8> Chains;
14041 SDValue Ptr = Ld->getBasePtr();
14042 SDValue Increment =
14043 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14044 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14046 for (unsigned i = 0; i < NumLoads; ++i) {
14047 // Perform a single load.
14048 SDValue ScalarLoad =
14049 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14050 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14051 Ld->getAlignment());
14052 Chains.push_back(ScalarLoad.getValue(1));
14053 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14054 // another round of DAGCombining.
14056 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14058 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14059 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14061 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14064 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14066 // Bitcast the loaded value to a vector of the original element type, in
14067 // the size of the target vector type.
14068 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14069 unsigned SizeRatio = RegSz / MemSz;
14071 if (Ext == ISD::SEXTLOAD) {
14072 // If we have SSE4.1, we can directly emit a VSEXT node.
14073 if (Subtarget->hasSSE41()) {
14074 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14075 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14079 // Otherwise we'll shuffle the small elements in the high bits of the
14080 // larger type and perform an arithmetic shift. If the shift is not legal
14081 // it's better to scalarize.
14082 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14083 "We can't implement a sext load without an arithmetic right shift!");
14085 // Redistribute the loaded elements into the different locations.
14086 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14087 for (unsigned i = 0; i != NumElems; ++i)
14088 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14090 SDValue Shuff = DAG.getVectorShuffle(
14091 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14093 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14095 // Build the arithmetic shift.
14096 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14097 MemVT.getVectorElementType().getSizeInBits();
14099 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14100 DAG.getConstant(Amt, dl, RegVT));
14102 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14106 // Redistribute the loaded elements into the different locations.
14107 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14108 for (unsigned i = 0; i != NumElems; ++i)
14109 ShuffleVec[i * SizeRatio] = i;
14111 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14112 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14114 // Bitcast to the requested type.
14115 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14116 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14120 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14121 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14122 // from the AND / OR.
14123 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14124 Opc = Op.getOpcode();
14125 if (Opc != ISD::OR && Opc != ISD::AND)
14127 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14128 Op.getOperand(0).hasOneUse() &&
14129 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14130 Op.getOperand(1).hasOneUse());
14133 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14134 // 1 and that the SETCC node has a single use.
14135 static bool isXor1OfSetCC(SDValue Op) {
14136 if (Op.getOpcode() != ISD::XOR)
14138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14139 if (N1C && N1C->getAPIntValue() == 1) {
14140 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14141 Op.getOperand(0).hasOneUse();
14146 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14147 bool addTest = true;
14148 SDValue Chain = Op.getOperand(0);
14149 SDValue Cond = Op.getOperand(1);
14150 SDValue Dest = Op.getOperand(2);
14153 bool Inverted = false;
14155 if (Cond.getOpcode() == ISD::SETCC) {
14156 // Check for setcc([su]{add,sub,mul}o == 0).
14157 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14158 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14159 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14160 Cond.getOperand(0).getResNo() == 1 &&
14161 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14162 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14163 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14164 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14165 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14166 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14168 Cond = Cond.getOperand(0);
14170 SDValue NewCond = LowerSETCC(Cond, DAG);
14171 if (NewCond.getNode())
14176 // FIXME: LowerXALUO doesn't handle these!!
14177 else if (Cond.getOpcode() == X86ISD::ADD ||
14178 Cond.getOpcode() == X86ISD::SUB ||
14179 Cond.getOpcode() == X86ISD::SMUL ||
14180 Cond.getOpcode() == X86ISD::UMUL)
14181 Cond = LowerXALUO(Cond, DAG);
14184 // Look pass (and (setcc_carry (cmp ...)), 1).
14185 if (Cond.getOpcode() == ISD::AND &&
14186 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14187 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14188 if (C && C->getAPIntValue() == 1)
14189 Cond = Cond.getOperand(0);
14192 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14193 // setting operand in place of the X86ISD::SETCC.
14194 unsigned CondOpcode = Cond.getOpcode();
14195 if (CondOpcode == X86ISD::SETCC ||
14196 CondOpcode == X86ISD::SETCC_CARRY) {
14197 CC = Cond.getOperand(0);
14199 SDValue Cmp = Cond.getOperand(1);
14200 unsigned Opc = Cmp.getOpcode();
14201 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14202 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14206 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14210 // These can only come from an arithmetic instruction with overflow,
14211 // e.g. SADDO, UADDO.
14212 Cond = Cond.getNode()->getOperand(1);
14218 CondOpcode = Cond.getOpcode();
14219 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14220 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14221 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14222 Cond.getOperand(0).getValueType() != MVT::i8)) {
14223 SDValue LHS = Cond.getOperand(0);
14224 SDValue RHS = Cond.getOperand(1);
14225 unsigned X86Opcode;
14228 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14229 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14231 switch (CondOpcode) {
14232 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14236 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14239 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14240 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14244 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14247 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14248 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14249 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14250 default: llvm_unreachable("unexpected overflowing operator");
14253 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14254 if (CondOpcode == ISD::UMULO)
14255 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14258 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14260 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14262 if (CondOpcode == ISD::UMULO)
14263 Cond = X86Op.getValue(2);
14265 Cond = X86Op.getValue(1);
14267 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14271 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14272 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14273 if (CondOpc == ISD::OR) {
14274 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14275 // two branches instead of an explicit OR instruction with a
14277 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14278 isX86LogicalCmp(Cmp)) {
14279 CC = Cond.getOperand(0).getOperand(0);
14280 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14281 Chain, Dest, CC, Cmp);
14282 CC = Cond.getOperand(1).getOperand(0);
14286 } else { // ISD::AND
14287 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14288 // two branches instead of an explicit AND instruction with a
14289 // separate test. However, we only do this if this block doesn't
14290 // have a fall-through edge, because this requires an explicit
14291 // jmp when the condition is false.
14292 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14293 isX86LogicalCmp(Cmp) &&
14294 Op.getNode()->hasOneUse()) {
14295 X86::CondCode CCode =
14296 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14297 CCode = X86::GetOppositeBranchCondition(CCode);
14298 CC = DAG.getConstant(CCode, dl, MVT::i8);
14299 SDNode *User = *Op.getNode()->use_begin();
14300 // Look for an unconditional branch following this conditional branch.
14301 // We need this because we need to reverse the successors in order
14302 // to implement FCMP_OEQ.
14303 if (User->getOpcode() == ISD::BR) {
14304 SDValue FalseBB = User->getOperand(1);
14306 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14307 assert(NewBR == User);
14311 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14312 Chain, Dest, CC, Cmp);
14313 X86::CondCode CCode =
14314 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14315 CCode = X86::GetOppositeBranchCondition(CCode);
14316 CC = DAG.getConstant(CCode, dl, MVT::i8);
14322 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14323 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14324 // It should be transformed during dag combiner except when the condition
14325 // is set by a arithmetics with overflow node.
14326 X86::CondCode CCode =
14327 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14328 CCode = X86::GetOppositeBranchCondition(CCode);
14329 CC = DAG.getConstant(CCode, dl, MVT::i8);
14330 Cond = Cond.getOperand(0).getOperand(1);
14332 } else if (Cond.getOpcode() == ISD::SETCC &&
14333 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14334 // For FCMP_OEQ, we can emit
14335 // two branches instead of an explicit AND instruction with a
14336 // separate test. However, we only do this if this block doesn't
14337 // have a fall-through edge, because this requires an explicit
14338 // jmp when the condition is false.
14339 if (Op.getNode()->hasOneUse()) {
14340 SDNode *User = *Op.getNode()->use_begin();
14341 // Look for an unconditional branch following this conditional branch.
14342 // We need this because we need to reverse the successors in order
14343 // to implement FCMP_OEQ.
14344 if (User->getOpcode() == ISD::BR) {
14345 SDValue FalseBB = User->getOperand(1);
14347 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14348 assert(NewBR == User);
14352 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14353 Cond.getOperand(0), Cond.getOperand(1));
14354 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14355 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14356 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14357 Chain, Dest, CC, Cmp);
14358 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14363 } else if (Cond.getOpcode() == ISD::SETCC &&
14364 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14365 // For FCMP_UNE, we can emit
14366 // two branches instead of an explicit AND instruction with a
14367 // separate test. However, we only do this if this block doesn't
14368 // have a fall-through edge, because this requires an explicit
14369 // jmp when the condition is false.
14370 if (Op.getNode()->hasOneUse()) {
14371 SDNode *User = *Op.getNode()->use_begin();
14372 // Look for an unconditional branch following this conditional branch.
14373 // We need this because we need to reverse the successors in order
14374 // to implement FCMP_UNE.
14375 if (User->getOpcode() == ISD::BR) {
14376 SDValue FalseBB = User->getOperand(1);
14378 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14379 assert(NewBR == User);
14382 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14383 Cond.getOperand(0), Cond.getOperand(1));
14384 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14385 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14386 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14387 Chain, Dest, CC, Cmp);
14388 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14398 // Look pass the truncate if the high bits are known zero.
14399 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14400 Cond = Cond.getOperand(0);
14402 // We know the result of AND is compared against zero. Try to match
14404 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14405 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14406 if (NewSetCC.getNode()) {
14407 CC = NewSetCC.getOperand(0);
14408 Cond = NewSetCC.getOperand(1);
14415 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14416 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14417 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14419 Cond = ConvertCmpIfNecessary(Cond, DAG);
14420 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14421 Chain, Dest, CC, Cond);
14424 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14425 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14426 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14427 // that the guard pages used by the OS virtual memory manager are allocated in
14428 // correct sequence.
14430 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14431 SelectionDAG &DAG) const {
14432 MachineFunction &MF = DAG.getMachineFunction();
14433 bool SplitStack = MF.shouldSplitStack();
14434 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14439 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14440 SDNode* Node = Op.getNode();
14442 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14443 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14444 " not tell us which reg is the stack pointer!");
14445 EVT VT = Node->getValueType(0);
14446 SDValue Tmp1 = SDValue(Node, 0);
14447 SDValue Tmp2 = SDValue(Node, 1);
14448 SDValue Tmp3 = Node->getOperand(2);
14449 SDValue Chain = Tmp1.getOperand(0);
14451 // Chain the dynamic stack allocation so that it doesn't modify the stack
14452 // pointer when other instructions are using the stack.
14453 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14456 SDValue Size = Tmp2.getOperand(1);
14457 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14458 Chain = SP.getValue(1);
14459 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14460 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14461 unsigned StackAlign = TFI.getStackAlignment();
14462 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14463 if (Align > StackAlign)
14464 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14465 DAG.getConstant(-(uint64_t)Align, dl, VT));
14466 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14468 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14469 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14472 SDValue Ops[2] = { Tmp1, Tmp2 };
14473 return DAG.getMergeValues(Ops, dl);
14477 SDValue Chain = Op.getOperand(0);
14478 SDValue Size = Op.getOperand(1);
14479 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14480 EVT VT = Op.getNode()->getValueType(0);
14482 bool Is64Bit = Subtarget->is64Bit();
14483 EVT SPTy = getPointerTy();
14486 MachineRegisterInfo &MRI = MF.getRegInfo();
14489 // The 64 bit implementation of segmented stacks needs to clobber both r10
14490 // r11. This makes it impossible to use it along with nested parameters.
14491 const Function *F = MF.getFunction();
14493 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14495 if (I->hasNestAttr())
14496 report_fatal_error("Cannot use segmented stacks with functions that "
14497 "have nested arguments.");
14500 const TargetRegisterClass *AddrRegClass =
14501 getRegClassFor(getPointerTy());
14502 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14503 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14504 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14505 DAG.getRegister(Vreg, SPTy));
14506 SDValue Ops1[2] = { Value, Chain };
14507 return DAG.getMergeValues(Ops1, dl);
14510 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14512 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14513 Flag = Chain.getValue(1);
14514 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14516 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14518 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14519 unsigned SPReg = RegInfo->getStackRegister();
14520 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14521 Chain = SP.getValue(1);
14524 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14525 DAG.getConstant(-(uint64_t)Align, dl, VT));
14526 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14529 SDValue Ops1[2] = { SP, Chain };
14530 return DAG.getMergeValues(Ops1, dl);
14534 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14535 MachineFunction &MF = DAG.getMachineFunction();
14536 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14538 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14541 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14542 // vastart just stores the address of the VarArgsFrameIndex slot into the
14543 // memory location argument.
14544 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14546 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14547 MachinePointerInfo(SV), false, false, 0);
14551 // gp_offset (0 - 6 * 8)
14552 // fp_offset (48 - 48 + 8 * 16)
14553 // overflow_arg_area (point to parameters coming in memory).
14555 SmallVector<SDValue, 8> MemOps;
14556 SDValue FIN = Op.getOperand(1);
14558 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14559 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14561 FIN, MachinePointerInfo(SV), false, false, 0);
14562 MemOps.push_back(Store);
14565 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14566 FIN, DAG.getIntPtrConstant(4, DL));
14567 Store = DAG.getStore(Op.getOperand(0), DL,
14568 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14570 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14571 MemOps.push_back(Store);
14573 // Store ptr to overflow_arg_area
14574 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14575 FIN, DAG.getIntPtrConstant(4, DL));
14576 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14578 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14579 MachinePointerInfo(SV, 8),
14581 MemOps.push_back(Store);
14583 // Store ptr to reg_save_area.
14584 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14585 FIN, DAG.getIntPtrConstant(8, DL));
14586 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14588 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14589 MachinePointerInfo(SV, 16), false, false, 0);
14590 MemOps.push_back(Store);
14591 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14594 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14595 assert(Subtarget->is64Bit() &&
14596 "LowerVAARG only handles 64-bit va_arg!");
14597 assert((Subtarget->isTargetLinux() ||
14598 Subtarget->isTargetDarwin()) &&
14599 "Unhandled target in LowerVAARG");
14600 assert(Op.getNode()->getNumOperands() == 4);
14601 SDValue Chain = Op.getOperand(0);
14602 SDValue SrcPtr = Op.getOperand(1);
14603 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14604 unsigned Align = Op.getConstantOperandVal(3);
14607 EVT ArgVT = Op.getNode()->getValueType(0);
14608 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14609 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14612 // Decide which area this value should be read from.
14613 // TODO: Implement the AMD64 ABI in its entirety. This simple
14614 // selection mechanism works only for the basic types.
14615 if (ArgVT == MVT::f80) {
14616 llvm_unreachable("va_arg for f80 not yet implemented");
14617 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14618 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14619 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14620 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14622 llvm_unreachable("Unhandled argument type in LowerVAARG");
14625 if (ArgMode == 2) {
14626 // Sanity Check: Make sure using fp_offset makes sense.
14627 assert(!Subtarget->useSoftFloat() &&
14628 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14629 Attribute::NoImplicitFloat)) &&
14630 Subtarget->hasSSE1());
14633 // Insert VAARG_64 node into the DAG
14634 // VAARG_64 returns two values: Variable Argument Address, Chain
14635 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14636 DAG.getConstant(ArgMode, dl, MVT::i8),
14637 DAG.getConstant(Align, dl, MVT::i32)};
14638 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14639 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14640 VTs, InstOps, MVT::i64,
14641 MachinePointerInfo(SV),
14643 /*Volatile=*/false,
14645 /*WriteMem=*/true);
14646 Chain = VAARG.getValue(1);
14648 // Load the next argument and return it
14649 return DAG.getLoad(ArgVT, dl,
14652 MachinePointerInfo(),
14653 false, false, false, 0);
14656 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14657 SelectionDAG &DAG) {
14658 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14659 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14660 SDValue Chain = Op.getOperand(0);
14661 SDValue DstPtr = Op.getOperand(1);
14662 SDValue SrcPtr = Op.getOperand(2);
14663 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14664 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14667 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14668 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14670 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14673 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14674 // amount is a constant. Takes immediate version of shift as input.
14675 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14676 SDValue SrcOp, uint64_t ShiftAmt,
14677 SelectionDAG &DAG) {
14678 MVT ElementType = VT.getVectorElementType();
14680 // Fold this packed shift into its first operand if ShiftAmt is 0.
14684 // Check for ShiftAmt >= element width
14685 if (ShiftAmt >= ElementType.getSizeInBits()) {
14686 if (Opc == X86ISD::VSRAI)
14687 ShiftAmt = ElementType.getSizeInBits() - 1;
14689 return DAG.getConstant(0, dl, VT);
14692 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14693 && "Unknown target vector shift-by-constant node");
14695 // Fold this packed vector shift into a build vector if SrcOp is a
14696 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14697 if (VT == SrcOp.getSimpleValueType() &&
14698 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14699 SmallVector<SDValue, 8> Elts;
14700 unsigned NumElts = SrcOp->getNumOperands();
14701 ConstantSDNode *ND;
14704 default: llvm_unreachable(nullptr);
14705 case X86ISD::VSHLI:
14706 for (unsigned i=0; i!=NumElts; ++i) {
14707 SDValue CurrentOp = SrcOp->getOperand(i);
14708 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14709 Elts.push_back(CurrentOp);
14712 ND = cast<ConstantSDNode>(CurrentOp);
14713 const APInt &C = ND->getAPIntValue();
14714 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14717 case X86ISD::VSRLI:
14718 for (unsigned i=0; i!=NumElts; ++i) {
14719 SDValue CurrentOp = SrcOp->getOperand(i);
14720 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14721 Elts.push_back(CurrentOp);
14724 ND = cast<ConstantSDNode>(CurrentOp);
14725 const APInt &C = ND->getAPIntValue();
14726 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14729 case X86ISD::VSRAI:
14730 for (unsigned i=0; i!=NumElts; ++i) {
14731 SDValue CurrentOp = SrcOp->getOperand(i);
14732 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14733 Elts.push_back(CurrentOp);
14736 ND = cast<ConstantSDNode>(CurrentOp);
14737 const APInt &C = ND->getAPIntValue();
14738 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14743 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14746 return DAG.getNode(Opc, dl, VT, SrcOp,
14747 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14750 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14751 // may or may not be a constant. Takes immediate version of shift as input.
14752 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14753 SDValue SrcOp, SDValue ShAmt,
14754 SelectionDAG &DAG) {
14755 MVT SVT = ShAmt.getSimpleValueType();
14756 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14758 // Catch shift-by-constant.
14759 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14760 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14761 CShAmt->getZExtValue(), DAG);
14763 // Change opcode to non-immediate version
14765 default: llvm_unreachable("Unknown target vector shift node");
14766 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14767 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14768 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14771 const X86Subtarget &Subtarget =
14772 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14773 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14774 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14775 // Let the shuffle legalizer expand this shift amount node.
14776 SDValue Op0 = ShAmt.getOperand(0);
14777 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14778 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14780 // Need to build a vector containing shift amount.
14781 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14782 SmallVector<SDValue, 4> ShOps;
14783 ShOps.push_back(ShAmt);
14784 if (SVT == MVT::i32) {
14785 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14786 ShOps.push_back(DAG.getUNDEF(SVT));
14788 ShOps.push_back(DAG.getUNDEF(SVT));
14790 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14791 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14794 // The return type has to be a 128-bit type with the same element
14795 // type as the input type.
14796 MVT EltVT = VT.getVectorElementType();
14797 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14799 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14800 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14803 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14804 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14805 /// necessary casting for \p Mask when lowering masking intrinsics.
14806 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14807 SDValue PreservedSrc,
14808 const X86Subtarget *Subtarget,
14809 SelectionDAG &DAG) {
14810 EVT VT = Op.getValueType();
14811 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14812 MVT::i1, VT.getVectorNumElements());
14813 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14814 Mask.getValueType().getSizeInBits());
14817 assert(MaskVT.isSimple() && "invalid mask type");
14819 if (isAllOnes(Mask))
14822 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14823 // are extracted by EXTRACT_SUBVECTOR.
14824 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14825 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14826 DAG.getIntPtrConstant(0, dl));
14828 switch (Op.getOpcode()) {
14830 case X86ISD::PCMPEQM:
14831 case X86ISD::PCMPGTM:
14833 case X86ISD::CMPMU:
14834 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14836 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14837 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14838 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14841 /// \brief Creates an SDNode for a predicated scalar operation.
14842 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14843 /// The mask is comming as MVT::i8 and it should be truncated
14844 /// to MVT::i1 while lowering masking intrinsics.
14845 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14846 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14847 /// a scalar instruction.
14848 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14849 SDValue PreservedSrc,
14850 const X86Subtarget *Subtarget,
14851 SelectionDAG &DAG) {
14852 if (isAllOnes(Mask))
14855 EVT VT = Op.getValueType();
14857 // The mask should be of type MVT::i1
14858 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14860 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14861 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14862 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14865 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14866 SelectionDAG &DAG) {
14868 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14869 EVT VT = Op.getValueType();
14870 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14872 switch(IntrData->Type) {
14873 case INTR_TYPE_1OP:
14874 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14875 case INTR_TYPE_2OP:
14876 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14878 case INTR_TYPE_3OP:
14879 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14880 Op.getOperand(2), Op.getOperand(3));
14881 case INTR_TYPE_1OP_MASK_RM: {
14882 SDValue Src = Op.getOperand(1);
14883 SDValue Src0 = Op.getOperand(2);
14884 SDValue Mask = Op.getOperand(3);
14885 SDValue RoundingMode = Op.getOperand(4);
14886 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14888 Mask, Src0, Subtarget, DAG);
14890 case INTR_TYPE_SCALAR_MASK_RM: {
14891 SDValue Src1 = Op.getOperand(1);
14892 SDValue Src2 = Op.getOperand(2);
14893 SDValue Src0 = Op.getOperand(3);
14894 SDValue Mask = Op.getOperand(4);
14895 // There are 2 kinds of intrinsics in this group:
14896 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
14897 // (2) With rounding mode and sae - 7 operands.
14898 if (Op.getNumOperands() == 6) {
14899 SDValue Sae = Op.getOperand(5);
14900 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
14901 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
14903 Mask, Src0, Subtarget, DAG);
14905 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
14906 SDValue RoundingMode = Op.getOperand(5);
14907 SDValue Sae = Op.getOperand(6);
14908 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14909 RoundingMode, Sae),
14910 Mask, Src0, Subtarget, DAG);
14912 case INTR_TYPE_2OP_MASK: {
14913 SDValue Src1 = Op.getOperand(1);
14914 SDValue Src2 = Op.getOperand(2);
14915 SDValue PassThru = Op.getOperand(3);
14916 SDValue Mask = Op.getOperand(4);
14917 // We specify 2 possible opcodes for intrinsics with rounding modes.
14918 // First, we check if the intrinsic may have non-default rounding mode,
14919 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14920 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14921 if (IntrWithRoundingModeOpcode != 0) {
14922 SDValue Rnd = Op.getOperand(5);
14923 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14924 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14925 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14926 dl, Op.getValueType(),
14928 Mask, PassThru, Subtarget, DAG);
14931 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14933 Mask, PassThru, Subtarget, DAG);
14935 case FMA_OP_MASK: {
14936 SDValue Src1 = Op.getOperand(1);
14937 SDValue Src2 = Op.getOperand(2);
14938 SDValue Src3 = Op.getOperand(3);
14939 SDValue Mask = Op.getOperand(4);
14940 // We specify 2 possible opcodes for intrinsics with rounding modes.
14941 // First, we check if the intrinsic may have non-default rounding mode,
14942 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14943 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14944 if (IntrWithRoundingModeOpcode != 0) {
14945 SDValue Rnd = Op.getOperand(5);
14946 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14947 X86::STATIC_ROUNDING::CUR_DIRECTION)
14948 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14949 dl, Op.getValueType(),
14950 Src1, Src2, Src3, Rnd),
14951 Mask, Src1, Subtarget, DAG);
14953 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14954 dl, Op.getValueType(),
14956 Mask, Src1, Subtarget, DAG);
14959 case CMP_MASK_CC: {
14960 // Comparison intrinsics with masks.
14961 // Example of transformation:
14962 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14963 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14965 // (v8i1 (insert_subvector undef,
14966 // (v2i1 (and (PCMPEQM %a, %b),
14967 // (extract_subvector
14968 // (v8i1 (bitcast %mask)), 0))), 0))))
14969 EVT VT = Op.getOperand(1).getValueType();
14970 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14971 VT.getVectorNumElements());
14972 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14973 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14974 Mask.getValueType().getSizeInBits());
14976 if (IntrData->Type == CMP_MASK_CC) {
14977 SDValue CC = Op.getOperand(3);
14978 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
14979 // We specify 2 possible opcodes for intrinsics with rounding modes.
14980 // First, we check if the intrinsic may have non-default rounding mode,
14981 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14982 if (IntrData->Opc1 != 0) {
14983 SDValue Rnd = Op.getOperand(5);
14984 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14985 X86::STATIC_ROUNDING::CUR_DIRECTION)
14986 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
14987 Op.getOperand(2), CC, Rnd);
14989 //default rounding mode
14991 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14992 Op.getOperand(2), CC);
14995 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14996 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14999 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15000 DAG.getTargetConstant(0, dl,
15003 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15004 DAG.getUNDEF(BitcastVT), CmpMask,
15005 DAG.getIntPtrConstant(0, dl));
15006 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
15008 case COMI: { // Comparison intrinsics
15009 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15010 SDValue LHS = Op.getOperand(1);
15011 SDValue RHS = Op.getOperand(2);
15012 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15013 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15014 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15015 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15016 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15017 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15020 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15021 Op.getOperand(1), Op.getOperand(2), DAG);
15023 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15024 Op.getSimpleValueType(),
15026 Op.getOperand(2), DAG),
15027 Op.getOperand(4), Op.getOperand(3), Subtarget,
15029 case COMPRESS_EXPAND_IN_REG: {
15030 SDValue Mask = Op.getOperand(3);
15031 SDValue DataToCompress = Op.getOperand(1);
15032 SDValue PassThru = Op.getOperand(2);
15033 if (isAllOnes(Mask)) // return data as is
15034 return Op.getOperand(1);
15035 EVT VT = Op.getValueType();
15036 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15037 VT.getVectorNumElements());
15038 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15039 Mask.getValueType().getSizeInBits());
15041 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15042 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15043 DAG.getIntPtrConstant(0, dl));
15045 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15049 SDValue Mask = Op.getOperand(3);
15050 EVT VT = Op.getValueType();
15051 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15052 VT.getVectorNumElements());
15053 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15054 Mask.getValueType().getSizeInBits());
15056 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15057 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15058 DAG.getIntPtrConstant(0, dl));
15059 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15068 default: return SDValue(); // Don't custom lower most intrinsics.
15070 case Intrinsic::x86_avx2_permd:
15071 case Intrinsic::x86_avx2_permps:
15072 // Operands intentionally swapped. Mask is last operand to intrinsic,
15073 // but second operand for node/instruction.
15074 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15075 Op.getOperand(2), Op.getOperand(1));
15077 case Intrinsic::x86_avx512_mask_valign_q_512:
15078 case Intrinsic::x86_avx512_mask_valign_d_512:
15079 // Vector source operands are swapped.
15080 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15081 Op.getValueType(), Op.getOperand(2),
15084 Op.getOperand(5), Op.getOperand(4),
15087 // ptest and testp intrinsics. The intrinsic these come from are designed to
15088 // return an integer value, not just an instruction so lower it to the ptest
15089 // or testp pattern and a setcc for the result.
15090 case Intrinsic::x86_sse41_ptestz:
15091 case Intrinsic::x86_sse41_ptestc:
15092 case Intrinsic::x86_sse41_ptestnzc:
15093 case Intrinsic::x86_avx_ptestz_256:
15094 case Intrinsic::x86_avx_ptestc_256:
15095 case Intrinsic::x86_avx_ptestnzc_256:
15096 case Intrinsic::x86_avx_vtestz_ps:
15097 case Intrinsic::x86_avx_vtestc_ps:
15098 case Intrinsic::x86_avx_vtestnzc_ps:
15099 case Intrinsic::x86_avx_vtestz_pd:
15100 case Intrinsic::x86_avx_vtestc_pd:
15101 case Intrinsic::x86_avx_vtestnzc_pd:
15102 case Intrinsic::x86_avx_vtestz_ps_256:
15103 case Intrinsic::x86_avx_vtestc_ps_256:
15104 case Intrinsic::x86_avx_vtestnzc_ps_256:
15105 case Intrinsic::x86_avx_vtestz_pd_256:
15106 case Intrinsic::x86_avx_vtestc_pd_256:
15107 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15108 bool IsTestPacked = false;
15111 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15112 case Intrinsic::x86_avx_vtestz_ps:
15113 case Intrinsic::x86_avx_vtestz_pd:
15114 case Intrinsic::x86_avx_vtestz_ps_256:
15115 case Intrinsic::x86_avx_vtestz_pd_256:
15116 IsTestPacked = true; // Fallthrough
15117 case Intrinsic::x86_sse41_ptestz:
15118 case Intrinsic::x86_avx_ptestz_256:
15120 X86CC = X86::COND_E;
15122 case Intrinsic::x86_avx_vtestc_ps:
15123 case Intrinsic::x86_avx_vtestc_pd:
15124 case Intrinsic::x86_avx_vtestc_ps_256:
15125 case Intrinsic::x86_avx_vtestc_pd_256:
15126 IsTestPacked = true; // Fallthrough
15127 case Intrinsic::x86_sse41_ptestc:
15128 case Intrinsic::x86_avx_ptestc_256:
15130 X86CC = X86::COND_B;
15132 case Intrinsic::x86_avx_vtestnzc_ps:
15133 case Intrinsic::x86_avx_vtestnzc_pd:
15134 case Intrinsic::x86_avx_vtestnzc_ps_256:
15135 case Intrinsic::x86_avx_vtestnzc_pd_256:
15136 IsTestPacked = true; // Fallthrough
15137 case Intrinsic::x86_sse41_ptestnzc:
15138 case Intrinsic::x86_avx_ptestnzc_256:
15140 X86CC = X86::COND_A;
15144 SDValue LHS = Op.getOperand(1);
15145 SDValue RHS = Op.getOperand(2);
15146 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15147 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15148 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15149 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15150 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15152 case Intrinsic::x86_avx512_kortestz_w:
15153 case Intrinsic::x86_avx512_kortestc_w: {
15154 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15155 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15156 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15157 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15158 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15159 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15160 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15163 case Intrinsic::x86_sse42_pcmpistria128:
15164 case Intrinsic::x86_sse42_pcmpestria128:
15165 case Intrinsic::x86_sse42_pcmpistric128:
15166 case Intrinsic::x86_sse42_pcmpestric128:
15167 case Intrinsic::x86_sse42_pcmpistrio128:
15168 case Intrinsic::x86_sse42_pcmpestrio128:
15169 case Intrinsic::x86_sse42_pcmpistris128:
15170 case Intrinsic::x86_sse42_pcmpestris128:
15171 case Intrinsic::x86_sse42_pcmpistriz128:
15172 case Intrinsic::x86_sse42_pcmpestriz128: {
15176 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15177 case Intrinsic::x86_sse42_pcmpistria128:
15178 Opcode = X86ISD::PCMPISTRI;
15179 X86CC = X86::COND_A;
15181 case Intrinsic::x86_sse42_pcmpestria128:
15182 Opcode = X86ISD::PCMPESTRI;
15183 X86CC = X86::COND_A;
15185 case Intrinsic::x86_sse42_pcmpistric128:
15186 Opcode = X86ISD::PCMPISTRI;
15187 X86CC = X86::COND_B;
15189 case Intrinsic::x86_sse42_pcmpestric128:
15190 Opcode = X86ISD::PCMPESTRI;
15191 X86CC = X86::COND_B;
15193 case Intrinsic::x86_sse42_pcmpistrio128:
15194 Opcode = X86ISD::PCMPISTRI;
15195 X86CC = X86::COND_O;
15197 case Intrinsic::x86_sse42_pcmpestrio128:
15198 Opcode = X86ISD::PCMPESTRI;
15199 X86CC = X86::COND_O;
15201 case Intrinsic::x86_sse42_pcmpistris128:
15202 Opcode = X86ISD::PCMPISTRI;
15203 X86CC = X86::COND_S;
15205 case Intrinsic::x86_sse42_pcmpestris128:
15206 Opcode = X86ISD::PCMPESTRI;
15207 X86CC = X86::COND_S;
15209 case Intrinsic::x86_sse42_pcmpistriz128:
15210 Opcode = X86ISD::PCMPISTRI;
15211 X86CC = X86::COND_E;
15213 case Intrinsic::x86_sse42_pcmpestriz128:
15214 Opcode = X86ISD::PCMPESTRI;
15215 X86CC = X86::COND_E;
15218 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15219 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15220 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15221 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15222 DAG.getConstant(X86CC, dl, MVT::i8),
15223 SDValue(PCMP.getNode(), 1));
15224 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15227 case Intrinsic::x86_sse42_pcmpistri128:
15228 case Intrinsic::x86_sse42_pcmpestri128: {
15230 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15231 Opcode = X86ISD::PCMPISTRI;
15233 Opcode = X86ISD::PCMPESTRI;
15235 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15236 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15237 return DAG.getNode(Opcode, dl, VTs, NewOps);
15242 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15243 SDValue Src, SDValue Mask, SDValue Base,
15244 SDValue Index, SDValue ScaleOp, SDValue Chain,
15245 const X86Subtarget * Subtarget) {
15247 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15248 assert(C && "Invalid scale type");
15249 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15250 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15251 Index.getSimpleValueType().getVectorNumElements());
15253 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15255 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15257 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15258 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15259 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15260 SDValue Segment = DAG.getRegister(0, MVT::i32);
15261 if (Src.getOpcode() == ISD::UNDEF)
15262 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15263 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15264 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15265 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15266 return DAG.getMergeValues(RetOps, dl);
15269 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15270 SDValue Src, SDValue Mask, SDValue Base,
15271 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15273 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15274 assert(C && "Invalid scale type");
15275 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15276 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15277 SDValue Segment = DAG.getRegister(0, MVT::i32);
15278 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15279 Index.getSimpleValueType().getVectorNumElements());
15281 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15283 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15285 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15286 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15287 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15288 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15289 return SDValue(Res, 1);
15292 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15293 SDValue Mask, SDValue Base, SDValue Index,
15294 SDValue ScaleOp, SDValue Chain) {
15296 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15297 assert(C && "Invalid scale type");
15298 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15299 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15300 SDValue Segment = DAG.getRegister(0, MVT::i32);
15302 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15304 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15306 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15308 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15309 //SDVTList VTs = DAG.getVTList(MVT::Other);
15310 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15311 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15312 return SDValue(Res, 0);
15315 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15316 // read performance monitor counters (x86_rdpmc).
15317 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15318 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15319 SmallVectorImpl<SDValue> &Results) {
15320 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15321 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15324 // The ECX register is used to select the index of the performance counter
15326 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15328 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15330 // Reads the content of a 64-bit performance counter and returns it in the
15331 // registers EDX:EAX.
15332 if (Subtarget->is64Bit()) {
15333 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15334 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15337 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15338 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15341 Chain = HI.getValue(1);
15343 if (Subtarget->is64Bit()) {
15344 // The EAX register is loaded with the low-order 32 bits. The EDX register
15345 // is loaded with the supported high-order bits of the counter.
15346 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15347 DAG.getConstant(32, DL, MVT::i8));
15348 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15349 Results.push_back(Chain);
15353 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15354 SDValue Ops[] = { LO, HI };
15355 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15356 Results.push_back(Pair);
15357 Results.push_back(Chain);
15360 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15361 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15362 // also used to custom lower READCYCLECOUNTER nodes.
15363 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15364 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15365 SmallVectorImpl<SDValue> &Results) {
15366 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15367 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15370 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15371 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15372 // and the EAX register is loaded with the low-order 32 bits.
15373 if (Subtarget->is64Bit()) {
15374 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15375 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15378 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15379 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15382 SDValue Chain = HI.getValue(1);
15384 if (Opcode == X86ISD::RDTSCP_DAG) {
15385 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15387 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15388 // the ECX register. Add 'ecx' explicitly to the chain.
15389 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15391 // Explicitly store the content of ECX at the location passed in input
15392 // to the 'rdtscp' intrinsic.
15393 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15394 MachinePointerInfo(), false, false, 0);
15397 if (Subtarget->is64Bit()) {
15398 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15399 // the EAX register is loaded with the low-order 32 bits.
15400 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15401 DAG.getConstant(32, DL, MVT::i8));
15402 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15403 Results.push_back(Chain);
15407 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15408 SDValue Ops[] = { LO, HI };
15409 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15410 Results.push_back(Pair);
15411 Results.push_back(Chain);
15414 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15415 SelectionDAG &DAG) {
15416 SmallVector<SDValue, 2> Results;
15418 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15420 return DAG.getMergeValues(Results, DL);
15424 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15425 SelectionDAG &DAG) {
15426 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15428 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15433 switch(IntrData->Type) {
15435 llvm_unreachable("Unknown Intrinsic Type");
15439 // Emit the node with the right value type.
15440 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15441 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15443 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15444 // Otherwise return the value from Rand, which is always 0, casted to i32.
15445 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15446 DAG.getConstant(1, dl, Op->getValueType(1)),
15447 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15448 SDValue(Result.getNode(), 1) };
15449 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15450 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15453 // Return { result, isValid, chain }.
15454 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15455 SDValue(Result.getNode(), 2));
15458 //gather(v1, mask, index, base, scale);
15459 SDValue Chain = Op.getOperand(0);
15460 SDValue Src = Op.getOperand(2);
15461 SDValue Base = Op.getOperand(3);
15462 SDValue Index = Op.getOperand(4);
15463 SDValue Mask = Op.getOperand(5);
15464 SDValue Scale = Op.getOperand(6);
15465 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15469 //scatter(base, mask, index, v1, scale);
15470 SDValue Chain = Op.getOperand(0);
15471 SDValue Base = Op.getOperand(2);
15472 SDValue Mask = Op.getOperand(3);
15473 SDValue Index = Op.getOperand(4);
15474 SDValue Src = Op.getOperand(5);
15475 SDValue Scale = Op.getOperand(6);
15476 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15480 SDValue Hint = Op.getOperand(6);
15481 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15482 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15483 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15484 SDValue Chain = Op.getOperand(0);
15485 SDValue Mask = Op.getOperand(2);
15486 SDValue Index = Op.getOperand(3);
15487 SDValue Base = Op.getOperand(4);
15488 SDValue Scale = Op.getOperand(5);
15489 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15491 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15493 SmallVector<SDValue, 2> Results;
15494 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15496 return DAG.getMergeValues(Results, dl);
15498 // Read Performance Monitoring Counters.
15500 SmallVector<SDValue, 2> Results;
15501 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15502 return DAG.getMergeValues(Results, dl);
15504 // XTEST intrinsics.
15506 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15507 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15508 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15509 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15511 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15512 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15513 Ret, SDValue(InTrans.getNode(), 1));
15517 SmallVector<SDValue, 2> Results;
15518 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15519 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15520 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15521 DAG.getConstant(-1, dl, MVT::i8));
15522 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15523 Op.getOperand(4), GenCF.getValue(1));
15524 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15525 Op.getOperand(5), MachinePointerInfo(),
15527 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15528 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15530 Results.push_back(SetCC);
15531 Results.push_back(Store);
15532 return DAG.getMergeValues(Results, dl);
15534 case COMPRESS_TO_MEM: {
15536 SDValue Mask = Op.getOperand(4);
15537 SDValue DataToCompress = Op.getOperand(3);
15538 SDValue Addr = Op.getOperand(2);
15539 SDValue Chain = Op.getOperand(0);
15541 if (isAllOnes(Mask)) // return just a store
15542 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15543 MachinePointerInfo(), false, false, 0);
15545 EVT VT = DataToCompress.getValueType();
15546 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15547 VT.getVectorNumElements());
15548 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15549 Mask.getValueType().getSizeInBits());
15550 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15551 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15552 DAG.getIntPtrConstant(0, dl));
15554 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15555 DataToCompress, DAG.getUNDEF(VT));
15556 return DAG.getStore(Chain, dl, Compressed, Addr,
15557 MachinePointerInfo(), false, false, 0);
15559 case EXPAND_FROM_MEM: {
15561 SDValue Mask = Op.getOperand(4);
15562 SDValue PathThru = Op.getOperand(3);
15563 SDValue Addr = Op.getOperand(2);
15564 SDValue Chain = Op.getOperand(0);
15565 EVT VT = Op.getValueType();
15567 if (isAllOnes(Mask)) // return just a load
15568 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15570 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15571 VT.getVectorNumElements());
15572 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15573 Mask.getValueType().getSizeInBits());
15574 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15575 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15576 DAG.getIntPtrConstant(0, dl));
15578 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15579 false, false, false, 0);
15581 SDValue Results[] = {
15582 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15584 return DAG.getMergeValues(Results, dl);
15589 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15590 SelectionDAG &DAG) const {
15591 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15592 MFI->setReturnAddressIsTaken(true);
15594 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15597 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15599 EVT PtrVT = getPointerTy();
15602 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15603 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15604 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15605 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15606 DAG.getNode(ISD::ADD, dl, PtrVT,
15607 FrameAddr, Offset),
15608 MachinePointerInfo(), false, false, false, 0);
15611 // Just load the return address.
15612 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15613 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15614 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15617 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15618 MachineFunction &MF = DAG.getMachineFunction();
15619 MachineFrameInfo *MFI = MF.getFrameInfo();
15620 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15621 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15622 EVT VT = Op.getValueType();
15624 MFI->setFrameAddressIsTaken(true);
15626 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15627 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15628 // is not possible to crawl up the stack without looking at the unwind codes
15630 int FrameAddrIndex = FuncInfo->getFAIndex();
15631 if (!FrameAddrIndex) {
15632 // Set up a frame object for the return address.
15633 unsigned SlotSize = RegInfo->getSlotSize();
15634 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15635 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15636 FuncInfo->setFAIndex(FrameAddrIndex);
15638 return DAG.getFrameIndex(FrameAddrIndex, VT);
15641 unsigned FrameReg =
15642 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15643 SDLoc dl(Op); // FIXME probably not meaningful
15644 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15645 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15646 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15647 "Invalid Frame Register!");
15648 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15650 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15651 MachinePointerInfo(),
15652 false, false, false, 0);
15656 // FIXME? Maybe this could be a TableGen attribute on some registers and
15657 // this table could be generated automatically from RegInfo.
15658 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15660 unsigned Reg = StringSwitch<unsigned>(RegName)
15661 .Case("esp", X86::ESP)
15662 .Case("rsp", X86::RSP)
15666 report_fatal_error("Invalid register name global variable");
15669 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15670 SelectionDAG &DAG) const {
15671 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15672 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15675 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15676 SDValue Chain = Op.getOperand(0);
15677 SDValue Offset = Op.getOperand(1);
15678 SDValue Handler = Op.getOperand(2);
15681 EVT PtrVT = getPointerTy();
15682 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15683 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15684 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15685 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15686 "Invalid Frame Register!");
15687 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15688 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15690 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15691 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15693 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15694 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15696 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15698 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15699 DAG.getRegister(StoreAddrReg, PtrVT));
15702 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15703 SelectionDAG &DAG) const {
15705 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15706 DAG.getVTList(MVT::i32, MVT::Other),
15707 Op.getOperand(0), Op.getOperand(1));
15710 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15711 SelectionDAG &DAG) const {
15713 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15714 Op.getOperand(0), Op.getOperand(1));
15717 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15718 return Op.getOperand(0);
15721 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15722 SelectionDAG &DAG) const {
15723 SDValue Root = Op.getOperand(0);
15724 SDValue Trmp = Op.getOperand(1); // trampoline
15725 SDValue FPtr = Op.getOperand(2); // nested function
15726 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15729 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15730 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15732 if (Subtarget->is64Bit()) {
15733 SDValue OutChains[6];
15735 // Large code-model.
15736 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15737 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15739 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15740 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15742 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15744 // Load the pointer to the nested function into R11.
15745 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15746 SDValue Addr = Trmp;
15747 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15748 Addr, MachinePointerInfo(TrmpAddr),
15751 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15752 DAG.getConstant(2, dl, MVT::i64));
15753 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15754 MachinePointerInfo(TrmpAddr, 2),
15757 // Load the 'nest' parameter value into R10.
15758 // R10 is specified in X86CallingConv.td
15759 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15760 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15761 DAG.getConstant(10, dl, MVT::i64));
15762 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15763 Addr, MachinePointerInfo(TrmpAddr, 10),
15766 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15767 DAG.getConstant(12, dl, MVT::i64));
15768 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15769 MachinePointerInfo(TrmpAddr, 12),
15772 // Jump to the nested function.
15773 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15774 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15775 DAG.getConstant(20, dl, MVT::i64));
15776 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15777 Addr, MachinePointerInfo(TrmpAddr, 20),
15780 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15781 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15782 DAG.getConstant(22, dl, MVT::i64));
15783 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
15784 Addr, MachinePointerInfo(TrmpAddr, 22),
15787 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15789 const Function *Func =
15790 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15791 CallingConv::ID CC = Func->getCallingConv();
15796 llvm_unreachable("Unsupported calling convention");
15797 case CallingConv::C:
15798 case CallingConv::X86_StdCall: {
15799 // Pass 'nest' parameter in ECX.
15800 // Must be kept in sync with X86CallingConv.td
15801 NestReg = X86::ECX;
15803 // Check that ECX wasn't needed by an 'inreg' parameter.
15804 FunctionType *FTy = Func->getFunctionType();
15805 const AttributeSet &Attrs = Func->getAttributes();
15807 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15808 unsigned InRegCount = 0;
15811 for (FunctionType::param_iterator I = FTy->param_begin(),
15812 E = FTy->param_end(); I != E; ++I, ++Idx)
15813 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15814 // FIXME: should only count parameters that are lowered to integers.
15815 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15817 if (InRegCount > 2) {
15818 report_fatal_error("Nest register in use - reduce number of inreg"
15824 case CallingConv::X86_FastCall:
15825 case CallingConv::X86_ThisCall:
15826 case CallingConv::Fast:
15827 // Pass 'nest' parameter in EAX.
15828 // Must be kept in sync with X86CallingConv.td
15829 NestReg = X86::EAX;
15833 SDValue OutChains[4];
15834 SDValue Addr, Disp;
15836 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15837 DAG.getConstant(10, dl, MVT::i32));
15838 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15840 // This is storing the opcode for MOV32ri.
15841 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15842 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15843 OutChains[0] = DAG.getStore(Root, dl,
15844 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
15845 Trmp, MachinePointerInfo(TrmpAddr),
15848 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15849 DAG.getConstant(1, dl, MVT::i32));
15850 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15851 MachinePointerInfo(TrmpAddr, 1),
15854 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15855 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15856 DAG.getConstant(5, dl, MVT::i32));
15857 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
15858 Addr, MachinePointerInfo(TrmpAddr, 5),
15861 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15862 DAG.getConstant(6, dl, MVT::i32));
15863 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15864 MachinePointerInfo(TrmpAddr, 6),
15867 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15871 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15872 SelectionDAG &DAG) const {
15874 The rounding mode is in bits 11:10 of FPSR, and has the following
15876 00 Round to nearest
15881 FLT_ROUNDS, on the other hand, expects the following:
15888 To perform the conversion, we do:
15889 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15892 MachineFunction &MF = DAG.getMachineFunction();
15893 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15894 unsigned StackAlignment = TFI.getStackAlignment();
15895 MVT VT = Op.getSimpleValueType();
15898 // Save FP Control Word to stack slot
15899 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15900 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15902 MachineMemOperand *MMO =
15903 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15904 MachineMemOperand::MOStore, 2, 2);
15906 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15907 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15908 DAG.getVTList(MVT::Other),
15909 Ops, MVT::i16, MMO);
15911 // Load FP Control Word from stack slot
15912 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15913 MachinePointerInfo(), false, false, false, 0);
15915 // Transform as necessary
15917 DAG.getNode(ISD::SRL, DL, MVT::i16,
15918 DAG.getNode(ISD::AND, DL, MVT::i16,
15919 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
15920 DAG.getConstant(11, DL, MVT::i8));
15922 DAG.getNode(ISD::SRL, DL, MVT::i16,
15923 DAG.getNode(ISD::AND, DL, MVT::i16,
15924 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
15925 DAG.getConstant(9, DL, MVT::i8));
15928 DAG.getNode(ISD::AND, DL, MVT::i16,
15929 DAG.getNode(ISD::ADD, DL, MVT::i16,
15930 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15931 DAG.getConstant(1, DL, MVT::i16)),
15932 DAG.getConstant(3, DL, MVT::i16));
15934 return DAG.getNode((VT.getSizeInBits() < 16 ?
15935 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15938 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15939 MVT VT = Op.getSimpleValueType();
15941 unsigned NumBits = VT.getSizeInBits();
15944 Op = Op.getOperand(0);
15945 if (VT == MVT::i8) {
15946 // Zero extend to i32 since there is not an i8 bsr.
15948 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15951 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15952 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15953 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15955 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15958 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
15959 DAG.getConstant(X86::COND_E, dl, MVT::i8),
15962 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15964 // Finally xor with NumBits-1.
15965 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
15966 DAG.getConstant(NumBits - 1, dl, OpVT));
15969 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15973 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15974 MVT VT = Op.getSimpleValueType();
15976 unsigned NumBits = VT.getSizeInBits();
15979 Op = Op.getOperand(0);
15980 if (VT == MVT::i8) {
15981 // Zero extend to i32 since there is not an i8 bsr.
15983 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15986 // Issue a bsr (scan bits in reverse).
15987 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15988 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15990 // And xor with NumBits-1.
15991 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
15992 DAG.getConstant(NumBits - 1, dl, OpVT));
15995 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15999 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16000 MVT VT = Op.getSimpleValueType();
16001 unsigned NumBits = VT.getSizeInBits();
16003 Op = Op.getOperand(0);
16005 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16006 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16007 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16009 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16012 DAG.getConstant(NumBits, dl, VT),
16013 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16016 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16019 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16020 // ones, and then concatenate the result back.
16021 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16022 MVT VT = Op.getSimpleValueType();
16024 assert(VT.is256BitVector() && VT.isInteger() &&
16025 "Unsupported value type for operation");
16027 unsigned NumElems = VT.getVectorNumElements();
16030 // Extract the LHS vectors
16031 SDValue LHS = Op.getOperand(0);
16032 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16033 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16035 // Extract the RHS vectors
16036 SDValue RHS = Op.getOperand(1);
16037 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16038 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16040 MVT EltVT = VT.getVectorElementType();
16041 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16043 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16044 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16045 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16048 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16049 assert(Op.getSimpleValueType().is256BitVector() &&
16050 Op.getSimpleValueType().isInteger() &&
16051 "Only handle AVX 256-bit vector integer operation");
16052 return Lower256IntArith(Op, DAG);
16055 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16056 assert(Op.getSimpleValueType().is256BitVector() &&
16057 Op.getSimpleValueType().isInteger() &&
16058 "Only handle AVX 256-bit vector integer operation");
16059 return Lower256IntArith(Op, DAG);
16062 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16063 SelectionDAG &DAG) {
16065 MVT VT = Op.getSimpleValueType();
16067 // Decompose 256-bit ops into smaller 128-bit ops.
16068 if (VT.is256BitVector() && !Subtarget->hasInt256())
16069 return Lower256IntArith(Op, DAG);
16071 SDValue A = Op.getOperand(0);
16072 SDValue B = Op.getOperand(1);
16074 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16075 // pairs, multiply and truncate.
16076 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16077 if (Subtarget->hasInt256()) {
16078 if (VT == MVT::v32i8) {
16079 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16080 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16081 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16082 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16083 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16084 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16085 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16086 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16087 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16088 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16091 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16092 return DAG.getNode(
16093 ISD::TRUNCATE, dl, VT,
16094 DAG.getNode(ISD::MUL, dl, ExVT,
16095 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16096 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16099 assert(VT == MVT::v16i8 &&
16100 "Pre-AVX2 support only supports v16i8 multiplication");
16101 MVT ExVT = MVT::v8i16;
16103 // Extract the lo parts and sign extend to i16
16105 if (Subtarget->hasSSE41()) {
16106 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16107 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16109 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16110 -1, 4, -1, 5, -1, 6, -1, 7};
16111 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16112 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16113 ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);
16114 BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);
16115 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16116 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16119 // Extract the hi parts and sign extend to i16
16121 if (Subtarget->hasSSE41()) {
16122 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16123 -1, -1, -1, -1, -1, -1, -1, -1};
16124 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16125 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16126 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16127 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16129 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16130 -1, 12, -1, 13, -1, 14, -1, 15};
16131 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16132 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16133 AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);
16134 BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);
16135 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16136 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16139 // Multiply, mask the lower 8bits of the lo/hi results and pack
16140 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16141 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16142 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16143 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16144 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16147 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16148 if (VT == MVT::v4i32) {
16149 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16150 "Should not custom lower when pmuldq is available!");
16152 // Extract the odd parts.
16153 static const int UnpackMask[] = { 1, -1, 3, -1 };
16154 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16155 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16157 // Multiply the even parts.
16158 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16159 // Now multiply odd parts.
16160 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16162 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16163 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16165 // Merge the two vectors back together with a shuffle. This expands into 2
16167 static const int ShufMask[] = { 0, 4, 2, 6 };
16168 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16171 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16172 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16174 // Ahi = psrlqi(a, 32);
16175 // Bhi = psrlqi(b, 32);
16177 // AloBlo = pmuludq(a, b);
16178 // AloBhi = pmuludq(a, Bhi);
16179 // AhiBlo = pmuludq(Ahi, b);
16181 // AloBhi = psllqi(AloBhi, 32);
16182 // AhiBlo = psllqi(AhiBlo, 32);
16183 // return AloBlo + AloBhi + AhiBlo;
16185 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16186 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16188 // Bit cast to 32-bit vectors for MULUDQ
16189 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16190 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16191 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16192 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16193 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16194 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16196 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16197 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16198 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16200 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16201 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16203 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16204 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16207 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16208 assert(Subtarget->isTargetWin64() && "Unexpected target");
16209 EVT VT = Op.getValueType();
16210 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16211 "Unexpected return type for lowering");
16215 switch (Op->getOpcode()) {
16216 default: llvm_unreachable("Unexpected request for libcall!");
16217 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16218 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16219 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16220 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16221 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16222 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16226 SDValue InChain = DAG.getEntryNode();
16228 TargetLowering::ArgListTy Args;
16229 TargetLowering::ArgListEntry Entry;
16230 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16231 EVT ArgVT = Op->getOperand(i).getValueType();
16232 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16233 "Unexpected argument type for lowering");
16234 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16235 Entry.Node = StackPtr;
16236 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16238 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16239 Entry.Ty = PointerType::get(ArgTy,0);
16240 Entry.isSExt = false;
16241 Entry.isZExt = false;
16242 Args.push_back(Entry);
16245 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16248 TargetLowering::CallLoweringInfo CLI(DAG);
16249 CLI.setDebugLoc(dl).setChain(InChain)
16250 .setCallee(getLibcallCallingConv(LC),
16251 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16252 Callee, std::move(Args), 0)
16253 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16255 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16256 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16259 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16260 SelectionDAG &DAG) {
16261 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16262 EVT VT = Op0.getValueType();
16265 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16266 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16268 // PMULxD operations multiply each even value (starting at 0) of LHS with
16269 // the related value of RHS and produce a widen result.
16270 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16271 // => <2 x i64> <ae|cg>
16273 // In other word, to have all the results, we need to perform two PMULxD:
16274 // 1. one with the even values.
16275 // 2. one with the odd values.
16276 // To achieve #2, with need to place the odd values at an even position.
16278 // Place the odd value at an even position (basically, shift all values 1
16279 // step to the left):
16280 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16281 // <a|b|c|d> => <b|undef|d|undef>
16282 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16283 // <e|f|g|h> => <f|undef|h|undef>
16284 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16286 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16288 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16289 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16291 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16292 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16293 // => <2 x i64> <ae|cg>
16294 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16295 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16296 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16297 // => <2 x i64> <bf|dh>
16298 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16299 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16301 // Shuffle it back into the right order.
16302 SDValue Highs, Lows;
16303 if (VT == MVT::v8i32) {
16304 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16305 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16306 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16307 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16309 const int HighMask[] = {1, 5, 3, 7};
16310 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16311 const int LowMask[] = {0, 4, 2, 6};
16312 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16315 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16316 // unsigned multiply.
16317 if (IsSigned && !Subtarget->hasSSE41()) {
16319 DAG.getConstant(31, dl,
16320 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16321 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16322 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16323 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16324 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16326 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16327 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16330 // The first result of MUL_LOHI is actually the low value, followed by the
16332 SDValue Ops[] = {Lows, Highs};
16333 return DAG.getMergeValues(Ops, dl);
16336 // Return true if the requred (according to Opcode) shift-imm form is natively
16337 // supported by the Subtarget
16338 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16340 if (VT.getScalarSizeInBits() < 16)
16343 if (VT.is512BitVector() &&
16344 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16347 bool LShift = VT.is128BitVector() ||
16348 (VT.is256BitVector() && Subtarget->hasInt256());
16350 bool AShift = LShift && (Subtarget->hasVLX() ||
16351 (VT != MVT::v2i64 && VT != MVT::v4i64));
16352 return (Opcode == ISD::SRA) ? AShift : LShift;
16355 // The shift amount is a variable, but it is the same for all vector lanes.
16356 // These instrcutions are defined together with shift-immediate.
16358 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16360 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16363 // Return true if the requred (according to Opcode) variable-shift form is
16364 // natively supported by the Subtarget
16365 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16368 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16371 // vXi16 supported only on AVX-512, BWI
16372 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16375 if (VT.is512BitVector() || Subtarget->hasVLX())
16378 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16379 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16380 return (Opcode == ISD::SRA) ? AShift : LShift;
16383 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16384 const X86Subtarget *Subtarget) {
16385 MVT VT = Op.getSimpleValueType();
16387 SDValue R = Op.getOperand(0);
16388 SDValue Amt = Op.getOperand(1);
16390 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16391 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16393 // Optimize shl/srl/sra with constant shift amount.
16394 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16395 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16396 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16398 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16399 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16401 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16402 unsigned NumElts = VT.getVectorNumElements();
16403 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16405 if (Op.getOpcode() == ISD::SHL) {
16406 // Make a large shift.
16407 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16409 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16410 // Zero out the rightmost bits.
16411 SmallVector<SDValue, 32> V(
16412 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16413 return DAG.getNode(ISD::AND, dl, VT, SHL,
16414 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16416 if (Op.getOpcode() == ISD::SRL) {
16417 // Make a large shift.
16418 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16420 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16421 // Zero out the leftmost bits.
16422 SmallVector<SDValue, 32> V(
16423 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16424 return DAG.getNode(ISD::AND, dl, VT, SRL,
16425 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16427 if (Op.getOpcode() == ISD::SRA) {
16428 if (ShiftAmt == 7) {
16429 // R s>> 7 === R s< 0
16430 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16431 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16434 // R s>> a === ((R u>> a) ^ m) - m
16435 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16436 SmallVector<SDValue, 32> V(NumElts,
16437 DAG.getConstant(128 >> ShiftAmt, dl,
16439 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16440 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16441 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16444 llvm_unreachable("Unknown shift opcode.");
16449 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16450 if (!Subtarget->is64Bit() &&
16451 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16452 Amt.getOpcode() == ISD::BITCAST &&
16453 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16454 Amt = Amt.getOperand(0);
16455 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16456 VT.getVectorNumElements();
16457 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16458 uint64_t ShiftAmt = 0;
16459 for (unsigned i = 0; i != Ratio; ++i) {
16460 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16464 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16466 // Check remaining shift amounts.
16467 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16468 uint64_t ShAmt = 0;
16469 for (unsigned j = 0; j != Ratio; ++j) {
16470 ConstantSDNode *C =
16471 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16475 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16477 if (ShAmt != ShiftAmt)
16480 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16486 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16487 const X86Subtarget* Subtarget) {
16488 MVT VT = Op.getSimpleValueType();
16490 SDValue R = Op.getOperand(0);
16491 SDValue Amt = Op.getOperand(1);
16493 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16494 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16496 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16497 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16499 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16501 EVT EltVT = VT.getVectorElementType();
16503 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16504 // Check if this build_vector node is doing a splat.
16505 // If so, then set BaseShAmt equal to the splat value.
16506 BaseShAmt = BV->getSplatValue();
16507 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16508 BaseShAmt = SDValue();
16510 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16511 Amt = Amt.getOperand(0);
16513 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16514 if (SVN && SVN->isSplat()) {
16515 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16516 SDValue InVec = Amt.getOperand(0);
16517 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16518 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16519 "Unexpected shuffle index found!");
16520 BaseShAmt = InVec.getOperand(SplatIdx);
16521 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16522 if (ConstantSDNode *C =
16523 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16524 if (C->getZExtValue() == SplatIdx)
16525 BaseShAmt = InVec.getOperand(1);
16530 // Avoid introducing an extract element from a shuffle.
16531 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16532 DAG.getIntPtrConstant(SplatIdx, dl));
16536 if (BaseShAmt.getNode()) {
16537 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16538 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16539 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16540 else if (EltVT.bitsLT(MVT::i32))
16541 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16543 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16547 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16548 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16549 Amt.getOpcode() == ISD::BITCAST &&
16550 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16551 Amt = Amt.getOperand(0);
16552 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16553 VT.getVectorNumElements();
16554 std::vector<SDValue> Vals(Ratio);
16555 for (unsigned i = 0; i != Ratio; ++i)
16556 Vals[i] = Amt.getOperand(i);
16557 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16558 for (unsigned j = 0; j != Ratio; ++j)
16559 if (Vals[j] != Amt.getOperand(i + j))
16562 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16567 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16568 SelectionDAG &DAG) {
16569 MVT VT = Op.getSimpleValueType();
16571 SDValue R = Op.getOperand(0);
16572 SDValue Amt = Op.getOperand(1);
16574 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16575 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16577 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16580 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16583 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16586 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16587 // shifts per-lane and then shuffle the partial results back together.
16588 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16589 // Splat the shift amounts so the scalar shifts above will catch it.
16590 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16591 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16592 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16593 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16594 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16597 // If possible, lower this packed shift into a vector multiply instead of
16598 // expanding it into a sequence of scalar shifts.
16599 // Do this only if the vector shift count is a constant build_vector.
16600 if (Op.getOpcode() == ISD::SHL &&
16601 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16602 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16603 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16604 SmallVector<SDValue, 8> Elts;
16605 EVT SVT = VT.getScalarType();
16606 unsigned SVTBits = SVT.getSizeInBits();
16607 const APInt &One = APInt(SVTBits, 1);
16608 unsigned NumElems = VT.getVectorNumElements();
16610 for (unsigned i=0; i !=NumElems; ++i) {
16611 SDValue Op = Amt->getOperand(i);
16612 if (Op->getOpcode() == ISD::UNDEF) {
16613 Elts.push_back(Op);
16617 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16618 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16619 uint64_t ShAmt = C.getZExtValue();
16620 if (ShAmt >= SVTBits) {
16621 Elts.push_back(DAG.getUNDEF(SVT));
16624 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16626 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16627 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16630 // Lower SHL with variable shift amount.
16631 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16632 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16634 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16635 DAG.getConstant(0x3f800000U, dl, VT));
16636 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16637 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16638 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16641 // If possible, lower this shift as a sequence of two shifts by
16642 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16644 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16646 // Could be rewritten as:
16647 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16649 // The advantage is that the two shifts from the example would be
16650 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16651 // the vector shift into four scalar shifts plus four pairs of vector
16653 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16654 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16655 unsigned TargetOpcode = X86ISD::MOVSS;
16656 bool CanBeSimplified;
16657 // The splat value for the first packed shift (the 'X' from the example).
16658 SDValue Amt1 = Amt->getOperand(0);
16659 // The splat value for the second packed shift (the 'Y' from the example).
16660 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16661 Amt->getOperand(2);
16663 // See if it is possible to replace this node with a sequence of
16664 // two shifts followed by a MOVSS/MOVSD
16665 if (VT == MVT::v4i32) {
16666 // Check if it is legal to use a MOVSS.
16667 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16668 Amt2 == Amt->getOperand(3);
16669 if (!CanBeSimplified) {
16670 // Otherwise, check if we can still simplify this node using a MOVSD.
16671 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16672 Amt->getOperand(2) == Amt->getOperand(3);
16673 TargetOpcode = X86ISD::MOVSD;
16674 Amt2 = Amt->getOperand(2);
16677 // Do similar checks for the case where the machine value type
16679 CanBeSimplified = Amt1 == Amt->getOperand(1);
16680 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16681 CanBeSimplified = Amt2 == Amt->getOperand(i);
16683 if (!CanBeSimplified) {
16684 TargetOpcode = X86ISD::MOVSD;
16685 CanBeSimplified = true;
16686 Amt2 = Amt->getOperand(4);
16687 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16688 CanBeSimplified = Amt1 == Amt->getOperand(i);
16689 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16690 CanBeSimplified = Amt2 == Amt->getOperand(j);
16694 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16695 isa<ConstantSDNode>(Amt2)) {
16696 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16697 EVT CastVT = MVT::v4i32;
16699 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16700 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16702 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16703 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16704 if (TargetOpcode == X86ISD::MOVSD)
16705 CastVT = MVT::v2i64;
16706 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16707 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16708 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16710 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16714 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16715 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
16716 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
16718 SDValue VSelM = DAG.getConstant(0x80, dl, VT);
16719 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16720 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16722 // r = VSELECT(r, shl(r, 4), a);
16723 SDValue M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(4, dl, VT));
16724 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16727 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16728 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16729 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16731 // r = VSELECT(r, shl(r, 2), a);
16732 M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(2, dl, VT));
16733 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16736 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16737 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16738 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16740 // return VSELECT(r, r+r, a);
16741 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16742 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16746 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16747 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16748 // solution better.
16749 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16750 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16752 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16753 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16754 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16755 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16756 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16759 // Decompose 256-bit shifts into smaller 128-bit shifts.
16760 if (VT.is256BitVector()) {
16761 unsigned NumElems = VT.getVectorNumElements();
16762 MVT EltVT = VT.getVectorElementType();
16763 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16765 // Extract the two vectors
16766 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16767 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16769 // Recreate the shift amount vectors
16770 SDValue Amt1, Amt2;
16771 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16772 // Constant shift amount
16773 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16774 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16775 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16777 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16778 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16780 // Variable shift amount
16781 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16782 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16785 // Issue new vector shifts for the smaller types
16786 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16787 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16789 // Concatenate the result back
16790 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16796 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16797 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16798 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16799 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16800 // has only one use.
16801 SDNode *N = Op.getNode();
16802 SDValue LHS = N->getOperand(0);
16803 SDValue RHS = N->getOperand(1);
16804 unsigned BaseOp = 0;
16807 switch (Op.getOpcode()) {
16808 default: llvm_unreachable("Unknown ovf instruction!");
16810 // A subtract of one will be selected as a INC. Note that INC doesn't
16811 // set CF, so we can't do this for UADDO.
16812 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16814 BaseOp = X86ISD::INC;
16815 Cond = X86::COND_O;
16818 BaseOp = X86ISD::ADD;
16819 Cond = X86::COND_O;
16822 BaseOp = X86ISD::ADD;
16823 Cond = X86::COND_B;
16826 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16827 // set CF, so we can't do this for USUBO.
16828 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16830 BaseOp = X86ISD::DEC;
16831 Cond = X86::COND_O;
16834 BaseOp = X86ISD::SUB;
16835 Cond = X86::COND_O;
16838 BaseOp = X86ISD::SUB;
16839 Cond = X86::COND_B;
16842 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16843 Cond = X86::COND_O;
16845 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16846 if (N->getValueType(0) == MVT::i8) {
16847 BaseOp = X86ISD::UMUL8;
16848 Cond = X86::COND_O;
16851 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16853 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16856 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16857 DAG.getConstant(X86::COND_O, DL, MVT::i32),
16858 SDValue(Sum.getNode(), 2));
16860 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16864 // Also sets EFLAGS.
16865 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16866 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16869 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16870 DAG.getConstant(Cond, DL, MVT::i32),
16871 SDValue(Sum.getNode(), 1));
16873 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16876 /// Returns true if the operand type is exactly twice the native width, and
16877 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16878 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16879 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16880 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16881 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16884 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16885 else if (OpWidth == 128)
16886 return Subtarget->hasCmpxchg16b();
16891 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16892 return needsCmpXchgNb(SI->getValueOperand()->getType());
16895 // Note: this turns large loads into lock cmpxchg8b/16b.
16896 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16897 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16898 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16899 return needsCmpXchgNb(PTy->getElementType());
16902 TargetLoweringBase::AtomicRMWExpansionKind
16903 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16904 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16905 const Type *MemType = AI->getType();
16907 // If the operand is too big, we must see if cmpxchg8/16b is available
16908 // and default to library calls otherwise.
16909 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
16910 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
16911 : AtomicRMWExpansionKind::None;
16914 AtomicRMWInst::BinOp Op = AI->getOperation();
16917 llvm_unreachable("Unknown atomic operation");
16918 case AtomicRMWInst::Xchg:
16919 case AtomicRMWInst::Add:
16920 case AtomicRMWInst::Sub:
16921 // It's better to use xadd, xsub or xchg for these in all cases.
16922 return AtomicRMWExpansionKind::None;
16923 case AtomicRMWInst::Or:
16924 case AtomicRMWInst::And:
16925 case AtomicRMWInst::Xor:
16926 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16927 // prefix to a normal instruction for these operations.
16928 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
16929 : AtomicRMWExpansionKind::None;
16930 case AtomicRMWInst::Nand:
16931 case AtomicRMWInst::Max:
16932 case AtomicRMWInst::Min:
16933 case AtomicRMWInst::UMax:
16934 case AtomicRMWInst::UMin:
16935 // These always require a non-trivial set of data operations on x86. We must
16936 // use a cmpxchg loop.
16937 return AtomicRMWExpansionKind::CmpXChg;
16941 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16942 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16943 // no-sse2). There isn't any reason to disable it if the target processor
16945 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16949 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16950 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16951 const Type *MemType = AI->getType();
16952 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16953 // there is no benefit in turning such RMWs into loads, and it is actually
16954 // harmful as it introduces a mfence.
16955 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16958 auto Builder = IRBuilder<>(AI);
16959 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16960 auto SynchScope = AI->getSynchScope();
16961 // We must restrict the ordering to avoid generating loads with Release or
16962 // ReleaseAcquire orderings.
16963 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16964 auto Ptr = AI->getPointerOperand();
16966 // Before the load we need a fence. Here is an example lifted from
16967 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16970 // x.store(1, relaxed);
16971 // r1 = y.fetch_add(0, release);
16973 // y.fetch_add(42, acquire);
16974 // r2 = x.load(relaxed);
16975 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16976 // lowered to just a load without a fence. A mfence flushes the store buffer,
16977 // making the optimization clearly correct.
16978 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16979 // otherwise, we might be able to be more agressive on relaxed idempotent
16980 // rmw. In practice, they do not look useful, so we don't try to be
16981 // especially clever.
16982 if (SynchScope == SingleThread)
16983 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16984 // the IR level, so we must wrap it in an intrinsic.
16987 if (!hasMFENCE(*Subtarget))
16988 // FIXME: it might make sense to use a locked operation here but on a
16989 // different cache-line to prevent cache-line bouncing. In practice it
16990 // is probably a small win, and x86 processors without mfence are rare
16991 // enough that we do not bother.
16995 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
16996 Builder.CreateCall(MFence, {});
16998 // Finally we can emit the atomic load.
16999 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17000 AI->getType()->getPrimitiveSizeInBits());
17001 Loaded->setAtomic(Order, SynchScope);
17002 AI->replaceAllUsesWith(Loaded);
17003 AI->eraseFromParent();
17007 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17008 SelectionDAG &DAG) {
17010 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17011 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17012 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17013 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17015 // The only fence that needs an instruction is a sequentially-consistent
17016 // cross-thread fence.
17017 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17018 if (hasMFENCE(*Subtarget))
17019 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17021 SDValue Chain = Op.getOperand(0);
17022 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17024 DAG.getRegister(X86::ESP, MVT::i32), // Base
17025 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17026 DAG.getRegister(0, MVT::i32), // Index
17027 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17028 DAG.getRegister(0, MVT::i32), // Segment.
17032 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17033 return SDValue(Res, 0);
17036 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17037 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17040 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17041 SelectionDAG &DAG) {
17042 MVT T = Op.getSimpleValueType();
17046 switch(T.SimpleTy) {
17047 default: llvm_unreachable("Invalid value type!");
17048 case MVT::i8: Reg = X86::AL; size = 1; break;
17049 case MVT::i16: Reg = X86::AX; size = 2; break;
17050 case MVT::i32: Reg = X86::EAX; size = 4; break;
17052 assert(Subtarget->is64Bit() && "Node not type legal!");
17053 Reg = X86::RAX; size = 8;
17056 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17057 Op.getOperand(2), SDValue());
17058 SDValue Ops[] = { cpIn.getValue(0),
17061 DAG.getTargetConstant(size, DL, MVT::i8),
17062 cpIn.getValue(1) };
17063 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17064 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17065 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17069 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17070 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17071 MVT::i32, cpOut.getValue(2));
17072 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17073 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17076 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17077 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17078 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17082 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17083 SelectionDAG &DAG) {
17084 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17085 MVT DstVT = Op.getSimpleValueType();
17087 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17088 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17089 if (DstVT != MVT::f64)
17090 // This conversion needs to be expanded.
17093 SDValue InVec = Op->getOperand(0);
17095 unsigned NumElts = SrcVT.getVectorNumElements();
17096 EVT SVT = SrcVT.getVectorElementType();
17098 // Widen the vector in input in the case of MVT::v2i32.
17099 // Example: from MVT::v2i32 to MVT::v4i32.
17100 SmallVector<SDValue, 16> Elts;
17101 for (unsigned i = 0, e = NumElts; i != e; ++i)
17102 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17103 DAG.getIntPtrConstant(i, dl)));
17105 // Explicitly mark the extra elements as Undef.
17106 Elts.append(NumElts, DAG.getUNDEF(SVT));
17108 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17109 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17110 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17111 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17112 DAG.getIntPtrConstant(0, dl));
17115 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17116 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17117 assert((DstVT == MVT::i64 ||
17118 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17119 "Unexpected custom BITCAST");
17120 // i64 <=> MMX conversions are Legal.
17121 if (SrcVT==MVT::i64 && DstVT.isVector())
17123 if (DstVT==MVT::i64 && SrcVT.isVector())
17125 // MMX <=> MMX conversions are Legal.
17126 if (SrcVT.isVector() && DstVT.isVector())
17128 // All other conversions need to be expanded.
17132 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17133 SelectionDAG &DAG) {
17134 SDNode *Node = Op.getNode();
17137 Op = Op.getOperand(0);
17138 EVT VT = Op.getValueType();
17139 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17140 "CTPOP lowering only implemented for 128/256-bit wide vector types");
17142 unsigned NumElts = VT.getVectorNumElements();
17143 EVT EltVT = VT.getVectorElementType();
17144 unsigned Len = EltVT.getSizeInBits();
17146 // This is the vectorized version of the "best" algorithm from
17147 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17148 // with a minor tweak to use a series of adds + shifts instead of vector
17149 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
17151 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
17152 // v8i32 => Always profitable
17154 // FIXME: There a couple of possible improvements:
17156 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
17157 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
17159 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
17160 "CTPOP not implemented for this vector element type.");
17162 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
17163 // extra legalization.
17164 bool NeedsBitcast = EltVT == MVT::i32;
17165 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
17167 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl,
17169 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl,
17171 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl,
17174 // v = v - ((v >> 1) & 0x55555555...)
17175 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, dl, EltVT));
17176 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
17177 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
17179 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17181 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
17182 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
17184 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
17186 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
17187 if (VT != And.getValueType())
17188 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17189 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
17191 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17192 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
17193 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
17194 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, dl, EltVT));
17195 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
17197 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
17198 if (NeedsBitcast) {
17199 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17200 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
17201 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
17204 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
17205 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
17206 if (VT != AndRHS.getValueType()) {
17207 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
17208 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
17210 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
17212 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17213 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, dl, EltVT));
17214 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
17215 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
17216 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17218 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
17219 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
17220 if (NeedsBitcast) {
17221 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17222 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
17224 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
17225 if (VT != And.getValueType())
17226 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17228 // The algorithm mentioned above uses:
17229 // v = (v * 0x01010101...) >> (Len - 8)
17231 // Change it to use vector adds + vector shifts which yield faster results on
17232 // Haswell than using vector integer multiplication.
17234 // For i32 elements:
17235 // v = v + (v >> 8)
17236 // v = v + (v >> 16)
17238 // For i64 elements:
17239 // v = v + (v >> 8)
17240 // v = v + (v >> 16)
17241 // v = v + (v >> 32)
17244 SmallVector<SDValue, 8> Csts;
17245 for (unsigned i = 8; i <= Len/2; i *= 2) {
17246 Csts.assign(NumElts, DAG.getConstant(i, dl, EltVT));
17247 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
17248 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
17249 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17253 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
17254 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), dl,
17256 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
17257 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
17258 if (NeedsBitcast) {
17259 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17260 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
17262 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
17263 if (VT != And.getValueType())
17264 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17269 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17270 SDNode *Node = Op.getNode();
17272 EVT T = Node->getValueType(0);
17273 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17274 DAG.getConstant(0, dl, T), Node->getOperand(2));
17275 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17276 cast<AtomicSDNode>(Node)->getMemoryVT(),
17277 Node->getOperand(0),
17278 Node->getOperand(1), negOp,
17279 cast<AtomicSDNode>(Node)->getMemOperand(),
17280 cast<AtomicSDNode>(Node)->getOrdering(),
17281 cast<AtomicSDNode>(Node)->getSynchScope());
17284 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17285 SDNode *Node = Op.getNode();
17287 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17289 // Convert seq_cst store -> xchg
17290 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17291 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17292 // (The only way to get a 16-byte store is cmpxchg16b)
17293 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17294 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17295 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17296 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17297 cast<AtomicSDNode>(Node)->getMemoryVT(),
17298 Node->getOperand(0),
17299 Node->getOperand(1), Node->getOperand(2),
17300 cast<AtomicSDNode>(Node)->getMemOperand(),
17301 cast<AtomicSDNode>(Node)->getOrdering(),
17302 cast<AtomicSDNode>(Node)->getSynchScope());
17303 return Swap.getValue(1);
17305 // Other atomic stores have a simple pattern.
17309 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17310 EVT VT = Op.getNode()->getSimpleValueType(0);
17312 // Let legalize expand this if it isn't a legal type yet.
17313 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17316 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17319 bool ExtraOp = false;
17320 switch (Op.getOpcode()) {
17321 default: llvm_unreachable("Invalid code");
17322 case ISD::ADDC: Opc = X86ISD::ADD; break;
17323 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17324 case ISD::SUBC: Opc = X86ISD::SUB; break;
17325 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17329 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17331 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17332 Op.getOperand(1), Op.getOperand(2));
17335 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17336 SelectionDAG &DAG) {
17337 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17339 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17340 // which returns the values as { float, float } (in XMM0) or
17341 // { double, double } (which is returned in XMM0, XMM1).
17343 SDValue Arg = Op.getOperand(0);
17344 EVT ArgVT = Arg.getValueType();
17345 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17347 TargetLowering::ArgListTy Args;
17348 TargetLowering::ArgListEntry Entry;
17352 Entry.isSExt = false;
17353 Entry.isZExt = false;
17354 Args.push_back(Entry);
17356 bool isF64 = ArgVT == MVT::f64;
17357 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17358 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17359 // the results are returned via SRet in memory.
17360 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17362 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17364 Type *RetTy = isF64
17365 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17366 : (Type*)VectorType::get(ArgTy, 4);
17368 TargetLowering::CallLoweringInfo CLI(DAG);
17369 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17370 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17372 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17375 // Returned in xmm0 and xmm1.
17376 return CallResult.first;
17378 // Returned in bits 0:31 and 32:64 xmm0.
17379 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17380 CallResult.first, DAG.getIntPtrConstant(0, dl));
17381 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17382 CallResult.first, DAG.getIntPtrConstant(1, dl));
17383 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17384 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17387 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17388 SelectionDAG &DAG) {
17389 assert(Subtarget->hasAVX512() &&
17390 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17392 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17393 EVT VT = N->getValue().getValueType();
17394 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17397 // X86 scatter kills mask register, so its type should be added to
17398 // the list of return values
17399 if (N->getNumValues() == 1) {
17400 SDValue Index = N->getIndex();
17401 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17402 !Index.getValueType().is512BitVector())
17403 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17405 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17406 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17407 N->getOperand(3), Index };
17409 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17410 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17411 return SDValue(NewScatter.getNode(), 0);
17416 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17417 SelectionDAG &DAG) {
17418 assert(Subtarget->hasAVX512() &&
17419 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17421 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17422 EVT VT = Op.getValueType();
17423 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17426 SDValue Index = N->getIndex();
17427 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17428 !Index.getValueType().is512BitVector()) {
17429 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17430 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17431 N->getOperand(3), Index };
17432 DAG.UpdateNodeOperands(N, Ops);
17437 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
17438 SelectionDAG &DAG) const {
17439 // TODO: Eventually, the lowering of these nodes should be informed by or
17440 // deferred to the GC strategy for the function in which they appear. For
17441 // now, however, they must be lowered to something. Since they are logically
17442 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17443 // require special handling for these nodes), lower them as literal NOOPs for
17445 SmallVector<SDValue, 2> Ops;
17447 Ops.push_back(Op.getOperand(0));
17448 if (Op->getGluedNode())
17449 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17452 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17453 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17458 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
17459 SelectionDAG &DAG) const {
17460 // TODO: Eventually, the lowering of these nodes should be informed by or
17461 // deferred to the GC strategy for the function in which they appear. For
17462 // now, however, they must be lowered to something. Since they are logically
17463 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17464 // require special handling for these nodes), lower them as literal NOOPs for
17466 SmallVector<SDValue, 2> Ops;
17468 Ops.push_back(Op.getOperand(0));
17469 if (Op->getGluedNode())
17470 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17473 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17474 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17479 /// LowerOperation - Provide custom lowering hooks for some operations.
17481 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17482 switch (Op.getOpcode()) {
17483 default: llvm_unreachable("Should not custom lower this!");
17484 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17485 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17486 return LowerCMP_SWAP(Op, Subtarget, DAG);
17487 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17488 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17489 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17490 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17491 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17492 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17493 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17494 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17495 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17496 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17497 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17498 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17499 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17500 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17501 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17502 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17503 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17504 case ISD::SHL_PARTS:
17505 case ISD::SRA_PARTS:
17506 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17507 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17508 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17509 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17510 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17511 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17512 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17513 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17514 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17515 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17516 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17518 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17519 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17520 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17521 case ISD::SETCC: return LowerSETCC(Op, DAG);
17522 case ISD::SELECT: return LowerSELECT(Op, DAG);
17523 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17524 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17525 case ISD::VASTART: return LowerVASTART(Op, DAG);
17526 case ISD::VAARG: return LowerVAARG(Op, DAG);
17527 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17528 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17529 case ISD::INTRINSIC_VOID:
17530 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17531 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17532 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17533 case ISD::FRAME_TO_ARGS_OFFSET:
17534 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17535 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17536 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17537 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17538 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17539 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17540 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17541 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17542 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17543 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17544 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17545 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17546 case ISD::UMUL_LOHI:
17547 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17550 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17556 case ISD::UMULO: return LowerXALUO(Op, DAG);
17557 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17558 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17562 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17563 case ISD::ADD: return LowerADD(Op, DAG);
17564 case ISD::SUB: return LowerSUB(Op, DAG);
17565 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17566 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
17567 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
17568 case ISD::GC_TRANSITION_START:
17569 return LowerGC_TRANSITION_START(Op, DAG);
17570 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
17574 /// ReplaceNodeResults - Replace a node with an illegal result type
17575 /// with a new node built out of custom code.
17576 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17577 SmallVectorImpl<SDValue>&Results,
17578 SelectionDAG &DAG) const {
17580 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17581 switch (N->getOpcode()) {
17583 llvm_unreachable("Do not know how to custom type legalize this operation!");
17584 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17585 case X86ISD::FMINC:
17587 case X86ISD::FMAXC:
17588 case X86ISD::FMAX: {
17589 EVT VT = N->getValueType(0);
17590 if (VT != MVT::v2f32)
17591 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17592 SDValue UNDEF = DAG.getUNDEF(VT);
17593 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17594 N->getOperand(0), UNDEF);
17595 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17596 N->getOperand(1), UNDEF);
17597 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17600 case ISD::SIGN_EXTEND_INREG:
17605 // We don't want to expand or promote these.
17612 case ISD::UDIVREM: {
17613 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17614 Results.push_back(V);
17617 case ISD::FP_TO_SINT:
17618 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
17619 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
17620 if (N->getOperand(0).getValueType() == MVT::f16)
17623 case ISD::FP_TO_UINT: {
17624 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17626 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17629 std::pair<SDValue,SDValue> Vals =
17630 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17631 SDValue FIST = Vals.first, StackSlot = Vals.second;
17632 if (FIST.getNode()) {
17633 EVT VT = N->getValueType(0);
17634 // Return a load from the stack slot.
17635 if (StackSlot.getNode())
17636 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17637 MachinePointerInfo(),
17638 false, false, false, 0));
17640 Results.push_back(FIST);
17644 case ISD::UINT_TO_FP: {
17645 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17646 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17647 N->getValueType(0) != MVT::v2f32)
17649 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17651 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
17653 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17654 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17655 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17656 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17657 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17658 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17661 case ISD::FP_ROUND: {
17662 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17664 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17665 Results.push_back(V);
17668 case ISD::FP_EXTEND: {
17669 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
17670 // No other ValueType for FP_EXTEND should reach this point.
17671 assert(N->getValueType(0) == MVT::v2f32 &&
17672 "Do not know how to legalize this Node");
17675 case ISD::INTRINSIC_W_CHAIN: {
17676 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17678 default : llvm_unreachable("Do not know how to custom type "
17679 "legalize this intrinsic operation!");
17680 case Intrinsic::x86_rdtsc:
17681 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17683 case Intrinsic::x86_rdtscp:
17684 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17686 case Intrinsic::x86_rdpmc:
17687 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17690 case ISD::READCYCLECOUNTER: {
17691 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17694 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17695 EVT T = N->getValueType(0);
17696 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17697 bool Regs64bit = T == MVT::i128;
17698 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17699 SDValue cpInL, cpInH;
17700 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17701 DAG.getConstant(0, dl, HalfT));
17702 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17703 DAG.getConstant(1, dl, HalfT));
17704 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17705 Regs64bit ? X86::RAX : X86::EAX,
17707 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17708 Regs64bit ? X86::RDX : X86::EDX,
17709 cpInH, cpInL.getValue(1));
17710 SDValue swapInL, swapInH;
17711 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17712 DAG.getConstant(0, dl, HalfT));
17713 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17714 DAG.getConstant(1, dl, HalfT));
17715 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17716 Regs64bit ? X86::RBX : X86::EBX,
17717 swapInL, cpInH.getValue(1));
17718 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17719 Regs64bit ? X86::RCX : X86::ECX,
17720 swapInH, swapInL.getValue(1));
17721 SDValue Ops[] = { swapInH.getValue(0),
17723 swapInH.getValue(1) };
17724 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17725 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17726 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17727 X86ISD::LCMPXCHG8_DAG;
17728 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17729 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17730 Regs64bit ? X86::RAX : X86::EAX,
17731 HalfT, Result.getValue(1));
17732 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17733 Regs64bit ? X86::RDX : X86::EDX,
17734 HalfT, cpOutL.getValue(2));
17735 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17737 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17738 MVT::i32, cpOutH.getValue(2));
17740 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17741 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
17742 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17744 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17745 Results.push_back(Success);
17746 Results.push_back(EFLAGS.getValue(1));
17749 case ISD::ATOMIC_SWAP:
17750 case ISD::ATOMIC_LOAD_ADD:
17751 case ISD::ATOMIC_LOAD_SUB:
17752 case ISD::ATOMIC_LOAD_AND:
17753 case ISD::ATOMIC_LOAD_OR:
17754 case ISD::ATOMIC_LOAD_XOR:
17755 case ISD::ATOMIC_LOAD_NAND:
17756 case ISD::ATOMIC_LOAD_MIN:
17757 case ISD::ATOMIC_LOAD_MAX:
17758 case ISD::ATOMIC_LOAD_UMIN:
17759 case ISD::ATOMIC_LOAD_UMAX:
17760 case ISD::ATOMIC_LOAD: {
17761 // Delegate to generic TypeLegalization. Situations we can really handle
17762 // should have already been dealt with by AtomicExpandPass.cpp.
17765 case ISD::BITCAST: {
17766 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17767 EVT DstVT = N->getValueType(0);
17768 EVT SrcVT = N->getOperand(0)->getValueType(0);
17770 if (SrcVT != MVT::f64 ||
17771 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17774 unsigned NumElts = DstVT.getVectorNumElements();
17775 EVT SVT = DstVT.getVectorElementType();
17776 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17777 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17778 MVT::v2f64, N->getOperand(0));
17779 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17781 if (ExperimentalVectorWideningLegalization) {
17782 // If we are legalizing vectors by widening, we already have the desired
17783 // legal vector type, just return it.
17784 Results.push_back(ToVecInt);
17788 SmallVector<SDValue, 8> Elts;
17789 for (unsigned i = 0, e = NumElts; i != e; ++i)
17790 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17791 ToVecInt, DAG.getIntPtrConstant(i, dl)));
17793 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17798 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17799 switch ((X86ISD::NodeType)Opcode) {
17800 case X86ISD::FIRST_NUMBER: break;
17801 case X86ISD::BSF: return "X86ISD::BSF";
17802 case X86ISD::BSR: return "X86ISD::BSR";
17803 case X86ISD::SHLD: return "X86ISD::SHLD";
17804 case X86ISD::SHRD: return "X86ISD::SHRD";
17805 case X86ISD::FAND: return "X86ISD::FAND";
17806 case X86ISD::FANDN: return "X86ISD::FANDN";
17807 case X86ISD::FOR: return "X86ISD::FOR";
17808 case X86ISD::FXOR: return "X86ISD::FXOR";
17809 case X86ISD::FSRL: return "X86ISD::FSRL";
17810 case X86ISD::FILD: return "X86ISD::FILD";
17811 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17812 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17813 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17814 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17815 case X86ISD::FLD: return "X86ISD::FLD";
17816 case X86ISD::FST: return "X86ISD::FST";
17817 case X86ISD::CALL: return "X86ISD::CALL";
17818 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17819 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17820 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17821 case X86ISD::BT: return "X86ISD::BT";
17822 case X86ISD::CMP: return "X86ISD::CMP";
17823 case X86ISD::COMI: return "X86ISD::COMI";
17824 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17825 case X86ISD::CMPM: return "X86ISD::CMPM";
17826 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17827 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
17828 case X86ISD::SETCC: return "X86ISD::SETCC";
17829 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17830 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17831 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
17832 case X86ISD::CMOV: return "X86ISD::CMOV";
17833 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17834 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17835 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17836 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17837 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17838 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17839 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17840 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
17841 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
17842 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
17843 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17844 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17845 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17846 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17847 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17848 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
17849 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17850 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17851 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17852 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17853 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17854 case X86ISD::ADDUS: return "X86ISD::ADDUS";
17855 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17856 case X86ISD::HADD: return "X86ISD::HADD";
17857 case X86ISD::HSUB: return "X86ISD::HSUB";
17858 case X86ISD::FHADD: return "X86ISD::FHADD";
17859 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17860 case X86ISD::UMAX: return "X86ISD::UMAX";
17861 case X86ISD::UMIN: return "X86ISD::UMIN";
17862 case X86ISD::SMAX: return "X86ISD::SMAX";
17863 case X86ISD::SMIN: return "X86ISD::SMIN";
17864 case X86ISD::FMAX: return "X86ISD::FMAX";
17865 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
17866 case X86ISD::FMIN: return "X86ISD::FMIN";
17867 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
17868 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17869 case X86ISD::FMINC: return "X86ISD::FMINC";
17870 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17871 case X86ISD::FRCP: return "X86ISD::FRCP";
17872 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17873 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17874 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17875 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17876 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17877 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17878 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17879 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17880 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17881 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17882 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17883 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17884 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17885 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17886 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17887 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17888 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17889 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17890 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17891 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17892 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17893 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17894 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17895 case X86ISD::VSHL: return "X86ISD::VSHL";
17896 case X86ISD::VSRL: return "X86ISD::VSRL";
17897 case X86ISD::VSRA: return "X86ISD::VSRA";
17898 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17899 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17900 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17901 case X86ISD::CMPP: return "X86ISD::CMPP";
17902 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17903 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17904 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17905 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17906 case X86ISD::ADD: return "X86ISD::ADD";
17907 case X86ISD::SUB: return "X86ISD::SUB";
17908 case X86ISD::ADC: return "X86ISD::ADC";
17909 case X86ISD::SBB: return "X86ISD::SBB";
17910 case X86ISD::SMUL: return "X86ISD::SMUL";
17911 case X86ISD::UMUL: return "X86ISD::UMUL";
17912 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17913 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17914 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17915 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17916 case X86ISD::INC: return "X86ISD::INC";
17917 case X86ISD::DEC: return "X86ISD::DEC";
17918 case X86ISD::OR: return "X86ISD::OR";
17919 case X86ISD::XOR: return "X86ISD::XOR";
17920 case X86ISD::AND: return "X86ISD::AND";
17921 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17922 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17923 case X86ISD::PTEST: return "X86ISD::PTEST";
17924 case X86ISD::TESTP: return "X86ISD::TESTP";
17925 case X86ISD::TESTM: return "X86ISD::TESTM";
17926 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17927 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17928 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17929 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17930 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17931 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17932 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17933 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17934 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17935 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17936 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17937 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17938 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17939 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17940 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17941 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17942 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17943 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17944 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17945 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17946 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17947 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17948 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17949 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
17950 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17951 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
17952 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17953 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17954 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17955 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17956 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17957 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17958 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17959 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17960 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17961 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17962 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17963 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17964 case X86ISD::MFENCE: return "X86ISD::MFENCE";
17965 case X86ISD::SFENCE: return "X86ISD::SFENCE";
17966 case X86ISD::LFENCE: return "X86ISD::LFENCE";
17967 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17968 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17969 case X86ISD::SAHF: return "X86ISD::SAHF";
17970 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17971 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17972 case X86ISD::FMADD: return "X86ISD::FMADD";
17973 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17974 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17975 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17976 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17977 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17978 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
17979 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
17980 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
17981 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
17982 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
17983 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
17984 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
17985 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17986 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17987 case X86ISD::XTEST: return "X86ISD::XTEST";
17988 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17989 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17990 case X86ISD::SELECT: return "X86ISD::SELECT";
17991 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17992 case X86ISD::RCP28: return "X86ISD::RCP28";
17993 case X86ISD::EXP2: return "X86ISD::EXP2";
17994 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17995 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17996 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17997 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17998 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17999 case X86ISD::ADDS: return "X86ISD::ADDS";
18000 case X86ISD::SUBS: return "X86ISD::SUBS";
18005 // isLegalAddressingMode - Return true if the addressing mode represented
18006 // by AM is legal for this target, for a load/store of the specified type.
18007 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18009 // X86 supports extremely general addressing modes.
18010 CodeModel::Model M = getTargetMachine().getCodeModel();
18011 Reloc::Model R = getTargetMachine().getRelocationModel();
18013 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18014 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18019 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18021 // If a reference to this global requires an extra load, we can't fold it.
18022 if (isGlobalStubReference(GVFlags))
18025 // If BaseGV requires a register for the PIC base, we cannot also have a
18026 // BaseReg specified.
18027 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18030 // If lower 4G is not available, then we must use rip-relative addressing.
18031 if ((M != CodeModel::Small || R != Reloc::Static) &&
18032 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18036 switch (AM.Scale) {
18042 // These scales always work.
18047 // These scales are formed with basereg+scalereg. Only accept if there is
18052 default: // Other stuff never works.
18059 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18060 unsigned Bits = Ty->getScalarSizeInBits();
18062 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18063 // particularly cheaper than those without.
18067 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18068 // variable shifts just as cheap as scalar ones.
18069 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18072 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18073 // fully general vector.
18077 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18078 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18080 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18081 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18082 return NumBits1 > NumBits2;
18085 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18086 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18089 if (!isTypeLegal(EVT::getEVT(Ty1)))
18092 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18094 // Assuming the caller doesn't have a zeroext or signext return parameter,
18095 // truncation all the way down to i1 is valid.
18099 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18100 return isInt<32>(Imm);
18103 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18104 // Can also use sub to handle negated immediates.
18105 return isInt<32>(Imm);
18108 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18109 if (!VT1.isInteger() || !VT2.isInteger())
18111 unsigned NumBits1 = VT1.getSizeInBits();
18112 unsigned NumBits2 = VT2.getSizeInBits();
18113 return NumBits1 > NumBits2;
18116 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18117 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18118 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18121 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18122 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18123 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18126 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18127 EVT VT1 = Val.getValueType();
18128 if (isZExtFree(VT1, VT2))
18131 if (Val.getOpcode() != ISD::LOAD)
18134 if (!VT1.isSimple() || !VT1.isInteger() ||
18135 !VT2.isSimple() || !VT2.isInteger())
18138 switch (VT1.getSimpleVT().SimpleTy) {
18143 // X86 has 8, 16, and 32-bit zero-extending loads.
18150 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18153 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18154 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18157 VT = VT.getScalarType();
18159 if (!VT.isSimple())
18162 switch (VT.getSimpleVT().SimpleTy) {
18173 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18174 // i16 instructions are longer (0x66 prefix) and potentially slower.
18175 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18178 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18179 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18180 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18181 /// are assumed to be legal.
18183 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18185 if (!VT.isSimple())
18188 // Not for i1 vectors
18189 if (VT.getScalarType() == MVT::i1)
18192 // Very little shuffling can be done for 64-bit vectors right now.
18193 if (VT.getSizeInBits() == 64)
18196 // We only care that the types being shuffled are legal. The lowering can
18197 // handle any possible shuffle mask that results.
18198 return isTypeLegal(VT.getSimpleVT());
18202 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18204 // Just delegate to the generic legality, clear masks aren't special.
18205 return isShuffleMaskLegal(Mask, VT);
18208 //===----------------------------------------------------------------------===//
18209 // X86 Scheduler Hooks
18210 //===----------------------------------------------------------------------===//
18212 /// Utility function to emit xbegin specifying the start of an RTM region.
18213 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18214 const TargetInstrInfo *TII) {
18215 DebugLoc DL = MI->getDebugLoc();
18217 const BasicBlock *BB = MBB->getBasicBlock();
18218 MachineFunction::iterator I = MBB;
18221 // For the v = xbegin(), we generate
18232 MachineBasicBlock *thisMBB = MBB;
18233 MachineFunction *MF = MBB->getParent();
18234 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18235 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18236 MF->insert(I, mainMBB);
18237 MF->insert(I, sinkMBB);
18239 // Transfer the remainder of BB and its successor edges to sinkMBB.
18240 sinkMBB->splice(sinkMBB->begin(), MBB,
18241 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18242 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18246 // # fallthrough to mainMBB
18247 // # abortion to sinkMBB
18248 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18249 thisMBB->addSuccessor(mainMBB);
18250 thisMBB->addSuccessor(sinkMBB);
18254 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18255 mainMBB->addSuccessor(sinkMBB);
18258 // EAX is live into the sinkMBB
18259 sinkMBB->addLiveIn(X86::EAX);
18260 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18261 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18264 MI->eraseFromParent();
18268 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18269 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18270 // in the .td file.
18271 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18272 const TargetInstrInfo *TII) {
18274 switch (MI->getOpcode()) {
18275 default: llvm_unreachable("illegal opcode!");
18276 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18277 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18278 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18279 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18280 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18281 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18282 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18283 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18286 DebugLoc dl = MI->getDebugLoc();
18287 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18289 unsigned NumArgs = MI->getNumOperands();
18290 for (unsigned i = 1; i < NumArgs; ++i) {
18291 MachineOperand &Op = MI->getOperand(i);
18292 if (!(Op.isReg() && Op.isImplicit()))
18293 MIB.addOperand(Op);
18295 if (MI->hasOneMemOperand())
18296 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18298 BuildMI(*BB, MI, dl,
18299 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18300 .addReg(X86::XMM0);
18302 MI->eraseFromParent();
18306 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18307 // defs in an instruction pattern
18308 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18309 const TargetInstrInfo *TII) {
18311 switch (MI->getOpcode()) {
18312 default: llvm_unreachable("illegal opcode!");
18313 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18314 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18315 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18316 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18317 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18318 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18319 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18320 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18323 DebugLoc dl = MI->getDebugLoc();
18324 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18326 unsigned NumArgs = MI->getNumOperands(); // remove the results
18327 for (unsigned i = 1; i < NumArgs; ++i) {
18328 MachineOperand &Op = MI->getOperand(i);
18329 if (!(Op.isReg() && Op.isImplicit()))
18330 MIB.addOperand(Op);
18332 if (MI->hasOneMemOperand())
18333 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18335 BuildMI(*BB, MI, dl,
18336 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18339 MI->eraseFromParent();
18343 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18344 const X86Subtarget *Subtarget) {
18345 DebugLoc dl = MI->getDebugLoc();
18346 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18347 // Address into RAX/EAX, other two args into ECX, EDX.
18348 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18349 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18350 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18351 for (int i = 0; i < X86::AddrNumOperands; ++i)
18352 MIB.addOperand(MI->getOperand(i));
18354 unsigned ValOps = X86::AddrNumOperands;
18355 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18356 .addReg(MI->getOperand(ValOps).getReg());
18357 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18358 .addReg(MI->getOperand(ValOps+1).getReg());
18360 // The instruction doesn't actually take any operands though.
18361 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18363 MI->eraseFromParent(); // The pseudo is gone now.
18367 MachineBasicBlock *
18368 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18369 MachineBasicBlock *MBB) const {
18370 // Emit va_arg instruction on X86-64.
18372 // Operands to this pseudo-instruction:
18373 // 0 ) Output : destination address (reg)
18374 // 1-5) Input : va_list address (addr, i64mem)
18375 // 6 ) ArgSize : Size (in bytes) of vararg type
18376 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18377 // 8 ) Align : Alignment of type
18378 // 9 ) EFLAGS (implicit-def)
18380 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18381 static_assert(X86::AddrNumOperands == 5,
18382 "VAARG_64 assumes 5 address operands");
18384 unsigned DestReg = MI->getOperand(0).getReg();
18385 MachineOperand &Base = MI->getOperand(1);
18386 MachineOperand &Scale = MI->getOperand(2);
18387 MachineOperand &Index = MI->getOperand(3);
18388 MachineOperand &Disp = MI->getOperand(4);
18389 MachineOperand &Segment = MI->getOperand(5);
18390 unsigned ArgSize = MI->getOperand(6).getImm();
18391 unsigned ArgMode = MI->getOperand(7).getImm();
18392 unsigned Align = MI->getOperand(8).getImm();
18394 // Memory Reference
18395 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18396 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18397 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18399 // Machine Information
18400 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18401 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18402 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18403 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18404 DebugLoc DL = MI->getDebugLoc();
18406 // struct va_list {
18409 // i64 overflow_area (address)
18410 // i64 reg_save_area (address)
18412 // sizeof(va_list) = 24
18413 // alignment(va_list) = 8
18415 unsigned TotalNumIntRegs = 6;
18416 unsigned TotalNumXMMRegs = 8;
18417 bool UseGPOffset = (ArgMode == 1);
18418 bool UseFPOffset = (ArgMode == 2);
18419 unsigned MaxOffset = TotalNumIntRegs * 8 +
18420 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18422 /* Align ArgSize to a multiple of 8 */
18423 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18424 bool NeedsAlign = (Align > 8);
18426 MachineBasicBlock *thisMBB = MBB;
18427 MachineBasicBlock *overflowMBB;
18428 MachineBasicBlock *offsetMBB;
18429 MachineBasicBlock *endMBB;
18431 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18432 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18433 unsigned OffsetReg = 0;
18435 if (!UseGPOffset && !UseFPOffset) {
18436 // If we only pull from the overflow region, we don't create a branch.
18437 // We don't need to alter control flow.
18438 OffsetDestReg = 0; // unused
18439 OverflowDestReg = DestReg;
18441 offsetMBB = nullptr;
18442 overflowMBB = thisMBB;
18445 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18446 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18447 // If not, pull from overflow_area. (branch to overflowMBB)
18452 // offsetMBB overflowMBB
18457 // Registers for the PHI in endMBB
18458 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18459 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18461 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18462 MachineFunction *MF = MBB->getParent();
18463 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18464 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18465 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18467 MachineFunction::iterator MBBIter = MBB;
18470 // Insert the new basic blocks
18471 MF->insert(MBBIter, offsetMBB);
18472 MF->insert(MBBIter, overflowMBB);
18473 MF->insert(MBBIter, endMBB);
18475 // Transfer the remainder of MBB and its successor edges to endMBB.
18476 endMBB->splice(endMBB->begin(), thisMBB,
18477 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18478 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18480 // Make offsetMBB and overflowMBB successors of thisMBB
18481 thisMBB->addSuccessor(offsetMBB);
18482 thisMBB->addSuccessor(overflowMBB);
18484 // endMBB is a successor of both offsetMBB and overflowMBB
18485 offsetMBB->addSuccessor(endMBB);
18486 overflowMBB->addSuccessor(endMBB);
18488 // Load the offset value into a register
18489 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18490 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18494 .addDisp(Disp, UseFPOffset ? 4 : 0)
18495 .addOperand(Segment)
18496 .setMemRefs(MMOBegin, MMOEnd);
18498 // Check if there is enough room left to pull this argument.
18499 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18501 .addImm(MaxOffset + 8 - ArgSizeA8);
18503 // Branch to "overflowMBB" if offset >= max
18504 // Fall through to "offsetMBB" otherwise
18505 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18506 .addMBB(overflowMBB);
18509 // In offsetMBB, emit code to use the reg_save_area.
18511 assert(OffsetReg != 0);
18513 // Read the reg_save_area address.
18514 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18515 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18520 .addOperand(Segment)
18521 .setMemRefs(MMOBegin, MMOEnd);
18523 // Zero-extend the offset
18524 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18525 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18528 .addImm(X86::sub_32bit);
18530 // Add the offset to the reg_save_area to get the final address.
18531 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18532 .addReg(OffsetReg64)
18533 .addReg(RegSaveReg);
18535 // Compute the offset for the next argument
18536 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18537 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18539 .addImm(UseFPOffset ? 16 : 8);
18541 // Store it back into the va_list.
18542 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18546 .addDisp(Disp, UseFPOffset ? 4 : 0)
18547 .addOperand(Segment)
18548 .addReg(NextOffsetReg)
18549 .setMemRefs(MMOBegin, MMOEnd);
18552 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18557 // Emit code to use overflow area
18560 // Load the overflow_area address into a register.
18561 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18562 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18567 .addOperand(Segment)
18568 .setMemRefs(MMOBegin, MMOEnd);
18570 // If we need to align it, do so. Otherwise, just copy the address
18571 // to OverflowDestReg.
18573 // Align the overflow address
18574 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18575 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18577 // aligned_addr = (addr + (align-1)) & ~(align-1)
18578 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18579 .addReg(OverflowAddrReg)
18582 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18584 .addImm(~(uint64_t)(Align-1));
18586 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18587 .addReg(OverflowAddrReg);
18590 // Compute the next overflow address after this argument.
18591 // (the overflow address should be kept 8-byte aligned)
18592 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18593 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18594 .addReg(OverflowDestReg)
18595 .addImm(ArgSizeA8);
18597 // Store the new overflow address.
18598 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18603 .addOperand(Segment)
18604 .addReg(NextAddrReg)
18605 .setMemRefs(MMOBegin, MMOEnd);
18607 // If we branched, emit the PHI to the front of endMBB.
18609 BuildMI(*endMBB, endMBB->begin(), DL,
18610 TII->get(X86::PHI), DestReg)
18611 .addReg(OffsetDestReg).addMBB(offsetMBB)
18612 .addReg(OverflowDestReg).addMBB(overflowMBB);
18615 // Erase the pseudo instruction
18616 MI->eraseFromParent();
18621 MachineBasicBlock *
18622 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18624 MachineBasicBlock *MBB) const {
18625 // Emit code to save XMM registers to the stack. The ABI says that the
18626 // number of registers to save is given in %al, so it's theoretically
18627 // possible to do an indirect jump trick to avoid saving all of them,
18628 // however this code takes a simpler approach and just executes all
18629 // of the stores if %al is non-zero. It's less code, and it's probably
18630 // easier on the hardware branch predictor, and stores aren't all that
18631 // expensive anyway.
18633 // Create the new basic blocks. One block contains all the XMM stores,
18634 // and one block is the final destination regardless of whether any
18635 // stores were performed.
18636 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18637 MachineFunction *F = MBB->getParent();
18638 MachineFunction::iterator MBBIter = MBB;
18640 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18641 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18642 F->insert(MBBIter, XMMSaveMBB);
18643 F->insert(MBBIter, EndMBB);
18645 // Transfer the remainder of MBB and its successor edges to EndMBB.
18646 EndMBB->splice(EndMBB->begin(), MBB,
18647 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18648 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18650 // The original block will now fall through to the XMM save block.
18651 MBB->addSuccessor(XMMSaveMBB);
18652 // The XMMSaveMBB will fall through to the end block.
18653 XMMSaveMBB->addSuccessor(EndMBB);
18655 // Now add the instructions.
18656 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18657 DebugLoc DL = MI->getDebugLoc();
18659 unsigned CountReg = MI->getOperand(0).getReg();
18660 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18661 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18663 if (!Subtarget->isTargetWin64()) {
18664 // If %al is 0, branch around the XMM save block.
18665 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18666 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18667 MBB->addSuccessor(EndMBB);
18670 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18671 // that was just emitted, but clearly shouldn't be "saved".
18672 assert((MI->getNumOperands() <= 3 ||
18673 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18674 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18675 && "Expected last argument to be EFLAGS");
18676 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18677 // In the XMM save block, save all the XMM argument registers.
18678 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18679 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18680 MachineMemOperand *MMO =
18681 F->getMachineMemOperand(
18682 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18683 MachineMemOperand::MOStore,
18684 /*Size=*/16, /*Align=*/16);
18685 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18686 .addFrameIndex(RegSaveFrameIndex)
18687 .addImm(/*Scale=*/1)
18688 .addReg(/*IndexReg=*/0)
18689 .addImm(/*Disp=*/Offset)
18690 .addReg(/*Segment=*/0)
18691 .addReg(MI->getOperand(i).getReg())
18692 .addMemOperand(MMO);
18695 MI->eraseFromParent(); // The pseudo instruction is gone now.
18700 // The EFLAGS operand of SelectItr might be missing a kill marker
18701 // because there were multiple uses of EFLAGS, and ISel didn't know
18702 // which to mark. Figure out whether SelectItr should have had a
18703 // kill marker, and set it if it should. Returns the correct kill
18705 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18706 MachineBasicBlock* BB,
18707 const TargetRegisterInfo* TRI) {
18708 // Scan forward through BB for a use/def of EFLAGS.
18709 MachineBasicBlock::iterator miI(std::next(SelectItr));
18710 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18711 const MachineInstr& mi = *miI;
18712 if (mi.readsRegister(X86::EFLAGS))
18714 if (mi.definesRegister(X86::EFLAGS))
18715 break; // Should have kill-flag - update below.
18718 // If we hit the end of the block, check whether EFLAGS is live into a
18720 if (miI == BB->end()) {
18721 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18722 sEnd = BB->succ_end();
18723 sItr != sEnd; ++sItr) {
18724 MachineBasicBlock* succ = *sItr;
18725 if (succ->isLiveIn(X86::EFLAGS))
18730 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18731 // out. SelectMI should have a kill flag on EFLAGS.
18732 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18736 MachineBasicBlock *
18737 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18738 MachineBasicBlock *BB) const {
18739 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18740 DebugLoc DL = MI->getDebugLoc();
18742 // To "insert" a SELECT_CC instruction, we actually have to insert the
18743 // diamond control-flow pattern. The incoming instruction knows the
18744 // destination vreg to set, the condition code register to branch on, the
18745 // true/false values to select between, and a branch opcode to use.
18746 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18747 MachineFunction::iterator It = BB;
18753 // cmpTY ccX, r1, r2
18755 // fallthrough --> copy0MBB
18756 MachineBasicBlock *thisMBB = BB;
18757 MachineFunction *F = BB->getParent();
18759 // We also lower double CMOVs:
18760 // (CMOV (CMOV F, T, cc1), T, cc2)
18761 // to two successives branches. For that, we look for another CMOV as the
18762 // following instruction.
18764 // Without this, we would add a PHI between the two jumps, which ends up
18765 // creating a few copies all around. For instance, for
18767 // (sitofp (zext (fcmp une)))
18769 // we would generate:
18771 // ucomiss %xmm1, %xmm0
18772 // movss <1.0f>, %xmm0
18773 // movaps %xmm0, %xmm1
18775 // xorps %xmm1, %xmm1
18778 // movaps %xmm1, %xmm0
18782 // because this custom-inserter would have generated:
18794 // A: X = ...; Y = ...
18796 // C: Z = PHI [X, A], [Y, B]
18798 // E: PHI [X, C], [Z, D]
18800 // If we lower both CMOVs in a single step, we can instead generate:
18812 // A: X = ...; Y = ...
18814 // E: PHI [X, A], [X, C], [Y, D]
18816 // Which, in our sitofp/fcmp example, gives us something like:
18818 // ucomiss %xmm1, %xmm0
18819 // movss <1.0f>, %xmm0
18822 // xorps %xmm0, %xmm0
18826 MachineInstr *NextCMOV = nullptr;
18827 MachineBasicBlock::iterator NextMIIt =
18828 std::next(MachineBasicBlock::iterator(MI));
18829 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
18830 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
18831 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
18832 NextCMOV = &*NextMIIt;
18834 MachineBasicBlock *jcc1MBB = nullptr;
18836 // If we have a double CMOV, we lower it to two successive branches to
18837 // the same block. EFLAGS is used by both, so mark it as live in the second.
18839 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
18840 F->insert(It, jcc1MBB);
18841 jcc1MBB->addLiveIn(X86::EFLAGS);
18844 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18845 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18846 F->insert(It, copy0MBB);
18847 F->insert(It, sinkMBB);
18849 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18850 // live into the sink and copy blocks.
18851 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18853 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
18854 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
18855 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
18856 copy0MBB->addLiveIn(X86::EFLAGS);
18857 sinkMBB->addLiveIn(X86::EFLAGS);
18860 // Transfer the remainder of BB and its successor edges to sinkMBB.
18861 sinkMBB->splice(sinkMBB->begin(), BB,
18862 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18863 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18865 // Add the true and fallthrough blocks as its successors.
18867 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
18868 BB->addSuccessor(jcc1MBB);
18870 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
18871 // jump to the sinkMBB.
18872 jcc1MBB->addSuccessor(copy0MBB);
18873 jcc1MBB->addSuccessor(sinkMBB);
18875 BB->addSuccessor(copy0MBB);
18878 // The true block target of the first (or only) branch is always sinkMBB.
18879 BB->addSuccessor(sinkMBB);
18881 // Create the conditional branch instruction.
18883 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18884 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18887 unsigned Opc2 = X86::GetCondBranchFromCond(
18888 (X86::CondCode)NextCMOV->getOperand(3).getImm());
18889 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
18893 // %FalseValue = ...
18894 // # fallthrough to sinkMBB
18895 copy0MBB->addSuccessor(sinkMBB);
18898 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18900 MachineInstrBuilder MIB =
18901 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
18902 MI->getOperand(0).getReg())
18903 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18904 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18906 // If we have a double CMOV, the second Jcc provides the same incoming
18907 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
18909 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
18910 // Copy the PHI result to the register defined by the second CMOV.
18911 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
18912 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
18913 .addReg(MI->getOperand(0).getReg());
18914 NextCMOV->eraseFromParent();
18917 MI->eraseFromParent(); // The pseudo instruction is gone now.
18921 MachineBasicBlock *
18922 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18923 MachineBasicBlock *BB) const {
18924 MachineFunction *MF = BB->getParent();
18925 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18926 DebugLoc DL = MI->getDebugLoc();
18927 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18929 assert(MF->shouldSplitStack());
18931 const bool Is64Bit = Subtarget->is64Bit();
18932 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18934 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18935 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18938 // ... [Till the alloca]
18939 // If stacklet is not large enough, jump to mallocMBB
18942 // Allocate by subtracting from RSP
18943 // Jump to continueMBB
18946 // Allocate by call to runtime
18950 // [rest of original BB]
18953 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18954 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18955 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18957 MachineRegisterInfo &MRI = MF->getRegInfo();
18958 const TargetRegisterClass *AddrRegClass =
18959 getRegClassFor(getPointerTy());
18961 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18962 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18963 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18964 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18965 sizeVReg = MI->getOperand(1).getReg(),
18966 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18968 MachineFunction::iterator MBBIter = BB;
18971 MF->insert(MBBIter, bumpMBB);
18972 MF->insert(MBBIter, mallocMBB);
18973 MF->insert(MBBIter, continueMBB);
18975 continueMBB->splice(continueMBB->begin(), BB,
18976 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18977 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18979 // Add code to the main basic block to check if the stack limit has been hit,
18980 // and if so, jump to mallocMBB otherwise to bumpMBB.
18981 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18982 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18983 .addReg(tmpSPVReg).addReg(sizeVReg);
18984 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18985 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18986 .addReg(SPLimitVReg);
18987 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18989 // bumpMBB simply decreases the stack pointer, since we know the current
18990 // stacklet has enough space.
18991 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18992 .addReg(SPLimitVReg);
18993 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18994 .addReg(SPLimitVReg);
18995 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18997 // Calls into a routine in libgcc to allocate more space from the heap.
18998 const uint32_t *RegMask =
18999 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19001 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19003 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19004 .addExternalSymbol("__morestack_allocate_stack_space")
19005 .addRegMask(RegMask)
19006 .addReg(X86::RDI, RegState::Implicit)
19007 .addReg(X86::RAX, RegState::ImplicitDefine);
19008 } else if (Is64Bit) {
19009 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19011 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19012 .addExternalSymbol("__morestack_allocate_stack_space")
19013 .addRegMask(RegMask)
19014 .addReg(X86::EDI, RegState::Implicit)
19015 .addReg(X86::EAX, RegState::ImplicitDefine);
19017 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19019 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19020 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19021 .addExternalSymbol("__morestack_allocate_stack_space")
19022 .addRegMask(RegMask)
19023 .addReg(X86::EAX, RegState::ImplicitDefine);
19027 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19030 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19031 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19032 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19034 // Set up the CFG correctly.
19035 BB->addSuccessor(bumpMBB);
19036 BB->addSuccessor(mallocMBB);
19037 mallocMBB->addSuccessor(continueMBB);
19038 bumpMBB->addSuccessor(continueMBB);
19040 // Take care of the PHI nodes.
19041 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19042 MI->getOperand(0).getReg())
19043 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19044 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19046 // Delete the original pseudo instruction.
19047 MI->eraseFromParent();
19050 return continueMBB;
19053 MachineBasicBlock *
19054 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19055 MachineBasicBlock *BB) const {
19056 DebugLoc DL = MI->getDebugLoc();
19058 assert(!Subtarget->isTargetMachO());
19060 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19062 MI->eraseFromParent(); // The pseudo instruction is gone now.
19066 MachineBasicBlock *
19067 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19068 MachineBasicBlock *BB) const {
19069 // This is pretty easy. We're taking the value that we received from
19070 // our load from the relocation, sticking it in either RDI (x86-64)
19071 // or EAX and doing an indirect call. The return value will then
19072 // be in the normal return register.
19073 MachineFunction *F = BB->getParent();
19074 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19075 DebugLoc DL = MI->getDebugLoc();
19077 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19078 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19080 // Get a register mask for the lowered call.
19081 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19082 // proper register mask.
19083 const uint32_t *RegMask =
19084 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19085 if (Subtarget->is64Bit()) {
19086 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19087 TII->get(X86::MOV64rm), X86::RDI)
19089 .addImm(0).addReg(0)
19090 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19091 MI->getOperand(3).getTargetFlags())
19093 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19094 addDirectMem(MIB, X86::RDI);
19095 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19096 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19097 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19098 TII->get(X86::MOV32rm), X86::EAX)
19100 .addImm(0).addReg(0)
19101 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19102 MI->getOperand(3).getTargetFlags())
19104 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19105 addDirectMem(MIB, X86::EAX);
19106 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19108 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19109 TII->get(X86::MOV32rm), X86::EAX)
19110 .addReg(TII->getGlobalBaseReg(F))
19111 .addImm(0).addReg(0)
19112 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19113 MI->getOperand(3).getTargetFlags())
19115 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19116 addDirectMem(MIB, X86::EAX);
19117 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19120 MI->eraseFromParent(); // The pseudo instruction is gone now.
19124 MachineBasicBlock *
19125 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19126 MachineBasicBlock *MBB) const {
19127 DebugLoc DL = MI->getDebugLoc();
19128 MachineFunction *MF = MBB->getParent();
19129 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19130 MachineRegisterInfo &MRI = MF->getRegInfo();
19132 const BasicBlock *BB = MBB->getBasicBlock();
19133 MachineFunction::iterator I = MBB;
19136 // Memory Reference
19137 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19138 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19141 unsigned MemOpndSlot = 0;
19143 unsigned CurOp = 0;
19145 DstReg = MI->getOperand(CurOp++).getReg();
19146 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19147 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19148 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19149 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19151 MemOpndSlot = CurOp;
19153 MVT PVT = getPointerTy();
19154 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19155 "Invalid Pointer Size!");
19157 // For v = setjmp(buf), we generate
19160 // buf[LabelOffset] = restoreMBB
19161 // SjLjSetup restoreMBB
19167 // v = phi(main, restore)
19170 // if base pointer being used, load it from frame
19173 MachineBasicBlock *thisMBB = MBB;
19174 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19175 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19176 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19177 MF->insert(I, mainMBB);
19178 MF->insert(I, sinkMBB);
19179 MF->push_back(restoreMBB);
19181 MachineInstrBuilder MIB;
19183 // Transfer the remainder of BB and its successor edges to sinkMBB.
19184 sinkMBB->splice(sinkMBB->begin(), MBB,
19185 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19186 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19189 unsigned PtrStoreOpc = 0;
19190 unsigned LabelReg = 0;
19191 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19192 Reloc::Model RM = MF->getTarget().getRelocationModel();
19193 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19194 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19196 // Prepare IP either in reg or imm.
19197 if (!UseImmLabel) {
19198 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19199 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19200 LabelReg = MRI.createVirtualRegister(PtrRC);
19201 if (Subtarget->is64Bit()) {
19202 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19206 .addMBB(restoreMBB)
19209 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19210 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19211 .addReg(XII->getGlobalBaseReg(MF))
19214 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19218 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19220 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19221 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19222 if (i == X86::AddrDisp)
19223 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19225 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19228 MIB.addReg(LabelReg);
19230 MIB.addMBB(restoreMBB);
19231 MIB.setMemRefs(MMOBegin, MMOEnd);
19233 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19234 .addMBB(restoreMBB);
19236 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19237 MIB.addRegMask(RegInfo->getNoPreservedMask());
19238 thisMBB->addSuccessor(mainMBB);
19239 thisMBB->addSuccessor(restoreMBB);
19243 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19244 mainMBB->addSuccessor(sinkMBB);
19247 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19248 TII->get(X86::PHI), DstReg)
19249 .addReg(mainDstReg).addMBB(mainMBB)
19250 .addReg(restoreDstReg).addMBB(restoreMBB);
19253 if (RegInfo->hasBasePointer(*MF)) {
19254 const bool Uses64BitFramePtr =
19255 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19256 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19257 X86FI->setRestoreBasePointer(MF);
19258 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19259 unsigned BasePtr = RegInfo->getBaseRegister();
19260 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19261 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19262 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19263 .setMIFlag(MachineInstr::FrameSetup);
19265 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19266 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19267 restoreMBB->addSuccessor(sinkMBB);
19269 MI->eraseFromParent();
19273 MachineBasicBlock *
19274 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19275 MachineBasicBlock *MBB) const {
19276 DebugLoc DL = MI->getDebugLoc();
19277 MachineFunction *MF = MBB->getParent();
19278 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19279 MachineRegisterInfo &MRI = MF->getRegInfo();
19281 // Memory Reference
19282 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19283 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19285 MVT PVT = getPointerTy();
19286 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19287 "Invalid Pointer Size!");
19289 const TargetRegisterClass *RC =
19290 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19291 unsigned Tmp = MRI.createVirtualRegister(RC);
19292 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19293 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19294 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19295 unsigned SP = RegInfo->getStackRegister();
19297 MachineInstrBuilder MIB;
19299 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19300 const int64_t SPOffset = 2 * PVT.getStoreSize();
19302 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19303 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19306 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19307 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19308 MIB.addOperand(MI->getOperand(i));
19309 MIB.setMemRefs(MMOBegin, MMOEnd);
19311 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19312 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19313 if (i == X86::AddrDisp)
19314 MIB.addDisp(MI->getOperand(i), LabelOffset);
19316 MIB.addOperand(MI->getOperand(i));
19318 MIB.setMemRefs(MMOBegin, MMOEnd);
19320 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19321 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19322 if (i == X86::AddrDisp)
19323 MIB.addDisp(MI->getOperand(i), SPOffset);
19325 MIB.addOperand(MI->getOperand(i));
19327 MIB.setMemRefs(MMOBegin, MMOEnd);
19329 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19331 MI->eraseFromParent();
19335 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19336 // accumulator loops. Writing back to the accumulator allows the coalescer
19337 // to remove extra copies in the loop.
19338 MachineBasicBlock *
19339 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19340 MachineBasicBlock *MBB) const {
19341 MachineOperand &AddendOp = MI->getOperand(3);
19343 // Bail out early if the addend isn't a register - we can't switch these.
19344 if (!AddendOp.isReg())
19347 MachineFunction &MF = *MBB->getParent();
19348 MachineRegisterInfo &MRI = MF.getRegInfo();
19350 // Check whether the addend is defined by a PHI:
19351 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19352 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19353 if (!AddendDef.isPHI())
19356 // Look for the following pattern:
19358 // %addend = phi [%entry, 0], [%loop, %result]
19360 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19364 // %addend = phi [%entry, 0], [%loop, %result]
19366 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19368 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19369 assert(AddendDef.getOperand(i).isReg());
19370 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19371 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19372 if (&PHISrcInst == MI) {
19373 // Found a matching instruction.
19374 unsigned NewFMAOpc = 0;
19375 switch (MI->getOpcode()) {
19376 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19377 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19378 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19379 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19380 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19381 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19382 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19383 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19384 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19385 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19386 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19387 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19388 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19389 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19390 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19391 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19392 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19393 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19394 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19395 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19397 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19398 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19399 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19400 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19401 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19402 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19403 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19404 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19405 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19406 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19407 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19408 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19409 default: llvm_unreachable("Unrecognized FMA variant.");
19412 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19413 MachineInstrBuilder MIB =
19414 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19415 .addOperand(MI->getOperand(0))
19416 .addOperand(MI->getOperand(3))
19417 .addOperand(MI->getOperand(2))
19418 .addOperand(MI->getOperand(1));
19419 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19420 MI->eraseFromParent();
19427 MachineBasicBlock *
19428 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19429 MachineBasicBlock *BB) const {
19430 switch (MI->getOpcode()) {
19431 default: llvm_unreachable("Unexpected instr type to insert");
19432 case X86::TAILJMPd64:
19433 case X86::TAILJMPr64:
19434 case X86::TAILJMPm64:
19435 case X86::TAILJMPd64_REX:
19436 case X86::TAILJMPr64_REX:
19437 case X86::TAILJMPm64_REX:
19438 llvm_unreachable("TAILJMP64 would not be touched here.");
19439 case X86::TCRETURNdi64:
19440 case X86::TCRETURNri64:
19441 case X86::TCRETURNmi64:
19443 case X86::WIN_ALLOCA:
19444 return EmitLoweredWinAlloca(MI, BB);
19445 case X86::SEG_ALLOCA_32:
19446 case X86::SEG_ALLOCA_64:
19447 return EmitLoweredSegAlloca(MI, BB);
19448 case X86::TLSCall_32:
19449 case X86::TLSCall_64:
19450 return EmitLoweredTLSCall(MI, BB);
19451 case X86::CMOV_GR8:
19452 case X86::CMOV_FR32:
19453 case X86::CMOV_FR64:
19454 case X86::CMOV_V4F32:
19455 case X86::CMOV_V2F64:
19456 case X86::CMOV_V2I64:
19457 case X86::CMOV_V8F32:
19458 case X86::CMOV_V4F64:
19459 case X86::CMOV_V4I64:
19460 case X86::CMOV_V16F32:
19461 case X86::CMOV_V8F64:
19462 case X86::CMOV_V8I64:
19463 case X86::CMOV_GR16:
19464 case X86::CMOV_GR32:
19465 case X86::CMOV_RFP32:
19466 case X86::CMOV_RFP64:
19467 case X86::CMOV_RFP80:
19468 case X86::CMOV_V8I1:
19469 case X86::CMOV_V16I1:
19470 case X86::CMOV_V32I1:
19471 case X86::CMOV_V64I1:
19472 return EmitLoweredSelect(MI, BB);
19474 case X86::FP32_TO_INT16_IN_MEM:
19475 case X86::FP32_TO_INT32_IN_MEM:
19476 case X86::FP32_TO_INT64_IN_MEM:
19477 case X86::FP64_TO_INT16_IN_MEM:
19478 case X86::FP64_TO_INT32_IN_MEM:
19479 case X86::FP64_TO_INT64_IN_MEM:
19480 case X86::FP80_TO_INT16_IN_MEM:
19481 case X86::FP80_TO_INT32_IN_MEM:
19482 case X86::FP80_TO_INT64_IN_MEM: {
19483 MachineFunction *F = BB->getParent();
19484 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19485 DebugLoc DL = MI->getDebugLoc();
19487 // Change the floating point control register to use "round towards zero"
19488 // mode when truncating to an integer value.
19489 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19490 addFrameReference(BuildMI(*BB, MI, DL,
19491 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19493 // Load the old value of the high byte of the control word...
19495 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19496 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19499 // Set the high part to be round to zero...
19500 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19503 // Reload the modified control word now...
19504 addFrameReference(BuildMI(*BB, MI, DL,
19505 TII->get(X86::FLDCW16m)), CWFrameIdx);
19507 // Restore the memory image of control word to original value
19508 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19511 // Get the X86 opcode to use.
19513 switch (MI->getOpcode()) {
19514 default: llvm_unreachable("illegal opcode!");
19515 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19516 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19517 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19518 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19519 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19520 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19521 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19522 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19523 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19527 MachineOperand &Op = MI->getOperand(0);
19529 AM.BaseType = X86AddressMode::RegBase;
19530 AM.Base.Reg = Op.getReg();
19532 AM.BaseType = X86AddressMode::FrameIndexBase;
19533 AM.Base.FrameIndex = Op.getIndex();
19535 Op = MI->getOperand(1);
19537 AM.Scale = Op.getImm();
19538 Op = MI->getOperand(2);
19540 AM.IndexReg = Op.getImm();
19541 Op = MI->getOperand(3);
19542 if (Op.isGlobal()) {
19543 AM.GV = Op.getGlobal();
19545 AM.Disp = Op.getImm();
19547 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19548 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19550 // Reload the original control word now.
19551 addFrameReference(BuildMI(*BB, MI, DL,
19552 TII->get(X86::FLDCW16m)), CWFrameIdx);
19554 MI->eraseFromParent(); // The pseudo instruction is gone now.
19557 // String/text processing lowering.
19558 case X86::PCMPISTRM128REG:
19559 case X86::VPCMPISTRM128REG:
19560 case X86::PCMPISTRM128MEM:
19561 case X86::VPCMPISTRM128MEM:
19562 case X86::PCMPESTRM128REG:
19563 case X86::VPCMPESTRM128REG:
19564 case X86::PCMPESTRM128MEM:
19565 case X86::VPCMPESTRM128MEM:
19566 assert(Subtarget->hasSSE42() &&
19567 "Target must have SSE4.2 or AVX features enabled");
19568 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19570 // String/text processing lowering.
19571 case X86::PCMPISTRIREG:
19572 case X86::VPCMPISTRIREG:
19573 case X86::PCMPISTRIMEM:
19574 case X86::VPCMPISTRIMEM:
19575 case X86::PCMPESTRIREG:
19576 case X86::VPCMPESTRIREG:
19577 case X86::PCMPESTRIMEM:
19578 case X86::VPCMPESTRIMEM:
19579 assert(Subtarget->hasSSE42() &&
19580 "Target must have SSE4.2 or AVX features enabled");
19581 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19583 // Thread synchronization.
19585 return EmitMonitor(MI, BB, Subtarget);
19589 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19591 case X86::VASTART_SAVE_XMM_REGS:
19592 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19594 case X86::VAARG_64:
19595 return EmitVAARG64WithCustomInserter(MI, BB);
19597 case X86::EH_SjLj_SetJmp32:
19598 case X86::EH_SjLj_SetJmp64:
19599 return emitEHSjLjSetJmp(MI, BB);
19601 case X86::EH_SjLj_LongJmp32:
19602 case X86::EH_SjLj_LongJmp64:
19603 return emitEHSjLjLongJmp(MI, BB);
19605 case TargetOpcode::STATEPOINT:
19606 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19607 // this point in the process. We diverge later.
19608 return emitPatchPoint(MI, BB);
19610 case TargetOpcode::STACKMAP:
19611 case TargetOpcode::PATCHPOINT:
19612 return emitPatchPoint(MI, BB);
19614 case X86::VFMADDPDr213r:
19615 case X86::VFMADDPSr213r:
19616 case X86::VFMADDSDr213r:
19617 case X86::VFMADDSSr213r:
19618 case X86::VFMSUBPDr213r:
19619 case X86::VFMSUBPSr213r:
19620 case X86::VFMSUBSDr213r:
19621 case X86::VFMSUBSSr213r:
19622 case X86::VFNMADDPDr213r:
19623 case X86::VFNMADDPSr213r:
19624 case X86::VFNMADDSDr213r:
19625 case X86::VFNMADDSSr213r:
19626 case X86::VFNMSUBPDr213r:
19627 case X86::VFNMSUBPSr213r:
19628 case X86::VFNMSUBSDr213r:
19629 case X86::VFNMSUBSSr213r:
19630 case X86::VFMADDSUBPDr213r:
19631 case X86::VFMADDSUBPSr213r:
19632 case X86::VFMSUBADDPDr213r:
19633 case X86::VFMSUBADDPSr213r:
19634 case X86::VFMADDPDr213rY:
19635 case X86::VFMADDPSr213rY:
19636 case X86::VFMSUBPDr213rY:
19637 case X86::VFMSUBPSr213rY:
19638 case X86::VFNMADDPDr213rY:
19639 case X86::VFNMADDPSr213rY:
19640 case X86::VFNMSUBPDr213rY:
19641 case X86::VFNMSUBPSr213rY:
19642 case X86::VFMADDSUBPDr213rY:
19643 case X86::VFMADDSUBPSr213rY:
19644 case X86::VFMSUBADDPDr213rY:
19645 case X86::VFMSUBADDPSr213rY:
19646 return emitFMA3Instr(MI, BB);
19650 //===----------------------------------------------------------------------===//
19651 // X86 Optimization Hooks
19652 //===----------------------------------------------------------------------===//
19654 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19657 const SelectionDAG &DAG,
19658 unsigned Depth) const {
19659 unsigned BitWidth = KnownZero.getBitWidth();
19660 unsigned Opc = Op.getOpcode();
19661 assert((Opc >= ISD::BUILTIN_OP_END ||
19662 Opc == ISD::INTRINSIC_WO_CHAIN ||
19663 Opc == ISD::INTRINSIC_W_CHAIN ||
19664 Opc == ISD::INTRINSIC_VOID) &&
19665 "Should use MaskedValueIsZero if you don't know whether Op"
19666 " is a target node!");
19668 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19682 // These nodes' second result is a boolean.
19683 if (Op.getResNo() == 0)
19686 case X86ISD::SETCC:
19687 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19689 case ISD::INTRINSIC_WO_CHAIN: {
19690 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19691 unsigned NumLoBits = 0;
19694 case Intrinsic::x86_sse_movmsk_ps:
19695 case Intrinsic::x86_avx_movmsk_ps_256:
19696 case Intrinsic::x86_sse2_movmsk_pd:
19697 case Intrinsic::x86_avx_movmsk_pd_256:
19698 case Intrinsic::x86_mmx_pmovmskb:
19699 case Intrinsic::x86_sse2_pmovmskb_128:
19700 case Intrinsic::x86_avx2_pmovmskb: {
19701 // High bits of movmskp{s|d}, pmovmskb are known zero.
19703 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19704 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19705 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19706 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19707 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19708 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19709 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19710 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19712 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19721 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19723 const SelectionDAG &,
19724 unsigned Depth) const {
19725 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19726 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19727 return Op.getValueType().getScalarType().getSizeInBits();
19733 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19734 /// node is a GlobalAddress + offset.
19735 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19736 const GlobalValue* &GA,
19737 int64_t &Offset) const {
19738 if (N->getOpcode() == X86ISD::Wrapper) {
19739 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19740 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19741 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19745 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19748 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19749 /// same as extracting the high 128-bit part of 256-bit vector and then
19750 /// inserting the result into the low part of a new 256-bit vector
19751 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19752 EVT VT = SVOp->getValueType(0);
19753 unsigned NumElems = VT.getVectorNumElements();
19755 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19756 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19757 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19758 SVOp->getMaskElt(j) >= 0)
19764 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19765 /// same as extracting the low 128-bit part of 256-bit vector and then
19766 /// inserting the result into the high part of a new 256-bit vector
19767 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19768 EVT VT = SVOp->getValueType(0);
19769 unsigned NumElems = VT.getVectorNumElements();
19771 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19772 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19773 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19774 SVOp->getMaskElt(j) >= 0)
19780 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19781 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19782 TargetLowering::DAGCombinerInfo &DCI,
19783 const X86Subtarget* Subtarget) {
19785 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19786 SDValue V1 = SVOp->getOperand(0);
19787 SDValue V2 = SVOp->getOperand(1);
19788 EVT VT = SVOp->getValueType(0);
19789 unsigned NumElems = VT.getVectorNumElements();
19791 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19792 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19796 // V UNDEF BUILD_VECTOR UNDEF
19798 // CONCAT_VECTOR CONCAT_VECTOR
19801 // RESULT: V + zero extended
19803 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19804 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19805 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19808 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19811 // To match the shuffle mask, the first half of the mask should
19812 // be exactly the first vector, and all the rest a splat with the
19813 // first element of the second one.
19814 for (unsigned i = 0; i != NumElems/2; ++i)
19815 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19816 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19819 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19820 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19821 if (Ld->hasNUsesOfValue(1, 0)) {
19822 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19823 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19825 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19827 Ld->getPointerInfo(),
19828 Ld->getAlignment(),
19829 false/*isVolatile*/, true/*ReadMem*/,
19830 false/*WriteMem*/);
19832 // Make sure the newly-created LOAD is in the same position as Ld in
19833 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19834 // and update uses of Ld's output chain to use the TokenFactor.
19835 if (Ld->hasAnyUseOfValue(1)) {
19836 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19837 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19838 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19839 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19840 SDValue(ResNode.getNode(), 1));
19843 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19847 // Emit a zeroed vector and insert the desired subvector on its
19849 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19850 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19851 return DCI.CombineTo(N, InsV);
19854 //===--------------------------------------------------------------------===//
19855 // Combine some shuffles into subvector extracts and inserts:
19858 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19859 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19860 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19861 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19862 return DCI.CombineTo(N, InsV);
19865 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19866 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19867 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19868 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19869 return DCI.CombineTo(N, InsV);
19875 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19878 /// This is the leaf of the recursive combinine below. When we have found some
19879 /// chain of single-use x86 shuffle instructions and accumulated the combined
19880 /// shuffle mask represented by them, this will try to pattern match that mask
19881 /// into either a single instruction if there is a special purpose instruction
19882 /// for this operation, or into a PSHUFB instruction which is a fully general
19883 /// instruction but should only be used to replace chains over a certain depth.
19884 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19885 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19886 TargetLowering::DAGCombinerInfo &DCI,
19887 const X86Subtarget *Subtarget) {
19888 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19890 // Find the operand that enters the chain. Note that multiple uses are OK
19891 // here, we're not going to remove the operand we find.
19892 SDValue Input = Op.getOperand(0);
19893 while (Input.getOpcode() == ISD::BITCAST)
19894 Input = Input.getOperand(0);
19896 MVT VT = Input.getSimpleValueType();
19897 MVT RootVT = Root.getSimpleValueType();
19900 // Just remove no-op shuffle masks.
19901 if (Mask.size() == 1) {
19902 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19907 // Use the float domain if the operand type is a floating point type.
19908 bool FloatDomain = VT.isFloatingPoint();
19910 // For floating point shuffles, we don't have free copies in the shuffle
19911 // instructions or the ability to load as part of the instruction, so
19912 // canonicalize their shuffles to UNPCK or MOV variants.
19914 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19915 // vectors because it can have a load folded into it that UNPCK cannot. This
19916 // doesn't preclude something switching to the shorter encoding post-RA.
19918 // FIXME: Should teach these routines about AVX vector widths.
19919 if (FloatDomain && VT.getSizeInBits() == 128) {
19920 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
19921 bool Lo = Mask.equals({0, 0});
19924 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19925 // is no slower than UNPCKLPD but has the option to fold the input operand
19926 // into even an unaligned memory load.
19927 if (Lo && Subtarget->hasSSE3()) {
19928 Shuffle = X86ISD::MOVDDUP;
19929 ShuffleVT = MVT::v2f64;
19931 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19932 // than the UNPCK variants.
19933 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19934 ShuffleVT = MVT::v4f32;
19936 if (Depth == 1 && Root->getOpcode() == Shuffle)
19937 return false; // Nothing to do!
19938 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19939 DCI.AddToWorklist(Op.getNode());
19940 if (Shuffle == X86ISD::MOVDDUP)
19941 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19943 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19944 DCI.AddToWorklist(Op.getNode());
19945 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19949 if (Subtarget->hasSSE3() &&
19950 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
19951 bool Lo = Mask.equals({0, 0, 2, 2});
19952 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19953 MVT ShuffleVT = MVT::v4f32;
19954 if (Depth == 1 && Root->getOpcode() == Shuffle)
19955 return false; // Nothing to do!
19956 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19957 DCI.AddToWorklist(Op.getNode());
19958 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19959 DCI.AddToWorklist(Op.getNode());
19960 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19964 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
19965 bool Lo = Mask.equals({0, 0, 1, 1});
19966 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19967 MVT ShuffleVT = MVT::v4f32;
19968 if (Depth == 1 && Root->getOpcode() == Shuffle)
19969 return false; // Nothing to do!
19970 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19971 DCI.AddToWorklist(Op.getNode());
19972 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19973 DCI.AddToWorklist(Op.getNode());
19974 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19980 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19981 // variants as none of these have single-instruction variants that are
19982 // superior to the UNPCK formulation.
19983 if (!FloatDomain && VT.getSizeInBits() == 128 &&
19984 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
19985 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
19986 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
19988 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
19989 bool Lo = Mask[0] == 0;
19990 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19991 if (Depth == 1 && Root->getOpcode() == Shuffle)
19992 return false; // Nothing to do!
19994 switch (Mask.size()) {
19996 ShuffleVT = MVT::v8i16;
19999 ShuffleVT = MVT::v16i8;
20002 llvm_unreachable("Impossible mask size!");
20004 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20005 DCI.AddToWorklist(Op.getNode());
20006 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20007 DCI.AddToWorklist(Op.getNode());
20008 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20013 // Don't try to re-form single instruction chains under any circumstances now
20014 // that we've done encoding canonicalization for them.
20018 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20019 // can replace them with a single PSHUFB instruction profitably. Intel's
20020 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20021 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20022 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20023 SmallVector<SDValue, 16> PSHUFBMask;
20024 int NumBytes = VT.getSizeInBits() / 8;
20025 int Ratio = NumBytes / Mask.size();
20026 for (int i = 0; i < NumBytes; ++i) {
20027 if (Mask[i / Ratio] == SM_SentinelUndef) {
20028 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20031 int M = Mask[i / Ratio] != SM_SentinelZero
20032 ? Ratio * Mask[i / Ratio] + i % Ratio
20034 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20036 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20037 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
20038 DCI.AddToWorklist(Op.getNode());
20039 SDValue PSHUFBMaskOp =
20040 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20041 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20042 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20043 DCI.AddToWorklist(Op.getNode());
20044 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20049 // Failed to find any combines.
20053 /// \brief Fully generic combining of x86 shuffle instructions.
20055 /// This should be the last combine run over the x86 shuffle instructions. Once
20056 /// they have been fully optimized, this will recursively consider all chains
20057 /// of single-use shuffle instructions, build a generic model of the cumulative
20058 /// shuffle operation, and check for simpler instructions which implement this
20059 /// operation. We use this primarily for two purposes:
20061 /// 1) Collapse generic shuffles to specialized single instructions when
20062 /// equivalent. In most cases, this is just an encoding size win, but
20063 /// sometimes we will collapse multiple generic shuffles into a single
20064 /// special-purpose shuffle.
20065 /// 2) Look for sequences of shuffle instructions with 3 or more total
20066 /// instructions, and replace them with the slightly more expensive SSSE3
20067 /// PSHUFB instruction if available. We do this as the last combining step
20068 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20069 /// a suitable short sequence of other instructions. The PHUFB will either
20070 /// use a register or have to read from memory and so is slightly (but only
20071 /// slightly) more expensive than the other shuffle instructions.
20073 /// Because this is inherently a quadratic operation (for each shuffle in
20074 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20075 /// This should never be an issue in practice as the shuffle lowering doesn't
20076 /// produce sequences of more than 8 instructions.
20078 /// FIXME: We will currently miss some cases where the redundant shuffling
20079 /// would simplify under the threshold for PSHUFB formation because of
20080 /// combine-ordering. To fix this, we should do the redundant instruction
20081 /// combining in this recursive walk.
20082 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20083 ArrayRef<int> RootMask,
20084 int Depth, bool HasPSHUFB,
20086 TargetLowering::DAGCombinerInfo &DCI,
20087 const X86Subtarget *Subtarget) {
20088 // Bound the depth of our recursive combine because this is ultimately
20089 // quadratic in nature.
20093 // Directly rip through bitcasts to find the underlying operand.
20094 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20095 Op = Op.getOperand(0);
20097 MVT VT = Op.getSimpleValueType();
20098 if (!VT.isVector())
20099 return false; // Bail if we hit a non-vector.
20101 assert(Root.getSimpleValueType().isVector() &&
20102 "Shuffles operate on vector types!");
20103 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20104 "Can only combine shuffles of the same vector register size.");
20106 if (!isTargetShuffle(Op.getOpcode()))
20108 SmallVector<int, 16> OpMask;
20110 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20111 // We only can combine unary shuffles which we can decode the mask for.
20112 if (!HaveMask || !IsUnary)
20115 assert(VT.getVectorNumElements() == OpMask.size() &&
20116 "Different mask size from vector size!");
20117 assert(((RootMask.size() > OpMask.size() &&
20118 RootMask.size() % OpMask.size() == 0) ||
20119 (OpMask.size() > RootMask.size() &&
20120 OpMask.size() % RootMask.size() == 0) ||
20121 OpMask.size() == RootMask.size()) &&
20122 "The smaller number of elements must divide the larger.");
20123 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20124 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20125 assert(((RootRatio == 1 && OpRatio == 1) ||
20126 (RootRatio == 1) != (OpRatio == 1)) &&
20127 "Must not have a ratio for both incoming and op masks!");
20129 SmallVector<int, 16> Mask;
20130 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20132 // Merge this shuffle operation's mask into our accumulated mask. Note that
20133 // this shuffle's mask will be the first applied to the input, followed by the
20134 // root mask to get us all the way to the root value arrangement. The reason
20135 // for this order is that we are recursing up the operation chain.
20136 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20137 int RootIdx = i / RootRatio;
20138 if (RootMask[RootIdx] < 0) {
20139 // This is a zero or undef lane, we're done.
20140 Mask.push_back(RootMask[RootIdx]);
20144 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20145 int OpIdx = RootMaskedIdx / OpRatio;
20146 if (OpMask[OpIdx] < 0) {
20147 // The incoming lanes are zero or undef, it doesn't matter which ones we
20149 Mask.push_back(OpMask[OpIdx]);
20153 // Ok, we have non-zero lanes, map them through.
20154 Mask.push_back(OpMask[OpIdx] * OpRatio +
20155 RootMaskedIdx % OpRatio);
20158 // See if we can recurse into the operand to combine more things.
20159 switch (Op.getOpcode()) {
20160 case X86ISD::PSHUFB:
20162 case X86ISD::PSHUFD:
20163 case X86ISD::PSHUFHW:
20164 case X86ISD::PSHUFLW:
20165 if (Op.getOperand(0).hasOneUse() &&
20166 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20167 HasPSHUFB, DAG, DCI, Subtarget))
20171 case X86ISD::UNPCKL:
20172 case X86ISD::UNPCKH:
20173 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20174 // We can't check for single use, we have to check that this shuffle is the only user.
20175 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20176 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20177 HasPSHUFB, DAG, DCI, Subtarget))
20182 // Minor canonicalization of the accumulated shuffle mask to make it easier
20183 // to match below. All this does is detect masks with squential pairs of
20184 // elements, and shrink them to the half-width mask. It does this in a loop
20185 // so it will reduce the size of the mask to the minimal width mask which
20186 // performs an equivalent shuffle.
20187 SmallVector<int, 16> WidenedMask;
20188 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20189 Mask = std::move(WidenedMask);
20190 WidenedMask.clear();
20193 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20197 /// \brief Get the PSHUF-style mask from PSHUF node.
20199 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20200 /// PSHUF-style masks that can be reused with such instructions.
20201 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20202 MVT VT = N.getSimpleValueType();
20203 SmallVector<int, 4> Mask;
20205 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20209 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20210 // matter. Check that the upper masks are repeats and remove them.
20211 if (VT.getSizeInBits() > 128) {
20212 int LaneElts = 128 / VT.getScalarSizeInBits();
20214 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20215 for (int j = 0; j < LaneElts; ++j)
20216 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
20217 "Mask doesn't repeat in high 128-bit lanes!");
20219 Mask.resize(LaneElts);
20222 switch (N.getOpcode()) {
20223 case X86ISD::PSHUFD:
20225 case X86ISD::PSHUFLW:
20228 case X86ISD::PSHUFHW:
20229 Mask.erase(Mask.begin(), Mask.begin() + 4);
20230 for (int &M : Mask)
20234 llvm_unreachable("No valid shuffle instruction found!");
20238 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20240 /// We walk up the chain and look for a combinable shuffle, skipping over
20241 /// shuffles that we could hoist this shuffle's transformation past without
20242 /// altering anything.
20244 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20246 TargetLowering::DAGCombinerInfo &DCI) {
20247 assert(N.getOpcode() == X86ISD::PSHUFD &&
20248 "Called with something other than an x86 128-bit half shuffle!");
20251 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20252 // of the shuffles in the chain so that we can form a fresh chain to replace
20254 SmallVector<SDValue, 8> Chain;
20255 SDValue V = N.getOperand(0);
20256 for (; V.hasOneUse(); V = V.getOperand(0)) {
20257 switch (V.getOpcode()) {
20259 return SDValue(); // Nothing combined!
20262 // Skip bitcasts as we always know the type for the target specific
20266 case X86ISD::PSHUFD:
20267 // Found another dword shuffle.
20270 case X86ISD::PSHUFLW:
20271 // Check that the low words (being shuffled) are the identity in the
20272 // dword shuffle, and the high words are self-contained.
20273 if (Mask[0] != 0 || Mask[1] != 1 ||
20274 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20277 Chain.push_back(V);
20280 case X86ISD::PSHUFHW:
20281 // Check that the high words (being shuffled) are the identity in the
20282 // dword shuffle, and the low words are self-contained.
20283 if (Mask[2] != 2 || Mask[3] != 3 ||
20284 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20287 Chain.push_back(V);
20290 case X86ISD::UNPCKL:
20291 case X86ISD::UNPCKH:
20292 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20293 // shuffle into a preceding word shuffle.
20294 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20295 V.getSimpleValueType().getScalarType() != MVT::i16)
20298 // Search for a half-shuffle which we can combine with.
20299 unsigned CombineOp =
20300 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20301 if (V.getOperand(0) != V.getOperand(1) ||
20302 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20304 Chain.push_back(V);
20305 V = V.getOperand(0);
20307 switch (V.getOpcode()) {
20309 return SDValue(); // Nothing to combine.
20311 case X86ISD::PSHUFLW:
20312 case X86ISD::PSHUFHW:
20313 if (V.getOpcode() == CombineOp)
20316 Chain.push_back(V);
20320 V = V.getOperand(0);
20324 } while (V.hasOneUse());
20327 // Break out of the loop if we break out of the switch.
20331 if (!V.hasOneUse())
20332 // We fell out of the loop without finding a viable combining instruction.
20335 // Merge this node's mask and our incoming mask.
20336 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20337 for (int &M : Mask)
20339 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20340 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20342 // Rebuild the chain around this new shuffle.
20343 while (!Chain.empty()) {
20344 SDValue W = Chain.pop_back_val();
20346 if (V.getValueType() != W.getOperand(0).getValueType())
20347 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20349 switch (W.getOpcode()) {
20351 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20353 case X86ISD::UNPCKL:
20354 case X86ISD::UNPCKH:
20355 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20358 case X86ISD::PSHUFD:
20359 case X86ISD::PSHUFLW:
20360 case X86ISD::PSHUFHW:
20361 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20365 if (V.getValueType() != N.getValueType())
20366 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20368 // Return the new chain to replace N.
20372 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20374 /// We walk up the chain, skipping shuffles of the other half and looking
20375 /// through shuffles which switch halves trying to find a shuffle of the same
20376 /// pair of dwords.
20377 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20379 TargetLowering::DAGCombinerInfo &DCI) {
20381 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20382 "Called with something other than an x86 128-bit half shuffle!");
20384 unsigned CombineOpcode = N.getOpcode();
20386 // Walk up a single-use chain looking for a combinable shuffle.
20387 SDValue V = N.getOperand(0);
20388 for (; V.hasOneUse(); V = V.getOperand(0)) {
20389 switch (V.getOpcode()) {
20391 return false; // Nothing combined!
20394 // Skip bitcasts as we always know the type for the target specific
20398 case X86ISD::PSHUFLW:
20399 case X86ISD::PSHUFHW:
20400 if (V.getOpcode() == CombineOpcode)
20403 // Other-half shuffles are no-ops.
20406 // Break out of the loop if we break out of the switch.
20410 if (!V.hasOneUse())
20411 // We fell out of the loop without finding a viable combining instruction.
20414 // Combine away the bottom node as its shuffle will be accumulated into
20415 // a preceding shuffle.
20416 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20418 // Record the old value.
20421 // Merge this node's mask and our incoming mask (adjusted to account for all
20422 // the pshufd instructions encountered).
20423 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20424 for (int &M : Mask)
20426 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20427 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20429 // Check that the shuffles didn't cancel each other out. If not, we need to
20430 // combine to the new one.
20432 // Replace the combinable shuffle with the combined one, updating all users
20433 // so that we re-evaluate the chain here.
20434 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20439 /// \brief Try to combine x86 target specific shuffles.
20440 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20441 TargetLowering::DAGCombinerInfo &DCI,
20442 const X86Subtarget *Subtarget) {
20444 MVT VT = N.getSimpleValueType();
20445 SmallVector<int, 4> Mask;
20447 switch (N.getOpcode()) {
20448 case X86ISD::PSHUFD:
20449 case X86ISD::PSHUFLW:
20450 case X86ISD::PSHUFHW:
20451 Mask = getPSHUFShuffleMask(N);
20452 assert(Mask.size() == 4);
20458 // Nuke no-op shuffles that show up after combining.
20459 if (isNoopShuffleMask(Mask))
20460 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20462 // Look for simplifications involving one or two shuffle instructions.
20463 SDValue V = N.getOperand(0);
20464 switch (N.getOpcode()) {
20467 case X86ISD::PSHUFLW:
20468 case X86ISD::PSHUFHW:
20469 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20471 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20472 return SDValue(); // We combined away this shuffle, so we're done.
20474 // See if this reduces to a PSHUFD which is no more expensive and can
20475 // combine with more operations. Note that it has to at least flip the
20476 // dwords as otherwise it would have been removed as a no-op.
20477 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20478 int DMask[] = {0, 1, 2, 3};
20479 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20480 DMask[DOffset + 0] = DOffset + 1;
20481 DMask[DOffset + 1] = DOffset + 0;
20482 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20483 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20484 DCI.AddToWorklist(V.getNode());
20485 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20486 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20487 DCI.AddToWorklist(V.getNode());
20488 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20491 // Look for shuffle patterns which can be implemented as a single unpack.
20492 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20493 // only works when we have a PSHUFD followed by two half-shuffles.
20494 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20495 (V.getOpcode() == X86ISD::PSHUFLW ||
20496 V.getOpcode() == X86ISD::PSHUFHW) &&
20497 V.getOpcode() != N.getOpcode() &&
20499 SDValue D = V.getOperand(0);
20500 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20501 D = D.getOperand(0);
20502 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20503 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20504 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20505 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20506 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20508 for (int i = 0; i < 4; ++i) {
20509 WordMask[i + NOffset] = Mask[i] + NOffset;
20510 WordMask[i + VOffset] = VMask[i] + VOffset;
20512 // Map the word mask through the DWord mask.
20514 for (int i = 0; i < 8; ++i)
20515 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20516 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20517 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20518 // We can replace all three shuffles with an unpack.
20519 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20520 DCI.AddToWorklist(V.getNode());
20521 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20530 case X86ISD::PSHUFD:
20531 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20540 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20542 /// We combine this directly on the abstract vector shuffle nodes so it is
20543 /// easier to generically match. We also insert dummy vector shuffle nodes for
20544 /// the operands which explicitly discard the lanes which are unused by this
20545 /// operation to try to flow through the rest of the combiner the fact that
20546 /// they're unused.
20547 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20549 EVT VT = N->getValueType(0);
20551 // We only handle target-independent shuffles.
20552 // FIXME: It would be easy and harmless to use the target shuffle mask
20553 // extraction tool to support more.
20554 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20557 auto *SVN = cast<ShuffleVectorSDNode>(N);
20558 ArrayRef<int> Mask = SVN->getMask();
20559 SDValue V1 = N->getOperand(0);
20560 SDValue V2 = N->getOperand(1);
20562 // We require the first shuffle operand to be the SUB node, and the second to
20563 // be the ADD node.
20564 // FIXME: We should support the commuted patterns.
20565 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20568 // If there are other uses of these operations we can't fold them.
20569 if (!V1->hasOneUse() || !V2->hasOneUse())
20572 // Ensure that both operations have the same operands. Note that we can
20573 // commute the FADD operands.
20574 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20575 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20576 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20579 // We're looking for blends between FADD and FSUB nodes. We insist on these
20580 // nodes being lined up in a specific expected pattern.
20581 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20582 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20583 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20586 // Only specific types are legal at this point, assert so we notice if and
20587 // when these change.
20588 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20589 VT == MVT::v4f64) &&
20590 "Unknown vector type encountered!");
20592 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20595 /// PerformShuffleCombine - Performs several different shuffle combines.
20596 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20597 TargetLowering::DAGCombinerInfo &DCI,
20598 const X86Subtarget *Subtarget) {
20600 SDValue N0 = N->getOperand(0);
20601 SDValue N1 = N->getOperand(1);
20602 EVT VT = N->getValueType(0);
20604 // Don't create instructions with illegal types after legalize types has run.
20605 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20606 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20609 // If we have legalized the vector types, look for blends of FADD and FSUB
20610 // nodes that we can fuse into an ADDSUB node.
20611 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20612 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20615 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20616 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20617 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20618 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20620 // During Type Legalization, when promoting illegal vector types,
20621 // the backend might introduce new shuffle dag nodes and bitcasts.
20623 // This code performs the following transformation:
20624 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20625 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20627 // We do this only if both the bitcast and the BINOP dag nodes have
20628 // one use. Also, perform this transformation only if the new binary
20629 // operation is legal. This is to avoid introducing dag nodes that
20630 // potentially need to be further expanded (or custom lowered) into a
20631 // less optimal sequence of dag nodes.
20632 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20633 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20634 N0.getOpcode() == ISD::BITCAST) {
20635 SDValue BC0 = N0.getOperand(0);
20636 EVT SVT = BC0.getValueType();
20637 unsigned Opcode = BC0.getOpcode();
20638 unsigned NumElts = VT.getVectorNumElements();
20640 if (BC0.hasOneUse() && SVT.isVector() &&
20641 SVT.getVectorNumElements() * 2 == NumElts &&
20642 TLI.isOperationLegal(Opcode, VT)) {
20643 bool CanFold = false;
20655 unsigned SVTNumElts = SVT.getVectorNumElements();
20656 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20657 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20658 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20659 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20660 CanFold = SVOp->getMaskElt(i) < 0;
20663 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20664 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20665 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20666 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20671 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20672 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20673 // consecutive, non-overlapping, and in the right order.
20674 SmallVector<SDValue, 16> Elts;
20675 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20676 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20678 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20682 if (isTargetShuffle(N->getOpcode())) {
20684 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20685 if (Shuffle.getNode())
20688 // Try recursively combining arbitrary sequences of x86 shuffle
20689 // instructions into higher-order shuffles. We do this after combining
20690 // specific PSHUF instruction sequences into their minimal form so that we
20691 // can evaluate how many specialized shuffle instructions are involved in
20692 // a particular chain.
20693 SmallVector<int, 1> NonceMask; // Just a placeholder.
20694 NonceMask.push_back(0);
20695 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20696 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20698 return SDValue(); // This routine will use CombineTo to replace N.
20704 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20705 /// specific shuffle of a load can be folded into a single element load.
20706 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20707 /// shuffles have been custom lowered so we need to handle those here.
20708 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20709 TargetLowering::DAGCombinerInfo &DCI) {
20710 if (DCI.isBeforeLegalizeOps())
20713 SDValue InVec = N->getOperand(0);
20714 SDValue EltNo = N->getOperand(1);
20716 if (!isa<ConstantSDNode>(EltNo))
20719 EVT OriginalVT = InVec.getValueType();
20721 if (InVec.getOpcode() == ISD::BITCAST) {
20722 // Don't duplicate a load with other uses.
20723 if (!InVec.hasOneUse())
20725 EVT BCVT = InVec.getOperand(0).getValueType();
20726 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20728 InVec = InVec.getOperand(0);
20731 EVT CurrentVT = InVec.getValueType();
20733 if (!isTargetShuffle(InVec.getOpcode()))
20736 // Don't duplicate a load with other uses.
20737 if (!InVec.hasOneUse())
20740 SmallVector<int, 16> ShuffleMask;
20742 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20743 ShuffleMask, UnaryShuffle))
20746 // Select the input vector, guarding against out of range extract vector.
20747 unsigned NumElems = CurrentVT.getVectorNumElements();
20748 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20749 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20750 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20751 : InVec.getOperand(1);
20753 // If inputs to shuffle are the same for both ops, then allow 2 uses
20754 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20755 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20757 if (LdNode.getOpcode() == ISD::BITCAST) {
20758 // Don't duplicate a load with other uses.
20759 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20762 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20763 LdNode = LdNode.getOperand(0);
20766 if (!ISD::isNormalLoad(LdNode.getNode()))
20769 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20771 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20774 EVT EltVT = N->getValueType(0);
20775 // If there's a bitcast before the shuffle, check if the load type and
20776 // alignment is valid.
20777 unsigned Align = LN0->getAlignment();
20778 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20779 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20780 EltVT.getTypeForEVT(*DAG.getContext()));
20782 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20785 // All checks match so transform back to vector_shuffle so that DAG combiner
20786 // can finish the job
20789 // Create shuffle node taking into account the case that its a unary shuffle
20790 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20791 : InVec.getOperand(1);
20792 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20793 InVec.getOperand(0), Shuffle,
20795 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20796 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20800 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20801 /// special and don't usually play with other vector types, it's better to
20802 /// handle them early to be sure we emit efficient code by avoiding
20803 /// store-load conversions.
20804 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20805 if (N->getValueType(0) != MVT::x86mmx ||
20806 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
20807 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20810 SDValue V = N->getOperand(0);
20811 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20812 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20813 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20814 N->getValueType(0), V.getOperand(0));
20819 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20820 /// generation and convert it from being a bunch of shuffles and extracts
20821 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20822 /// storing the value and loading scalars back, while for x64 we should
20823 /// use 64-bit extracts and shifts.
20824 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20825 TargetLowering::DAGCombinerInfo &DCI) {
20826 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20827 if (NewOp.getNode())
20830 SDValue InputVector = N->getOperand(0);
20832 // Detect mmx to i32 conversion through a v2i32 elt extract.
20833 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20834 N->getValueType(0) == MVT::i32 &&
20835 InputVector.getValueType() == MVT::v2i32) {
20837 // The bitcast source is a direct mmx result.
20838 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20839 if (MMXSrc.getValueType() == MVT::x86mmx)
20840 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20841 N->getValueType(0),
20842 InputVector.getNode()->getOperand(0));
20844 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20845 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20846 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20847 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20848 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20849 MMXSrcOp.getValueType() == MVT::v1i64 &&
20850 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20851 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20852 N->getValueType(0),
20853 MMXSrcOp.getOperand(0));
20856 // Only operate on vectors of 4 elements, where the alternative shuffling
20857 // gets to be more expensive.
20858 if (InputVector.getValueType() != MVT::v4i32)
20861 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20862 // single use which is a sign-extend or zero-extend, and all elements are
20864 SmallVector<SDNode *, 4> Uses;
20865 unsigned ExtractedElements = 0;
20866 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20867 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20868 if (UI.getUse().getResNo() != InputVector.getResNo())
20871 SDNode *Extract = *UI;
20872 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20875 if (Extract->getValueType(0) != MVT::i32)
20877 if (!Extract->hasOneUse())
20879 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20880 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20882 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20885 // Record which element was extracted.
20886 ExtractedElements |=
20887 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20889 Uses.push_back(Extract);
20892 // If not all the elements were used, this may not be worthwhile.
20893 if (ExtractedElements != 15)
20896 // Ok, we've now decided to do the transformation.
20897 // If 64-bit shifts are legal, use the extract-shift sequence,
20898 // otherwise bounce the vector off the cache.
20899 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20901 SDLoc dl(InputVector);
20903 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20904 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20905 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20906 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20907 DAG.getConstant(0, dl, VecIdxTy));
20908 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20909 DAG.getConstant(1, dl, VecIdxTy));
20911 SDValue ShAmt = DAG.getConstant(32, dl,
20912 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20913 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20914 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20915 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20916 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20917 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20918 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20920 // Store the value to a temporary stack slot.
20921 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20922 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20923 MachinePointerInfo(), false, false, 0);
20925 EVT ElementType = InputVector.getValueType().getVectorElementType();
20926 unsigned EltSize = ElementType.getSizeInBits() / 8;
20928 // Replace each use (extract) with a load of the appropriate element.
20929 for (unsigned i = 0; i < 4; ++i) {
20930 uint64_t Offset = EltSize * i;
20931 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
20933 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20934 StackPtr, OffsetVal);
20936 // Load the scalar.
20937 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20938 ScalarAddr, MachinePointerInfo(),
20939 false, false, false, 0);
20944 // Replace the extracts
20945 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20946 UE = Uses.end(); UI != UE; ++UI) {
20947 SDNode *Extract = *UI;
20949 SDValue Idx = Extract->getOperand(1);
20950 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20951 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20954 // The replacement was made in place; don't return anything.
20958 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20959 static std::pair<unsigned, bool>
20960 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20961 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20962 if (!VT.isVector())
20963 return std::make_pair(0, false);
20965 bool NeedSplit = false;
20966 switch (VT.getSimpleVT().SimpleTy) {
20967 default: return std::make_pair(0, false);
20970 if (!Subtarget->hasVLX())
20971 return std::make_pair(0, false);
20975 if (!Subtarget->hasBWI())
20976 return std::make_pair(0, false);
20980 if (!Subtarget->hasAVX512())
20981 return std::make_pair(0, false);
20986 if (!Subtarget->hasAVX2())
20988 if (!Subtarget->hasAVX())
20989 return std::make_pair(0, false);
20994 if (!Subtarget->hasSSE2())
20995 return std::make_pair(0, false);
20998 // SSE2 has only a small subset of the operations.
20999 bool hasUnsigned = Subtarget->hasSSE41() ||
21000 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21001 bool hasSigned = Subtarget->hasSSE41() ||
21002 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21004 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21007 // Check for x CC y ? x : y.
21008 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21009 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21014 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21017 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21020 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21023 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21025 // Check for x CC y ? y : x -- a min/max with reversed arms.
21026 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21027 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21032 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21035 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21038 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21041 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21045 return std::make_pair(Opc, NeedSplit);
21049 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21050 const X86Subtarget *Subtarget) {
21052 SDValue Cond = N->getOperand(0);
21053 SDValue LHS = N->getOperand(1);
21054 SDValue RHS = N->getOperand(2);
21056 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21057 SDValue CondSrc = Cond->getOperand(0);
21058 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21059 Cond = CondSrc->getOperand(0);
21062 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21065 // A vselect where all conditions and data are constants can be optimized into
21066 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21067 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21068 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21071 unsigned MaskValue = 0;
21072 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21075 MVT VT = N->getSimpleValueType(0);
21076 unsigned NumElems = VT.getVectorNumElements();
21077 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21078 for (unsigned i = 0; i < NumElems; ++i) {
21079 // Be sure we emit undef where we can.
21080 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21081 ShuffleMask[i] = -1;
21083 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21086 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21087 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21089 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21092 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21094 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21095 TargetLowering::DAGCombinerInfo &DCI,
21096 const X86Subtarget *Subtarget) {
21098 SDValue Cond = N->getOperand(0);
21099 // Get the LHS/RHS of the select.
21100 SDValue LHS = N->getOperand(1);
21101 SDValue RHS = N->getOperand(2);
21102 EVT VT = LHS.getValueType();
21103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21105 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21106 // instructions match the semantics of the common C idiom x<y?x:y but not
21107 // x<=y?x:y, because of how they handle negative zero (which can be
21108 // ignored in unsafe-math mode).
21109 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21110 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21111 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21112 (Subtarget->hasSSE2() ||
21113 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21114 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21116 unsigned Opcode = 0;
21117 // Check for x CC y ? x : y.
21118 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21119 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21123 // Converting this to a min would handle NaNs incorrectly, and swapping
21124 // the operands would cause it to handle comparisons between positive
21125 // and negative zero incorrectly.
21126 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21127 if (!DAG.getTarget().Options.UnsafeFPMath &&
21128 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21130 std::swap(LHS, RHS);
21132 Opcode = X86ISD::FMIN;
21135 // Converting this to a min would handle comparisons between positive
21136 // and negative zero incorrectly.
21137 if (!DAG.getTarget().Options.UnsafeFPMath &&
21138 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21140 Opcode = X86ISD::FMIN;
21143 // Converting this to a min would handle both negative zeros and NaNs
21144 // incorrectly, but we can swap the operands to fix both.
21145 std::swap(LHS, RHS);
21149 Opcode = X86ISD::FMIN;
21153 // Converting this to a max would handle comparisons between positive
21154 // and negative zero incorrectly.
21155 if (!DAG.getTarget().Options.UnsafeFPMath &&
21156 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21158 Opcode = X86ISD::FMAX;
21161 // Converting this to a max would handle NaNs incorrectly, and swapping
21162 // the operands would cause it to handle comparisons between positive
21163 // and negative zero incorrectly.
21164 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21165 if (!DAG.getTarget().Options.UnsafeFPMath &&
21166 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21168 std::swap(LHS, RHS);
21170 Opcode = X86ISD::FMAX;
21173 // Converting this to a max would handle both negative zeros and NaNs
21174 // incorrectly, but we can swap the operands to fix both.
21175 std::swap(LHS, RHS);
21179 Opcode = X86ISD::FMAX;
21182 // Check for x CC y ? y : x -- a min/max with reversed arms.
21183 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21184 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21188 // Converting this to a min would handle comparisons between positive
21189 // and negative zero incorrectly, and swapping the operands would
21190 // cause it to handle NaNs incorrectly.
21191 if (!DAG.getTarget().Options.UnsafeFPMath &&
21192 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21193 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21195 std::swap(LHS, RHS);
21197 Opcode = X86ISD::FMIN;
21200 // Converting this to a min would handle NaNs incorrectly.
21201 if (!DAG.getTarget().Options.UnsafeFPMath &&
21202 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21204 Opcode = X86ISD::FMIN;
21207 // Converting this to a min would handle both negative zeros and NaNs
21208 // incorrectly, but we can swap the operands to fix both.
21209 std::swap(LHS, RHS);
21213 Opcode = X86ISD::FMIN;
21217 // Converting this to a max would handle NaNs incorrectly.
21218 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21220 Opcode = X86ISD::FMAX;
21223 // Converting this to a max would handle comparisons between positive
21224 // and negative zero incorrectly, and swapping the operands would
21225 // cause it to handle NaNs incorrectly.
21226 if (!DAG.getTarget().Options.UnsafeFPMath &&
21227 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21228 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21230 std::swap(LHS, RHS);
21232 Opcode = X86ISD::FMAX;
21235 // Converting this to a max would handle both negative zeros and NaNs
21236 // incorrectly, but we can swap the operands to fix both.
21237 std::swap(LHS, RHS);
21241 Opcode = X86ISD::FMAX;
21247 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21250 EVT CondVT = Cond.getValueType();
21251 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21252 CondVT.getVectorElementType() == MVT::i1) {
21253 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21254 // lowering on KNL. In this case we convert it to
21255 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21256 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21257 // Since SKX these selects have a proper lowering.
21258 EVT OpVT = LHS.getValueType();
21259 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21260 (OpVT.getVectorElementType() == MVT::i8 ||
21261 OpVT.getVectorElementType() == MVT::i16) &&
21262 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21263 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21264 DCI.AddToWorklist(Cond.getNode());
21265 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21268 // If this is a select between two integer constants, try to do some
21270 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21271 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21272 // Don't do this for crazy integer types.
21273 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21274 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21275 // so that TrueC (the true value) is larger than FalseC.
21276 bool NeedsCondInvert = false;
21278 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21279 // Efficiently invertible.
21280 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21281 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21282 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21283 NeedsCondInvert = true;
21284 std::swap(TrueC, FalseC);
21287 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21288 if (FalseC->getAPIntValue() == 0 &&
21289 TrueC->getAPIntValue().isPowerOf2()) {
21290 if (NeedsCondInvert) // Invert the condition if needed.
21291 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21292 DAG.getConstant(1, DL, Cond.getValueType()));
21294 // Zero extend the condition if needed.
21295 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21297 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21298 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21299 DAG.getConstant(ShAmt, DL, MVT::i8));
21302 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21303 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21304 if (NeedsCondInvert) // Invert the condition if needed.
21305 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21306 DAG.getConstant(1, DL, Cond.getValueType()));
21308 // Zero extend the condition if needed.
21309 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21310 FalseC->getValueType(0), Cond);
21311 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21312 SDValue(FalseC, 0));
21315 // Optimize cases that will turn into an LEA instruction. This requires
21316 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21317 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21318 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21319 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21321 bool isFastMultiplier = false;
21323 switch ((unsigned char)Diff) {
21325 case 1: // result = add base, cond
21326 case 2: // result = lea base( , cond*2)
21327 case 3: // result = lea base(cond, cond*2)
21328 case 4: // result = lea base( , cond*4)
21329 case 5: // result = lea base(cond, cond*4)
21330 case 8: // result = lea base( , cond*8)
21331 case 9: // result = lea base(cond, cond*8)
21332 isFastMultiplier = true;
21337 if (isFastMultiplier) {
21338 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21339 if (NeedsCondInvert) // Invert the condition if needed.
21340 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21341 DAG.getConstant(1, DL, Cond.getValueType()));
21343 // Zero extend the condition if needed.
21344 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21346 // Scale the condition by the difference.
21348 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21349 DAG.getConstant(Diff, DL,
21350 Cond.getValueType()));
21352 // Add the base if non-zero.
21353 if (FalseC->getAPIntValue() != 0)
21354 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21355 SDValue(FalseC, 0));
21362 // Canonicalize max and min:
21363 // (x > y) ? x : y -> (x >= y) ? x : y
21364 // (x < y) ? x : y -> (x <= y) ? x : y
21365 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21366 // the need for an extra compare
21367 // against zero. e.g.
21368 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21370 // testl %edi, %edi
21372 // cmovgl %edi, %eax
21376 // cmovsl %eax, %edi
21377 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21378 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21379 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21380 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21385 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21386 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21387 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21388 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21393 // Early exit check
21394 if (!TLI.isTypeLegal(VT))
21397 // Match VSELECTs into subs with unsigned saturation.
21398 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21399 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21400 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21401 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21402 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21404 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21405 // left side invert the predicate to simplify logic below.
21407 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21409 CC = ISD::getSetCCInverse(CC, true);
21410 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21414 if (Other.getNode() && Other->getNumOperands() == 2 &&
21415 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21416 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21417 SDValue CondRHS = Cond->getOperand(1);
21419 // Look for a general sub with unsigned saturation first.
21420 // x >= y ? x-y : 0 --> subus x, y
21421 // x > y ? x-y : 0 --> subus x, y
21422 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21423 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21424 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21426 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21427 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21428 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21429 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21430 // If the RHS is a constant we have to reverse the const
21431 // canonicalization.
21432 // x > C-1 ? x+-C : 0 --> subus x, C
21433 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21434 CondRHSConst->getAPIntValue() ==
21435 (-OpRHSConst->getAPIntValue() - 1))
21436 return DAG.getNode(
21437 X86ISD::SUBUS, DL, VT, OpLHS,
21438 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21440 // Another special case: If C was a sign bit, the sub has been
21441 // canonicalized into a xor.
21442 // FIXME: Would it be better to use computeKnownBits to determine
21443 // whether it's safe to decanonicalize the xor?
21444 // x s< 0 ? x^C : 0 --> subus x, C
21445 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21446 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21447 OpRHSConst->getAPIntValue().isSignBit())
21448 // Note that we have to rebuild the RHS constant here to ensure we
21449 // don't rely on particular values of undef lanes.
21450 return DAG.getNode(
21451 X86ISD::SUBUS, DL, VT, OpLHS,
21452 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21457 // Try to match a min/max vector operation.
21458 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21459 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21460 unsigned Opc = ret.first;
21461 bool NeedSplit = ret.second;
21463 if (Opc && NeedSplit) {
21464 unsigned NumElems = VT.getVectorNumElements();
21465 // Extract the LHS vectors
21466 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21467 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21469 // Extract the RHS vectors
21470 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21471 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21473 // Create min/max for each subvector
21474 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21475 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21477 // Merge the result
21478 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21480 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21483 // Simplify vector selection if condition value type matches vselect
21485 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21486 assert(Cond.getValueType().isVector() &&
21487 "vector select expects a vector selector!");
21489 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21490 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21492 // Try invert the condition if true value is not all 1s and false value
21494 if (!TValIsAllOnes && !FValIsAllZeros &&
21495 // Check if the selector will be produced by CMPP*/PCMP*
21496 Cond.getOpcode() == ISD::SETCC &&
21497 // Check if SETCC has already been promoted
21498 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21499 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21500 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21502 if (TValIsAllZeros || FValIsAllOnes) {
21503 SDValue CC = Cond.getOperand(2);
21504 ISD::CondCode NewCC =
21505 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21506 Cond.getOperand(0).getValueType().isInteger());
21507 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21508 std::swap(LHS, RHS);
21509 TValIsAllOnes = FValIsAllOnes;
21510 FValIsAllZeros = TValIsAllZeros;
21514 if (TValIsAllOnes || FValIsAllZeros) {
21517 if (TValIsAllOnes && FValIsAllZeros)
21519 else if (TValIsAllOnes)
21520 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21521 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21522 else if (FValIsAllZeros)
21523 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21524 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21526 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21530 // We should generate an X86ISD::BLENDI from a vselect if its argument
21531 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21532 // constants. This specific pattern gets generated when we split a
21533 // selector for a 512 bit vector in a machine without AVX512 (but with
21534 // 256-bit vectors), during legalization:
21536 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21538 // Iff we find this pattern and the build_vectors are built from
21539 // constants, we translate the vselect into a shuffle_vector that we
21540 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21541 if ((N->getOpcode() == ISD::VSELECT ||
21542 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21543 !DCI.isBeforeLegalize()) {
21544 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21545 if (Shuffle.getNode())
21549 // If this is a *dynamic* select (non-constant condition) and we can match
21550 // this node with one of the variable blend instructions, restructure the
21551 // condition so that the blends can use the high bit of each element and use
21552 // SimplifyDemandedBits to simplify the condition operand.
21553 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21554 !DCI.isBeforeLegalize() &&
21555 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21556 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21558 // Don't optimize vector selects that map to mask-registers.
21562 // We can only handle the cases where VSELECT is directly legal on the
21563 // subtarget. We custom lower VSELECT nodes with constant conditions and
21564 // this makes it hard to see whether a dynamic VSELECT will correctly
21565 // lower, so we both check the operation's status and explicitly handle the
21566 // cases where a *dynamic* blend will fail even though a constant-condition
21567 // blend could be custom lowered.
21568 // FIXME: We should find a better way to handle this class of problems.
21569 // Potentially, we should combine constant-condition vselect nodes
21570 // pre-legalization into shuffles and not mark as many types as custom
21572 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21574 // FIXME: We don't support i16-element blends currently. We could and
21575 // should support them by making *all* the bits in the condition be set
21576 // rather than just the high bit and using an i8-element blend.
21577 if (VT.getScalarType() == MVT::i16)
21579 // Dynamic blending was only available from SSE4.1 onward.
21580 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21582 // Byte blends are only available in AVX2
21583 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21584 !Subtarget->hasAVX2())
21587 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21588 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21590 APInt KnownZero, KnownOne;
21591 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21592 DCI.isBeforeLegalizeOps());
21593 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21594 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21596 // If we changed the computation somewhere in the DAG, this change
21597 // will affect all users of Cond.
21598 // Make sure it is fine and update all the nodes so that we do not
21599 // use the generic VSELECT anymore. Otherwise, we may perform
21600 // wrong optimizations as we messed up with the actual expectation
21601 // for the vector boolean values.
21602 if (Cond != TLO.Old) {
21603 // Check all uses of that condition operand to check whether it will be
21604 // consumed by non-BLEND instructions, which may depend on all bits are
21606 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21608 if (I->getOpcode() != ISD::VSELECT)
21609 // TODO: Add other opcodes eventually lowered into BLEND.
21612 // Update all the users of the condition, before committing the change,
21613 // so that the VSELECT optimizations that expect the correct vector
21614 // boolean value will not be triggered.
21615 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21617 DAG.ReplaceAllUsesOfValueWith(
21619 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21620 Cond, I->getOperand(1), I->getOperand(2)));
21621 DCI.CommitTargetLoweringOpt(TLO);
21624 // At this point, only Cond is changed. Change the condition
21625 // just for N to keep the opportunity to optimize all other
21626 // users their own way.
21627 DAG.ReplaceAllUsesOfValueWith(
21629 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21630 TLO.New, N->getOperand(1), N->getOperand(2)));
21638 // Check whether a boolean test is testing a boolean value generated by
21639 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21642 // Simplify the following patterns:
21643 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21644 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21645 // to (Op EFLAGS Cond)
21647 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21648 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21649 // to (Op EFLAGS !Cond)
21651 // where Op could be BRCOND or CMOV.
21653 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21654 // Quit if not CMP and SUB with its value result used.
21655 if (Cmp.getOpcode() != X86ISD::CMP &&
21656 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21659 // Quit if not used as a boolean value.
21660 if (CC != X86::COND_E && CC != X86::COND_NE)
21663 // Check CMP operands. One of them should be 0 or 1 and the other should be
21664 // an SetCC or extended from it.
21665 SDValue Op1 = Cmp.getOperand(0);
21666 SDValue Op2 = Cmp.getOperand(1);
21669 const ConstantSDNode* C = nullptr;
21670 bool needOppositeCond = (CC == X86::COND_E);
21671 bool checkAgainstTrue = false; // Is it a comparison against 1?
21673 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21675 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21677 else // Quit if all operands are not constants.
21680 if (C->getZExtValue() == 1) {
21681 needOppositeCond = !needOppositeCond;
21682 checkAgainstTrue = true;
21683 } else if (C->getZExtValue() != 0)
21684 // Quit if the constant is neither 0 or 1.
21687 bool truncatedToBoolWithAnd = false;
21688 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21689 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21690 SetCC.getOpcode() == ISD::TRUNCATE ||
21691 SetCC.getOpcode() == ISD::AND) {
21692 if (SetCC.getOpcode() == ISD::AND) {
21694 ConstantSDNode *CS;
21695 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21696 CS->getZExtValue() == 1)
21698 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21699 CS->getZExtValue() == 1)
21703 SetCC = SetCC.getOperand(OpIdx);
21704 truncatedToBoolWithAnd = true;
21706 SetCC = SetCC.getOperand(0);
21709 switch (SetCC.getOpcode()) {
21710 case X86ISD::SETCC_CARRY:
21711 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21712 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21713 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21714 // truncated to i1 using 'and'.
21715 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21717 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21718 "Invalid use of SETCC_CARRY!");
21720 case X86ISD::SETCC:
21721 // Set the condition code or opposite one if necessary.
21722 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21723 if (needOppositeCond)
21724 CC = X86::GetOppositeBranchCondition(CC);
21725 return SetCC.getOperand(1);
21726 case X86ISD::CMOV: {
21727 // Check whether false/true value has canonical one, i.e. 0 or 1.
21728 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21729 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21730 // Quit if true value is not a constant.
21733 // Quit if false value is not a constant.
21735 SDValue Op = SetCC.getOperand(0);
21736 // Skip 'zext' or 'trunc' node.
21737 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21738 Op.getOpcode() == ISD::TRUNCATE)
21739 Op = Op.getOperand(0);
21740 // A special case for rdrand/rdseed, where 0 is set if false cond is
21742 if ((Op.getOpcode() != X86ISD::RDRAND &&
21743 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21746 // Quit if false value is not the constant 0 or 1.
21747 bool FValIsFalse = true;
21748 if (FVal && FVal->getZExtValue() != 0) {
21749 if (FVal->getZExtValue() != 1)
21751 // If FVal is 1, opposite cond is needed.
21752 needOppositeCond = !needOppositeCond;
21753 FValIsFalse = false;
21755 // Quit if TVal is not the constant opposite of FVal.
21756 if (FValIsFalse && TVal->getZExtValue() != 1)
21758 if (!FValIsFalse && TVal->getZExtValue() != 0)
21760 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21761 if (needOppositeCond)
21762 CC = X86::GetOppositeBranchCondition(CC);
21763 return SetCC.getOperand(3);
21770 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21772 /// (X86or (X86setcc) (X86setcc))
21773 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21774 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21775 X86::CondCode &CC1, SDValue &Flags,
21777 if (Cond->getOpcode() == X86ISD::CMP) {
21778 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21779 if (!CondOp1C || !CondOp1C->isNullValue())
21782 Cond = Cond->getOperand(0);
21787 SDValue SetCC0, SetCC1;
21788 switch (Cond->getOpcode()) {
21789 default: return false;
21796 SetCC0 = Cond->getOperand(0);
21797 SetCC1 = Cond->getOperand(1);
21801 // Make sure we have SETCC nodes, using the same flags value.
21802 if (SetCC0.getOpcode() != X86ISD::SETCC ||
21803 SetCC1.getOpcode() != X86ISD::SETCC ||
21804 SetCC0->getOperand(1) != SetCC1->getOperand(1))
21807 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
21808 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
21809 Flags = SetCC0->getOperand(1);
21813 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21814 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21815 TargetLowering::DAGCombinerInfo &DCI,
21816 const X86Subtarget *Subtarget) {
21819 // If the flag operand isn't dead, don't touch this CMOV.
21820 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21823 SDValue FalseOp = N->getOperand(0);
21824 SDValue TrueOp = N->getOperand(1);
21825 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21826 SDValue Cond = N->getOperand(3);
21828 if (CC == X86::COND_E || CC == X86::COND_NE) {
21829 switch (Cond.getOpcode()) {
21833 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21834 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21835 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21841 Flags = checkBoolTestSetCCCombine(Cond, CC);
21842 if (Flags.getNode() &&
21843 // Extra check as FCMOV only supports a subset of X86 cond.
21844 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21845 SDValue Ops[] = { FalseOp, TrueOp,
21846 DAG.getConstant(CC, DL, MVT::i8), Flags };
21847 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21850 // If this is a select between two integer constants, try to do some
21851 // optimizations. Note that the operands are ordered the opposite of SELECT
21853 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21854 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21855 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21856 // larger than FalseC (the false value).
21857 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21858 CC = X86::GetOppositeBranchCondition(CC);
21859 std::swap(TrueC, FalseC);
21860 std::swap(TrueOp, FalseOp);
21863 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21864 // This is efficient for any integer data type (including i8/i16) and
21866 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21867 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21868 DAG.getConstant(CC, DL, MVT::i8), Cond);
21870 // Zero extend the condition if needed.
21871 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21873 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21874 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21875 DAG.getConstant(ShAmt, DL, MVT::i8));
21876 if (N->getNumValues() == 2) // Dead flag value?
21877 return DCI.CombineTo(N, Cond, SDValue());
21881 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21882 // for any integer data type, including i8/i16.
21883 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21884 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21885 DAG.getConstant(CC, DL, MVT::i8), Cond);
21887 // Zero extend the condition if needed.
21888 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21889 FalseC->getValueType(0), Cond);
21890 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21891 SDValue(FalseC, 0));
21893 if (N->getNumValues() == 2) // Dead flag value?
21894 return DCI.CombineTo(N, Cond, SDValue());
21898 // Optimize cases that will turn into an LEA instruction. This requires
21899 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21900 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21901 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21902 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21904 bool isFastMultiplier = false;
21906 switch ((unsigned char)Diff) {
21908 case 1: // result = add base, cond
21909 case 2: // result = lea base( , cond*2)
21910 case 3: // result = lea base(cond, cond*2)
21911 case 4: // result = lea base( , cond*4)
21912 case 5: // result = lea base(cond, cond*4)
21913 case 8: // result = lea base( , cond*8)
21914 case 9: // result = lea base(cond, cond*8)
21915 isFastMultiplier = true;
21920 if (isFastMultiplier) {
21921 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21922 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21923 DAG.getConstant(CC, DL, MVT::i8), Cond);
21924 // Zero extend the condition if needed.
21925 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21927 // Scale the condition by the difference.
21929 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21930 DAG.getConstant(Diff, DL, Cond.getValueType()));
21932 // Add the base if non-zero.
21933 if (FalseC->getAPIntValue() != 0)
21934 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21935 SDValue(FalseC, 0));
21936 if (N->getNumValues() == 2) // Dead flag value?
21937 return DCI.CombineTo(N, Cond, SDValue());
21944 // Handle these cases:
21945 // (select (x != c), e, c) -> select (x != c), e, x),
21946 // (select (x == c), c, e) -> select (x == c), x, e)
21947 // where the c is an integer constant, and the "select" is the combination
21948 // of CMOV and CMP.
21950 // The rationale for this change is that the conditional-move from a constant
21951 // needs two instructions, however, conditional-move from a register needs
21952 // only one instruction.
21954 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21955 // some instruction-combining opportunities. This opt needs to be
21956 // postponed as late as possible.
21958 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21959 // the DCI.xxxx conditions are provided to postpone the optimization as
21960 // late as possible.
21962 ConstantSDNode *CmpAgainst = nullptr;
21963 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21964 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21965 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21967 if (CC == X86::COND_NE &&
21968 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21969 CC = X86::GetOppositeBranchCondition(CC);
21970 std::swap(TrueOp, FalseOp);
21973 if (CC == X86::COND_E &&
21974 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21975 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21976 DAG.getConstant(CC, DL, MVT::i8), Cond };
21977 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21982 // Fold and/or of setcc's to double CMOV:
21983 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
21984 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
21986 // This combine lets us generate:
21987 // cmovcc1 (jcc1 if we don't have CMOV)
21993 // cmovne (jne if we don't have CMOV)
21994 // When we can't use the CMOV instruction, it might increase branch
21996 // When we can use CMOV, or when there is no mispredict, this improves
21997 // throughput and reduces register pressure.
21999 if (CC == X86::COND_NE) {
22001 X86::CondCode CC0, CC1;
22003 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22005 std::swap(FalseOp, TrueOp);
22006 CC0 = X86::GetOppositeBranchCondition(CC0);
22007 CC1 = X86::GetOppositeBranchCondition(CC1);
22010 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22012 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22013 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22014 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22015 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22023 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22024 const X86Subtarget *Subtarget) {
22025 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22027 default: return SDValue();
22028 // SSE/AVX/AVX2 blend intrinsics.
22029 case Intrinsic::x86_avx2_pblendvb:
22030 // Don't try to simplify this intrinsic if we don't have AVX2.
22031 if (!Subtarget->hasAVX2())
22034 case Intrinsic::x86_avx_blendv_pd_256:
22035 case Intrinsic::x86_avx_blendv_ps_256:
22036 // Don't try to simplify this intrinsic if we don't have AVX.
22037 if (!Subtarget->hasAVX())
22040 case Intrinsic::x86_sse41_blendvps:
22041 case Intrinsic::x86_sse41_blendvpd:
22042 case Intrinsic::x86_sse41_pblendvb: {
22043 SDValue Op0 = N->getOperand(1);
22044 SDValue Op1 = N->getOperand(2);
22045 SDValue Mask = N->getOperand(3);
22047 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22048 if (!Subtarget->hasSSE41())
22051 // fold (blend A, A, Mask) -> A
22054 // fold (blend A, B, allZeros) -> A
22055 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22057 // fold (blend A, B, allOnes) -> B
22058 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22061 // Simplify the case where the mask is a constant i32 value.
22062 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22063 if (C->isNullValue())
22065 if (C->isAllOnesValue())
22072 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22073 case Intrinsic::x86_sse2_psrai_w:
22074 case Intrinsic::x86_sse2_psrai_d:
22075 case Intrinsic::x86_avx2_psrai_w:
22076 case Intrinsic::x86_avx2_psrai_d:
22077 case Intrinsic::x86_sse2_psra_w:
22078 case Intrinsic::x86_sse2_psra_d:
22079 case Intrinsic::x86_avx2_psra_w:
22080 case Intrinsic::x86_avx2_psra_d: {
22081 SDValue Op0 = N->getOperand(1);
22082 SDValue Op1 = N->getOperand(2);
22083 EVT VT = Op0.getValueType();
22084 assert(VT.isVector() && "Expected a vector type!");
22086 if (isa<BuildVectorSDNode>(Op1))
22087 Op1 = Op1.getOperand(0);
22089 if (!isa<ConstantSDNode>(Op1))
22092 EVT SVT = VT.getVectorElementType();
22093 unsigned SVTBits = SVT.getSizeInBits();
22095 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22096 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22097 uint64_t ShAmt = C.getZExtValue();
22099 // Don't try to convert this shift into a ISD::SRA if the shift
22100 // count is bigger than or equal to the element size.
22101 if (ShAmt >= SVTBits)
22104 // Trivial case: if the shift count is zero, then fold this
22105 // into the first operand.
22109 // Replace this packed shift intrinsic with a target independent
22112 SDValue Splat = DAG.getConstant(C, DL, VT);
22113 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22118 /// PerformMulCombine - Optimize a single multiply with constant into two
22119 /// in order to implement it with two cheaper instructions, e.g.
22120 /// LEA + SHL, LEA + LEA.
22121 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22122 TargetLowering::DAGCombinerInfo &DCI) {
22123 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22126 EVT VT = N->getValueType(0);
22127 if (VT != MVT::i64 && VT != MVT::i32)
22130 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22133 uint64_t MulAmt = C->getZExtValue();
22134 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22137 uint64_t MulAmt1 = 0;
22138 uint64_t MulAmt2 = 0;
22139 if ((MulAmt % 9) == 0) {
22141 MulAmt2 = MulAmt / 9;
22142 } else if ((MulAmt % 5) == 0) {
22144 MulAmt2 = MulAmt / 5;
22145 } else if ((MulAmt % 3) == 0) {
22147 MulAmt2 = MulAmt / 3;
22150 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22153 if (isPowerOf2_64(MulAmt2) &&
22154 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22155 // If second multiplifer is pow2, issue it first. We want the multiply by
22156 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22158 std::swap(MulAmt1, MulAmt2);
22161 if (isPowerOf2_64(MulAmt1))
22162 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22163 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22165 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22166 DAG.getConstant(MulAmt1, DL, VT));
22168 if (isPowerOf2_64(MulAmt2))
22169 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22170 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22172 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22173 DAG.getConstant(MulAmt2, DL, VT));
22175 // Do not add new nodes to DAG combiner worklist.
22176 DCI.CombineTo(N, NewMul, false);
22181 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22182 SDValue N0 = N->getOperand(0);
22183 SDValue N1 = N->getOperand(1);
22184 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22185 EVT VT = N0.getValueType();
22187 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22188 // since the result of setcc_c is all zero's or all ones.
22189 if (VT.isInteger() && !VT.isVector() &&
22190 N1C && N0.getOpcode() == ISD::AND &&
22191 N0.getOperand(1).getOpcode() == ISD::Constant) {
22192 SDValue N00 = N0.getOperand(0);
22193 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22194 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22195 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22196 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22197 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22198 APInt ShAmt = N1C->getAPIntValue();
22199 Mask = Mask.shl(ShAmt);
22202 return DAG.getNode(ISD::AND, DL, VT,
22203 N00, DAG.getConstant(Mask, DL, VT));
22208 // Hardware support for vector shifts is sparse which makes us scalarize the
22209 // vector operations in many cases. Also, on sandybridge ADD is faster than
22211 // (shl V, 1) -> add V,V
22212 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22213 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22214 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22215 // We shift all of the values by one. In many cases we do not have
22216 // hardware support for this operation. This is better expressed as an ADD
22218 if (N1SplatC->getZExtValue() == 1)
22219 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22225 /// \brief Returns a vector of 0s if the node in input is a vector logical
22226 /// shift by a constant amount which is known to be bigger than or equal
22227 /// to the vector element size in bits.
22228 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22229 const X86Subtarget *Subtarget) {
22230 EVT VT = N->getValueType(0);
22232 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22233 (!Subtarget->hasInt256() ||
22234 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22237 SDValue Amt = N->getOperand(1);
22239 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22240 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22241 APInt ShiftAmt = AmtSplat->getAPIntValue();
22242 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22244 // SSE2/AVX2 logical shifts always return a vector of 0s
22245 // if the shift amount is bigger than or equal to
22246 // the element size. The constant shift amount will be
22247 // encoded as a 8-bit immediate.
22248 if (ShiftAmt.trunc(8).uge(MaxAmount))
22249 return getZeroVector(VT, Subtarget, DAG, DL);
22255 /// PerformShiftCombine - Combine shifts.
22256 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22257 TargetLowering::DAGCombinerInfo &DCI,
22258 const X86Subtarget *Subtarget) {
22259 if (N->getOpcode() == ISD::SHL) {
22260 SDValue V = PerformSHLCombine(N, DAG);
22261 if (V.getNode()) return V;
22264 if (N->getOpcode() != ISD::SRA) {
22265 // Try to fold this logical shift into a zero vector.
22266 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22267 if (V.getNode()) return V;
22273 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22274 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22275 // and friends. Likewise for OR -> CMPNEQSS.
22276 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22277 TargetLowering::DAGCombinerInfo &DCI,
22278 const X86Subtarget *Subtarget) {
22281 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22282 // we're requiring SSE2 for both.
22283 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22284 SDValue N0 = N->getOperand(0);
22285 SDValue N1 = N->getOperand(1);
22286 SDValue CMP0 = N0->getOperand(1);
22287 SDValue CMP1 = N1->getOperand(1);
22290 // The SETCCs should both refer to the same CMP.
22291 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22294 SDValue CMP00 = CMP0->getOperand(0);
22295 SDValue CMP01 = CMP0->getOperand(1);
22296 EVT VT = CMP00.getValueType();
22298 if (VT == MVT::f32 || VT == MVT::f64) {
22299 bool ExpectingFlags = false;
22300 // Check for any users that want flags:
22301 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22302 !ExpectingFlags && UI != UE; ++UI)
22303 switch (UI->getOpcode()) {
22308 ExpectingFlags = true;
22310 case ISD::CopyToReg:
22311 case ISD::SIGN_EXTEND:
22312 case ISD::ZERO_EXTEND:
22313 case ISD::ANY_EXTEND:
22317 if (!ExpectingFlags) {
22318 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22319 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22321 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22322 X86::CondCode tmp = cc0;
22327 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22328 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22329 // FIXME: need symbolic constants for these magic numbers.
22330 // See X86ATTInstPrinter.cpp:printSSECC().
22331 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22332 if (Subtarget->hasAVX512()) {
22333 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22335 DAG.getConstant(x86cc, DL, MVT::i8));
22336 if (N->getValueType(0) != MVT::i1)
22337 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22341 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22342 CMP00.getValueType(), CMP00, CMP01,
22343 DAG.getConstant(x86cc, DL,
22346 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22347 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22349 if (is64BitFP && !Subtarget->is64Bit()) {
22350 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22351 // 64-bit integer, since that's not a legal type. Since
22352 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22353 // bits, but can do this little dance to extract the lowest 32 bits
22354 // and work with those going forward.
22355 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22357 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22359 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22360 Vector32, DAG.getIntPtrConstant(0, DL));
22364 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
22366 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22367 DAG.getConstant(1, DL, IntVT));
22368 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22370 return OneBitOfTruth;
22378 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22379 /// so it can be folded inside ANDNP.
22380 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22381 EVT VT = N->getValueType(0);
22383 // Match direct AllOnes for 128 and 256-bit vectors
22384 if (ISD::isBuildVectorAllOnes(N))
22387 // Look through a bit convert.
22388 if (N->getOpcode() == ISD::BITCAST)
22389 N = N->getOperand(0).getNode();
22391 // Sometimes the operand may come from a insert_subvector building a 256-bit
22393 if (VT.is256BitVector() &&
22394 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22395 SDValue V1 = N->getOperand(0);
22396 SDValue V2 = N->getOperand(1);
22398 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22399 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22400 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22401 ISD::isBuildVectorAllOnes(V2.getNode()))
22408 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22409 // register. In most cases we actually compare or select YMM-sized registers
22410 // and mixing the two types creates horrible code. This method optimizes
22411 // some of the transition sequences.
22412 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22413 TargetLowering::DAGCombinerInfo &DCI,
22414 const X86Subtarget *Subtarget) {
22415 EVT VT = N->getValueType(0);
22416 if (!VT.is256BitVector())
22419 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22420 N->getOpcode() == ISD::ZERO_EXTEND ||
22421 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22423 SDValue Narrow = N->getOperand(0);
22424 EVT NarrowVT = Narrow->getValueType(0);
22425 if (!NarrowVT.is128BitVector())
22428 if (Narrow->getOpcode() != ISD::XOR &&
22429 Narrow->getOpcode() != ISD::AND &&
22430 Narrow->getOpcode() != ISD::OR)
22433 SDValue N0 = Narrow->getOperand(0);
22434 SDValue N1 = Narrow->getOperand(1);
22437 // The Left side has to be a trunc.
22438 if (N0.getOpcode() != ISD::TRUNCATE)
22441 // The type of the truncated inputs.
22442 EVT WideVT = N0->getOperand(0)->getValueType(0);
22446 // The right side has to be a 'trunc' or a constant vector.
22447 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22448 ConstantSDNode *RHSConstSplat = nullptr;
22449 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22450 RHSConstSplat = RHSBV->getConstantSplatNode();
22451 if (!RHSTrunc && !RHSConstSplat)
22454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22456 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22459 // Set N0 and N1 to hold the inputs to the new wide operation.
22460 N0 = N0->getOperand(0);
22461 if (RHSConstSplat) {
22462 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22463 SDValue(RHSConstSplat, 0));
22464 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22465 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22466 } else if (RHSTrunc) {
22467 N1 = N1->getOperand(0);
22470 // Generate the wide operation.
22471 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22472 unsigned Opcode = N->getOpcode();
22474 case ISD::ANY_EXTEND:
22476 case ISD::ZERO_EXTEND: {
22477 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22478 APInt Mask = APInt::getAllOnesValue(InBits);
22479 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22480 return DAG.getNode(ISD::AND, DL, VT,
22481 Op, DAG.getConstant(Mask, DL, VT));
22483 case ISD::SIGN_EXTEND:
22484 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22485 Op, DAG.getValueType(NarrowVT));
22487 llvm_unreachable("Unexpected opcode");
22491 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22492 TargetLowering::DAGCombinerInfo &DCI,
22493 const X86Subtarget *Subtarget) {
22494 SDValue N0 = N->getOperand(0);
22495 SDValue N1 = N->getOperand(1);
22498 // A vector zext_in_reg may be represented as a shuffle,
22499 // feeding into a bitcast (this represents anyext) feeding into
22500 // an and with a mask.
22501 // We'd like to try to combine that into a shuffle with zero
22502 // plus a bitcast, removing the and.
22503 if (N0.getOpcode() != ISD::BITCAST ||
22504 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22507 // The other side of the AND should be a splat of 2^C, where C
22508 // is the number of bits in the source type.
22509 if (N1.getOpcode() == ISD::BITCAST)
22510 N1 = N1.getOperand(0);
22511 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22513 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22515 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22516 EVT SrcType = Shuffle->getValueType(0);
22518 // We expect a single-source shuffle
22519 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22522 unsigned SrcSize = SrcType.getScalarSizeInBits();
22524 APInt SplatValue, SplatUndef;
22525 unsigned SplatBitSize;
22527 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22528 SplatBitSize, HasAnyUndefs))
22531 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22532 // Make sure the splat matches the mask we expect
22533 if (SplatBitSize > ResSize ||
22534 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22537 // Make sure the input and output size make sense
22538 if (SrcSize >= ResSize || ResSize % SrcSize)
22541 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22542 // The number of u's between each two values depends on the ratio between
22543 // the source and dest type.
22544 unsigned ZextRatio = ResSize / SrcSize;
22545 bool IsZext = true;
22546 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22547 if (i % ZextRatio) {
22548 if (Shuffle->getMaskElt(i) > 0) {
22554 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22555 // Expected element number
22565 // Ok, perform the transformation - replace the shuffle with
22566 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22567 // (instead of undef) where the k elements come from the zero vector.
22568 SmallVector<int, 8> Mask;
22569 unsigned NumElems = SrcType.getVectorNumElements();
22570 for (unsigned i = 0; i < NumElems; ++i)
22572 Mask.push_back(NumElems);
22574 Mask.push_back(i / ZextRatio);
22576 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22577 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
22578 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22581 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22582 TargetLowering::DAGCombinerInfo &DCI,
22583 const X86Subtarget *Subtarget) {
22584 if (DCI.isBeforeLegalizeOps())
22587 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22590 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22593 EVT VT = N->getValueType(0);
22594 SDValue N0 = N->getOperand(0);
22595 SDValue N1 = N->getOperand(1);
22598 // Create BEXTR instructions
22599 // BEXTR is ((X >> imm) & (2**size-1))
22600 if (VT == MVT::i32 || VT == MVT::i64) {
22601 // Check for BEXTR.
22602 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22603 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22604 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22605 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22606 if (MaskNode && ShiftNode) {
22607 uint64_t Mask = MaskNode->getZExtValue();
22608 uint64_t Shift = ShiftNode->getZExtValue();
22609 if (isMask_64(Mask)) {
22610 uint64_t MaskSize = countPopulation(Mask);
22611 if (Shift + MaskSize <= VT.getSizeInBits())
22612 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22613 DAG.getConstant(Shift | (MaskSize << 8), DL,
22622 // Want to form ANDNP nodes:
22623 // 1) In the hopes of then easily combining them with OR and AND nodes
22624 // to form PBLEND/PSIGN.
22625 // 2) To match ANDN packed intrinsics
22626 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22629 // Check LHS for vnot
22630 if (N0.getOpcode() == ISD::XOR &&
22631 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22632 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22633 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22635 // Check RHS for vnot
22636 if (N1.getOpcode() == ISD::XOR &&
22637 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22638 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22639 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22644 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22645 TargetLowering::DAGCombinerInfo &DCI,
22646 const X86Subtarget *Subtarget) {
22647 if (DCI.isBeforeLegalizeOps())
22650 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22654 SDValue N0 = N->getOperand(0);
22655 SDValue N1 = N->getOperand(1);
22656 EVT VT = N->getValueType(0);
22658 // look for psign/blend
22659 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22660 if (!Subtarget->hasSSSE3() ||
22661 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22664 // Canonicalize pandn to RHS
22665 if (N0.getOpcode() == X86ISD::ANDNP)
22667 // or (and (m, y), (pandn m, x))
22668 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22669 SDValue Mask = N1.getOperand(0);
22670 SDValue X = N1.getOperand(1);
22672 if (N0.getOperand(0) == Mask)
22673 Y = N0.getOperand(1);
22674 if (N0.getOperand(1) == Mask)
22675 Y = N0.getOperand(0);
22677 // Check to see if the mask appeared in both the AND and ANDNP and
22681 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22682 // Look through mask bitcast.
22683 if (Mask.getOpcode() == ISD::BITCAST)
22684 Mask = Mask.getOperand(0);
22685 if (X.getOpcode() == ISD::BITCAST)
22686 X = X.getOperand(0);
22687 if (Y.getOpcode() == ISD::BITCAST)
22688 Y = Y.getOperand(0);
22690 EVT MaskVT = Mask.getValueType();
22692 // Validate that the Mask operand is a vector sra node.
22693 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22694 // there is no psrai.b
22695 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22696 unsigned SraAmt = ~0;
22697 if (Mask.getOpcode() == ISD::SRA) {
22698 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22699 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22700 SraAmt = AmtConst->getZExtValue();
22701 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22702 SDValue SraC = Mask.getOperand(1);
22703 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22705 if ((SraAmt + 1) != EltBits)
22710 // Now we know we at least have a plendvb with the mask val. See if
22711 // we can form a psignb/w/d.
22712 // psign = x.type == y.type == mask.type && y = sub(0, x);
22713 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22714 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22715 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22716 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22717 "Unsupported VT for PSIGN");
22718 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22719 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22721 // PBLENDVB only available on SSE 4.1
22722 if (!Subtarget->hasSSE41())
22725 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22727 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22728 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22729 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22730 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22731 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22735 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22738 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22739 MachineFunction &MF = DAG.getMachineFunction();
22741 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22743 // SHLD/SHRD instructions have lower register pressure, but on some
22744 // platforms they have higher latency than the equivalent
22745 // series of shifts/or that would otherwise be generated.
22746 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22747 // have higher latencies and we are not optimizing for size.
22748 if (!OptForSize && Subtarget->isSHLDSlow())
22751 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22753 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22755 if (!N0.hasOneUse() || !N1.hasOneUse())
22758 SDValue ShAmt0 = N0.getOperand(1);
22759 if (ShAmt0.getValueType() != MVT::i8)
22761 SDValue ShAmt1 = N1.getOperand(1);
22762 if (ShAmt1.getValueType() != MVT::i8)
22764 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22765 ShAmt0 = ShAmt0.getOperand(0);
22766 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22767 ShAmt1 = ShAmt1.getOperand(0);
22770 unsigned Opc = X86ISD::SHLD;
22771 SDValue Op0 = N0.getOperand(0);
22772 SDValue Op1 = N1.getOperand(0);
22773 if (ShAmt0.getOpcode() == ISD::SUB) {
22774 Opc = X86ISD::SHRD;
22775 std::swap(Op0, Op1);
22776 std::swap(ShAmt0, ShAmt1);
22779 unsigned Bits = VT.getSizeInBits();
22780 if (ShAmt1.getOpcode() == ISD::SUB) {
22781 SDValue Sum = ShAmt1.getOperand(0);
22782 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22783 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22784 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22785 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22786 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22787 return DAG.getNode(Opc, DL, VT,
22789 DAG.getNode(ISD::TRUNCATE, DL,
22792 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22793 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22795 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22796 return DAG.getNode(Opc, DL, VT,
22797 N0.getOperand(0), N1.getOperand(0),
22798 DAG.getNode(ISD::TRUNCATE, DL,
22805 // Generate NEG and CMOV for integer abs.
22806 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22807 EVT VT = N->getValueType(0);
22809 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22810 // 8-bit integer abs to NEG and CMOV.
22811 if (VT.isInteger() && VT.getSizeInBits() == 8)
22814 SDValue N0 = N->getOperand(0);
22815 SDValue N1 = N->getOperand(1);
22818 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22819 // and change it to SUB and CMOV.
22820 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22821 N0.getOpcode() == ISD::ADD &&
22822 N0.getOperand(1) == N1 &&
22823 N1.getOpcode() == ISD::SRA &&
22824 N1.getOperand(0) == N0.getOperand(0))
22825 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22826 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22827 // Generate SUB & CMOV.
22828 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22829 DAG.getConstant(0, DL, VT), N0.getOperand(0));
22831 SDValue Ops[] = { N0.getOperand(0), Neg,
22832 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
22833 SDValue(Neg.getNode(), 1) };
22834 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22839 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22840 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22841 TargetLowering::DAGCombinerInfo &DCI,
22842 const X86Subtarget *Subtarget) {
22843 if (DCI.isBeforeLegalizeOps())
22846 if (Subtarget->hasCMov()) {
22847 SDValue RV = performIntegerAbsCombine(N, DAG);
22855 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22856 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22857 TargetLowering::DAGCombinerInfo &DCI,
22858 const X86Subtarget *Subtarget) {
22859 LoadSDNode *Ld = cast<LoadSDNode>(N);
22860 EVT RegVT = Ld->getValueType(0);
22861 EVT MemVT = Ld->getMemoryVT();
22863 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22865 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
22866 // into two 16-byte operations.
22867 ISD::LoadExtType Ext = Ld->getExtensionType();
22868 unsigned Alignment = Ld->getAlignment();
22869 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22870 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22871 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22872 unsigned NumElems = RegVT.getVectorNumElements();
22876 SDValue Ptr = Ld->getBasePtr();
22877 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
22879 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22881 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22882 Ld->getPointerInfo(), Ld->isVolatile(),
22883 Ld->isNonTemporal(), Ld->isInvariant(),
22885 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22886 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22887 Ld->getPointerInfo(), Ld->isVolatile(),
22888 Ld->isNonTemporal(), Ld->isInvariant(),
22889 std::min(16U, Alignment));
22890 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22892 Load2.getValue(1));
22894 SDValue NewVec = DAG.getUNDEF(RegVT);
22895 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22896 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22897 return DCI.CombineTo(N, NewVec, TF, true);
22903 /// PerformMLOADCombine - Resolve extending loads
22904 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22905 TargetLowering::DAGCombinerInfo &DCI,
22906 const X86Subtarget *Subtarget) {
22907 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22908 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22911 EVT VT = Mld->getValueType(0);
22912 unsigned NumElems = VT.getVectorNumElements();
22913 EVT LdVT = Mld->getMemoryVT();
22916 assert(LdVT != VT && "Cannot extend to the same type");
22917 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22918 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22919 // From, To sizes and ElemCount must be pow of two
22920 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22921 "Unexpected size for extending masked load");
22923 unsigned SizeRatio = ToSz / FromSz;
22924 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22926 // Create a type on which we perform the shuffle
22927 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22928 LdVT.getScalarType(), NumElems*SizeRatio);
22929 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22931 // Convert Src0 value
22932 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22933 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22934 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22935 for (unsigned i = 0; i != NumElems; ++i)
22936 ShuffleVec[i] = i * SizeRatio;
22938 // Can't shuffle using an illegal type.
22939 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22940 && "WideVecVT should be legal");
22941 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22942 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22944 // Prepare the new mask
22946 SDValue Mask = Mld->getMask();
22947 if (Mask.getValueType() == VT) {
22948 // Mask and original value have the same type
22949 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22950 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22951 for (unsigned i = 0; i != NumElems; ++i)
22952 ShuffleVec[i] = i * SizeRatio;
22953 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22954 ShuffleVec[i] = NumElems*SizeRatio;
22955 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22956 DAG.getConstant(0, dl, WideVecVT),
22960 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22961 unsigned WidenNumElts = NumElems*SizeRatio;
22962 unsigned MaskNumElts = VT.getVectorNumElements();
22963 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22966 unsigned NumConcat = WidenNumElts / MaskNumElts;
22967 SmallVector<SDValue, 16> Ops(NumConcat);
22968 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
22970 for (unsigned i = 1; i != NumConcat; ++i)
22973 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22976 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22977 Mld->getBasePtr(), NewMask, WideSrc0,
22978 Mld->getMemoryVT(), Mld->getMemOperand(),
22980 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22981 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22984 /// PerformMSTORECombine - Resolve truncating stores
22985 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22986 const X86Subtarget *Subtarget) {
22987 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22988 if (!Mst->isTruncatingStore())
22991 EVT VT = Mst->getValue().getValueType();
22992 unsigned NumElems = VT.getVectorNumElements();
22993 EVT StVT = Mst->getMemoryVT();
22996 assert(StVT != VT && "Cannot truncate to the same type");
22997 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22998 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23000 // From, To sizes and ElemCount must be pow of two
23001 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23002 "Unexpected size for truncating masked store");
23003 // We are going to use the original vector elt for storing.
23004 // Accumulated smaller vector elements must be a multiple of the store size.
23005 assert (((NumElems * FromSz) % ToSz) == 0 &&
23006 "Unexpected ratio for truncating masked store");
23008 unsigned SizeRatio = FromSz / ToSz;
23009 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23011 // Create a type on which we perform the shuffle
23012 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23013 StVT.getScalarType(), NumElems*SizeRatio);
23015 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23017 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
23018 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23019 for (unsigned i = 0; i != NumElems; ++i)
23020 ShuffleVec[i] = i * SizeRatio;
23022 // Can't shuffle using an illegal type.
23023 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23024 && "WideVecVT should be legal");
23026 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23027 DAG.getUNDEF(WideVecVT),
23031 SDValue Mask = Mst->getMask();
23032 if (Mask.getValueType() == VT) {
23033 // Mask and original value have the same type
23034 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23035 for (unsigned i = 0; i != NumElems; ++i)
23036 ShuffleVec[i] = i * SizeRatio;
23037 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23038 ShuffleVec[i] = NumElems*SizeRatio;
23039 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23040 DAG.getConstant(0, dl, WideVecVT),
23044 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23045 unsigned WidenNumElts = NumElems*SizeRatio;
23046 unsigned MaskNumElts = VT.getVectorNumElements();
23047 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23050 unsigned NumConcat = WidenNumElts / MaskNumElts;
23051 SmallVector<SDValue, 16> Ops(NumConcat);
23052 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23054 for (unsigned i = 1; i != NumConcat; ++i)
23057 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23060 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23061 NewMask, StVT, Mst->getMemOperand(), false);
23063 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23064 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23065 const X86Subtarget *Subtarget) {
23066 StoreSDNode *St = cast<StoreSDNode>(N);
23067 EVT VT = St->getValue().getValueType();
23068 EVT StVT = St->getMemoryVT();
23070 SDValue StoredVal = St->getOperand(1);
23071 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23073 // If we are saving a concatenation of two XMM registers and 32-byte stores
23074 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23075 unsigned Alignment = St->getAlignment();
23076 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23077 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23078 StVT == VT && !IsAligned) {
23079 unsigned NumElems = VT.getVectorNumElements();
23083 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23084 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23086 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23087 SDValue Ptr0 = St->getBasePtr();
23088 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23090 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23091 St->getPointerInfo(), St->isVolatile(),
23092 St->isNonTemporal(), Alignment);
23093 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23094 St->getPointerInfo(), St->isVolatile(),
23095 St->isNonTemporal(),
23096 std::min(16U, Alignment));
23097 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23100 // Optimize trunc store (of multiple scalars) to shuffle and store.
23101 // First, pack all of the elements in one place. Next, store to memory
23102 // in fewer chunks.
23103 if (St->isTruncatingStore() && VT.isVector()) {
23104 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23105 unsigned NumElems = VT.getVectorNumElements();
23106 assert(StVT != VT && "Cannot truncate to the same type");
23107 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23108 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23110 // From, To sizes and ElemCount must be pow of two
23111 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23112 // We are going to use the original vector elt for storing.
23113 // Accumulated smaller vector elements must be a multiple of the store size.
23114 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23116 unsigned SizeRatio = FromSz / ToSz;
23118 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23120 // Create a type on which we perform the shuffle
23121 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23122 StVT.getScalarType(), NumElems*SizeRatio);
23124 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23126 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23127 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23128 for (unsigned i = 0; i != NumElems; ++i)
23129 ShuffleVec[i] = i * SizeRatio;
23131 // Can't shuffle using an illegal type.
23132 if (!TLI.isTypeLegal(WideVecVT))
23135 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23136 DAG.getUNDEF(WideVecVT),
23138 // At this point all of the data is stored at the bottom of the
23139 // register. We now need to save it to mem.
23141 // Find the largest store unit
23142 MVT StoreType = MVT::i8;
23143 for (MVT Tp : MVT::integer_valuetypes()) {
23144 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23148 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23149 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23150 (64 <= NumElems * ToSz))
23151 StoreType = MVT::f64;
23153 // Bitcast the original vector into a vector of store-size units
23154 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23155 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23156 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23157 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23158 SmallVector<SDValue, 8> Chains;
23159 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23160 TLI.getPointerTy());
23161 SDValue Ptr = St->getBasePtr();
23163 // Perform one or more big stores into memory.
23164 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23165 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23166 StoreType, ShuffWide,
23167 DAG.getIntPtrConstant(i, dl));
23168 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23169 St->getPointerInfo(), St->isVolatile(),
23170 St->isNonTemporal(), St->getAlignment());
23171 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23172 Chains.push_back(Ch);
23175 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23178 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23179 // the FP state in cases where an emms may be missing.
23180 // A preferable solution to the general problem is to figure out the right
23181 // places to insert EMMS. This qualifies as a quick hack.
23183 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23184 if (VT.getSizeInBits() != 64)
23187 const Function *F = DAG.getMachineFunction().getFunction();
23188 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23190 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23191 if ((VT.isVector() ||
23192 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23193 isa<LoadSDNode>(St->getValue()) &&
23194 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23195 St->getChain().hasOneUse() && !St->isVolatile()) {
23196 SDNode* LdVal = St->getValue().getNode();
23197 LoadSDNode *Ld = nullptr;
23198 int TokenFactorIndex = -1;
23199 SmallVector<SDValue, 8> Ops;
23200 SDNode* ChainVal = St->getChain().getNode();
23201 // Must be a store of a load. We currently handle two cases: the load
23202 // is a direct child, and it's under an intervening TokenFactor. It is
23203 // possible to dig deeper under nested TokenFactors.
23204 if (ChainVal == LdVal)
23205 Ld = cast<LoadSDNode>(St->getChain());
23206 else if (St->getValue().hasOneUse() &&
23207 ChainVal->getOpcode() == ISD::TokenFactor) {
23208 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23209 if (ChainVal->getOperand(i).getNode() == LdVal) {
23210 TokenFactorIndex = i;
23211 Ld = cast<LoadSDNode>(St->getValue());
23213 Ops.push_back(ChainVal->getOperand(i));
23217 if (!Ld || !ISD::isNormalLoad(Ld))
23220 // If this is not the MMX case, i.e. we are just turning i64 load/store
23221 // into f64 load/store, avoid the transformation if there are multiple
23222 // uses of the loaded value.
23223 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23228 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23229 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23231 if (Subtarget->is64Bit() || F64IsLegal) {
23232 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23233 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23234 Ld->getPointerInfo(), Ld->isVolatile(),
23235 Ld->isNonTemporal(), Ld->isInvariant(),
23236 Ld->getAlignment());
23237 SDValue NewChain = NewLd.getValue(1);
23238 if (TokenFactorIndex != -1) {
23239 Ops.push_back(NewChain);
23240 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23242 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23243 St->getPointerInfo(),
23244 St->isVolatile(), St->isNonTemporal(),
23245 St->getAlignment());
23248 // Otherwise, lower to two pairs of 32-bit loads / stores.
23249 SDValue LoAddr = Ld->getBasePtr();
23250 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23251 DAG.getConstant(4, LdDL, MVT::i32));
23253 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23254 Ld->getPointerInfo(),
23255 Ld->isVolatile(), Ld->isNonTemporal(),
23256 Ld->isInvariant(), Ld->getAlignment());
23257 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23258 Ld->getPointerInfo().getWithOffset(4),
23259 Ld->isVolatile(), Ld->isNonTemporal(),
23261 MinAlign(Ld->getAlignment(), 4));
23263 SDValue NewChain = LoLd.getValue(1);
23264 if (TokenFactorIndex != -1) {
23265 Ops.push_back(LoLd);
23266 Ops.push_back(HiLd);
23267 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23270 LoAddr = St->getBasePtr();
23271 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23272 DAG.getConstant(4, StDL, MVT::i32));
23274 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23275 St->getPointerInfo(),
23276 St->isVolatile(), St->isNonTemporal(),
23277 St->getAlignment());
23278 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23279 St->getPointerInfo().getWithOffset(4),
23281 St->isNonTemporal(),
23282 MinAlign(St->getAlignment(), 4));
23283 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23286 // This is similar to the above case, but here we handle a scalar 64-bit
23287 // integer store that is extracted from a vector on a 32-bit target.
23288 // If we have SSE2, then we can treat it like a floating-point double
23289 // to get past legalization. The execution dependencies fixup pass will
23290 // choose the optimal machine instruction for the store if this really is
23291 // an integer or v2f32 rather than an f64.
23292 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23293 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23294 SDValue OldExtract = St->getOperand(1);
23295 SDValue ExtOp0 = OldExtract.getOperand(0);
23296 unsigned VecSize = ExtOp0.getValueSizeInBits();
23297 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23298 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
23299 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23300 BitCast, OldExtract.getOperand(1));
23301 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23302 St->getPointerInfo(), St->isVolatile(),
23303 St->isNonTemporal(), St->getAlignment());
23309 /// Return 'true' if this vector operation is "horizontal"
23310 /// and return the operands for the horizontal operation in LHS and RHS. A
23311 /// horizontal operation performs the binary operation on successive elements
23312 /// of its first operand, then on successive elements of its second operand,
23313 /// returning the resulting values in a vector. For example, if
23314 /// A = < float a0, float a1, float a2, float a3 >
23316 /// B = < float b0, float b1, float b2, float b3 >
23317 /// then the result of doing a horizontal operation on A and B is
23318 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23319 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23320 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23321 /// set to A, RHS to B, and the routine returns 'true'.
23322 /// Note that the binary operation should have the property that if one of the
23323 /// operands is UNDEF then the result is UNDEF.
23324 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23325 // Look for the following pattern: if
23326 // A = < float a0, float a1, float a2, float a3 >
23327 // B = < float b0, float b1, float b2, float b3 >
23329 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23330 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23331 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23332 // which is A horizontal-op B.
23334 // At least one of the operands should be a vector shuffle.
23335 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23336 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23339 MVT VT = LHS.getSimpleValueType();
23341 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23342 "Unsupported vector type for horizontal add/sub");
23344 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23345 // operate independently on 128-bit lanes.
23346 unsigned NumElts = VT.getVectorNumElements();
23347 unsigned NumLanes = VT.getSizeInBits()/128;
23348 unsigned NumLaneElts = NumElts / NumLanes;
23349 assert((NumLaneElts % 2 == 0) &&
23350 "Vector type should have an even number of elements in each lane");
23351 unsigned HalfLaneElts = NumLaneElts/2;
23353 // View LHS in the form
23354 // LHS = VECTOR_SHUFFLE A, B, LMask
23355 // If LHS is not a shuffle then pretend it is the shuffle
23356 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23357 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23360 SmallVector<int, 16> LMask(NumElts);
23361 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23362 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23363 A = LHS.getOperand(0);
23364 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23365 B = LHS.getOperand(1);
23366 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23367 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23369 if (LHS.getOpcode() != ISD::UNDEF)
23371 for (unsigned i = 0; i != NumElts; ++i)
23375 // Likewise, view RHS in the form
23376 // RHS = VECTOR_SHUFFLE C, D, RMask
23378 SmallVector<int, 16> RMask(NumElts);
23379 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23380 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23381 C = RHS.getOperand(0);
23382 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23383 D = RHS.getOperand(1);
23384 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23385 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23387 if (RHS.getOpcode() != ISD::UNDEF)
23389 for (unsigned i = 0; i != NumElts; ++i)
23393 // Check that the shuffles are both shuffling the same vectors.
23394 if (!(A == C && B == D) && !(A == D && B == C))
23397 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23398 if (!A.getNode() && !B.getNode())
23401 // If A and B occur in reverse order in RHS, then "swap" them (which means
23402 // rewriting the mask).
23404 ShuffleVectorSDNode::commuteMask(RMask);
23406 // At this point LHS and RHS are equivalent to
23407 // LHS = VECTOR_SHUFFLE A, B, LMask
23408 // RHS = VECTOR_SHUFFLE A, B, RMask
23409 // Check that the masks correspond to performing a horizontal operation.
23410 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23411 for (unsigned i = 0; i != NumLaneElts; ++i) {
23412 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23414 // Ignore any UNDEF components.
23415 if (LIdx < 0 || RIdx < 0 ||
23416 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23417 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23420 // Check that successive elements are being operated on. If not, this is
23421 // not a horizontal operation.
23422 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23423 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23424 if (!(LIdx == Index && RIdx == Index + 1) &&
23425 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23430 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23431 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23435 /// Do target-specific dag combines on floating point adds.
23436 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23437 const X86Subtarget *Subtarget) {
23438 EVT VT = N->getValueType(0);
23439 SDValue LHS = N->getOperand(0);
23440 SDValue RHS = N->getOperand(1);
23442 // Try to synthesize horizontal adds from adds of shuffles.
23443 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23444 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23445 isHorizontalBinOp(LHS, RHS, true))
23446 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23450 /// Do target-specific dag combines on floating point subs.
23451 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23452 const X86Subtarget *Subtarget) {
23453 EVT VT = N->getValueType(0);
23454 SDValue LHS = N->getOperand(0);
23455 SDValue RHS = N->getOperand(1);
23457 // Try to synthesize horizontal subs from subs of shuffles.
23458 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23459 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23460 isHorizontalBinOp(LHS, RHS, false))
23461 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23465 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23466 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23467 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23469 // F[X]OR(0.0, x) -> x
23470 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23471 if (C->getValueAPF().isPosZero())
23472 return N->getOperand(1);
23474 // F[X]OR(x, 0.0) -> x
23475 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23476 if (C->getValueAPF().isPosZero())
23477 return N->getOperand(0);
23481 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23482 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23483 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23485 // Only perform optimizations if UnsafeMath is used.
23486 if (!DAG.getTarget().Options.UnsafeFPMath)
23489 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23490 // into FMINC and FMAXC, which are Commutative operations.
23491 unsigned NewOp = 0;
23492 switch (N->getOpcode()) {
23493 default: llvm_unreachable("unknown opcode");
23494 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23495 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23498 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23499 N->getOperand(0), N->getOperand(1));
23502 /// Do target-specific dag combines on X86ISD::FAND nodes.
23503 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23504 // FAND(0.0, x) -> 0.0
23505 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23506 if (C->getValueAPF().isPosZero())
23507 return N->getOperand(0);
23509 // FAND(x, 0.0) -> 0.0
23510 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23511 if (C->getValueAPF().isPosZero())
23512 return N->getOperand(1);
23517 /// Do target-specific dag combines on X86ISD::FANDN nodes
23518 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23519 // FANDN(0.0, x) -> x
23520 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23521 if (C->getValueAPF().isPosZero())
23522 return N->getOperand(1);
23524 // FANDN(x, 0.0) -> 0.0
23525 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23526 if (C->getValueAPF().isPosZero())
23527 return N->getOperand(1);
23532 static SDValue PerformBTCombine(SDNode *N,
23534 TargetLowering::DAGCombinerInfo &DCI) {
23535 // BT ignores high bits in the bit index operand.
23536 SDValue Op1 = N->getOperand(1);
23537 if (Op1.hasOneUse()) {
23538 unsigned BitWidth = Op1.getValueSizeInBits();
23539 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23540 APInt KnownZero, KnownOne;
23541 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23542 !DCI.isBeforeLegalizeOps());
23543 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23544 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23545 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23546 DCI.CommitTargetLoweringOpt(TLO);
23551 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23552 SDValue Op = N->getOperand(0);
23553 if (Op.getOpcode() == ISD::BITCAST)
23554 Op = Op.getOperand(0);
23555 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23556 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23557 VT.getVectorElementType().getSizeInBits() ==
23558 OpVT.getVectorElementType().getSizeInBits()) {
23559 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23564 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23565 const X86Subtarget *Subtarget) {
23566 EVT VT = N->getValueType(0);
23567 if (!VT.isVector())
23570 SDValue N0 = N->getOperand(0);
23571 SDValue N1 = N->getOperand(1);
23572 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23575 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23576 // both SSE and AVX2 since there is no sign-extended shift right
23577 // operation on a vector with 64-bit elements.
23578 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23579 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23580 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23581 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23582 SDValue N00 = N0.getOperand(0);
23584 // EXTLOAD has a better solution on AVX2,
23585 // it may be replaced with X86ISD::VSEXT node.
23586 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23587 if (!ISD::isNormalLoad(N00.getNode()))
23590 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23591 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23593 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23599 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23600 TargetLowering::DAGCombinerInfo &DCI,
23601 const X86Subtarget *Subtarget) {
23602 SDValue N0 = N->getOperand(0);
23603 EVT VT = N->getValueType(0);
23605 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23606 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23607 // This exposes the sext to the sdivrem lowering, so that it directly extends
23608 // from AH (which we otherwise need to do contortions to access).
23609 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23610 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
23612 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23613 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
23614 N0.getOperand(0), N0.getOperand(1));
23615 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23616 return R.getValue(1);
23619 if (!DCI.isBeforeLegalizeOps())
23622 if (!Subtarget->hasFp256())
23625 if (VT.isVector() && VT.getSizeInBits() == 256) {
23626 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23634 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23635 const X86Subtarget* Subtarget) {
23637 EVT VT = N->getValueType(0);
23639 // Let legalize expand this if it isn't a legal type yet.
23640 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23643 EVT ScalarVT = VT.getScalarType();
23644 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23645 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23648 SDValue A = N->getOperand(0);
23649 SDValue B = N->getOperand(1);
23650 SDValue C = N->getOperand(2);
23652 bool NegA = (A.getOpcode() == ISD::FNEG);
23653 bool NegB = (B.getOpcode() == ISD::FNEG);
23654 bool NegC = (C.getOpcode() == ISD::FNEG);
23656 // Negative multiplication when NegA xor NegB
23657 bool NegMul = (NegA != NegB);
23659 A = A.getOperand(0);
23661 B = B.getOperand(0);
23663 C = C.getOperand(0);
23667 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23669 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23671 return DAG.getNode(Opcode, dl, VT, A, B, C);
23674 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23675 TargetLowering::DAGCombinerInfo &DCI,
23676 const X86Subtarget *Subtarget) {
23677 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23678 // (and (i32 x86isd::setcc_carry), 1)
23679 // This eliminates the zext. This transformation is necessary because
23680 // ISD::SETCC is always legalized to i8.
23682 SDValue N0 = N->getOperand(0);
23683 EVT VT = N->getValueType(0);
23685 if (N0.getOpcode() == ISD::AND &&
23687 N0.getOperand(0).hasOneUse()) {
23688 SDValue N00 = N0.getOperand(0);
23689 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23690 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23691 if (!C || C->getZExtValue() != 1)
23693 return DAG.getNode(ISD::AND, dl, VT,
23694 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23695 N00.getOperand(0), N00.getOperand(1)),
23696 DAG.getConstant(1, dl, VT));
23700 if (N0.getOpcode() == ISD::TRUNCATE &&
23702 N0.getOperand(0).hasOneUse()) {
23703 SDValue N00 = N0.getOperand(0);
23704 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23705 return DAG.getNode(ISD::AND, dl, VT,
23706 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23707 N00.getOperand(0), N00.getOperand(1)),
23708 DAG.getConstant(1, dl, VT));
23711 if (VT.is256BitVector()) {
23712 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23717 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23718 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23719 // This exposes the zext to the udivrem lowering, so that it directly extends
23720 // from AH (which we otherwise need to do contortions to access).
23721 if (N0.getOpcode() == ISD::UDIVREM &&
23722 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23723 (VT == MVT::i32 || VT == MVT::i64)) {
23724 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23725 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23726 N0.getOperand(0), N0.getOperand(1));
23727 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23728 return R.getValue(1);
23734 // Optimize x == -y --> x+y == 0
23735 // x != -y --> x+y != 0
23736 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23737 const X86Subtarget* Subtarget) {
23738 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23739 SDValue LHS = N->getOperand(0);
23740 SDValue RHS = N->getOperand(1);
23741 EVT VT = N->getValueType(0);
23744 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23745 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23746 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23747 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
23748 LHS.getOperand(1));
23749 return DAG.getSetCC(DL, N->getValueType(0), addV,
23750 DAG.getConstant(0, DL, addV.getValueType()), CC);
23752 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23753 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23754 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23755 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
23756 RHS.getOperand(1));
23757 return DAG.getSetCC(DL, N->getValueType(0), addV,
23758 DAG.getConstant(0, DL, addV.getValueType()), CC);
23761 if (VT.getScalarType() == MVT::i1 &&
23762 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
23764 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23765 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23766 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23768 if (!IsSEXT0 || !IsVZero1) {
23769 // Swap the operands and update the condition code.
23770 std::swap(LHS, RHS);
23771 CC = ISD::getSetCCSwappedOperands(CC);
23773 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23774 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23775 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23778 if (IsSEXT0 && IsVZero1) {
23779 assert(VT == LHS.getOperand(0).getValueType() &&
23780 "Uexpected operand type");
23781 if (CC == ISD::SETGT)
23782 return DAG.getConstant(0, DL, VT);
23783 if (CC == ISD::SETLE)
23784 return DAG.getConstant(1, DL, VT);
23785 if (CC == ISD::SETEQ || CC == ISD::SETGE)
23786 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23788 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
23789 "Unexpected condition code!");
23790 return LHS.getOperand(0);
23797 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
23798 SelectionDAG &DAG) {
23800 MVT VT = Load->getSimpleValueType(0);
23801 MVT EVT = VT.getVectorElementType();
23802 SDValue Addr = Load->getOperand(1);
23803 SDValue NewAddr = DAG.getNode(
23804 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
23805 DAG.getConstant(Index * EVT.getStoreSize(), dl,
23806 Addr.getSimpleValueType()));
23809 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
23810 DAG.getMachineFunction().getMachineMemOperand(
23811 Load->getMemOperand(), 0, EVT.getStoreSize()));
23815 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23816 const X86Subtarget *Subtarget) {
23818 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23819 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23820 "X86insertps is only defined for v4x32");
23822 SDValue Ld = N->getOperand(1);
23823 if (MayFoldLoad(Ld)) {
23824 // Extract the countS bits from the immediate so we can get the proper
23825 // address when narrowing the vector load to a specific element.
23826 // When the second source op is a memory address, insertps doesn't use
23827 // countS and just gets an f32 from that address.
23828 unsigned DestIndex =
23829 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23831 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23833 // Create this as a scalar to vector to match the instruction pattern.
23834 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23835 // countS bits are ignored when loading from memory on insertps, which
23836 // means we don't need to explicitly set them to 0.
23837 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23838 LoadScalarToVector, N->getOperand(2));
23843 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
23844 SDValue V0 = N->getOperand(0);
23845 SDValue V1 = N->getOperand(1);
23847 EVT VT = N->getValueType(0);
23849 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23850 // operands and changing the mask to 1. This saves us a bunch of
23851 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23852 // x86InstrInfo knows how to commute this back after instruction selection
23853 // if it would help register allocation.
23855 // TODO: If optimizing for size or a processor that doesn't suffer from
23856 // partial register update stalls, this should be transformed into a MOVSD
23857 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23859 if (VT == MVT::v2f64)
23860 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23861 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23862 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
23863 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23869 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23870 // as "sbb reg,reg", since it can be extended without zext and produces
23871 // an all-ones bit which is more useful than 0/1 in some cases.
23872 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23875 return DAG.getNode(ISD::AND, DL, VT,
23876 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23877 DAG.getConstant(X86::COND_B, DL, MVT::i8),
23879 DAG.getConstant(1, DL, VT));
23880 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23881 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23882 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23883 DAG.getConstant(X86::COND_B, DL, MVT::i8),
23887 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23888 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23889 TargetLowering::DAGCombinerInfo &DCI,
23890 const X86Subtarget *Subtarget) {
23892 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23893 SDValue EFLAGS = N->getOperand(1);
23895 if (CC == X86::COND_A) {
23896 // Try to convert COND_A into COND_B in an attempt to facilitate
23897 // materializing "setb reg".
23899 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23900 // cannot take an immediate as its first operand.
23902 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23903 EFLAGS.getValueType().isInteger() &&
23904 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23905 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23906 EFLAGS.getNode()->getVTList(),
23907 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23908 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23909 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23913 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23914 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23916 if (CC == X86::COND_B)
23917 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23921 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23922 if (Flags.getNode()) {
23923 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
23924 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23930 // Optimize branch condition evaluation.
23932 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23933 TargetLowering::DAGCombinerInfo &DCI,
23934 const X86Subtarget *Subtarget) {
23936 SDValue Chain = N->getOperand(0);
23937 SDValue Dest = N->getOperand(1);
23938 SDValue EFLAGS = N->getOperand(3);
23939 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23943 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23944 if (Flags.getNode()) {
23945 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
23946 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23953 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23954 SelectionDAG &DAG) {
23955 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23956 // optimize away operation when it's from a constant.
23958 // The general transformation is:
23959 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23960 // AND(VECTOR_CMP(x,y), constant2)
23961 // constant2 = UNARYOP(constant)
23963 // Early exit if this isn't a vector operation, the operand of the
23964 // unary operation isn't a bitwise AND, or if the sizes of the operations
23965 // aren't the same.
23966 EVT VT = N->getValueType(0);
23967 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23968 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23969 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23972 // Now check that the other operand of the AND is a constant. We could
23973 // make the transformation for non-constant splats as well, but it's unclear
23974 // that would be a benefit as it would not eliminate any operations, just
23975 // perform one more step in scalar code before moving to the vector unit.
23976 if (BuildVectorSDNode *BV =
23977 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23978 // Bail out if the vector isn't a constant.
23979 if (!BV->isConstant())
23982 // Everything checks out. Build up the new and improved node.
23984 EVT IntVT = BV->getValueType(0);
23985 // Create a new constant of the appropriate type for the transformed
23987 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23988 // The AND node needs bitcasts to/from an integer vector type around it.
23989 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23990 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23991 N->getOperand(0)->getOperand(0), MaskConst);
23992 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23999 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24000 const X86Subtarget *Subtarget) {
24001 // First try to optimize away the conversion entirely when it's
24002 // conditionally from a constant. Vectors only.
24003 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24004 if (Res != SDValue())
24007 // Now move on to more general possibilities.
24008 SDValue Op0 = N->getOperand(0);
24009 EVT InVT = Op0->getValueType(0);
24011 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24012 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24014 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24015 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24016 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24019 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24020 // a 32-bit target where SSE doesn't support i64->FP operations.
24021 if (Op0.getOpcode() == ISD::LOAD) {
24022 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24023 EVT VT = Ld->getValueType(0);
24025 // This transformation is not supported if the result type is f16
24026 if (N->getValueType(0) == MVT::f16)
24029 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24030 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24031 !Subtarget->is64Bit() && VT == MVT::i64) {
24032 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24033 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24034 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24041 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24042 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24043 X86TargetLowering::DAGCombinerInfo &DCI) {
24044 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24045 // the result is either zero or one (depending on the input carry bit).
24046 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24047 if (X86::isZeroNode(N->getOperand(0)) &&
24048 X86::isZeroNode(N->getOperand(1)) &&
24049 // We don't have a good way to replace an EFLAGS use, so only do this when
24051 SDValue(N, 1).use_empty()) {
24053 EVT VT = N->getValueType(0);
24054 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24055 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24056 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24057 DAG.getConstant(X86::COND_B, DL,
24060 DAG.getConstant(1, DL, VT));
24061 return DCI.CombineTo(N, Res1, CarryOut);
24067 // fold (add Y, (sete X, 0)) -> adc 0, Y
24068 // (add Y, (setne X, 0)) -> sbb -1, Y
24069 // (sub (sete X, 0), Y) -> sbb 0, Y
24070 // (sub (setne X, 0), Y) -> adc -1, Y
24071 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24074 // Look through ZExts.
24075 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24076 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24079 SDValue SetCC = Ext.getOperand(0);
24080 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24083 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24084 if (CC != X86::COND_E && CC != X86::COND_NE)
24087 SDValue Cmp = SetCC.getOperand(1);
24088 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24089 !X86::isZeroNode(Cmp.getOperand(1)) ||
24090 !Cmp.getOperand(0).getValueType().isInteger())
24093 SDValue CmpOp0 = Cmp.getOperand(0);
24094 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24095 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24097 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24098 if (CC == X86::COND_NE)
24099 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24100 DL, OtherVal.getValueType(), OtherVal,
24101 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24103 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24104 DL, OtherVal.getValueType(), OtherVal,
24105 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24108 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24109 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24110 const X86Subtarget *Subtarget) {
24111 EVT VT = N->getValueType(0);
24112 SDValue Op0 = N->getOperand(0);
24113 SDValue Op1 = N->getOperand(1);
24115 // Try to synthesize horizontal adds from adds of shuffles.
24116 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24117 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24118 isHorizontalBinOp(Op0, Op1, true))
24119 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24121 return OptimizeConditionalInDecrement(N, DAG);
24124 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24125 const X86Subtarget *Subtarget) {
24126 SDValue Op0 = N->getOperand(0);
24127 SDValue Op1 = N->getOperand(1);
24129 // X86 can't encode an immediate LHS of a sub. See if we can push the
24130 // negation into a preceding instruction.
24131 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24132 // If the RHS of the sub is a XOR with one use and a constant, invert the
24133 // immediate. Then add one to the LHS of the sub so we can turn
24134 // X-Y -> X+~Y+1, saving one register.
24135 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24136 isa<ConstantSDNode>(Op1.getOperand(1))) {
24137 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24138 EVT VT = Op0.getValueType();
24139 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24141 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24142 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24143 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24147 // Try to synthesize horizontal adds from adds of shuffles.
24148 EVT VT = N->getValueType(0);
24149 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24150 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24151 isHorizontalBinOp(Op0, Op1, true))
24152 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24154 return OptimizeConditionalInDecrement(N, DAG);
24157 /// performVZEXTCombine - Performs build vector combines
24158 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24159 TargetLowering::DAGCombinerInfo &DCI,
24160 const X86Subtarget *Subtarget) {
24162 MVT VT = N->getSimpleValueType(0);
24163 SDValue Op = N->getOperand(0);
24164 MVT OpVT = Op.getSimpleValueType();
24165 MVT OpEltVT = OpVT.getVectorElementType();
24166 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24168 // (vzext (bitcast (vzext (x)) -> (vzext x)
24170 while (V.getOpcode() == ISD::BITCAST)
24171 V = V.getOperand(0);
24173 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24174 MVT InnerVT = V.getSimpleValueType();
24175 MVT InnerEltVT = InnerVT.getVectorElementType();
24177 // If the element sizes match exactly, we can just do one larger vzext. This
24178 // is always an exact type match as vzext operates on integer types.
24179 if (OpEltVT == InnerEltVT) {
24180 assert(OpVT == InnerVT && "Types must match for vzext!");
24181 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24184 // The only other way we can combine them is if only a single element of the
24185 // inner vzext is used in the input to the outer vzext.
24186 if (InnerEltVT.getSizeInBits() < InputBits)
24189 // In this case, the inner vzext is completely dead because we're going to
24190 // only look at bits inside of the low element. Just do the outer vzext on
24191 // a bitcast of the input to the inner.
24192 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24193 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24196 // Check if we can bypass extracting and re-inserting an element of an input
24197 // vector. Essentialy:
24198 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24199 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24200 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24201 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24202 SDValue ExtractedV = V.getOperand(0);
24203 SDValue OrigV = ExtractedV.getOperand(0);
24204 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24205 if (ExtractIdx->getZExtValue() == 0) {
24206 MVT OrigVT = OrigV.getSimpleValueType();
24207 // Extract a subvector if necessary...
24208 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24209 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24210 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24211 OrigVT.getVectorNumElements() / Ratio);
24212 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24213 DAG.getIntPtrConstant(0, DL));
24215 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24216 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24223 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24224 DAGCombinerInfo &DCI) const {
24225 SelectionDAG &DAG = DCI.DAG;
24226 switch (N->getOpcode()) {
24228 case ISD::EXTRACT_VECTOR_ELT:
24229 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24232 case X86ISD::SHRUNKBLEND:
24233 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24234 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24235 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24236 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24237 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24238 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24239 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24242 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24243 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24244 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24245 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24246 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24247 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24248 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24249 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24250 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24251 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24252 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24254 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24256 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24257 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24258 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24259 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24260 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24261 case ISD::ANY_EXTEND:
24262 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24263 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24264 case ISD::SIGN_EXTEND_INREG:
24265 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24266 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24267 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24268 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24269 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24270 case X86ISD::SHUFP: // Handle all target specific shuffles
24271 case X86ISD::PALIGNR:
24272 case X86ISD::UNPCKH:
24273 case X86ISD::UNPCKL:
24274 case X86ISD::MOVHLPS:
24275 case X86ISD::MOVLHPS:
24276 case X86ISD::PSHUFB:
24277 case X86ISD::PSHUFD:
24278 case X86ISD::PSHUFHW:
24279 case X86ISD::PSHUFLW:
24280 case X86ISD::MOVSS:
24281 case X86ISD::MOVSD:
24282 case X86ISD::VPERMILPI:
24283 case X86ISD::VPERM2X128:
24284 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24285 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24286 case ISD::INTRINSIC_WO_CHAIN:
24287 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24288 case X86ISD::INSERTPS: {
24289 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24290 return PerformINSERTPSCombine(N, DAG, Subtarget);
24293 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24299 /// isTypeDesirableForOp - Return true if the target has native support for
24300 /// the specified value type and it is 'desirable' to use the type for the
24301 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24302 /// instruction encodings are longer and some i16 instructions are slow.
24303 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24304 if (!isTypeLegal(VT))
24306 if (VT != MVT::i16)
24313 case ISD::SIGN_EXTEND:
24314 case ISD::ZERO_EXTEND:
24315 case ISD::ANY_EXTEND:
24328 /// IsDesirableToPromoteOp - This method query the target whether it is
24329 /// beneficial for dag combiner to promote the specified node. If true, it
24330 /// should return the desired promotion type by reference.
24331 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24332 EVT VT = Op.getValueType();
24333 if (VT != MVT::i16)
24336 bool Promote = false;
24337 bool Commute = false;
24338 switch (Op.getOpcode()) {
24341 LoadSDNode *LD = cast<LoadSDNode>(Op);
24342 // If the non-extending load has a single use and it's not live out, then it
24343 // might be folded.
24344 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24345 Op.hasOneUse()*/) {
24346 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24347 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24348 // The only case where we'd want to promote LOAD (rather then it being
24349 // promoted as an operand is when it's only use is liveout.
24350 if (UI->getOpcode() != ISD::CopyToReg)
24357 case ISD::SIGN_EXTEND:
24358 case ISD::ZERO_EXTEND:
24359 case ISD::ANY_EXTEND:
24364 SDValue N0 = Op.getOperand(0);
24365 // Look out for (store (shl (load), x)).
24366 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24379 SDValue N0 = Op.getOperand(0);
24380 SDValue N1 = Op.getOperand(1);
24381 if (!Commute && MayFoldLoad(N1))
24383 // Avoid disabling potential load folding opportunities.
24384 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24386 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24396 //===----------------------------------------------------------------------===//
24397 // X86 Inline Assembly Support
24398 //===----------------------------------------------------------------------===//
24400 // Helper to match a string separated by whitespace.
24401 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24402 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24404 for (StringRef Piece : Pieces) {
24405 if (!S.startswith(Piece)) // Check if the piece matches.
24408 S = S.substr(Piece.size());
24409 StringRef::size_type Pos = S.find_first_not_of(" \t");
24410 if (Pos == 0) // We matched a prefix.
24419 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24421 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24422 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24423 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24424 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24426 if (AsmPieces.size() == 3)
24428 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24435 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24436 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24438 std::string AsmStr = IA->getAsmString();
24440 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24441 if (!Ty || Ty->getBitWidth() % 16 != 0)
24444 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24445 SmallVector<StringRef, 4> AsmPieces;
24446 SplitString(AsmStr, AsmPieces, ";\n");
24448 switch (AsmPieces.size()) {
24449 default: return false;
24451 // FIXME: this should verify that we are targeting a 486 or better. If not,
24452 // we will turn this bswap into something that will be lowered to logical
24453 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24454 // lower so don't worry about this.
24456 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24457 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24458 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24459 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24460 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24461 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24462 // No need to check constraints, nothing other than the equivalent of
24463 // "=r,0" would be valid here.
24464 return IntrinsicLowering::LowerToByteSwap(CI);
24467 // rorw $$8, ${0:w} --> llvm.bswap.i16
24468 if (CI->getType()->isIntegerTy(16) &&
24469 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24470 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24471 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24473 const std::string &ConstraintsStr = IA->getConstraintString();
24474 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24475 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24476 if (clobbersFlagRegisters(AsmPieces))
24477 return IntrinsicLowering::LowerToByteSwap(CI);
24481 if (CI->getType()->isIntegerTy(32) &&
24482 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24483 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24484 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24485 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24487 const std::string &ConstraintsStr = IA->getConstraintString();
24488 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24489 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24490 if (clobbersFlagRegisters(AsmPieces))
24491 return IntrinsicLowering::LowerToByteSwap(CI);
24494 if (CI->getType()->isIntegerTy(64)) {
24495 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24496 if (Constraints.size() >= 2 &&
24497 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24498 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24499 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24500 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24501 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24502 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24503 return IntrinsicLowering::LowerToByteSwap(CI);
24511 /// getConstraintType - Given a constraint letter, return the type of
24512 /// constraint it is for this target.
24513 X86TargetLowering::ConstraintType
24514 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24515 if (Constraint.size() == 1) {
24516 switch (Constraint[0]) {
24527 return C_RegisterClass;
24551 return TargetLowering::getConstraintType(Constraint);
24554 /// Examine constraint type and operand type and determine a weight value.
24555 /// This object must already have been set up with the operand type
24556 /// and the current alternative constraint selected.
24557 TargetLowering::ConstraintWeight
24558 X86TargetLowering::getSingleConstraintMatchWeight(
24559 AsmOperandInfo &info, const char *constraint) const {
24560 ConstraintWeight weight = CW_Invalid;
24561 Value *CallOperandVal = info.CallOperandVal;
24562 // If we don't have a value, we can't do a match,
24563 // but allow it at the lowest weight.
24564 if (!CallOperandVal)
24566 Type *type = CallOperandVal->getType();
24567 // Look at the constraint type.
24568 switch (*constraint) {
24570 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24581 if (CallOperandVal->getType()->isIntegerTy())
24582 weight = CW_SpecificReg;
24587 if (type->isFloatingPointTy())
24588 weight = CW_SpecificReg;
24591 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24592 weight = CW_SpecificReg;
24596 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24597 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24598 weight = CW_Register;
24601 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24602 if (C->getZExtValue() <= 31)
24603 weight = CW_Constant;
24607 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24608 if (C->getZExtValue() <= 63)
24609 weight = CW_Constant;
24613 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24614 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24615 weight = CW_Constant;
24619 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24620 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24621 weight = CW_Constant;
24625 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24626 if (C->getZExtValue() <= 3)
24627 weight = CW_Constant;
24631 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24632 if (C->getZExtValue() <= 0xff)
24633 weight = CW_Constant;
24638 if (isa<ConstantFP>(CallOperandVal)) {
24639 weight = CW_Constant;
24643 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24644 if ((C->getSExtValue() >= -0x80000000LL) &&
24645 (C->getSExtValue() <= 0x7fffffffLL))
24646 weight = CW_Constant;
24650 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24651 if (C->getZExtValue() <= 0xffffffff)
24652 weight = CW_Constant;
24659 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24660 /// with another that has more specific requirements based on the type of the
24661 /// corresponding operand.
24662 const char *X86TargetLowering::
24663 LowerXConstraint(EVT ConstraintVT) const {
24664 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24665 // 'f' like normal targets.
24666 if (ConstraintVT.isFloatingPoint()) {
24667 if (Subtarget->hasSSE2())
24669 if (Subtarget->hasSSE1())
24673 return TargetLowering::LowerXConstraint(ConstraintVT);
24676 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24677 /// vector. If it is invalid, don't add anything to Ops.
24678 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24679 std::string &Constraint,
24680 std::vector<SDValue>&Ops,
24681 SelectionDAG &DAG) const {
24684 // Only support length 1 constraints for now.
24685 if (Constraint.length() > 1) return;
24687 char ConstraintLetter = Constraint[0];
24688 switch (ConstraintLetter) {
24691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24692 if (C->getZExtValue() <= 31) {
24693 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24694 Op.getValueType());
24700 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24701 if (C->getZExtValue() <= 63) {
24702 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24703 Op.getValueType());
24709 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24710 if (isInt<8>(C->getSExtValue())) {
24711 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24712 Op.getValueType());
24718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24719 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24720 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24721 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
24722 Op.getValueType());
24728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24729 if (C->getZExtValue() <= 3) {
24730 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24731 Op.getValueType());
24737 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24738 if (C->getZExtValue() <= 255) {
24739 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24740 Op.getValueType());
24746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24747 if (C->getZExtValue() <= 127) {
24748 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24749 Op.getValueType());
24755 // 32-bit signed value
24756 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24757 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24758 C->getSExtValue())) {
24759 // Widen to 64 bits here to get it sign extended.
24760 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
24763 // FIXME gcc accepts some relocatable values here too, but only in certain
24764 // memory models; it's complicated.
24769 // 32-bit unsigned value
24770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24771 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24772 C->getZExtValue())) {
24773 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24774 Op.getValueType());
24778 // FIXME gcc accepts some relocatable values here too, but only in certain
24779 // memory models; it's complicated.
24783 // Literal immediates are always ok.
24784 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24785 // Widen to 64 bits here to get it sign extended.
24786 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
24790 // In any sort of PIC mode addresses need to be computed at runtime by
24791 // adding in a register or some sort of table lookup. These can't
24792 // be used as immediates.
24793 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24796 // If we are in non-pic codegen mode, we allow the address of a global (with
24797 // an optional displacement) to be used with 'i'.
24798 GlobalAddressSDNode *GA = nullptr;
24799 int64_t Offset = 0;
24801 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24803 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24804 Offset += GA->getOffset();
24806 } else if (Op.getOpcode() == ISD::ADD) {
24807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24808 Offset += C->getZExtValue();
24809 Op = Op.getOperand(0);
24812 } else if (Op.getOpcode() == ISD::SUB) {
24813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24814 Offset += -C->getZExtValue();
24815 Op = Op.getOperand(0);
24820 // Otherwise, this isn't something we can handle, reject it.
24824 const GlobalValue *GV = GA->getGlobal();
24825 // If we require an extra load to get this address, as in PIC mode, we
24826 // can't accept it.
24827 if (isGlobalStubReference(
24828 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24831 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24832 GA->getValueType(0), Offset);
24837 if (Result.getNode()) {
24838 Ops.push_back(Result);
24841 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24844 std::pair<unsigned, const TargetRegisterClass *>
24845 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
24846 const std::string &Constraint,
24848 // First, see if this is a constraint that directly corresponds to an LLVM
24850 if (Constraint.size() == 1) {
24851 // GCC Constraint Letters
24852 switch (Constraint[0]) {
24854 // TODO: Slight differences here in allocation order and leaving
24855 // RIP in the class. Do they matter any more here than they do
24856 // in the normal allocation?
24857 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24858 if (Subtarget->is64Bit()) {
24859 if (VT == MVT::i32 || VT == MVT::f32)
24860 return std::make_pair(0U, &X86::GR32RegClass);
24861 if (VT == MVT::i16)
24862 return std::make_pair(0U, &X86::GR16RegClass);
24863 if (VT == MVT::i8 || VT == MVT::i1)
24864 return std::make_pair(0U, &X86::GR8RegClass);
24865 if (VT == MVT::i64 || VT == MVT::f64)
24866 return std::make_pair(0U, &X86::GR64RegClass);
24869 // 32-bit fallthrough
24870 case 'Q': // Q_REGS
24871 if (VT == MVT::i32 || VT == MVT::f32)
24872 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24873 if (VT == MVT::i16)
24874 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24875 if (VT == MVT::i8 || VT == MVT::i1)
24876 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24877 if (VT == MVT::i64)
24878 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24880 case 'r': // GENERAL_REGS
24881 case 'l': // INDEX_REGS
24882 if (VT == MVT::i8 || VT == MVT::i1)
24883 return std::make_pair(0U, &X86::GR8RegClass);
24884 if (VT == MVT::i16)
24885 return std::make_pair(0U, &X86::GR16RegClass);
24886 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24887 return std::make_pair(0U, &X86::GR32RegClass);
24888 return std::make_pair(0U, &X86::GR64RegClass);
24889 case 'R': // LEGACY_REGS
24890 if (VT == MVT::i8 || VT == MVT::i1)
24891 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24892 if (VT == MVT::i16)
24893 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24894 if (VT == MVT::i32 || !Subtarget->is64Bit())
24895 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24896 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24897 case 'f': // FP Stack registers.
24898 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24899 // value to the correct fpstack register class.
24900 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24901 return std::make_pair(0U, &X86::RFP32RegClass);
24902 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24903 return std::make_pair(0U, &X86::RFP64RegClass);
24904 return std::make_pair(0U, &X86::RFP80RegClass);
24905 case 'y': // MMX_REGS if MMX allowed.
24906 if (!Subtarget->hasMMX()) break;
24907 return std::make_pair(0U, &X86::VR64RegClass);
24908 case 'Y': // SSE_REGS if SSE2 allowed
24909 if (!Subtarget->hasSSE2()) break;
24911 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24912 if (!Subtarget->hasSSE1()) break;
24914 switch (VT.SimpleTy) {
24916 // Scalar SSE types.
24919 return std::make_pair(0U, &X86::FR32RegClass);
24922 return std::make_pair(0U, &X86::FR64RegClass);
24930 return std::make_pair(0U, &X86::VR128RegClass);
24938 return std::make_pair(0U, &X86::VR256RegClass);
24943 return std::make_pair(0U, &X86::VR512RegClass);
24949 // Use the default implementation in TargetLowering to convert the register
24950 // constraint into a member of a register class.
24951 std::pair<unsigned, const TargetRegisterClass*> Res;
24952 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
24954 // Not found as a standard register?
24956 // Map st(0) -> st(7) -> ST0
24957 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24958 tolower(Constraint[1]) == 's' &&
24959 tolower(Constraint[2]) == 't' &&
24960 Constraint[3] == '(' &&
24961 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24962 Constraint[5] == ')' &&
24963 Constraint[6] == '}') {
24965 Res.first = X86::FP0+Constraint[4]-'0';
24966 Res.second = &X86::RFP80RegClass;
24970 // GCC allows "st(0)" to be called just plain "st".
24971 if (StringRef("{st}").equals_lower(Constraint)) {
24972 Res.first = X86::FP0;
24973 Res.second = &X86::RFP80RegClass;
24978 if (StringRef("{flags}").equals_lower(Constraint)) {
24979 Res.first = X86::EFLAGS;
24980 Res.second = &X86::CCRRegClass;
24984 // 'A' means EAX + EDX.
24985 if (Constraint == "A") {
24986 Res.first = X86::EAX;
24987 Res.second = &X86::GR32_ADRegClass;
24993 // Otherwise, check to see if this is a register class of the wrong value
24994 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24995 // turn into {ax},{dx}.
24996 if (Res.second->hasType(VT))
24997 return Res; // Correct type already, nothing to do.
24999 // All of the single-register GCC register classes map their values onto
25000 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25001 // really want an 8-bit or 32-bit register, map to the appropriate register
25002 // class and return the appropriate register.
25003 if (Res.second == &X86::GR16RegClass) {
25004 if (VT == MVT::i8 || VT == MVT::i1) {
25005 unsigned DestReg = 0;
25006 switch (Res.first) {
25008 case X86::AX: DestReg = X86::AL; break;
25009 case X86::DX: DestReg = X86::DL; break;
25010 case X86::CX: DestReg = X86::CL; break;
25011 case X86::BX: DestReg = X86::BL; break;
25014 Res.first = DestReg;
25015 Res.second = &X86::GR8RegClass;
25017 } else if (VT == MVT::i32 || VT == MVT::f32) {
25018 unsigned DestReg = 0;
25019 switch (Res.first) {
25021 case X86::AX: DestReg = X86::EAX; break;
25022 case X86::DX: DestReg = X86::EDX; break;
25023 case X86::CX: DestReg = X86::ECX; break;
25024 case X86::BX: DestReg = X86::EBX; break;
25025 case X86::SI: DestReg = X86::ESI; break;
25026 case X86::DI: DestReg = X86::EDI; break;
25027 case X86::BP: DestReg = X86::EBP; break;
25028 case X86::SP: DestReg = X86::ESP; break;
25031 Res.first = DestReg;
25032 Res.second = &X86::GR32RegClass;
25034 } else if (VT == MVT::i64 || VT == MVT::f64) {
25035 unsigned DestReg = 0;
25036 switch (Res.first) {
25038 case X86::AX: DestReg = X86::RAX; break;
25039 case X86::DX: DestReg = X86::RDX; break;
25040 case X86::CX: DestReg = X86::RCX; break;
25041 case X86::BX: DestReg = X86::RBX; break;
25042 case X86::SI: DestReg = X86::RSI; break;
25043 case X86::DI: DestReg = X86::RDI; break;
25044 case X86::BP: DestReg = X86::RBP; break;
25045 case X86::SP: DestReg = X86::RSP; break;
25048 Res.first = DestReg;
25049 Res.second = &X86::GR64RegClass;
25052 } else if (Res.second == &X86::FR32RegClass ||
25053 Res.second == &X86::FR64RegClass ||
25054 Res.second == &X86::VR128RegClass ||
25055 Res.second == &X86::VR256RegClass ||
25056 Res.second == &X86::FR32XRegClass ||
25057 Res.second == &X86::FR64XRegClass ||
25058 Res.second == &X86::VR128XRegClass ||
25059 Res.second == &X86::VR256XRegClass ||
25060 Res.second == &X86::VR512RegClass) {
25061 // Handle references to XMM physical registers that got mapped into the
25062 // wrong class. This can happen with constraints like {xmm0} where the
25063 // target independent register mapper will just pick the first match it can
25064 // find, ignoring the required type.
25066 if (VT == MVT::f32 || VT == MVT::i32)
25067 Res.second = &X86::FR32RegClass;
25068 else if (VT == MVT::f64 || VT == MVT::i64)
25069 Res.second = &X86::FR64RegClass;
25070 else if (X86::VR128RegClass.hasType(VT))
25071 Res.second = &X86::VR128RegClass;
25072 else if (X86::VR256RegClass.hasType(VT))
25073 Res.second = &X86::VR256RegClass;
25074 else if (X86::VR512RegClass.hasType(VT))
25075 Res.second = &X86::VR512RegClass;
25081 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25083 // Scaling factors are not free at all.
25084 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25085 // will take 2 allocations in the out of order engine instead of 1
25086 // for plain addressing mode, i.e. inst (reg1).
25088 // vaddps (%rsi,%drx), %ymm0, %ymm1
25089 // Requires two allocations (one for the load, one for the computation)
25091 // vaddps (%rsi), %ymm0, %ymm1
25092 // Requires just 1 allocation, i.e., freeing allocations for other operations
25093 // and having less micro operations to execute.
25095 // For some X86 architectures, this is even worse because for instance for
25096 // stores, the complex addressing mode forces the instruction to use the
25097 // "load" ports instead of the dedicated "store" port.
25098 // E.g., on Haswell:
25099 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25100 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25101 if (isLegalAddressingMode(AM, Ty))
25102 // Scale represents reg2 * scale, thus account for 1
25103 // as soon as we use a second register.
25104 return AM.Scale != 0;
25108 bool X86TargetLowering::isTargetFTOL() const {
25109 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();