1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
57 using namespace dwarf;
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> UseRegMask("x86-use-regmask",
62 cl::desc("Use register masks for x86 calls"));
64 // Forward declarations.
65 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
68 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
69 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
70 /// simple subregister reference. Idx is an index in the 128 bits we
71 /// want. It need not be aligned to a 128-bit bounday. That makes
72 /// lowering EXTRACT_VECTOR_ELT operations easier.
73 static SDValue Extract128BitVector(SDValue Vec,
77 EVT VT = Vec.getValueType();
78 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
79 EVT ElVT = VT.getVectorElementType();
80 int Factor = VT.getSizeInBits()/128;
81 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
82 VT.getVectorNumElements()/Factor);
84 // Extract from UNDEF is UNDEF.
85 if (Vec.getOpcode() == ISD::UNDEF)
86 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
88 if (isa<ConstantSDNode>(Idx)) {
89 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
91 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
92 // we can match to VEXTRACTF128.
93 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
95 // This is the index of the first element of the 128-bit chunk
97 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
100 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
101 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
110 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
111 /// sets things up to match to an AVX VINSERTF128 instruction or a
112 /// simple superregister reference. Idx is an index in the 128 bits
113 /// we want. It need not be aligned to a 128-bit bounday. That makes
114 /// lowering INSERT_VECTOR_ELT operations easier.
115 static SDValue Insert128BitVector(SDValue Result,
120 if (isa<ConstantSDNode>(Idx)) {
121 EVT VT = Vec.getValueType();
122 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
124 EVT ElVT = VT.getVectorElementType();
125 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant 128 bits.
129 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
131 // This is the index of the first element of the 128-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
136 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
137 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
145 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
146 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
147 bool is64Bit = Subtarget->is64Bit();
149 if (Subtarget->isTargetEnvMacho()) {
151 return new X8664_MachoTargetObjectFile();
152 return new TargetLoweringObjectFileMachO();
155 if (Subtarget->isTargetELF())
156 return new TargetLoweringObjectFileELF();
157 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
158 return new TargetLoweringObjectFileCOFF();
159 llvm_unreachable("unknown subtarget type");
162 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
163 : TargetLowering(TM, createTLOF(TM)) {
164 Subtarget = &TM.getSubtarget<X86Subtarget>();
165 X86ScalarSSEf64 = Subtarget->hasSSE2();
166 X86ScalarSSEf32 = Subtarget->hasSSE1();
167 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
169 RegInfo = TM.getRegisterInfo();
170 TD = getTargetData();
172 // Set up the TargetLowering object.
173 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
175 // X86 is weird, it always uses i8 for shift amounts and setcc results.
176 setBooleanContents(ZeroOrOneBooleanContent);
177 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
178 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
180 // For 64-bit since we have so many registers use the ILP scheduler, for
181 // 32-bit code use the register pressure specific scheduling.
182 if (Subtarget->is64Bit())
183 setSchedulingPreference(Sched::ILP);
185 setSchedulingPreference(Sched::RegPressure);
186 setStackPointerRegisterToSaveRestore(X86StackPtr);
188 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
189 // Setup Windows compiler runtime calls.
190 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
191 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
192 setLibcallName(RTLIB::SREM_I64, "_allrem");
193 setLibcallName(RTLIB::UREM_I64, "_aullrem");
194 setLibcallName(RTLIB::MUL_I64, "_allmul");
195 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
196 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
197 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
198 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
199 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
200 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
201 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
203 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
206 if (Subtarget->isTargetDarwin()) {
207 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
208 setUseUnderscoreSetJmp(false);
209 setUseUnderscoreLongJmp(false);
210 } else if (Subtarget->isTargetMingw()) {
211 // MS runtime is weird: it exports _setjmp, but longjmp!
212 setUseUnderscoreSetJmp(true);
213 setUseUnderscoreLongJmp(false);
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(true);
219 // Set up the register classes.
220 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
221 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
222 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
223 if (Subtarget->is64Bit())
224 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
228 // We don't accept any truncstore of integer registers.
229 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
233 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
234 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
236 // SETOEQ and SETUNE require checking two conditions.
237 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
239 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
244 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
246 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
248 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
250 if (Subtarget->is64Bit()) {
251 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
253 } else if (!TM.Options.UseSoftFloat) {
254 // We have an algorithm for SSE2->double, and we turn this into a
255 // 64-bit FILD followed by conditional FADD for other targets.
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
257 // We have an algorithm for SSE2, and we turn this into a 64-bit
258 // FILD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
262 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
264 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
265 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
267 if (!TM.Options.UseSoftFloat) {
268 // SSE has no i16 to fp conversion, only i32
269 if (X86ScalarSSEf32) {
270 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
271 // f32 and f64 cases are Legal, f80 case is not
272 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
282 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
283 // are Legal, f80 is custom lowered.
284 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
287 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
289 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
290 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
292 if (X86ScalarSSEf32) {
293 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
294 // f32 and f64 cases are Legal, f80 case is not
295 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 // Handle FP_TO_UINT by promoting the destination to a larger signed
303 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
305 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
307 if (Subtarget->is64Bit()) {
308 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
310 } else if (!TM.Options.UseSoftFloat) {
311 // Since AVX is a superset of SSE3, only check for SSE here.
312 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
313 // Expand FP_TO_UINT into a select.
314 // FIXME: We would like to use a Custom expander here eventually to do
315 // the optimal thing for SSE vs. the default expansion in the legalizer.
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
318 // With SSE3 we can use fisttpll to convert to a signed i64; without
319 // SSE, we're stuck with a fistpll.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
323 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
324 if (!X86ScalarSSEf64) {
325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
329 // Without SSE, i64->f64 goes through memory.
330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
334 // Scalar integer divide and remainder are lowered to use operations that
335 // produce two results, to match the available instructions. This exposes
336 // the two-result form to trivial CSE, which is able to combine x/y and x%y
337 // into a single instruction.
339 // Scalar integer multiply-high is also lowered to use two-result
340 // operations, to match the available instructions. However, plain multiply
341 // (low) operations are left as Legal, as there are single-result
342 // instructions for this in x86. Using the two-result multiply instructions
343 // when both high and low results are needed must be arranged by dagcombine.
344 for (unsigned i = 0, e = 4; i != e; ++i) {
346 setOperationAction(ISD::MULHS, VT, Expand);
347 setOperationAction(ISD::MULHU, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
354 setOperationAction(ISD::ADDC, VT, Custom);
355 setOperationAction(ISD::ADDE, VT, Custom);
356 setOperationAction(ISD::SUBC, VT, Custom);
357 setOperationAction(ISD::SUBE, VT, Custom);
360 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
361 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
362 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f32 , Expand);
371 setOperationAction(ISD::FREM , MVT::f64 , Expand);
372 setOperationAction(ISD::FREM , MVT::f80 , Expand);
373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
375 // Promote the i8 variants and force them on up to i32 which has a shorter
377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 if (Subtarget->hasLZCNT()) {
394 // When promoting the i8 variants, force them to i32 for a shorter
396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
417 if (Subtarget->hasPOPCNT()) {
418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
430 // These should be promoted to a larger select which is supported.
431 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
432 // X86 wants to expand cmov itself.
433 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
435 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
438 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
441 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
444 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
460 if (Subtarget->is64Bit()) {
461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
471 if (Subtarget->is64Bit()) {
472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
477 if (Subtarget->hasSSE1())
478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
483 // On X86 and X86-64, atomic operations are lowered to locked instructions.
484 // Locked instructions, in turn, have implicit fence semantics (all memory
485 // operations are flushed before issuing the locked instruction, and they
486 // are not buffered), so we can fold away the common pattern of
487 // fence-atomic-fence.
488 setShouldFoldAtomicFences(true);
490 // Expand certain atomics
491 for (unsigned i = 0, e = 4; i != e; ++i) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
498 if (!Subtarget->is64Bit()) {
499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
509 if (Subtarget->hasCmpxchg16b()) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
513 // FIXME - use subtarget debug flags
514 if (!Subtarget->isTargetDarwin() &&
515 !Subtarget->isTargetELF() &&
516 !Subtarget->isTargetCygMing()) {
517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
524 if (Subtarget->is64Bit()) {
525 setExceptionPointerRegister(X86::RAX);
526 setExceptionSelectorRegister(X86::RDX);
528 setExceptionPointerRegister(X86::EAX);
529 setExceptionSelectorRegister(X86::EDX);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
537 setOperationAction(ISD::TRAP, MVT::Other, Legal);
539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
540 setOperationAction(ISD::VASTART , MVT::Other, Custom);
541 setOperationAction(ISD::VAEND , MVT::Other, Expand);
542 if (Subtarget->is64Bit()) {
543 setOperationAction(ISD::VAARG , MVT::Other, Custom);
544 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
546 setOperationAction(ISD::VAARG , MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
555 MVT::i64 : MVT::i32, Custom);
556 else if (TM.Options.EnableSegmentedStacks)
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Expand);
563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
564 // f32 and f64 use SSE.
565 // Set up the FP register classes.
566 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
567 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
569 // Use ANDPD to simulate FABS.
570 setOperationAction(ISD::FABS , MVT::f64, Custom);
571 setOperationAction(ISD::FABS , MVT::f32, Custom);
573 // Use XORP to simulate FNEG.
574 setOperationAction(ISD::FNEG , MVT::f64, Custom);
575 setOperationAction(ISD::FNEG , MVT::f32, Custom);
577 // Use ANDPD and ORPD to simulate FCOPYSIGN.
578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
581 // Lower this to FGETSIGNx86 plus an AND.
582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f64, Expand);
587 setOperationAction(ISD::FCOS , MVT::f64, Expand);
588 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FCOS , MVT::f32, Expand);
591 // Expand FP immediates into loads from the stack, except for the special
593 addLegalFPImmediate(APFloat(+0.0)); // xorpd
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
596 // Use SSE for f32, x87 for f64.
597 // Set up the FP register classes.
598 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
599 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
601 // Use ANDPS to simulate FABS.
602 setOperationAction(ISD::FABS , MVT::f32, Custom);
604 // Use XORP to simulate FNEG.
605 setOperationAction(ISD::FNEG , MVT::f32, Custom);
607 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
609 // Use ANDPS and ORPS to simulate FCOPYSIGN.
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
613 // We don't support sin/cos/fmod
614 setOperationAction(ISD::FSIN , MVT::f32, Expand);
615 setOperationAction(ISD::FCOS , MVT::f32, Expand);
617 // Special cases we handle for FP constants.
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
624 if (!TM.Options.UnsafeFPMath) {
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 } else if (!TM.Options.UseSoftFloat) {
629 // f32 and f64 in x87.
630 // Set up the FP register classes.
631 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
632 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
634 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
635 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
653 // We don't support FMA.
654 setOperationAction(ISD::FMA, MVT::f64, Expand);
655 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 // Long double always uses X87.
658 if (!TM.Options.UseSoftFloat) {
659 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
660 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
664 addLegalFPImmediate(TmpFlt); // FLD0
666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
669 APFloat TmpFlt2(+1.0);
670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
672 addLegalFPImmediate(TmpFlt2); // FLD1
673 TmpFlt2.changeSign();
674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
677 if (!TM.Options.UnsafeFPMath) {
678 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
679 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
683 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
685 setOperationAction(ISD::FRINT, MVT::f80, Expand);
686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
687 setOperationAction(ISD::FMA, MVT::f80, Expand);
690 // Always use a library call for pow.
691 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
693 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
695 setOperationAction(ISD::FLOG, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
697 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP, MVT::f80, Expand);
699 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
701 // First set operation action for all vector types to either promote
702 // (for widening) or expand (for scalarization). Then we will selectively
703 // turn on ones that can be effectively codegen'd.
704 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
705 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
763 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
764 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
765 setTruncStoreAction((MVT::SimpleValueType)VT,
766 (MVT::SimpleValueType)InnerVT, Expand);
767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
773 // with -msoft-float, disable use of MMX as well.
774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
775 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
776 // No operations on x86mmx supported, everything uses intrinsics.
779 // MMX-sized vectors (other than x86mmx) are expected to be expanded
780 // into smaller operations.
781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
785 setOperationAction(ISD::AND, MVT::v8i8, Expand);
786 setOperationAction(ISD::AND, MVT::v4i16, Expand);
787 setOperationAction(ISD::AND, MVT::v2i32, Expand);
788 setOperationAction(ISD::AND, MVT::v1i64, Expand);
789 setOperationAction(ISD::OR, MVT::v8i8, Expand);
790 setOperationAction(ISD::OR, MVT::v4i16, Expand);
791 setOperationAction(ISD::OR, MVT::v2i32, Expand);
792 setOperationAction(ISD::OR, MVT::v1i64, Expand);
793 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
794 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
795 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
796 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
812 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
814 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
829 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
832 // registers cannot be used even for integer operations.
833 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
834 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
835 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
836 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
838 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
839 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
840 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
841 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
843 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
844 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
845 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
846 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
848 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR,
882 VT.getSimpleVT().SimpleTy, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE,
884 VT.getSimpleVT().SimpleTy, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
886 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
902 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
906 // Do not attempt to promote non-128-bit vectors
907 if (!VT.is128BitVector())
910 setOperationAction(ISD::AND, SVT, Promote);
911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
912 setOperationAction(ISD::OR, SVT, Promote);
913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
914 setOperationAction(ISD::XOR, SVT, Promote);
915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
916 setOperationAction(ISD::LOAD, SVT, Promote);
917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
918 setOperationAction(ISD::SELECT, SVT, Promote);
919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
922 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
924 // Custom lower v2i64 and v2f64 selects.
925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
934 if (Subtarget->hasSSE41()) {
935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
938 setOperationAction(ISD::FRINT, MVT::f32, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
946 // FIXME: Do we need to handle scalar-to-vector here?
947 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
955 // i8 and i16 vectors are custom , because the source register and source
956 // source memory operand types are not the same width. f32 vectors are
957 // custom since the immediate controlling the insert encodes additional
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
969 // FIXME: these should be Legal but thats only for the case where
970 // the index is constant. For now custom expand to deal with that.
971 if (Subtarget->is64Bit()) {
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
977 if (Subtarget->hasSSE2()) {
978 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
981 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
987 if (Subtarget->hasAVX2()) {
988 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
989 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
991 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
997 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1006 if (Subtarget->hasSSE42())
1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1010 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1011 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1012 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1013 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1014 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1015 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1069 if (Subtarget->hasAVX2()) {
1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1083 // Don't lower v32i8 because there is no 128-bit byte mul
1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1108 // Don't lower v32i8 because there is no 128-bit byte mul
1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1119 // Custom lower several nodes for 256-bit types.
1120 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1125 // Extract subvector is special because the value type
1126 // (result) is 128-bit but the source is 256-bit wide.
1127 if (VT.is128BitVector())
1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1130 // Do not attempt to custom lower other non-256-bit vectors
1131 if (!VT.is256BitVector())
1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1143 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1147 // Do not attempt to promote non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::AND, SVT, Promote);
1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1153 setOperationAction(ISD::OR, SVT, Promote);
1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1155 setOperationAction(ISD::XOR, SVT, Promote);
1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1157 setOperationAction(ISD::LOAD, SVT, Promote);
1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1159 setOperationAction(ISD::SELECT, SVT, Promote);
1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1165 // of this type with custom code.
1166 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1167 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1172 // We want to custom lower some of our intrinsics.
1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1177 // handle type legalization for these operations here.
1179 // FIXME: We really should do custom legalization for addition and
1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1181 // than generic legalization for 64-bit multiplication-with-overflow, though.
1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1183 // Add/Sub/Mul with overflow operations are custom lowered.
1185 setOperationAction(ISD::SADDO, VT, Custom);
1186 setOperationAction(ISD::UADDO, VT, Custom);
1187 setOperationAction(ISD::SSUBO, VT, Custom);
1188 setOperationAction(ISD::USUBO, VT, Custom);
1189 setOperationAction(ISD::SMULO, VT, Custom);
1190 setOperationAction(ISD::UMULO, VT, Custom);
1193 // There are no 8-bit 3-address imul/mul instructions
1194 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1195 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1197 if (!Subtarget->is64Bit()) {
1198 // These libcalls are not available in 32-bit.
1199 setLibcallName(RTLIB::SHL_I128, 0);
1200 setLibcallName(RTLIB::SRL_I128, 0);
1201 setLibcallName(RTLIB::SRA_I128, 0);
1204 // We have target-specific dag combine patterns for the following nodes:
1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1207 setTargetDAGCombine(ISD::VSELECT);
1208 setTargetDAGCombine(ISD::SELECT);
1209 setTargetDAGCombine(ISD::SHL);
1210 setTargetDAGCombine(ISD::SRA);
1211 setTargetDAGCombine(ISD::SRL);
1212 setTargetDAGCombine(ISD::OR);
1213 setTargetDAGCombine(ISD::AND);
1214 setTargetDAGCombine(ISD::ADD);
1215 setTargetDAGCombine(ISD::FADD);
1216 setTargetDAGCombine(ISD::FSUB);
1217 setTargetDAGCombine(ISD::SUB);
1218 setTargetDAGCombine(ISD::LOAD);
1219 setTargetDAGCombine(ISD::STORE);
1220 setTargetDAGCombine(ISD::ZERO_EXTEND);
1221 setTargetDAGCombine(ISD::TRUNCATE);
1222 setTargetDAGCombine(ISD::SINT_TO_FP);
1223 if (Subtarget->is64Bit())
1224 setTargetDAGCombine(ISD::MUL);
1225 if (Subtarget->hasBMI())
1226 setTargetDAGCombine(ISD::XOR);
1228 computeRegisterProperties();
1230 // On Darwin, -Os means optimize for size without hurting performance,
1231 // do not reduce the limit.
1232 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1233 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1234 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1235 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1236 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1237 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1238 setPrefLoopAlignment(4); // 2^4 bytes.
1239 benefitFromCodePlacementOpt = true;
1241 setPrefFunctionAlignment(4); // 2^4 bytes.
1245 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1246 if (!VT.isVector()) return MVT::i8;
1247 return VT.changeVectorElementTypeToInteger();
1251 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1252 /// the desired ByVal argument alignment.
1253 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1256 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1257 if (VTy->getBitWidth() == 128)
1259 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1260 unsigned EltAlign = 0;
1261 getMaxByValAlign(ATy->getElementType(), EltAlign);
1262 if (EltAlign > MaxAlign)
1263 MaxAlign = EltAlign;
1264 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1265 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1266 unsigned EltAlign = 0;
1267 getMaxByValAlign(STy->getElementType(i), EltAlign);
1268 if (EltAlign > MaxAlign)
1269 MaxAlign = EltAlign;
1277 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1278 /// function arguments in the caller parameter area. For X86, aggregates
1279 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1280 /// are at 4-byte boundaries.
1281 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1282 if (Subtarget->is64Bit()) {
1283 // Max of 8 and alignment of type.
1284 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1291 if (Subtarget->hasSSE1())
1292 getMaxByValAlign(Ty, Align);
1296 /// getOptimalMemOpType - Returns the target specific optimal type for load
1297 /// and store operations as a result of memset, memcpy, and memmove
1298 /// lowering. If DstAlign is zero that means it's safe to destination
1299 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1300 /// means there isn't a need to check it against alignment requirement,
1301 /// probably because the source does not need to be loaded. If
1302 /// 'IsZeroVal' is true, that means it's safe to return a
1303 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1304 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1305 /// constant so it does not need to be loaded.
1306 /// It returns EVT::Other if the type should be determined using generic
1307 /// target-independent logic.
1309 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1310 unsigned DstAlign, unsigned SrcAlign,
1313 MachineFunction &MF) const {
1314 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1315 // linux. This is because the stack realignment code can't handle certain
1316 // cases like PR2962. This should be removed when PR2962 is fixed.
1317 const Function *F = MF.getFunction();
1319 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1321 (Subtarget->isUnalignedMemAccessFast() ||
1322 ((DstAlign == 0 || DstAlign >= 16) &&
1323 (SrcAlign == 0 || SrcAlign >= 16))) &&
1324 Subtarget->getStackAlignment() >= 16) {
1325 if (Subtarget->getStackAlignment() >= 32) {
1326 if (Subtarget->hasAVX2())
1328 if (Subtarget->hasAVX())
1331 if (Subtarget->hasSSE2())
1333 if (Subtarget->hasSSE1())
1335 } else if (!MemcpyStrSrc && Size >= 8 &&
1336 !Subtarget->is64Bit() &&
1337 Subtarget->getStackAlignment() >= 8 &&
1338 Subtarget->hasSSE2()) {
1339 // Do not use f64 to lower memcpy if source is string constant. It's
1340 // better to use i32 to avoid the loads.
1344 if (Subtarget->is64Bit() && Size >= 8)
1349 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1350 /// current function. The returned value is a member of the
1351 /// MachineJumpTableInfo::JTEntryKind enum.
1352 unsigned X86TargetLowering::getJumpTableEncoding() const {
1353 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1355 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1356 Subtarget->isPICStyleGOT())
1357 return MachineJumpTableInfo::EK_Custom32;
1359 // Otherwise, use the normal jump table encoding heuristics.
1360 return TargetLowering::getJumpTableEncoding();
1364 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1365 const MachineBasicBlock *MBB,
1366 unsigned uid,MCContext &Ctx) const{
1367 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1368 Subtarget->isPICStyleGOT());
1369 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1371 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1372 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1375 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1377 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1378 SelectionDAG &DAG) const {
1379 if (!Subtarget->is64Bit())
1380 // This doesn't have DebugLoc associated with it, but is not really the
1381 // same as a Register.
1382 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1386 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1387 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1389 const MCExpr *X86TargetLowering::
1390 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1391 MCContext &Ctx) const {
1392 // X86-64 uses RIP relative addressing based on the jump table label.
1393 if (Subtarget->isPICStyleRIPRel())
1394 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1396 // Otherwise, the reference is relative to the PIC base.
1397 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1400 // FIXME: Why this routine is here? Move to RegInfo!
1401 std::pair<const TargetRegisterClass*, uint8_t>
1402 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1403 const TargetRegisterClass *RRC = 0;
1405 switch (VT.getSimpleVT().SimpleTy) {
1407 return TargetLowering::findRepresentativeClass(VT);
1408 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1409 RRC = (Subtarget->is64Bit()
1410 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1413 RRC = X86::VR64RegisterClass;
1415 case MVT::f32: case MVT::f64:
1416 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1417 case MVT::v4f32: case MVT::v2f64:
1418 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1420 RRC = X86::VR128RegisterClass;
1423 return std::make_pair(RRC, Cost);
1426 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1427 unsigned &Offset) const {
1428 if (!Subtarget->isTargetLinux())
1431 if (Subtarget->is64Bit()) {
1432 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1434 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1447 //===----------------------------------------------------------------------===//
1448 // Return Value Calling Convention Implementation
1449 //===----------------------------------------------------------------------===//
1451 #include "X86GenCallingConv.inc"
1454 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1455 MachineFunction &MF, bool isVarArg,
1456 const SmallVectorImpl<ISD::OutputArg> &Outs,
1457 LLVMContext &Context) const {
1458 SmallVector<CCValAssign, 16> RVLocs;
1459 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1461 return CCInfo.CheckReturn(Outs, RetCC_X86);
1465 X86TargetLowering::LowerReturn(SDValue Chain,
1466 CallingConv::ID CallConv, bool isVarArg,
1467 const SmallVectorImpl<ISD::OutputArg> &Outs,
1468 const SmallVectorImpl<SDValue> &OutVals,
1469 DebugLoc dl, SelectionDAG &DAG) const {
1470 MachineFunction &MF = DAG.getMachineFunction();
1471 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1473 SmallVector<CCValAssign, 16> RVLocs;
1474 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1475 RVLocs, *DAG.getContext());
1476 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1478 // Add the regs to the liveout set for the function.
1479 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1480 for (unsigned i = 0; i != RVLocs.size(); ++i)
1481 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1482 MRI.addLiveOut(RVLocs[i].getLocReg());
1486 SmallVector<SDValue, 6> RetOps;
1487 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1488 // Operand #1 = Bytes To Pop
1489 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1492 // Copy the result values into the output registers.
1493 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1494 CCValAssign &VA = RVLocs[i];
1495 assert(VA.isRegLoc() && "Can only return in registers!");
1496 SDValue ValToCopy = OutVals[i];
1497 EVT ValVT = ValToCopy.getValueType();
1499 // If this is x86-64, and we disabled SSE, we can't return FP values,
1500 // or SSE or MMX vectors.
1501 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1502 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1503 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1504 report_fatal_error("SSE register return with SSE disabled");
1506 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1507 // llvm-gcc has never done it right and no one has noticed, so this
1508 // should be OK for now.
1509 if (ValVT == MVT::f64 &&
1510 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1511 report_fatal_error("SSE2 register return with SSE2 disabled");
1513 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1514 // the RET instruction and handled by the FP Stackifier.
1515 if (VA.getLocReg() == X86::ST0 ||
1516 VA.getLocReg() == X86::ST1) {
1517 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1518 // change the value to the FP stack register class.
1519 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1520 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1521 RetOps.push_back(ValToCopy);
1522 // Don't emit a copytoreg.
1526 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1527 // which is returned in RAX / RDX.
1528 if (Subtarget->is64Bit()) {
1529 if (ValVT == MVT::x86mmx) {
1530 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1531 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1532 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1534 // If we don't have SSE2 available, convert to v4f32 so the generated
1535 // register is legal.
1536 if (!Subtarget->hasSSE2())
1537 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1542 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1543 Flag = Chain.getValue(1);
1546 // The x86-64 ABI for returning structs by value requires that we copy
1547 // the sret argument into %rax for the return. We saved the argument into
1548 // a virtual register in the entry block, so now we copy the value out
1550 if (Subtarget->is64Bit() &&
1551 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1552 MachineFunction &MF = DAG.getMachineFunction();
1553 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1554 unsigned Reg = FuncInfo->getSRetReturnReg();
1556 "SRetReturnReg should have been set in LowerFormalArguments().");
1557 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1559 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1560 Flag = Chain.getValue(1);
1562 // RAX now acts like a return value.
1563 MRI.addLiveOut(X86::RAX);
1566 RetOps[0] = Chain; // Update chain.
1568 // Add the flag if we have it.
1570 RetOps.push_back(Flag);
1572 return DAG.getNode(X86ISD::RET_FLAG, dl,
1573 MVT::Other, &RetOps[0], RetOps.size());
1576 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1577 if (N->getNumValues() != 1)
1579 if (!N->hasNUsesOfValue(1, 0))
1582 SDNode *Copy = *N->use_begin();
1583 if (Copy->getOpcode() != ISD::CopyToReg &&
1584 Copy->getOpcode() != ISD::FP_EXTEND)
1587 bool HasRet = false;
1588 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1590 if (UI->getOpcode() != X86ISD::RET_FLAG)
1599 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1600 ISD::NodeType ExtendKind) const {
1602 // TODO: Is this also valid on 32-bit?
1603 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1604 ReturnMVT = MVT::i8;
1606 ReturnMVT = MVT::i32;
1608 EVT MinVT = getRegisterType(Context, ReturnMVT);
1609 return VT.bitsLT(MinVT) ? MinVT : VT;
1612 /// LowerCallResult - Lower the result values of a call into the
1613 /// appropriate copies out of appropriate physical registers.
1616 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1617 CallingConv::ID CallConv, bool isVarArg,
1618 const SmallVectorImpl<ISD::InputArg> &Ins,
1619 DebugLoc dl, SelectionDAG &DAG,
1620 SmallVectorImpl<SDValue> &InVals) const {
1622 // Assign locations to each value returned by this call.
1623 SmallVector<CCValAssign, 16> RVLocs;
1624 bool Is64Bit = Subtarget->is64Bit();
1625 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1626 getTargetMachine(), RVLocs, *DAG.getContext());
1627 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1629 // Copy all of the result registers out of their specified physreg.
1630 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1631 CCValAssign &VA = RVLocs[i];
1632 EVT CopyVT = VA.getValVT();
1634 // If this is x86-64, and we disabled SSE, we can't return FP values
1635 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1636 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1637 report_fatal_error("SSE register return with SSE disabled");
1642 // If this is a call to a function that returns an fp value on the floating
1643 // point stack, we must guarantee the the value is popped from the stack, so
1644 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1645 // if the return value is not used. We use the FpPOP_RETVAL instruction
1647 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1648 // If we prefer to use the value in xmm registers, copy it out as f80 and
1649 // use a truncate to move it from fp stack reg to xmm reg.
1650 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1651 SDValue Ops[] = { Chain, InFlag };
1652 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1653 MVT::Other, MVT::Glue, Ops, 2), 1);
1654 Val = Chain.getValue(0);
1656 // Round the f80 to the right size, which also moves it to the appropriate
1658 if (CopyVT != VA.getValVT())
1659 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1660 // This truncation won't change the value.
1661 DAG.getIntPtrConstant(1));
1663 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1664 CopyVT, InFlag).getValue(1);
1665 Val = Chain.getValue(0);
1667 InFlag = Chain.getValue(2);
1668 InVals.push_back(Val);
1675 //===----------------------------------------------------------------------===//
1676 // C & StdCall & Fast Calling Convention implementation
1677 //===----------------------------------------------------------------------===//
1678 // StdCall calling convention seems to be standard for many Windows' API
1679 // routines and around. It differs from C calling convention just a little:
1680 // callee should clean up the stack, not caller. Symbols should be also
1681 // decorated in some fancy way :) It doesn't support any vector arguments.
1682 // For info on fast calling convention see Fast Calling Convention (tail call)
1683 // implementation LowerX86_32FastCCCallTo.
1685 /// CallIsStructReturn - Determines whether a call uses struct return
1687 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1691 return Outs[0].Flags.isSRet();
1694 /// ArgsAreStructReturn - Determines whether a function uses struct
1695 /// return semantics.
1697 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1701 return Ins[0].Flags.isSRet();
1704 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1705 /// by "Src" to address "Dst" with size and alignment information specified by
1706 /// the specific parameter attribute. The copy will be passed as a byval
1707 /// function parameter.
1709 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1710 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1712 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1714 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1715 /*isVolatile*/false, /*AlwaysInline=*/true,
1716 MachinePointerInfo(), MachinePointerInfo());
1719 /// IsTailCallConvention - Return true if the calling convention is one that
1720 /// supports tail call optimization.
1721 static bool IsTailCallConvention(CallingConv::ID CC) {
1722 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1725 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1726 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1730 CallingConv::ID CalleeCC = CS.getCallingConv();
1731 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1737 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1738 /// a tailcall target by changing its ABI.
1739 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1740 bool GuaranteedTailCallOpt) {
1741 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1745 X86TargetLowering::LowerMemArgument(SDValue Chain,
1746 CallingConv::ID CallConv,
1747 const SmallVectorImpl<ISD::InputArg> &Ins,
1748 DebugLoc dl, SelectionDAG &DAG,
1749 const CCValAssign &VA,
1750 MachineFrameInfo *MFI,
1752 // Create the nodes corresponding to a load from this parameter slot.
1753 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1754 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1755 getTargetMachine().Options.GuaranteedTailCallOpt);
1756 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1759 // If value is passed by pointer we have address passed instead of the value
1761 if (VA.getLocInfo() == CCValAssign::Indirect)
1762 ValVT = VA.getLocVT();
1764 ValVT = VA.getValVT();
1766 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1767 // changed with more analysis.
1768 // In case of tail call optimization mark all arguments mutable. Since they
1769 // could be overwritten by lowering of arguments in case of a tail call.
1770 if (Flags.isByVal()) {
1771 unsigned Bytes = Flags.getByValSize();
1772 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1773 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1774 return DAG.getFrameIndex(FI, getPointerTy());
1776 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1777 VA.getLocMemOffset(), isImmutable);
1778 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1779 return DAG.getLoad(ValVT, dl, Chain, FIN,
1780 MachinePointerInfo::getFixedStack(FI),
1781 false, false, false, 0);
1786 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1787 CallingConv::ID CallConv,
1789 const SmallVectorImpl<ISD::InputArg> &Ins,
1792 SmallVectorImpl<SDValue> &InVals)
1794 MachineFunction &MF = DAG.getMachineFunction();
1795 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1797 const Function* Fn = MF.getFunction();
1798 if (Fn->hasExternalLinkage() &&
1799 Subtarget->isTargetCygMing() &&
1800 Fn->getName() == "main")
1801 FuncInfo->setForceFramePointer(true);
1803 MachineFrameInfo *MFI = MF.getFrameInfo();
1804 bool Is64Bit = Subtarget->is64Bit();
1805 bool IsWindows = Subtarget->isTargetWindows();
1806 bool IsWin64 = Subtarget->isTargetWin64();
1808 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1809 "Var args not supported with calling convention fastcc or ghc");
1811 // Assign locations to all of the incoming arguments.
1812 SmallVector<CCValAssign, 16> ArgLocs;
1813 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1814 ArgLocs, *DAG.getContext());
1816 // Allocate shadow area for Win64
1818 CCInfo.AllocateStack(32, 8);
1821 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1823 unsigned LastVal = ~0U;
1825 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1826 CCValAssign &VA = ArgLocs[i];
1827 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1829 assert(VA.getValNo() != LastVal &&
1830 "Don't support value assigned to multiple locs yet");
1832 LastVal = VA.getValNo();
1834 if (VA.isRegLoc()) {
1835 EVT RegVT = VA.getLocVT();
1836 TargetRegisterClass *RC = NULL;
1837 if (RegVT == MVT::i32)
1838 RC = X86::GR32RegisterClass;
1839 else if (Is64Bit && RegVT == MVT::i64)
1840 RC = X86::GR64RegisterClass;
1841 else if (RegVT == MVT::f32)
1842 RC = X86::FR32RegisterClass;
1843 else if (RegVT == MVT::f64)
1844 RC = X86::FR64RegisterClass;
1845 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1846 RC = X86::VR256RegisterClass;
1847 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1848 RC = X86::VR128RegisterClass;
1849 else if (RegVT == MVT::x86mmx)
1850 RC = X86::VR64RegisterClass;
1852 llvm_unreachable("Unknown argument type!");
1854 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1855 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1857 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1858 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1860 if (VA.getLocInfo() == CCValAssign::SExt)
1861 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1862 DAG.getValueType(VA.getValVT()));
1863 else if (VA.getLocInfo() == CCValAssign::ZExt)
1864 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1865 DAG.getValueType(VA.getValVT()));
1866 else if (VA.getLocInfo() == CCValAssign::BCvt)
1867 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1869 if (VA.isExtInLoc()) {
1870 // Handle MMX values passed in XMM regs.
1871 if (RegVT.isVector()) {
1872 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1875 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1878 assert(VA.isMemLoc());
1879 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1882 // If value is passed via pointer - do a load.
1883 if (VA.getLocInfo() == CCValAssign::Indirect)
1884 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1885 MachinePointerInfo(), false, false, false, 0);
1887 InVals.push_back(ArgValue);
1890 // The x86-64 ABI for returning structs by value requires that we copy
1891 // the sret argument into %rax for the return. Save the argument into
1892 // a virtual register so that we can access it from the return points.
1893 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1894 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1895 unsigned Reg = FuncInfo->getSRetReturnReg();
1897 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1898 FuncInfo->setSRetReturnReg(Reg);
1900 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1901 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1904 unsigned StackSize = CCInfo.getNextStackOffset();
1905 // Align stack specially for tail calls.
1906 if (FuncIsMadeTailCallSafe(CallConv,
1907 MF.getTarget().Options.GuaranteedTailCallOpt))
1908 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1910 // If the function takes variable number of arguments, make a frame index for
1911 // the start of the first vararg value... for expansion of llvm.va_start.
1913 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1914 CallConv != CallingConv::X86_ThisCall)) {
1915 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1918 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1920 // FIXME: We should really autogenerate these arrays
1921 static const unsigned GPR64ArgRegsWin64[] = {
1922 X86::RCX, X86::RDX, X86::R8, X86::R9
1924 static const unsigned GPR64ArgRegs64Bit[] = {
1925 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1927 static const unsigned XMMArgRegs64Bit[] = {
1928 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1929 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1931 const unsigned *GPR64ArgRegs;
1932 unsigned NumXMMRegs = 0;
1935 // The XMM registers which might contain var arg parameters are shadowed
1936 // in their paired GPR. So we only need to save the GPR to their home
1938 TotalNumIntRegs = 4;
1939 GPR64ArgRegs = GPR64ArgRegsWin64;
1941 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1942 GPR64ArgRegs = GPR64ArgRegs64Bit;
1944 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1947 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1950 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1951 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1952 "SSE register cannot be used when SSE is disabled!");
1953 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1954 NoImplicitFloatOps) &&
1955 "SSE register cannot be used when SSE is disabled!");
1956 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1957 !Subtarget->hasSSE1())
1958 // Kernel mode asks for SSE to be disabled, so don't push them
1960 TotalNumXMMRegs = 0;
1963 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1964 // Get to the caller-allocated home save location. Add 8 to account
1965 // for the return address.
1966 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1967 FuncInfo->setRegSaveFrameIndex(
1968 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1969 // Fixup to set vararg frame on shadow area (4 x i64).
1971 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1973 // For X86-64, if there are vararg parameters that are passed via
1974 // registers, then we must store them to their spots on the stack so
1975 // they may be loaded by deferencing the result of va_next.
1976 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1977 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1978 FuncInfo->setRegSaveFrameIndex(
1979 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1983 // Store the integer parameter registers.
1984 SmallVector<SDValue, 8> MemOps;
1985 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1987 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1988 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1989 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1990 DAG.getIntPtrConstant(Offset));
1991 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1992 X86::GR64RegisterClass);
1993 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1995 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1996 MachinePointerInfo::getFixedStack(
1997 FuncInfo->getRegSaveFrameIndex(), Offset),
1999 MemOps.push_back(Store);
2003 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2004 // Now store the XMM (fp + vector) parameter registers.
2005 SmallVector<SDValue, 11> SaveXMMOps;
2006 SaveXMMOps.push_back(Chain);
2008 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2009 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2010 SaveXMMOps.push_back(ALVal);
2012 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2013 FuncInfo->getRegSaveFrameIndex()));
2014 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2015 FuncInfo->getVarArgsFPOffset()));
2017 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2018 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2019 X86::VR128RegisterClass);
2020 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2021 SaveXMMOps.push_back(Val);
2023 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2025 &SaveXMMOps[0], SaveXMMOps.size()));
2028 if (!MemOps.empty())
2029 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2030 &MemOps[0], MemOps.size());
2034 // Some CCs need callee pop.
2035 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2036 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2037 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2039 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2040 // If this is an sret function, the return should pop the hidden pointer.
2041 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2042 ArgsAreStructReturn(Ins))
2043 FuncInfo->setBytesToPopOnReturn(4);
2047 // RegSaveFrameIndex is X86-64 only.
2048 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2049 if (CallConv == CallingConv::X86_FastCall ||
2050 CallConv == CallingConv::X86_ThisCall)
2051 // fastcc functions can't have varargs.
2052 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2055 FuncInfo->setArgumentStackSize(StackSize);
2061 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2062 SDValue StackPtr, SDValue Arg,
2063 DebugLoc dl, SelectionDAG &DAG,
2064 const CCValAssign &VA,
2065 ISD::ArgFlagsTy Flags) const {
2066 unsigned LocMemOffset = VA.getLocMemOffset();
2067 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2068 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2069 if (Flags.isByVal())
2070 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2072 return DAG.getStore(Chain, dl, Arg, PtrOff,
2073 MachinePointerInfo::getStack(LocMemOffset),
2077 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2078 /// optimization is performed and it is required.
2080 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2081 SDValue &OutRetAddr, SDValue Chain,
2082 bool IsTailCall, bool Is64Bit,
2083 int FPDiff, DebugLoc dl) const {
2084 // Adjust the Return address stack slot.
2085 EVT VT = getPointerTy();
2086 OutRetAddr = getReturnAddressFrameIndex(DAG);
2088 // Load the "old" Return address.
2089 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2090 false, false, false, 0);
2091 return SDValue(OutRetAddr.getNode(), 1);
2094 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2095 /// optimization is performed and it is required (FPDiff!=0).
2097 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2098 SDValue Chain, SDValue RetAddrFrIdx,
2099 bool Is64Bit, int FPDiff, DebugLoc dl) {
2100 // Store the return address to the appropriate stack slot.
2101 if (!FPDiff) return Chain;
2102 // Calculate the new stack slot for the return address.
2103 int SlotSize = Is64Bit ? 8 : 4;
2104 int NewReturnAddrFI =
2105 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2106 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2107 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2108 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2109 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2115 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2116 CallingConv::ID CallConv, bool isVarArg,
2118 const SmallVectorImpl<ISD::OutputArg> &Outs,
2119 const SmallVectorImpl<SDValue> &OutVals,
2120 const SmallVectorImpl<ISD::InputArg> &Ins,
2121 DebugLoc dl, SelectionDAG &DAG,
2122 SmallVectorImpl<SDValue> &InVals) const {
2123 MachineFunction &MF = DAG.getMachineFunction();
2124 bool Is64Bit = Subtarget->is64Bit();
2125 bool IsWin64 = Subtarget->isTargetWin64();
2126 bool IsWindows = Subtarget->isTargetWindows();
2127 bool IsStructRet = CallIsStructReturn(Outs);
2128 bool IsSibcall = false;
2130 if (MF.getTarget().Options.DisableTailCalls)
2134 // Check if it's really possible to do a tail call.
2135 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2136 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2137 Outs, OutVals, Ins, DAG);
2139 // Sibcalls are automatically detected tailcalls which do not require
2141 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2148 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2149 "Var args not supported with calling convention fastcc or ghc");
2151 // Analyze operands of the call, assigning locations to each operand.
2152 SmallVector<CCValAssign, 16> ArgLocs;
2153 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2154 ArgLocs, *DAG.getContext());
2156 // Allocate shadow area for Win64
2158 CCInfo.AllocateStack(32, 8);
2161 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2163 // Get a count of how many bytes are to be pushed on the stack.
2164 unsigned NumBytes = CCInfo.getNextStackOffset();
2166 // This is a sibcall. The memory operands are available in caller's
2167 // own caller's stack.
2169 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2170 IsTailCallConvention(CallConv))
2171 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2174 if (isTailCall && !IsSibcall) {
2175 // Lower arguments at fp - stackoffset + fpdiff.
2176 unsigned NumBytesCallerPushed =
2177 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2178 FPDiff = NumBytesCallerPushed - NumBytes;
2180 // Set the delta of movement of the returnaddr stackslot.
2181 // But only set if delta is greater than previous delta.
2182 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2183 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2187 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2189 SDValue RetAddrFrIdx;
2190 // Load return address for tail calls.
2191 if (isTailCall && FPDiff)
2192 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2193 Is64Bit, FPDiff, dl);
2195 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2196 SmallVector<SDValue, 8> MemOpChains;
2199 // Walk the register/memloc assignments, inserting copies/loads. In the case
2200 // of tail call optimization arguments are handle later.
2201 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2202 CCValAssign &VA = ArgLocs[i];
2203 EVT RegVT = VA.getLocVT();
2204 SDValue Arg = OutVals[i];
2205 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2206 bool isByVal = Flags.isByVal();
2208 // Promote the value if needed.
2209 switch (VA.getLocInfo()) {
2210 default: llvm_unreachable("Unknown loc info!");
2211 case CCValAssign::Full: break;
2212 case CCValAssign::SExt:
2213 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2215 case CCValAssign::ZExt:
2216 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2218 case CCValAssign::AExt:
2219 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2220 // Special case: passing MMX values in XMM registers.
2221 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2222 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2223 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2225 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2227 case CCValAssign::BCvt:
2228 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2230 case CCValAssign::Indirect: {
2231 // Store the argument.
2232 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2233 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2234 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2235 MachinePointerInfo::getFixedStack(FI),
2242 if (VA.isRegLoc()) {
2243 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2244 if (isVarArg && IsWin64) {
2245 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2246 // shadow reg if callee is a varargs function.
2247 unsigned ShadowReg = 0;
2248 switch (VA.getLocReg()) {
2249 case X86::XMM0: ShadowReg = X86::RCX; break;
2250 case X86::XMM1: ShadowReg = X86::RDX; break;
2251 case X86::XMM2: ShadowReg = X86::R8; break;
2252 case X86::XMM3: ShadowReg = X86::R9; break;
2255 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2257 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2258 assert(VA.isMemLoc());
2259 if (StackPtr.getNode() == 0)
2260 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2261 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2262 dl, DAG, VA, Flags));
2266 if (!MemOpChains.empty())
2267 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2268 &MemOpChains[0], MemOpChains.size());
2270 // Build a sequence of copy-to-reg nodes chained together with token chain
2271 // and flag operands which copy the outgoing args into registers.
2273 // Tail call byval lowering might overwrite argument registers so in case of
2274 // tail call optimization the copies to registers are lowered later.
2276 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2277 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2278 RegsToPass[i].second, InFlag);
2279 InFlag = Chain.getValue(1);
2282 if (Subtarget->isPICStyleGOT()) {
2283 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2286 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2287 DAG.getNode(X86ISD::GlobalBaseReg,
2288 DebugLoc(), getPointerTy()),
2290 InFlag = Chain.getValue(1);
2292 // If we are tail calling and generating PIC/GOT style code load the
2293 // address of the callee into ECX. The value in ecx is used as target of
2294 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2295 // for tail calls on PIC/GOT architectures. Normally we would just put the
2296 // address of GOT into ebx and then call target@PLT. But for tail calls
2297 // ebx would be restored (since ebx is callee saved) before jumping to the
2300 // Note: The actual moving to ECX is done further down.
2301 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2302 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2303 !G->getGlobal()->hasProtectedVisibility())
2304 Callee = LowerGlobalAddress(Callee, DAG);
2305 else if (isa<ExternalSymbolSDNode>(Callee))
2306 Callee = LowerExternalSymbol(Callee, DAG);
2310 if (Is64Bit && isVarArg && !IsWin64) {
2311 // From AMD64 ABI document:
2312 // For calls that may call functions that use varargs or stdargs
2313 // (prototype-less calls or calls to functions containing ellipsis (...) in
2314 // the declaration) %al is used as hidden argument to specify the number
2315 // of SSE registers used. The contents of %al do not need to match exactly
2316 // the number of registers, but must be an ubound on the number of SSE
2317 // registers used and is in the range 0 - 8 inclusive.
2319 // Count the number of XMM registers allocated.
2320 static const unsigned XMMArgRegs[] = {
2321 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2322 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2324 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2325 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2326 && "SSE registers cannot be used when SSE is disabled");
2328 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2329 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2330 InFlag = Chain.getValue(1);
2334 // For tail calls lower the arguments to the 'real' stack slot.
2336 // Force all the incoming stack arguments to be loaded from the stack
2337 // before any new outgoing arguments are stored to the stack, because the
2338 // outgoing stack slots may alias the incoming argument stack slots, and
2339 // the alias isn't otherwise explicit. This is slightly more conservative
2340 // than necessary, because it means that each store effectively depends
2341 // on every argument instead of just those arguments it would clobber.
2342 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2344 SmallVector<SDValue, 8> MemOpChains2;
2347 // Do not flag preceding copytoreg stuff together with the following stuff.
2349 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2350 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2351 CCValAssign &VA = ArgLocs[i];
2354 assert(VA.isMemLoc());
2355 SDValue Arg = OutVals[i];
2356 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2357 // Create frame index.
2358 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2359 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2360 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2361 FIN = DAG.getFrameIndex(FI, getPointerTy());
2363 if (Flags.isByVal()) {
2364 // Copy relative to framepointer.
2365 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2366 if (StackPtr.getNode() == 0)
2367 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2369 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2371 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2375 // Store relative to framepointer.
2376 MemOpChains2.push_back(
2377 DAG.getStore(ArgChain, dl, Arg, FIN,
2378 MachinePointerInfo::getFixedStack(FI),
2384 if (!MemOpChains2.empty())
2385 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2386 &MemOpChains2[0], MemOpChains2.size());
2388 // Copy arguments to their registers.
2389 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2390 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2391 RegsToPass[i].second, InFlag);
2392 InFlag = Chain.getValue(1);
2396 // Store the return address to the appropriate stack slot.
2397 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2401 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2402 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2403 // In the 64-bit large code model, we have to make all calls
2404 // through a register, since the call instruction's 32-bit
2405 // pc-relative offset may not be large enough to hold the whole
2407 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2408 // If the callee is a GlobalAddress node (quite common, every direct call
2409 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2412 // We should use extra load for direct calls to dllimported functions in
2414 const GlobalValue *GV = G->getGlobal();
2415 if (!GV->hasDLLImportLinkage()) {
2416 unsigned char OpFlags = 0;
2417 bool ExtraLoad = false;
2418 unsigned WrapperKind = ISD::DELETED_NODE;
2420 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2421 // external symbols most go through the PLT in PIC mode. If the symbol
2422 // has hidden or protected visibility, or if it is static or local, then
2423 // we don't need to use the PLT - we can directly call it.
2424 if (Subtarget->isTargetELF() &&
2425 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2426 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2427 OpFlags = X86II::MO_PLT;
2428 } else if (Subtarget->isPICStyleStubAny() &&
2429 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2430 (!Subtarget->getTargetTriple().isMacOSX() ||
2431 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2432 // PC-relative references to external symbols should go through $stub,
2433 // unless we're building with the leopard linker or later, which
2434 // automatically synthesizes these stubs.
2435 OpFlags = X86II::MO_DARWIN_STUB;
2436 } else if (Subtarget->isPICStyleRIPRel() &&
2437 isa<Function>(GV) &&
2438 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2439 // If the function is marked as non-lazy, generate an indirect call
2440 // which loads from the GOT directly. This avoids runtime overhead
2441 // at the cost of eager binding (and one extra byte of encoding).
2442 OpFlags = X86II::MO_GOTPCREL;
2443 WrapperKind = X86ISD::WrapperRIP;
2447 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2448 G->getOffset(), OpFlags);
2450 // Add a wrapper if needed.
2451 if (WrapperKind != ISD::DELETED_NODE)
2452 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2453 // Add extra indirection if needed.
2455 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2456 MachinePointerInfo::getGOT(),
2457 false, false, false, 0);
2459 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2460 unsigned char OpFlags = 0;
2462 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2463 // external symbols should go through the PLT.
2464 if (Subtarget->isTargetELF() &&
2465 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2466 OpFlags = X86II::MO_PLT;
2467 } else if (Subtarget->isPICStyleStubAny() &&
2468 (!Subtarget->getTargetTriple().isMacOSX() ||
2469 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2470 // PC-relative references to external symbols should go through $stub,
2471 // unless we're building with the leopard linker or later, which
2472 // automatically synthesizes these stubs.
2473 OpFlags = X86II::MO_DARWIN_STUB;
2476 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2480 // Returns a chain & a flag for retval copy to use.
2481 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2482 SmallVector<SDValue, 8> Ops;
2484 if (!IsSibcall && isTailCall) {
2485 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2486 DAG.getIntPtrConstant(0, true), InFlag);
2487 InFlag = Chain.getValue(1);
2490 Ops.push_back(Chain);
2491 Ops.push_back(Callee);
2494 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2496 // Add argument registers to the end of the list so that they are known live
2498 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2499 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2500 RegsToPass[i].second.getValueType()));
2502 // Add an implicit use GOT pointer in EBX.
2503 if (!isTailCall && Subtarget->isPICStyleGOT())
2504 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2506 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2507 if (Is64Bit && isVarArg && !IsWin64)
2508 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2510 // Experimental: Add a register mask operand representing the call-preserved
2513 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2514 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2515 Ops.push_back(DAG.getRegisterMask(Mask));
2518 if (InFlag.getNode())
2519 Ops.push_back(InFlag);
2523 //// If this is the first return lowered for this function, add the regs
2524 //// to the liveout set for the function.
2525 // This isn't right, although it's probably harmless on x86; liveouts
2526 // should be computed from returns not tail calls. Consider a void
2527 // function making a tail call to a function returning int.
2528 return DAG.getNode(X86ISD::TC_RETURN, dl,
2529 NodeTys, &Ops[0], Ops.size());
2532 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2533 InFlag = Chain.getValue(1);
2535 // Create the CALLSEQ_END node.
2536 unsigned NumBytesForCalleeToPush;
2537 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2538 getTargetMachine().Options.GuaranteedTailCallOpt))
2539 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2540 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2542 // If this is a call to a struct-return function, the callee
2543 // pops the hidden struct pointer, so we have to push it back.
2544 // This is common for Darwin/X86, Linux & Mingw32 targets.
2545 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2546 NumBytesForCalleeToPush = 4;
2548 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2550 // Returns a flag for retval copy to use.
2552 Chain = DAG.getCALLSEQ_END(Chain,
2553 DAG.getIntPtrConstant(NumBytes, true),
2554 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2557 InFlag = Chain.getValue(1);
2560 // Handle result values, copying them out of physregs into vregs that we
2562 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2563 Ins, dl, DAG, InVals);
2567 //===----------------------------------------------------------------------===//
2568 // Fast Calling Convention (tail call) implementation
2569 //===----------------------------------------------------------------------===//
2571 // Like std call, callee cleans arguments, convention except that ECX is
2572 // reserved for storing the tail called function address. Only 2 registers are
2573 // free for argument passing (inreg). Tail call optimization is performed
2575 // * tailcallopt is enabled
2576 // * caller/callee are fastcc
2577 // On X86_64 architecture with GOT-style position independent code only local
2578 // (within module) calls are supported at the moment.
2579 // To keep the stack aligned according to platform abi the function
2580 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2581 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2582 // If a tail called function callee has more arguments than the caller the
2583 // caller needs to make sure that there is room to move the RETADDR to. This is
2584 // achieved by reserving an area the size of the argument delta right after the
2585 // original REtADDR, but before the saved framepointer or the spilled registers
2586 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2598 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2599 /// for a 16 byte align requirement.
2601 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2602 SelectionDAG& DAG) const {
2603 MachineFunction &MF = DAG.getMachineFunction();
2604 const TargetMachine &TM = MF.getTarget();
2605 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2606 unsigned StackAlignment = TFI.getStackAlignment();
2607 uint64_t AlignMask = StackAlignment - 1;
2608 int64_t Offset = StackSize;
2609 uint64_t SlotSize = TD->getPointerSize();
2610 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2611 // Number smaller than 12 so just add the difference.
2612 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2614 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2615 Offset = ((~AlignMask) & Offset) + StackAlignment +
2616 (StackAlignment-SlotSize);
2621 /// MatchingStackOffset - Return true if the given stack call argument is
2622 /// already available in the same position (relatively) of the caller's
2623 /// incoming argument stack.
2625 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2626 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2627 const X86InstrInfo *TII) {
2628 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2630 if (Arg.getOpcode() == ISD::CopyFromReg) {
2631 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2632 if (!TargetRegisterInfo::isVirtualRegister(VR))
2634 MachineInstr *Def = MRI->getVRegDef(VR);
2637 if (!Flags.isByVal()) {
2638 if (!TII->isLoadFromStackSlot(Def, FI))
2641 unsigned Opcode = Def->getOpcode();
2642 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2643 Def->getOperand(1).isFI()) {
2644 FI = Def->getOperand(1).getIndex();
2645 Bytes = Flags.getByValSize();
2649 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2650 if (Flags.isByVal())
2651 // ByVal argument is passed in as a pointer but it's now being
2652 // dereferenced. e.g.
2653 // define @foo(%struct.X* %A) {
2654 // tail call @bar(%struct.X* byval %A)
2657 SDValue Ptr = Ld->getBasePtr();
2658 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2661 FI = FINode->getIndex();
2662 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2663 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2664 FI = FINode->getIndex();
2665 Bytes = Flags.getByValSize();
2669 assert(FI != INT_MAX);
2670 if (!MFI->isFixedObjectIndex(FI))
2672 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2675 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2676 /// for tail call optimization. Targets which want to do tail call
2677 /// optimization should implement this function.
2679 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2680 CallingConv::ID CalleeCC,
2682 bool isCalleeStructRet,
2683 bool isCallerStructRet,
2684 const SmallVectorImpl<ISD::OutputArg> &Outs,
2685 const SmallVectorImpl<SDValue> &OutVals,
2686 const SmallVectorImpl<ISD::InputArg> &Ins,
2687 SelectionDAG& DAG) const {
2688 if (!IsTailCallConvention(CalleeCC) &&
2689 CalleeCC != CallingConv::C)
2692 // If -tailcallopt is specified, make fastcc functions tail-callable.
2693 const MachineFunction &MF = DAG.getMachineFunction();
2694 const Function *CallerF = DAG.getMachineFunction().getFunction();
2695 CallingConv::ID CallerCC = CallerF->getCallingConv();
2696 bool CCMatch = CallerCC == CalleeCC;
2698 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2699 if (IsTailCallConvention(CalleeCC) && CCMatch)
2704 // Look for obvious safe cases to perform tail call optimization that do not
2705 // require ABI changes. This is what gcc calls sibcall.
2707 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2708 // emit a special epilogue.
2709 if (RegInfo->needsStackRealignment(MF))
2712 // Also avoid sibcall optimization if either caller or callee uses struct
2713 // return semantics.
2714 if (isCalleeStructRet || isCallerStructRet)
2717 // An stdcall caller is expected to clean up its arguments; the callee
2718 // isn't going to do that.
2719 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2722 // Do not sibcall optimize vararg calls unless all arguments are passed via
2724 if (isVarArg && !Outs.empty()) {
2726 // Optimizing for varargs on Win64 is unlikely to be safe without
2727 // additional testing.
2728 if (Subtarget->isTargetWin64())
2731 SmallVector<CCValAssign, 16> ArgLocs;
2732 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2733 getTargetMachine(), ArgLocs, *DAG.getContext());
2735 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2736 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2737 if (!ArgLocs[i].isRegLoc())
2741 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2742 // stack. Therefore, if it's not used by the call it is not safe to optimize
2743 // this into a sibcall.
2744 bool Unused = false;
2745 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2752 SmallVector<CCValAssign, 16> RVLocs;
2753 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2754 getTargetMachine(), RVLocs, *DAG.getContext());
2755 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2756 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2757 CCValAssign &VA = RVLocs[i];
2758 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2763 // If the calling conventions do not match, then we'd better make sure the
2764 // results are returned in the same way as what the caller expects.
2766 SmallVector<CCValAssign, 16> RVLocs1;
2767 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2768 getTargetMachine(), RVLocs1, *DAG.getContext());
2769 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2771 SmallVector<CCValAssign, 16> RVLocs2;
2772 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2773 getTargetMachine(), RVLocs2, *DAG.getContext());
2774 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2776 if (RVLocs1.size() != RVLocs2.size())
2778 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2779 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2781 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2783 if (RVLocs1[i].isRegLoc()) {
2784 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2787 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2793 // If the callee takes no arguments then go on to check the results of the
2795 if (!Outs.empty()) {
2796 // Check if stack adjustment is needed. For now, do not do this if any
2797 // argument is passed on the stack.
2798 SmallVector<CCValAssign, 16> ArgLocs;
2799 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2800 getTargetMachine(), ArgLocs, *DAG.getContext());
2802 // Allocate shadow area for Win64
2803 if (Subtarget->isTargetWin64()) {
2804 CCInfo.AllocateStack(32, 8);
2807 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2808 if (CCInfo.getNextStackOffset()) {
2809 MachineFunction &MF = DAG.getMachineFunction();
2810 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2813 // Check if the arguments are already laid out in the right way as
2814 // the caller's fixed stack objects.
2815 MachineFrameInfo *MFI = MF.getFrameInfo();
2816 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2817 const X86InstrInfo *TII =
2818 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2819 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2820 CCValAssign &VA = ArgLocs[i];
2821 SDValue Arg = OutVals[i];
2822 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2823 if (VA.getLocInfo() == CCValAssign::Indirect)
2825 if (!VA.isRegLoc()) {
2826 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2833 // If the tailcall address may be in a register, then make sure it's
2834 // possible to register allocate for it. In 32-bit, the call address can
2835 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2836 // callee-saved registers are restored. These happen to be the same
2837 // registers used to pass 'inreg' arguments so watch out for those.
2838 if (!Subtarget->is64Bit() &&
2839 !isa<GlobalAddressSDNode>(Callee) &&
2840 !isa<ExternalSymbolSDNode>(Callee)) {
2841 unsigned NumInRegs = 0;
2842 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2843 CCValAssign &VA = ArgLocs[i];
2846 unsigned Reg = VA.getLocReg();
2849 case X86::EAX: case X86::EDX: case X86::ECX:
2850 if (++NumInRegs == 3)
2862 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2863 return X86::createFastISel(funcInfo);
2867 //===----------------------------------------------------------------------===//
2868 // Other Lowering Hooks
2869 //===----------------------------------------------------------------------===//
2871 static bool MayFoldLoad(SDValue Op) {
2872 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2875 static bool MayFoldIntoStore(SDValue Op) {
2876 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2879 static bool isTargetShuffle(unsigned Opcode) {
2881 default: return false;
2882 case X86ISD::PSHUFD:
2883 case X86ISD::PSHUFHW:
2884 case X86ISD::PSHUFLW:
2886 case X86ISD::PALIGN:
2887 case X86ISD::MOVLHPS:
2888 case X86ISD::MOVLHPD:
2889 case X86ISD::MOVHLPS:
2890 case X86ISD::MOVLPS:
2891 case X86ISD::MOVLPD:
2892 case X86ISD::MOVSHDUP:
2893 case X86ISD::MOVSLDUP:
2894 case X86ISD::MOVDDUP:
2897 case X86ISD::UNPCKL:
2898 case X86ISD::UNPCKH:
2899 case X86ISD::VPERMILP:
2900 case X86ISD::VPERM2X128:
2905 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2906 SDValue V1, SelectionDAG &DAG) {
2908 default: llvm_unreachable("Unknown x86 shuffle node");
2909 case X86ISD::MOVSHDUP:
2910 case X86ISD::MOVSLDUP:
2911 case X86ISD::MOVDDUP:
2912 return DAG.getNode(Opc, dl, VT, V1);
2916 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2917 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2919 default: llvm_unreachable("Unknown x86 shuffle node");
2920 case X86ISD::PSHUFD:
2921 case X86ISD::PSHUFHW:
2922 case X86ISD::PSHUFLW:
2923 case X86ISD::VPERMILP:
2924 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2928 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2929 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2931 default: llvm_unreachable("Unknown x86 shuffle node");
2932 case X86ISD::PALIGN:
2934 case X86ISD::VPERM2X128:
2935 return DAG.getNode(Opc, dl, VT, V1, V2,
2936 DAG.getConstant(TargetMask, MVT::i8));
2940 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2941 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2943 default: llvm_unreachable("Unknown x86 shuffle node");
2944 case X86ISD::MOVLHPS:
2945 case X86ISD::MOVLHPD:
2946 case X86ISD::MOVHLPS:
2947 case X86ISD::MOVLPS:
2948 case X86ISD::MOVLPD:
2951 case X86ISD::UNPCKL:
2952 case X86ISD::UNPCKH:
2953 return DAG.getNode(Opc, dl, VT, V1, V2);
2957 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2958 MachineFunction &MF = DAG.getMachineFunction();
2959 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2960 int ReturnAddrIndex = FuncInfo->getRAIndex();
2962 if (ReturnAddrIndex == 0) {
2963 // Set up a frame object for the return address.
2964 uint64_t SlotSize = TD->getPointerSize();
2965 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2967 FuncInfo->setRAIndex(ReturnAddrIndex);
2970 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2974 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2975 bool hasSymbolicDisplacement) {
2976 // Offset should fit into 32 bit immediate field.
2977 if (!isInt<32>(Offset))
2980 // If we don't have a symbolic displacement - we don't have any extra
2982 if (!hasSymbolicDisplacement)
2985 // FIXME: Some tweaks might be needed for medium code model.
2986 if (M != CodeModel::Small && M != CodeModel::Kernel)
2989 // For small code model we assume that latest object is 16MB before end of 31
2990 // bits boundary. We may also accept pretty large negative constants knowing
2991 // that all objects are in the positive half of address space.
2992 if (M == CodeModel::Small && Offset < 16*1024*1024)
2995 // For kernel code model we know that all object resist in the negative half
2996 // of 32bits address space. We may not accept negative offsets, since they may
2997 // be just off and we may accept pretty large positive ones.
2998 if (M == CodeModel::Kernel && Offset > 0)
3004 /// isCalleePop - Determines whether the callee is required to pop its
3005 /// own arguments. Callee pop is necessary to support tail calls.
3006 bool X86::isCalleePop(CallingConv::ID CallingConv,
3007 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3011 switch (CallingConv) {
3014 case CallingConv::X86_StdCall:
3016 case CallingConv::X86_FastCall:
3018 case CallingConv::X86_ThisCall:
3020 case CallingConv::Fast:
3022 case CallingConv::GHC:
3027 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3028 /// specific condition code, returning the condition code and the LHS/RHS of the
3029 /// comparison to make.
3030 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3031 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3033 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3034 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3035 // X > -1 -> X == 0, jump !sign.
3036 RHS = DAG.getConstant(0, RHS.getValueType());
3037 return X86::COND_NS;
3038 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3039 // X < 0 -> X == 0, jump on sign.
3041 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3043 RHS = DAG.getConstant(0, RHS.getValueType());
3044 return X86::COND_LE;
3048 switch (SetCCOpcode) {
3049 default: llvm_unreachable("Invalid integer condition!");
3050 case ISD::SETEQ: return X86::COND_E;
3051 case ISD::SETGT: return X86::COND_G;
3052 case ISD::SETGE: return X86::COND_GE;
3053 case ISD::SETLT: return X86::COND_L;
3054 case ISD::SETLE: return X86::COND_LE;
3055 case ISD::SETNE: return X86::COND_NE;
3056 case ISD::SETULT: return X86::COND_B;
3057 case ISD::SETUGT: return X86::COND_A;
3058 case ISD::SETULE: return X86::COND_BE;
3059 case ISD::SETUGE: return X86::COND_AE;
3063 // First determine if it is required or is profitable to flip the operands.
3065 // If LHS is a foldable load, but RHS is not, flip the condition.
3066 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3067 !ISD::isNON_EXTLoad(RHS.getNode())) {
3068 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3069 std::swap(LHS, RHS);
3072 switch (SetCCOpcode) {
3078 std::swap(LHS, RHS);
3082 // On a floating point condition, the flags are set as follows:
3084 // 0 | 0 | 0 | X > Y
3085 // 0 | 0 | 1 | X < Y
3086 // 1 | 0 | 0 | X == Y
3087 // 1 | 1 | 1 | unordered
3088 switch (SetCCOpcode) {
3089 default: llvm_unreachable("Condcode should be pre-legalized away");
3091 case ISD::SETEQ: return X86::COND_E;
3092 case ISD::SETOLT: // flipped
3094 case ISD::SETGT: return X86::COND_A;
3095 case ISD::SETOLE: // flipped
3097 case ISD::SETGE: return X86::COND_AE;
3098 case ISD::SETUGT: // flipped
3100 case ISD::SETLT: return X86::COND_B;
3101 case ISD::SETUGE: // flipped
3103 case ISD::SETLE: return X86::COND_BE;
3105 case ISD::SETNE: return X86::COND_NE;
3106 case ISD::SETUO: return X86::COND_P;
3107 case ISD::SETO: return X86::COND_NP;
3109 case ISD::SETUNE: return X86::COND_INVALID;
3113 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3114 /// code. Current x86 isa includes the following FP cmov instructions:
3115 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3116 static bool hasFPCMov(unsigned X86CC) {
3132 /// isFPImmLegal - Returns true if the target can instruction select the
3133 /// specified FP immediate natively. If false, the legalizer will
3134 /// materialize the FP immediate as a load from a constant pool.
3135 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3136 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3137 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3143 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3144 /// the specified range (L, H].
3145 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3146 return (Val < 0) || (Val >= Low && Val < Hi);
3149 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3150 /// specified value.
3151 static bool isUndefOrEqual(int Val, int CmpVal) {
3152 if (Val < 0 || Val == CmpVal)
3157 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3158 /// from position Pos and ending in Pos+Size, falls within the specified
3159 /// sequential range (L, L+Pos]. or is undef.
3160 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3161 int Pos, int Size, int Low) {
3162 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3163 if (!isUndefOrEqual(Mask[i], Low))
3168 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3169 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3170 /// the second operand.
3171 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3172 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3173 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3174 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3175 return (Mask[0] < 2 && Mask[1] < 2);
3179 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3180 return ::isPSHUFDMask(N->getMask(), N->getValueType(0));
3183 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3184 /// is suitable for input to PSHUFHW.
3185 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3186 if (VT != MVT::v8i16)
3189 // Lower quadword copied in order or undef.
3190 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3193 // Upper quadword shuffled.
3194 for (unsigned i = 4; i != 8; ++i)
3195 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3201 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3202 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0));
3205 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3206 /// is suitable for input to PSHUFLW.
3207 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3208 if (VT != MVT::v8i16)
3211 // Upper quadword copied in order.
3212 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3215 // Lower quadword shuffled.
3216 for (unsigned i = 0; i != 4; ++i)
3223 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3224 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0));
3227 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3228 /// is suitable for input to PALIGNR.
3229 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3230 const X86Subtarget *Subtarget) {
3231 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3232 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3235 unsigned NumElts = VT.getVectorNumElements();
3236 unsigned NumLanes = VT.getSizeInBits()/128;
3237 unsigned NumLaneElts = NumElts/NumLanes;
3239 // Do not handle 64-bit element shuffles with palignr.
3240 if (NumLaneElts == 2)
3243 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3245 for (i = 0; i != NumLaneElts; ++i) {
3250 // Lane is all undef, go to next lane
3251 if (i == NumLaneElts)
3254 int Start = Mask[i+l];
3256 // Make sure its in this lane in one of the sources
3257 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3258 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3261 // If not lane 0, then we must match lane 0
3262 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3265 // Correct second source to be contiguous with first source
3266 if (Start >= (int)NumElts)
3267 Start -= NumElts - NumLaneElts;
3269 // Make sure we're shifting in the right direction.
3270 if (Start <= (int)(i+l))
3275 // Check the rest of the elements to see if they are consecutive.
3276 for (++i; i != NumLaneElts; ++i) {
3277 int Idx = Mask[i+l];
3279 // Make sure its in this lane
3280 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3281 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3284 // If not lane 0, then we must match lane 0
3285 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3288 if (Idx >= (int)NumElts)
3289 Idx -= NumElts - NumLaneElts;
3291 if (!isUndefOrEqual(Idx, Start+i))
3300 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3301 /// the two vector operands have swapped position.
3302 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3303 unsigned NumElems) {
3304 for (unsigned i = 0; i != NumElems; ++i) {
3308 else if (idx < (int)NumElems)
3309 Mask[i] = idx + NumElems;
3311 Mask[i] = idx - NumElems;
3315 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3316 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3317 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3318 /// reverse of what x86 shuffles want.
3319 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3320 bool Commuted = false) {
3321 if (!HasAVX && VT.getSizeInBits() == 256)
3324 unsigned NumElems = VT.getVectorNumElements();
3325 unsigned NumLanes = VT.getSizeInBits()/128;
3326 unsigned NumLaneElems = NumElems/NumLanes;
3328 if (NumLaneElems != 2 && NumLaneElems != 4)
3331 // VSHUFPSY divides the resulting vector into 4 chunks.
3332 // The sources are also splitted into 4 chunks, and each destination
3333 // chunk must come from a different source chunk.
3335 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3336 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3338 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3339 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3341 // VSHUFPDY divides the resulting vector into 4 chunks.
3342 // The sources are also splitted into 4 chunks, and each destination
3343 // chunk must come from a different source chunk.
3345 // SRC1 => X3 X2 X1 X0
3346 // SRC2 => Y3 Y2 Y1 Y0
3348 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3350 unsigned HalfLaneElems = NumLaneElems/2;
3351 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3352 for (unsigned i = 0; i != NumLaneElems; ++i) {
3353 int Idx = Mask[i+l];
3354 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3355 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3357 // For VSHUFPSY, the mask of the second half must be the same as the
3358 // first but with the appropriate offsets. This works in the same way as
3359 // VPERMILPS works with masks.
3360 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3362 if (!isUndefOrEqual(Idx, Mask[i]+l))
3370 bool X86::isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX) {
3371 return ::isSHUFPMask(N->getMask(), N->getValueType(0), HasAVX);
3374 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3375 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3376 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3377 EVT VT = N->getValueType(0);
3378 unsigned NumElems = VT.getVectorNumElements();
3380 if (VT.getSizeInBits() != 128)
3386 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3387 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3388 isUndefOrEqual(N->getMaskElt(1), 7) &&
3389 isUndefOrEqual(N->getMaskElt(2), 2) &&
3390 isUndefOrEqual(N->getMaskElt(3), 3);
3393 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3394 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3396 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3397 EVT VT = N->getValueType(0);
3398 unsigned NumElems = VT.getVectorNumElements();
3400 if (VT.getSizeInBits() != 128)
3406 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3407 isUndefOrEqual(N->getMaskElt(1), 3) &&
3408 isUndefOrEqual(N->getMaskElt(2), 2) &&
3409 isUndefOrEqual(N->getMaskElt(3), 3);
3412 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3413 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3414 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3415 EVT VT = N->getValueType(0);
3417 if (VT.getSizeInBits() != 128)
3420 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3422 if (NumElems != 2 && NumElems != 4)
3425 for (unsigned i = 0; i < NumElems/2; ++i)
3426 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3429 for (unsigned i = NumElems/2; i < NumElems; ++i)
3430 if (!isUndefOrEqual(N->getMaskElt(i), i))
3436 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3437 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3438 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3439 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3441 if ((NumElems != 2 && NumElems != 4)
3442 || N->getValueType(0).getSizeInBits() > 128)
3445 for (unsigned i = 0; i < NumElems/2; ++i)
3446 if (!isUndefOrEqual(N->getMaskElt(i), i))
3449 for (unsigned i = 0; i < NumElems/2; ++i)
3450 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3456 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3457 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3458 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3459 bool HasAVX2, bool V2IsSplat = false) {
3460 unsigned NumElts = VT.getVectorNumElements();
3462 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3463 "Unsupported vector type for unpckh");
3465 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3466 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3469 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3470 // independently on 128-bit lanes.
3471 unsigned NumLanes = VT.getSizeInBits()/128;
3472 unsigned NumLaneElts = NumElts/NumLanes;
3474 for (unsigned l = 0; l != NumLanes; ++l) {
3475 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3476 i != (l+1)*NumLaneElts;
3479 int BitI1 = Mask[i+1];
3480 if (!isUndefOrEqual(BitI, j))
3483 if (!isUndefOrEqual(BitI1, NumElts))
3486 if (!isUndefOrEqual(BitI1, j + NumElts))
3495 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3496 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3499 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3500 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3501 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3502 bool HasAVX2, bool V2IsSplat = false) {
3503 unsigned NumElts = VT.getVectorNumElements();
3505 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3506 "Unsupported vector type for unpckh");
3508 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3509 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3512 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3513 // independently on 128-bit lanes.
3514 unsigned NumLanes = VT.getSizeInBits()/128;
3515 unsigned NumLaneElts = NumElts/NumLanes;
3517 for (unsigned l = 0; l != NumLanes; ++l) {
3518 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3519 i != (l+1)*NumLaneElts; i += 2, ++j) {
3521 int BitI1 = Mask[i+1];
3522 if (!isUndefOrEqual(BitI, j))
3525 if (isUndefOrEqual(BitI1, NumElts))
3528 if (!isUndefOrEqual(BitI1, j+NumElts))
3536 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3537 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3540 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3541 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3543 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3545 unsigned NumElts = VT.getVectorNumElements();
3547 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3548 "Unsupported vector type for unpckh");
3550 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3551 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3554 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3555 // FIXME: Need a better way to get rid of this, there's no latency difference
3556 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3557 // the former later. We should also remove the "_undef" special mask.
3558 if (NumElts == 4 && VT.getSizeInBits() == 256)
3561 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3562 // independently on 128-bit lanes.
3563 unsigned NumLanes = VT.getSizeInBits()/128;
3564 unsigned NumLaneElts = NumElts/NumLanes;
3566 for (unsigned l = 0; l != NumLanes; ++l) {
3567 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3568 i != (l+1)*NumLaneElts;
3571 int BitI1 = Mask[i+1];
3573 if (!isUndefOrEqual(BitI, j))
3575 if (!isUndefOrEqual(BitI1, j))
3583 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3584 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3587 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3588 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3590 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3591 unsigned NumElts = VT.getVectorNumElements();
3593 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3594 "Unsupported vector type for unpckh");
3596 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3597 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3600 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3601 // independently on 128-bit lanes.
3602 unsigned NumLanes = VT.getSizeInBits()/128;
3603 unsigned NumLaneElts = NumElts/NumLanes;
3605 for (unsigned l = 0; l != NumLanes; ++l) {
3606 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3607 i != (l+1)*NumLaneElts; i += 2, ++j) {
3609 int BitI1 = Mask[i+1];
3610 if (!isUndefOrEqual(BitI, j))
3612 if (!isUndefOrEqual(BitI1, j))
3619 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3620 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3623 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3624 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3625 /// MOVSD, and MOVD, i.e. setting the lowest element.
3626 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3627 if (VT.getVectorElementType().getSizeInBits() < 32)
3629 if (VT.getSizeInBits() == 256)
3632 unsigned NumElts = VT.getVectorNumElements();
3634 if (!isUndefOrEqual(Mask[0], NumElts))
3637 for (unsigned i = 1; i != NumElts; ++i)
3638 if (!isUndefOrEqual(Mask[i], i))
3644 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3645 return ::isMOVLMask(N->getMask(), N->getValueType(0));
3648 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3649 /// as permutations between 128-bit chunks or halves. As an example: this
3651 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3652 /// The first half comes from the second half of V1 and the second half from the
3653 /// the second half of V2.
3654 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3655 if (!HasAVX || VT.getSizeInBits() != 256)
3658 // The shuffle result is divided into half A and half B. In total the two
3659 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3660 // B must come from C, D, E or F.
3661 unsigned HalfSize = VT.getVectorNumElements()/2;
3662 bool MatchA = false, MatchB = false;
3664 // Check if A comes from one of C, D, E, F.
3665 for (unsigned Half = 0; Half != 4; ++Half) {
3666 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3672 // Check if B comes from one of C, D, E, F.
3673 for (unsigned Half = 0; Half != 4; ++Half) {
3674 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3680 return MatchA && MatchB;
3683 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3684 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3685 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3686 EVT VT = SVOp->getValueType(0);
3688 unsigned HalfSize = VT.getVectorNumElements()/2;
3690 unsigned FstHalf = 0, SndHalf = 0;
3691 for (unsigned i = 0; i < HalfSize; ++i) {
3692 if (SVOp->getMaskElt(i) > 0) {
3693 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3697 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3698 if (SVOp->getMaskElt(i) > 0) {
3699 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3704 return (FstHalf | (SndHalf << 4));
3707 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3708 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3709 /// Note that VPERMIL mask matching is different depending whether theunderlying
3710 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3711 /// to the same elements of the low, but to the higher half of the source.
3712 /// In VPERMILPD the two lanes could be shuffled independently of each other
3713 /// with the same restriction that lanes can't be crossed.
3714 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3718 unsigned NumElts = VT.getVectorNumElements();
3719 // Only match 256-bit with 32/64-bit types
3720 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3723 unsigned NumLanes = VT.getSizeInBits()/128;
3724 unsigned LaneSize = NumElts/NumLanes;
3725 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3726 for (unsigned i = 0; i != LaneSize; ++i) {
3727 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3729 if (NumElts != 8 || l == 0)
3731 // VPERMILPS handling
3734 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3742 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3743 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3744 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3745 EVT VT = SVOp->getValueType(0);
3747 unsigned NumElts = VT.getVectorNumElements();
3748 unsigned NumLanes = VT.getSizeInBits()/128;
3749 unsigned LaneSize = NumElts/NumLanes;
3751 // Although the mask is equal for both lanes do it twice to get the cases
3752 // where a mask will match because the same mask element is undef on the
3753 // first half but valid on the second. This would get pathological cases
3754 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3755 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3757 for (unsigned i = 0; i != NumElts; ++i) {
3758 int MaskElt = SVOp->getMaskElt(i);
3761 MaskElt %= LaneSize;
3763 // VPERMILPSY, the mask of the first half must be equal to the second one
3764 if (NumElts == 8) Shamt %= LaneSize;
3765 Mask |= MaskElt << (Shamt*Shift);
3771 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3772 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3773 /// element of vector 2 and the other elements to come from vector 1 in order.
3774 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3775 bool V2IsSplat = false, bool V2IsUndef = false) {
3776 unsigned NumOps = VT.getVectorNumElements();
3777 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3780 if (!isUndefOrEqual(Mask[0], 0))
3783 for (unsigned i = 1; i != NumOps; ++i)
3784 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3785 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3786 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3792 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3793 bool V2IsUndef = false) {
3794 return isCommutedMOVLMask(N->getMask(), N->getValueType(0),
3795 V2IsSplat, V2IsUndef);
3798 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3799 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3800 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3801 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3802 const X86Subtarget *Subtarget) {
3803 if (!Subtarget->hasSSE3())
3806 // The second vector must be undef
3807 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3810 EVT VT = N->getValueType(0);
3811 unsigned NumElems = VT.getVectorNumElements();
3813 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3814 (VT.getSizeInBits() == 256 && NumElems != 8))
3817 // "i+1" is the value the indexed mask element must have
3818 for (unsigned i = 0; i < NumElems; i += 2)
3819 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3820 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3826 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3827 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3828 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3829 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3830 const X86Subtarget *Subtarget) {
3831 if (!Subtarget->hasSSE3())
3834 // The second vector must be undef
3835 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3838 EVT VT = N->getValueType(0);
3839 unsigned NumElems = VT.getVectorNumElements();
3841 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3842 (VT.getSizeInBits() == 256 && NumElems != 8))
3845 // "i" is the value the indexed mask element must have
3846 for (unsigned i = 0; i != NumElems; i += 2)
3847 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3848 !isUndefOrEqual(N->getMaskElt(i+1), i))
3854 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3855 /// specifies a shuffle of elements that is suitable for input to 256-bit
3856 /// version of MOVDDUP.
3857 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3858 unsigned NumElts = VT.getVectorNumElements();
3860 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3863 for (unsigned i = 0; i != NumElts/2; ++i)
3864 if (!isUndefOrEqual(Mask[i], 0))
3866 for (unsigned i = NumElts/2; i != NumElts; ++i)
3867 if (!isUndefOrEqual(Mask[i], NumElts/2))
3872 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3873 /// specifies a shuffle of elements that is suitable for input to 128-bit
3874 /// version of MOVDDUP.
3875 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3876 EVT VT = N->getValueType(0);
3878 if (VT.getSizeInBits() != 128)
3881 unsigned e = VT.getVectorNumElements() / 2;
3882 for (unsigned i = 0; i != e; ++i)
3883 if (!isUndefOrEqual(N->getMaskElt(i), i))
3885 for (unsigned i = 0; i != e; ++i)
3886 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3891 /// isVEXTRACTF128Index - Return true if the specified
3892 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3893 /// suitable for input to VEXTRACTF128.
3894 bool X86::isVEXTRACTF128Index(SDNode *N) {
3895 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3898 // The index should be aligned on a 128-bit boundary.
3900 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3902 unsigned VL = N->getValueType(0).getVectorNumElements();
3903 unsigned VBits = N->getValueType(0).getSizeInBits();
3904 unsigned ElSize = VBits / VL;
3905 bool Result = (Index * ElSize) % 128 == 0;
3910 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3911 /// operand specifies a subvector insert that is suitable for input to
3913 bool X86::isVINSERTF128Index(SDNode *N) {
3914 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3917 // The index should be aligned on a 128-bit boundary.
3919 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3921 unsigned VL = N->getValueType(0).getVectorNumElements();
3922 unsigned VBits = N->getValueType(0).getSizeInBits();
3923 unsigned ElSize = VBits / VL;
3924 bool Result = (Index * ElSize) % 128 == 0;
3929 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3930 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3931 /// Handles 128-bit and 256-bit.
3932 unsigned X86::getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3933 EVT VT = N->getValueType(0);
3935 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3936 "Unsupported vector type for PSHUF/SHUFP");
3938 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3939 // independently on 128-bit lanes.
3940 unsigned NumElts = VT.getVectorNumElements();
3941 unsigned NumLanes = VT.getSizeInBits()/128;
3942 unsigned NumLaneElts = NumElts/NumLanes;
3944 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3945 "Only supports 2 or 4 elements per lane");
3947 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3949 for (unsigned i = 0; i != NumElts; ++i) {
3950 int Elt = N->getMaskElt(i);
3951 if (Elt < 0) continue;
3953 unsigned ShAmt = i << Shift;
3954 if (ShAmt >= 8) ShAmt -= 8;
3955 Mask |= Elt << ShAmt;
3961 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3962 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3963 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3964 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3966 // 8 nodes, but we only care about the last 4.
3967 for (unsigned i = 7; i >= 4; --i) {
3968 int Val = SVOp->getMaskElt(i);
3977 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3978 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3979 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3980 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3982 // 8 nodes, but we only care about the first 4.
3983 for (int i = 3; i >= 0; --i) {
3984 int Val = SVOp->getMaskElt(i);
3993 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3994 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3995 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3996 EVT VT = SVOp->getValueType(0);
3997 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3999 unsigned NumElts = VT.getVectorNumElements();
4000 unsigned NumLanes = VT.getSizeInBits()/128;
4001 unsigned NumLaneElts = NumElts/NumLanes;
4005 for (i = 0; i != NumElts; ++i) {
4006 Val = SVOp->getMaskElt(i);
4010 if (Val >= (int)NumElts)
4011 Val -= NumElts - NumLaneElts;
4013 assert(Val - i > 0 && "PALIGNR imm should be positive");
4014 return (Val - i) * EltSize;
4017 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4018 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4020 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4021 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4022 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4025 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4027 EVT VecVT = N->getOperand(0).getValueType();
4028 EVT ElVT = VecVT.getVectorElementType();
4030 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4031 return Index / NumElemsPerChunk;
4034 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4035 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4037 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4038 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4039 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4042 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4044 EVT VecVT = N->getValueType(0);
4045 EVT ElVT = VecVT.getVectorElementType();
4047 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4048 return Index / NumElemsPerChunk;
4051 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4053 bool X86::isZeroNode(SDValue Elt) {
4054 return ((isa<ConstantSDNode>(Elt) &&
4055 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4056 (isa<ConstantFPSDNode>(Elt) &&
4057 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4060 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4061 /// their permute mask.
4062 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4063 SelectionDAG &DAG) {
4064 EVT VT = SVOp->getValueType(0);
4065 unsigned NumElems = VT.getVectorNumElements();
4066 SmallVector<int, 8> MaskVec;
4068 for (unsigned i = 0; i != NumElems; ++i) {
4069 int idx = SVOp->getMaskElt(i);
4071 MaskVec.push_back(idx);
4072 else if (idx < (int)NumElems)
4073 MaskVec.push_back(idx + NumElems);
4075 MaskVec.push_back(idx - NumElems);
4077 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4078 SVOp->getOperand(0), &MaskVec[0]);
4081 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4082 /// match movhlps. The lower half elements should come from upper half of
4083 /// V1 (and in order), and the upper half elements should come from the upper
4084 /// half of V2 (and in order).
4085 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4086 EVT VT = Op->getValueType(0);
4087 if (VT.getSizeInBits() != 128)
4089 if (VT.getVectorNumElements() != 4)
4091 for (unsigned i = 0, e = 2; i != e; ++i)
4092 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4094 for (unsigned i = 2; i != 4; ++i)
4095 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4100 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4101 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4103 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4104 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4106 N = N->getOperand(0).getNode();
4107 if (!ISD::isNON_EXTLoad(N))
4110 *LD = cast<LoadSDNode>(N);
4114 // Test whether the given value is a vector value which will be legalized
4116 static bool WillBeConstantPoolLoad(SDNode *N) {
4117 if (N->getOpcode() != ISD::BUILD_VECTOR)
4120 // Check for any non-constant elements.
4121 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4122 switch (N->getOperand(i).getNode()->getOpcode()) {
4124 case ISD::ConstantFP:
4131 // Vectors of all-zeros and all-ones are materialized with special
4132 // instructions rather than being loaded.
4133 return !ISD::isBuildVectorAllZeros(N) &&
4134 !ISD::isBuildVectorAllOnes(N);
4137 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4138 /// match movlp{s|d}. The lower half elements should come from lower half of
4139 /// V1 (and in order), and the upper half elements should come from the upper
4140 /// half of V2 (and in order). And since V1 will become the source of the
4141 /// MOVLP, it must be either a vector load or a scalar load to vector.
4142 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4143 ShuffleVectorSDNode *Op) {
4144 EVT VT = Op->getValueType(0);
4145 if (VT.getSizeInBits() != 128)
4148 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4150 // Is V2 is a vector load, don't do this transformation. We will try to use
4151 // load folding shufps op.
4152 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4155 unsigned NumElems = VT.getVectorNumElements();
4157 if (NumElems != 2 && NumElems != 4)
4159 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4160 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4162 for (unsigned i = NumElems/2; i != NumElems; ++i)
4163 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4168 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4170 static bool isSplatVector(SDNode *N) {
4171 if (N->getOpcode() != ISD::BUILD_VECTOR)
4174 SDValue SplatValue = N->getOperand(0);
4175 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4176 if (N->getOperand(i) != SplatValue)
4181 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4182 /// to an zero vector.
4183 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4184 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4185 SDValue V1 = N->getOperand(0);
4186 SDValue V2 = N->getOperand(1);
4187 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4188 for (unsigned i = 0; i != NumElems; ++i) {
4189 int Idx = N->getMaskElt(i);
4190 if (Idx >= (int)NumElems) {
4191 unsigned Opc = V2.getOpcode();
4192 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4194 if (Opc != ISD::BUILD_VECTOR ||
4195 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4197 } else if (Idx >= 0) {
4198 unsigned Opc = V1.getOpcode();
4199 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4201 if (Opc != ISD::BUILD_VECTOR ||
4202 !X86::isZeroNode(V1.getOperand(Idx)))
4209 /// getZeroVector - Returns a vector of specified type with all zero elements.
4211 static SDValue getZeroVector(EVT VT, bool HasSSE2, bool HasAVX2,
4212 SelectionDAG &DAG, DebugLoc dl) {
4213 assert(VT.isVector() && "Expected a vector type");
4215 // Always build SSE zero vectors as <4 x i32> bitcasted
4216 // to their dest type. This ensures they get CSE'd.
4218 if (VT.getSizeInBits() == 128) { // SSE
4219 if (HasSSE2) { // SSE2
4220 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4221 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4223 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4224 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4226 } else if (VT.getSizeInBits() == 256) { // AVX
4227 if (HasAVX2) { // AVX2
4228 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4229 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4230 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4232 // 256-bit logic and arithmetic instructions in AVX are all
4233 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4234 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4235 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4236 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4239 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4242 /// getOnesVector - Returns a vector of specified type with all bits set.
4243 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4244 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4245 /// Then bitcast to their original type, ensuring they get CSE'd.
4246 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4248 assert(VT.isVector() && "Expected a vector type");
4249 assert((VT.is128BitVector() || VT.is256BitVector())
4250 && "Expected a 128-bit or 256-bit vector type");
4252 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4254 if (VT.getSizeInBits() == 256) {
4255 if (HasAVX2) { // AVX2
4256 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4257 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4260 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4261 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4262 Vec = Insert128BitVector(InsV, Vec,
4263 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4266 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4269 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4272 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4273 /// that point to V2 points to its first element.
4274 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4275 EVT VT = SVOp->getValueType(0);
4276 unsigned NumElems = VT.getVectorNumElements();
4278 bool Changed = false;
4279 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end());
4281 for (unsigned i = 0; i != NumElems; ++i) {
4282 if (MaskVec[i] > (int)NumElems) {
4283 MaskVec[i] = NumElems;
4288 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4289 SVOp->getOperand(1), &MaskVec[0]);
4290 return SDValue(SVOp, 0);
4293 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4294 /// operation of specified width.
4295 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4297 unsigned NumElems = VT.getVectorNumElements();
4298 SmallVector<int, 8> Mask;
4299 Mask.push_back(NumElems);
4300 for (unsigned i = 1; i != NumElems; ++i)
4302 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4305 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4306 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4308 unsigned NumElems = VT.getVectorNumElements();
4309 SmallVector<int, 8> Mask;
4310 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4312 Mask.push_back(i + NumElems);
4314 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4317 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4318 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4320 unsigned NumElems = VT.getVectorNumElements();
4321 unsigned Half = NumElems/2;
4322 SmallVector<int, 8> Mask;
4323 for (unsigned i = 0; i != Half; ++i) {
4324 Mask.push_back(i + Half);
4325 Mask.push_back(i + NumElems + Half);
4327 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4330 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4331 // a generic shuffle instruction because the target has no such instructions.
4332 // Generate shuffles which repeat i16 and i8 several times until they can be
4333 // represented by v4f32 and then be manipulated by target suported shuffles.
4334 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4335 EVT VT = V.getValueType();
4336 int NumElems = VT.getVectorNumElements();
4337 DebugLoc dl = V.getDebugLoc();
4339 while (NumElems > 4) {
4340 if (EltNo < NumElems/2) {
4341 V = getUnpackl(DAG, dl, VT, V, V);
4343 V = getUnpackh(DAG, dl, VT, V, V);
4344 EltNo -= NumElems/2;
4351 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4352 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4353 EVT VT = V.getValueType();
4354 DebugLoc dl = V.getDebugLoc();
4355 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4356 && "Vector size not supported");
4358 if (VT.getSizeInBits() == 128) {
4359 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4360 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4361 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4364 // To use VPERMILPS to splat scalars, the second half of indicies must
4365 // refer to the higher part, which is a duplication of the lower one,
4366 // because VPERMILPS can only handle in-lane permutations.
4367 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4368 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4370 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4371 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4375 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4378 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4379 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4380 EVT SrcVT = SV->getValueType(0);
4381 SDValue V1 = SV->getOperand(0);
4382 DebugLoc dl = SV->getDebugLoc();
4384 int EltNo = SV->getSplatIndex();
4385 int NumElems = SrcVT.getVectorNumElements();
4386 unsigned Size = SrcVT.getSizeInBits();
4388 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4389 "Unknown how to promote splat for type");
4391 // Extract the 128-bit part containing the splat element and update
4392 // the splat element index when it refers to the higher register.
4394 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4395 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4397 EltNo -= NumElems/2;
4400 // All i16 and i8 vector types can't be used directly by a generic shuffle
4401 // instruction because the target has no such instruction. Generate shuffles
4402 // which repeat i16 and i8 several times until they fit in i32, and then can
4403 // be manipulated by target suported shuffles.
4404 EVT EltVT = SrcVT.getVectorElementType();
4405 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4406 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4408 // Recreate the 256-bit vector and place the same 128-bit vector
4409 // into the low and high part. This is necessary because we want
4410 // to use VPERM* to shuffle the vectors
4412 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4413 DAG.getConstant(0, MVT::i32), DAG, dl);
4414 V1 = Insert128BitVector(InsV, V1,
4415 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4418 return getLegalSplat(DAG, V1, EltNo);
4421 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4422 /// vector of zero or undef vector. This produces a shuffle where the low
4423 /// element of V2 is swizzled into the zero/undef vector, landing at element
4424 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4425 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4427 const X86Subtarget *Subtarget,
4428 SelectionDAG &DAG) {
4429 EVT VT = V2.getValueType();
4431 ? getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG,
4432 V2.getDebugLoc()) : DAG.getUNDEF(VT);
4433 unsigned NumElems = VT.getVectorNumElements();
4434 SmallVector<int, 16> MaskVec;
4435 for (unsigned i = 0; i != NumElems; ++i)
4436 // If this is the insertion idx, put the low elt of V2 here.
4437 MaskVec.push_back(i == Idx ? NumElems : i);
4438 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4441 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4442 /// element of the result of the vector shuffle.
4443 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4446 return SDValue(); // Limit search depth.
4448 SDValue V = SDValue(N, 0);
4449 EVT VT = V.getValueType();
4450 unsigned Opcode = V.getOpcode();
4452 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4453 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4454 Index = SV->getMaskElt(Index);
4457 return DAG.getUNDEF(VT.getVectorElementType());
4459 int NumElems = VT.getVectorNumElements();
4460 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4461 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4464 // Recurse into target specific vector shuffles to find scalars.
4465 if (isTargetShuffle(Opcode)) {
4466 int NumElems = VT.getVectorNumElements();
4467 SmallVector<unsigned, 16> ShuffleMask;
4472 ImmN = N->getOperand(N->getNumOperands()-1);
4473 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4476 case X86ISD::UNPCKH:
4477 DecodeUNPCKHMask(VT, ShuffleMask);
4479 case X86ISD::UNPCKL:
4480 DecodeUNPCKLMask(VT, ShuffleMask);
4482 case X86ISD::MOVHLPS:
4483 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4485 case X86ISD::MOVLHPS:
4486 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4488 case X86ISD::PSHUFD:
4489 ImmN = N->getOperand(N->getNumOperands()-1);
4490 DecodePSHUFMask(NumElems,
4491 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4494 case X86ISD::PSHUFHW:
4495 ImmN = N->getOperand(N->getNumOperands()-1);
4496 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4499 case X86ISD::PSHUFLW:
4500 ImmN = N->getOperand(N->getNumOperands()-1);
4501 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4505 case X86ISD::MOVSD: {
4506 // The index 0 always comes from the first element of the second source,
4507 // this is why MOVSS and MOVSD are used in the first place. The other
4508 // elements come from the other positions of the first source vector.
4509 unsigned OpNum = (Index == 0) ? 1 : 0;
4510 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4513 case X86ISD::VPERMILP:
4514 ImmN = N->getOperand(N->getNumOperands()-1);
4515 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4518 case X86ISD::VPERM2X128:
4519 ImmN = N->getOperand(N->getNumOperands()-1);
4520 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4523 case X86ISD::MOVDDUP:
4524 case X86ISD::MOVLHPD:
4525 case X86ISD::MOVLPD:
4526 case X86ISD::MOVLPS:
4527 case X86ISD::MOVSHDUP:
4528 case X86ISD::MOVSLDUP:
4529 case X86ISD::PALIGN:
4530 return SDValue(); // Not yet implemented.
4532 assert(0 && "unknown target shuffle node");
4536 Index = ShuffleMask[Index];
4538 return DAG.getUNDEF(VT.getVectorElementType());
4540 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4541 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4545 // Actual nodes that may contain scalar elements
4546 if (Opcode == ISD::BITCAST) {
4547 V = V.getOperand(0);
4548 EVT SrcVT = V.getValueType();
4549 unsigned NumElems = VT.getVectorNumElements();
4551 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4555 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4556 return (Index == 0) ? V.getOperand(0)
4557 : DAG.getUNDEF(VT.getVectorElementType());
4559 if (V.getOpcode() == ISD::BUILD_VECTOR)
4560 return V.getOperand(Index);
4565 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4566 /// shuffle operation which come from a consecutively from a zero. The
4567 /// search can start in two different directions, from left or right.
4569 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4570 bool ZerosFromLeft, SelectionDAG &DAG) {
4573 while (i < NumElems) {
4574 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4575 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4576 if (!(Elt.getNode() &&
4577 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4585 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4586 /// MaskE correspond consecutively to elements from one of the vector operands,
4587 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4589 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4590 int OpIdx, int NumElems, unsigned &OpNum) {
4591 bool SeenV1 = false;
4592 bool SeenV2 = false;
4594 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4595 int Idx = SVOp->getMaskElt(i);
4596 // Ignore undef indicies
4605 // Only accept consecutive elements from the same vector
4606 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4610 OpNum = SeenV1 ? 0 : 1;
4614 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4615 /// logical left shift of a vector.
4616 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4617 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4618 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4619 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4620 false /* check zeros from right */, DAG);
4626 // Considering the elements in the mask that are not consecutive zeros,
4627 // check if they consecutively come from only one of the source vectors.
4629 // V1 = {X, A, B, C} 0
4631 // vector_shuffle V1, V2 <1, 2, 3, X>
4633 if (!isShuffleMaskConsecutive(SVOp,
4634 0, // Mask Start Index
4635 NumElems-NumZeros-1, // Mask End Index
4636 NumZeros, // Where to start looking in the src vector
4637 NumElems, // Number of elements in vector
4638 OpSrc)) // Which source operand ?
4643 ShVal = SVOp->getOperand(OpSrc);
4647 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4648 /// logical left shift of a vector.
4649 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4650 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4651 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4652 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4653 true /* check zeros from left */, DAG);
4659 // Considering the elements in the mask that are not consecutive zeros,
4660 // check if they consecutively come from only one of the source vectors.
4662 // 0 { A, B, X, X } = V2
4664 // vector_shuffle V1, V2 <X, X, 4, 5>
4666 if (!isShuffleMaskConsecutive(SVOp,
4667 NumZeros, // Mask Start Index
4668 NumElems-1, // Mask End Index
4669 0, // Where to start looking in the src vector
4670 NumElems, // Number of elements in vector
4671 OpSrc)) // Which source operand ?
4676 ShVal = SVOp->getOperand(OpSrc);
4680 /// isVectorShift - Returns true if the shuffle can be implemented as a
4681 /// logical left or right shift of a vector.
4682 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4683 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4684 // Although the logic below support any bitwidth size, there are no
4685 // shift instructions which handle more than 128-bit vectors.
4686 if (SVOp->getValueType(0).getSizeInBits() > 128)
4689 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4690 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4696 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4698 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4699 unsigned NumNonZero, unsigned NumZero,
4701 const TargetLowering &TLI) {
4705 DebugLoc dl = Op.getDebugLoc();
4708 for (unsigned i = 0; i < 16; ++i) {
4709 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4710 if (ThisIsNonZero && First) {
4712 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4715 V = DAG.getUNDEF(MVT::v8i16);
4720 SDValue ThisElt(0, 0), LastElt(0, 0);
4721 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4722 if (LastIsNonZero) {
4723 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4724 MVT::i16, Op.getOperand(i-1));
4726 if (ThisIsNonZero) {
4727 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4728 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4729 ThisElt, DAG.getConstant(8, MVT::i8));
4731 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4735 if (ThisElt.getNode())
4736 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4737 DAG.getIntPtrConstant(i/2));
4741 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4744 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4746 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4747 unsigned NumNonZero, unsigned NumZero,
4749 const TargetLowering &TLI) {
4753 DebugLoc dl = Op.getDebugLoc();
4756 for (unsigned i = 0; i < 8; ++i) {
4757 bool isNonZero = (NonZeros & (1 << i)) != 0;
4761 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4764 V = DAG.getUNDEF(MVT::v8i16);
4767 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4768 MVT::v8i16, V, Op.getOperand(i),
4769 DAG.getIntPtrConstant(i));
4776 /// getVShift - Return a vector logical shift node.
4778 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4779 unsigned NumBits, SelectionDAG &DAG,
4780 const TargetLowering &TLI, DebugLoc dl) {
4781 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4782 EVT ShVT = MVT::v2i64;
4783 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4784 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4785 return DAG.getNode(ISD::BITCAST, dl, VT,
4786 DAG.getNode(Opc, dl, ShVT, SrcOp,
4787 DAG.getConstant(NumBits,
4788 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4792 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4793 SelectionDAG &DAG) const {
4795 // Check if the scalar load can be widened into a vector load. And if
4796 // the address is "base + cst" see if the cst can be "absorbed" into
4797 // the shuffle mask.
4798 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4799 SDValue Ptr = LD->getBasePtr();
4800 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4802 EVT PVT = LD->getValueType(0);
4803 if (PVT != MVT::i32 && PVT != MVT::f32)
4808 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4809 FI = FINode->getIndex();
4811 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4812 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4813 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4814 Offset = Ptr.getConstantOperandVal(1);
4815 Ptr = Ptr.getOperand(0);
4820 // FIXME: 256-bit vector instructions don't require a strict alignment,
4821 // improve this code to support it better.
4822 unsigned RequiredAlign = VT.getSizeInBits()/8;
4823 SDValue Chain = LD->getChain();
4824 // Make sure the stack object alignment is at least 16 or 32.
4825 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4826 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4827 if (MFI->isFixedObjectIndex(FI)) {
4828 // Can't change the alignment. FIXME: It's possible to compute
4829 // the exact stack offset and reference FI + adjust offset instead.
4830 // If someone *really* cares about this. That's the way to implement it.
4833 MFI->setObjectAlignment(FI, RequiredAlign);
4837 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4838 // Ptr + (Offset & ~15).
4841 if ((Offset % RequiredAlign) & 3)
4843 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4845 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4846 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4848 int EltNo = (Offset - StartOffset) >> 2;
4849 int NumElems = VT.getVectorNumElements();
4851 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4852 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4853 LD->getPointerInfo().getWithOffset(StartOffset),
4854 false, false, false, 0);
4856 SmallVector<int, 8> Mask;
4857 for (int i = 0; i < NumElems; ++i)
4858 Mask.push_back(EltNo);
4860 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4866 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4867 /// vector of type 'VT', see if the elements can be replaced by a single large
4868 /// load which has the same value as a build_vector whose operands are 'elts'.
4870 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4872 /// FIXME: we'd also like to handle the case where the last elements are zero
4873 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4874 /// There's even a handy isZeroNode for that purpose.
4875 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4876 DebugLoc &DL, SelectionDAG &DAG) {
4877 EVT EltVT = VT.getVectorElementType();
4878 unsigned NumElems = Elts.size();
4880 LoadSDNode *LDBase = NULL;
4881 unsigned LastLoadedElt = -1U;
4883 // For each element in the initializer, see if we've found a load or an undef.
4884 // If we don't find an initial load element, or later load elements are
4885 // non-consecutive, bail out.
4886 for (unsigned i = 0; i < NumElems; ++i) {
4887 SDValue Elt = Elts[i];
4889 if (!Elt.getNode() ||
4890 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4893 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4895 LDBase = cast<LoadSDNode>(Elt.getNode());
4899 if (Elt.getOpcode() == ISD::UNDEF)
4902 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4903 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4908 // If we have found an entire vector of loads and undefs, then return a large
4909 // load of the entire vector width starting at the base pointer. If we found
4910 // consecutive loads for the low half, generate a vzext_load node.
4911 if (LastLoadedElt == NumElems - 1) {
4912 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4913 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4914 LDBase->getPointerInfo(),
4915 LDBase->isVolatile(), LDBase->isNonTemporal(),
4916 LDBase->isInvariant(), 0);
4917 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4918 LDBase->getPointerInfo(),
4919 LDBase->isVolatile(), LDBase->isNonTemporal(),
4920 LDBase->isInvariant(), LDBase->getAlignment());
4921 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4922 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4923 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4924 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4926 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4927 LDBase->getPointerInfo(),
4928 LDBase->getAlignment(),
4929 false/*isVolatile*/, true/*ReadMem*/,
4931 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4936 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4937 /// a vbroadcast node. We support two patterns:
4938 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4939 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4941 /// The scalar load node is returned when a pattern is found,
4942 /// or SDValue() otherwise.
4943 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4944 if (!Subtarget->hasAVX())
4947 EVT VT = Op.getValueType();
4950 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4951 V = V.getOperand(0);
4953 //A suspected load to be broadcasted.
4956 switch (V.getOpcode()) {
4958 // Unknown pattern found.
4961 case ISD::BUILD_VECTOR: {
4962 // The BUILD_VECTOR node must be a splat.
4963 if (!isSplatVector(V.getNode()))
4966 Ld = V.getOperand(0);
4968 // The suspected load node has several users. Make sure that all
4969 // of its users are from the BUILD_VECTOR node.
4970 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4975 case ISD::VECTOR_SHUFFLE: {
4976 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4978 // Shuffles must have a splat mask where the first element is
4980 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4983 SDValue Sc = Op.getOperand(0);
4984 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4987 Ld = Sc.getOperand(0);
4989 // The scalar_to_vector node and the suspected
4990 // load node must have exactly one user.
4991 if (!Sc.hasOneUse() || !Ld.hasOneUse())
4997 // The scalar source must be a normal load.
4998 if (!ISD::isNormalLoad(Ld.getNode()))
5001 // Reject loads that have uses of the chain result
5002 if (Ld->hasAnyUseOfValue(1))
5005 bool Is256 = VT.getSizeInBits() == 256;
5006 bool Is128 = VT.getSizeInBits() == 128;
5007 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5009 // VBroadcast to YMM
5010 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5013 // VBroadcast to XMM
5014 if (Is128 && (ScalarSize == 32))
5017 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5018 // double since there is vbroadcastsd xmm
5019 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5020 // VBroadcast to YMM
5021 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5024 // VBroadcast to XMM
5025 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5029 // Unsupported broadcast.
5034 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5035 DebugLoc dl = Op.getDebugLoc();
5037 EVT VT = Op.getValueType();
5038 EVT ExtVT = VT.getVectorElementType();
5039 unsigned NumElems = Op.getNumOperands();
5041 // Vectors containing all zeros can be matched by pxor and xorps later
5042 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5043 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5044 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5045 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5048 return getZeroVector(VT, Subtarget->hasSSE2(),
5049 Subtarget->hasAVX2(), DAG, dl);
5052 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5053 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5054 // vpcmpeqd on 256-bit vectors.
5055 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5056 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5059 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5062 SDValue LD = isVectorBroadcast(Op, Subtarget);
5064 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5066 unsigned EVTBits = ExtVT.getSizeInBits();
5068 unsigned NumZero = 0;
5069 unsigned NumNonZero = 0;
5070 unsigned NonZeros = 0;
5071 bool IsAllConstants = true;
5072 SmallSet<SDValue, 8> Values;
5073 for (unsigned i = 0; i < NumElems; ++i) {
5074 SDValue Elt = Op.getOperand(i);
5075 if (Elt.getOpcode() == ISD::UNDEF)
5078 if (Elt.getOpcode() != ISD::Constant &&
5079 Elt.getOpcode() != ISD::ConstantFP)
5080 IsAllConstants = false;
5081 if (X86::isZeroNode(Elt))
5084 NonZeros |= (1 << i);
5089 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5090 if (NumNonZero == 0)
5091 return DAG.getUNDEF(VT);
5093 // Special case for single non-zero, non-undef, element.
5094 if (NumNonZero == 1) {
5095 unsigned Idx = CountTrailingZeros_32(NonZeros);
5096 SDValue Item = Op.getOperand(Idx);
5098 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5099 // the value are obviously zero, truncate the value to i32 and do the
5100 // insertion that way. Only do this if the value is non-constant or if the
5101 // value is a constant being inserted into element 0. It is cheaper to do
5102 // a constant pool load than it is to do a movd + shuffle.
5103 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5104 (!IsAllConstants || Idx == 0)) {
5105 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5107 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5108 EVT VecVT = MVT::v4i32;
5109 unsigned VecElts = 4;
5111 // Truncate the value (which may itself be a constant) to i32, and
5112 // convert it to a vector with movd (S2V+shuffle to zero extend).
5113 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5114 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5115 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5117 // Now we have our 32-bit value zero extended in the low element of
5118 // a vector. If Idx != 0, swizzle it into place.
5120 SmallVector<int, 4> Mask;
5121 Mask.push_back(Idx);
5122 for (unsigned i = 1; i != VecElts; ++i)
5124 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5125 DAG.getUNDEF(Item.getValueType()),
5128 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5132 // If we have a constant or non-constant insertion into the low element of
5133 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5134 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5135 // depending on what the source datatype is.
5138 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5140 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5141 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5142 if (VT.getSizeInBits() == 256) {
5143 SDValue ZeroVec = getZeroVector(VT, Subtarget->hasSSE2(),
5144 Subtarget->hasAVX2(), DAG, dl);
5145 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5146 Item, DAG.getIntPtrConstant(0));
5148 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5149 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5150 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5151 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5154 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5155 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5156 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5157 if (VT.getSizeInBits() == 256) {
5158 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget->hasSSE2(),
5159 Subtarget->hasAVX2(), DAG, dl);
5160 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5163 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5164 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5166 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5170 // Is it a vector logical left shift?
5171 if (NumElems == 2 && Idx == 1 &&
5172 X86::isZeroNode(Op.getOperand(0)) &&
5173 !X86::isZeroNode(Op.getOperand(1))) {
5174 unsigned NumBits = VT.getSizeInBits();
5175 return getVShift(true, VT,
5176 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5177 VT, Op.getOperand(1)),
5178 NumBits/2, DAG, *this, dl);
5181 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5184 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5185 // is a non-constant being inserted into an element other than the low one,
5186 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5187 // movd/movss) to move this into the low element, then shuffle it into
5189 if (EVTBits == 32) {
5190 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5192 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5193 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5194 SmallVector<int, 8> MaskVec;
5195 for (unsigned i = 0; i < NumElems; i++)
5196 MaskVec.push_back(i == Idx ? 0 : 1);
5197 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5201 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5202 if (Values.size() == 1) {
5203 if (EVTBits == 32) {
5204 // Instead of a shuffle like this:
5205 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5206 // Check if it's possible to issue this instead.
5207 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5208 unsigned Idx = CountTrailingZeros_32(NonZeros);
5209 SDValue Item = Op.getOperand(Idx);
5210 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5211 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5216 // A vector full of immediates; various special cases are already
5217 // handled, so this is best done with a single constant-pool load.
5221 // For AVX-length vectors, build the individual 128-bit pieces and use
5222 // shuffles to put them in place.
5223 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5224 SmallVector<SDValue, 32> V;
5225 for (unsigned i = 0; i < NumElems; ++i)
5226 V.push_back(Op.getOperand(i));
5228 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5230 // Build both the lower and upper subvector.
5231 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5232 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5235 // Recreate the wider vector with the lower and upper part.
5236 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5237 DAG.getConstant(0, MVT::i32), DAG, dl);
5238 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5242 // Let legalizer expand 2-wide build_vectors.
5243 if (EVTBits == 64) {
5244 if (NumNonZero == 1) {
5245 // One half is zero or undef.
5246 unsigned Idx = CountTrailingZeros_32(NonZeros);
5247 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5248 Op.getOperand(Idx));
5249 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5254 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5255 if (EVTBits == 8 && NumElems == 16) {
5256 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5258 if (V.getNode()) return V;
5261 if (EVTBits == 16 && NumElems == 8) {
5262 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5264 if (V.getNode()) return V;
5267 // If element VT is == 32 bits, turn it into a number of shuffles.
5268 SmallVector<SDValue, 8> V(NumElems);
5269 if (NumElems == 4 && NumZero > 0) {
5270 for (unsigned i = 0; i < 4; ++i) {
5271 bool isZero = !(NonZeros & (1 << i));
5273 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
5276 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5279 for (unsigned i = 0; i < 2; ++i) {
5280 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5283 V[i] = V[i*2]; // Must be a zero vector.
5286 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5289 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5292 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5297 bool Reverse1 = (NonZeros & 0x3) == 2;
5298 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5302 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5303 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5305 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5308 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5309 // Check for a build vector of consecutive loads.
5310 for (unsigned i = 0; i < NumElems; ++i)
5311 V[i] = Op.getOperand(i);
5313 // Check for elements which are consecutive loads.
5314 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5318 // For SSE 4.1, use insertps to put the high elements into the low element.
5319 if (getSubtarget()->hasSSE41()) {
5321 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5322 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5324 Result = DAG.getUNDEF(VT);
5326 for (unsigned i = 1; i < NumElems; ++i) {
5327 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5328 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5329 Op.getOperand(i), DAG.getIntPtrConstant(i));
5334 // Otherwise, expand into a number of unpckl*, start by extending each of
5335 // our (non-undef) elements to the full vector width with the element in the
5336 // bottom slot of the vector (which generates no code for SSE).
5337 for (unsigned i = 0; i < NumElems; ++i) {
5338 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5339 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5341 V[i] = DAG.getUNDEF(VT);
5344 // Next, we iteratively mix elements, e.g. for v4f32:
5345 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5346 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5347 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5348 unsigned EltStride = NumElems >> 1;
5349 while (EltStride != 0) {
5350 for (unsigned i = 0; i < EltStride; ++i) {
5351 // If V[i+EltStride] is undef and this is the first round of mixing,
5352 // then it is safe to just drop this shuffle: V[i] is already in the
5353 // right place, the one element (since it's the first round) being
5354 // inserted as undef can be dropped. This isn't safe for successive
5355 // rounds because they will permute elements within both vectors.
5356 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5357 EltStride == NumElems/2)
5360 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5369 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5370 // them in a MMX register. This is better than doing a stack convert.
5371 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5372 DebugLoc dl = Op.getDebugLoc();
5373 EVT ResVT = Op.getValueType();
5375 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5376 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5378 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5379 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5380 InVec = Op.getOperand(1);
5381 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5382 unsigned NumElts = ResVT.getVectorNumElements();
5383 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5384 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5385 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5387 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5388 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5389 Mask[0] = 0; Mask[1] = 2;
5390 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5392 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5395 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5396 // to create 256-bit vectors from two other 128-bit ones.
5397 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5398 DebugLoc dl = Op.getDebugLoc();
5399 EVT ResVT = Op.getValueType();
5401 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5403 SDValue V1 = Op.getOperand(0);
5404 SDValue V2 = Op.getOperand(1);
5405 unsigned NumElems = ResVT.getVectorNumElements();
5407 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5408 DAG.getConstant(0, MVT::i32), DAG, dl);
5409 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5414 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5415 EVT ResVT = Op.getValueType();
5417 assert(Op.getNumOperands() == 2);
5418 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5419 "Unsupported CONCAT_VECTORS for value type");
5421 // We support concatenate two MMX registers and place them in a MMX register.
5422 // This is better than doing a stack convert.
5423 if (ResVT.is128BitVector())
5424 return LowerMMXCONCAT_VECTORS(Op, DAG);
5426 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5427 // from two other 128-bit ones.
5428 return LowerAVXCONCAT_VECTORS(Op, DAG);
5431 // v8i16 shuffles - Prefer shuffles in the following order:
5432 // 1. [all] pshuflw, pshufhw, optional move
5433 // 2. [ssse3] 1 x pshufb
5434 // 3. [ssse3] 2 x pshufb + 1 x por
5435 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5437 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5438 SelectionDAG &DAG) const {
5439 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5440 SDValue V1 = SVOp->getOperand(0);
5441 SDValue V2 = SVOp->getOperand(1);
5442 DebugLoc dl = SVOp->getDebugLoc();
5443 SmallVector<int, 8> MaskVals;
5445 // Determine if more than 1 of the words in each of the low and high quadwords
5446 // of the result come from the same quadword of one of the two inputs. Undef
5447 // mask values count as coming from any quadword, for better codegen.
5448 unsigned LoQuad[] = { 0, 0, 0, 0 };
5449 unsigned HiQuad[] = { 0, 0, 0, 0 };
5450 BitVector InputQuads(4);
5451 for (unsigned i = 0; i < 8; ++i) {
5452 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5453 int EltIdx = SVOp->getMaskElt(i);
5454 MaskVals.push_back(EltIdx);
5463 InputQuads.set(EltIdx / 4);
5466 int BestLoQuad = -1;
5467 unsigned MaxQuad = 1;
5468 for (unsigned i = 0; i < 4; ++i) {
5469 if (LoQuad[i] > MaxQuad) {
5471 MaxQuad = LoQuad[i];
5475 int BestHiQuad = -1;
5477 for (unsigned i = 0; i < 4; ++i) {
5478 if (HiQuad[i] > MaxQuad) {
5480 MaxQuad = HiQuad[i];
5484 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5485 // of the two input vectors, shuffle them into one input vector so only a
5486 // single pshufb instruction is necessary. If There are more than 2 input
5487 // quads, disable the next transformation since it does not help SSSE3.
5488 bool V1Used = InputQuads[0] || InputQuads[1];
5489 bool V2Used = InputQuads[2] || InputQuads[3];
5490 if (Subtarget->hasSSSE3()) {
5491 if (InputQuads.count() == 2 && V1Used && V2Used) {
5492 BestLoQuad = InputQuads.find_first();
5493 BestHiQuad = InputQuads.find_next(BestLoQuad);
5495 if (InputQuads.count() > 2) {
5501 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5502 // the shuffle mask. If a quad is scored as -1, that means that it contains
5503 // words from all 4 input quadwords.
5505 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5507 BestLoQuad < 0 ? 0 : BestLoQuad,
5508 BestHiQuad < 0 ? 1 : BestHiQuad
5510 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5511 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5512 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5513 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5515 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5516 // source words for the shuffle, to aid later transformations.
5517 bool AllWordsInNewV = true;
5518 bool InOrder[2] = { true, true };
5519 for (unsigned i = 0; i != 8; ++i) {
5520 int idx = MaskVals[i];
5522 InOrder[i/4] = false;
5523 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5525 AllWordsInNewV = false;
5529 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5530 if (AllWordsInNewV) {
5531 for (int i = 0; i != 8; ++i) {
5532 int idx = MaskVals[i];
5535 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5536 if ((idx != i) && idx < 4)
5538 if ((idx != i) && idx > 3)
5547 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5548 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5549 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5550 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5551 unsigned TargetMask = 0;
5552 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5553 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5554 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5555 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5556 V1 = NewV.getOperand(0);
5557 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5561 // If we have SSSE3, and all words of the result are from 1 input vector,
5562 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5563 // is present, fall back to case 4.
5564 if (Subtarget->hasSSSE3()) {
5565 SmallVector<SDValue,16> pshufbMask;
5567 // If we have elements from both input vectors, set the high bit of the
5568 // shuffle mask element to zero out elements that come from V2 in the V1
5569 // mask, and elements that come from V1 in the V2 mask, so that the two
5570 // results can be OR'd together.
5571 bool TwoInputs = V1Used && V2Used;
5572 for (unsigned i = 0; i != 8; ++i) {
5573 int EltIdx = MaskVals[i] * 2;
5574 if (TwoInputs && (EltIdx >= 16)) {
5575 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5576 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5579 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5580 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5582 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5583 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5584 DAG.getNode(ISD::BUILD_VECTOR, dl,
5585 MVT::v16i8, &pshufbMask[0], 16));
5587 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5589 // Calculate the shuffle mask for the second input, shuffle it, and
5590 // OR it with the first shuffled input.
5592 for (unsigned i = 0; i != 8; ++i) {
5593 int EltIdx = MaskVals[i] * 2;
5595 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5596 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5599 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5600 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5602 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5603 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5604 DAG.getNode(ISD::BUILD_VECTOR, dl,
5605 MVT::v16i8, &pshufbMask[0], 16));
5606 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5607 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5610 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5611 // and update MaskVals with new element order.
5612 std::bitset<8> InOrder;
5613 if (BestLoQuad >= 0) {
5614 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5615 for (int i = 0; i != 4; ++i) {
5616 int idx = MaskVals[i];
5619 } else if ((idx / 4) == BestLoQuad) {
5624 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5627 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5628 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5630 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5634 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5635 // and update MaskVals with the new element order.
5636 if (BestHiQuad >= 0) {
5637 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5638 for (unsigned i = 4; i != 8; ++i) {
5639 int idx = MaskVals[i];
5642 } else if ((idx / 4) == BestHiQuad) {
5643 MaskV[i] = (idx & 3) + 4;
5647 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5650 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5651 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5653 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5657 // In case BestHi & BestLo were both -1, which means each quadword has a word
5658 // from each of the four input quadwords, calculate the InOrder bitvector now
5659 // before falling through to the insert/extract cleanup.
5660 if (BestLoQuad == -1 && BestHiQuad == -1) {
5662 for (int i = 0; i != 8; ++i)
5663 if (MaskVals[i] < 0 || MaskVals[i] == i)
5667 // The other elements are put in the right place using pextrw and pinsrw.
5668 for (unsigned i = 0; i != 8; ++i) {
5671 int EltIdx = MaskVals[i];
5674 SDValue ExtOp = (EltIdx < 8)
5675 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5676 DAG.getIntPtrConstant(EltIdx))
5677 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5678 DAG.getIntPtrConstant(EltIdx - 8));
5679 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5680 DAG.getIntPtrConstant(i));
5685 // v16i8 shuffles - Prefer shuffles in the following order:
5686 // 1. [ssse3] 1 x pshufb
5687 // 2. [ssse3] 2 x pshufb + 1 x por
5688 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5690 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5692 const X86TargetLowering &TLI) {
5693 SDValue V1 = SVOp->getOperand(0);
5694 SDValue V2 = SVOp->getOperand(1);
5695 DebugLoc dl = SVOp->getDebugLoc();
5696 ArrayRef<int> MaskVals = SVOp->getMask();
5698 // If we have SSSE3, case 1 is generated when all result bytes come from
5699 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5700 // present, fall back to case 3.
5701 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5704 for (unsigned i = 0; i < 16; ++i) {
5705 int EltIdx = MaskVals[i];
5714 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5715 if (TLI.getSubtarget()->hasSSSE3()) {
5716 SmallVector<SDValue,16> pshufbMask;
5718 // If all result elements are from one input vector, then only translate
5719 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5721 // Otherwise, we have elements from both input vectors, and must zero out
5722 // elements that come from V2 in the first mask, and V1 in the second mask
5723 // so that we can OR them together.
5724 bool TwoInputs = !(V1Only || V2Only);
5725 for (unsigned i = 0; i != 16; ++i) {
5726 int EltIdx = MaskVals[i];
5727 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5728 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5731 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5733 // If all the elements are from V2, assign it to V1 and return after
5734 // building the first pshufb.
5737 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5738 DAG.getNode(ISD::BUILD_VECTOR, dl,
5739 MVT::v16i8, &pshufbMask[0], 16));
5743 // Calculate the shuffle mask for the second input, shuffle it, and
5744 // OR it with the first shuffled input.
5746 for (unsigned i = 0; i != 16; ++i) {
5747 int EltIdx = MaskVals[i];
5749 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5752 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5754 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5755 DAG.getNode(ISD::BUILD_VECTOR, dl,
5756 MVT::v16i8, &pshufbMask[0], 16));
5757 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5760 // No SSSE3 - Calculate in place words and then fix all out of place words
5761 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5762 // the 16 different words that comprise the two doublequadword input vectors.
5763 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5764 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5765 SDValue NewV = V2Only ? V2 : V1;
5766 for (int i = 0; i != 8; ++i) {
5767 int Elt0 = MaskVals[i*2];
5768 int Elt1 = MaskVals[i*2+1];
5770 // This word of the result is all undef, skip it.
5771 if (Elt0 < 0 && Elt1 < 0)
5774 // This word of the result is already in the correct place, skip it.
5775 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5777 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5780 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5781 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5784 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5785 // using a single extract together, load it and store it.
5786 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5787 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5788 DAG.getIntPtrConstant(Elt1 / 2));
5789 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5790 DAG.getIntPtrConstant(i));
5794 // If Elt1 is defined, extract it from the appropriate source. If the
5795 // source byte is not also odd, shift the extracted word left 8 bits
5796 // otherwise clear the bottom 8 bits if we need to do an or.
5798 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5799 DAG.getIntPtrConstant(Elt1 / 2));
5800 if ((Elt1 & 1) == 0)
5801 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5803 TLI.getShiftAmountTy(InsElt.getValueType())));
5805 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5806 DAG.getConstant(0xFF00, MVT::i16));
5808 // If Elt0 is defined, extract it from the appropriate source. If the
5809 // source byte is not also even, shift the extracted word right 8 bits. If
5810 // Elt1 was also defined, OR the extracted values together before
5811 // inserting them in the result.
5813 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5814 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5815 if ((Elt0 & 1) != 0)
5816 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5818 TLI.getShiftAmountTy(InsElt0.getValueType())));
5820 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5821 DAG.getConstant(0x00FF, MVT::i16));
5822 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5825 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5826 DAG.getIntPtrConstant(i));
5828 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5831 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5832 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5833 /// done when every pair / quad of shuffle mask elements point to elements in
5834 /// the right sequence. e.g.
5835 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5837 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5838 SelectionDAG &DAG, DebugLoc dl) {
5839 EVT VT = SVOp->getValueType(0);
5840 SDValue V1 = SVOp->getOperand(0);
5841 SDValue V2 = SVOp->getOperand(1);
5842 unsigned NumElems = VT.getVectorNumElements();
5843 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5845 switch (VT.getSimpleVT().SimpleTy) {
5846 default: assert(false && "Unexpected!");
5847 case MVT::v4f32: NewVT = MVT::v2f64; break;
5848 case MVT::v4i32: NewVT = MVT::v2i64; break;
5849 case MVT::v8i16: NewVT = MVT::v4i32; break;
5850 case MVT::v16i8: NewVT = MVT::v4i32; break;
5853 int Scale = NumElems / NewWidth;
5854 SmallVector<int, 8> MaskVec;
5855 for (unsigned i = 0; i < NumElems; i += Scale) {
5857 for (int j = 0; j < Scale; ++j) {
5858 int EltIdx = SVOp->getMaskElt(i+j);
5862 StartIdx = EltIdx - (EltIdx % Scale);
5863 if (EltIdx != StartIdx + j)
5867 MaskVec.push_back(-1);
5869 MaskVec.push_back(StartIdx / Scale);
5872 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5873 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5874 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5877 /// getVZextMovL - Return a zero-extending vector move low node.
5879 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5880 SDValue SrcOp, SelectionDAG &DAG,
5881 const X86Subtarget *Subtarget, DebugLoc dl) {
5882 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5883 LoadSDNode *LD = NULL;
5884 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5885 LD = dyn_cast<LoadSDNode>(SrcOp);
5887 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5889 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5890 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5891 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5892 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5893 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5895 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5896 return DAG.getNode(ISD::BITCAST, dl, VT,
5897 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5906 return DAG.getNode(ISD::BITCAST, dl, VT,
5907 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5908 DAG.getNode(ISD::BITCAST, dl,
5912 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5913 /// which could not be matched by any known target speficic shuffle
5915 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5916 EVT VT = SVOp->getValueType(0);
5918 unsigned NumElems = VT.getVectorNumElements();
5919 unsigned NumLaneElems = NumElems / 2;
5921 int MinRange[2][2] = { { static_cast<int>(NumElems),
5922 static_cast<int>(NumElems) },
5923 { static_cast<int>(NumElems),
5924 static_cast<int>(NumElems) } };
5925 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5927 // Collect used ranges for each source in each lane
5928 for (unsigned l = 0; l < 2; ++l) {
5929 unsigned LaneStart = l*NumLaneElems;
5930 for (unsigned i = 0; i != NumLaneElems; ++i) {
5931 int Idx = SVOp->getMaskElt(i+LaneStart);
5936 if (Idx >= (int)NumElems) {
5941 if (Idx > MaxRange[l][Input])
5942 MaxRange[l][Input] = Idx;
5943 if (Idx < MinRange[l][Input])
5944 MinRange[l][Input] = Idx;
5948 // Make sure each range is 128-bits
5949 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5950 for (unsigned l = 0; l < 2; ++l) {
5951 for (unsigned Input = 0; Input < 2; ++Input) {
5952 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5955 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems)
5956 ExtractIdx[l][Input] = 0;
5957 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5958 MaxRange[l][Input] < (int)NumElems)
5959 ExtractIdx[l][Input] = NumLaneElems;
5965 DebugLoc dl = SVOp->getDebugLoc();
5966 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5967 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5970 for (unsigned l = 0; l < 2; ++l) {
5971 for (unsigned Input = 0; Input < 2; ++Input) {
5972 if (ExtractIdx[l][Input] >= 0)
5973 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
5974 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
5977 Ops[l][Input] = DAG.getUNDEF(NVT);
5981 // Generate 128-bit shuffles
5982 SmallVector<int, 16> Mask1, Mask2;
5983 for (unsigned i = 0; i != NumLaneElems; ++i) {
5984 int Elt = SVOp->getMaskElt(i);
5985 if (Elt >= (int)NumElems) {
5986 Elt %= NumLaneElems;
5987 Elt += NumLaneElems;
5988 } else if (Elt >= 0) {
5989 Elt %= NumLaneElems;
5991 Mask1.push_back(Elt);
5993 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
5994 int Elt = SVOp->getMaskElt(i);
5995 if (Elt >= (int)NumElems) {
5996 Elt %= NumLaneElems;
5997 Elt += NumLaneElems;
5998 } else if (Elt >= 0) {
5999 Elt %= NumLaneElems;
6001 Mask2.push_back(Elt);
6004 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
6005 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
6007 // Concatenate the result back
6008 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
6009 DAG.getConstant(0, MVT::i32), DAG, dl);
6010 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
6014 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6015 /// 4 elements, and match them with several different shuffle types.
6017 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6018 SDValue V1 = SVOp->getOperand(0);
6019 SDValue V2 = SVOp->getOperand(1);
6020 DebugLoc dl = SVOp->getDebugLoc();
6021 EVT VT = SVOp->getValueType(0);
6023 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6025 std::pair<int, int> Locs[4];
6026 int Mask1[] = { -1, -1, -1, -1 };
6027 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6031 for (unsigned i = 0; i != 4; ++i) {
6032 int Idx = PermMask[i];
6034 Locs[i] = std::make_pair(-1, -1);
6036 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6038 Locs[i] = std::make_pair(0, NumLo);
6042 Locs[i] = std::make_pair(1, NumHi);
6044 Mask1[2+NumHi] = Idx;
6050 if (NumLo <= 2 && NumHi <= 2) {
6051 // If no more than two elements come from either vector. This can be
6052 // implemented with two shuffles. First shuffle gather the elements.
6053 // The second shuffle, which takes the first shuffle as both of its
6054 // vector operands, put the elements into the right order.
6055 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6057 int Mask2[] = { -1, -1, -1, -1 };
6059 for (unsigned i = 0; i != 4; ++i)
6060 if (Locs[i].first != -1) {
6061 unsigned Idx = (i < 2) ? 0 : 4;
6062 Idx += Locs[i].first * 2 + Locs[i].second;
6066 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6067 } else if (NumLo == 3 || NumHi == 3) {
6068 // Otherwise, we must have three elements from one vector, call it X, and
6069 // one element from the other, call it Y. First, use a shufps to build an
6070 // intermediate vector with the one element from Y and the element from X
6071 // that will be in the same half in the final destination (the indexes don't
6072 // matter). Then, use a shufps to build the final vector, taking the half
6073 // containing the element from Y from the intermediate, and the other half
6076 // Normalize it so the 3 elements come from V1.
6077 CommuteVectorShuffleMask(PermMask, 4);
6081 // Find the element from V2.
6083 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6084 int Val = PermMask[HiIndex];
6091 Mask1[0] = PermMask[HiIndex];
6093 Mask1[2] = PermMask[HiIndex^1];
6095 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6098 Mask1[0] = PermMask[0];
6099 Mask1[1] = PermMask[1];
6100 Mask1[2] = HiIndex & 1 ? 6 : 4;
6101 Mask1[3] = HiIndex & 1 ? 4 : 6;
6102 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6104 Mask1[0] = HiIndex & 1 ? 2 : 0;
6105 Mask1[1] = HiIndex & 1 ? 0 : 2;
6106 Mask1[2] = PermMask[2];
6107 Mask1[3] = PermMask[3];
6112 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6116 // Break it into (shuffle shuffle_hi, shuffle_lo).
6117 int LoMask[] = { -1, -1, -1, -1 };
6118 int HiMask[] = { -1, -1, -1, -1 };
6120 int *MaskPtr = LoMask;
6121 unsigned MaskIdx = 0;
6124 for (unsigned i = 0; i != 4; ++i) {
6131 int Idx = PermMask[i];
6133 Locs[i] = std::make_pair(-1, -1);
6134 } else if (Idx < 4) {
6135 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6136 MaskPtr[LoIdx] = Idx;
6139 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6140 MaskPtr[HiIdx] = Idx;
6145 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6146 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6147 int MaskOps[] = { -1, -1, -1, -1 };
6148 for (unsigned i = 0; i != 4; ++i)
6149 if (Locs[i].first != -1)
6150 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6151 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6154 static bool MayFoldVectorLoad(SDValue V) {
6155 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6156 V = V.getOperand(0);
6157 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6158 V = V.getOperand(0);
6159 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6160 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6161 // BUILD_VECTOR (load), undef
6162 V = V.getOperand(0);
6168 // FIXME: the version above should always be used. Since there's
6169 // a bug where several vector shuffles can't be folded because the
6170 // DAG is not updated during lowering and a node claims to have two
6171 // uses while it only has one, use this version, and let isel match
6172 // another instruction if the load really happens to have more than
6173 // one use. Remove this version after this bug get fixed.
6174 // rdar://8434668, PR8156
6175 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6176 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6177 V = V.getOperand(0);
6178 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6179 V = V.getOperand(0);
6180 if (ISD::isNormalLoad(V.getNode()))
6185 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6186 /// a vector extract, and if both can be later optimized into a single load.
6187 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6188 /// here because otherwise a target specific shuffle node is going to be
6189 /// emitted for this shuffle, and the optimization not done.
6190 /// FIXME: This is probably not the best approach, but fix the problem
6191 /// until the right path is decided.
6193 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6194 const TargetLowering &TLI) {
6195 EVT VT = V.getValueType();
6196 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6198 // Be sure that the vector shuffle is present in a pattern like this:
6199 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6203 SDNode *N = *V.getNode()->use_begin();
6204 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6207 SDValue EltNo = N->getOperand(1);
6208 if (!isa<ConstantSDNode>(EltNo))
6211 // If the bit convert changed the number of elements, it is unsafe
6212 // to examine the mask.
6213 bool HasShuffleIntoBitcast = false;
6214 if (V.getOpcode() == ISD::BITCAST) {
6215 EVT SrcVT = V.getOperand(0).getValueType();
6216 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6218 V = V.getOperand(0);
6219 HasShuffleIntoBitcast = true;
6222 // Select the input vector, guarding against out of range extract vector.
6223 unsigned NumElems = VT.getVectorNumElements();
6224 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6225 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6226 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6228 // If we are accessing the upper part of a YMM register
6229 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6230 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6231 // because the legalization of N did not happen yet.
6232 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6235 // Skip one more bit_convert if necessary
6236 if (V.getOpcode() == ISD::BITCAST)
6237 V = V.getOperand(0);
6239 if (!ISD::isNormalLoad(V.getNode()))
6242 // Is the original load suitable?
6243 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6245 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6248 if (!HasShuffleIntoBitcast)
6251 // If there's a bitcast before the shuffle, check if the load type and
6252 // alignment is valid.
6253 unsigned Align = LN0->getAlignment();
6255 TLI.getTargetData()->getABITypeAlignment(
6256 VT.getTypeForEVT(*DAG.getContext()));
6258 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6265 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6266 EVT VT = Op.getValueType();
6268 // Canonizalize to v2f64.
6269 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6270 return DAG.getNode(ISD::BITCAST, dl, VT,
6271 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6276 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6278 SDValue V1 = Op.getOperand(0);
6279 SDValue V2 = Op.getOperand(1);
6280 EVT VT = Op.getValueType();
6282 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6284 if (HasSSE2 && VT == MVT::v2f64)
6285 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6287 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6288 return DAG.getNode(ISD::BITCAST, dl, VT,
6289 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6290 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6291 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6295 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6296 SDValue V1 = Op.getOperand(0);
6297 SDValue V2 = Op.getOperand(1);
6298 EVT VT = Op.getValueType();
6300 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6301 "unsupported shuffle type");
6303 if (V2.getOpcode() == ISD::UNDEF)
6307 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6311 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6312 SDValue V1 = Op.getOperand(0);
6313 SDValue V2 = Op.getOperand(1);
6314 EVT VT = Op.getValueType();
6315 unsigned NumElems = VT.getVectorNumElements();
6317 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6318 // operand of these instructions is only memory, so check if there's a
6319 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6321 bool CanFoldLoad = false;
6323 // Trivial case, when V2 comes from a load.
6324 if (MayFoldVectorLoad(V2))
6327 // When V1 is a load, it can be folded later into a store in isel, example:
6328 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6330 // (MOVLPSmr addr:$src1, VR128:$src2)
6331 // So, recognize this potential and also use MOVLPS or MOVLPD
6332 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6337 if (HasSSE2 && NumElems == 2)
6338 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6341 // If we don't care about the second element, procede to use movss.
6342 if (SVOp->getMaskElt(1) != -1)
6343 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6346 // movl and movlp will both match v2i64, but v2i64 is never matched by
6347 // movl earlier because we make it strict to avoid messing with the movlp load
6348 // folding logic (see the code above getMOVLP call). Match it here then,
6349 // this is horrible, but will stay like this until we move all shuffle
6350 // matching to x86 specific nodes. Note that for the 1st condition all
6351 // types are matched with movsd.
6353 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6354 // as to remove this logic from here, as much as possible
6355 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6356 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6357 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6360 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6362 // Invert the operand order and use SHUFPS to match it.
6363 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6364 X86::getShuffleSHUFImmediate(SVOp), DAG);
6368 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6369 const TargetLowering &TLI,
6370 const X86Subtarget *Subtarget) {
6371 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6372 EVT VT = Op.getValueType();
6373 DebugLoc dl = Op.getDebugLoc();
6374 SDValue V1 = Op.getOperand(0);
6375 SDValue V2 = Op.getOperand(1);
6377 if (isZeroShuffle(SVOp))
6378 return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
6381 // Handle splat operations
6382 if (SVOp->isSplat()) {
6383 unsigned NumElem = VT.getVectorNumElements();
6384 int Size = VT.getSizeInBits();
6385 // Special case, this is the only place now where it's allowed to return
6386 // a vector_shuffle operation without using a target specific node, because
6387 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6388 // this be moved to DAGCombine instead?
6389 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6392 // Use vbroadcast whenever the splat comes from a foldable load
6393 SDValue LD = isVectorBroadcast(Op, Subtarget);
6395 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6397 // Handle splats by matching through known shuffle masks
6398 if ((Size == 128 && NumElem <= 4) ||
6399 (Size == 256 && NumElem < 8))
6402 // All remaning splats are promoted to target supported vector shuffles.
6403 return PromoteSplat(SVOp, DAG);
6406 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6408 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6409 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6410 if (NewOp.getNode())
6411 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6412 } else if ((VT == MVT::v4i32 ||
6413 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6414 // FIXME: Figure out a cleaner way to do this.
6415 // Try to make use of movq to zero out the top part.
6416 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6417 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6418 if (NewOp.getNode()) {
6419 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6420 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6421 DAG, Subtarget, dl);
6423 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6424 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6425 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6426 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6427 DAG, Subtarget, dl);
6434 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6435 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6436 SDValue V1 = Op.getOperand(0);
6437 SDValue V2 = Op.getOperand(1);
6438 EVT VT = Op.getValueType();
6439 DebugLoc dl = Op.getDebugLoc();
6440 unsigned NumElems = VT.getVectorNumElements();
6441 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6442 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6443 bool V1IsSplat = false;
6444 bool V2IsSplat = false;
6445 bool HasSSE2 = Subtarget->hasSSE2();
6446 bool HasAVX = Subtarget->hasAVX();
6447 bool HasAVX2 = Subtarget->hasAVX2();
6448 MachineFunction &MF = DAG.getMachineFunction();
6449 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6451 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6453 if (V1IsUndef && V2IsUndef)
6454 return DAG.getUNDEF(VT);
6456 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6458 // Vector shuffle lowering takes 3 steps:
6460 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6461 // narrowing and commutation of operands should be handled.
6462 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6464 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6465 // so the shuffle can be broken into other shuffles and the legalizer can
6466 // try the lowering again.
6468 // The general idea is that no vector_shuffle operation should be left to
6469 // be matched during isel, all of them must be converted to a target specific
6472 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6473 // narrowing and commutation of operands should be handled. The actual code
6474 // doesn't include all of those, work in progress...
6475 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6476 if (NewOp.getNode())
6479 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6480 // unpckh_undef). Only use pshufd if speed is more important than size.
6481 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6482 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6483 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6484 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6486 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() &&
6487 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6488 return getMOVDDup(Op, dl, V1, DAG);
6490 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6491 return getMOVHighToLow(Op, dl, DAG);
6493 // Use to match splats
6494 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6495 (VT == MVT::v2f64 || VT == MVT::v2i64))
6496 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6498 if (X86::isPSHUFDMask(SVOp)) {
6499 // The actual implementation will match the mask in the if above and then
6500 // during isel it can match several different instructions, not only pshufd
6501 // as its name says, sad but true, emulate the behavior for now...
6502 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6503 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6505 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6507 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6508 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6510 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6514 // Check if this can be converted into a logical shift.
6515 bool isLeft = false;
6518 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6519 if (isShift && ShVal.hasOneUse()) {
6520 // If the shifted value has multiple uses, it may be cheaper to use
6521 // v_set0 + movlhps or movhlps, etc.
6522 EVT EltVT = VT.getVectorElementType();
6523 ShAmt *= EltVT.getSizeInBits();
6524 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6527 if (X86::isMOVLMask(SVOp)) {
6528 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6529 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6530 if (!X86::isMOVLPMask(SVOp)) {
6531 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6532 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6534 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6535 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6539 // FIXME: fold these into legal mask.
6540 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6541 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6543 if (X86::isMOVHLPSMask(SVOp))
6544 return getMOVHighToLow(Op, dl, DAG);
6546 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6547 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6549 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6550 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6552 if (X86::isMOVLPMask(SVOp))
6553 return getMOVLP(Op, dl, DAG, HasSSE2);
6555 if (ShouldXformToMOVHLPS(SVOp) ||
6556 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6557 return CommuteVectorShuffle(SVOp, DAG);
6560 // No better options. Use a vshldq / vsrldq.
6561 EVT EltVT = VT.getVectorElementType();
6562 ShAmt *= EltVT.getSizeInBits();
6563 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6566 bool Commuted = false;
6567 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6568 // 1,1,1,1 -> v8i16 though.
6569 V1IsSplat = isSplatVector(V1.getNode());
6570 V2IsSplat = isSplatVector(V2.getNode());
6572 // Canonicalize the splat or undef, if present, to be on the RHS.
6573 if (V1IsSplat && !V2IsSplat) {
6574 Op = CommuteVectorShuffle(SVOp, DAG);
6575 SVOp = cast<ShuffleVectorSDNode>(Op);
6576 V1 = SVOp->getOperand(0);
6577 V2 = SVOp->getOperand(1);
6578 std::swap(V1IsSplat, V2IsSplat);
6582 ArrayRef<int> M = SVOp->getMask();
6584 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6585 // Shuffling low element of v1 into undef, just return v1.
6588 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6589 // the instruction selector will not match, so get a canonical MOVL with
6590 // swapped operands to undo the commute.
6591 return getMOVL(DAG, dl, VT, V2, V1);
6594 if (isUNPCKLMask(M, VT, HasAVX2))
6595 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6597 if (isUNPCKHMask(M, VT, HasAVX2))
6598 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6601 // Normalize mask so all entries that point to V2 points to its first
6602 // element then try to match unpck{h|l} again. If match, return a
6603 // new vector_shuffle with the corrected mask.
6604 SDValue NewMask = NormalizeMask(SVOp, DAG);
6605 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6606 if (NSVOp != SVOp) {
6607 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6609 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6616 // Commute is back and try unpck* again.
6617 // FIXME: this seems wrong.
6618 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6619 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6621 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6622 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6624 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6625 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6628 // Normalize the node to match x86 shuffle ops if needed
6629 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6630 return CommuteVectorShuffle(SVOp, DAG);
6632 // The checks below are all present in isShuffleMaskLegal, but they are
6633 // inlined here right now to enable us to directly emit target specific
6634 // nodes, and remove one by one until they don't return Op anymore.
6636 if (isPALIGNRMask(M, VT, Subtarget))
6637 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6638 getShufflePALIGNRImmediate(SVOp),
6641 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6642 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6643 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6644 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6647 if (isPSHUFHWMask(M, VT))
6648 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6649 X86::getShufflePSHUFHWImmediate(SVOp),
6652 if (isPSHUFLWMask(M, VT))
6653 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6654 X86::getShufflePSHUFLWImmediate(SVOp),
6657 if (isSHUFPMask(M, VT, HasAVX))
6658 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6659 X86::getShuffleSHUFImmediate(SVOp), DAG);
6661 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6662 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6663 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6664 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6666 //===--------------------------------------------------------------------===//
6667 // Generate target specific nodes for 128 or 256-bit shuffles only
6668 // supported in the AVX instruction set.
6671 // Handle VMOVDDUPY permutations
6672 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6673 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6675 // Handle VPERMILPS/D* permutations
6676 if (isVPERMILPMask(M, VT, HasAVX))
6677 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6678 getShuffleVPERMILPImmediate(SVOp), DAG);
6680 // Handle VPERM2F128/VPERM2I128 permutations
6681 if (isVPERM2X128Mask(M, VT, HasAVX))
6682 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6683 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6685 //===--------------------------------------------------------------------===//
6686 // Since no target specific shuffle was selected for this generic one,
6687 // lower it into other known shuffles. FIXME: this isn't true yet, but
6688 // this is the plan.
6691 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6692 if (VT == MVT::v8i16) {
6693 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6694 if (NewOp.getNode())
6698 if (VT == MVT::v16i8) {
6699 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6700 if (NewOp.getNode())
6704 // Handle all 128-bit wide vectors with 4 elements, and match them with
6705 // several different shuffle types.
6706 if (NumElems == 4 && VT.getSizeInBits() == 128)
6707 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6709 // Handle general 256-bit shuffles
6710 if (VT.is256BitVector())
6711 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6717 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6718 SelectionDAG &DAG) const {
6719 EVT VT = Op.getValueType();
6720 DebugLoc dl = Op.getDebugLoc();
6722 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6725 if (VT.getSizeInBits() == 8) {
6726 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6727 Op.getOperand(0), Op.getOperand(1));
6728 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6729 DAG.getValueType(VT));
6730 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6731 } else if (VT.getSizeInBits() == 16) {
6732 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6733 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6735 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6736 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6737 DAG.getNode(ISD::BITCAST, dl,
6741 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6742 Op.getOperand(0), Op.getOperand(1));
6743 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6744 DAG.getValueType(VT));
6745 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6746 } else if (VT == MVT::f32) {
6747 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6748 // the result back to FR32 register. It's only worth matching if the
6749 // result has a single use which is a store or a bitcast to i32. And in
6750 // the case of a store, it's not worth it if the index is a constant 0,
6751 // because a MOVSSmr can be used instead, which is smaller and faster.
6752 if (!Op.hasOneUse())
6754 SDNode *User = *Op.getNode()->use_begin();
6755 if ((User->getOpcode() != ISD::STORE ||
6756 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6757 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6758 (User->getOpcode() != ISD::BITCAST ||
6759 User->getValueType(0) != MVT::i32))
6761 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6762 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6765 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6766 } else if (VT == MVT::i32 || VT == MVT::i64) {
6767 // ExtractPS/pextrq works with constant index.
6768 if (isa<ConstantSDNode>(Op.getOperand(1)))
6776 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6777 SelectionDAG &DAG) const {
6778 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6781 SDValue Vec = Op.getOperand(0);
6782 EVT VecVT = Vec.getValueType();
6784 // If this is a 256-bit vector result, first extract the 128-bit vector and
6785 // then extract the element from the 128-bit vector.
6786 if (VecVT.getSizeInBits() == 256) {
6787 DebugLoc dl = Op.getNode()->getDebugLoc();
6788 unsigned NumElems = VecVT.getVectorNumElements();
6789 SDValue Idx = Op.getOperand(1);
6790 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6792 // Get the 128-bit vector.
6793 bool Upper = IdxVal >= NumElems/2;
6794 Vec = Extract128BitVector(Vec,
6795 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6797 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6798 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6801 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6803 if (Subtarget->hasSSE41()) {
6804 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6809 EVT VT = Op.getValueType();
6810 DebugLoc dl = Op.getDebugLoc();
6811 // TODO: handle v16i8.
6812 if (VT.getSizeInBits() == 16) {
6813 SDValue Vec = Op.getOperand(0);
6814 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6816 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6817 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6818 DAG.getNode(ISD::BITCAST, dl,
6821 // Transform it so it match pextrw which produces a 32-bit result.
6822 EVT EltVT = MVT::i32;
6823 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6824 Op.getOperand(0), Op.getOperand(1));
6825 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6826 DAG.getValueType(VT));
6827 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6828 } else if (VT.getSizeInBits() == 32) {
6829 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6833 // SHUFPS the element to the lowest double word, then movss.
6834 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6835 EVT VVT = Op.getOperand(0).getValueType();
6836 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6837 DAG.getUNDEF(VVT), Mask);
6838 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6839 DAG.getIntPtrConstant(0));
6840 } else if (VT.getSizeInBits() == 64) {
6841 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6842 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6843 // to match extract_elt for f64.
6844 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6848 // UNPCKHPD the element to the lowest double word, then movsd.
6849 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6850 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6851 int Mask[2] = { 1, -1 };
6852 EVT VVT = Op.getOperand(0).getValueType();
6853 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6854 DAG.getUNDEF(VVT), Mask);
6855 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6856 DAG.getIntPtrConstant(0));
6863 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6864 SelectionDAG &DAG) const {
6865 EVT VT = Op.getValueType();
6866 EVT EltVT = VT.getVectorElementType();
6867 DebugLoc dl = Op.getDebugLoc();
6869 SDValue N0 = Op.getOperand(0);
6870 SDValue N1 = Op.getOperand(1);
6871 SDValue N2 = Op.getOperand(2);
6873 if (VT.getSizeInBits() == 256)
6876 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6877 isa<ConstantSDNode>(N2)) {
6879 if (VT == MVT::v8i16)
6880 Opc = X86ISD::PINSRW;
6881 else if (VT == MVT::v16i8)
6882 Opc = X86ISD::PINSRB;
6884 Opc = X86ISD::PINSRB;
6886 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6888 if (N1.getValueType() != MVT::i32)
6889 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6890 if (N2.getValueType() != MVT::i32)
6891 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6892 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6893 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6894 // Bits [7:6] of the constant are the source select. This will always be
6895 // zero here. The DAG Combiner may combine an extract_elt index into these
6896 // bits. For example (insert (extract, 3), 2) could be matched by putting
6897 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6898 // Bits [5:4] of the constant are the destination select. This is the
6899 // value of the incoming immediate.
6900 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6901 // combine either bitwise AND or insert of float 0.0 to set these bits.
6902 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6903 // Create this as a scalar to vector..
6904 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6905 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6906 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6907 isa<ConstantSDNode>(N2)) {
6908 // PINSR* works with constant index.
6915 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6916 EVT VT = Op.getValueType();
6917 EVT EltVT = VT.getVectorElementType();
6919 DebugLoc dl = Op.getDebugLoc();
6920 SDValue N0 = Op.getOperand(0);
6921 SDValue N1 = Op.getOperand(1);
6922 SDValue N2 = Op.getOperand(2);
6924 // If this is a 256-bit vector result, first extract the 128-bit vector,
6925 // insert the element into the extracted half and then place it back.
6926 if (VT.getSizeInBits() == 256) {
6927 if (!isa<ConstantSDNode>(N2))
6930 // Get the desired 128-bit vector half.
6931 unsigned NumElems = VT.getVectorNumElements();
6932 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6933 bool Upper = IdxVal >= NumElems/2;
6934 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6935 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6937 // Insert the element into the desired half.
6938 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6939 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6941 // Insert the changed part back to the 256-bit vector
6942 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6945 if (Subtarget->hasSSE41())
6946 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6948 if (EltVT == MVT::i8)
6951 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6952 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6953 // as its second argument.
6954 if (N1.getValueType() != MVT::i32)
6955 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6956 if (N2.getValueType() != MVT::i32)
6957 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6958 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6964 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6965 LLVMContext *Context = DAG.getContext();
6966 DebugLoc dl = Op.getDebugLoc();
6967 EVT OpVT = Op.getValueType();
6969 // If this is a 256-bit vector result, first insert into a 128-bit
6970 // vector and then insert into the 256-bit vector.
6971 if (OpVT.getSizeInBits() > 128) {
6972 // Insert into a 128-bit vector.
6973 EVT VT128 = EVT::getVectorVT(*Context,
6974 OpVT.getVectorElementType(),
6975 OpVT.getVectorNumElements() / 2);
6977 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6979 // Insert the 128-bit vector.
6980 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6981 DAG.getConstant(0, MVT::i32),
6985 if (Op.getValueType() == MVT::v1i64 &&
6986 Op.getOperand(0).getValueType() == MVT::i64)
6987 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6989 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6990 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6991 "Expected an SSE type!");
6992 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6993 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6996 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6997 // a simple subregister reference or explicit instructions to grab
6998 // upper bits of a vector.
7000 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7001 if (Subtarget->hasAVX()) {
7002 DebugLoc dl = Op.getNode()->getDebugLoc();
7003 SDValue Vec = Op.getNode()->getOperand(0);
7004 SDValue Idx = Op.getNode()->getOperand(1);
7006 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7007 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7008 return Extract128BitVector(Vec, Idx, DAG, dl);
7014 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7015 // simple superregister reference or explicit instructions to insert
7016 // the upper bits of a vector.
7018 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7019 if (Subtarget->hasAVX()) {
7020 DebugLoc dl = Op.getNode()->getDebugLoc();
7021 SDValue Vec = Op.getNode()->getOperand(0);
7022 SDValue SubVec = Op.getNode()->getOperand(1);
7023 SDValue Idx = Op.getNode()->getOperand(2);
7025 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7026 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7027 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7033 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7034 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7035 // one of the above mentioned nodes. It has to be wrapped because otherwise
7036 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7037 // be used to form addressing mode. These wrapped nodes will be selected
7040 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7041 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7043 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7045 unsigned char OpFlag = 0;
7046 unsigned WrapperKind = X86ISD::Wrapper;
7047 CodeModel::Model M = getTargetMachine().getCodeModel();
7049 if (Subtarget->isPICStyleRIPRel() &&
7050 (M == CodeModel::Small || M == CodeModel::Kernel))
7051 WrapperKind = X86ISD::WrapperRIP;
7052 else if (Subtarget->isPICStyleGOT())
7053 OpFlag = X86II::MO_GOTOFF;
7054 else if (Subtarget->isPICStyleStubPIC())
7055 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7057 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7059 CP->getOffset(), OpFlag);
7060 DebugLoc DL = CP->getDebugLoc();
7061 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7062 // With PIC, the address is actually $g + Offset.
7064 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7065 DAG.getNode(X86ISD::GlobalBaseReg,
7066 DebugLoc(), getPointerTy()),
7073 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7074 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7076 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7078 unsigned char OpFlag = 0;
7079 unsigned WrapperKind = X86ISD::Wrapper;
7080 CodeModel::Model M = getTargetMachine().getCodeModel();
7082 if (Subtarget->isPICStyleRIPRel() &&
7083 (M == CodeModel::Small || M == CodeModel::Kernel))
7084 WrapperKind = X86ISD::WrapperRIP;
7085 else if (Subtarget->isPICStyleGOT())
7086 OpFlag = X86II::MO_GOTOFF;
7087 else if (Subtarget->isPICStyleStubPIC())
7088 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7090 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7092 DebugLoc DL = JT->getDebugLoc();
7093 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7095 // With PIC, the address is actually $g + Offset.
7097 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7098 DAG.getNode(X86ISD::GlobalBaseReg,
7099 DebugLoc(), getPointerTy()),
7106 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7107 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7109 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7111 unsigned char OpFlag = 0;
7112 unsigned WrapperKind = X86ISD::Wrapper;
7113 CodeModel::Model M = getTargetMachine().getCodeModel();
7115 if (Subtarget->isPICStyleRIPRel() &&
7116 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7117 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7118 OpFlag = X86II::MO_GOTPCREL;
7119 WrapperKind = X86ISD::WrapperRIP;
7120 } else if (Subtarget->isPICStyleGOT()) {
7121 OpFlag = X86II::MO_GOT;
7122 } else if (Subtarget->isPICStyleStubPIC()) {
7123 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7124 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7125 OpFlag = X86II::MO_DARWIN_NONLAZY;
7128 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7130 DebugLoc DL = Op.getDebugLoc();
7131 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7134 // With PIC, the address is actually $g + Offset.
7135 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7136 !Subtarget->is64Bit()) {
7137 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7138 DAG.getNode(X86ISD::GlobalBaseReg,
7139 DebugLoc(), getPointerTy()),
7143 // For symbols that require a load from a stub to get the address, emit the
7145 if (isGlobalStubReference(OpFlag))
7146 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7147 MachinePointerInfo::getGOT(), false, false, false, 0);
7153 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7154 // Create the TargetBlockAddressAddress node.
7155 unsigned char OpFlags =
7156 Subtarget->ClassifyBlockAddressReference();
7157 CodeModel::Model M = getTargetMachine().getCodeModel();
7158 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7159 DebugLoc dl = Op.getDebugLoc();
7160 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7161 /*isTarget=*/true, OpFlags);
7163 if (Subtarget->isPICStyleRIPRel() &&
7164 (M == CodeModel::Small || M == CodeModel::Kernel))
7165 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7167 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7169 // With PIC, the address is actually $g + Offset.
7170 if (isGlobalRelativeToPICBase(OpFlags)) {
7171 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7172 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7180 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7182 SelectionDAG &DAG) const {
7183 // Create the TargetGlobalAddress node, folding in the constant
7184 // offset if it is legal.
7185 unsigned char OpFlags =
7186 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7187 CodeModel::Model M = getTargetMachine().getCodeModel();
7189 if (OpFlags == X86II::MO_NO_FLAG &&
7190 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7191 // A direct static reference to a global.
7192 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7195 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7198 if (Subtarget->isPICStyleRIPRel() &&
7199 (M == CodeModel::Small || M == CodeModel::Kernel))
7200 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7202 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7204 // With PIC, the address is actually $g + Offset.
7205 if (isGlobalRelativeToPICBase(OpFlags)) {
7206 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7207 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7211 // For globals that require a load from a stub to get the address, emit the
7213 if (isGlobalStubReference(OpFlags))
7214 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7215 MachinePointerInfo::getGOT(), false, false, false, 0);
7217 // If there was a non-zero offset that we didn't fold, create an explicit
7220 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7221 DAG.getConstant(Offset, getPointerTy()));
7227 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7228 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7229 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7230 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7234 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7235 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7236 unsigned char OperandFlags) {
7237 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7238 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7239 DebugLoc dl = GA->getDebugLoc();
7240 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7241 GA->getValueType(0),
7245 SDValue Ops[] = { Chain, TGA, *InFlag };
7246 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7248 SDValue Ops[] = { Chain, TGA };
7249 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7252 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7253 MFI->setAdjustsStack(true);
7255 SDValue Flag = Chain.getValue(1);
7256 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7259 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7261 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7264 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7265 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7266 DAG.getNode(X86ISD::GlobalBaseReg,
7267 DebugLoc(), PtrVT), InFlag);
7268 InFlag = Chain.getValue(1);
7270 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7273 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7275 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7277 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7278 X86::RAX, X86II::MO_TLSGD);
7281 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7282 // "local exec" model.
7283 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7284 const EVT PtrVT, TLSModel::Model model,
7286 DebugLoc dl = GA->getDebugLoc();
7288 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7289 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7290 is64Bit ? 257 : 256));
7292 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7293 DAG.getIntPtrConstant(0),
7294 MachinePointerInfo(Ptr),
7295 false, false, false, 0);
7297 unsigned char OperandFlags = 0;
7298 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7300 unsigned WrapperKind = X86ISD::Wrapper;
7301 if (model == TLSModel::LocalExec) {
7302 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7303 } else if (is64Bit) {
7304 assert(model == TLSModel::InitialExec);
7305 OperandFlags = X86II::MO_GOTTPOFF;
7306 WrapperKind = X86ISD::WrapperRIP;
7308 assert(model == TLSModel::InitialExec);
7309 OperandFlags = X86II::MO_INDNTPOFF;
7312 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7314 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7315 GA->getValueType(0),
7316 GA->getOffset(), OperandFlags);
7317 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7319 if (model == TLSModel::InitialExec)
7320 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7321 MachinePointerInfo::getGOT(), false, false, false, 0);
7323 // The address of the thread local variable is the add of the thread
7324 // pointer with the offset of the variable.
7325 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7329 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7331 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7332 const GlobalValue *GV = GA->getGlobal();
7334 if (Subtarget->isTargetELF()) {
7335 // TODO: implement the "local dynamic" model
7336 // TODO: implement the "initial exec"model for pic executables
7338 // If GV is an alias then use the aliasee for determining
7339 // thread-localness.
7340 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7341 GV = GA->resolveAliasedGlobal(false);
7343 TLSModel::Model model
7344 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7347 case TLSModel::GeneralDynamic:
7348 case TLSModel::LocalDynamic: // not implemented
7349 if (Subtarget->is64Bit())
7350 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7351 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7353 case TLSModel::InitialExec:
7354 case TLSModel::LocalExec:
7355 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7356 Subtarget->is64Bit());
7358 } else if (Subtarget->isTargetDarwin()) {
7359 // Darwin only has one model of TLS. Lower to that.
7360 unsigned char OpFlag = 0;
7361 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7362 X86ISD::WrapperRIP : X86ISD::Wrapper;
7364 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7366 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7367 !Subtarget->is64Bit();
7369 OpFlag = X86II::MO_TLVP_PIC_BASE;
7371 OpFlag = X86II::MO_TLVP;
7372 DebugLoc DL = Op.getDebugLoc();
7373 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7374 GA->getValueType(0),
7375 GA->getOffset(), OpFlag);
7376 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7378 // With PIC32, the address is actually $g + Offset.
7380 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7381 DAG.getNode(X86ISD::GlobalBaseReg,
7382 DebugLoc(), getPointerTy()),
7385 // Lowering the machine isd will make sure everything is in the right
7387 SDValue Chain = DAG.getEntryNode();
7388 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7389 SDValue Args[] = { Chain, Offset };
7390 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7392 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7393 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7394 MFI->setAdjustsStack(true);
7396 // And our return value (tls address) is in the standard call return value
7398 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7399 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7403 llvm_unreachable("TLS not implemented for this target.");
7407 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7408 /// and take a 2 x i32 value to shift plus a shift amount.
7409 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7410 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7411 EVT VT = Op.getValueType();
7412 unsigned VTBits = VT.getSizeInBits();
7413 DebugLoc dl = Op.getDebugLoc();
7414 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7415 SDValue ShOpLo = Op.getOperand(0);
7416 SDValue ShOpHi = Op.getOperand(1);
7417 SDValue ShAmt = Op.getOperand(2);
7418 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7419 DAG.getConstant(VTBits - 1, MVT::i8))
7420 : DAG.getConstant(0, VT);
7423 if (Op.getOpcode() == ISD::SHL_PARTS) {
7424 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7425 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7427 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7428 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7431 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7432 DAG.getConstant(VTBits, MVT::i8));
7433 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7434 AndNode, DAG.getConstant(0, MVT::i8));
7437 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7438 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7439 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7441 if (Op.getOpcode() == ISD::SHL_PARTS) {
7442 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7443 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7445 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7446 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7449 SDValue Ops[2] = { Lo, Hi };
7450 return DAG.getMergeValues(Ops, 2, dl);
7453 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7454 SelectionDAG &DAG) const {
7455 EVT SrcVT = Op.getOperand(0).getValueType();
7457 if (SrcVT.isVector())
7460 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7461 "Unknown SINT_TO_FP to lower!");
7463 // These are really Legal; return the operand so the caller accepts it as
7465 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7467 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7468 Subtarget->is64Bit()) {
7472 DebugLoc dl = Op.getDebugLoc();
7473 unsigned Size = SrcVT.getSizeInBits()/8;
7474 MachineFunction &MF = DAG.getMachineFunction();
7475 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7476 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7477 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7479 MachinePointerInfo::getFixedStack(SSFI),
7481 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7484 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7486 SelectionDAG &DAG) const {
7488 DebugLoc DL = Op.getDebugLoc();
7490 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7492 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7494 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7496 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7498 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7499 MachineMemOperand *MMO;
7501 int SSFI = FI->getIndex();
7503 DAG.getMachineFunction()
7504 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7505 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7507 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7508 StackSlot = StackSlot.getOperand(1);
7510 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7511 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7513 Tys, Ops, array_lengthof(Ops),
7517 Chain = Result.getValue(1);
7518 SDValue InFlag = Result.getValue(2);
7520 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7521 // shouldn't be necessary except that RFP cannot be live across
7522 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7523 MachineFunction &MF = DAG.getMachineFunction();
7524 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7525 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7526 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7527 Tys = DAG.getVTList(MVT::Other);
7529 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7531 MachineMemOperand *MMO =
7532 DAG.getMachineFunction()
7533 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7534 MachineMemOperand::MOStore, SSFISize, SSFISize);
7536 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7537 Ops, array_lengthof(Ops),
7538 Op.getValueType(), MMO);
7539 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7540 MachinePointerInfo::getFixedStack(SSFI),
7541 false, false, false, 0);
7547 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7548 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7549 SelectionDAG &DAG) const {
7550 // This algorithm is not obvious. Here it is what we're trying to output:
7553 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7554 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7558 pshufd $0x4e, %xmm0, %xmm1
7563 DebugLoc dl = Op.getDebugLoc();
7564 LLVMContext *Context = DAG.getContext();
7566 // Build some magic constants.
7567 SmallVector<Constant*,4> CV0;
7568 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7569 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7570 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7571 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7572 Constant *C0 = ConstantVector::get(CV0);
7573 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7575 SmallVector<Constant*,2> CV1;
7577 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7579 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7580 Constant *C1 = ConstantVector::get(CV1);
7581 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7583 // Load the 64-bit value into an XMM register.
7584 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7586 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7587 MachinePointerInfo::getConstantPool(),
7588 false, false, false, 16);
7589 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7590 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7593 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7594 MachinePointerInfo::getConstantPool(),
7595 false, false, false, 16);
7596 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7597 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7600 if (Subtarget->hasSSE3()) {
7601 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7602 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7604 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7605 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7607 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7608 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7612 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7613 DAG.getIntPtrConstant(0));
7616 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7617 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7618 SelectionDAG &DAG) const {
7619 DebugLoc dl = Op.getDebugLoc();
7620 // FP constant to bias correct the final result.
7621 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7624 // Load the 32-bit value into an XMM register.
7625 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7628 // Zero out the upper parts of the register.
7629 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7631 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7632 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7633 DAG.getIntPtrConstant(0));
7635 // Or the load with the bias.
7636 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7637 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7638 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7640 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7641 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7642 MVT::v2f64, Bias)));
7643 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7644 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7645 DAG.getIntPtrConstant(0));
7647 // Subtract the bias.
7648 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7650 // Handle final rounding.
7651 EVT DestVT = Op.getValueType();
7653 if (DestVT.bitsLT(MVT::f64)) {
7654 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7655 DAG.getIntPtrConstant(0));
7656 } else if (DestVT.bitsGT(MVT::f64)) {
7657 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7660 // Handle final rounding.
7664 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7665 SelectionDAG &DAG) const {
7666 SDValue N0 = Op.getOperand(0);
7667 DebugLoc dl = Op.getDebugLoc();
7669 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7670 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7671 // the optimization here.
7672 if (DAG.SignBitIsZero(N0))
7673 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7675 EVT SrcVT = N0.getValueType();
7676 EVT DstVT = Op.getValueType();
7677 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7678 return LowerUINT_TO_FP_i64(Op, DAG);
7679 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7680 return LowerUINT_TO_FP_i32(Op, DAG);
7681 else if (Subtarget->is64Bit() &&
7682 SrcVT == MVT::i64 && DstVT == MVT::f32)
7685 // Make a 64-bit buffer, and use it to build an FILD.
7686 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7687 if (SrcVT == MVT::i32) {
7688 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7689 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7690 getPointerTy(), StackSlot, WordOff);
7691 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7692 StackSlot, MachinePointerInfo(),
7694 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7695 OffsetSlot, MachinePointerInfo(),
7697 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7701 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7702 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7703 StackSlot, MachinePointerInfo(),
7705 // For i64 source, we need to add the appropriate power of 2 if the input
7706 // was negative. This is the same as the optimization in
7707 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7708 // we must be careful to do the computation in x87 extended precision, not
7709 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7710 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7711 MachineMemOperand *MMO =
7712 DAG.getMachineFunction()
7713 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7714 MachineMemOperand::MOLoad, 8, 8);
7716 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7717 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7718 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7721 APInt FF(32, 0x5F800000ULL);
7723 // Check whether the sign bit is set.
7724 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7725 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7728 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7729 SDValue FudgePtr = DAG.getConstantPool(
7730 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7733 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7734 SDValue Zero = DAG.getIntPtrConstant(0);
7735 SDValue Four = DAG.getIntPtrConstant(4);
7736 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7738 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7740 // Load the value out, extending it from f32 to f80.
7741 // FIXME: Avoid the extend by constructing the right constant pool?
7742 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7743 FudgePtr, MachinePointerInfo::getConstantPool(),
7744 MVT::f32, false, false, 4);
7745 // Extend everything to 80 bits to force it to be done on x87.
7746 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7747 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7750 std::pair<SDValue,SDValue> X86TargetLowering::
7751 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7752 DebugLoc DL = Op.getDebugLoc();
7754 EVT DstTy = Op.getValueType();
7757 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7761 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7762 DstTy.getSimpleVT() >= MVT::i16 &&
7763 "Unknown FP_TO_SINT to lower!");
7765 // These are really Legal.
7766 if (DstTy == MVT::i32 &&
7767 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7768 return std::make_pair(SDValue(), SDValue());
7769 if (Subtarget->is64Bit() &&
7770 DstTy == MVT::i64 &&
7771 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7772 return std::make_pair(SDValue(), SDValue());
7774 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7776 MachineFunction &MF = DAG.getMachineFunction();
7777 unsigned MemSize = DstTy.getSizeInBits()/8;
7778 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7779 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7784 switch (DstTy.getSimpleVT().SimpleTy) {
7785 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7786 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7787 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7788 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7791 SDValue Chain = DAG.getEntryNode();
7792 SDValue Value = Op.getOperand(0);
7793 EVT TheVT = Op.getOperand(0).getValueType();
7794 if (isScalarFPTypeInSSEReg(TheVT)) {
7795 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7796 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7797 MachinePointerInfo::getFixedStack(SSFI),
7799 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7801 Chain, StackSlot, DAG.getValueType(TheVT)
7804 MachineMemOperand *MMO =
7805 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7806 MachineMemOperand::MOLoad, MemSize, MemSize);
7807 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7809 Chain = Value.getValue(1);
7810 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7811 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7814 MachineMemOperand *MMO =
7815 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7816 MachineMemOperand::MOStore, MemSize, MemSize);
7818 // Build the FP_TO_INT*_IN_MEM
7819 SDValue Ops[] = { Chain, Value, StackSlot };
7820 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7821 Ops, 3, DstTy, MMO);
7823 return std::make_pair(FIST, StackSlot);
7826 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7827 SelectionDAG &DAG) const {
7828 if (Op.getValueType().isVector())
7831 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7832 SDValue FIST = Vals.first, StackSlot = Vals.second;
7833 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7834 if (FIST.getNode() == 0) return Op;
7837 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7838 FIST, StackSlot, MachinePointerInfo(),
7839 false, false, false, 0);
7842 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7843 SelectionDAG &DAG) const {
7844 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7845 SDValue FIST = Vals.first, StackSlot = Vals.second;
7846 assert(FIST.getNode() && "Unexpected failure");
7849 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7850 FIST, StackSlot, MachinePointerInfo(),
7851 false, false, false, 0);
7854 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7855 SelectionDAG &DAG) const {
7856 LLVMContext *Context = DAG.getContext();
7857 DebugLoc dl = Op.getDebugLoc();
7858 EVT VT = Op.getValueType();
7861 EltVT = VT.getVectorElementType();
7863 if (EltVT == MVT::f64) {
7864 C = ConstantVector::getSplat(2,
7865 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7867 C = ConstantVector::getSplat(4,
7868 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7870 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7871 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7872 MachinePointerInfo::getConstantPool(),
7873 false, false, false, 16);
7874 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7877 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7878 LLVMContext *Context = DAG.getContext();
7879 DebugLoc dl = Op.getDebugLoc();
7880 EVT VT = Op.getValueType();
7882 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7883 if (VT.isVector()) {
7884 EltVT = VT.getVectorElementType();
7885 NumElts = VT.getVectorNumElements();
7888 if (EltVT == MVT::f64)
7889 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7891 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7892 C = ConstantVector::getSplat(NumElts, C);
7893 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7894 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7895 MachinePointerInfo::getConstantPool(),
7896 false, false, false, 16);
7897 if (VT.isVector()) {
7898 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7899 return DAG.getNode(ISD::BITCAST, dl, VT,
7900 DAG.getNode(ISD::XOR, dl, XORVT,
7901 DAG.getNode(ISD::BITCAST, dl, XORVT,
7903 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7905 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7909 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7910 LLVMContext *Context = DAG.getContext();
7911 SDValue Op0 = Op.getOperand(0);
7912 SDValue Op1 = Op.getOperand(1);
7913 DebugLoc dl = Op.getDebugLoc();
7914 EVT VT = Op.getValueType();
7915 EVT SrcVT = Op1.getValueType();
7917 // If second operand is smaller, extend it first.
7918 if (SrcVT.bitsLT(VT)) {
7919 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7922 // And if it is bigger, shrink it first.
7923 if (SrcVT.bitsGT(VT)) {
7924 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7928 // At this point the operands and the result should have the same
7929 // type, and that won't be f80 since that is not custom lowered.
7931 // First get the sign bit of second operand.
7932 SmallVector<Constant*,4> CV;
7933 if (SrcVT == MVT::f64) {
7934 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7935 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7937 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7938 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7939 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7940 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7942 Constant *C = ConstantVector::get(CV);
7943 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7944 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7945 MachinePointerInfo::getConstantPool(),
7946 false, false, false, 16);
7947 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7949 // Shift sign bit right or left if the two operands have different types.
7950 if (SrcVT.bitsGT(VT)) {
7951 // Op0 is MVT::f32, Op1 is MVT::f64.
7952 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7953 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7954 DAG.getConstant(32, MVT::i32));
7955 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7956 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7957 DAG.getIntPtrConstant(0));
7960 // Clear first operand sign bit.
7962 if (VT == MVT::f64) {
7963 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7964 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7966 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7967 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7968 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7969 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7971 C = ConstantVector::get(CV);
7972 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7973 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7974 MachinePointerInfo::getConstantPool(),
7975 false, false, false, 16);
7976 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7978 // Or the value with the sign bit.
7979 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7982 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7983 SDValue N0 = Op.getOperand(0);
7984 DebugLoc dl = Op.getDebugLoc();
7985 EVT VT = Op.getValueType();
7987 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7988 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7989 DAG.getConstant(1, VT));
7990 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7993 /// Emit nodes that will be selected as "test Op0,Op0", or something
7995 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7996 SelectionDAG &DAG) const {
7997 DebugLoc dl = Op.getDebugLoc();
7999 // CF and OF aren't always set the way we want. Determine which
8000 // of these we need.
8001 bool NeedCF = false;
8002 bool NeedOF = false;
8005 case X86::COND_A: case X86::COND_AE:
8006 case X86::COND_B: case X86::COND_BE:
8009 case X86::COND_G: case X86::COND_GE:
8010 case X86::COND_L: case X86::COND_LE:
8011 case X86::COND_O: case X86::COND_NO:
8016 // See if we can use the EFLAGS value from the operand instead of
8017 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8018 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8019 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8020 // Emit a CMP with 0, which is the TEST pattern.
8021 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8022 DAG.getConstant(0, Op.getValueType()));
8024 unsigned Opcode = 0;
8025 unsigned NumOperands = 0;
8026 switch (Op.getNode()->getOpcode()) {
8028 // Due to an isel shortcoming, be conservative if this add is likely to be
8029 // selected as part of a load-modify-store instruction. When the root node
8030 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8031 // uses of other nodes in the match, such as the ADD in this case. This
8032 // leads to the ADD being left around and reselected, with the result being
8033 // two adds in the output. Alas, even if none our users are stores, that
8034 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8035 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8036 // climbing the DAG back to the root, and it doesn't seem to be worth the
8038 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8039 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8040 if (UI->getOpcode() != ISD::CopyToReg &&
8041 UI->getOpcode() != ISD::SETCC &&
8042 UI->getOpcode() != ISD::STORE)
8045 if (ConstantSDNode *C =
8046 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8047 // An add of one will be selected as an INC.
8048 if (C->getAPIntValue() == 1) {
8049 Opcode = X86ISD::INC;
8054 // An add of negative one (subtract of one) will be selected as a DEC.
8055 if (C->getAPIntValue().isAllOnesValue()) {
8056 Opcode = X86ISD::DEC;
8062 // Otherwise use a regular EFLAGS-setting add.
8063 Opcode = X86ISD::ADD;
8067 // If the primary and result isn't used, don't bother using X86ISD::AND,
8068 // because a TEST instruction will be better.
8069 bool NonFlagUse = false;
8070 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8071 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8073 unsigned UOpNo = UI.getOperandNo();
8074 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8075 // Look pass truncate.
8076 UOpNo = User->use_begin().getOperandNo();
8077 User = *User->use_begin();
8080 if (User->getOpcode() != ISD::BRCOND &&
8081 User->getOpcode() != ISD::SETCC &&
8082 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8095 // Due to the ISEL shortcoming noted above, be conservative if this op is
8096 // likely to be selected as part of a load-modify-store instruction.
8097 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8098 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8099 if (UI->getOpcode() == ISD::STORE)
8102 // Otherwise use a regular EFLAGS-setting instruction.
8103 switch (Op.getNode()->getOpcode()) {
8104 default: llvm_unreachable("unexpected operator!");
8105 case ISD::SUB: Opcode = X86ISD::SUB; break;
8106 case ISD::OR: Opcode = X86ISD::OR; break;
8107 case ISD::XOR: Opcode = X86ISD::XOR; break;
8108 case ISD::AND: Opcode = X86ISD::AND; break;
8120 return SDValue(Op.getNode(), 1);
8127 // Emit a CMP with 0, which is the TEST pattern.
8128 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8129 DAG.getConstant(0, Op.getValueType()));
8131 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8132 SmallVector<SDValue, 4> Ops;
8133 for (unsigned i = 0; i != NumOperands; ++i)
8134 Ops.push_back(Op.getOperand(i));
8136 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8137 DAG.ReplaceAllUsesWith(Op, New);
8138 return SDValue(New.getNode(), 1);
8141 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8143 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8144 SelectionDAG &DAG) const {
8145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8146 if (C->getAPIntValue() == 0)
8147 return EmitTest(Op0, X86CC, DAG);
8149 DebugLoc dl = Op0.getDebugLoc();
8150 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8153 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8154 /// if it's possible.
8155 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8156 DebugLoc dl, SelectionDAG &DAG) const {
8157 SDValue Op0 = And.getOperand(0);
8158 SDValue Op1 = And.getOperand(1);
8159 if (Op0.getOpcode() == ISD::TRUNCATE)
8160 Op0 = Op0.getOperand(0);
8161 if (Op1.getOpcode() == ISD::TRUNCATE)
8162 Op1 = Op1.getOperand(0);
8165 if (Op1.getOpcode() == ISD::SHL)
8166 std::swap(Op0, Op1);
8167 if (Op0.getOpcode() == ISD::SHL) {
8168 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8169 if (And00C->getZExtValue() == 1) {
8170 // If we looked past a truncate, check that it's only truncating away
8172 unsigned BitWidth = Op0.getValueSizeInBits();
8173 unsigned AndBitWidth = And.getValueSizeInBits();
8174 if (BitWidth > AndBitWidth) {
8175 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8176 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8177 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8181 RHS = Op0.getOperand(1);
8183 } else if (Op1.getOpcode() == ISD::Constant) {
8184 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8185 uint64_t AndRHSVal = AndRHS->getZExtValue();
8186 SDValue AndLHS = Op0;
8188 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8189 LHS = AndLHS.getOperand(0);
8190 RHS = AndLHS.getOperand(1);
8193 // Use BT if the immediate can't be encoded in a TEST instruction.
8194 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8196 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8200 if (LHS.getNode()) {
8201 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8202 // instruction. Since the shift amount is in-range-or-undefined, we know
8203 // that doing a bittest on the i32 value is ok. We extend to i32 because
8204 // the encoding for the i16 version is larger than the i32 version.
8205 // Also promote i16 to i32 for performance / code size reason.
8206 if (LHS.getValueType() == MVT::i8 ||
8207 LHS.getValueType() == MVT::i16)
8208 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8210 // If the operand types disagree, extend the shift amount to match. Since
8211 // BT ignores high bits (like shifts) we can use anyextend.
8212 if (LHS.getValueType() != RHS.getValueType())
8213 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8215 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8216 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8217 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8218 DAG.getConstant(Cond, MVT::i8), BT);
8224 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8226 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8228 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8229 SDValue Op0 = Op.getOperand(0);
8230 SDValue Op1 = Op.getOperand(1);
8231 DebugLoc dl = Op.getDebugLoc();
8232 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8234 // Optimize to BT if possible.
8235 // Lower (X & (1 << N)) == 0 to BT(X, N).
8236 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8237 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8238 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8239 Op1.getOpcode() == ISD::Constant &&
8240 cast<ConstantSDNode>(Op1)->isNullValue() &&
8241 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8242 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8243 if (NewSetCC.getNode())
8247 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8249 if (Op1.getOpcode() == ISD::Constant &&
8250 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8251 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8252 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8254 // If the input is a setcc, then reuse the input setcc or use a new one with
8255 // the inverted condition.
8256 if (Op0.getOpcode() == X86ISD::SETCC) {
8257 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8258 bool Invert = (CC == ISD::SETNE) ^
8259 cast<ConstantSDNode>(Op1)->isNullValue();
8260 if (!Invert) return Op0;
8262 CCode = X86::GetOppositeBranchCondition(CCode);
8263 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8264 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8268 bool isFP = Op1.getValueType().isFloatingPoint();
8269 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8270 if (X86CC == X86::COND_INVALID)
8273 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8274 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8275 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8278 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8279 // ones, and then concatenate the result back.
8280 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8281 EVT VT = Op.getValueType();
8283 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8284 "Unsupported value type for operation");
8286 int NumElems = VT.getVectorNumElements();
8287 DebugLoc dl = Op.getDebugLoc();
8288 SDValue CC = Op.getOperand(2);
8289 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8290 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8292 // Extract the LHS vectors
8293 SDValue LHS = Op.getOperand(0);
8294 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8295 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8297 // Extract the RHS vectors
8298 SDValue RHS = Op.getOperand(1);
8299 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8300 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8302 // Issue the operation on the smaller types and concatenate the result back
8303 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8304 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8305 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8306 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8307 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8311 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8313 SDValue Op0 = Op.getOperand(0);
8314 SDValue Op1 = Op.getOperand(1);
8315 SDValue CC = Op.getOperand(2);
8316 EVT VT = Op.getValueType();
8317 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8318 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8319 DebugLoc dl = Op.getDebugLoc();
8323 EVT EltVT = Op0.getValueType().getVectorElementType();
8324 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8328 // SSE Condition code mapping:
8337 switch (SetCCOpcode) {
8340 case ISD::SETEQ: SSECC = 0; break;
8342 case ISD::SETGT: Swap = true; // Fallthrough
8344 case ISD::SETOLT: SSECC = 1; break;
8346 case ISD::SETGE: Swap = true; // Fallthrough
8348 case ISD::SETOLE: SSECC = 2; break;
8349 case ISD::SETUO: SSECC = 3; break;
8351 case ISD::SETNE: SSECC = 4; break;
8352 case ISD::SETULE: Swap = true;
8353 case ISD::SETUGE: SSECC = 5; break;
8354 case ISD::SETULT: Swap = true;
8355 case ISD::SETUGT: SSECC = 6; break;
8356 case ISD::SETO: SSECC = 7; break;
8359 std::swap(Op0, Op1);
8361 // In the two special cases we can't handle, emit two comparisons.
8363 if (SetCCOpcode == ISD::SETUEQ) {
8365 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8366 DAG.getConstant(3, MVT::i8));
8367 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8368 DAG.getConstant(0, MVT::i8));
8369 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8370 } else if (SetCCOpcode == ISD::SETONE) {
8372 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8373 DAG.getConstant(7, MVT::i8));
8374 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8375 DAG.getConstant(4, MVT::i8));
8376 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8378 llvm_unreachable("Illegal FP comparison");
8380 // Handle all other FP comparisons here.
8381 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8382 DAG.getConstant(SSECC, MVT::i8));
8385 // Break 256-bit integer vector compare into smaller ones.
8386 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8387 return Lower256IntVSETCC(Op, DAG);
8389 // We are handling one of the integer comparisons here. Since SSE only has
8390 // GT and EQ comparisons for integer, swapping operands and multiple
8391 // operations may be required for some comparisons.
8393 bool Swap = false, Invert = false, FlipSigns = false;
8395 switch (SetCCOpcode) {
8397 case ISD::SETNE: Invert = true;
8398 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8399 case ISD::SETLT: Swap = true;
8400 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8401 case ISD::SETGE: Swap = true;
8402 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8403 case ISD::SETULT: Swap = true;
8404 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8405 case ISD::SETUGE: Swap = true;
8406 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8409 std::swap(Op0, Op1);
8411 // Check that the operation in question is available (most are plain SSE2,
8412 // but PCMPGTQ and PCMPEQQ have different requirements).
8413 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8415 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8418 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8419 // bits of the inputs before performing those operations.
8421 EVT EltVT = VT.getVectorElementType();
8422 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8424 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8425 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8427 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8428 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8431 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8433 // If the logical-not of the result is required, perform that now.
8435 Result = DAG.getNOT(dl, Result, VT);
8440 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8441 static bool isX86LogicalCmp(SDValue Op) {
8442 unsigned Opc = Op.getNode()->getOpcode();
8443 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8445 if (Op.getResNo() == 1 &&
8446 (Opc == X86ISD::ADD ||
8447 Opc == X86ISD::SUB ||
8448 Opc == X86ISD::ADC ||
8449 Opc == X86ISD::SBB ||
8450 Opc == X86ISD::SMUL ||
8451 Opc == X86ISD::UMUL ||
8452 Opc == X86ISD::INC ||
8453 Opc == X86ISD::DEC ||
8454 Opc == X86ISD::OR ||
8455 Opc == X86ISD::XOR ||
8456 Opc == X86ISD::AND))
8459 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8465 static bool isZero(SDValue V) {
8466 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8467 return C && C->isNullValue();
8470 static bool isAllOnes(SDValue V) {
8471 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8472 return C && C->isAllOnesValue();
8475 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8476 bool addTest = true;
8477 SDValue Cond = Op.getOperand(0);
8478 SDValue Op1 = Op.getOperand(1);
8479 SDValue Op2 = Op.getOperand(2);
8480 DebugLoc DL = Op.getDebugLoc();
8483 if (Cond.getOpcode() == ISD::SETCC) {
8484 SDValue NewCond = LowerSETCC(Cond, DAG);
8485 if (NewCond.getNode())
8489 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8490 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8491 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8492 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8493 if (Cond.getOpcode() == X86ISD::SETCC &&
8494 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8495 isZero(Cond.getOperand(1).getOperand(1))) {
8496 SDValue Cmp = Cond.getOperand(1);
8498 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8500 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8501 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8502 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8504 SDValue CmpOp0 = Cmp.getOperand(0);
8505 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8506 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8508 SDValue Res = // Res = 0 or -1.
8509 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8510 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8512 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8513 Res = DAG.getNOT(DL, Res, Res.getValueType());
8515 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8516 if (N2C == 0 || !N2C->isNullValue())
8517 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8522 // Look past (and (setcc_carry (cmp ...)), 1).
8523 if (Cond.getOpcode() == ISD::AND &&
8524 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8525 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8526 if (C && C->getAPIntValue() == 1)
8527 Cond = Cond.getOperand(0);
8530 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8531 // setting operand in place of the X86ISD::SETCC.
8532 unsigned CondOpcode = Cond.getOpcode();
8533 if (CondOpcode == X86ISD::SETCC ||
8534 CondOpcode == X86ISD::SETCC_CARRY) {
8535 CC = Cond.getOperand(0);
8537 SDValue Cmp = Cond.getOperand(1);
8538 unsigned Opc = Cmp.getOpcode();
8539 EVT VT = Op.getValueType();
8541 bool IllegalFPCMov = false;
8542 if (VT.isFloatingPoint() && !VT.isVector() &&
8543 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8544 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8546 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8547 Opc == X86ISD::BT) { // FIXME
8551 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8552 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8553 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8554 Cond.getOperand(0).getValueType() != MVT::i8)) {
8555 SDValue LHS = Cond.getOperand(0);
8556 SDValue RHS = Cond.getOperand(1);
8560 switch (CondOpcode) {
8561 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8562 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8563 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8564 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8565 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8566 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8567 default: llvm_unreachable("unexpected overflowing operator");
8569 if (CondOpcode == ISD::UMULO)
8570 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8573 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8575 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8577 if (CondOpcode == ISD::UMULO)
8578 Cond = X86Op.getValue(2);
8580 Cond = X86Op.getValue(1);
8582 CC = DAG.getConstant(X86Cond, MVT::i8);
8587 // Look pass the truncate.
8588 if (Cond.getOpcode() == ISD::TRUNCATE)
8589 Cond = Cond.getOperand(0);
8591 // We know the result of AND is compared against zero. Try to match
8593 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8594 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8595 if (NewSetCC.getNode()) {
8596 CC = NewSetCC.getOperand(0);
8597 Cond = NewSetCC.getOperand(1);
8604 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8605 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8608 // a < b ? -1 : 0 -> RES = ~setcc_carry
8609 // a < b ? 0 : -1 -> RES = setcc_carry
8610 // a >= b ? -1 : 0 -> RES = setcc_carry
8611 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8612 if (Cond.getOpcode() == X86ISD::CMP) {
8613 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8615 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8616 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8617 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8618 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8619 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8620 return DAG.getNOT(DL, Res, Res.getValueType());
8625 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8626 // condition is true.
8627 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8628 SDValue Ops[] = { Op2, Op1, CC, Cond };
8629 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8632 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8633 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8634 // from the AND / OR.
8635 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8636 Opc = Op.getOpcode();
8637 if (Opc != ISD::OR && Opc != ISD::AND)
8639 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8640 Op.getOperand(0).hasOneUse() &&
8641 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8642 Op.getOperand(1).hasOneUse());
8645 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8646 // 1 and that the SETCC node has a single use.
8647 static bool isXor1OfSetCC(SDValue Op) {
8648 if (Op.getOpcode() != ISD::XOR)
8650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8651 if (N1C && N1C->getAPIntValue() == 1) {
8652 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8653 Op.getOperand(0).hasOneUse();
8658 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8659 bool addTest = true;
8660 SDValue Chain = Op.getOperand(0);
8661 SDValue Cond = Op.getOperand(1);
8662 SDValue Dest = Op.getOperand(2);
8663 DebugLoc dl = Op.getDebugLoc();
8665 bool Inverted = false;
8667 if (Cond.getOpcode() == ISD::SETCC) {
8668 // Check for setcc([su]{add,sub,mul}o == 0).
8669 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8670 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8671 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8672 Cond.getOperand(0).getResNo() == 1 &&
8673 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8674 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8675 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8676 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8677 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8678 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8680 Cond = Cond.getOperand(0);
8682 SDValue NewCond = LowerSETCC(Cond, DAG);
8683 if (NewCond.getNode())
8688 // FIXME: LowerXALUO doesn't handle these!!
8689 else if (Cond.getOpcode() == X86ISD::ADD ||
8690 Cond.getOpcode() == X86ISD::SUB ||
8691 Cond.getOpcode() == X86ISD::SMUL ||
8692 Cond.getOpcode() == X86ISD::UMUL)
8693 Cond = LowerXALUO(Cond, DAG);
8696 // Look pass (and (setcc_carry (cmp ...)), 1).
8697 if (Cond.getOpcode() == ISD::AND &&
8698 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8699 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8700 if (C && C->getAPIntValue() == 1)
8701 Cond = Cond.getOperand(0);
8704 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8705 // setting operand in place of the X86ISD::SETCC.
8706 unsigned CondOpcode = Cond.getOpcode();
8707 if (CondOpcode == X86ISD::SETCC ||
8708 CondOpcode == X86ISD::SETCC_CARRY) {
8709 CC = Cond.getOperand(0);
8711 SDValue Cmp = Cond.getOperand(1);
8712 unsigned Opc = Cmp.getOpcode();
8713 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8714 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8718 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8722 // These can only come from an arithmetic instruction with overflow,
8723 // e.g. SADDO, UADDO.
8724 Cond = Cond.getNode()->getOperand(1);
8730 CondOpcode = Cond.getOpcode();
8731 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8732 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8733 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8734 Cond.getOperand(0).getValueType() != MVT::i8)) {
8735 SDValue LHS = Cond.getOperand(0);
8736 SDValue RHS = Cond.getOperand(1);
8740 switch (CondOpcode) {
8741 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8742 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8743 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8744 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8745 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8746 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8747 default: llvm_unreachable("unexpected overflowing operator");
8750 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8751 if (CondOpcode == ISD::UMULO)
8752 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8755 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8757 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8759 if (CondOpcode == ISD::UMULO)
8760 Cond = X86Op.getValue(2);
8762 Cond = X86Op.getValue(1);
8764 CC = DAG.getConstant(X86Cond, MVT::i8);
8768 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8769 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8770 if (CondOpc == ISD::OR) {
8771 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8772 // two branches instead of an explicit OR instruction with a
8774 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8775 isX86LogicalCmp(Cmp)) {
8776 CC = Cond.getOperand(0).getOperand(0);
8777 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8778 Chain, Dest, CC, Cmp);
8779 CC = Cond.getOperand(1).getOperand(0);
8783 } else { // ISD::AND
8784 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8785 // two branches instead of an explicit AND instruction with a
8786 // separate test. However, we only do this if this block doesn't
8787 // have a fall-through edge, because this requires an explicit
8788 // jmp when the condition is false.
8789 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8790 isX86LogicalCmp(Cmp) &&
8791 Op.getNode()->hasOneUse()) {
8792 X86::CondCode CCode =
8793 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8794 CCode = X86::GetOppositeBranchCondition(CCode);
8795 CC = DAG.getConstant(CCode, MVT::i8);
8796 SDNode *User = *Op.getNode()->use_begin();
8797 // Look for an unconditional branch following this conditional branch.
8798 // We need this because we need to reverse the successors in order
8799 // to implement FCMP_OEQ.
8800 if (User->getOpcode() == ISD::BR) {
8801 SDValue FalseBB = User->getOperand(1);
8803 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8804 assert(NewBR == User);
8808 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8809 Chain, Dest, CC, Cmp);
8810 X86::CondCode CCode =
8811 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8812 CCode = X86::GetOppositeBranchCondition(CCode);
8813 CC = DAG.getConstant(CCode, MVT::i8);
8819 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8820 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8821 // It should be transformed during dag combiner except when the condition
8822 // is set by a arithmetics with overflow node.
8823 X86::CondCode CCode =
8824 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8825 CCode = X86::GetOppositeBranchCondition(CCode);
8826 CC = DAG.getConstant(CCode, MVT::i8);
8827 Cond = Cond.getOperand(0).getOperand(1);
8829 } else if (Cond.getOpcode() == ISD::SETCC &&
8830 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8831 // For FCMP_OEQ, we can emit
8832 // two branches instead of an explicit AND instruction with a
8833 // separate test. However, we only do this if this block doesn't
8834 // have a fall-through edge, because this requires an explicit
8835 // jmp when the condition is false.
8836 if (Op.getNode()->hasOneUse()) {
8837 SDNode *User = *Op.getNode()->use_begin();
8838 // Look for an unconditional branch following this conditional branch.
8839 // We need this because we need to reverse the successors in order
8840 // to implement FCMP_OEQ.
8841 if (User->getOpcode() == ISD::BR) {
8842 SDValue FalseBB = User->getOperand(1);
8844 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8845 assert(NewBR == User);
8849 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8850 Cond.getOperand(0), Cond.getOperand(1));
8851 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8852 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8853 Chain, Dest, CC, Cmp);
8854 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8859 } else if (Cond.getOpcode() == ISD::SETCC &&
8860 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8861 // For FCMP_UNE, we can emit
8862 // two branches instead of an explicit AND instruction with a
8863 // separate test. However, we only do this if this block doesn't
8864 // have a fall-through edge, because this requires an explicit
8865 // jmp when the condition is false.
8866 if (Op.getNode()->hasOneUse()) {
8867 SDNode *User = *Op.getNode()->use_begin();
8868 // Look for an unconditional branch following this conditional branch.
8869 // We need this because we need to reverse the successors in order
8870 // to implement FCMP_UNE.
8871 if (User->getOpcode() == ISD::BR) {
8872 SDValue FalseBB = User->getOperand(1);
8874 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8875 assert(NewBR == User);
8878 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8879 Cond.getOperand(0), Cond.getOperand(1));
8880 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8881 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8882 Chain, Dest, CC, Cmp);
8883 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8893 // Look pass the truncate.
8894 if (Cond.getOpcode() == ISD::TRUNCATE)
8895 Cond = Cond.getOperand(0);
8897 // We know the result of AND is compared against zero. Try to match
8899 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8900 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8901 if (NewSetCC.getNode()) {
8902 CC = NewSetCC.getOperand(0);
8903 Cond = NewSetCC.getOperand(1);
8910 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8911 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8913 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8914 Chain, Dest, CC, Cond);
8918 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8919 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8920 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8921 // that the guard pages used by the OS virtual memory manager are allocated in
8922 // correct sequence.
8924 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8925 SelectionDAG &DAG) const {
8926 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8927 getTargetMachine().Options.EnableSegmentedStacks) &&
8928 "This should be used only on Windows targets or when segmented stacks "
8930 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8931 DebugLoc dl = Op.getDebugLoc();
8934 SDValue Chain = Op.getOperand(0);
8935 SDValue Size = Op.getOperand(1);
8936 // FIXME: Ensure alignment here
8938 bool Is64Bit = Subtarget->is64Bit();
8939 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8941 if (getTargetMachine().Options.EnableSegmentedStacks) {
8942 MachineFunction &MF = DAG.getMachineFunction();
8943 MachineRegisterInfo &MRI = MF.getRegInfo();
8946 // The 64 bit implementation of segmented stacks needs to clobber both r10
8947 // r11. This makes it impossible to use it along with nested parameters.
8948 const Function *F = MF.getFunction();
8950 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8952 if (I->hasNestAttr())
8953 report_fatal_error("Cannot use segmented stacks with functions that "
8954 "have nested arguments.");
8957 const TargetRegisterClass *AddrRegClass =
8958 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8959 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8960 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8961 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8962 DAG.getRegister(Vreg, SPTy));
8963 SDValue Ops1[2] = { Value, Chain };
8964 return DAG.getMergeValues(Ops1, 2, dl);
8967 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8969 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8970 Flag = Chain.getValue(1);
8971 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8973 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8974 Flag = Chain.getValue(1);
8976 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8978 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8979 return DAG.getMergeValues(Ops1, 2, dl);
8983 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8984 MachineFunction &MF = DAG.getMachineFunction();
8985 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8987 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8988 DebugLoc DL = Op.getDebugLoc();
8990 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8991 // vastart just stores the address of the VarArgsFrameIndex slot into the
8992 // memory location argument.
8993 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8995 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8996 MachinePointerInfo(SV), false, false, 0);
9000 // gp_offset (0 - 6 * 8)
9001 // fp_offset (48 - 48 + 8 * 16)
9002 // overflow_arg_area (point to parameters coming in memory).
9004 SmallVector<SDValue, 8> MemOps;
9005 SDValue FIN = Op.getOperand(1);
9007 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9008 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9010 FIN, MachinePointerInfo(SV), false, false, 0);
9011 MemOps.push_back(Store);
9014 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9015 FIN, DAG.getIntPtrConstant(4));
9016 Store = DAG.getStore(Op.getOperand(0), DL,
9017 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9019 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9020 MemOps.push_back(Store);
9022 // Store ptr to overflow_arg_area
9023 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9024 FIN, DAG.getIntPtrConstant(4));
9025 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9027 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9028 MachinePointerInfo(SV, 8),
9030 MemOps.push_back(Store);
9032 // Store ptr to reg_save_area.
9033 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9034 FIN, DAG.getIntPtrConstant(8));
9035 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9037 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9038 MachinePointerInfo(SV, 16), false, false, 0);
9039 MemOps.push_back(Store);
9040 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9041 &MemOps[0], MemOps.size());
9044 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9045 assert(Subtarget->is64Bit() &&
9046 "LowerVAARG only handles 64-bit va_arg!");
9047 assert((Subtarget->isTargetLinux() ||
9048 Subtarget->isTargetDarwin()) &&
9049 "Unhandled target in LowerVAARG");
9050 assert(Op.getNode()->getNumOperands() == 4);
9051 SDValue Chain = Op.getOperand(0);
9052 SDValue SrcPtr = Op.getOperand(1);
9053 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9054 unsigned Align = Op.getConstantOperandVal(3);
9055 DebugLoc dl = Op.getDebugLoc();
9057 EVT ArgVT = Op.getNode()->getValueType(0);
9058 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9059 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9062 // Decide which area this value should be read from.
9063 // TODO: Implement the AMD64 ABI in its entirety. This simple
9064 // selection mechanism works only for the basic types.
9065 if (ArgVT == MVT::f80) {
9066 llvm_unreachable("va_arg for f80 not yet implemented");
9067 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9068 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9069 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9070 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9072 llvm_unreachable("Unhandled argument type in LowerVAARG");
9076 // Sanity Check: Make sure using fp_offset makes sense.
9077 assert(!getTargetMachine().Options.UseSoftFloat &&
9078 !(DAG.getMachineFunction()
9079 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9080 Subtarget->hasSSE1());
9083 // Insert VAARG_64 node into the DAG
9084 // VAARG_64 returns two values: Variable Argument Address, Chain
9085 SmallVector<SDValue, 11> InstOps;
9086 InstOps.push_back(Chain);
9087 InstOps.push_back(SrcPtr);
9088 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9089 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9090 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9091 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9092 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9093 VTs, &InstOps[0], InstOps.size(),
9095 MachinePointerInfo(SV),
9100 Chain = VAARG.getValue(1);
9102 // Load the next argument and return it
9103 return DAG.getLoad(ArgVT, dl,
9106 MachinePointerInfo(),
9107 false, false, false, 0);
9110 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9111 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9112 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9113 SDValue Chain = Op.getOperand(0);
9114 SDValue DstPtr = Op.getOperand(1);
9115 SDValue SrcPtr = Op.getOperand(2);
9116 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9117 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9118 DebugLoc DL = Op.getDebugLoc();
9120 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9121 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9123 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9126 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9127 // may or may not be a constant. Takes immediate version of shift as input.
9128 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9129 SDValue SrcOp, SDValue ShAmt,
9130 SelectionDAG &DAG) {
9131 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9133 if (isa<ConstantSDNode>(ShAmt)) {
9135 default: llvm_unreachable("Unknown target vector shift node");
9139 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9143 // Change opcode to non-immediate version
9145 default: llvm_unreachable("Unknown target vector shift node");
9146 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9147 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9148 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9151 // Need to build a vector containing shift amount
9152 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9155 ShOps[1] = DAG.getConstant(0, MVT::i32);
9156 ShOps[2] = DAG.getUNDEF(MVT::i32);
9157 ShOps[3] = DAG.getUNDEF(MVT::i32);
9158 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9159 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9160 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9164 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9165 DebugLoc dl = Op.getDebugLoc();
9166 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9168 default: return SDValue(); // Don't custom lower most intrinsics.
9169 // Comparison intrinsics.
9170 case Intrinsic::x86_sse_comieq_ss:
9171 case Intrinsic::x86_sse_comilt_ss:
9172 case Intrinsic::x86_sse_comile_ss:
9173 case Intrinsic::x86_sse_comigt_ss:
9174 case Intrinsic::x86_sse_comige_ss:
9175 case Intrinsic::x86_sse_comineq_ss:
9176 case Intrinsic::x86_sse_ucomieq_ss:
9177 case Intrinsic::x86_sse_ucomilt_ss:
9178 case Intrinsic::x86_sse_ucomile_ss:
9179 case Intrinsic::x86_sse_ucomigt_ss:
9180 case Intrinsic::x86_sse_ucomige_ss:
9181 case Intrinsic::x86_sse_ucomineq_ss:
9182 case Intrinsic::x86_sse2_comieq_sd:
9183 case Intrinsic::x86_sse2_comilt_sd:
9184 case Intrinsic::x86_sse2_comile_sd:
9185 case Intrinsic::x86_sse2_comigt_sd:
9186 case Intrinsic::x86_sse2_comige_sd:
9187 case Intrinsic::x86_sse2_comineq_sd:
9188 case Intrinsic::x86_sse2_ucomieq_sd:
9189 case Intrinsic::x86_sse2_ucomilt_sd:
9190 case Intrinsic::x86_sse2_ucomile_sd:
9191 case Intrinsic::x86_sse2_ucomigt_sd:
9192 case Intrinsic::x86_sse2_ucomige_sd:
9193 case Intrinsic::x86_sse2_ucomineq_sd: {
9195 ISD::CondCode CC = ISD::SETCC_INVALID;
9197 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9198 case Intrinsic::x86_sse_comieq_ss:
9199 case Intrinsic::x86_sse2_comieq_sd:
9203 case Intrinsic::x86_sse_comilt_ss:
9204 case Intrinsic::x86_sse2_comilt_sd:
9208 case Intrinsic::x86_sse_comile_ss:
9209 case Intrinsic::x86_sse2_comile_sd:
9213 case Intrinsic::x86_sse_comigt_ss:
9214 case Intrinsic::x86_sse2_comigt_sd:
9218 case Intrinsic::x86_sse_comige_ss:
9219 case Intrinsic::x86_sse2_comige_sd:
9223 case Intrinsic::x86_sse_comineq_ss:
9224 case Intrinsic::x86_sse2_comineq_sd:
9228 case Intrinsic::x86_sse_ucomieq_ss:
9229 case Intrinsic::x86_sse2_ucomieq_sd:
9230 Opc = X86ISD::UCOMI;
9233 case Intrinsic::x86_sse_ucomilt_ss:
9234 case Intrinsic::x86_sse2_ucomilt_sd:
9235 Opc = X86ISD::UCOMI;
9238 case Intrinsic::x86_sse_ucomile_ss:
9239 case Intrinsic::x86_sse2_ucomile_sd:
9240 Opc = X86ISD::UCOMI;
9243 case Intrinsic::x86_sse_ucomigt_ss:
9244 case Intrinsic::x86_sse2_ucomigt_sd:
9245 Opc = X86ISD::UCOMI;
9248 case Intrinsic::x86_sse_ucomige_ss:
9249 case Intrinsic::x86_sse2_ucomige_sd:
9250 Opc = X86ISD::UCOMI;
9253 case Intrinsic::x86_sse_ucomineq_ss:
9254 case Intrinsic::x86_sse2_ucomineq_sd:
9255 Opc = X86ISD::UCOMI;
9260 SDValue LHS = Op.getOperand(1);
9261 SDValue RHS = Op.getOperand(2);
9262 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9263 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9264 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9265 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9266 DAG.getConstant(X86CC, MVT::i8), Cond);
9267 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9269 // XOP comparison intrinsics
9270 case Intrinsic::x86_xop_vpcomltb:
9271 case Intrinsic::x86_xop_vpcomltw:
9272 case Intrinsic::x86_xop_vpcomltd:
9273 case Intrinsic::x86_xop_vpcomltq:
9274 case Intrinsic::x86_xop_vpcomltub:
9275 case Intrinsic::x86_xop_vpcomltuw:
9276 case Intrinsic::x86_xop_vpcomltud:
9277 case Intrinsic::x86_xop_vpcomltuq:
9278 case Intrinsic::x86_xop_vpcomleb:
9279 case Intrinsic::x86_xop_vpcomlew:
9280 case Intrinsic::x86_xop_vpcomled:
9281 case Intrinsic::x86_xop_vpcomleq:
9282 case Intrinsic::x86_xop_vpcomleub:
9283 case Intrinsic::x86_xop_vpcomleuw:
9284 case Intrinsic::x86_xop_vpcomleud:
9285 case Intrinsic::x86_xop_vpcomleuq:
9286 case Intrinsic::x86_xop_vpcomgtb:
9287 case Intrinsic::x86_xop_vpcomgtw:
9288 case Intrinsic::x86_xop_vpcomgtd:
9289 case Intrinsic::x86_xop_vpcomgtq:
9290 case Intrinsic::x86_xop_vpcomgtub:
9291 case Intrinsic::x86_xop_vpcomgtuw:
9292 case Intrinsic::x86_xop_vpcomgtud:
9293 case Intrinsic::x86_xop_vpcomgtuq:
9294 case Intrinsic::x86_xop_vpcomgeb:
9295 case Intrinsic::x86_xop_vpcomgew:
9296 case Intrinsic::x86_xop_vpcomged:
9297 case Intrinsic::x86_xop_vpcomgeq:
9298 case Intrinsic::x86_xop_vpcomgeub:
9299 case Intrinsic::x86_xop_vpcomgeuw:
9300 case Intrinsic::x86_xop_vpcomgeud:
9301 case Intrinsic::x86_xop_vpcomgeuq:
9302 case Intrinsic::x86_xop_vpcomeqb:
9303 case Intrinsic::x86_xop_vpcomeqw:
9304 case Intrinsic::x86_xop_vpcomeqd:
9305 case Intrinsic::x86_xop_vpcomeqq:
9306 case Intrinsic::x86_xop_vpcomequb:
9307 case Intrinsic::x86_xop_vpcomequw:
9308 case Intrinsic::x86_xop_vpcomequd:
9309 case Intrinsic::x86_xop_vpcomequq:
9310 case Intrinsic::x86_xop_vpcomneb:
9311 case Intrinsic::x86_xop_vpcomnew:
9312 case Intrinsic::x86_xop_vpcomned:
9313 case Intrinsic::x86_xop_vpcomneq:
9314 case Intrinsic::x86_xop_vpcomneub:
9315 case Intrinsic::x86_xop_vpcomneuw:
9316 case Intrinsic::x86_xop_vpcomneud:
9317 case Intrinsic::x86_xop_vpcomneuq:
9318 case Intrinsic::x86_xop_vpcomfalseb:
9319 case Intrinsic::x86_xop_vpcomfalsew:
9320 case Intrinsic::x86_xop_vpcomfalsed:
9321 case Intrinsic::x86_xop_vpcomfalseq:
9322 case Intrinsic::x86_xop_vpcomfalseub:
9323 case Intrinsic::x86_xop_vpcomfalseuw:
9324 case Intrinsic::x86_xop_vpcomfalseud:
9325 case Intrinsic::x86_xop_vpcomfalseuq:
9326 case Intrinsic::x86_xop_vpcomtrueb:
9327 case Intrinsic::x86_xop_vpcomtruew:
9328 case Intrinsic::x86_xop_vpcomtrued:
9329 case Intrinsic::x86_xop_vpcomtrueq:
9330 case Intrinsic::x86_xop_vpcomtrueub:
9331 case Intrinsic::x86_xop_vpcomtrueuw:
9332 case Intrinsic::x86_xop_vpcomtrueud:
9333 case Intrinsic::x86_xop_vpcomtrueuq: {
9338 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9339 case Intrinsic::x86_xop_vpcomltb:
9340 case Intrinsic::x86_xop_vpcomltw:
9341 case Intrinsic::x86_xop_vpcomltd:
9342 case Intrinsic::x86_xop_vpcomltq:
9344 Opc = X86ISD::VPCOM;
9346 case Intrinsic::x86_xop_vpcomltub:
9347 case Intrinsic::x86_xop_vpcomltuw:
9348 case Intrinsic::x86_xop_vpcomltud:
9349 case Intrinsic::x86_xop_vpcomltuq:
9351 Opc = X86ISD::VPCOMU;
9353 case Intrinsic::x86_xop_vpcomleb:
9354 case Intrinsic::x86_xop_vpcomlew:
9355 case Intrinsic::x86_xop_vpcomled:
9356 case Intrinsic::x86_xop_vpcomleq:
9358 Opc = X86ISD::VPCOM;
9360 case Intrinsic::x86_xop_vpcomleub:
9361 case Intrinsic::x86_xop_vpcomleuw:
9362 case Intrinsic::x86_xop_vpcomleud:
9363 case Intrinsic::x86_xop_vpcomleuq:
9365 Opc = X86ISD::VPCOMU;
9367 case Intrinsic::x86_xop_vpcomgtb:
9368 case Intrinsic::x86_xop_vpcomgtw:
9369 case Intrinsic::x86_xop_vpcomgtd:
9370 case Intrinsic::x86_xop_vpcomgtq:
9372 Opc = X86ISD::VPCOM;
9374 case Intrinsic::x86_xop_vpcomgtub:
9375 case Intrinsic::x86_xop_vpcomgtuw:
9376 case Intrinsic::x86_xop_vpcomgtud:
9377 case Intrinsic::x86_xop_vpcomgtuq:
9379 Opc = X86ISD::VPCOMU;
9381 case Intrinsic::x86_xop_vpcomgeb:
9382 case Intrinsic::x86_xop_vpcomgew:
9383 case Intrinsic::x86_xop_vpcomged:
9384 case Intrinsic::x86_xop_vpcomgeq:
9386 Opc = X86ISD::VPCOM;
9388 case Intrinsic::x86_xop_vpcomgeub:
9389 case Intrinsic::x86_xop_vpcomgeuw:
9390 case Intrinsic::x86_xop_vpcomgeud:
9391 case Intrinsic::x86_xop_vpcomgeuq:
9393 Opc = X86ISD::VPCOMU;
9395 case Intrinsic::x86_xop_vpcomeqb:
9396 case Intrinsic::x86_xop_vpcomeqw:
9397 case Intrinsic::x86_xop_vpcomeqd:
9398 case Intrinsic::x86_xop_vpcomeqq:
9400 Opc = X86ISD::VPCOM;
9402 case Intrinsic::x86_xop_vpcomequb:
9403 case Intrinsic::x86_xop_vpcomequw:
9404 case Intrinsic::x86_xop_vpcomequd:
9405 case Intrinsic::x86_xop_vpcomequq:
9407 Opc = X86ISD::VPCOMU;
9409 case Intrinsic::x86_xop_vpcomneb:
9410 case Intrinsic::x86_xop_vpcomnew:
9411 case Intrinsic::x86_xop_vpcomned:
9412 case Intrinsic::x86_xop_vpcomneq:
9414 Opc = X86ISD::VPCOM;
9416 case Intrinsic::x86_xop_vpcomneub:
9417 case Intrinsic::x86_xop_vpcomneuw:
9418 case Intrinsic::x86_xop_vpcomneud:
9419 case Intrinsic::x86_xop_vpcomneuq:
9421 Opc = X86ISD::VPCOMU;
9423 case Intrinsic::x86_xop_vpcomfalseb:
9424 case Intrinsic::x86_xop_vpcomfalsew:
9425 case Intrinsic::x86_xop_vpcomfalsed:
9426 case Intrinsic::x86_xop_vpcomfalseq:
9428 Opc = X86ISD::VPCOM;
9430 case Intrinsic::x86_xop_vpcomfalseub:
9431 case Intrinsic::x86_xop_vpcomfalseuw:
9432 case Intrinsic::x86_xop_vpcomfalseud:
9433 case Intrinsic::x86_xop_vpcomfalseuq:
9435 Opc = X86ISD::VPCOMU;
9437 case Intrinsic::x86_xop_vpcomtrueb:
9438 case Intrinsic::x86_xop_vpcomtruew:
9439 case Intrinsic::x86_xop_vpcomtrued:
9440 case Intrinsic::x86_xop_vpcomtrueq:
9442 Opc = X86ISD::VPCOM;
9444 case Intrinsic::x86_xop_vpcomtrueub:
9445 case Intrinsic::x86_xop_vpcomtrueuw:
9446 case Intrinsic::x86_xop_vpcomtrueud:
9447 case Intrinsic::x86_xop_vpcomtrueuq:
9449 Opc = X86ISD::VPCOMU;
9453 SDValue LHS = Op.getOperand(1);
9454 SDValue RHS = Op.getOperand(2);
9455 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9456 DAG.getConstant(CC, MVT::i8));
9459 // Arithmetic intrinsics.
9460 case Intrinsic::x86_sse3_hadd_ps:
9461 case Intrinsic::x86_sse3_hadd_pd:
9462 case Intrinsic::x86_avx_hadd_ps_256:
9463 case Intrinsic::x86_avx_hadd_pd_256:
9464 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9465 Op.getOperand(1), Op.getOperand(2));
9466 case Intrinsic::x86_sse3_hsub_ps:
9467 case Intrinsic::x86_sse3_hsub_pd:
9468 case Intrinsic::x86_avx_hsub_ps_256:
9469 case Intrinsic::x86_avx_hsub_pd_256:
9470 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9471 Op.getOperand(1), Op.getOperand(2));
9472 case Intrinsic::x86_ssse3_phadd_w_128:
9473 case Intrinsic::x86_ssse3_phadd_d_128:
9474 case Intrinsic::x86_avx2_phadd_w:
9475 case Intrinsic::x86_avx2_phadd_d:
9476 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9477 Op.getOperand(1), Op.getOperand(2));
9478 case Intrinsic::x86_ssse3_phsub_w_128:
9479 case Intrinsic::x86_ssse3_phsub_d_128:
9480 case Intrinsic::x86_avx2_phsub_w:
9481 case Intrinsic::x86_avx2_phsub_d:
9482 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9483 Op.getOperand(1), Op.getOperand(2));
9484 case Intrinsic::x86_avx2_psllv_d:
9485 case Intrinsic::x86_avx2_psllv_q:
9486 case Intrinsic::x86_avx2_psllv_d_256:
9487 case Intrinsic::x86_avx2_psllv_q_256:
9488 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9489 Op.getOperand(1), Op.getOperand(2));
9490 case Intrinsic::x86_avx2_psrlv_d:
9491 case Intrinsic::x86_avx2_psrlv_q:
9492 case Intrinsic::x86_avx2_psrlv_d_256:
9493 case Intrinsic::x86_avx2_psrlv_q_256:
9494 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9495 Op.getOperand(1), Op.getOperand(2));
9496 case Intrinsic::x86_avx2_psrav_d:
9497 case Intrinsic::x86_avx2_psrav_d_256:
9498 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9499 Op.getOperand(1), Op.getOperand(2));
9500 case Intrinsic::x86_ssse3_pshuf_b_128:
9501 case Intrinsic::x86_avx2_pshuf_b:
9502 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9503 Op.getOperand(1), Op.getOperand(2));
9504 case Intrinsic::x86_ssse3_psign_b_128:
9505 case Intrinsic::x86_ssse3_psign_w_128:
9506 case Intrinsic::x86_ssse3_psign_d_128:
9507 case Intrinsic::x86_avx2_psign_b:
9508 case Intrinsic::x86_avx2_psign_w:
9509 case Intrinsic::x86_avx2_psign_d:
9510 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9511 Op.getOperand(1), Op.getOperand(2));
9512 case Intrinsic::x86_sse41_insertps:
9513 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9514 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9515 case Intrinsic::x86_avx_vperm2f128_ps_256:
9516 case Intrinsic::x86_avx_vperm2f128_pd_256:
9517 case Intrinsic::x86_avx_vperm2f128_si_256:
9518 case Intrinsic::x86_avx2_vperm2i128:
9519 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9520 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9522 // ptest and testp intrinsics. The intrinsic these come from are designed to
9523 // return an integer value, not just an instruction so lower it to the ptest
9524 // or testp pattern and a setcc for the result.
9525 case Intrinsic::x86_sse41_ptestz:
9526 case Intrinsic::x86_sse41_ptestc:
9527 case Intrinsic::x86_sse41_ptestnzc:
9528 case Intrinsic::x86_avx_ptestz_256:
9529 case Intrinsic::x86_avx_ptestc_256:
9530 case Intrinsic::x86_avx_ptestnzc_256:
9531 case Intrinsic::x86_avx_vtestz_ps:
9532 case Intrinsic::x86_avx_vtestc_ps:
9533 case Intrinsic::x86_avx_vtestnzc_ps:
9534 case Intrinsic::x86_avx_vtestz_pd:
9535 case Intrinsic::x86_avx_vtestc_pd:
9536 case Intrinsic::x86_avx_vtestnzc_pd:
9537 case Intrinsic::x86_avx_vtestz_ps_256:
9538 case Intrinsic::x86_avx_vtestc_ps_256:
9539 case Intrinsic::x86_avx_vtestnzc_ps_256:
9540 case Intrinsic::x86_avx_vtestz_pd_256:
9541 case Intrinsic::x86_avx_vtestc_pd_256:
9542 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9543 bool IsTestPacked = false;
9546 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9547 case Intrinsic::x86_avx_vtestz_ps:
9548 case Intrinsic::x86_avx_vtestz_pd:
9549 case Intrinsic::x86_avx_vtestz_ps_256:
9550 case Intrinsic::x86_avx_vtestz_pd_256:
9551 IsTestPacked = true; // Fallthrough
9552 case Intrinsic::x86_sse41_ptestz:
9553 case Intrinsic::x86_avx_ptestz_256:
9555 X86CC = X86::COND_E;
9557 case Intrinsic::x86_avx_vtestc_ps:
9558 case Intrinsic::x86_avx_vtestc_pd:
9559 case Intrinsic::x86_avx_vtestc_ps_256:
9560 case Intrinsic::x86_avx_vtestc_pd_256:
9561 IsTestPacked = true; // Fallthrough
9562 case Intrinsic::x86_sse41_ptestc:
9563 case Intrinsic::x86_avx_ptestc_256:
9565 X86CC = X86::COND_B;
9567 case Intrinsic::x86_avx_vtestnzc_ps:
9568 case Intrinsic::x86_avx_vtestnzc_pd:
9569 case Intrinsic::x86_avx_vtestnzc_ps_256:
9570 case Intrinsic::x86_avx_vtestnzc_pd_256:
9571 IsTestPacked = true; // Fallthrough
9572 case Intrinsic::x86_sse41_ptestnzc:
9573 case Intrinsic::x86_avx_ptestnzc_256:
9575 X86CC = X86::COND_A;
9579 SDValue LHS = Op.getOperand(1);
9580 SDValue RHS = Op.getOperand(2);
9581 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9582 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9583 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9584 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9585 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9588 // SSE/AVX shift intrinsics
9589 case Intrinsic::x86_sse2_psll_w:
9590 case Intrinsic::x86_sse2_psll_d:
9591 case Intrinsic::x86_sse2_psll_q:
9592 case Intrinsic::x86_avx2_psll_w:
9593 case Intrinsic::x86_avx2_psll_d:
9594 case Intrinsic::x86_avx2_psll_q:
9595 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9596 Op.getOperand(1), Op.getOperand(2));
9597 case Intrinsic::x86_sse2_psrl_w:
9598 case Intrinsic::x86_sse2_psrl_d:
9599 case Intrinsic::x86_sse2_psrl_q:
9600 case Intrinsic::x86_avx2_psrl_w:
9601 case Intrinsic::x86_avx2_psrl_d:
9602 case Intrinsic::x86_avx2_psrl_q:
9603 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9604 Op.getOperand(1), Op.getOperand(2));
9605 case Intrinsic::x86_sse2_psra_w:
9606 case Intrinsic::x86_sse2_psra_d:
9607 case Intrinsic::x86_avx2_psra_w:
9608 case Intrinsic::x86_avx2_psra_d:
9609 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9610 Op.getOperand(1), Op.getOperand(2));
9611 case Intrinsic::x86_sse2_pslli_w:
9612 case Intrinsic::x86_sse2_pslli_d:
9613 case Intrinsic::x86_sse2_pslli_q:
9614 case Intrinsic::x86_avx2_pslli_w:
9615 case Intrinsic::x86_avx2_pslli_d:
9616 case Intrinsic::x86_avx2_pslli_q:
9617 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9618 Op.getOperand(1), Op.getOperand(2), DAG);
9619 case Intrinsic::x86_sse2_psrli_w:
9620 case Intrinsic::x86_sse2_psrli_d:
9621 case Intrinsic::x86_sse2_psrli_q:
9622 case Intrinsic::x86_avx2_psrli_w:
9623 case Intrinsic::x86_avx2_psrli_d:
9624 case Intrinsic::x86_avx2_psrli_q:
9625 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9626 Op.getOperand(1), Op.getOperand(2), DAG);
9627 case Intrinsic::x86_sse2_psrai_w:
9628 case Intrinsic::x86_sse2_psrai_d:
9629 case Intrinsic::x86_avx2_psrai_w:
9630 case Intrinsic::x86_avx2_psrai_d:
9631 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9632 Op.getOperand(1), Op.getOperand(2), DAG);
9633 // Fix vector shift instructions where the last operand is a non-immediate
9635 case Intrinsic::x86_mmx_pslli_w:
9636 case Intrinsic::x86_mmx_pslli_d:
9637 case Intrinsic::x86_mmx_pslli_q:
9638 case Intrinsic::x86_mmx_psrli_w:
9639 case Intrinsic::x86_mmx_psrli_d:
9640 case Intrinsic::x86_mmx_psrli_q:
9641 case Intrinsic::x86_mmx_psrai_w:
9642 case Intrinsic::x86_mmx_psrai_d: {
9643 SDValue ShAmt = Op.getOperand(2);
9644 if (isa<ConstantSDNode>(ShAmt))
9647 unsigned NewIntNo = 0;
9649 case Intrinsic::x86_mmx_pslli_w:
9650 NewIntNo = Intrinsic::x86_mmx_psll_w;
9652 case Intrinsic::x86_mmx_pslli_d:
9653 NewIntNo = Intrinsic::x86_mmx_psll_d;
9655 case Intrinsic::x86_mmx_pslli_q:
9656 NewIntNo = Intrinsic::x86_mmx_psll_q;
9658 case Intrinsic::x86_mmx_psrli_w:
9659 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9661 case Intrinsic::x86_mmx_psrli_d:
9662 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9664 case Intrinsic::x86_mmx_psrli_q:
9665 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9667 case Intrinsic::x86_mmx_psrai_w:
9668 NewIntNo = Intrinsic::x86_mmx_psra_w;
9670 case Intrinsic::x86_mmx_psrai_d:
9671 NewIntNo = Intrinsic::x86_mmx_psra_d;
9673 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9676 // The vector shift intrinsics with scalars uses 32b shift amounts but
9677 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9679 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9680 DAG.getConstant(0, MVT::i32));
9681 // FIXME this must be lowered to get rid of the invalid type.
9683 EVT VT = Op.getValueType();
9684 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9685 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9686 DAG.getConstant(NewIntNo, MVT::i32),
9687 Op.getOperand(1), ShAmt);
9692 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9693 SelectionDAG &DAG) const {
9694 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9695 MFI->setReturnAddressIsTaken(true);
9697 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9698 DebugLoc dl = Op.getDebugLoc();
9701 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9703 DAG.getConstant(TD->getPointerSize(),
9704 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9705 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9706 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9708 MachinePointerInfo(), false, false, false, 0);
9711 // Just load the return address.
9712 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9713 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9714 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9717 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9718 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9719 MFI->setFrameAddressIsTaken(true);
9721 EVT VT = Op.getValueType();
9722 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9723 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9724 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9725 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9727 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9728 MachinePointerInfo(),
9729 false, false, false, 0);
9733 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9734 SelectionDAG &DAG) const {
9735 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9738 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9739 MachineFunction &MF = DAG.getMachineFunction();
9740 SDValue Chain = Op.getOperand(0);
9741 SDValue Offset = Op.getOperand(1);
9742 SDValue Handler = Op.getOperand(2);
9743 DebugLoc dl = Op.getDebugLoc();
9745 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9746 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9748 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9750 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9751 DAG.getIntPtrConstant(TD->getPointerSize()));
9752 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9753 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9755 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9756 MF.getRegInfo().addLiveOut(StoreAddrReg);
9758 return DAG.getNode(X86ISD::EH_RETURN, dl,
9760 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9763 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9764 SelectionDAG &DAG) const {
9765 return Op.getOperand(0);
9768 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9769 SelectionDAG &DAG) const {
9770 SDValue Root = Op.getOperand(0);
9771 SDValue Trmp = Op.getOperand(1); // trampoline
9772 SDValue FPtr = Op.getOperand(2); // nested function
9773 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9774 DebugLoc dl = Op.getDebugLoc();
9776 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9778 if (Subtarget->is64Bit()) {
9779 SDValue OutChains[6];
9781 // Large code-model.
9782 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9783 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9785 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9786 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9788 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9790 // Load the pointer to the nested function into R11.
9791 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9792 SDValue Addr = Trmp;
9793 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9794 Addr, MachinePointerInfo(TrmpAddr),
9797 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9798 DAG.getConstant(2, MVT::i64));
9799 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9800 MachinePointerInfo(TrmpAddr, 2),
9803 // Load the 'nest' parameter value into R10.
9804 // R10 is specified in X86CallingConv.td
9805 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9806 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9807 DAG.getConstant(10, MVT::i64));
9808 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9809 Addr, MachinePointerInfo(TrmpAddr, 10),
9812 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9813 DAG.getConstant(12, MVT::i64));
9814 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9815 MachinePointerInfo(TrmpAddr, 12),
9818 // Jump to the nested function.
9819 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9820 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9821 DAG.getConstant(20, MVT::i64));
9822 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9823 Addr, MachinePointerInfo(TrmpAddr, 20),
9826 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9827 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9828 DAG.getConstant(22, MVT::i64));
9829 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9830 MachinePointerInfo(TrmpAddr, 22),
9833 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9835 const Function *Func =
9836 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9837 CallingConv::ID CC = Func->getCallingConv();
9842 llvm_unreachable("Unsupported calling convention");
9843 case CallingConv::C:
9844 case CallingConv::X86_StdCall: {
9845 // Pass 'nest' parameter in ECX.
9846 // Must be kept in sync with X86CallingConv.td
9849 // Check that ECX wasn't needed by an 'inreg' parameter.
9850 FunctionType *FTy = Func->getFunctionType();
9851 const AttrListPtr &Attrs = Func->getAttributes();
9853 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9854 unsigned InRegCount = 0;
9857 for (FunctionType::param_iterator I = FTy->param_begin(),
9858 E = FTy->param_end(); I != E; ++I, ++Idx)
9859 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9860 // FIXME: should only count parameters that are lowered to integers.
9861 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9863 if (InRegCount > 2) {
9864 report_fatal_error("Nest register in use - reduce number of inreg"
9870 case CallingConv::X86_FastCall:
9871 case CallingConv::X86_ThisCall:
9872 case CallingConv::Fast:
9873 // Pass 'nest' parameter in EAX.
9874 // Must be kept in sync with X86CallingConv.td
9879 SDValue OutChains[4];
9882 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9883 DAG.getConstant(10, MVT::i32));
9884 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9886 // This is storing the opcode for MOV32ri.
9887 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9888 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9889 OutChains[0] = DAG.getStore(Root, dl,
9890 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9891 Trmp, MachinePointerInfo(TrmpAddr),
9894 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9895 DAG.getConstant(1, MVT::i32));
9896 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9897 MachinePointerInfo(TrmpAddr, 1),
9900 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9901 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9902 DAG.getConstant(5, MVT::i32));
9903 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9904 MachinePointerInfo(TrmpAddr, 5),
9907 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9908 DAG.getConstant(6, MVT::i32));
9909 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9910 MachinePointerInfo(TrmpAddr, 6),
9913 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9917 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9918 SelectionDAG &DAG) const {
9920 The rounding mode is in bits 11:10 of FPSR, and has the following
9927 FLT_ROUNDS, on the other hand, expects the following:
9934 To perform the conversion, we do:
9935 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9938 MachineFunction &MF = DAG.getMachineFunction();
9939 const TargetMachine &TM = MF.getTarget();
9940 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9941 unsigned StackAlignment = TFI.getStackAlignment();
9942 EVT VT = Op.getValueType();
9943 DebugLoc DL = Op.getDebugLoc();
9945 // Save FP Control Word to stack slot
9946 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9947 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9950 MachineMemOperand *MMO =
9951 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9952 MachineMemOperand::MOStore, 2, 2);
9954 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9955 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9956 DAG.getVTList(MVT::Other),
9957 Ops, 2, MVT::i16, MMO);
9959 // Load FP Control Word from stack slot
9960 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9961 MachinePointerInfo(), false, false, false, 0);
9963 // Transform as necessary
9965 DAG.getNode(ISD::SRL, DL, MVT::i16,
9966 DAG.getNode(ISD::AND, DL, MVT::i16,
9967 CWD, DAG.getConstant(0x800, MVT::i16)),
9968 DAG.getConstant(11, MVT::i8));
9970 DAG.getNode(ISD::SRL, DL, MVT::i16,
9971 DAG.getNode(ISD::AND, DL, MVT::i16,
9972 CWD, DAG.getConstant(0x400, MVT::i16)),
9973 DAG.getConstant(9, MVT::i8));
9976 DAG.getNode(ISD::AND, DL, MVT::i16,
9977 DAG.getNode(ISD::ADD, DL, MVT::i16,
9978 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9979 DAG.getConstant(1, MVT::i16)),
9980 DAG.getConstant(3, MVT::i16));
9983 return DAG.getNode((VT.getSizeInBits() < 16 ?
9984 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9987 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9988 EVT VT = Op.getValueType();
9990 unsigned NumBits = VT.getSizeInBits();
9991 DebugLoc dl = Op.getDebugLoc();
9993 Op = Op.getOperand(0);
9994 if (VT == MVT::i8) {
9995 // Zero extend to i32 since there is not an i8 bsr.
9997 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10000 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10001 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10002 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10004 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10007 DAG.getConstant(NumBits+NumBits-1, OpVT),
10008 DAG.getConstant(X86::COND_E, MVT::i8),
10011 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10013 // Finally xor with NumBits-1.
10014 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10017 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10021 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10022 SelectionDAG &DAG) const {
10023 EVT VT = Op.getValueType();
10025 unsigned NumBits = VT.getSizeInBits();
10026 DebugLoc dl = Op.getDebugLoc();
10028 Op = Op.getOperand(0);
10029 if (VT == MVT::i8) {
10030 // Zero extend to i32 since there is not an i8 bsr.
10032 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10035 // Issue a bsr (scan bits in reverse).
10036 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10037 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10039 // And xor with NumBits-1.
10040 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10043 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10047 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10048 EVT VT = Op.getValueType();
10049 unsigned NumBits = VT.getSizeInBits();
10050 DebugLoc dl = Op.getDebugLoc();
10051 Op = Op.getOperand(0);
10053 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10054 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10055 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10057 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10060 DAG.getConstant(NumBits, VT),
10061 DAG.getConstant(X86::COND_E, MVT::i8),
10064 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10067 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10068 // ones, and then concatenate the result back.
10069 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10070 EVT VT = Op.getValueType();
10072 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10073 "Unsupported value type for operation");
10075 int NumElems = VT.getVectorNumElements();
10076 DebugLoc dl = Op.getDebugLoc();
10077 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10078 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10080 // Extract the LHS vectors
10081 SDValue LHS = Op.getOperand(0);
10082 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10083 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10085 // Extract the RHS vectors
10086 SDValue RHS = Op.getOperand(1);
10087 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10088 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10090 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10091 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10093 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10094 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10095 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10098 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10099 assert(Op.getValueType().getSizeInBits() == 256 &&
10100 Op.getValueType().isInteger() &&
10101 "Only handle AVX 256-bit vector integer operation");
10102 return Lower256IntArith(Op, DAG);
10105 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10106 assert(Op.getValueType().getSizeInBits() == 256 &&
10107 Op.getValueType().isInteger() &&
10108 "Only handle AVX 256-bit vector integer operation");
10109 return Lower256IntArith(Op, DAG);
10112 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10113 EVT VT = Op.getValueType();
10115 // Decompose 256-bit ops into smaller 128-bit ops.
10116 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10117 return Lower256IntArith(Op, DAG);
10119 DebugLoc dl = Op.getDebugLoc();
10121 SDValue A = Op.getOperand(0);
10122 SDValue B = Op.getOperand(1);
10124 if (VT == MVT::v4i64) {
10125 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
10127 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
10128 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
10129 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
10130 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
10131 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
10133 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
10134 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
10135 // return AloBlo + AloBhi + AhiBlo;
10137 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
10138 DAG.getConstant(32, MVT::i32));
10139 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
10140 DAG.getConstant(32, MVT::i32));
10141 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10142 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10144 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10145 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10147 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10148 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10150 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
10151 DAG.getConstant(32, MVT::i32));
10152 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
10153 DAG.getConstant(32, MVT::i32));
10154 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10155 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10159 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
10161 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
10162 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
10163 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
10164 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
10165 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
10167 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
10168 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
10169 // return AloBlo + AloBhi + AhiBlo;
10171 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
10172 DAG.getConstant(32, MVT::i32));
10173 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
10174 DAG.getConstant(32, MVT::i32));
10175 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10176 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10178 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10179 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10181 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10182 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10184 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
10185 DAG.getConstant(32, MVT::i32));
10186 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
10187 DAG.getConstant(32, MVT::i32));
10188 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10189 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10193 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10195 EVT VT = Op.getValueType();
10196 DebugLoc dl = Op.getDebugLoc();
10197 SDValue R = Op.getOperand(0);
10198 SDValue Amt = Op.getOperand(1);
10199 LLVMContext *Context = DAG.getContext();
10201 if (!Subtarget->hasSSE2())
10204 // Optimize shl/srl/sra with constant shift amount.
10205 if (isSplatVector(Amt.getNode())) {
10206 SDValue SclrAmt = Amt->getOperand(0);
10207 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10208 uint64_t ShiftAmt = C->getZExtValue();
10210 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10211 (Subtarget->hasAVX2() &&
10212 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10213 if (Op.getOpcode() == ISD::SHL)
10214 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10215 DAG.getConstant(ShiftAmt, MVT::i32));
10216 if (Op.getOpcode() == ISD::SRL)
10217 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10218 DAG.getConstant(ShiftAmt, MVT::i32));
10219 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10220 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10221 DAG.getConstant(ShiftAmt, MVT::i32));
10224 if (VT == MVT::v16i8) {
10225 if (Op.getOpcode() == ISD::SHL) {
10226 // Make a large shift.
10227 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10228 DAG.getConstant(ShiftAmt, MVT::i32));
10229 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10230 // Zero out the rightmost bits.
10231 SmallVector<SDValue, 16> V(16,
10232 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10234 return DAG.getNode(ISD::AND, dl, VT, SHL,
10235 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10237 if (Op.getOpcode() == ISD::SRL) {
10238 // Make a large shift.
10239 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10240 DAG.getConstant(ShiftAmt, MVT::i32));
10241 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10242 // Zero out the leftmost bits.
10243 SmallVector<SDValue, 16> V(16,
10244 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10246 return DAG.getNode(ISD::AND, dl, VT, SRL,
10247 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10249 if (Op.getOpcode() == ISD::SRA) {
10250 if (ShiftAmt == 7) {
10251 // R s>> 7 === R s< 0
10252 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true,
10253 /* HasAVX2 */false, DAG, dl);
10254 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10257 // R s>> a === ((R u>> a) ^ m) - m
10258 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10259 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10261 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10262 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10263 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10268 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10269 if (Op.getOpcode() == ISD::SHL) {
10270 // Make a large shift.
10271 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10272 DAG.getConstant(ShiftAmt, MVT::i32));
10273 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10274 // Zero out the rightmost bits.
10275 SmallVector<SDValue, 32> V(32,
10276 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10278 return DAG.getNode(ISD::AND, dl, VT, SHL,
10279 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10281 if (Op.getOpcode() == ISD::SRL) {
10282 // Make a large shift.
10283 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10284 DAG.getConstant(ShiftAmt, MVT::i32));
10285 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10286 // Zero out the leftmost bits.
10287 SmallVector<SDValue, 32> V(32,
10288 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10290 return DAG.getNode(ISD::AND, dl, VT, SRL,
10291 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10293 if (Op.getOpcode() == ISD::SRA) {
10294 if (ShiftAmt == 7) {
10295 // R s>> 7 === R s< 0
10296 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */,
10297 true /* HasAVX2 */, DAG, dl);
10298 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10301 // R s>> a === ((R u>> a) ^ m) - m
10302 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10303 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10305 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10306 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10307 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10314 // Lower SHL with variable shift amount.
10315 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10316 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10317 DAG.getConstant(23, MVT::i32));
10319 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10320 Constant *C = ConstantVector::getSplat(4, CI);
10321 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10322 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10323 MachinePointerInfo::getConstantPool(),
10324 false, false, false, 16);
10326 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10327 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10328 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10329 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10331 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10332 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10335 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10336 DAG.getConstant(5, MVT::i32));
10337 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10339 // Turn 'a' into a mask suitable for VSELECT
10340 SDValue VSelM = DAG.getConstant(0x80, VT);
10341 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10342 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10344 SDValue CM1 = DAG.getConstant(0x0f, VT);
10345 SDValue CM2 = DAG.getConstant(0x3f, VT);
10347 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10348 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10349 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10350 DAG.getConstant(4, MVT::i32), DAG);
10351 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10352 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10355 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10356 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10357 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10359 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10360 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10361 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10362 DAG.getConstant(2, MVT::i32), DAG);
10363 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10364 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10367 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10368 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10369 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10371 // return VSELECT(r, r+r, a);
10372 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10373 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10377 // Decompose 256-bit shifts into smaller 128-bit shifts.
10378 if (VT.getSizeInBits() == 256) {
10379 unsigned NumElems = VT.getVectorNumElements();
10380 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10381 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10383 // Extract the two vectors
10384 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10385 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10388 // Recreate the shift amount vectors
10389 SDValue Amt1, Amt2;
10390 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10391 // Constant shift amount
10392 SmallVector<SDValue, 4> Amt1Csts;
10393 SmallVector<SDValue, 4> Amt2Csts;
10394 for (unsigned i = 0; i != NumElems/2; ++i)
10395 Amt1Csts.push_back(Amt->getOperand(i));
10396 for (unsigned i = NumElems/2; i != NumElems; ++i)
10397 Amt2Csts.push_back(Amt->getOperand(i));
10399 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10400 &Amt1Csts[0], NumElems/2);
10401 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10402 &Amt2Csts[0], NumElems/2);
10404 // Variable shift amount
10405 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10406 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10410 // Issue new vector shifts for the smaller types
10411 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10412 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10414 // Concatenate the result back
10415 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10421 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10422 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10423 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10424 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10425 // has only one use.
10426 SDNode *N = Op.getNode();
10427 SDValue LHS = N->getOperand(0);
10428 SDValue RHS = N->getOperand(1);
10429 unsigned BaseOp = 0;
10431 DebugLoc DL = Op.getDebugLoc();
10432 switch (Op.getOpcode()) {
10433 default: llvm_unreachable("Unknown ovf instruction!");
10435 // A subtract of one will be selected as a INC. Note that INC doesn't
10436 // set CF, so we can't do this for UADDO.
10437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10439 BaseOp = X86ISD::INC;
10440 Cond = X86::COND_O;
10443 BaseOp = X86ISD::ADD;
10444 Cond = X86::COND_O;
10447 BaseOp = X86ISD::ADD;
10448 Cond = X86::COND_B;
10451 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10452 // set CF, so we can't do this for USUBO.
10453 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10455 BaseOp = X86ISD::DEC;
10456 Cond = X86::COND_O;
10459 BaseOp = X86ISD::SUB;
10460 Cond = X86::COND_O;
10463 BaseOp = X86ISD::SUB;
10464 Cond = X86::COND_B;
10467 BaseOp = X86ISD::SMUL;
10468 Cond = X86::COND_O;
10470 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10471 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10473 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10476 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10477 DAG.getConstant(X86::COND_O, MVT::i32),
10478 SDValue(Sum.getNode(), 2));
10480 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10484 // Also sets EFLAGS.
10485 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10486 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10489 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10490 DAG.getConstant(Cond, MVT::i32),
10491 SDValue(Sum.getNode(), 1));
10493 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10496 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10497 SelectionDAG &DAG) const {
10498 DebugLoc dl = Op.getDebugLoc();
10499 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10500 EVT VT = Op.getValueType();
10502 if (!Subtarget->hasSSE2() || !VT.isVector())
10505 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10506 ExtraVT.getScalarType().getSizeInBits();
10507 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10509 switch (VT.getSimpleVT().SimpleTy) {
10510 default: return SDValue();
10513 if (!Subtarget->hasAVX())
10515 if (!Subtarget->hasAVX2()) {
10516 // needs to be split
10517 int NumElems = VT.getVectorNumElements();
10518 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10519 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10521 // Extract the LHS vectors
10522 SDValue LHS = Op.getOperand(0);
10523 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10524 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10526 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10527 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10529 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10530 int ExtraNumElems = ExtraVT.getVectorNumElements();
10531 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10533 SDValue Extra = DAG.getValueType(ExtraVT);
10535 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10536 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10538 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10543 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10544 Op.getOperand(0), ShAmt, DAG);
10545 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10551 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10552 DebugLoc dl = Op.getDebugLoc();
10554 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10555 // There isn't any reason to disable it if the target processor supports it.
10556 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10557 SDValue Chain = Op.getOperand(0);
10558 SDValue Zero = DAG.getConstant(0, MVT::i32);
10560 DAG.getRegister(X86::ESP, MVT::i32), // Base
10561 DAG.getTargetConstant(1, MVT::i8), // Scale
10562 DAG.getRegister(0, MVT::i32), // Index
10563 DAG.getTargetConstant(0, MVT::i32), // Disp
10564 DAG.getRegister(0, MVT::i32), // Segment.
10569 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10570 array_lengthof(Ops));
10571 return SDValue(Res, 0);
10574 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10576 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10578 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10579 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10580 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10581 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10583 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10584 if (!Op1 && !Op2 && !Op3 && Op4)
10585 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10587 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10588 if (Op1 && !Op2 && !Op3 && !Op4)
10589 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10591 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10593 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10596 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10597 SelectionDAG &DAG) const {
10598 DebugLoc dl = Op.getDebugLoc();
10599 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10600 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10601 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10602 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10604 // The only fence that needs an instruction is a sequentially-consistent
10605 // cross-thread fence.
10606 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10607 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10608 // no-sse2). There isn't any reason to disable it if the target processor
10610 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10611 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10613 SDValue Chain = Op.getOperand(0);
10614 SDValue Zero = DAG.getConstant(0, MVT::i32);
10616 DAG.getRegister(X86::ESP, MVT::i32), // Base
10617 DAG.getTargetConstant(1, MVT::i8), // Scale
10618 DAG.getRegister(0, MVT::i32), // Index
10619 DAG.getTargetConstant(0, MVT::i32), // Disp
10620 DAG.getRegister(0, MVT::i32), // Segment.
10625 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10626 array_lengthof(Ops));
10627 return SDValue(Res, 0);
10630 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10631 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10635 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10636 EVT T = Op.getValueType();
10637 DebugLoc DL = Op.getDebugLoc();
10640 switch(T.getSimpleVT().SimpleTy) {
10642 assert(false && "Invalid value type!");
10643 case MVT::i8: Reg = X86::AL; size = 1; break;
10644 case MVT::i16: Reg = X86::AX; size = 2; break;
10645 case MVT::i32: Reg = X86::EAX; size = 4; break;
10647 assert(Subtarget->is64Bit() && "Node not type legal!");
10648 Reg = X86::RAX; size = 8;
10651 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10652 Op.getOperand(2), SDValue());
10653 SDValue Ops[] = { cpIn.getValue(0),
10656 DAG.getTargetConstant(size, MVT::i8),
10657 cpIn.getValue(1) };
10658 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10659 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10660 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10663 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10667 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10668 SelectionDAG &DAG) const {
10669 assert(Subtarget->is64Bit() && "Result not type legalized?");
10670 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10671 SDValue TheChain = Op.getOperand(0);
10672 DebugLoc dl = Op.getDebugLoc();
10673 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10674 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10675 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10677 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10678 DAG.getConstant(32, MVT::i8));
10680 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10683 return DAG.getMergeValues(Ops, 2, dl);
10686 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10687 SelectionDAG &DAG) const {
10688 EVT SrcVT = Op.getOperand(0).getValueType();
10689 EVT DstVT = Op.getValueType();
10690 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10691 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10692 assert((DstVT == MVT::i64 ||
10693 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10694 "Unexpected custom BITCAST");
10695 // i64 <=> MMX conversions are Legal.
10696 if (SrcVT==MVT::i64 && DstVT.isVector())
10698 if (DstVT==MVT::i64 && SrcVT.isVector())
10700 // MMX <=> MMX conversions are Legal.
10701 if (SrcVT.isVector() && DstVT.isVector())
10703 // All other conversions need to be expanded.
10707 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10708 SDNode *Node = Op.getNode();
10709 DebugLoc dl = Node->getDebugLoc();
10710 EVT T = Node->getValueType(0);
10711 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10712 DAG.getConstant(0, T), Node->getOperand(2));
10713 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10714 cast<AtomicSDNode>(Node)->getMemoryVT(),
10715 Node->getOperand(0),
10716 Node->getOperand(1), negOp,
10717 cast<AtomicSDNode>(Node)->getSrcValue(),
10718 cast<AtomicSDNode>(Node)->getAlignment(),
10719 cast<AtomicSDNode>(Node)->getOrdering(),
10720 cast<AtomicSDNode>(Node)->getSynchScope());
10723 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10724 SDNode *Node = Op.getNode();
10725 DebugLoc dl = Node->getDebugLoc();
10726 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10728 // Convert seq_cst store -> xchg
10729 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10730 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10731 // (The only way to get a 16-byte store is cmpxchg16b)
10732 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10733 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10734 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10735 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10736 cast<AtomicSDNode>(Node)->getMemoryVT(),
10737 Node->getOperand(0),
10738 Node->getOperand(1), Node->getOperand(2),
10739 cast<AtomicSDNode>(Node)->getMemOperand(),
10740 cast<AtomicSDNode>(Node)->getOrdering(),
10741 cast<AtomicSDNode>(Node)->getSynchScope());
10742 return Swap.getValue(1);
10744 // Other atomic stores have a simple pattern.
10748 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10749 EVT VT = Op.getNode()->getValueType(0);
10751 // Let legalize expand this if it isn't a legal type yet.
10752 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10755 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10758 bool ExtraOp = false;
10759 switch (Op.getOpcode()) {
10760 default: assert(0 && "Invalid code");
10761 case ISD::ADDC: Opc = X86ISD::ADD; break;
10762 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10763 case ISD::SUBC: Opc = X86ISD::SUB; break;
10764 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10768 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10770 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10771 Op.getOperand(1), Op.getOperand(2));
10774 /// LowerOperation - Provide custom lowering hooks for some operations.
10776 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10777 switch (Op.getOpcode()) {
10778 default: llvm_unreachable("Should not custom lower this!");
10779 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10780 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10781 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10782 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10783 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10784 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10785 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10786 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10787 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10788 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10789 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10790 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10791 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10792 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10793 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10794 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10795 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10796 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10797 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10798 case ISD::SHL_PARTS:
10799 case ISD::SRA_PARTS:
10800 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10801 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10802 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10803 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10804 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10805 case ISD::FABS: return LowerFABS(Op, DAG);
10806 case ISD::FNEG: return LowerFNEG(Op, DAG);
10807 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10808 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10809 case ISD::SETCC: return LowerSETCC(Op, DAG);
10810 case ISD::SELECT: return LowerSELECT(Op, DAG);
10811 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10812 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10813 case ISD::VASTART: return LowerVASTART(Op, DAG);
10814 case ISD::VAARG: return LowerVAARG(Op, DAG);
10815 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10816 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10817 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10818 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10819 case ISD::FRAME_TO_ARGS_OFFSET:
10820 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10821 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10822 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10823 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10824 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10825 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10826 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10827 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10828 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10829 case ISD::MUL: return LowerMUL(Op, DAG);
10832 case ISD::SHL: return LowerShift(Op, DAG);
10838 case ISD::UMULO: return LowerXALUO(Op, DAG);
10839 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10840 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10844 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10845 case ISD::ADD: return LowerADD(Op, DAG);
10846 case ISD::SUB: return LowerSUB(Op, DAG);
10850 static void ReplaceATOMIC_LOAD(SDNode *Node,
10851 SmallVectorImpl<SDValue> &Results,
10852 SelectionDAG &DAG) {
10853 DebugLoc dl = Node->getDebugLoc();
10854 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10856 // Convert wide load -> cmpxchg8b/cmpxchg16b
10857 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10858 // (The only way to get a 16-byte load is cmpxchg16b)
10859 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10860 SDValue Zero = DAG.getConstant(0, VT);
10861 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10862 Node->getOperand(0),
10863 Node->getOperand(1), Zero, Zero,
10864 cast<AtomicSDNode>(Node)->getMemOperand(),
10865 cast<AtomicSDNode>(Node)->getOrdering(),
10866 cast<AtomicSDNode>(Node)->getSynchScope());
10867 Results.push_back(Swap.getValue(0));
10868 Results.push_back(Swap.getValue(1));
10871 void X86TargetLowering::
10872 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10873 SelectionDAG &DAG, unsigned NewOp) const {
10874 DebugLoc dl = Node->getDebugLoc();
10875 assert (Node->getValueType(0) == MVT::i64 &&
10876 "Only know how to expand i64 atomics");
10878 SDValue Chain = Node->getOperand(0);
10879 SDValue In1 = Node->getOperand(1);
10880 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10881 Node->getOperand(2), DAG.getIntPtrConstant(0));
10882 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10883 Node->getOperand(2), DAG.getIntPtrConstant(1));
10884 SDValue Ops[] = { Chain, In1, In2L, In2H };
10885 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10887 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10888 cast<MemSDNode>(Node)->getMemOperand());
10889 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10890 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10891 Results.push_back(Result.getValue(2));
10894 /// ReplaceNodeResults - Replace a node with an illegal result type
10895 /// with a new node built out of custom code.
10896 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10897 SmallVectorImpl<SDValue>&Results,
10898 SelectionDAG &DAG) const {
10899 DebugLoc dl = N->getDebugLoc();
10900 switch (N->getOpcode()) {
10902 assert(false && "Do not know how to custom type legalize this operation!");
10904 case ISD::SIGN_EXTEND_INREG:
10909 // We don't want to expand or promote these.
10911 case ISD::FP_TO_SINT: {
10912 std::pair<SDValue,SDValue> Vals =
10913 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10914 SDValue FIST = Vals.first, StackSlot = Vals.second;
10915 if (FIST.getNode() != 0) {
10916 EVT VT = N->getValueType(0);
10917 // Return a load from the stack slot.
10918 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10919 MachinePointerInfo(),
10920 false, false, false, 0));
10924 case ISD::READCYCLECOUNTER: {
10925 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10926 SDValue TheChain = N->getOperand(0);
10927 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10928 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10930 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10932 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10933 SDValue Ops[] = { eax, edx };
10934 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10935 Results.push_back(edx.getValue(1));
10938 case ISD::ATOMIC_CMP_SWAP: {
10939 EVT T = N->getValueType(0);
10940 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10941 bool Regs64bit = T == MVT::i128;
10942 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10943 SDValue cpInL, cpInH;
10944 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10945 DAG.getConstant(0, HalfT));
10946 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10947 DAG.getConstant(1, HalfT));
10948 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10949 Regs64bit ? X86::RAX : X86::EAX,
10951 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10952 Regs64bit ? X86::RDX : X86::EDX,
10953 cpInH, cpInL.getValue(1));
10954 SDValue swapInL, swapInH;
10955 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10956 DAG.getConstant(0, HalfT));
10957 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10958 DAG.getConstant(1, HalfT));
10959 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10960 Regs64bit ? X86::RBX : X86::EBX,
10961 swapInL, cpInH.getValue(1));
10962 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10963 Regs64bit ? X86::RCX : X86::ECX,
10964 swapInH, swapInL.getValue(1));
10965 SDValue Ops[] = { swapInH.getValue(0),
10967 swapInH.getValue(1) };
10968 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10969 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10970 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10971 X86ISD::LCMPXCHG8_DAG;
10972 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10974 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10975 Regs64bit ? X86::RAX : X86::EAX,
10976 HalfT, Result.getValue(1));
10977 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10978 Regs64bit ? X86::RDX : X86::EDX,
10979 HalfT, cpOutL.getValue(2));
10980 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10981 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10982 Results.push_back(cpOutH.getValue(1));
10985 case ISD::ATOMIC_LOAD_ADD:
10986 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10988 case ISD::ATOMIC_LOAD_AND:
10989 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10991 case ISD::ATOMIC_LOAD_NAND:
10992 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10994 case ISD::ATOMIC_LOAD_OR:
10995 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10997 case ISD::ATOMIC_LOAD_SUB:
10998 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11000 case ISD::ATOMIC_LOAD_XOR:
11001 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11003 case ISD::ATOMIC_SWAP:
11004 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11006 case ISD::ATOMIC_LOAD:
11007 ReplaceATOMIC_LOAD(N, Results, DAG);
11011 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11013 default: return NULL;
11014 case X86ISD::BSF: return "X86ISD::BSF";
11015 case X86ISD::BSR: return "X86ISD::BSR";
11016 case X86ISD::SHLD: return "X86ISD::SHLD";
11017 case X86ISD::SHRD: return "X86ISD::SHRD";
11018 case X86ISD::FAND: return "X86ISD::FAND";
11019 case X86ISD::FOR: return "X86ISD::FOR";
11020 case X86ISD::FXOR: return "X86ISD::FXOR";
11021 case X86ISD::FSRL: return "X86ISD::FSRL";
11022 case X86ISD::FILD: return "X86ISD::FILD";
11023 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11024 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11025 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11026 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11027 case X86ISD::FLD: return "X86ISD::FLD";
11028 case X86ISD::FST: return "X86ISD::FST";
11029 case X86ISD::CALL: return "X86ISD::CALL";
11030 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11031 case X86ISD::BT: return "X86ISD::BT";
11032 case X86ISD::CMP: return "X86ISD::CMP";
11033 case X86ISD::COMI: return "X86ISD::COMI";
11034 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11035 case X86ISD::SETCC: return "X86ISD::SETCC";
11036 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11037 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11038 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11039 case X86ISD::CMOV: return "X86ISD::CMOV";
11040 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11041 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11042 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11043 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11044 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11045 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11046 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11047 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11048 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11049 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11050 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11051 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11052 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11053 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11054 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11055 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11056 case X86ISD::HADD: return "X86ISD::HADD";
11057 case X86ISD::HSUB: return "X86ISD::HSUB";
11058 case X86ISD::FHADD: return "X86ISD::FHADD";
11059 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11060 case X86ISD::FMAX: return "X86ISD::FMAX";
11061 case X86ISD::FMIN: return "X86ISD::FMIN";
11062 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11063 case X86ISD::FRCP: return "X86ISD::FRCP";
11064 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11065 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11066 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11067 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11068 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11069 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11070 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11071 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11072 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11073 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11074 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11075 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11076 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11077 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11078 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11079 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11080 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11081 case X86ISD::VSHL: return "X86ISD::VSHL";
11082 case X86ISD::VSRL: return "X86ISD::VSRL";
11083 case X86ISD::VSRA: return "X86ISD::VSRA";
11084 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11085 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11086 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11087 case X86ISD::CMPP: return "X86ISD::CMPP";
11088 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11089 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11090 case X86ISD::ADD: return "X86ISD::ADD";
11091 case X86ISD::SUB: return "X86ISD::SUB";
11092 case X86ISD::ADC: return "X86ISD::ADC";
11093 case X86ISD::SBB: return "X86ISD::SBB";
11094 case X86ISD::SMUL: return "X86ISD::SMUL";
11095 case X86ISD::UMUL: return "X86ISD::UMUL";
11096 case X86ISD::INC: return "X86ISD::INC";
11097 case X86ISD::DEC: return "X86ISD::DEC";
11098 case X86ISD::OR: return "X86ISD::OR";
11099 case X86ISD::XOR: return "X86ISD::XOR";
11100 case X86ISD::AND: return "X86ISD::AND";
11101 case X86ISD::ANDN: return "X86ISD::ANDN";
11102 case X86ISD::BLSI: return "X86ISD::BLSI";
11103 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11104 case X86ISD::BLSR: return "X86ISD::BLSR";
11105 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11106 case X86ISD::PTEST: return "X86ISD::PTEST";
11107 case X86ISD::TESTP: return "X86ISD::TESTP";
11108 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11109 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11110 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11111 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11112 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11113 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11114 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11115 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11116 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11117 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11118 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11119 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11120 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11121 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11122 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11123 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11124 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11125 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11126 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11127 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11128 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11129 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11130 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11131 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11132 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11136 // isLegalAddressingMode - Return true if the addressing mode represented
11137 // by AM is legal for this target, for a load/store of the specified type.
11138 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11140 // X86 supports extremely general addressing modes.
11141 CodeModel::Model M = getTargetMachine().getCodeModel();
11142 Reloc::Model R = getTargetMachine().getRelocationModel();
11144 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11145 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11150 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11152 // If a reference to this global requires an extra load, we can't fold it.
11153 if (isGlobalStubReference(GVFlags))
11156 // If BaseGV requires a register for the PIC base, we cannot also have a
11157 // BaseReg specified.
11158 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11161 // If lower 4G is not available, then we must use rip-relative addressing.
11162 if ((M != CodeModel::Small || R != Reloc::Static) &&
11163 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11167 switch (AM.Scale) {
11173 // These scales always work.
11178 // These scales are formed with basereg+scalereg. Only accept if there is
11183 default: // Other stuff never works.
11191 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11192 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11194 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11195 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11196 if (NumBits1 <= NumBits2)
11201 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11202 if (!VT1.isInteger() || !VT2.isInteger())
11204 unsigned NumBits1 = VT1.getSizeInBits();
11205 unsigned NumBits2 = VT2.getSizeInBits();
11206 if (NumBits1 <= NumBits2)
11211 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11212 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11213 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11216 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11217 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11218 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11221 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11222 // i16 instructions are longer (0x66 prefix) and potentially slower.
11223 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11226 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11227 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11228 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11229 /// are assumed to be legal.
11231 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11233 // Very little shuffling can be done for 64-bit vectors right now.
11234 if (VT.getSizeInBits() == 64)
11237 // FIXME: pshufb, blends, shifts.
11238 return (VT.getVectorNumElements() == 2 ||
11239 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11240 isMOVLMask(M, VT) ||
11241 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11242 isPSHUFDMask(M, VT) ||
11243 isPSHUFHWMask(M, VT) ||
11244 isPSHUFLWMask(M, VT) ||
11245 isPALIGNRMask(M, VT, Subtarget) ||
11246 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11247 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11248 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11249 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11253 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11255 unsigned NumElts = VT.getVectorNumElements();
11256 // FIXME: This collection of masks seems suspect.
11259 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11260 return (isMOVLMask(Mask, VT) ||
11261 isCommutedMOVLMask(Mask, VT, true) ||
11262 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11263 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11268 //===----------------------------------------------------------------------===//
11269 // X86 Scheduler Hooks
11270 //===----------------------------------------------------------------------===//
11272 // private utility function
11273 MachineBasicBlock *
11274 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11275 MachineBasicBlock *MBB,
11282 TargetRegisterClass *RC,
11283 bool invSrc) const {
11284 // For the atomic bitwise operator, we generate
11287 // ld t1 = [bitinstr.addr]
11288 // op t2 = t1, [bitinstr.val]
11290 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11292 // fallthrough -->nextMBB
11293 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11294 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11295 MachineFunction::iterator MBBIter = MBB;
11298 /// First build the CFG
11299 MachineFunction *F = MBB->getParent();
11300 MachineBasicBlock *thisMBB = MBB;
11301 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11302 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11303 F->insert(MBBIter, newMBB);
11304 F->insert(MBBIter, nextMBB);
11306 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11307 nextMBB->splice(nextMBB->begin(), thisMBB,
11308 llvm::next(MachineBasicBlock::iterator(bInstr)),
11310 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11312 // Update thisMBB to fall through to newMBB
11313 thisMBB->addSuccessor(newMBB);
11315 // newMBB jumps to itself and fall through to nextMBB
11316 newMBB->addSuccessor(nextMBB);
11317 newMBB->addSuccessor(newMBB);
11319 // Insert instructions into newMBB based on incoming instruction
11320 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11321 "unexpected number of operands");
11322 DebugLoc dl = bInstr->getDebugLoc();
11323 MachineOperand& destOper = bInstr->getOperand(0);
11324 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11325 int numArgs = bInstr->getNumOperands() - 1;
11326 for (int i=0; i < numArgs; ++i)
11327 argOpers[i] = &bInstr->getOperand(i+1);
11329 // x86 address has 4 operands: base, index, scale, and displacement
11330 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11331 int valArgIndx = lastAddrIndx + 1;
11333 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11334 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11335 for (int i=0; i <= lastAddrIndx; ++i)
11336 (*MIB).addOperand(*argOpers[i]);
11338 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11340 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11345 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11346 assert((argOpers[valArgIndx]->isReg() ||
11347 argOpers[valArgIndx]->isImm()) &&
11348 "invalid operand");
11349 if (argOpers[valArgIndx]->isReg())
11350 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11352 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11354 (*MIB).addOperand(*argOpers[valArgIndx]);
11356 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11359 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11360 for (int i=0; i <= lastAddrIndx; ++i)
11361 (*MIB).addOperand(*argOpers[i]);
11363 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11364 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11365 bInstr->memoperands_end());
11367 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11368 MIB.addReg(EAXreg);
11371 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11373 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11377 // private utility function: 64 bit atomics on 32 bit host.
11378 MachineBasicBlock *
11379 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11380 MachineBasicBlock *MBB,
11385 bool invSrc) const {
11386 // For the atomic bitwise operator, we generate
11387 // thisMBB (instructions are in pairs, except cmpxchg8b)
11388 // ld t1,t2 = [bitinstr.addr]
11390 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11391 // op t5, t6 <- out1, out2, [bitinstr.val]
11392 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11393 // mov ECX, EBX <- t5, t6
11394 // mov EAX, EDX <- t1, t2
11395 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11396 // mov t3, t4 <- EAX, EDX
11398 // result in out1, out2
11399 // fallthrough -->nextMBB
11401 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11402 const unsigned LoadOpc = X86::MOV32rm;
11403 const unsigned NotOpc = X86::NOT32r;
11404 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11405 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11406 MachineFunction::iterator MBBIter = MBB;
11409 /// First build the CFG
11410 MachineFunction *F = MBB->getParent();
11411 MachineBasicBlock *thisMBB = MBB;
11412 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11413 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11414 F->insert(MBBIter, newMBB);
11415 F->insert(MBBIter, nextMBB);
11417 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11418 nextMBB->splice(nextMBB->begin(), thisMBB,
11419 llvm::next(MachineBasicBlock::iterator(bInstr)),
11421 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11423 // Update thisMBB to fall through to newMBB
11424 thisMBB->addSuccessor(newMBB);
11426 // newMBB jumps to itself and fall through to nextMBB
11427 newMBB->addSuccessor(nextMBB);
11428 newMBB->addSuccessor(newMBB);
11430 DebugLoc dl = bInstr->getDebugLoc();
11431 // Insert instructions into newMBB based on incoming instruction
11432 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11433 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11434 "unexpected number of operands");
11435 MachineOperand& dest1Oper = bInstr->getOperand(0);
11436 MachineOperand& dest2Oper = bInstr->getOperand(1);
11437 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11438 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11439 argOpers[i] = &bInstr->getOperand(i+2);
11441 // We use some of the operands multiple times, so conservatively just
11442 // clear any kill flags that might be present.
11443 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11444 argOpers[i]->setIsKill(false);
11447 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11448 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11450 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11451 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11452 for (int i=0; i <= lastAddrIndx; ++i)
11453 (*MIB).addOperand(*argOpers[i]);
11454 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11455 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11456 // add 4 to displacement.
11457 for (int i=0; i <= lastAddrIndx-2; ++i)
11458 (*MIB).addOperand(*argOpers[i]);
11459 MachineOperand newOp3 = *(argOpers[3]);
11460 if (newOp3.isImm())
11461 newOp3.setImm(newOp3.getImm()+4);
11463 newOp3.setOffset(newOp3.getOffset()+4);
11464 (*MIB).addOperand(newOp3);
11465 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11467 // t3/4 are defined later, at the bottom of the loop
11468 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11469 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11470 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11471 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11472 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11473 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11475 // The subsequent operations should be using the destination registers of
11476 //the PHI instructions.
11478 t1 = F->getRegInfo().createVirtualRegister(RC);
11479 t2 = F->getRegInfo().createVirtualRegister(RC);
11480 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11481 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11483 t1 = dest1Oper.getReg();
11484 t2 = dest2Oper.getReg();
11487 int valArgIndx = lastAddrIndx + 1;
11488 assert((argOpers[valArgIndx]->isReg() ||
11489 argOpers[valArgIndx]->isImm()) &&
11490 "invalid operand");
11491 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11492 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11493 if (argOpers[valArgIndx]->isReg())
11494 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11496 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11497 if (regOpcL != X86::MOV32rr)
11499 (*MIB).addOperand(*argOpers[valArgIndx]);
11500 assert(argOpers[valArgIndx + 1]->isReg() ==
11501 argOpers[valArgIndx]->isReg());
11502 assert(argOpers[valArgIndx + 1]->isImm() ==
11503 argOpers[valArgIndx]->isImm());
11504 if (argOpers[valArgIndx + 1]->isReg())
11505 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11507 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11508 if (regOpcH != X86::MOV32rr)
11510 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11512 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11514 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11517 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11519 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11522 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11523 for (int i=0; i <= lastAddrIndx; ++i)
11524 (*MIB).addOperand(*argOpers[i]);
11526 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11527 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11528 bInstr->memoperands_end());
11530 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11531 MIB.addReg(X86::EAX);
11532 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11533 MIB.addReg(X86::EDX);
11536 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11538 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11542 // private utility function
11543 MachineBasicBlock *
11544 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11545 MachineBasicBlock *MBB,
11546 unsigned cmovOpc) const {
11547 // For the atomic min/max operator, we generate
11550 // ld t1 = [min/max.addr]
11551 // mov t2 = [min/max.val]
11553 // cmov[cond] t2 = t1
11555 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11557 // fallthrough -->nextMBB
11559 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11560 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11561 MachineFunction::iterator MBBIter = MBB;
11564 /// First build the CFG
11565 MachineFunction *F = MBB->getParent();
11566 MachineBasicBlock *thisMBB = MBB;
11567 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11568 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11569 F->insert(MBBIter, newMBB);
11570 F->insert(MBBIter, nextMBB);
11572 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11573 nextMBB->splice(nextMBB->begin(), thisMBB,
11574 llvm::next(MachineBasicBlock::iterator(mInstr)),
11576 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11578 // Update thisMBB to fall through to newMBB
11579 thisMBB->addSuccessor(newMBB);
11581 // newMBB jumps to newMBB and fall through to nextMBB
11582 newMBB->addSuccessor(nextMBB);
11583 newMBB->addSuccessor(newMBB);
11585 DebugLoc dl = mInstr->getDebugLoc();
11586 // Insert instructions into newMBB based on incoming instruction
11587 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11588 "unexpected number of operands");
11589 MachineOperand& destOper = mInstr->getOperand(0);
11590 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11591 int numArgs = mInstr->getNumOperands() - 1;
11592 for (int i=0; i < numArgs; ++i)
11593 argOpers[i] = &mInstr->getOperand(i+1);
11595 // x86 address has 4 operands: base, index, scale, and displacement
11596 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11597 int valArgIndx = lastAddrIndx + 1;
11599 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11600 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11601 for (int i=0; i <= lastAddrIndx; ++i)
11602 (*MIB).addOperand(*argOpers[i]);
11604 // We only support register and immediate values
11605 assert((argOpers[valArgIndx]->isReg() ||
11606 argOpers[valArgIndx]->isImm()) &&
11607 "invalid operand");
11609 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11610 if (argOpers[valArgIndx]->isReg())
11611 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11613 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11614 (*MIB).addOperand(*argOpers[valArgIndx]);
11616 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11619 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11624 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11625 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11629 // Cmp and exchange if none has modified the memory location
11630 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11631 for (int i=0; i <= lastAddrIndx; ++i)
11632 (*MIB).addOperand(*argOpers[i]);
11634 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11635 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11636 mInstr->memoperands_end());
11638 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11639 MIB.addReg(X86::EAX);
11642 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11644 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11648 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11649 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11650 // in the .td file.
11651 MachineBasicBlock *
11652 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11653 unsigned numArgs, bool memArg) const {
11654 assert(Subtarget->hasSSE42() &&
11655 "Target must have SSE4.2 or AVX features enabled");
11657 DebugLoc dl = MI->getDebugLoc();
11658 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11660 if (!Subtarget->hasAVX()) {
11662 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11664 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11667 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11669 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11672 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11673 for (unsigned i = 0; i < numArgs; ++i) {
11674 MachineOperand &Op = MI->getOperand(i+1);
11675 if (!(Op.isReg() && Op.isImplicit()))
11676 MIB.addOperand(Op);
11678 BuildMI(*BB, MI, dl,
11679 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11680 MI->getOperand(0).getReg())
11681 .addReg(X86::XMM0);
11683 MI->eraseFromParent();
11687 MachineBasicBlock *
11688 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11689 DebugLoc dl = MI->getDebugLoc();
11690 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11692 // Address into RAX/EAX, other two args into ECX, EDX.
11693 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11694 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11695 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11696 for (int i = 0; i < X86::AddrNumOperands; ++i)
11697 MIB.addOperand(MI->getOperand(i));
11699 unsigned ValOps = X86::AddrNumOperands;
11700 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11701 .addReg(MI->getOperand(ValOps).getReg());
11702 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11703 .addReg(MI->getOperand(ValOps+1).getReg());
11705 // The instruction doesn't actually take any operands though.
11706 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11708 MI->eraseFromParent(); // The pseudo is gone now.
11712 MachineBasicBlock *
11713 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11714 DebugLoc dl = MI->getDebugLoc();
11715 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11717 // First arg in ECX, the second in EAX.
11718 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11719 .addReg(MI->getOperand(0).getReg());
11720 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11721 .addReg(MI->getOperand(1).getReg());
11723 // The instruction doesn't actually take any operands though.
11724 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11726 MI->eraseFromParent(); // The pseudo is gone now.
11730 MachineBasicBlock *
11731 X86TargetLowering::EmitVAARG64WithCustomInserter(
11733 MachineBasicBlock *MBB) const {
11734 // Emit va_arg instruction on X86-64.
11736 // Operands to this pseudo-instruction:
11737 // 0 ) Output : destination address (reg)
11738 // 1-5) Input : va_list address (addr, i64mem)
11739 // 6 ) ArgSize : Size (in bytes) of vararg type
11740 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11741 // 8 ) Align : Alignment of type
11742 // 9 ) EFLAGS (implicit-def)
11744 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11745 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11747 unsigned DestReg = MI->getOperand(0).getReg();
11748 MachineOperand &Base = MI->getOperand(1);
11749 MachineOperand &Scale = MI->getOperand(2);
11750 MachineOperand &Index = MI->getOperand(3);
11751 MachineOperand &Disp = MI->getOperand(4);
11752 MachineOperand &Segment = MI->getOperand(5);
11753 unsigned ArgSize = MI->getOperand(6).getImm();
11754 unsigned ArgMode = MI->getOperand(7).getImm();
11755 unsigned Align = MI->getOperand(8).getImm();
11757 // Memory Reference
11758 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11759 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11760 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11762 // Machine Information
11763 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11764 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11765 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11766 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11767 DebugLoc DL = MI->getDebugLoc();
11769 // struct va_list {
11772 // i64 overflow_area (address)
11773 // i64 reg_save_area (address)
11775 // sizeof(va_list) = 24
11776 // alignment(va_list) = 8
11778 unsigned TotalNumIntRegs = 6;
11779 unsigned TotalNumXMMRegs = 8;
11780 bool UseGPOffset = (ArgMode == 1);
11781 bool UseFPOffset = (ArgMode == 2);
11782 unsigned MaxOffset = TotalNumIntRegs * 8 +
11783 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11785 /* Align ArgSize to a multiple of 8 */
11786 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11787 bool NeedsAlign = (Align > 8);
11789 MachineBasicBlock *thisMBB = MBB;
11790 MachineBasicBlock *overflowMBB;
11791 MachineBasicBlock *offsetMBB;
11792 MachineBasicBlock *endMBB;
11794 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11795 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11796 unsigned OffsetReg = 0;
11798 if (!UseGPOffset && !UseFPOffset) {
11799 // If we only pull from the overflow region, we don't create a branch.
11800 // We don't need to alter control flow.
11801 OffsetDestReg = 0; // unused
11802 OverflowDestReg = DestReg;
11805 overflowMBB = thisMBB;
11808 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11809 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11810 // If not, pull from overflow_area. (branch to overflowMBB)
11815 // offsetMBB overflowMBB
11820 // Registers for the PHI in endMBB
11821 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11822 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11824 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11825 MachineFunction *MF = MBB->getParent();
11826 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11827 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11828 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11830 MachineFunction::iterator MBBIter = MBB;
11833 // Insert the new basic blocks
11834 MF->insert(MBBIter, offsetMBB);
11835 MF->insert(MBBIter, overflowMBB);
11836 MF->insert(MBBIter, endMBB);
11838 // Transfer the remainder of MBB and its successor edges to endMBB.
11839 endMBB->splice(endMBB->begin(), thisMBB,
11840 llvm::next(MachineBasicBlock::iterator(MI)),
11842 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11844 // Make offsetMBB and overflowMBB successors of thisMBB
11845 thisMBB->addSuccessor(offsetMBB);
11846 thisMBB->addSuccessor(overflowMBB);
11848 // endMBB is a successor of both offsetMBB and overflowMBB
11849 offsetMBB->addSuccessor(endMBB);
11850 overflowMBB->addSuccessor(endMBB);
11852 // Load the offset value into a register
11853 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11854 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11858 .addDisp(Disp, UseFPOffset ? 4 : 0)
11859 .addOperand(Segment)
11860 .setMemRefs(MMOBegin, MMOEnd);
11862 // Check if there is enough room left to pull this argument.
11863 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11865 .addImm(MaxOffset + 8 - ArgSizeA8);
11867 // Branch to "overflowMBB" if offset >= max
11868 // Fall through to "offsetMBB" otherwise
11869 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11870 .addMBB(overflowMBB);
11873 // In offsetMBB, emit code to use the reg_save_area.
11875 assert(OffsetReg != 0);
11877 // Read the reg_save_area address.
11878 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11879 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11884 .addOperand(Segment)
11885 .setMemRefs(MMOBegin, MMOEnd);
11887 // Zero-extend the offset
11888 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11889 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11892 .addImm(X86::sub_32bit);
11894 // Add the offset to the reg_save_area to get the final address.
11895 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11896 .addReg(OffsetReg64)
11897 .addReg(RegSaveReg);
11899 // Compute the offset for the next argument
11900 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11901 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11903 .addImm(UseFPOffset ? 16 : 8);
11905 // Store it back into the va_list.
11906 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11910 .addDisp(Disp, UseFPOffset ? 4 : 0)
11911 .addOperand(Segment)
11912 .addReg(NextOffsetReg)
11913 .setMemRefs(MMOBegin, MMOEnd);
11916 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11921 // Emit code to use overflow area
11924 // Load the overflow_area address into a register.
11925 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11926 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11931 .addOperand(Segment)
11932 .setMemRefs(MMOBegin, MMOEnd);
11934 // If we need to align it, do so. Otherwise, just copy the address
11935 // to OverflowDestReg.
11937 // Align the overflow address
11938 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11939 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11941 // aligned_addr = (addr + (align-1)) & ~(align-1)
11942 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11943 .addReg(OverflowAddrReg)
11946 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11948 .addImm(~(uint64_t)(Align-1));
11950 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11951 .addReg(OverflowAddrReg);
11954 // Compute the next overflow address after this argument.
11955 // (the overflow address should be kept 8-byte aligned)
11956 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11957 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11958 .addReg(OverflowDestReg)
11959 .addImm(ArgSizeA8);
11961 // Store the new overflow address.
11962 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11967 .addOperand(Segment)
11968 .addReg(NextAddrReg)
11969 .setMemRefs(MMOBegin, MMOEnd);
11971 // If we branched, emit the PHI to the front of endMBB.
11973 BuildMI(*endMBB, endMBB->begin(), DL,
11974 TII->get(X86::PHI), DestReg)
11975 .addReg(OffsetDestReg).addMBB(offsetMBB)
11976 .addReg(OverflowDestReg).addMBB(overflowMBB);
11979 // Erase the pseudo instruction
11980 MI->eraseFromParent();
11985 MachineBasicBlock *
11986 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11988 MachineBasicBlock *MBB) const {
11989 // Emit code to save XMM registers to the stack. The ABI says that the
11990 // number of registers to save is given in %al, so it's theoretically
11991 // possible to do an indirect jump trick to avoid saving all of them,
11992 // however this code takes a simpler approach and just executes all
11993 // of the stores if %al is non-zero. It's less code, and it's probably
11994 // easier on the hardware branch predictor, and stores aren't all that
11995 // expensive anyway.
11997 // Create the new basic blocks. One block contains all the XMM stores,
11998 // and one block is the final destination regardless of whether any
11999 // stores were performed.
12000 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12001 MachineFunction *F = MBB->getParent();
12002 MachineFunction::iterator MBBIter = MBB;
12004 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12005 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12006 F->insert(MBBIter, XMMSaveMBB);
12007 F->insert(MBBIter, EndMBB);
12009 // Transfer the remainder of MBB and its successor edges to EndMBB.
12010 EndMBB->splice(EndMBB->begin(), MBB,
12011 llvm::next(MachineBasicBlock::iterator(MI)),
12013 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12015 // The original block will now fall through to the XMM save block.
12016 MBB->addSuccessor(XMMSaveMBB);
12017 // The XMMSaveMBB will fall through to the end block.
12018 XMMSaveMBB->addSuccessor(EndMBB);
12020 // Now add the instructions.
12021 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12022 DebugLoc DL = MI->getDebugLoc();
12024 unsigned CountReg = MI->getOperand(0).getReg();
12025 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12026 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12028 if (!Subtarget->isTargetWin64()) {
12029 // If %al is 0, branch around the XMM save block.
12030 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12031 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12032 MBB->addSuccessor(EndMBB);
12035 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12036 // In the XMM save block, save all the XMM argument registers.
12037 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12038 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12039 MachineMemOperand *MMO =
12040 F->getMachineMemOperand(
12041 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12042 MachineMemOperand::MOStore,
12043 /*Size=*/16, /*Align=*/16);
12044 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12045 .addFrameIndex(RegSaveFrameIndex)
12046 .addImm(/*Scale=*/1)
12047 .addReg(/*IndexReg=*/0)
12048 .addImm(/*Disp=*/Offset)
12049 .addReg(/*Segment=*/0)
12050 .addReg(MI->getOperand(i).getReg())
12051 .addMemOperand(MMO);
12054 MI->eraseFromParent(); // The pseudo instruction is gone now.
12059 MachineBasicBlock *
12060 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12061 MachineBasicBlock *BB) const {
12062 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12063 DebugLoc DL = MI->getDebugLoc();
12065 // To "insert" a SELECT_CC instruction, we actually have to insert the
12066 // diamond control-flow pattern. The incoming instruction knows the
12067 // destination vreg to set, the condition code register to branch on, the
12068 // true/false values to select between, and a branch opcode to use.
12069 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12070 MachineFunction::iterator It = BB;
12076 // cmpTY ccX, r1, r2
12078 // fallthrough --> copy0MBB
12079 MachineBasicBlock *thisMBB = BB;
12080 MachineFunction *F = BB->getParent();
12081 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12082 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12083 F->insert(It, copy0MBB);
12084 F->insert(It, sinkMBB);
12086 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12087 // live into the sink and copy blocks.
12088 if (!MI->killsRegister(X86::EFLAGS)) {
12089 copy0MBB->addLiveIn(X86::EFLAGS);
12090 sinkMBB->addLiveIn(X86::EFLAGS);
12093 // Transfer the remainder of BB and its successor edges to sinkMBB.
12094 sinkMBB->splice(sinkMBB->begin(), BB,
12095 llvm::next(MachineBasicBlock::iterator(MI)),
12097 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12099 // Add the true and fallthrough blocks as its successors.
12100 BB->addSuccessor(copy0MBB);
12101 BB->addSuccessor(sinkMBB);
12103 // Create the conditional branch instruction.
12105 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12106 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12109 // %FalseValue = ...
12110 // # fallthrough to sinkMBB
12111 copy0MBB->addSuccessor(sinkMBB);
12114 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12116 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12117 TII->get(X86::PHI), MI->getOperand(0).getReg())
12118 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12119 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12121 MI->eraseFromParent(); // The pseudo instruction is gone now.
12125 MachineBasicBlock *
12126 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12127 bool Is64Bit) const {
12128 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12129 DebugLoc DL = MI->getDebugLoc();
12130 MachineFunction *MF = BB->getParent();
12131 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12133 assert(getTargetMachine().Options.EnableSegmentedStacks);
12135 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12136 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12139 // ... [Till the alloca]
12140 // If stacklet is not large enough, jump to mallocMBB
12143 // Allocate by subtracting from RSP
12144 // Jump to continueMBB
12147 // Allocate by call to runtime
12151 // [rest of original BB]
12154 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12155 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12156 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12158 MachineRegisterInfo &MRI = MF->getRegInfo();
12159 const TargetRegisterClass *AddrRegClass =
12160 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12162 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12163 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12164 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12165 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12166 sizeVReg = MI->getOperand(1).getReg(),
12167 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12169 MachineFunction::iterator MBBIter = BB;
12172 MF->insert(MBBIter, bumpMBB);
12173 MF->insert(MBBIter, mallocMBB);
12174 MF->insert(MBBIter, continueMBB);
12176 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12177 (MachineBasicBlock::iterator(MI)), BB->end());
12178 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12180 // Add code to the main basic block to check if the stack limit has been hit,
12181 // and if so, jump to mallocMBB otherwise to bumpMBB.
12182 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12183 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12184 .addReg(tmpSPVReg).addReg(sizeVReg);
12185 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12186 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12187 .addReg(SPLimitVReg);
12188 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12190 // bumpMBB simply decreases the stack pointer, since we know the current
12191 // stacklet has enough space.
12192 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12193 .addReg(SPLimitVReg);
12194 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12195 .addReg(SPLimitVReg);
12196 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12198 // Calls into a routine in libgcc to allocate more space from the heap.
12200 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12202 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12203 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12205 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12207 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12208 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12209 .addExternalSymbol("__morestack_allocate_stack_space");
12213 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12216 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12217 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12218 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12220 // Set up the CFG correctly.
12221 BB->addSuccessor(bumpMBB);
12222 BB->addSuccessor(mallocMBB);
12223 mallocMBB->addSuccessor(continueMBB);
12224 bumpMBB->addSuccessor(continueMBB);
12226 // Take care of the PHI nodes.
12227 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12228 MI->getOperand(0).getReg())
12229 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12230 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12232 // Delete the original pseudo instruction.
12233 MI->eraseFromParent();
12236 return continueMBB;
12239 MachineBasicBlock *
12240 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12241 MachineBasicBlock *BB) const {
12242 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12243 DebugLoc DL = MI->getDebugLoc();
12245 assert(!Subtarget->isTargetEnvMacho());
12247 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12248 // non-trivial part is impdef of ESP.
12250 if (Subtarget->isTargetWin64()) {
12251 if (Subtarget->isTargetCygMing()) {
12252 // ___chkstk(Mingw64):
12253 // Clobbers R10, R11, RAX and EFLAGS.
12255 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12256 .addExternalSymbol("___chkstk")
12257 .addReg(X86::RAX, RegState::Implicit)
12258 .addReg(X86::RSP, RegState::Implicit)
12259 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12260 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12261 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12263 // __chkstk(MSVCRT): does not update stack pointer.
12264 // Clobbers R10, R11 and EFLAGS.
12265 // FIXME: RAX(allocated size) might be reused and not killed.
12266 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12267 .addExternalSymbol("__chkstk")
12268 .addReg(X86::RAX, RegState::Implicit)
12269 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12270 // RAX has the offset to subtracted from RSP.
12271 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12276 const char *StackProbeSymbol =
12277 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12279 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12280 .addExternalSymbol(StackProbeSymbol)
12281 .addReg(X86::EAX, RegState::Implicit)
12282 .addReg(X86::ESP, RegState::Implicit)
12283 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12284 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12285 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12288 MI->eraseFromParent(); // The pseudo instruction is gone now.
12292 MachineBasicBlock *
12293 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12294 MachineBasicBlock *BB) const {
12295 // This is pretty easy. We're taking the value that we received from
12296 // our load from the relocation, sticking it in either RDI (x86-64)
12297 // or EAX and doing an indirect call. The return value will then
12298 // be in the normal return register.
12299 const X86InstrInfo *TII
12300 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12301 DebugLoc DL = MI->getDebugLoc();
12302 MachineFunction *F = BB->getParent();
12304 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12305 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12307 if (Subtarget->is64Bit()) {
12308 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12309 TII->get(X86::MOV64rm), X86::RDI)
12311 .addImm(0).addReg(0)
12312 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12313 MI->getOperand(3).getTargetFlags())
12315 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12316 addDirectMem(MIB, X86::RDI);
12317 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12318 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12319 TII->get(X86::MOV32rm), X86::EAX)
12321 .addImm(0).addReg(0)
12322 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12323 MI->getOperand(3).getTargetFlags())
12325 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12326 addDirectMem(MIB, X86::EAX);
12328 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12329 TII->get(X86::MOV32rm), X86::EAX)
12330 .addReg(TII->getGlobalBaseReg(F))
12331 .addImm(0).addReg(0)
12332 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12333 MI->getOperand(3).getTargetFlags())
12335 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12336 addDirectMem(MIB, X86::EAX);
12339 MI->eraseFromParent(); // The pseudo instruction is gone now.
12343 MachineBasicBlock *
12344 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12345 MachineBasicBlock *BB) const {
12346 switch (MI->getOpcode()) {
12347 default: assert(0 && "Unexpected instr type to insert");
12348 case X86::TAILJMPd64:
12349 case X86::TAILJMPr64:
12350 case X86::TAILJMPm64:
12351 assert(0 && "TAILJMP64 would not be touched here.");
12352 case X86::TCRETURNdi64:
12353 case X86::TCRETURNri64:
12354 case X86::TCRETURNmi64:
12355 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12356 // On AMD64, additional defs should be added before register allocation.
12357 if (!Subtarget->isTargetWin64()) {
12358 MI->addRegisterDefined(X86::RSI);
12359 MI->addRegisterDefined(X86::RDI);
12360 MI->addRegisterDefined(X86::XMM6);
12361 MI->addRegisterDefined(X86::XMM7);
12362 MI->addRegisterDefined(X86::XMM8);
12363 MI->addRegisterDefined(X86::XMM9);
12364 MI->addRegisterDefined(X86::XMM10);
12365 MI->addRegisterDefined(X86::XMM11);
12366 MI->addRegisterDefined(X86::XMM12);
12367 MI->addRegisterDefined(X86::XMM13);
12368 MI->addRegisterDefined(X86::XMM14);
12369 MI->addRegisterDefined(X86::XMM15);
12372 case X86::WIN_ALLOCA:
12373 return EmitLoweredWinAlloca(MI, BB);
12374 case X86::SEG_ALLOCA_32:
12375 return EmitLoweredSegAlloca(MI, BB, false);
12376 case X86::SEG_ALLOCA_64:
12377 return EmitLoweredSegAlloca(MI, BB, true);
12378 case X86::TLSCall_32:
12379 case X86::TLSCall_64:
12380 return EmitLoweredTLSCall(MI, BB);
12381 case X86::CMOV_GR8:
12382 case X86::CMOV_FR32:
12383 case X86::CMOV_FR64:
12384 case X86::CMOV_V4F32:
12385 case X86::CMOV_V2F64:
12386 case X86::CMOV_V2I64:
12387 case X86::CMOV_V8F32:
12388 case X86::CMOV_V4F64:
12389 case X86::CMOV_V4I64:
12390 case X86::CMOV_GR16:
12391 case X86::CMOV_GR32:
12392 case X86::CMOV_RFP32:
12393 case X86::CMOV_RFP64:
12394 case X86::CMOV_RFP80:
12395 return EmitLoweredSelect(MI, BB);
12397 case X86::FP32_TO_INT16_IN_MEM:
12398 case X86::FP32_TO_INT32_IN_MEM:
12399 case X86::FP32_TO_INT64_IN_MEM:
12400 case X86::FP64_TO_INT16_IN_MEM:
12401 case X86::FP64_TO_INT32_IN_MEM:
12402 case X86::FP64_TO_INT64_IN_MEM:
12403 case X86::FP80_TO_INT16_IN_MEM:
12404 case X86::FP80_TO_INT32_IN_MEM:
12405 case X86::FP80_TO_INT64_IN_MEM: {
12406 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12407 DebugLoc DL = MI->getDebugLoc();
12409 // Change the floating point control register to use "round towards zero"
12410 // mode when truncating to an integer value.
12411 MachineFunction *F = BB->getParent();
12412 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12413 addFrameReference(BuildMI(*BB, MI, DL,
12414 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12416 // Load the old value of the high byte of the control word...
12418 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12419 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12422 // Set the high part to be round to zero...
12423 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12426 // Reload the modified control word now...
12427 addFrameReference(BuildMI(*BB, MI, DL,
12428 TII->get(X86::FLDCW16m)), CWFrameIdx);
12430 // Restore the memory image of control word to original value
12431 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12434 // Get the X86 opcode to use.
12436 switch (MI->getOpcode()) {
12437 default: llvm_unreachable("illegal opcode!");
12438 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12439 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12440 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12441 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12442 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12443 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12444 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12445 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12446 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12450 MachineOperand &Op = MI->getOperand(0);
12452 AM.BaseType = X86AddressMode::RegBase;
12453 AM.Base.Reg = Op.getReg();
12455 AM.BaseType = X86AddressMode::FrameIndexBase;
12456 AM.Base.FrameIndex = Op.getIndex();
12458 Op = MI->getOperand(1);
12460 AM.Scale = Op.getImm();
12461 Op = MI->getOperand(2);
12463 AM.IndexReg = Op.getImm();
12464 Op = MI->getOperand(3);
12465 if (Op.isGlobal()) {
12466 AM.GV = Op.getGlobal();
12468 AM.Disp = Op.getImm();
12470 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12471 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12473 // Reload the original control word now.
12474 addFrameReference(BuildMI(*BB, MI, DL,
12475 TII->get(X86::FLDCW16m)), CWFrameIdx);
12477 MI->eraseFromParent(); // The pseudo instruction is gone now.
12480 // String/text processing lowering.
12481 case X86::PCMPISTRM128REG:
12482 case X86::VPCMPISTRM128REG:
12483 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12484 case X86::PCMPISTRM128MEM:
12485 case X86::VPCMPISTRM128MEM:
12486 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12487 case X86::PCMPESTRM128REG:
12488 case X86::VPCMPESTRM128REG:
12489 return EmitPCMP(MI, BB, 5, false /* in mem */);
12490 case X86::PCMPESTRM128MEM:
12491 case X86::VPCMPESTRM128MEM:
12492 return EmitPCMP(MI, BB, 5, true /* in mem */);
12494 // Thread synchronization.
12496 return EmitMonitor(MI, BB);
12498 return EmitMwait(MI, BB);
12500 // Atomic Lowering.
12501 case X86::ATOMAND32:
12502 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12503 X86::AND32ri, X86::MOV32rm,
12505 X86::NOT32r, X86::EAX,
12506 X86::GR32RegisterClass);
12507 case X86::ATOMOR32:
12508 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12509 X86::OR32ri, X86::MOV32rm,
12511 X86::NOT32r, X86::EAX,
12512 X86::GR32RegisterClass);
12513 case X86::ATOMXOR32:
12514 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12515 X86::XOR32ri, X86::MOV32rm,
12517 X86::NOT32r, X86::EAX,
12518 X86::GR32RegisterClass);
12519 case X86::ATOMNAND32:
12520 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12521 X86::AND32ri, X86::MOV32rm,
12523 X86::NOT32r, X86::EAX,
12524 X86::GR32RegisterClass, true);
12525 case X86::ATOMMIN32:
12526 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12527 case X86::ATOMMAX32:
12528 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12529 case X86::ATOMUMIN32:
12530 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12531 case X86::ATOMUMAX32:
12532 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12534 case X86::ATOMAND16:
12535 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12536 X86::AND16ri, X86::MOV16rm,
12538 X86::NOT16r, X86::AX,
12539 X86::GR16RegisterClass);
12540 case X86::ATOMOR16:
12541 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12542 X86::OR16ri, X86::MOV16rm,
12544 X86::NOT16r, X86::AX,
12545 X86::GR16RegisterClass);
12546 case X86::ATOMXOR16:
12547 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12548 X86::XOR16ri, X86::MOV16rm,
12550 X86::NOT16r, X86::AX,
12551 X86::GR16RegisterClass);
12552 case X86::ATOMNAND16:
12553 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12554 X86::AND16ri, X86::MOV16rm,
12556 X86::NOT16r, X86::AX,
12557 X86::GR16RegisterClass, true);
12558 case X86::ATOMMIN16:
12559 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12560 case X86::ATOMMAX16:
12561 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12562 case X86::ATOMUMIN16:
12563 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12564 case X86::ATOMUMAX16:
12565 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12567 case X86::ATOMAND8:
12568 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12569 X86::AND8ri, X86::MOV8rm,
12571 X86::NOT8r, X86::AL,
12572 X86::GR8RegisterClass);
12574 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12575 X86::OR8ri, X86::MOV8rm,
12577 X86::NOT8r, X86::AL,
12578 X86::GR8RegisterClass);
12579 case X86::ATOMXOR8:
12580 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12581 X86::XOR8ri, X86::MOV8rm,
12583 X86::NOT8r, X86::AL,
12584 X86::GR8RegisterClass);
12585 case X86::ATOMNAND8:
12586 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12587 X86::AND8ri, X86::MOV8rm,
12589 X86::NOT8r, X86::AL,
12590 X86::GR8RegisterClass, true);
12591 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12592 // This group is for 64-bit host.
12593 case X86::ATOMAND64:
12594 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12595 X86::AND64ri32, X86::MOV64rm,
12597 X86::NOT64r, X86::RAX,
12598 X86::GR64RegisterClass);
12599 case X86::ATOMOR64:
12600 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12601 X86::OR64ri32, X86::MOV64rm,
12603 X86::NOT64r, X86::RAX,
12604 X86::GR64RegisterClass);
12605 case X86::ATOMXOR64:
12606 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12607 X86::XOR64ri32, X86::MOV64rm,
12609 X86::NOT64r, X86::RAX,
12610 X86::GR64RegisterClass);
12611 case X86::ATOMNAND64:
12612 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12613 X86::AND64ri32, X86::MOV64rm,
12615 X86::NOT64r, X86::RAX,
12616 X86::GR64RegisterClass, true);
12617 case X86::ATOMMIN64:
12618 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12619 case X86::ATOMMAX64:
12620 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12621 case X86::ATOMUMIN64:
12622 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12623 case X86::ATOMUMAX64:
12624 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12626 // This group does 64-bit operations on a 32-bit host.
12627 case X86::ATOMAND6432:
12628 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12629 X86::AND32rr, X86::AND32rr,
12630 X86::AND32ri, X86::AND32ri,
12632 case X86::ATOMOR6432:
12633 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12634 X86::OR32rr, X86::OR32rr,
12635 X86::OR32ri, X86::OR32ri,
12637 case X86::ATOMXOR6432:
12638 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12639 X86::XOR32rr, X86::XOR32rr,
12640 X86::XOR32ri, X86::XOR32ri,
12642 case X86::ATOMNAND6432:
12643 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12644 X86::AND32rr, X86::AND32rr,
12645 X86::AND32ri, X86::AND32ri,
12647 case X86::ATOMADD6432:
12648 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12649 X86::ADD32rr, X86::ADC32rr,
12650 X86::ADD32ri, X86::ADC32ri,
12652 case X86::ATOMSUB6432:
12653 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12654 X86::SUB32rr, X86::SBB32rr,
12655 X86::SUB32ri, X86::SBB32ri,
12657 case X86::ATOMSWAP6432:
12658 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12659 X86::MOV32rr, X86::MOV32rr,
12660 X86::MOV32ri, X86::MOV32ri,
12662 case X86::VASTART_SAVE_XMM_REGS:
12663 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12665 case X86::VAARG_64:
12666 return EmitVAARG64WithCustomInserter(MI, BB);
12670 //===----------------------------------------------------------------------===//
12671 // X86 Optimization Hooks
12672 //===----------------------------------------------------------------------===//
12674 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12678 const SelectionDAG &DAG,
12679 unsigned Depth) const {
12680 unsigned Opc = Op.getOpcode();
12681 assert((Opc >= ISD::BUILTIN_OP_END ||
12682 Opc == ISD::INTRINSIC_WO_CHAIN ||
12683 Opc == ISD::INTRINSIC_W_CHAIN ||
12684 Opc == ISD::INTRINSIC_VOID) &&
12685 "Should use MaskedValueIsZero if you don't know whether Op"
12686 " is a target node!");
12688 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12702 // These nodes' second result is a boolean.
12703 if (Op.getResNo() == 0)
12706 case X86ISD::SETCC:
12707 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12708 Mask.getBitWidth() - 1);
12710 case ISD::INTRINSIC_WO_CHAIN: {
12711 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12712 unsigned NumLoBits = 0;
12715 case Intrinsic::x86_sse_movmsk_ps:
12716 case Intrinsic::x86_avx_movmsk_ps_256:
12717 case Intrinsic::x86_sse2_movmsk_pd:
12718 case Intrinsic::x86_avx_movmsk_pd_256:
12719 case Intrinsic::x86_mmx_pmovmskb:
12720 case Intrinsic::x86_sse2_pmovmskb_128:
12721 case Intrinsic::x86_avx2_pmovmskb: {
12722 // High bits of movmskp{s|d}, pmovmskb are known zero.
12724 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12725 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12726 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12727 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12728 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12729 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12730 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12732 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12733 Mask.getBitWidth() - NumLoBits);
12742 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12743 unsigned Depth) const {
12744 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12745 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12746 return Op.getValueType().getScalarType().getSizeInBits();
12752 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12753 /// node is a GlobalAddress + offset.
12754 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12755 const GlobalValue* &GA,
12756 int64_t &Offset) const {
12757 if (N->getOpcode() == X86ISD::Wrapper) {
12758 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12759 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12760 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12764 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12767 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12768 /// same as extracting the high 128-bit part of 256-bit vector and then
12769 /// inserting the result into the low part of a new 256-bit vector
12770 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12771 EVT VT = SVOp->getValueType(0);
12772 int NumElems = VT.getVectorNumElements();
12774 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12775 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12776 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12777 SVOp->getMaskElt(j) >= 0)
12783 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12784 /// same as extracting the low 128-bit part of 256-bit vector and then
12785 /// inserting the result into the high part of a new 256-bit vector
12786 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12787 EVT VT = SVOp->getValueType(0);
12788 int NumElems = VT.getVectorNumElements();
12790 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12791 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12792 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12793 SVOp->getMaskElt(j) >= 0)
12799 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12800 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12801 TargetLowering::DAGCombinerInfo &DCI,
12803 DebugLoc dl = N->getDebugLoc();
12804 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12805 SDValue V1 = SVOp->getOperand(0);
12806 SDValue V2 = SVOp->getOperand(1);
12807 EVT VT = SVOp->getValueType(0);
12808 int NumElems = VT.getVectorNumElements();
12810 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12811 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12815 // V UNDEF BUILD_VECTOR UNDEF
12817 // CONCAT_VECTOR CONCAT_VECTOR
12820 // RESULT: V + zero extended
12822 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12823 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12824 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12827 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12830 // To match the shuffle mask, the first half of the mask should
12831 // be exactly the first vector, and all the rest a splat with the
12832 // first element of the second one.
12833 for (int i = 0; i < NumElems/2; ++i)
12834 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12835 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12838 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12839 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12840 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12841 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12843 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12845 Ld->getPointerInfo(),
12846 Ld->getAlignment(),
12847 false/*isVolatile*/, true/*ReadMem*/,
12848 false/*WriteMem*/);
12849 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12852 // Emit a zeroed vector and insert the desired subvector on its
12854 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, HasAVX2, DAG, dl);
12855 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12856 DAG.getConstant(0, MVT::i32), DAG, dl);
12857 return DCI.CombineTo(N, InsV);
12860 //===--------------------------------------------------------------------===//
12861 // Combine some shuffles into subvector extracts and inserts:
12864 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12865 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12866 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12868 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12869 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12870 return DCI.CombineTo(N, InsV);
12873 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12874 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12875 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12876 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12877 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12878 return DCI.CombineTo(N, InsV);
12884 /// PerformShuffleCombine - Performs several different shuffle combines.
12885 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12886 TargetLowering::DAGCombinerInfo &DCI,
12887 const X86Subtarget *Subtarget) {
12888 DebugLoc dl = N->getDebugLoc();
12889 EVT VT = N->getValueType(0);
12891 // Don't create instructions with illegal types after legalize types has run.
12892 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12893 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12896 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12897 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12898 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12899 return PerformShuffleCombine256(N, DAG, DCI, Subtarget->hasAVX2());
12901 // Only handle 128 wide vector from here on.
12902 if (VT.getSizeInBits() != 128)
12905 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12906 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12907 // consecutive, non-overlapping, and in the right order.
12908 SmallVector<SDValue, 16> Elts;
12909 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12910 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12912 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12916 /// PerformTruncateCombine - Converts truncate operation to
12917 /// a sequence of vector shuffle operations.
12918 /// It is possible when we truncate 256-bit vector to 128-bit vector
12920 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12921 DAGCombinerInfo &DCI) const {
12922 if (!DCI.isBeforeLegalizeOps())
12925 if (!Subtarget->hasAVX()) return SDValue();
12927 EVT VT = N->getValueType(0);
12928 SDValue Op = N->getOperand(0);
12929 EVT OpVT = Op.getValueType();
12930 DebugLoc dl = N->getDebugLoc();
12932 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
12934 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12935 DAG.getIntPtrConstant(0));
12937 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12938 DAG.getIntPtrConstant(2));
12940 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12941 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12944 SmallVector<int,4> ShufMask1;
12945 ShufMask1.push_back(0);
12946 ShufMask1.push_back(2);
12947 ShufMask1.push_back(0);
12948 ShufMask1.push_back(0);
12950 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
12952 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
12956 SmallVector<int,4> ShufMask2;
12957 ShufMask2.push_back(0);
12958 ShufMask2.push_back(1);
12959 ShufMask2.push_back(4);
12960 ShufMask2.push_back(5);
12962 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2.data());
12964 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
12966 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12967 DAG.getIntPtrConstant(0));
12969 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12970 DAG.getIntPtrConstant(4));
12972 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
12973 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
12976 SmallVector<int,16> ShufMask1;
12977 ShufMask1.push_back(0x0);
12978 ShufMask1.push_back(0x1);
12979 ShufMask1.push_back(0x4);
12980 ShufMask1.push_back(0x5);
12981 ShufMask1.push_back(0x8);
12982 ShufMask1.push_back(0x9);
12983 ShufMask1.push_back(0xc);
12984 ShufMask1.push_back(0xd);
12985 for (unsigned i=0; i<8; ++i)
12986 ShufMask1.push_back(-1);
12988 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
12989 DAG.getUNDEF(MVT::v16i8),
12991 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
12992 DAG.getUNDEF(MVT::v16i8),
12995 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12996 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12999 SmallVector<int,4> ShufMask2;
13000 ShufMask2.push_back(0);
13001 ShufMask2.push_back(1);
13002 ShufMask2.push_back(4);
13003 ShufMask2.push_back(5);
13005 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2.data());
13006 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13013 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13014 /// generation and convert it from being a bunch of shuffles and extracts
13015 /// to a simple store and scalar loads to extract the elements.
13016 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13017 const TargetLowering &TLI) {
13018 SDValue InputVector = N->getOperand(0);
13020 // Only operate on vectors of 4 elements, where the alternative shuffling
13021 // gets to be more expensive.
13022 if (InputVector.getValueType() != MVT::v4i32)
13025 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13026 // single use which is a sign-extend or zero-extend, and all elements are
13028 SmallVector<SDNode *, 4> Uses;
13029 unsigned ExtractedElements = 0;
13030 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13031 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13032 if (UI.getUse().getResNo() != InputVector.getResNo())
13035 SDNode *Extract = *UI;
13036 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13039 if (Extract->getValueType(0) != MVT::i32)
13041 if (!Extract->hasOneUse())
13043 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13044 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13046 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13049 // Record which element was extracted.
13050 ExtractedElements |=
13051 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13053 Uses.push_back(Extract);
13056 // If not all the elements were used, this may not be worthwhile.
13057 if (ExtractedElements != 15)
13060 // Ok, we've now decided to do the transformation.
13061 DebugLoc dl = InputVector.getDebugLoc();
13063 // Store the value to a temporary stack slot.
13064 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13065 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13066 MachinePointerInfo(), false, false, 0);
13068 // Replace each use (extract) with a load of the appropriate element.
13069 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13070 UE = Uses.end(); UI != UE; ++UI) {
13071 SDNode *Extract = *UI;
13073 // cOMpute the element's address.
13074 SDValue Idx = Extract->getOperand(1);
13076 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13077 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13078 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13080 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13081 StackPtr, OffsetVal);
13083 // Load the scalar.
13084 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13085 ScalarAddr, MachinePointerInfo(),
13086 false, false, false, 0);
13088 // Replace the exact with the load.
13089 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13092 // The replacement was made in place; don't return anything.
13096 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13098 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13099 TargetLowering::DAGCombinerInfo &DCI,
13100 const X86Subtarget *Subtarget) {
13101 DebugLoc DL = N->getDebugLoc();
13102 SDValue Cond = N->getOperand(0);
13103 // Get the LHS/RHS of the select.
13104 SDValue LHS = N->getOperand(1);
13105 SDValue RHS = N->getOperand(2);
13106 EVT VT = LHS.getValueType();
13108 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13109 // instructions match the semantics of the common C idiom x<y?x:y but not
13110 // x<=y?x:y, because of how they handle negative zero (which can be
13111 // ignored in unsafe-math mode).
13112 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13113 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13114 (Subtarget->hasSSE2() ||
13115 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13116 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13118 unsigned Opcode = 0;
13119 // Check for x CC y ? x : y.
13120 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13121 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13125 // Converting this to a min would handle NaNs incorrectly, and swapping
13126 // the operands would cause it to handle comparisons between positive
13127 // and negative zero incorrectly.
13128 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13129 if (!DAG.getTarget().Options.UnsafeFPMath &&
13130 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13132 std::swap(LHS, RHS);
13134 Opcode = X86ISD::FMIN;
13137 // Converting this to a min would handle comparisons between positive
13138 // and negative zero incorrectly.
13139 if (!DAG.getTarget().Options.UnsafeFPMath &&
13140 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13142 Opcode = X86ISD::FMIN;
13145 // Converting this to a min would handle both negative zeros and NaNs
13146 // incorrectly, but we can swap the operands to fix both.
13147 std::swap(LHS, RHS);
13151 Opcode = X86ISD::FMIN;
13155 // Converting this to a max would handle comparisons between positive
13156 // and negative zero incorrectly.
13157 if (!DAG.getTarget().Options.UnsafeFPMath &&
13158 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13160 Opcode = X86ISD::FMAX;
13163 // Converting this to a max would handle NaNs incorrectly, and swapping
13164 // the operands would cause it to handle comparisons between positive
13165 // and negative zero incorrectly.
13166 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13167 if (!DAG.getTarget().Options.UnsafeFPMath &&
13168 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13170 std::swap(LHS, RHS);
13172 Opcode = X86ISD::FMAX;
13175 // Converting this to a max would handle both negative zeros and NaNs
13176 // incorrectly, but we can swap the operands to fix both.
13177 std::swap(LHS, RHS);
13181 Opcode = X86ISD::FMAX;
13184 // Check for x CC y ? y : x -- a min/max with reversed arms.
13185 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13186 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13190 // Converting this to a min would handle comparisons between positive
13191 // and negative zero incorrectly, and swapping the operands would
13192 // cause it to handle NaNs incorrectly.
13193 if (!DAG.getTarget().Options.UnsafeFPMath &&
13194 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13195 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13197 std::swap(LHS, RHS);
13199 Opcode = X86ISD::FMIN;
13202 // Converting this to a min would handle NaNs incorrectly.
13203 if (!DAG.getTarget().Options.UnsafeFPMath &&
13204 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13206 Opcode = X86ISD::FMIN;
13209 // Converting this to a min would handle both negative zeros and NaNs
13210 // incorrectly, but we can swap the operands to fix both.
13211 std::swap(LHS, RHS);
13215 Opcode = X86ISD::FMIN;
13219 // Converting this to a max would handle NaNs incorrectly.
13220 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13222 Opcode = X86ISD::FMAX;
13225 // Converting this to a max would handle comparisons between positive
13226 // and negative zero incorrectly, and swapping the operands would
13227 // cause it to handle NaNs incorrectly.
13228 if (!DAG.getTarget().Options.UnsafeFPMath &&
13229 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13230 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13232 std::swap(LHS, RHS);
13234 Opcode = X86ISD::FMAX;
13237 // Converting this to a max would handle both negative zeros and NaNs
13238 // incorrectly, but we can swap the operands to fix both.
13239 std::swap(LHS, RHS);
13243 Opcode = X86ISD::FMAX;
13249 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13252 // If this is a select between two integer constants, try to do some
13254 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13255 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13256 // Don't do this for crazy integer types.
13257 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13258 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13259 // so that TrueC (the true value) is larger than FalseC.
13260 bool NeedsCondInvert = false;
13262 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13263 // Efficiently invertible.
13264 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13265 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13266 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13267 NeedsCondInvert = true;
13268 std::swap(TrueC, FalseC);
13271 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13272 if (FalseC->getAPIntValue() == 0 &&
13273 TrueC->getAPIntValue().isPowerOf2()) {
13274 if (NeedsCondInvert) // Invert the condition if needed.
13275 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13276 DAG.getConstant(1, Cond.getValueType()));
13278 // Zero extend the condition if needed.
13279 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13281 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13282 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13283 DAG.getConstant(ShAmt, MVT::i8));
13286 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13287 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13288 if (NeedsCondInvert) // Invert the condition if needed.
13289 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13290 DAG.getConstant(1, Cond.getValueType()));
13292 // Zero extend the condition if needed.
13293 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13294 FalseC->getValueType(0), Cond);
13295 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13296 SDValue(FalseC, 0));
13299 // Optimize cases that will turn into an LEA instruction. This requires
13300 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13301 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13302 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13303 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13305 bool isFastMultiplier = false;
13307 switch ((unsigned char)Diff) {
13309 case 1: // result = add base, cond
13310 case 2: // result = lea base( , cond*2)
13311 case 3: // result = lea base(cond, cond*2)
13312 case 4: // result = lea base( , cond*4)
13313 case 5: // result = lea base(cond, cond*4)
13314 case 8: // result = lea base( , cond*8)
13315 case 9: // result = lea base(cond, cond*8)
13316 isFastMultiplier = true;
13321 if (isFastMultiplier) {
13322 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13323 if (NeedsCondInvert) // Invert the condition if needed.
13324 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13325 DAG.getConstant(1, Cond.getValueType()));
13327 // Zero extend the condition if needed.
13328 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13330 // Scale the condition by the difference.
13332 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13333 DAG.getConstant(Diff, Cond.getValueType()));
13335 // Add the base if non-zero.
13336 if (FalseC->getAPIntValue() != 0)
13337 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13338 SDValue(FalseC, 0));
13345 // Canonicalize max and min:
13346 // (x > y) ? x : y -> (x >= y) ? x : y
13347 // (x < y) ? x : y -> (x <= y) ? x : y
13348 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13349 // the need for an extra compare
13350 // against zero. e.g.
13351 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13353 // testl %edi, %edi
13355 // cmovgl %edi, %eax
13359 // cmovsl %eax, %edi
13360 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13361 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13362 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13363 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13368 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13369 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13370 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13371 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13376 // If we know that this node is legal then we know that it is going to be
13377 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13378 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13379 // to simplify previous instructions.
13380 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13381 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13382 !DCI.isBeforeLegalize() &&
13383 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13384 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13385 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13386 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13388 APInt KnownZero, KnownOne;
13389 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13390 DCI.isBeforeLegalizeOps());
13391 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13392 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13393 DCI.CommitTargetLoweringOpt(TLO);
13399 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13400 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13401 TargetLowering::DAGCombinerInfo &DCI) {
13402 DebugLoc DL = N->getDebugLoc();
13404 // If the flag operand isn't dead, don't touch this CMOV.
13405 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13408 SDValue FalseOp = N->getOperand(0);
13409 SDValue TrueOp = N->getOperand(1);
13410 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13411 SDValue Cond = N->getOperand(3);
13412 if (CC == X86::COND_E || CC == X86::COND_NE) {
13413 switch (Cond.getOpcode()) {
13417 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13418 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13419 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13423 // If this is a select between two integer constants, try to do some
13424 // optimizations. Note that the operands are ordered the opposite of SELECT
13426 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13427 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13428 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13429 // larger than FalseC (the false value).
13430 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13431 CC = X86::GetOppositeBranchCondition(CC);
13432 std::swap(TrueC, FalseC);
13435 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13436 // This is efficient for any integer data type (including i8/i16) and
13438 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13439 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13440 DAG.getConstant(CC, MVT::i8), Cond);
13442 // Zero extend the condition if needed.
13443 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13445 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13446 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13447 DAG.getConstant(ShAmt, MVT::i8));
13448 if (N->getNumValues() == 2) // Dead flag value?
13449 return DCI.CombineTo(N, Cond, SDValue());
13453 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13454 // for any integer data type, including i8/i16.
13455 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13456 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13457 DAG.getConstant(CC, MVT::i8), Cond);
13459 // Zero extend the condition if needed.
13460 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13461 FalseC->getValueType(0), Cond);
13462 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13463 SDValue(FalseC, 0));
13465 if (N->getNumValues() == 2) // Dead flag value?
13466 return DCI.CombineTo(N, Cond, SDValue());
13470 // Optimize cases that will turn into an LEA instruction. This requires
13471 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13472 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13473 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13474 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13476 bool isFastMultiplier = false;
13478 switch ((unsigned char)Diff) {
13480 case 1: // result = add base, cond
13481 case 2: // result = lea base( , cond*2)
13482 case 3: // result = lea base(cond, cond*2)
13483 case 4: // result = lea base( , cond*4)
13484 case 5: // result = lea base(cond, cond*4)
13485 case 8: // result = lea base( , cond*8)
13486 case 9: // result = lea base(cond, cond*8)
13487 isFastMultiplier = true;
13492 if (isFastMultiplier) {
13493 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13494 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13495 DAG.getConstant(CC, MVT::i8), Cond);
13496 // Zero extend the condition if needed.
13497 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13499 // Scale the condition by the difference.
13501 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13502 DAG.getConstant(Diff, Cond.getValueType()));
13504 // Add the base if non-zero.
13505 if (FalseC->getAPIntValue() != 0)
13506 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13507 SDValue(FalseC, 0));
13508 if (N->getNumValues() == 2) // Dead flag value?
13509 return DCI.CombineTo(N, Cond, SDValue());
13519 /// PerformMulCombine - Optimize a single multiply with constant into two
13520 /// in order to implement it with two cheaper instructions, e.g.
13521 /// LEA + SHL, LEA + LEA.
13522 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13523 TargetLowering::DAGCombinerInfo &DCI) {
13524 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13527 EVT VT = N->getValueType(0);
13528 if (VT != MVT::i64)
13531 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13534 uint64_t MulAmt = C->getZExtValue();
13535 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13538 uint64_t MulAmt1 = 0;
13539 uint64_t MulAmt2 = 0;
13540 if ((MulAmt % 9) == 0) {
13542 MulAmt2 = MulAmt / 9;
13543 } else if ((MulAmt % 5) == 0) {
13545 MulAmt2 = MulAmt / 5;
13546 } else if ((MulAmt % 3) == 0) {
13548 MulAmt2 = MulAmt / 3;
13551 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13552 DebugLoc DL = N->getDebugLoc();
13554 if (isPowerOf2_64(MulAmt2) &&
13555 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13556 // If second multiplifer is pow2, issue it first. We want the multiply by
13557 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13559 std::swap(MulAmt1, MulAmt2);
13562 if (isPowerOf2_64(MulAmt1))
13563 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13564 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13566 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13567 DAG.getConstant(MulAmt1, VT));
13569 if (isPowerOf2_64(MulAmt2))
13570 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13571 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13573 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13574 DAG.getConstant(MulAmt2, VT));
13576 // Do not add new nodes to DAG combiner worklist.
13577 DCI.CombineTo(N, NewMul, false);
13582 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13583 SDValue N0 = N->getOperand(0);
13584 SDValue N1 = N->getOperand(1);
13585 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13586 EVT VT = N0.getValueType();
13588 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13589 // since the result of setcc_c is all zero's or all ones.
13590 if (VT.isInteger() && !VT.isVector() &&
13591 N1C && N0.getOpcode() == ISD::AND &&
13592 N0.getOperand(1).getOpcode() == ISD::Constant) {
13593 SDValue N00 = N0.getOperand(0);
13594 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13595 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13596 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13597 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13598 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13599 APInt ShAmt = N1C->getAPIntValue();
13600 Mask = Mask.shl(ShAmt);
13602 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13603 N00, DAG.getConstant(Mask, VT));
13608 // Hardware support for vector shifts is sparse which makes us scalarize the
13609 // vector operations in many cases. Also, on sandybridge ADD is faster than
13611 // (shl V, 1) -> add V,V
13612 if (isSplatVector(N1.getNode())) {
13613 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13615 // We shift all of the values by one. In many cases we do not have
13616 // hardware support for this operation. This is better expressed as an ADD
13618 if (N1C && (1 == N1C->getZExtValue())) {
13619 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13626 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13628 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13629 const X86Subtarget *Subtarget) {
13630 EVT VT = N->getValueType(0);
13631 if (N->getOpcode() == ISD::SHL) {
13632 SDValue V = PerformSHLCombine(N, DAG);
13633 if (V.getNode()) return V;
13636 // On X86 with SSE2 support, we can transform this to a vector shift if
13637 // all elements are shifted by the same amount. We can't do this in legalize
13638 // because the a constant vector is typically transformed to a constant pool
13639 // so we have no knowledge of the shift amount.
13640 if (!Subtarget->hasSSE2())
13643 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13644 (!Subtarget->hasAVX2() ||
13645 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13648 SDValue ShAmtOp = N->getOperand(1);
13649 EVT EltVT = VT.getVectorElementType();
13650 DebugLoc DL = N->getDebugLoc();
13651 SDValue BaseShAmt = SDValue();
13652 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13653 unsigned NumElts = VT.getVectorNumElements();
13655 for (; i != NumElts; ++i) {
13656 SDValue Arg = ShAmtOp.getOperand(i);
13657 if (Arg.getOpcode() == ISD::UNDEF) continue;
13661 // Handle the case where the build_vector is all undef
13662 // FIXME: Should DAG allow this?
13666 for (; i != NumElts; ++i) {
13667 SDValue Arg = ShAmtOp.getOperand(i);
13668 if (Arg.getOpcode() == ISD::UNDEF) continue;
13669 if (Arg != BaseShAmt) {
13673 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13674 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13675 SDValue InVec = ShAmtOp.getOperand(0);
13676 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13677 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13679 for (; i != NumElts; ++i) {
13680 SDValue Arg = InVec.getOperand(i);
13681 if (Arg.getOpcode() == ISD::UNDEF) continue;
13685 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13686 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13687 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13688 if (C->getZExtValue() == SplatIdx)
13689 BaseShAmt = InVec.getOperand(1);
13692 if (BaseShAmt.getNode() == 0)
13693 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13694 DAG.getIntPtrConstant(0));
13698 // The shift amount is an i32.
13699 if (EltVT.bitsGT(MVT::i32))
13700 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13701 else if (EltVT.bitsLT(MVT::i32))
13702 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13704 // The shift amount is identical so we can do a vector shift.
13705 SDValue ValOp = N->getOperand(0);
13706 switch (N->getOpcode()) {
13708 llvm_unreachable("Unknown shift opcode!");
13710 switch (VT.getSimpleVT().SimpleTy) {
13711 default: return SDValue();
13718 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13721 switch (VT.getSimpleVT().SimpleTy) {
13722 default: return SDValue();
13727 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13730 switch (VT.getSimpleVT().SimpleTy) {
13731 default: return SDValue();
13738 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13744 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13745 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13746 // and friends. Likewise for OR -> CMPNEQSS.
13747 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13748 TargetLowering::DAGCombinerInfo &DCI,
13749 const X86Subtarget *Subtarget) {
13752 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13753 // we're requiring SSE2 for both.
13754 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13755 SDValue N0 = N->getOperand(0);
13756 SDValue N1 = N->getOperand(1);
13757 SDValue CMP0 = N0->getOperand(1);
13758 SDValue CMP1 = N1->getOperand(1);
13759 DebugLoc DL = N->getDebugLoc();
13761 // The SETCCs should both refer to the same CMP.
13762 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13765 SDValue CMP00 = CMP0->getOperand(0);
13766 SDValue CMP01 = CMP0->getOperand(1);
13767 EVT VT = CMP00.getValueType();
13769 if (VT == MVT::f32 || VT == MVT::f64) {
13770 bool ExpectingFlags = false;
13771 // Check for any users that want flags:
13772 for (SDNode::use_iterator UI = N->use_begin(),
13774 !ExpectingFlags && UI != UE; ++UI)
13775 switch (UI->getOpcode()) {
13780 ExpectingFlags = true;
13782 case ISD::CopyToReg:
13783 case ISD::SIGN_EXTEND:
13784 case ISD::ZERO_EXTEND:
13785 case ISD::ANY_EXTEND:
13789 if (!ExpectingFlags) {
13790 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13791 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13793 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13794 X86::CondCode tmp = cc0;
13799 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13800 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13801 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13802 X86ISD::NodeType NTOperator = is64BitFP ?
13803 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13804 // FIXME: need symbolic constants for these magic numbers.
13805 // See X86ATTInstPrinter.cpp:printSSECC().
13806 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13807 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13808 DAG.getConstant(x86cc, MVT::i8));
13809 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13811 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13812 DAG.getConstant(1, MVT::i32));
13813 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13814 return OneBitOfTruth;
13822 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13823 /// so it can be folded inside ANDNP.
13824 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13825 EVT VT = N->getValueType(0);
13827 // Match direct AllOnes for 128 and 256-bit vectors
13828 if (ISD::isBuildVectorAllOnes(N))
13831 // Look through a bit convert.
13832 if (N->getOpcode() == ISD::BITCAST)
13833 N = N->getOperand(0).getNode();
13835 // Sometimes the operand may come from a insert_subvector building a 256-bit
13837 if (VT.getSizeInBits() == 256 &&
13838 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13839 SDValue V1 = N->getOperand(0);
13840 SDValue V2 = N->getOperand(1);
13842 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13843 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13844 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13845 ISD::isBuildVectorAllOnes(V2.getNode()))
13852 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13853 TargetLowering::DAGCombinerInfo &DCI,
13854 const X86Subtarget *Subtarget) {
13855 if (DCI.isBeforeLegalizeOps())
13858 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13862 EVT VT = N->getValueType(0);
13864 // Create ANDN, BLSI, and BLSR instructions
13865 // BLSI is X & (-X)
13866 // BLSR is X & (X-1)
13867 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13868 SDValue N0 = N->getOperand(0);
13869 SDValue N1 = N->getOperand(1);
13870 DebugLoc DL = N->getDebugLoc();
13872 // Check LHS for not
13873 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13874 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13875 // Check RHS for not
13876 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13877 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13879 // Check LHS for neg
13880 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13881 isZero(N0.getOperand(0)))
13882 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13884 // Check RHS for neg
13885 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13886 isZero(N1.getOperand(0)))
13887 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13889 // Check LHS for X-1
13890 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13891 isAllOnes(N0.getOperand(1)))
13892 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13894 // Check RHS for X-1
13895 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13896 isAllOnes(N1.getOperand(1)))
13897 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13902 // Want to form ANDNP nodes:
13903 // 1) In the hopes of then easily combining them with OR and AND nodes
13904 // to form PBLEND/PSIGN.
13905 // 2) To match ANDN packed intrinsics
13906 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13909 SDValue N0 = N->getOperand(0);
13910 SDValue N1 = N->getOperand(1);
13911 DebugLoc DL = N->getDebugLoc();
13913 // Check LHS for vnot
13914 if (N0.getOpcode() == ISD::XOR &&
13915 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13916 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13917 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13919 // Check RHS for vnot
13920 if (N1.getOpcode() == ISD::XOR &&
13921 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13922 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13923 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13928 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13929 TargetLowering::DAGCombinerInfo &DCI,
13930 const X86Subtarget *Subtarget) {
13931 if (DCI.isBeforeLegalizeOps())
13934 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13938 EVT VT = N->getValueType(0);
13940 SDValue N0 = N->getOperand(0);
13941 SDValue N1 = N->getOperand(1);
13943 // look for psign/blend
13944 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13945 if (!Subtarget->hasSSSE3() ||
13946 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13949 // Canonicalize pandn to RHS
13950 if (N0.getOpcode() == X86ISD::ANDNP)
13952 // or (and (m, y), (pandn m, x))
13953 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13954 SDValue Mask = N1.getOperand(0);
13955 SDValue X = N1.getOperand(1);
13957 if (N0.getOperand(0) == Mask)
13958 Y = N0.getOperand(1);
13959 if (N0.getOperand(1) == Mask)
13960 Y = N0.getOperand(0);
13962 // Check to see if the mask appeared in both the AND and ANDNP and
13966 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13967 if (Mask.getOpcode() != ISD::BITCAST ||
13968 X.getOpcode() != ISD::BITCAST ||
13969 Y.getOpcode() != ISD::BITCAST)
13972 // Look through mask bitcast.
13973 Mask = Mask.getOperand(0);
13974 EVT MaskVT = Mask.getValueType();
13976 // Validate that the Mask operand is a vector sra node.
13977 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13978 // there is no psrai.b
13979 if (Mask.getOpcode() != X86ISD::VSRAI)
13982 // Check that the SRA is all signbits.
13983 SDValue SraC = Mask.getOperand(1);
13984 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13985 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13986 if ((SraAmt + 1) != EltBits)
13989 DebugLoc DL = N->getDebugLoc();
13991 // Now we know we at least have a plendvb with the mask val. See if
13992 // we can form a psignb/w/d.
13993 // psign = x.type == y.type == mask.type && y = sub(0, x);
13994 X = X.getOperand(0);
13995 Y = Y.getOperand(0);
13996 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13997 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13998 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
13999 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14000 "Unsupported VT for PSIGN");
14001 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14002 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14004 // PBLENDVB only available on SSE 4.1
14005 if (!Subtarget->hasSSE41())
14008 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14010 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14011 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14012 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14013 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14014 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14018 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14021 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14022 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14024 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14026 if (!N0.hasOneUse() || !N1.hasOneUse())
14029 SDValue ShAmt0 = N0.getOperand(1);
14030 if (ShAmt0.getValueType() != MVT::i8)
14032 SDValue ShAmt1 = N1.getOperand(1);
14033 if (ShAmt1.getValueType() != MVT::i8)
14035 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14036 ShAmt0 = ShAmt0.getOperand(0);
14037 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14038 ShAmt1 = ShAmt1.getOperand(0);
14040 DebugLoc DL = N->getDebugLoc();
14041 unsigned Opc = X86ISD::SHLD;
14042 SDValue Op0 = N0.getOperand(0);
14043 SDValue Op1 = N1.getOperand(0);
14044 if (ShAmt0.getOpcode() == ISD::SUB) {
14045 Opc = X86ISD::SHRD;
14046 std::swap(Op0, Op1);
14047 std::swap(ShAmt0, ShAmt1);
14050 unsigned Bits = VT.getSizeInBits();
14051 if (ShAmt1.getOpcode() == ISD::SUB) {
14052 SDValue Sum = ShAmt1.getOperand(0);
14053 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14054 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14055 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14056 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14057 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14058 return DAG.getNode(Opc, DL, VT,
14060 DAG.getNode(ISD::TRUNCATE, DL,
14063 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14064 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14066 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14067 return DAG.getNode(Opc, DL, VT,
14068 N0.getOperand(0), N1.getOperand(0),
14069 DAG.getNode(ISD::TRUNCATE, DL,
14076 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14077 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14078 TargetLowering::DAGCombinerInfo &DCI,
14079 const X86Subtarget *Subtarget) {
14080 if (DCI.isBeforeLegalizeOps())
14083 EVT VT = N->getValueType(0);
14085 if (VT != MVT::i32 && VT != MVT::i64)
14088 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14090 // Create BLSMSK instructions by finding X ^ (X-1)
14091 SDValue N0 = N->getOperand(0);
14092 SDValue N1 = N->getOperand(1);
14093 DebugLoc DL = N->getDebugLoc();
14095 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14096 isAllOnes(N0.getOperand(1)))
14097 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14099 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14100 isAllOnes(N1.getOperand(1)))
14101 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14106 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14107 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14108 const X86Subtarget *Subtarget) {
14109 LoadSDNode *Ld = cast<LoadSDNode>(N);
14110 EVT RegVT = Ld->getValueType(0);
14111 EVT MemVT = Ld->getMemoryVT();
14112 DebugLoc dl = Ld->getDebugLoc();
14113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14115 ISD::LoadExtType Ext = Ld->getExtensionType();
14117 // If this is a vector EXT Load then attempt to optimize it using a
14118 // shuffle. We need SSE4 for the shuffles.
14119 // TODO: It is possible to support ZExt by zeroing the undef values
14120 // during the shuffle phase or after the shuffle.
14121 if (RegVT.isVector() && RegVT.isInteger() &&
14122 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14123 assert(MemVT != RegVT && "Cannot extend to the same type");
14124 assert(MemVT.isVector() && "Must load a vector from memory");
14126 unsigned NumElems = RegVT.getVectorNumElements();
14127 unsigned RegSz = RegVT.getSizeInBits();
14128 unsigned MemSz = MemVT.getSizeInBits();
14129 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14130 // All sizes must be a power of two
14131 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14133 // Attempt to load the original value using a single load op.
14134 // Find a scalar type which is equal to the loaded word size.
14135 MVT SclrLoadTy = MVT::i8;
14136 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14137 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14138 MVT Tp = (MVT::SimpleValueType)tp;
14139 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14145 // Proceed if a load word is found.
14146 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14148 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14149 RegSz/SclrLoadTy.getSizeInBits());
14151 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14152 RegSz/MemVT.getScalarType().getSizeInBits());
14153 // Can't shuffle using an illegal type.
14154 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14156 // Perform a single load.
14157 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14159 Ld->getPointerInfo(), Ld->isVolatile(),
14160 Ld->isNonTemporal(), Ld->isInvariant(),
14161 Ld->getAlignment());
14163 // Insert the word loaded into a vector.
14164 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14165 LoadUnitVecVT, ScalarLoad);
14167 // Bitcast the loaded value to a vector of the original element type, in
14168 // the size of the target vector type.
14169 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14171 unsigned SizeRatio = RegSz/MemSz;
14173 // Redistribute the loaded elements into the different locations.
14174 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14175 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14177 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14178 DAG.getUNDEF(SlicedVec.getValueType()),
14179 ShuffleVec.data());
14181 // Bitcast to the requested type.
14182 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14183 // Replace the original load with the new sequence
14184 // and return the new chain.
14185 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14186 return SDValue(ScalarLoad.getNode(), 1);
14192 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14193 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14194 const X86Subtarget *Subtarget) {
14195 StoreSDNode *St = cast<StoreSDNode>(N);
14196 EVT VT = St->getValue().getValueType();
14197 EVT StVT = St->getMemoryVT();
14198 DebugLoc dl = St->getDebugLoc();
14199 SDValue StoredVal = St->getOperand(1);
14200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14202 // If we are saving a concatenation of two XMM registers, perform two stores.
14203 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14204 // 128-bit ones. If in the future the cost becomes only one memory access the
14205 // first version would be better.
14206 if (VT.getSizeInBits() == 256 &&
14207 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14208 StoredVal.getNumOperands() == 2) {
14210 SDValue Value0 = StoredVal.getOperand(0);
14211 SDValue Value1 = StoredVal.getOperand(1);
14213 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14214 SDValue Ptr0 = St->getBasePtr();
14215 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14217 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14218 St->getPointerInfo(), St->isVolatile(),
14219 St->isNonTemporal(), St->getAlignment());
14220 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14221 St->getPointerInfo(), St->isVolatile(),
14222 St->isNonTemporal(), St->getAlignment());
14223 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14226 // Optimize trunc store (of multiple scalars) to shuffle and store.
14227 // First, pack all of the elements in one place. Next, store to memory
14228 // in fewer chunks.
14229 if (St->isTruncatingStore() && VT.isVector()) {
14230 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14231 unsigned NumElems = VT.getVectorNumElements();
14232 assert(StVT != VT && "Cannot truncate to the same type");
14233 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14234 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14236 // From, To sizes and ElemCount must be pow of two
14237 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14238 // We are going to use the original vector elt for storing.
14239 // Accumulated smaller vector elements must be a multiple of the store size.
14240 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14242 unsigned SizeRatio = FromSz / ToSz;
14244 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14246 // Create a type on which we perform the shuffle
14247 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14248 StVT.getScalarType(), NumElems*SizeRatio);
14250 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14252 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14253 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14254 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14256 // Can't shuffle using an illegal type
14257 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14259 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14260 DAG.getUNDEF(WideVec.getValueType()),
14261 ShuffleVec.data());
14262 // At this point all of the data is stored at the bottom of the
14263 // register. We now need to save it to mem.
14265 // Find the largest store unit
14266 MVT StoreType = MVT::i8;
14267 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14268 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14269 MVT Tp = (MVT::SimpleValueType)tp;
14270 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14274 // Bitcast the original vector into a vector of store-size units
14275 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14276 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14277 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14278 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14279 SmallVector<SDValue, 8> Chains;
14280 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14281 TLI.getPointerTy());
14282 SDValue Ptr = St->getBasePtr();
14284 // Perform one or more big stores into memory.
14285 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14286 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14287 StoreType, ShuffWide,
14288 DAG.getIntPtrConstant(i));
14289 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14290 St->getPointerInfo(), St->isVolatile(),
14291 St->isNonTemporal(), St->getAlignment());
14292 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14293 Chains.push_back(Ch);
14296 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14301 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14302 // the FP state in cases where an emms may be missing.
14303 // A preferable solution to the general problem is to figure out the right
14304 // places to insert EMMS. This qualifies as a quick hack.
14306 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14307 if (VT.getSizeInBits() != 64)
14310 const Function *F = DAG.getMachineFunction().getFunction();
14311 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14312 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14313 && Subtarget->hasSSE2();
14314 if ((VT.isVector() ||
14315 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14316 isa<LoadSDNode>(St->getValue()) &&
14317 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14318 St->getChain().hasOneUse() && !St->isVolatile()) {
14319 SDNode* LdVal = St->getValue().getNode();
14320 LoadSDNode *Ld = 0;
14321 int TokenFactorIndex = -1;
14322 SmallVector<SDValue, 8> Ops;
14323 SDNode* ChainVal = St->getChain().getNode();
14324 // Must be a store of a load. We currently handle two cases: the load
14325 // is a direct child, and it's under an intervening TokenFactor. It is
14326 // possible to dig deeper under nested TokenFactors.
14327 if (ChainVal == LdVal)
14328 Ld = cast<LoadSDNode>(St->getChain());
14329 else if (St->getValue().hasOneUse() &&
14330 ChainVal->getOpcode() == ISD::TokenFactor) {
14331 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14332 if (ChainVal->getOperand(i).getNode() == LdVal) {
14333 TokenFactorIndex = i;
14334 Ld = cast<LoadSDNode>(St->getValue());
14336 Ops.push_back(ChainVal->getOperand(i));
14340 if (!Ld || !ISD::isNormalLoad(Ld))
14343 // If this is not the MMX case, i.e. we are just turning i64 load/store
14344 // into f64 load/store, avoid the transformation if there are multiple
14345 // uses of the loaded value.
14346 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14349 DebugLoc LdDL = Ld->getDebugLoc();
14350 DebugLoc StDL = N->getDebugLoc();
14351 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14352 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14354 if (Subtarget->is64Bit() || F64IsLegal) {
14355 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14356 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14357 Ld->getPointerInfo(), Ld->isVolatile(),
14358 Ld->isNonTemporal(), Ld->isInvariant(),
14359 Ld->getAlignment());
14360 SDValue NewChain = NewLd.getValue(1);
14361 if (TokenFactorIndex != -1) {
14362 Ops.push_back(NewChain);
14363 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14366 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14367 St->getPointerInfo(),
14368 St->isVolatile(), St->isNonTemporal(),
14369 St->getAlignment());
14372 // Otherwise, lower to two pairs of 32-bit loads / stores.
14373 SDValue LoAddr = Ld->getBasePtr();
14374 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14375 DAG.getConstant(4, MVT::i32));
14377 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14378 Ld->getPointerInfo(),
14379 Ld->isVolatile(), Ld->isNonTemporal(),
14380 Ld->isInvariant(), Ld->getAlignment());
14381 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14382 Ld->getPointerInfo().getWithOffset(4),
14383 Ld->isVolatile(), Ld->isNonTemporal(),
14385 MinAlign(Ld->getAlignment(), 4));
14387 SDValue NewChain = LoLd.getValue(1);
14388 if (TokenFactorIndex != -1) {
14389 Ops.push_back(LoLd);
14390 Ops.push_back(HiLd);
14391 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14395 LoAddr = St->getBasePtr();
14396 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14397 DAG.getConstant(4, MVT::i32));
14399 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14400 St->getPointerInfo(),
14401 St->isVolatile(), St->isNonTemporal(),
14402 St->getAlignment());
14403 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14404 St->getPointerInfo().getWithOffset(4),
14406 St->isNonTemporal(),
14407 MinAlign(St->getAlignment(), 4));
14408 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14413 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14414 /// and return the operands for the horizontal operation in LHS and RHS. A
14415 /// horizontal operation performs the binary operation on successive elements
14416 /// of its first operand, then on successive elements of its second operand,
14417 /// returning the resulting values in a vector. For example, if
14418 /// A = < float a0, float a1, float a2, float a3 >
14420 /// B = < float b0, float b1, float b2, float b3 >
14421 /// then the result of doing a horizontal operation on A and B is
14422 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14423 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14424 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14425 /// set to A, RHS to B, and the routine returns 'true'.
14426 /// Note that the binary operation should have the property that if one of the
14427 /// operands is UNDEF then the result is UNDEF.
14428 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14429 // Look for the following pattern: if
14430 // A = < float a0, float a1, float a2, float a3 >
14431 // B = < float b0, float b1, float b2, float b3 >
14433 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14434 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14435 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14436 // which is A horizontal-op B.
14438 // At least one of the operands should be a vector shuffle.
14439 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14440 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14443 EVT VT = LHS.getValueType();
14445 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14446 "Unsupported vector type for horizontal add/sub");
14448 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14449 // operate independently on 128-bit lanes.
14450 unsigned NumElts = VT.getVectorNumElements();
14451 unsigned NumLanes = VT.getSizeInBits()/128;
14452 unsigned NumLaneElts = NumElts / NumLanes;
14453 assert((NumLaneElts % 2 == 0) &&
14454 "Vector type should have an even number of elements in each lane");
14455 unsigned HalfLaneElts = NumLaneElts/2;
14457 // View LHS in the form
14458 // LHS = VECTOR_SHUFFLE A, B, LMask
14459 // If LHS is not a shuffle then pretend it is the shuffle
14460 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14461 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14464 SmallVector<int, 16> LMask(NumElts);
14465 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14466 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14467 A = LHS.getOperand(0);
14468 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14469 B = LHS.getOperand(1);
14470 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14471 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14473 if (LHS.getOpcode() != ISD::UNDEF)
14475 for (unsigned i = 0; i != NumElts; ++i)
14479 // Likewise, view RHS in the form
14480 // RHS = VECTOR_SHUFFLE C, D, RMask
14482 SmallVector<int, 16> RMask(NumElts);
14483 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14484 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14485 C = RHS.getOperand(0);
14486 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14487 D = RHS.getOperand(1);
14488 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14489 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14491 if (RHS.getOpcode() != ISD::UNDEF)
14493 for (unsigned i = 0; i != NumElts; ++i)
14497 // Check that the shuffles are both shuffling the same vectors.
14498 if (!(A == C && B == D) && !(A == D && B == C))
14501 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14502 if (!A.getNode() && !B.getNode())
14505 // If A and B occur in reverse order in RHS, then "swap" them (which means
14506 // rewriting the mask).
14508 CommuteVectorShuffleMask(RMask, NumElts);
14510 // At this point LHS and RHS are equivalent to
14511 // LHS = VECTOR_SHUFFLE A, B, LMask
14512 // RHS = VECTOR_SHUFFLE A, B, RMask
14513 // Check that the masks correspond to performing a horizontal operation.
14514 for (unsigned i = 0; i != NumElts; ++i) {
14515 int LIdx = LMask[i], RIdx = RMask[i];
14517 // Ignore any UNDEF components.
14518 if (LIdx < 0 || RIdx < 0 ||
14519 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14520 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14523 // Check that successive elements are being operated on. If not, this is
14524 // not a horizontal operation.
14525 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14526 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14527 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14528 if (!(LIdx == Index && RIdx == Index + 1) &&
14529 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14533 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14534 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14538 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14539 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14540 const X86Subtarget *Subtarget) {
14541 EVT VT = N->getValueType(0);
14542 SDValue LHS = N->getOperand(0);
14543 SDValue RHS = N->getOperand(1);
14545 // Try to synthesize horizontal adds from adds of shuffles.
14546 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14547 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14548 isHorizontalBinOp(LHS, RHS, true))
14549 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14553 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14554 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14555 const X86Subtarget *Subtarget) {
14556 EVT VT = N->getValueType(0);
14557 SDValue LHS = N->getOperand(0);
14558 SDValue RHS = N->getOperand(1);
14560 // Try to synthesize horizontal subs from subs of shuffles.
14561 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14562 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14563 isHorizontalBinOp(LHS, RHS, false))
14564 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14568 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14569 /// X86ISD::FXOR nodes.
14570 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14571 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14572 // F[X]OR(0.0, x) -> x
14573 // F[X]OR(x, 0.0) -> x
14574 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14575 if (C->getValueAPF().isPosZero())
14576 return N->getOperand(1);
14577 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14578 if (C->getValueAPF().isPosZero())
14579 return N->getOperand(0);
14583 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14584 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14585 // FAND(0.0, x) -> 0.0
14586 // FAND(x, 0.0) -> 0.0
14587 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14588 if (C->getValueAPF().isPosZero())
14589 return N->getOperand(0);
14590 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14591 if (C->getValueAPF().isPosZero())
14592 return N->getOperand(1);
14596 static SDValue PerformBTCombine(SDNode *N,
14598 TargetLowering::DAGCombinerInfo &DCI) {
14599 // BT ignores high bits in the bit index operand.
14600 SDValue Op1 = N->getOperand(1);
14601 if (Op1.hasOneUse()) {
14602 unsigned BitWidth = Op1.getValueSizeInBits();
14603 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14604 APInt KnownZero, KnownOne;
14605 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14606 !DCI.isBeforeLegalizeOps());
14607 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14608 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14609 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14610 DCI.CommitTargetLoweringOpt(TLO);
14615 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14616 SDValue Op = N->getOperand(0);
14617 if (Op.getOpcode() == ISD::BITCAST)
14618 Op = Op.getOperand(0);
14619 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14620 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14621 VT.getVectorElementType().getSizeInBits() ==
14622 OpVT.getVectorElementType().getSizeInBits()) {
14623 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14628 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14629 const X86Subtarget *Subtarget) {
14630 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14631 // (and (i32 x86isd::setcc_carry), 1)
14632 // This eliminates the zext. This transformation is necessary because
14633 // ISD::SETCC is always legalized to i8.
14634 DebugLoc dl = N->getDebugLoc();
14635 SDValue N0 = N->getOperand(0);
14636 EVT VT = N->getValueType(0);
14637 EVT OpVT = N0.getValueType();
14639 if (N0.getOpcode() == ISD::AND &&
14641 N0.getOperand(0).hasOneUse()) {
14642 SDValue N00 = N0.getOperand(0);
14643 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14645 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14646 if (!C || C->getZExtValue() != 1)
14648 return DAG.getNode(ISD::AND, dl, VT,
14649 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14650 N00.getOperand(0), N00.getOperand(1)),
14651 DAG.getConstant(1, VT));
14653 // Optimize vectors in AVX mode:
14656 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14657 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14658 // Concat upper and lower parts.
14661 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14662 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14663 // Concat upper and lower parts.
14665 if (Subtarget->hasAVX()) {
14667 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14668 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14670 SDValue ZeroVec = getZeroVector(OpVT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
14672 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14673 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14675 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14676 VT.getVectorNumElements()/2);
14678 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14679 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14681 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14689 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14690 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14691 unsigned X86CC = N->getConstantOperandVal(0);
14692 SDValue EFLAG = N->getOperand(1);
14693 DebugLoc DL = N->getDebugLoc();
14695 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14696 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14698 if (X86CC == X86::COND_B)
14699 return DAG.getNode(ISD::AND, DL, MVT::i8,
14700 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14701 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14702 DAG.getConstant(1, MVT::i8));
14707 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14708 const X86TargetLowering *XTLI) {
14709 SDValue Op0 = N->getOperand(0);
14710 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14711 // a 32-bit target where SSE doesn't support i64->FP operations.
14712 if (Op0.getOpcode() == ISD::LOAD) {
14713 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14714 EVT VT = Ld->getValueType(0);
14715 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14716 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14717 !XTLI->getSubtarget()->is64Bit() &&
14718 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14719 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14720 Ld->getChain(), Op0, DAG);
14721 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14728 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14729 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14730 X86TargetLowering::DAGCombinerInfo &DCI) {
14731 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14732 // the result is either zero or one (depending on the input carry bit).
14733 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14734 if (X86::isZeroNode(N->getOperand(0)) &&
14735 X86::isZeroNode(N->getOperand(1)) &&
14736 // We don't have a good way to replace an EFLAGS use, so only do this when
14738 SDValue(N, 1).use_empty()) {
14739 DebugLoc DL = N->getDebugLoc();
14740 EVT VT = N->getValueType(0);
14741 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14742 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14743 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14744 DAG.getConstant(X86::COND_B,MVT::i8),
14746 DAG.getConstant(1, VT));
14747 return DCI.CombineTo(N, Res1, CarryOut);
14753 // fold (add Y, (sete X, 0)) -> adc 0, Y
14754 // (add Y, (setne X, 0)) -> sbb -1, Y
14755 // (sub (sete X, 0), Y) -> sbb 0, Y
14756 // (sub (setne X, 0), Y) -> adc -1, Y
14757 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14758 DebugLoc DL = N->getDebugLoc();
14760 // Look through ZExts.
14761 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14762 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14765 SDValue SetCC = Ext.getOperand(0);
14766 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14769 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14770 if (CC != X86::COND_E && CC != X86::COND_NE)
14773 SDValue Cmp = SetCC.getOperand(1);
14774 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14775 !X86::isZeroNode(Cmp.getOperand(1)) ||
14776 !Cmp.getOperand(0).getValueType().isInteger())
14779 SDValue CmpOp0 = Cmp.getOperand(0);
14780 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14781 DAG.getConstant(1, CmpOp0.getValueType()));
14783 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14784 if (CC == X86::COND_NE)
14785 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14786 DL, OtherVal.getValueType(), OtherVal,
14787 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14788 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14789 DL, OtherVal.getValueType(), OtherVal,
14790 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14793 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14794 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14795 const X86Subtarget *Subtarget) {
14796 EVT VT = N->getValueType(0);
14797 SDValue Op0 = N->getOperand(0);
14798 SDValue Op1 = N->getOperand(1);
14800 // Try to synthesize horizontal adds from adds of shuffles.
14801 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14802 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14803 isHorizontalBinOp(Op0, Op1, true))
14804 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14806 return OptimizeConditionalInDecrement(N, DAG);
14809 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14810 const X86Subtarget *Subtarget) {
14811 SDValue Op0 = N->getOperand(0);
14812 SDValue Op1 = N->getOperand(1);
14814 // X86 can't encode an immediate LHS of a sub. See if we can push the
14815 // negation into a preceding instruction.
14816 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14817 // If the RHS of the sub is a XOR with one use and a constant, invert the
14818 // immediate. Then add one to the LHS of the sub so we can turn
14819 // X-Y -> X+~Y+1, saving one register.
14820 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14821 isa<ConstantSDNode>(Op1.getOperand(1))) {
14822 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14823 EVT VT = Op0.getValueType();
14824 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14826 DAG.getConstant(~XorC, VT));
14827 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14828 DAG.getConstant(C->getAPIntValue()+1, VT));
14832 // Try to synthesize horizontal adds from adds of shuffles.
14833 EVT VT = N->getValueType(0);
14834 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14835 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14836 isHorizontalBinOp(Op0, Op1, true))
14837 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14839 return OptimizeConditionalInDecrement(N, DAG);
14842 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14843 DAGCombinerInfo &DCI) const {
14844 SelectionDAG &DAG = DCI.DAG;
14845 switch (N->getOpcode()) {
14847 case ISD::EXTRACT_VECTOR_ELT:
14848 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14850 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14851 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14852 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14853 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14854 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14855 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14858 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14859 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14860 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14861 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14862 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14863 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14864 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14865 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14866 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14868 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14869 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14870 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14871 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14872 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
14873 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
14874 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14875 case X86ISD::SHUFP: // Handle all target specific shuffles
14876 case X86ISD::PALIGN:
14877 case X86ISD::UNPCKH:
14878 case X86ISD::UNPCKL:
14879 case X86ISD::MOVHLPS:
14880 case X86ISD::MOVLHPS:
14881 case X86ISD::PSHUFD:
14882 case X86ISD::PSHUFHW:
14883 case X86ISD::PSHUFLW:
14884 case X86ISD::MOVSS:
14885 case X86ISD::MOVSD:
14886 case X86ISD::VPERMILP:
14887 case X86ISD::VPERM2X128:
14888 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14894 /// isTypeDesirableForOp - Return true if the target has native support for
14895 /// the specified value type and it is 'desirable' to use the type for the
14896 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14897 /// instruction encodings are longer and some i16 instructions are slow.
14898 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14899 if (!isTypeLegal(VT))
14901 if (VT != MVT::i16)
14908 case ISD::SIGN_EXTEND:
14909 case ISD::ZERO_EXTEND:
14910 case ISD::ANY_EXTEND:
14923 /// IsDesirableToPromoteOp - This method query the target whether it is
14924 /// beneficial for dag combiner to promote the specified node. If true, it
14925 /// should return the desired promotion type by reference.
14926 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14927 EVT VT = Op.getValueType();
14928 if (VT != MVT::i16)
14931 bool Promote = false;
14932 bool Commute = false;
14933 switch (Op.getOpcode()) {
14936 LoadSDNode *LD = cast<LoadSDNode>(Op);
14937 // If the non-extending load has a single use and it's not live out, then it
14938 // might be folded.
14939 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14940 Op.hasOneUse()*/) {
14941 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14942 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14943 // The only case where we'd want to promote LOAD (rather then it being
14944 // promoted as an operand is when it's only use is liveout.
14945 if (UI->getOpcode() != ISD::CopyToReg)
14952 case ISD::SIGN_EXTEND:
14953 case ISD::ZERO_EXTEND:
14954 case ISD::ANY_EXTEND:
14959 SDValue N0 = Op.getOperand(0);
14960 // Look out for (store (shl (load), x)).
14961 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14974 SDValue N0 = Op.getOperand(0);
14975 SDValue N1 = Op.getOperand(1);
14976 if (!Commute && MayFoldLoad(N1))
14978 // Avoid disabling potential load folding opportunities.
14979 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14981 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14991 //===----------------------------------------------------------------------===//
14992 // X86 Inline Assembly Support
14993 //===----------------------------------------------------------------------===//
14996 // Helper to match a string separated by whitespace.
14997 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
14998 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15000 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15001 StringRef piece(*args[i]);
15002 if (!s.startswith(piece)) // Check if the piece matches.
15005 s = s.substr(piece.size());
15006 StringRef::size_type pos = s.find_first_not_of(" \t");
15007 if (pos == 0) // We matched a prefix.
15015 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15018 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15019 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15021 std::string AsmStr = IA->getAsmString();
15023 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15024 if (!Ty || Ty->getBitWidth() % 16 != 0)
15027 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15028 SmallVector<StringRef, 4> AsmPieces;
15029 SplitString(AsmStr, AsmPieces, ";\n");
15031 switch (AsmPieces.size()) {
15032 default: return false;
15034 // FIXME: this should verify that we are targeting a 486 or better. If not,
15035 // we will turn this bswap into something that will be lowered to logical
15036 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15037 // lower so don't worry about this.
15039 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15040 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15041 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15042 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15043 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15044 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15045 // No need to check constraints, nothing other than the equivalent of
15046 // "=r,0" would be valid here.
15047 return IntrinsicLowering::LowerToByteSwap(CI);
15050 // rorw $$8, ${0:w} --> llvm.bswap.i16
15051 if (CI->getType()->isIntegerTy(16) &&
15052 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15053 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15054 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15056 const std::string &ConstraintsStr = IA->getConstraintString();
15057 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15058 std::sort(AsmPieces.begin(), AsmPieces.end());
15059 if (AsmPieces.size() == 4 &&
15060 AsmPieces[0] == "~{cc}" &&
15061 AsmPieces[1] == "~{dirflag}" &&
15062 AsmPieces[2] == "~{flags}" &&
15063 AsmPieces[3] == "~{fpsr}")
15064 return IntrinsicLowering::LowerToByteSwap(CI);
15068 if (CI->getType()->isIntegerTy(32) &&
15069 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15070 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15071 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15072 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15074 const std::string &ConstraintsStr = IA->getConstraintString();
15075 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15076 std::sort(AsmPieces.begin(), AsmPieces.end());
15077 if (AsmPieces.size() == 4 &&
15078 AsmPieces[0] == "~{cc}" &&
15079 AsmPieces[1] == "~{dirflag}" &&
15080 AsmPieces[2] == "~{flags}" &&
15081 AsmPieces[3] == "~{fpsr}")
15082 return IntrinsicLowering::LowerToByteSwap(CI);
15085 if (CI->getType()->isIntegerTy(64)) {
15086 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15087 if (Constraints.size() >= 2 &&
15088 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15089 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15090 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15091 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15092 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15093 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15094 return IntrinsicLowering::LowerToByteSwap(CI);
15104 /// getConstraintType - Given a constraint letter, return the type of
15105 /// constraint it is for this target.
15106 X86TargetLowering::ConstraintType
15107 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15108 if (Constraint.size() == 1) {
15109 switch (Constraint[0]) {
15120 return C_RegisterClass;
15144 return TargetLowering::getConstraintType(Constraint);
15147 /// Examine constraint type and operand type and determine a weight value.
15148 /// This object must already have been set up with the operand type
15149 /// and the current alternative constraint selected.
15150 TargetLowering::ConstraintWeight
15151 X86TargetLowering::getSingleConstraintMatchWeight(
15152 AsmOperandInfo &info, const char *constraint) const {
15153 ConstraintWeight weight = CW_Invalid;
15154 Value *CallOperandVal = info.CallOperandVal;
15155 // If we don't have a value, we can't do a match,
15156 // but allow it at the lowest weight.
15157 if (CallOperandVal == NULL)
15159 Type *type = CallOperandVal->getType();
15160 // Look at the constraint type.
15161 switch (*constraint) {
15163 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15174 if (CallOperandVal->getType()->isIntegerTy())
15175 weight = CW_SpecificReg;
15180 if (type->isFloatingPointTy())
15181 weight = CW_SpecificReg;
15184 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15185 weight = CW_SpecificReg;
15189 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15190 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15191 weight = CW_Register;
15194 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15195 if (C->getZExtValue() <= 31)
15196 weight = CW_Constant;
15200 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15201 if (C->getZExtValue() <= 63)
15202 weight = CW_Constant;
15206 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15207 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15208 weight = CW_Constant;
15212 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15213 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15214 weight = CW_Constant;
15218 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15219 if (C->getZExtValue() <= 3)
15220 weight = CW_Constant;
15224 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15225 if (C->getZExtValue() <= 0xff)
15226 weight = CW_Constant;
15231 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15232 weight = CW_Constant;
15236 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15237 if ((C->getSExtValue() >= -0x80000000LL) &&
15238 (C->getSExtValue() <= 0x7fffffffLL))
15239 weight = CW_Constant;
15243 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15244 if (C->getZExtValue() <= 0xffffffff)
15245 weight = CW_Constant;
15252 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15253 /// with another that has more specific requirements based on the type of the
15254 /// corresponding operand.
15255 const char *X86TargetLowering::
15256 LowerXConstraint(EVT ConstraintVT) const {
15257 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15258 // 'f' like normal targets.
15259 if (ConstraintVT.isFloatingPoint()) {
15260 if (Subtarget->hasSSE2())
15262 if (Subtarget->hasSSE1())
15266 return TargetLowering::LowerXConstraint(ConstraintVT);
15269 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15270 /// vector. If it is invalid, don't add anything to Ops.
15271 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15272 std::string &Constraint,
15273 std::vector<SDValue>&Ops,
15274 SelectionDAG &DAG) const {
15275 SDValue Result(0, 0);
15277 // Only support length 1 constraints for now.
15278 if (Constraint.length() > 1) return;
15280 char ConstraintLetter = Constraint[0];
15281 switch (ConstraintLetter) {
15284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15285 if (C->getZExtValue() <= 31) {
15286 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15292 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15293 if (C->getZExtValue() <= 63) {
15294 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15300 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15301 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15302 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15308 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15309 if (C->getZExtValue() <= 255) {
15310 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15316 // 32-bit signed value
15317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15318 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15319 C->getSExtValue())) {
15320 // Widen to 64 bits here to get it sign extended.
15321 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15324 // FIXME gcc accepts some relocatable values here too, but only in certain
15325 // memory models; it's complicated.
15330 // 32-bit unsigned value
15331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15332 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15333 C->getZExtValue())) {
15334 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15338 // FIXME gcc accepts some relocatable values here too, but only in certain
15339 // memory models; it's complicated.
15343 // Literal immediates are always ok.
15344 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15345 // Widen to 64 bits here to get it sign extended.
15346 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15350 // In any sort of PIC mode addresses need to be computed at runtime by
15351 // adding in a register or some sort of table lookup. These can't
15352 // be used as immediates.
15353 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15356 // If we are in non-pic codegen mode, we allow the address of a global (with
15357 // an optional displacement) to be used with 'i'.
15358 GlobalAddressSDNode *GA = 0;
15359 int64_t Offset = 0;
15361 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15363 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15364 Offset += GA->getOffset();
15366 } else if (Op.getOpcode() == ISD::ADD) {
15367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15368 Offset += C->getZExtValue();
15369 Op = Op.getOperand(0);
15372 } else if (Op.getOpcode() == ISD::SUB) {
15373 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15374 Offset += -C->getZExtValue();
15375 Op = Op.getOperand(0);
15380 // Otherwise, this isn't something we can handle, reject it.
15384 const GlobalValue *GV = GA->getGlobal();
15385 // If we require an extra load to get this address, as in PIC mode, we
15386 // can't accept it.
15387 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15388 getTargetMachine())))
15391 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15392 GA->getValueType(0), Offset);
15397 if (Result.getNode()) {
15398 Ops.push_back(Result);
15401 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15404 std::pair<unsigned, const TargetRegisterClass*>
15405 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15407 // First, see if this is a constraint that directly corresponds to an LLVM
15409 if (Constraint.size() == 1) {
15410 // GCC Constraint Letters
15411 switch (Constraint[0]) {
15413 // TODO: Slight differences here in allocation order and leaving
15414 // RIP in the class. Do they matter any more here than they do
15415 // in the normal allocation?
15416 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15417 if (Subtarget->is64Bit()) {
15418 if (VT == MVT::i32 || VT == MVT::f32)
15419 return std::make_pair(0U, X86::GR32RegisterClass);
15420 else if (VT == MVT::i16)
15421 return std::make_pair(0U, X86::GR16RegisterClass);
15422 else if (VT == MVT::i8 || VT == MVT::i1)
15423 return std::make_pair(0U, X86::GR8RegisterClass);
15424 else if (VT == MVT::i64 || VT == MVT::f64)
15425 return std::make_pair(0U, X86::GR64RegisterClass);
15428 // 32-bit fallthrough
15429 case 'Q': // Q_REGS
15430 if (VT == MVT::i32 || VT == MVT::f32)
15431 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15432 else if (VT == MVT::i16)
15433 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15434 else if (VT == MVT::i8 || VT == MVT::i1)
15435 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15436 else if (VT == MVT::i64)
15437 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15439 case 'r': // GENERAL_REGS
15440 case 'l': // INDEX_REGS
15441 if (VT == MVT::i8 || VT == MVT::i1)
15442 return std::make_pair(0U, X86::GR8RegisterClass);
15443 if (VT == MVT::i16)
15444 return std::make_pair(0U, X86::GR16RegisterClass);
15445 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15446 return std::make_pair(0U, X86::GR32RegisterClass);
15447 return std::make_pair(0U, X86::GR64RegisterClass);
15448 case 'R': // LEGACY_REGS
15449 if (VT == MVT::i8 || VT == MVT::i1)
15450 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15451 if (VT == MVT::i16)
15452 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15453 if (VT == MVT::i32 || !Subtarget->is64Bit())
15454 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15455 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15456 case 'f': // FP Stack registers.
15457 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15458 // value to the correct fpstack register class.
15459 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15460 return std::make_pair(0U, X86::RFP32RegisterClass);
15461 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15462 return std::make_pair(0U, X86::RFP64RegisterClass);
15463 return std::make_pair(0U, X86::RFP80RegisterClass);
15464 case 'y': // MMX_REGS if MMX allowed.
15465 if (!Subtarget->hasMMX()) break;
15466 return std::make_pair(0U, X86::VR64RegisterClass);
15467 case 'Y': // SSE_REGS if SSE2 allowed
15468 if (!Subtarget->hasSSE2()) break;
15470 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15471 if (!Subtarget->hasSSE1()) break;
15473 switch (VT.getSimpleVT().SimpleTy) {
15475 // Scalar SSE types.
15478 return std::make_pair(0U, X86::FR32RegisterClass);
15481 return std::make_pair(0U, X86::FR64RegisterClass);
15489 return std::make_pair(0U, X86::VR128RegisterClass);
15497 return std::make_pair(0U, X86::VR256RegisterClass);
15504 // Use the default implementation in TargetLowering to convert the register
15505 // constraint into a member of a register class.
15506 std::pair<unsigned, const TargetRegisterClass*> Res;
15507 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15509 // Not found as a standard register?
15510 if (Res.second == 0) {
15511 // Map st(0) -> st(7) -> ST0
15512 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15513 tolower(Constraint[1]) == 's' &&
15514 tolower(Constraint[2]) == 't' &&
15515 Constraint[3] == '(' &&
15516 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15517 Constraint[5] == ')' &&
15518 Constraint[6] == '}') {
15520 Res.first = X86::ST0+Constraint[4]-'0';
15521 Res.second = X86::RFP80RegisterClass;
15525 // GCC allows "st(0)" to be called just plain "st".
15526 if (StringRef("{st}").equals_lower(Constraint)) {
15527 Res.first = X86::ST0;
15528 Res.second = X86::RFP80RegisterClass;
15533 if (StringRef("{flags}").equals_lower(Constraint)) {
15534 Res.first = X86::EFLAGS;
15535 Res.second = X86::CCRRegisterClass;
15539 // 'A' means EAX + EDX.
15540 if (Constraint == "A") {
15541 Res.first = X86::EAX;
15542 Res.second = X86::GR32_ADRegisterClass;
15548 // Otherwise, check to see if this is a register class of the wrong value
15549 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15550 // turn into {ax},{dx}.
15551 if (Res.second->hasType(VT))
15552 return Res; // Correct type already, nothing to do.
15554 // All of the single-register GCC register classes map their values onto
15555 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15556 // really want an 8-bit or 32-bit register, map to the appropriate register
15557 // class and return the appropriate register.
15558 if (Res.second == X86::GR16RegisterClass) {
15559 if (VT == MVT::i8) {
15560 unsigned DestReg = 0;
15561 switch (Res.first) {
15563 case X86::AX: DestReg = X86::AL; break;
15564 case X86::DX: DestReg = X86::DL; break;
15565 case X86::CX: DestReg = X86::CL; break;
15566 case X86::BX: DestReg = X86::BL; break;
15569 Res.first = DestReg;
15570 Res.second = X86::GR8RegisterClass;
15572 } else if (VT == MVT::i32) {
15573 unsigned DestReg = 0;
15574 switch (Res.first) {
15576 case X86::AX: DestReg = X86::EAX; break;
15577 case X86::DX: DestReg = X86::EDX; break;
15578 case X86::CX: DestReg = X86::ECX; break;
15579 case X86::BX: DestReg = X86::EBX; break;
15580 case X86::SI: DestReg = X86::ESI; break;
15581 case X86::DI: DestReg = X86::EDI; break;
15582 case X86::BP: DestReg = X86::EBP; break;
15583 case X86::SP: DestReg = X86::ESP; break;
15586 Res.first = DestReg;
15587 Res.second = X86::GR32RegisterClass;
15589 } else if (VT == MVT::i64) {
15590 unsigned DestReg = 0;
15591 switch (Res.first) {
15593 case X86::AX: DestReg = X86::RAX; break;
15594 case X86::DX: DestReg = X86::RDX; break;
15595 case X86::CX: DestReg = X86::RCX; break;
15596 case X86::BX: DestReg = X86::RBX; break;
15597 case X86::SI: DestReg = X86::RSI; break;
15598 case X86::DI: DestReg = X86::RDI; break;
15599 case X86::BP: DestReg = X86::RBP; break;
15600 case X86::SP: DestReg = X86::RSP; break;
15603 Res.first = DestReg;
15604 Res.second = X86::GR64RegisterClass;
15607 } else if (Res.second == X86::FR32RegisterClass ||
15608 Res.second == X86::FR64RegisterClass ||
15609 Res.second == X86::VR128RegisterClass) {
15610 // Handle references to XMM physical registers that got mapped into the
15611 // wrong class. This can happen with constraints like {xmm0} where the
15612 // target independent register mapper will just pick the first match it can
15613 // find, ignoring the required type.
15614 if (VT == MVT::f32)
15615 Res.second = X86::FR32RegisterClass;
15616 else if (VT == MVT::f64)
15617 Res.second = X86::FR64RegisterClass;
15618 else if (X86::VR128RegisterClass->hasType(VT))
15619 Res.second = X86::VR128RegisterClass;