1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
526 // There's never any support for operations beyond MVT::f32.
527 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
532 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
537 if (Subtarget->hasPOPCNT()) {
538 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
540 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
547 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
549 if (!Subtarget->hasMOVBE())
550 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
552 // These should be promoted to a larger select which is supported.
553 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554 // X86 wants to expand cmov itself.
555 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567 if (Subtarget->is64Bit()) {
568 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
571 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574 // support continuation, user-level threading, and etc.. As a result, no
575 // other SjLj exception interfaces are implemented and please don't build
576 // your own exception handling based on them.
577 // LLVM/Clang supports zero-cost DWARF exception handling.
578 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
582 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586 if (Subtarget->is64Bit())
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
597 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601 if (Subtarget->is64Bit()) {
602 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
607 if (Subtarget->hasSSE1())
608 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
610 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
612 // Expand certain atomics
613 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
615 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
620 if (Subtarget->hasCmpxchg16b()) {
621 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
624 // FIXME - use subtarget debug flags
625 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
630 if (Subtarget->is64Bit()) {
631 setExceptionPointerRegister(X86::RAX);
632 setExceptionSelectorRegister(X86::RDX);
634 setExceptionPointerRegister(X86::EAX);
635 setExceptionSelectorRegister(X86::EDX);
637 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
640 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
643 setOperationAction(ISD::TRAP, MVT::Other, Legal);
644 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
646 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647 setOperationAction(ISD::VASTART , MVT::Other, Custom);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650 // TargetInfo::X86_64ABIBuiltinVaList
651 setOperationAction(ISD::VAARG , MVT::Other, Custom);
652 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
654 // TargetInfo::CharPtrBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Expand);
656 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
662 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
663 MVT::i64 : MVT::i32, Custom);
665 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
666 // f32 and f64 use SSE.
667 // Set up the FP register classes.
668 addRegisterClass(MVT::f32, &X86::FR32RegClass);
669 addRegisterClass(MVT::f64, &X86::FR64RegClass);
671 // Use ANDPD to simulate FABS.
672 setOperationAction(ISD::FABS , MVT::f64, Custom);
673 setOperationAction(ISD::FABS , MVT::f32, Custom);
675 // Use XORP to simulate FNEG.
676 setOperationAction(ISD::FNEG , MVT::f64, Custom);
677 setOperationAction(ISD::FNEG , MVT::f32, Custom);
679 // Use ANDPD and ORPD to simulate FCOPYSIGN.
680 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
681 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
683 // Lower this to FGETSIGNx86 plus an AND.
684 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
685 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
687 // We don't support sin/cos/fmod
688 setOperationAction(ISD::FSIN , MVT::f64, Expand);
689 setOperationAction(ISD::FCOS , MVT::f64, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
691 setOperationAction(ISD::FSIN , MVT::f32, Expand);
692 setOperationAction(ISD::FCOS , MVT::f32, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
695 // Expand FP immediates into loads from the stack, except for the special
697 addLegalFPImmediate(APFloat(+0.0)); // xorpd
698 addLegalFPImmediate(APFloat(+0.0f)); // xorps
699 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
700 // Use SSE for f32, x87 for f64.
701 // Set up the FP register classes.
702 addRegisterClass(MVT::f32, &X86::FR32RegClass);
703 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
705 // Use ANDPS to simulate FABS.
706 setOperationAction(ISD::FABS , MVT::f32, Custom);
708 // Use XORP to simulate FNEG.
709 setOperationAction(ISD::FNEG , MVT::f32, Custom);
711 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
713 // Use ANDPS and ORPS to simulate FCOPYSIGN.
714 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
715 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
717 // We don't support sin/cos/fmod
718 setOperationAction(ISD::FSIN , MVT::f32, Expand);
719 setOperationAction(ISD::FCOS , MVT::f32, Expand);
720 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
722 // Special cases we handle for FP constants.
723 addLegalFPImmediate(APFloat(+0.0f)); // xorps
724 addLegalFPImmediate(APFloat(+0.0)); // FLD0
725 addLegalFPImmediate(APFloat(+1.0)); // FLD1
726 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
727 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
729 if (!TM.Options.UnsafeFPMath) {
730 setOperationAction(ISD::FSIN , MVT::f64, Expand);
731 setOperationAction(ISD::FCOS , MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
734 } else if (!TM.Options.UseSoftFloat) {
735 // f32 and f64 in x87.
736 // Set up the FP register classes.
737 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
738 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
740 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
741 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
743 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
745 if (!TM.Options.UnsafeFPMath) {
746 setOperationAction(ISD::FSIN , MVT::f64, Expand);
747 setOperationAction(ISD::FSIN , MVT::f32, Expand);
748 setOperationAction(ISD::FCOS , MVT::f64, Expand);
749 setOperationAction(ISD::FCOS , MVT::f32, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
751 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
753 addLegalFPImmediate(APFloat(+0.0)); // FLD0
754 addLegalFPImmediate(APFloat(+1.0)); // FLD1
755 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
756 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
757 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
758 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
759 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
760 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
763 // We don't support FMA.
764 setOperationAction(ISD::FMA, MVT::f64, Expand);
765 setOperationAction(ISD::FMA, MVT::f32, Expand);
767 // Long double always uses X87.
768 if (!TM.Options.UseSoftFloat) {
769 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
770 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
771 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
773 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
774 addLegalFPImmediate(TmpFlt); // FLD0
776 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
779 APFloat TmpFlt2(+1.0);
780 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
782 addLegalFPImmediate(TmpFlt2); // FLD1
783 TmpFlt2.changeSign();
784 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
787 if (!TM.Options.UnsafeFPMath) {
788 setOperationAction(ISD::FSIN , MVT::f80, Expand);
789 setOperationAction(ISD::FCOS , MVT::f80, Expand);
790 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
793 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
794 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
795 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
796 setOperationAction(ISD::FRINT, MVT::f80, Expand);
797 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
798 setOperationAction(ISD::FMA, MVT::f80, Expand);
801 // Always use a library call for pow.
802 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
804 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
806 setOperationAction(ISD::FLOG, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
808 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP, MVT::f80, Expand);
810 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
812 // First set operation action for all vector types to either promote
813 // (for widening) or expand (for scalarization). Then we will selectively
814 // turn on ones that can be effectively codegen'd.
815 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
816 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
817 MVT VT = (MVT::SimpleValueType)i;
818 setOperationAction(ISD::ADD , VT, Expand);
819 setOperationAction(ISD::SUB , VT, Expand);
820 setOperationAction(ISD::FADD, VT, Expand);
821 setOperationAction(ISD::FNEG, VT, Expand);
822 setOperationAction(ISD::FSUB, VT, Expand);
823 setOperationAction(ISD::MUL , VT, Expand);
824 setOperationAction(ISD::FMUL, VT, Expand);
825 setOperationAction(ISD::SDIV, VT, Expand);
826 setOperationAction(ISD::UDIV, VT, Expand);
827 setOperationAction(ISD::FDIV, VT, Expand);
828 setOperationAction(ISD::SREM, VT, Expand);
829 setOperationAction(ISD::UREM, VT, Expand);
830 setOperationAction(ISD::LOAD, VT, Expand);
831 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
834 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
836 setOperationAction(ISD::FABS, VT, Expand);
837 setOperationAction(ISD::FSIN, VT, Expand);
838 setOperationAction(ISD::FSINCOS, VT, Expand);
839 setOperationAction(ISD::FCOS, VT, Expand);
840 setOperationAction(ISD::FSINCOS, VT, Expand);
841 setOperationAction(ISD::FREM, VT, Expand);
842 setOperationAction(ISD::FMA, VT, Expand);
843 setOperationAction(ISD::FPOWI, VT, Expand);
844 setOperationAction(ISD::FSQRT, VT, Expand);
845 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
846 setOperationAction(ISD::FFLOOR, VT, Expand);
847 setOperationAction(ISD::FCEIL, VT, Expand);
848 setOperationAction(ISD::FTRUNC, VT, Expand);
849 setOperationAction(ISD::FRINT, VT, Expand);
850 setOperationAction(ISD::FNEARBYINT, VT, Expand);
851 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
852 setOperationAction(ISD::MULHS, VT, Expand);
853 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
854 setOperationAction(ISD::MULHU, VT, Expand);
855 setOperationAction(ISD::SDIVREM, VT, Expand);
856 setOperationAction(ISD::UDIVREM, VT, Expand);
857 setOperationAction(ISD::FPOW, VT, Expand);
858 setOperationAction(ISD::CTPOP, VT, Expand);
859 setOperationAction(ISD::CTTZ, VT, Expand);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
861 setOperationAction(ISD::CTLZ, VT, Expand);
862 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
863 setOperationAction(ISD::SHL, VT, Expand);
864 setOperationAction(ISD::SRA, VT, Expand);
865 setOperationAction(ISD::SRL, VT, Expand);
866 setOperationAction(ISD::ROTL, VT, Expand);
867 setOperationAction(ISD::ROTR, VT, Expand);
868 setOperationAction(ISD::BSWAP, VT, Expand);
869 setOperationAction(ISD::SETCC, VT, Expand);
870 setOperationAction(ISD::FLOG, VT, Expand);
871 setOperationAction(ISD::FLOG2, VT, Expand);
872 setOperationAction(ISD::FLOG10, VT, Expand);
873 setOperationAction(ISD::FEXP, VT, Expand);
874 setOperationAction(ISD::FEXP2, VT, Expand);
875 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
876 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
877 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
879 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
880 setOperationAction(ISD::TRUNCATE, VT, Expand);
881 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
882 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
883 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
884 setOperationAction(ISD::VSELECT, VT, Expand);
885 setOperationAction(ISD::SELECT_CC, VT, Expand);
886 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
887 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
888 setTruncStoreAction(VT,
889 (MVT::SimpleValueType)InnerVT, Expand);
890 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
891 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
893 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
894 // we have to deal with them whether we ask for Expansion or not. Setting
895 // Expand causes its own optimisation problems though, so leave them legal.
896 if (VT.getVectorElementType() == MVT::i1)
897 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
900 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
901 // with -msoft-float, disable use of MMX as well.
902 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
903 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
904 // No operations on x86mmx supported, everything uses intrinsics.
907 // MMX-sized vectors (other than x86mmx) are expected to be expanded
908 // into smaller operations.
909 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
910 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
911 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
912 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
913 setOperationAction(ISD::AND, MVT::v8i8, Expand);
914 setOperationAction(ISD::AND, MVT::v4i16, Expand);
915 setOperationAction(ISD::AND, MVT::v2i32, Expand);
916 setOperationAction(ISD::AND, MVT::v1i64, Expand);
917 setOperationAction(ISD::OR, MVT::v8i8, Expand);
918 setOperationAction(ISD::OR, MVT::v4i16, Expand);
919 setOperationAction(ISD::OR, MVT::v2i32, Expand);
920 setOperationAction(ISD::OR, MVT::v1i64, Expand);
921 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
922 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
923 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
924 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
930 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
931 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
932 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
933 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
939 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
940 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
942 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
943 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
944 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
945 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
947 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
948 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
949 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
950 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
951 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
952 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
953 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
956 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
957 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
959 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
960 // registers cannot be used even for integer operations.
961 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
962 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
963 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
964 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
966 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
967 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
968 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
969 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
971 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
972 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
974 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
975 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
976 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
977 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
978 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
979 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
980 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
981 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
982 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
983 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
984 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
986 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
987 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
990 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
991 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
992 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
995 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1001 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1002 MVT VT = (MVT::SimpleValueType)i;
1003 // Do not attempt to custom lower non-power-of-2 vectors
1004 if (!isPowerOf2_32(VT.getVectorNumElements()))
1006 // Do not attempt to custom lower non-128-bit vectors
1007 if (!VT.is128BitVector())
1009 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1010 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1014 // We support custom legalizing of sext and anyext loads for specific
1015 // memory vector types which we can load as a scalar (or sequence of
1016 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1017 // loads these must work with a single scalar load.
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1019 if (Subtarget->is64Bit()) {
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1034 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1037 if (Subtarget->is64Bit()) {
1038 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1039 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1042 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1043 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1044 MVT VT = (MVT::SimpleValueType)i;
1046 // Do not attempt to promote non-128-bit vectors
1047 if (!VT.is128BitVector())
1050 setOperationAction(ISD::AND, VT, Promote);
1051 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1052 setOperationAction(ISD::OR, VT, Promote);
1053 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1054 setOperationAction(ISD::XOR, VT, Promote);
1055 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1056 setOperationAction(ISD::LOAD, VT, Promote);
1057 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1058 setOperationAction(ISD::SELECT, VT, Promote);
1059 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1062 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1064 // Custom lower v2i64 and v2f64 selects.
1065 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1066 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1067 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1068 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1070 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1071 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1074 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1075 // As there is no 64-bit GPR available, we need build a special custom
1076 // sequence to convert from v2i32 to v2f32.
1077 if (!Subtarget->is64Bit())
1078 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1081 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1083 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1085 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1087 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1090 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1091 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1092 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1093 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1094 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1099 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1102 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1111 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1113 // FIXME: Do we need to handle scalar-to-vector here?
1114 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1116 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1120 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1121 // There is no BLENDI for byte vectors. We don't need to custom lower
1122 // some vselects for now.
1123 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1125 // SSE41 brings specific instructions for doing vector sign extend even in
1126 // cases where we don't have SRA.
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1129 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1131 // i8 and i16 vectors are custom , because the source register and source
1132 // source memory operand types are not the same width. f32 vectors are
1133 // custom since the immediate controlling the insert encodes additional
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1145 // FIXME: these should be Legal but thats only for the case where
1146 // the index is constant. For now custom expand to deal with that.
1147 if (Subtarget->is64Bit()) {
1148 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1153 if (Subtarget->hasSSE2()) {
1154 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1157 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1158 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1160 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1161 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1163 // In the customized shift lowering, the legal cases in AVX2 will be
1165 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1166 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1168 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1169 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1171 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1174 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1175 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1180 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1182 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1184 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1186 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1197 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1199 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1210 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1212 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1213 // even though v8i16 is a legal type.
1214 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1216 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1219 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1220 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1223 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1225 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1227 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1233 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1234 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1239 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1243 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1248 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1255 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1258 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1261 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1263 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1264 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1266 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1267 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1268 setOperationAction(ISD::FMA, MVT::f32, Legal);
1269 setOperationAction(ISD::FMA, MVT::f64, Legal);
1272 if (Subtarget->hasInt256()) {
1273 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1274 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1275 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1276 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1278 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1279 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1280 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1281 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1283 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1284 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1285 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1286 // Don't lower v32i8 because there is no 128-bit byte mul
1288 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1290 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1291 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1293 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1294 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1296 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1297 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1298 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1299 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1301 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1302 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1303 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1304 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1306 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1307 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1308 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1309 // Don't lower v32i8 because there is no 128-bit byte mul
1312 // In the customized shift lowering, the legal cases in AVX2 will be
1314 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1315 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1317 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1318 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1320 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1322 // Custom lower several nodes for 256-bit types.
1323 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1324 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1325 MVT VT = (MVT::SimpleValueType)i;
1327 // Extract subvector is special because the value type
1328 // (result) is 128-bit but the source is 256-bit wide.
1329 if (VT.is128BitVector())
1330 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1332 // Do not attempt to custom lower other non-256-bit vectors
1333 if (!VT.is256BitVector())
1336 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1337 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1338 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1340 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1341 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1342 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1345 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1346 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1347 MVT VT = (MVT::SimpleValueType)i;
1349 // Do not attempt to promote non-256-bit vectors
1350 if (!VT.is256BitVector())
1353 setOperationAction(ISD::AND, VT, Promote);
1354 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1355 setOperationAction(ISD::OR, VT, Promote);
1356 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1357 setOperationAction(ISD::XOR, VT, Promote);
1358 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1359 setOperationAction(ISD::LOAD, VT, Promote);
1360 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1361 setOperationAction(ISD::SELECT, VT, Promote);
1362 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1366 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1367 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1370 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1372 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1373 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1374 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1376 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1377 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1378 setOperationAction(ISD::XOR, MVT::i1, Legal);
1379 setOperationAction(ISD::OR, MVT::i1, Legal);
1380 setOperationAction(ISD::AND, MVT::i1, Legal);
1381 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1388 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1395 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1401 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1402 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1406 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1407 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1408 if (Subtarget->is64Bit()) {
1409 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1410 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1411 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1412 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1414 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1422 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1425 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1446 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1447 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1449 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1461 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1462 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1464 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1465 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1467 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1470 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1472 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1473 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1475 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1476 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1478 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1479 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1481 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1482 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1483 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1485 if (Subtarget->hasCDI()) {
1486 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1487 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1490 // Custom lower several nodes.
1491 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1492 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1493 MVT VT = (MVT::SimpleValueType)i;
1495 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1496 // Extract subvector is special because the value type
1497 // (result) is 256/128-bit but the source is 512-bit wide.
1498 if (VT.is128BitVector() || VT.is256BitVector())
1499 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1501 if (VT.getVectorElementType() == MVT::i1)
1502 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1504 // Do not attempt to custom lower other non-512-bit vectors
1505 if (!VT.is512BitVector())
1508 if ( EltSize >= 32) {
1509 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1510 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1511 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1512 setOperationAction(ISD::VSELECT, VT, Legal);
1513 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1514 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1515 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1518 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1519 MVT VT = (MVT::SimpleValueType)i;
1521 // Do not attempt to promote non-256-bit vectors
1522 if (!VT.is512BitVector())
1525 setOperationAction(ISD::SELECT, VT, Promote);
1526 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1530 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1531 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1532 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1536 // of this type with custom code.
1537 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1538 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1539 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1543 // We want to custom lower some of our intrinsics.
1544 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1545 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1546 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1547 if (!Subtarget->is64Bit())
1548 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1550 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1551 // handle type legalization for these operations here.
1553 // FIXME: We really should do custom legalization for addition and
1554 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1555 // than generic legalization for 64-bit multiplication-with-overflow, though.
1556 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1557 // Add/Sub/Mul with overflow operations are custom lowered.
1559 setOperationAction(ISD::SADDO, VT, Custom);
1560 setOperationAction(ISD::UADDO, VT, Custom);
1561 setOperationAction(ISD::SSUBO, VT, Custom);
1562 setOperationAction(ISD::USUBO, VT, Custom);
1563 setOperationAction(ISD::SMULO, VT, Custom);
1564 setOperationAction(ISD::UMULO, VT, Custom);
1567 // There are no 8-bit 3-address imul/mul instructions
1568 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1569 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1571 if (!Subtarget->is64Bit()) {
1572 // These libcalls are not available in 32-bit.
1573 setLibcallName(RTLIB::SHL_I128, nullptr);
1574 setLibcallName(RTLIB::SRL_I128, nullptr);
1575 setLibcallName(RTLIB::SRA_I128, nullptr);
1578 // Combine sin / cos into one node or libcall if possible.
1579 if (Subtarget->hasSinCos()) {
1580 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1581 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1582 if (Subtarget->isTargetDarwin()) {
1583 // For MacOSX, we don't want to the normal expansion of a libcall to
1584 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1586 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1587 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1591 if (Subtarget->isTargetWin64()) {
1592 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1593 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1594 setOperationAction(ISD::SREM, MVT::i128, Custom);
1595 setOperationAction(ISD::UREM, MVT::i128, Custom);
1596 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1597 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1600 // We have target-specific dag combine patterns for the following nodes:
1601 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1602 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1603 setTargetDAGCombine(ISD::VSELECT);
1604 setTargetDAGCombine(ISD::SELECT);
1605 setTargetDAGCombine(ISD::SHL);
1606 setTargetDAGCombine(ISD::SRA);
1607 setTargetDAGCombine(ISD::SRL);
1608 setTargetDAGCombine(ISD::OR);
1609 setTargetDAGCombine(ISD::AND);
1610 setTargetDAGCombine(ISD::ADD);
1611 setTargetDAGCombine(ISD::FADD);
1612 setTargetDAGCombine(ISD::FSUB);
1613 setTargetDAGCombine(ISD::FMA);
1614 setTargetDAGCombine(ISD::SUB);
1615 setTargetDAGCombine(ISD::LOAD);
1616 setTargetDAGCombine(ISD::STORE);
1617 setTargetDAGCombine(ISD::ZERO_EXTEND);
1618 setTargetDAGCombine(ISD::ANY_EXTEND);
1619 setTargetDAGCombine(ISD::SIGN_EXTEND);
1620 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1621 setTargetDAGCombine(ISD::TRUNCATE);
1622 setTargetDAGCombine(ISD::SINT_TO_FP);
1623 setTargetDAGCombine(ISD::SETCC);
1624 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1625 setTargetDAGCombine(ISD::BUILD_VECTOR);
1626 if (Subtarget->is64Bit())
1627 setTargetDAGCombine(ISD::MUL);
1628 setTargetDAGCombine(ISD::XOR);
1630 computeRegisterProperties();
1632 // On Darwin, -Os means optimize for size without hurting performance,
1633 // do not reduce the limit.
1634 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1635 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1636 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1637 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1638 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1639 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1640 setPrefLoopAlignment(4); // 2^4 bytes.
1642 // Predictable cmov don't hurt on atom because it's in-order.
1643 PredictableSelectIsExpensive = !Subtarget->isAtom();
1645 setPrefFunctionAlignment(4); // 2^4 bytes.
1648 // This has so far only been implemented for 64-bit MachO.
1649 bool X86TargetLowering::useLoadStackGuardNode() const {
1650 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1651 Subtarget->is64Bit();
1654 TargetLoweringBase::LegalizeTypeAction
1655 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1656 if (ExperimentalVectorWideningLegalization &&
1657 VT.getVectorNumElements() != 1 &&
1658 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1659 return TypeWidenVector;
1661 return TargetLoweringBase::getPreferredVectorAction(VT);
1664 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1666 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1668 if (Subtarget->hasAVX512())
1669 switch(VT.getVectorNumElements()) {
1670 case 8: return MVT::v8i1;
1671 case 16: return MVT::v16i1;
1674 return VT.changeVectorElementTypeToInteger();
1677 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1678 /// the desired ByVal argument alignment.
1679 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1682 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1683 if (VTy->getBitWidth() == 128)
1685 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1686 unsigned EltAlign = 0;
1687 getMaxByValAlign(ATy->getElementType(), EltAlign);
1688 if (EltAlign > MaxAlign)
1689 MaxAlign = EltAlign;
1690 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1691 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1692 unsigned EltAlign = 0;
1693 getMaxByValAlign(STy->getElementType(i), EltAlign);
1694 if (EltAlign > MaxAlign)
1695 MaxAlign = EltAlign;
1702 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1703 /// function arguments in the caller parameter area. For X86, aggregates
1704 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1705 /// are at 4-byte boundaries.
1706 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1707 if (Subtarget->is64Bit()) {
1708 // Max of 8 and alignment of type.
1709 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1716 if (Subtarget->hasSSE1())
1717 getMaxByValAlign(Ty, Align);
1721 /// getOptimalMemOpType - Returns the target specific optimal type for load
1722 /// and store operations as a result of memset, memcpy, and memmove
1723 /// lowering. If DstAlign is zero that means it's safe to destination
1724 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1725 /// means there isn't a need to check it against alignment requirement,
1726 /// probably because the source does not need to be loaded. If 'IsMemset' is
1727 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1728 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1729 /// source is constant so it does not need to be loaded.
1730 /// It returns EVT::Other if the type should be determined using generic
1731 /// target-independent logic.
1733 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1734 unsigned DstAlign, unsigned SrcAlign,
1735 bool IsMemset, bool ZeroMemset,
1737 MachineFunction &MF) const {
1738 const Function *F = MF.getFunction();
1739 if ((!IsMemset || ZeroMemset) &&
1740 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1741 Attribute::NoImplicitFloat)) {
1743 (Subtarget->isUnalignedMemAccessFast() ||
1744 ((DstAlign == 0 || DstAlign >= 16) &&
1745 (SrcAlign == 0 || SrcAlign >= 16)))) {
1747 if (Subtarget->hasInt256())
1749 if (Subtarget->hasFp256())
1752 if (Subtarget->hasSSE2())
1754 if (Subtarget->hasSSE1())
1756 } else if (!MemcpyStrSrc && Size >= 8 &&
1757 !Subtarget->is64Bit() &&
1758 Subtarget->hasSSE2()) {
1759 // Do not use f64 to lower memcpy if source is string constant. It's
1760 // better to use i32 to avoid the loads.
1764 if (Subtarget->is64Bit() && Size >= 8)
1769 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1771 return X86ScalarSSEf32;
1772 else if (VT == MVT::f64)
1773 return X86ScalarSSEf64;
1778 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1783 *Fast = Subtarget->isUnalignedMemAccessFast();
1787 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1788 /// current function. The returned value is a member of the
1789 /// MachineJumpTableInfo::JTEntryKind enum.
1790 unsigned X86TargetLowering::getJumpTableEncoding() const {
1791 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1793 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1794 Subtarget->isPICStyleGOT())
1795 return MachineJumpTableInfo::EK_Custom32;
1797 // Otherwise, use the normal jump table encoding heuristics.
1798 return TargetLowering::getJumpTableEncoding();
1802 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1803 const MachineBasicBlock *MBB,
1804 unsigned uid,MCContext &Ctx) const{
1805 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1806 Subtarget->isPICStyleGOT());
1807 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1809 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1810 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1813 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1815 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1816 SelectionDAG &DAG) const {
1817 if (!Subtarget->is64Bit())
1818 // This doesn't have SDLoc associated with it, but is not really the
1819 // same as a Register.
1820 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1824 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1825 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1827 const MCExpr *X86TargetLowering::
1828 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1829 MCContext &Ctx) const {
1830 // X86-64 uses RIP relative addressing based on the jump table label.
1831 if (Subtarget->isPICStyleRIPRel())
1832 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1834 // Otherwise, the reference is relative to the PIC base.
1835 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1838 // FIXME: Why this routine is here? Move to RegInfo!
1839 std::pair<const TargetRegisterClass*, uint8_t>
1840 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1841 const TargetRegisterClass *RRC = nullptr;
1843 switch (VT.SimpleTy) {
1845 return TargetLowering::findRepresentativeClass(VT);
1846 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1847 RRC = Subtarget->is64Bit() ?
1848 (const TargetRegisterClass*)&X86::GR64RegClass :
1849 (const TargetRegisterClass*)&X86::GR32RegClass;
1852 RRC = &X86::VR64RegClass;
1854 case MVT::f32: case MVT::f64:
1855 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1856 case MVT::v4f32: case MVT::v2f64:
1857 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1859 RRC = &X86::VR128RegClass;
1862 return std::make_pair(RRC, Cost);
1865 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1866 unsigned &Offset) const {
1867 if (!Subtarget->isTargetLinux())
1870 if (Subtarget->is64Bit()) {
1871 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1873 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1885 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1886 unsigned DestAS) const {
1887 assert(SrcAS != DestAS && "Expected different address spaces!");
1889 return SrcAS < 256 && DestAS < 256;
1892 //===----------------------------------------------------------------------===//
1893 // Return Value Calling Convention Implementation
1894 //===----------------------------------------------------------------------===//
1896 #include "X86GenCallingConv.inc"
1899 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1900 MachineFunction &MF, bool isVarArg,
1901 const SmallVectorImpl<ISD::OutputArg> &Outs,
1902 LLVMContext &Context) const {
1903 SmallVector<CCValAssign, 16> RVLocs;
1904 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1905 return CCInfo.CheckReturn(Outs, RetCC_X86);
1908 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1909 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1914 X86TargetLowering::LowerReturn(SDValue Chain,
1915 CallingConv::ID CallConv, bool isVarArg,
1916 const SmallVectorImpl<ISD::OutputArg> &Outs,
1917 const SmallVectorImpl<SDValue> &OutVals,
1918 SDLoc dl, SelectionDAG &DAG) const {
1919 MachineFunction &MF = DAG.getMachineFunction();
1920 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1922 SmallVector<CCValAssign, 16> RVLocs;
1923 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1924 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1927 SmallVector<SDValue, 6> RetOps;
1928 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1929 // Operand #1 = Bytes To Pop
1930 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1933 // Copy the result values into the output registers.
1934 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1935 CCValAssign &VA = RVLocs[i];
1936 assert(VA.isRegLoc() && "Can only return in registers!");
1937 SDValue ValToCopy = OutVals[i];
1938 EVT ValVT = ValToCopy.getValueType();
1940 // Promote values to the appropriate types
1941 if (VA.getLocInfo() == CCValAssign::SExt)
1942 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1943 else if (VA.getLocInfo() == CCValAssign::ZExt)
1944 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1945 else if (VA.getLocInfo() == CCValAssign::AExt)
1946 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1947 else if (VA.getLocInfo() == CCValAssign::BCvt)
1948 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1950 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1951 "Unexpected FP-extend for return value.");
1953 // If this is x86-64, and we disabled SSE, we can't return FP values,
1954 // or SSE or MMX vectors.
1955 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1956 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1957 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1958 report_fatal_error("SSE register return with SSE disabled");
1960 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1961 // llvm-gcc has never done it right and no one has noticed, so this
1962 // should be OK for now.
1963 if (ValVT == MVT::f64 &&
1964 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1965 report_fatal_error("SSE2 register return with SSE2 disabled");
1967 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1968 // the RET instruction and handled by the FP Stackifier.
1969 if (VA.getLocReg() == X86::FP0 ||
1970 VA.getLocReg() == X86::FP1) {
1971 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1972 // change the value to the FP stack register class.
1973 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1974 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1975 RetOps.push_back(ValToCopy);
1976 // Don't emit a copytoreg.
1980 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1981 // which is returned in RAX / RDX.
1982 if (Subtarget->is64Bit()) {
1983 if (ValVT == MVT::x86mmx) {
1984 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1985 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1986 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1988 // If we don't have SSE2 available, convert to v4f32 so the generated
1989 // register is legal.
1990 if (!Subtarget->hasSSE2())
1991 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1996 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1997 Flag = Chain.getValue(1);
1998 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2001 // The x86-64 ABIs require that for returning structs by value we copy
2002 // the sret argument into %rax/%eax (depending on ABI) for the return.
2003 // Win32 requires us to put the sret argument to %eax as well.
2004 // We saved the argument into a virtual register in the entry block,
2005 // so now we copy the value out and into %rax/%eax.
2006 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2007 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2008 MachineFunction &MF = DAG.getMachineFunction();
2009 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2010 unsigned Reg = FuncInfo->getSRetReturnReg();
2012 "SRetReturnReg should have been set in LowerFormalArguments().");
2013 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2016 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2017 X86::RAX : X86::EAX;
2018 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2019 Flag = Chain.getValue(1);
2021 // RAX/EAX now acts like a return value.
2022 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2025 RetOps[0] = Chain; // Update chain.
2027 // Add the flag if we have it.
2029 RetOps.push_back(Flag);
2031 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2034 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2035 if (N->getNumValues() != 1)
2037 if (!N->hasNUsesOfValue(1, 0))
2040 SDValue TCChain = Chain;
2041 SDNode *Copy = *N->use_begin();
2042 if (Copy->getOpcode() == ISD::CopyToReg) {
2043 // If the copy has a glue operand, we conservatively assume it isn't safe to
2044 // perform a tail call.
2045 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2047 TCChain = Copy->getOperand(0);
2048 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2051 bool HasRet = false;
2052 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2054 if (UI->getOpcode() != X86ISD::RET_FLAG)
2067 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
2068 ISD::NodeType ExtendKind) const {
2070 // TODO: Is this also valid on 32-bit?
2071 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2072 ReturnMVT = MVT::i8;
2074 ReturnMVT = MVT::i32;
2076 MVT MinVT = getRegisterType(ReturnMVT);
2077 return VT.bitsLT(MinVT) ? MinVT : VT;
2080 /// LowerCallResult - Lower the result values of a call into the
2081 /// appropriate copies out of appropriate physical registers.
2084 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2085 CallingConv::ID CallConv, bool isVarArg,
2086 const SmallVectorImpl<ISD::InputArg> &Ins,
2087 SDLoc dl, SelectionDAG &DAG,
2088 SmallVectorImpl<SDValue> &InVals) const {
2090 // Assign locations to each value returned by this call.
2091 SmallVector<CCValAssign, 16> RVLocs;
2092 bool Is64Bit = Subtarget->is64Bit();
2093 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2095 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2097 // Copy all of the result registers out of their specified physreg.
2098 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2099 CCValAssign &VA = RVLocs[i];
2100 EVT CopyVT = VA.getValVT();
2102 // If this is x86-64, and we disabled SSE, we can't return FP values
2103 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2104 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2105 report_fatal_error("SSE register return with SSE disabled");
2108 // If we prefer to use the value in xmm registers, copy it out as f80 and
2109 // use a truncate to move it from fp stack reg to xmm reg.
2110 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2111 isScalarFPTypeInSSEReg(VA.getValVT()))
2114 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2115 CopyVT, InFlag).getValue(1);
2116 SDValue Val = Chain.getValue(0);
2118 if (CopyVT != VA.getValVT())
2119 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2120 // This truncation won't change the value.
2121 DAG.getIntPtrConstant(1));
2123 InFlag = Chain.getValue(2);
2124 InVals.push_back(Val);
2130 //===----------------------------------------------------------------------===//
2131 // C & StdCall & Fast Calling Convention implementation
2132 //===----------------------------------------------------------------------===//
2133 // StdCall calling convention seems to be standard for many Windows' API
2134 // routines and around. It differs from C calling convention just a little:
2135 // callee should clean up the stack, not caller. Symbols should be also
2136 // decorated in some fancy way :) It doesn't support any vector arguments.
2137 // For info on fast calling convention see Fast Calling Convention (tail call)
2138 // implementation LowerX86_32FastCCCallTo.
2140 /// CallIsStructReturn - Determines whether a call uses struct return
2142 enum StructReturnType {
2147 static StructReturnType
2148 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2150 return NotStructReturn;
2152 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2153 if (!Flags.isSRet())
2154 return NotStructReturn;
2155 if (Flags.isInReg())
2156 return RegStructReturn;
2157 return StackStructReturn;
2160 /// ArgsAreStructReturn - Determines whether a function uses struct
2161 /// return semantics.
2162 static StructReturnType
2163 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2165 return NotStructReturn;
2167 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2168 if (!Flags.isSRet())
2169 return NotStructReturn;
2170 if (Flags.isInReg())
2171 return RegStructReturn;
2172 return StackStructReturn;
2175 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2176 /// by "Src" to address "Dst" with size and alignment information specified by
2177 /// the specific parameter attribute. The copy will be passed as a byval
2178 /// function parameter.
2180 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2181 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2183 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2185 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2186 /*isVolatile*/false, /*AlwaysInline=*/true,
2187 MachinePointerInfo(), MachinePointerInfo());
2190 /// IsTailCallConvention - Return true if the calling convention is one that
2191 /// supports tail call optimization.
2192 static bool IsTailCallConvention(CallingConv::ID CC) {
2193 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2194 CC == CallingConv::HiPE);
2197 /// \brief Return true if the calling convention is a C calling convention.
2198 static bool IsCCallConvention(CallingConv::ID CC) {
2199 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2200 CC == CallingConv::X86_64_SysV);
2203 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2204 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2208 CallingConv::ID CalleeCC = CS.getCallingConv();
2209 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2215 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2216 /// a tailcall target by changing its ABI.
2217 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2218 bool GuaranteedTailCallOpt) {
2219 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2223 X86TargetLowering::LowerMemArgument(SDValue Chain,
2224 CallingConv::ID CallConv,
2225 const SmallVectorImpl<ISD::InputArg> &Ins,
2226 SDLoc dl, SelectionDAG &DAG,
2227 const CCValAssign &VA,
2228 MachineFrameInfo *MFI,
2230 // Create the nodes corresponding to a load from this parameter slot.
2231 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2232 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2233 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2234 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2237 // If value is passed by pointer we have address passed instead of the value
2239 if (VA.getLocInfo() == CCValAssign::Indirect)
2240 ValVT = VA.getLocVT();
2242 ValVT = VA.getValVT();
2244 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2245 // changed with more analysis.
2246 // In case of tail call optimization mark all arguments mutable. Since they
2247 // could be overwritten by lowering of arguments in case of a tail call.
2248 if (Flags.isByVal()) {
2249 unsigned Bytes = Flags.getByValSize();
2250 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2251 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2252 return DAG.getFrameIndex(FI, getPointerTy());
2254 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2255 VA.getLocMemOffset(), isImmutable);
2256 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2257 return DAG.getLoad(ValVT, dl, Chain, FIN,
2258 MachinePointerInfo::getFixedStack(FI),
2259 false, false, false, 0);
2264 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2265 CallingConv::ID CallConv,
2267 const SmallVectorImpl<ISD::InputArg> &Ins,
2270 SmallVectorImpl<SDValue> &InVals)
2272 MachineFunction &MF = DAG.getMachineFunction();
2273 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2275 const Function* Fn = MF.getFunction();
2276 if (Fn->hasExternalLinkage() &&
2277 Subtarget->isTargetCygMing() &&
2278 Fn->getName() == "main")
2279 FuncInfo->setForceFramePointer(true);
2281 MachineFrameInfo *MFI = MF.getFrameInfo();
2282 bool Is64Bit = Subtarget->is64Bit();
2283 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2285 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2286 "Var args not supported with calling convention fastcc, ghc or hipe");
2288 // Assign locations to all of the incoming arguments.
2289 SmallVector<CCValAssign, 16> ArgLocs;
2290 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2292 // Allocate shadow area for Win64
2294 CCInfo.AllocateStack(32, 8);
2296 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2298 unsigned LastVal = ~0U;
2300 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2301 CCValAssign &VA = ArgLocs[i];
2302 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2304 assert(VA.getValNo() != LastVal &&
2305 "Don't support value assigned to multiple locs yet");
2307 LastVal = VA.getValNo();
2309 if (VA.isRegLoc()) {
2310 EVT RegVT = VA.getLocVT();
2311 const TargetRegisterClass *RC;
2312 if (RegVT == MVT::i32)
2313 RC = &X86::GR32RegClass;
2314 else if (Is64Bit && RegVT == MVT::i64)
2315 RC = &X86::GR64RegClass;
2316 else if (RegVT == MVT::f32)
2317 RC = &X86::FR32RegClass;
2318 else if (RegVT == MVT::f64)
2319 RC = &X86::FR64RegClass;
2320 else if (RegVT.is512BitVector())
2321 RC = &X86::VR512RegClass;
2322 else if (RegVT.is256BitVector())
2323 RC = &X86::VR256RegClass;
2324 else if (RegVT.is128BitVector())
2325 RC = &X86::VR128RegClass;
2326 else if (RegVT == MVT::x86mmx)
2327 RC = &X86::VR64RegClass;
2328 else if (RegVT == MVT::i1)
2329 RC = &X86::VK1RegClass;
2330 else if (RegVT == MVT::v8i1)
2331 RC = &X86::VK8RegClass;
2332 else if (RegVT == MVT::v16i1)
2333 RC = &X86::VK16RegClass;
2334 else if (RegVT == MVT::v32i1)
2335 RC = &X86::VK32RegClass;
2336 else if (RegVT == MVT::v64i1)
2337 RC = &X86::VK64RegClass;
2339 llvm_unreachable("Unknown argument type!");
2341 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2342 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2344 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2345 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2347 if (VA.getLocInfo() == CCValAssign::SExt)
2348 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2349 DAG.getValueType(VA.getValVT()));
2350 else if (VA.getLocInfo() == CCValAssign::ZExt)
2351 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2352 DAG.getValueType(VA.getValVT()));
2353 else if (VA.getLocInfo() == CCValAssign::BCvt)
2354 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2356 if (VA.isExtInLoc()) {
2357 // Handle MMX values passed in XMM regs.
2358 if (RegVT.isVector())
2359 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2361 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2364 assert(VA.isMemLoc());
2365 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2368 // If value is passed via pointer - do a load.
2369 if (VA.getLocInfo() == CCValAssign::Indirect)
2370 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2371 MachinePointerInfo(), false, false, false, 0);
2373 InVals.push_back(ArgValue);
2376 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2377 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2378 // The x86-64 ABIs require that for returning structs by value we copy
2379 // the sret argument into %rax/%eax (depending on ABI) for the return.
2380 // Win32 requires us to put the sret argument to %eax as well.
2381 // Save the argument into a virtual register so that we can access it
2382 // from the return points.
2383 if (Ins[i].Flags.isSRet()) {
2384 unsigned Reg = FuncInfo->getSRetReturnReg();
2386 MVT PtrTy = getPointerTy();
2387 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2388 FuncInfo->setSRetReturnReg(Reg);
2390 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2391 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2397 unsigned StackSize = CCInfo.getNextStackOffset();
2398 // Align stack specially for tail calls.
2399 if (FuncIsMadeTailCallSafe(CallConv,
2400 MF.getTarget().Options.GuaranteedTailCallOpt))
2401 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2403 // If the function takes variable number of arguments, make a frame index for
2404 // the start of the first vararg value... for expansion of llvm.va_start.
2406 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2407 CallConv != CallingConv::X86_ThisCall)) {
2408 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2411 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2413 // FIXME: We should really autogenerate these arrays
2414 static const MCPhysReg GPR64ArgRegsWin64[] = {
2415 X86::RCX, X86::RDX, X86::R8, X86::R9
2417 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2418 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2420 static const MCPhysReg XMMArgRegs64Bit[] = {
2421 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2422 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2424 const MCPhysReg *GPR64ArgRegs;
2425 unsigned NumXMMRegs = 0;
2428 // The XMM registers which might contain var arg parameters are shadowed
2429 // in their paired GPR. So we only need to save the GPR to their home
2431 TotalNumIntRegs = 4;
2432 GPR64ArgRegs = GPR64ArgRegsWin64;
2434 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2435 GPR64ArgRegs = GPR64ArgRegs64Bit;
2437 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2440 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2443 bool NoImplicitFloatOps = Fn->getAttributes().
2444 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2445 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2446 "SSE register cannot be used when SSE is disabled!");
2447 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2448 NoImplicitFloatOps) &&
2449 "SSE register cannot be used when SSE is disabled!");
2450 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2451 !Subtarget->hasSSE1())
2452 // Kernel mode asks for SSE to be disabled, so don't push them
2454 TotalNumXMMRegs = 0;
2457 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2458 // Get to the caller-allocated home save location. Add 8 to account
2459 // for the return address.
2460 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2461 FuncInfo->setRegSaveFrameIndex(
2462 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2463 // Fixup to set vararg frame on shadow area (4 x i64).
2465 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2467 // For X86-64, if there are vararg parameters that are passed via
2468 // registers, then we must store them to their spots on the stack so
2469 // they may be loaded by deferencing the result of va_next.
2470 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2471 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2472 FuncInfo->setRegSaveFrameIndex(
2473 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2477 // Store the integer parameter registers.
2478 SmallVector<SDValue, 8> MemOps;
2479 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2481 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2482 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2483 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2484 DAG.getIntPtrConstant(Offset));
2485 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2486 &X86::GR64RegClass);
2487 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2489 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2490 MachinePointerInfo::getFixedStack(
2491 FuncInfo->getRegSaveFrameIndex(), Offset),
2493 MemOps.push_back(Store);
2497 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2498 // Now store the XMM (fp + vector) parameter registers.
2499 SmallVector<SDValue, 11> SaveXMMOps;
2500 SaveXMMOps.push_back(Chain);
2502 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2503 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2504 SaveXMMOps.push_back(ALVal);
2506 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2507 FuncInfo->getRegSaveFrameIndex()));
2508 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2509 FuncInfo->getVarArgsFPOffset()));
2511 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2512 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2513 &X86::VR128RegClass);
2514 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2515 SaveXMMOps.push_back(Val);
2517 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2518 MVT::Other, SaveXMMOps));
2521 if (!MemOps.empty())
2522 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2526 // Some CCs need callee pop.
2527 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2528 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2529 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2531 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2532 // If this is an sret function, the return should pop the hidden pointer.
2533 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2534 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2535 argsAreStructReturn(Ins) == StackStructReturn)
2536 FuncInfo->setBytesToPopOnReturn(4);
2540 // RegSaveFrameIndex is X86-64 only.
2541 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2542 if (CallConv == CallingConv::X86_FastCall ||
2543 CallConv == CallingConv::X86_ThisCall)
2544 // fastcc functions can't have varargs.
2545 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2548 FuncInfo->setArgumentStackSize(StackSize);
2554 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2555 SDValue StackPtr, SDValue Arg,
2556 SDLoc dl, SelectionDAG &DAG,
2557 const CCValAssign &VA,
2558 ISD::ArgFlagsTy Flags) const {
2559 unsigned LocMemOffset = VA.getLocMemOffset();
2560 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2561 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2562 if (Flags.isByVal())
2563 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2565 return DAG.getStore(Chain, dl, Arg, PtrOff,
2566 MachinePointerInfo::getStack(LocMemOffset),
2570 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2571 /// optimization is performed and it is required.
2573 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2574 SDValue &OutRetAddr, SDValue Chain,
2575 bool IsTailCall, bool Is64Bit,
2576 int FPDiff, SDLoc dl) const {
2577 // Adjust the Return address stack slot.
2578 EVT VT = getPointerTy();
2579 OutRetAddr = getReturnAddressFrameIndex(DAG);
2581 // Load the "old" Return address.
2582 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2583 false, false, false, 0);
2584 return SDValue(OutRetAddr.getNode(), 1);
2587 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2588 /// optimization is performed and it is required (FPDiff!=0).
2589 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2590 SDValue Chain, SDValue RetAddrFrIdx,
2591 EVT PtrVT, unsigned SlotSize,
2592 int FPDiff, SDLoc dl) {
2593 // Store the return address to the appropriate stack slot.
2594 if (!FPDiff) return Chain;
2595 // Calculate the new stack slot for the return address.
2596 int NewReturnAddrFI =
2597 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2599 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2600 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2601 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2607 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2608 SmallVectorImpl<SDValue> &InVals) const {
2609 SelectionDAG &DAG = CLI.DAG;
2611 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2612 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2613 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2614 SDValue Chain = CLI.Chain;
2615 SDValue Callee = CLI.Callee;
2616 CallingConv::ID CallConv = CLI.CallConv;
2617 bool &isTailCall = CLI.IsTailCall;
2618 bool isVarArg = CLI.IsVarArg;
2620 MachineFunction &MF = DAG.getMachineFunction();
2621 bool Is64Bit = Subtarget->is64Bit();
2622 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2623 StructReturnType SR = callIsStructReturn(Outs);
2624 bool IsSibcall = false;
2626 if (MF.getTarget().Options.DisableTailCalls)
2629 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2631 // Force this to be a tail call. The verifier rules are enough to ensure
2632 // that we can lower this successfully without moving the return address
2635 } else if (isTailCall) {
2636 // Check if it's really possible to do a tail call.
2637 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2638 isVarArg, SR != NotStructReturn,
2639 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2640 Outs, OutVals, Ins, DAG);
2642 // Sibcalls are automatically detected tailcalls which do not require
2644 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2651 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2652 "Var args not supported with calling convention fastcc, ghc or hipe");
2654 // Analyze operands of the call, assigning locations to each operand.
2655 SmallVector<CCValAssign, 16> ArgLocs;
2656 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2658 // Allocate shadow area for Win64
2660 CCInfo.AllocateStack(32, 8);
2662 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2664 // Get a count of how many bytes are to be pushed on the stack.
2665 unsigned NumBytes = CCInfo.getNextStackOffset();
2667 // This is a sibcall. The memory operands are available in caller's
2668 // own caller's stack.
2670 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2671 IsTailCallConvention(CallConv))
2672 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2675 if (isTailCall && !IsSibcall && !IsMustTail) {
2676 // Lower arguments at fp - stackoffset + fpdiff.
2677 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2678 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2680 FPDiff = NumBytesCallerPushed - NumBytes;
2682 // Set the delta of movement of the returnaddr stackslot.
2683 // But only set if delta is greater than previous delta.
2684 if (FPDiff < X86Info->getTCReturnAddrDelta())
2685 X86Info->setTCReturnAddrDelta(FPDiff);
2688 unsigned NumBytesToPush = NumBytes;
2689 unsigned NumBytesToPop = NumBytes;
2691 // If we have an inalloca argument, all stack space has already been allocated
2692 // for us and be right at the top of the stack. We don't support multiple
2693 // arguments passed in memory when using inalloca.
2694 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2696 if (!ArgLocs.back().isMemLoc())
2697 report_fatal_error("cannot use inalloca attribute on a register "
2699 if (ArgLocs.back().getLocMemOffset() != 0)
2700 report_fatal_error("any parameter with the inalloca attribute must be "
2701 "the only memory argument");
2705 Chain = DAG.getCALLSEQ_START(
2706 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2708 SDValue RetAddrFrIdx;
2709 // Load return address for tail calls.
2710 if (isTailCall && FPDiff)
2711 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2712 Is64Bit, FPDiff, dl);
2714 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2715 SmallVector<SDValue, 8> MemOpChains;
2718 // Walk the register/memloc assignments, inserting copies/loads. In the case
2719 // of tail call optimization arguments are handle later.
2720 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2721 DAG.getSubtarget().getRegisterInfo());
2722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2723 // Skip inalloca arguments, they have already been written.
2724 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2725 if (Flags.isInAlloca())
2728 CCValAssign &VA = ArgLocs[i];
2729 EVT RegVT = VA.getLocVT();
2730 SDValue Arg = OutVals[i];
2731 bool isByVal = Flags.isByVal();
2733 // Promote the value if needed.
2734 switch (VA.getLocInfo()) {
2735 default: llvm_unreachable("Unknown loc info!");
2736 case CCValAssign::Full: break;
2737 case CCValAssign::SExt:
2738 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2740 case CCValAssign::ZExt:
2741 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2743 case CCValAssign::AExt:
2744 if (RegVT.is128BitVector()) {
2745 // Special case: passing MMX values in XMM registers.
2746 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2747 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2748 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2750 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2752 case CCValAssign::BCvt:
2753 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2755 case CCValAssign::Indirect: {
2756 // Store the argument.
2757 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2758 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2759 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2760 MachinePointerInfo::getFixedStack(FI),
2767 if (VA.isRegLoc()) {
2768 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2769 if (isVarArg && IsWin64) {
2770 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2771 // shadow reg if callee is a varargs function.
2772 unsigned ShadowReg = 0;
2773 switch (VA.getLocReg()) {
2774 case X86::XMM0: ShadowReg = X86::RCX; break;
2775 case X86::XMM1: ShadowReg = X86::RDX; break;
2776 case X86::XMM2: ShadowReg = X86::R8; break;
2777 case X86::XMM3: ShadowReg = X86::R9; break;
2780 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2782 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2783 assert(VA.isMemLoc());
2784 if (!StackPtr.getNode())
2785 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2787 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2788 dl, DAG, VA, Flags));
2792 if (!MemOpChains.empty())
2793 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2795 if (Subtarget->isPICStyleGOT()) {
2796 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2799 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2800 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2802 // If we are tail calling and generating PIC/GOT style code load the
2803 // address of the callee into ECX. The value in ecx is used as target of
2804 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2805 // for tail calls on PIC/GOT architectures. Normally we would just put the
2806 // address of GOT into ebx and then call target@PLT. But for tail calls
2807 // ebx would be restored (since ebx is callee saved) before jumping to the
2810 // Note: The actual moving to ECX is done further down.
2811 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2812 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2813 !G->getGlobal()->hasProtectedVisibility())
2814 Callee = LowerGlobalAddress(Callee, DAG);
2815 else if (isa<ExternalSymbolSDNode>(Callee))
2816 Callee = LowerExternalSymbol(Callee, DAG);
2820 if (Is64Bit && isVarArg && !IsWin64) {
2821 // From AMD64 ABI document:
2822 // For calls that may call functions that use varargs or stdargs
2823 // (prototype-less calls or calls to functions containing ellipsis (...) in
2824 // the declaration) %al is used as hidden argument to specify the number
2825 // of SSE registers used. The contents of %al do not need to match exactly
2826 // the number of registers, but must be an ubound on the number of SSE
2827 // registers used and is in the range 0 - 8 inclusive.
2829 // Count the number of XMM registers allocated.
2830 static const MCPhysReg XMMArgRegs[] = {
2831 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2832 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2834 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2835 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2836 && "SSE registers cannot be used when SSE is disabled");
2838 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2839 DAG.getConstant(NumXMMRegs, MVT::i8)));
2842 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2843 // don't need this because the eligibility check rejects calls that require
2844 // shuffling arguments passed in memory.
2845 if (!IsSibcall && isTailCall) {
2846 // Force all the incoming stack arguments to be loaded from the stack
2847 // before any new outgoing arguments are stored to the stack, because the
2848 // outgoing stack slots may alias the incoming argument stack slots, and
2849 // the alias isn't otherwise explicit. This is slightly more conservative
2850 // than necessary, because it means that each store effectively depends
2851 // on every argument instead of just those arguments it would clobber.
2852 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2854 SmallVector<SDValue, 8> MemOpChains2;
2857 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2858 CCValAssign &VA = ArgLocs[i];
2861 assert(VA.isMemLoc());
2862 SDValue Arg = OutVals[i];
2863 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2864 // Skip inalloca arguments. They don't require any work.
2865 if (Flags.isInAlloca())
2867 // Create frame index.
2868 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2869 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2870 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2871 FIN = DAG.getFrameIndex(FI, getPointerTy());
2873 if (Flags.isByVal()) {
2874 // Copy relative to framepointer.
2875 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2876 if (!StackPtr.getNode())
2877 StackPtr = DAG.getCopyFromReg(Chain, dl,
2878 RegInfo->getStackRegister(),
2880 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2882 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2886 // Store relative to framepointer.
2887 MemOpChains2.push_back(
2888 DAG.getStore(ArgChain, dl, Arg, FIN,
2889 MachinePointerInfo::getFixedStack(FI),
2894 if (!MemOpChains2.empty())
2895 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2897 // Store the return address to the appropriate stack slot.
2898 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2899 getPointerTy(), RegInfo->getSlotSize(),
2903 // Build a sequence of copy-to-reg nodes chained together with token chain
2904 // and flag operands which copy the outgoing args into registers.
2906 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2907 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2908 RegsToPass[i].second, InFlag);
2909 InFlag = Chain.getValue(1);
2912 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2913 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2914 // In the 64-bit large code model, we have to make all calls
2915 // through a register, since the call instruction's 32-bit
2916 // pc-relative offset may not be large enough to hold the whole
2918 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2919 // If the callee is a GlobalAddress node (quite common, every direct call
2920 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2923 // We should use extra load for direct calls to dllimported functions in
2925 const GlobalValue *GV = G->getGlobal();
2926 if (!GV->hasDLLImportStorageClass()) {
2927 unsigned char OpFlags = 0;
2928 bool ExtraLoad = false;
2929 unsigned WrapperKind = ISD::DELETED_NODE;
2931 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2932 // external symbols most go through the PLT in PIC mode. If the symbol
2933 // has hidden or protected visibility, or if it is static or local, then
2934 // we don't need to use the PLT - we can directly call it.
2935 if (Subtarget->isTargetELF() &&
2936 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2937 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2938 OpFlags = X86II::MO_PLT;
2939 } else if (Subtarget->isPICStyleStubAny() &&
2940 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2941 (!Subtarget->getTargetTriple().isMacOSX() ||
2942 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2943 // PC-relative references to external symbols should go through $stub,
2944 // unless we're building with the leopard linker or later, which
2945 // automatically synthesizes these stubs.
2946 OpFlags = X86II::MO_DARWIN_STUB;
2947 } else if (Subtarget->isPICStyleRIPRel() &&
2948 isa<Function>(GV) &&
2949 cast<Function>(GV)->getAttributes().
2950 hasAttribute(AttributeSet::FunctionIndex,
2951 Attribute::NonLazyBind)) {
2952 // If the function is marked as non-lazy, generate an indirect call
2953 // which loads from the GOT directly. This avoids runtime overhead
2954 // at the cost of eager binding (and one extra byte of encoding).
2955 OpFlags = X86II::MO_GOTPCREL;
2956 WrapperKind = X86ISD::WrapperRIP;
2960 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2961 G->getOffset(), OpFlags);
2963 // Add a wrapper if needed.
2964 if (WrapperKind != ISD::DELETED_NODE)
2965 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2966 // Add extra indirection if needed.
2968 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2969 MachinePointerInfo::getGOT(),
2970 false, false, false, 0);
2972 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2973 unsigned char OpFlags = 0;
2975 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2976 // external symbols should go through the PLT.
2977 if (Subtarget->isTargetELF() &&
2978 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2979 OpFlags = X86II::MO_PLT;
2980 } else if (Subtarget->isPICStyleStubAny() &&
2981 (!Subtarget->getTargetTriple().isMacOSX() ||
2982 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2983 // PC-relative references to external symbols should go through $stub,
2984 // unless we're building with the leopard linker or later, which
2985 // automatically synthesizes these stubs.
2986 OpFlags = X86II::MO_DARWIN_STUB;
2989 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2993 // Returns a chain & a flag for retval copy to use.
2994 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2995 SmallVector<SDValue, 8> Ops;
2997 if (!IsSibcall && isTailCall) {
2998 Chain = DAG.getCALLSEQ_END(Chain,
2999 DAG.getIntPtrConstant(NumBytesToPop, true),
3000 DAG.getIntPtrConstant(0, true), InFlag, dl);
3001 InFlag = Chain.getValue(1);
3004 Ops.push_back(Chain);
3005 Ops.push_back(Callee);
3008 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3010 // Add argument registers to the end of the list so that they are known live
3012 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3013 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3014 RegsToPass[i].second.getValueType()));
3016 // Add a register mask operand representing the call-preserved registers.
3017 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3018 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3019 assert(Mask && "Missing call preserved mask for calling convention");
3020 Ops.push_back(DAG.getRegisterMask(Mask));
3022 if (InFlag.getNode())
3023 Ops.push_back(InFlag);
3027 //// If this is the first return lowered for this function, add the regs
3028 //// to the liveout set for the function.
3029 // This isn't right, although it's probably harmless on x86; liveouts
3030 // should be computed from returns not tail calls. Consider a void
3031 // function making a tail call to a function returning int.
3032 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3035 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3036 InFlag = Chain.getValue(1);
3038 // Create the CALLSEQ_END node.
3039 unsigned NumBytesForCalleeToPop;
3040 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3041 DAG.getTarget().Options.GuaranteedTailCallOpt))
3042 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3043 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3044 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3045 SR == StackStructReturn)
3046 // If this is a call to a struct-return function, the callee
3047 // pops the hidden struct pointer, so we have to push it back.
3048 // This is common for Darwin/X86, Linux & Mingw32 targets.
3049 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3050 NumBytesForCalleeToPop = 4;
3052 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3054 // Returns a flag for retval copy to use.
3056 Chain = DAG.getCALLSEQ_END(Chain,
3057 DAG.getIntPtrConstant(NumBytesToPop, true),
3058 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3061 InFlag = Chain.getValue(1);
3064 // Handle result values, copying them out of physregs into vregs that we
3066 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3067 Ins, dl, DAG, InVals);
3070 //===----------------------------------------------------------------------===//
3071 // Fast Calling Convention (tail call) implementation
3072 //===----------------------------------------------------------------------===//
3074 // Like std call, callee cleans arguments, convention except that ECX is
3075 // reserved for storing the tail called function address. Only 2 registers are
3076 // free for argument passing (inreg). Tail call optimization is performed
3078 // * tailcallopt is enabled
3079 // * caller/callee are fastcc
3080 // On X86_64 architecture with GOT-style position independent code only local
3081 // (within module) calls are supported at the moment.
3082 // To keep the stack aligned according to platform abi the function
3083 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3084 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3085 // If a tail called function callee has more arguments than the caller the
3086 // caller needs to make sure that there is room to move the RETADDR to. This is
3087 // achieved by reserving an area the size of the argument delta right after the
3088 // original RETADDR, but before the saved framepointer or the spilled registers
3089 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3101 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3102 /// for a 16 byte align requirement.
3104 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3105 SelectionDAG& DAG) const {
3106 MachineFunction &MF = DAG.getMachineFunction();
3107 const TargetMachine &TM = MF.getTarget();
3108 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3109 TM.getSubtargetImpl()->getRegisterInfo());
3110 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3111 unsigned StackAlignment = TFI.getStackAlignment();
3112 uint64_t AlignMask = StackAlignment - 1;
3113 int64_t Offset = StackSize;
3114 unsigned SlotSize = RegInfo->getSlotSize();
3115 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3116 // Number smaller than 12 so just add the difference.
3117 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3119 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3120 Offset = ((~AlignMask) & Offset) + StackAlignment +
3121 (StackAlignment-SlotSize);
3126 /// MatchingStackOffset - Return true if the given stack call argument is
3127 /// already available in the same position (relatively) of the caller's
3128 /// incoming argument stack.
3130 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3131 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3132 const X86InstrInfo *TII) {
3133 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3135 if (Arg.getOpcode() == ISD::CopyFromReg) {
3136 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3137 if (!TargetRegisterInfo::isVirtualRegister(VR))
3139 MachineInstr *Def = MRI->getVRegDef(VR);
3142 if (!Flags.isByVal()) {
3143 if (!TII->isLoadFromStackSlot(Def, FI))
3146 unsigned Opcode = Def->getOpcode();
3147 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3148 Def->getOperand(1).isFI()) {
3149 FI = Def->getOperand(1).getIndex();
3150 Bytes = Flags.getByValSize();
3154 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3155 if (Flags.isByVal())
3156 // ByVal argument is passed in as a pointer but it's now being
3157 // dereferenced. e.g.
3158 // define @foo(%struct.X* %A) {
3159 // tail call @bar(%struct.X* byval %A)
3162 SDValue Ptr = Ld->getBasePtr();
3163 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3166 FI = FINode->getIndex();
3167 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3168 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3169 FI = FINode->getIndex();
3170 Bytes = Flags.getByValSize();
3174 assert(FI != INT_MAX);
3175 if (!MFI->isFixedObjectIndex(FI))
3177 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3180 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3181 /// for tail call optimization. Targets which want to do tail call
3182 /// optimization should implement this function.
3184 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3185 CallingConv::ID CalleeCC,
3187 bool isCalleeStructRet,
3188 bool isCallerStructRet,
3190 const SmallVectorImpl<ISD::OutputArg> &Outs,
3191 const SmallVectorImpl<SDValue> &OutVals,
3192 const SmallVectorImpl<ISD::InputArg> &Ins,
3193 SelectionDAG &DAG) const {
3194 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3197 // If -tailcallopt is specified, make fastcc functions tail-callable.
3198 const MachineFunction &MF = DAG.getMachineFunction();
3199 const Function *CallerF = MF.getFunction();
3201 // If the function return type is x86_fp80 and the callee return type is not,
3202 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3203 // perform a tailcall optimization here.
3204 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3207 CallingConv::ID CallerCC = CallerF->getCallingConv();
3208 bool CCMatch = CallerCC == CalleeCC;
3209 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3210 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3212 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3213 if (IsTailCallConvention(CalleeCC) && CCMatch)
3218 // Look for obvious safe cases to perform tail call optimization that do not
3219 // require ABI changes. This is what gcc calls sibcall.
3221 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3222 // emit a special epilogue.
3223 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3224 DAG.getSubtarget().getRegisterInfo());
3225 if (RegInfo->needsStackRealignment(MF))
3228 // Also avoid sibcall optimization if either caller or callee uses struct
3229 // return semantics.
3230 if (isCalleeStructRet || isCallerStructRet)
3233 // An stdcall/thiscall caller is expected to clean up its arguments; the
3234 // callee isn't going to do that.
3235 // FIXME: this is more restrictive than needed. We could produce a tailcall
3236 // when the stack adjustment matches. For example, with a thiscall that takes
3237 // only one argument.
3238 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3239 CallerCC == CallingConv::X86_ThisCall))
3242 // Do not sibcall optimize vararg calls unless all arguments are passed via
3244 if (isVarArg && !Outs.empty()) {
3246 // Optimizing for varargs on Win64 is unlikely to be safe without
3247 // additional testing.
3248 if (IsCalleeWin64 || IsCallerWin64)
3251 SmallVector<CCValAssign, 16> ArgLocs;
3252 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3255 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3256 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3257 if (!ArgLocs[i].isRegLoc())
3261 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3262 // stack. Therefore, if it's not used by the call it is not safe to optimize
3263 // this into a sibcall.
3264 bool Unused = false;
3265 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3272 SmallVector<CCValAssign, 16> RVLocs;
3273 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3275 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3276 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3277 CCValAssign &VA = RVLocs[i];
3278 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3283 // If the calling conventions do not match, then we'd better make sure the
3284 // results are returned in the same way as what the caller expects.
3286 SmallVector<CCValAssign, 16> RVLocs1;
3287 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3289 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3291 SmallVector<CCValAssign, 16> RVLocs2;
3292 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3294 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3296 if (RVLocs1.size() != RVLocs2.size())
3298 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3299 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3301 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3303 if (RVLocs1[i].isRegLoc()) {
3304 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3307 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3313 // If the callee takes no arguments then go on to check the results of the
3315 if (!Outs.empty()) {
3316 // Check if stack adjustment is needed. For now, do not do this if any
3317 // argument is passed on the stack.
3318 SmallVector<CCValAssign, 16> ArgLocs;
3319 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3322 // Allocate shadow area for Win64
3324 CCInfo.AllocateStack(32, 8);
3326 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3327 if (CCInfo.getNextStackOffset()) {
3328 MachineFunction &MF = DAG.getMachineFunction();
3329 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3332 // Check if the arguments are already laid out in the right way as
3333 // the caller's fixed stack objects.
3334 MachineFrameInfo *MFI = MF.getFrameInfo();
3335 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3336 const X86InstrInfo *TII =
3337 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3338 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3339 CCValAssign &VA = ArgLocs[i];
3340 SDValue Arg = OutVals[i];
3341 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3342 if (VA.getLocInfo() == CCValAssign::Indirect)
3344 if (!VA.isRegLoc()) {
3345 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3352 // If the tailcall address may be in a register, then make sure it's
3353 // possible to register allocate for it. In 32-bit, the call address can
3354 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3355 // callee-saved registers are restored. These happen to be the same
3356 // registers used to pass 'inreg' arguments so watch out for those.
3357 if (!Subtarget->is64Bit() &&
3358 ((!isa<GlobalAddressSDNode>(Callee) &&
3359 !isa<ExternalSymbolSDNode>(Callee)) ||
3360 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3361 unsigned NumInRegs = 0;
3362 // In PIC we need an extra register to formulate the address computation
3364 unsigned MaxInRegs =
3365 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3367 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3368 CCValAssign &VA = ArgLocs[i];
3371 unsigned Reg = VA.getLocReg();
3374 case X86::EAX: case X86::EDX: case X86::ECX:
3375 if (++NumInRegs == MaxInRegs)
3387 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3388 const TargetLibraryInfo *libInfo) const {
3389 return X86::createFastISel(funcInfo, libInfo);
3392 //===----------------------------------------------------------------------===//
3393 // Other Lowering Hooks
3394 //===----------------------------------------------------------------------===//
3396 static bool MayFoldLoad(SDValue Op) {
3397 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3400 static bool MayFoldIntoStore(SDValue Op) {
3401 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3404 static bool isTargetShuffle(unsigned Opcode) {
3406 default: return false;
3407 case X86ISD::PSHUFB:
3408 case X86ISD::PSHUFD:
3409 case X86ISD::PSHUFHW:
3410 case X86ISD::PSHUFLW:
3412 case X86ISD::PALIGNR:
3413 case X86ISD::MOVLHPS:
3414 case X86ISD::MOVLHPD:
3415 case X86ISD::MOVHLPS:
3416 case X86ISD::MOVLPS:
3417 case X86ISD::MOVLPD:
3418 case X86ISD::MOVSHDUP:
3419 case X86ISD::MOVSLDUP:
3420 case X86ISD::MOVDDUP:
3423 case X86ISD::UNPCKL:
3424 case X86ISD::UNPCKH:
3425 case X86ISD::VPERMILP:
3426 case X86ISD::VPERM2X128:
3427 case X86ISD::VPERMI:
3432 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3433 SDValue V1, SelectionDAG &DAG) {
3435 default: llvm_unreachable("Unknown x86 shuffle node");
3436 case X86ISD::MOVSHDUP:
3437 case X86ISD::MOVSLDUP:
3438 case X86ISD::MOVDDUP:
3439 return DAG.getNode(Opc, dl, VT, V1);
3443 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3444 SDValue V1, unsigned TargetMask,
3445 SelectionDAG &DAG) {
3447 default: llvm_unreachable("Unknown x86 shuffle node");
3448 case X86ISD::PSHUFD:
3449 case X86ISD::PSHUFHW:
3450 case X86ISD::PSHUFLW:
3451 case X86ISD::VPERMILP:
3452 case X86ISD::VPERMI:
3453 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3457 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3458 SDValue V1, SDValue V2, unsigned TargetMask,
3459 SelectionDAG &DAG) {
3461 default: llvm_unreachable("Unknown x86 shuffle node");
3462 case X86ISD::PALIGNR:
3463 case X86ISD::VALIGN:
3465 case X86ISD::VPERM2X128:
3466 return DAG.getNode(Opc, dl, VT, V1, V2,
3467 DAG.getConstant(TargetMask, MVT::i8));
3471 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3472 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3474 default: llvm_unreachable("Unknown x86 shuffle node");
3475 case X86ISD::MOVLHPS:
3476 case X86ISD::MOVLHPD:
3477 case X86ISD::MOVHLPS:
3478 case X86ISD::MOVLPS:
3479 case X86ISD::MOVLPD:
3482 case X86ISD::UNPCKL:
3483 case X86ISD::UNPCKH:
3484 return DAG.getNode(Opc, dl, VT, V1, V2);
3488 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3489 MachineFunction &MF = DAG.getMachineFunction();
3490 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3491 DAG.getSubtarget().getRegisterInfo());
3492 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3493 int ReturnAddrIndex = FuncInfo->getRAIndex();
3495 if (ReturnAddrIndex == 0) {
3496 // Set up a frame object for the return address.
3497 unsigned SlotSize = RegInfo->getSlotSize();
3498 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3501 FuncInfo->setRAIndex(ReturnAddrIndex);
3504 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3507 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3508 bool hasSymbolicDisplacement) {
3509 // Offset should fit into 32 bit immediate field.
3510 if (!isInt<32>(Offset))
3513 // If we don't have a symbolic displacement - we don't have any extra
3515 if (!hasSymbolicDisplacement)
3518 // FIXME: Some tweaks might be needed for medium code model.
3519 if (M != CodeModel::Small && M != CodeModel::Kernel)
3522 // For small code model we assume that latest object is 16MB before end of 31
3523 // bits boundary. We may also accept pretty large negative constants knowing
3524 // that all objects are in the positive half of address space.
3525 if (M == CodeModel::Small && Offset < 16*1024*1024)
3528 // For kernel code model we know that all object resist in the negative half
3529 // of 32bits address space. We may not accept negative offsets, since they may
3530 // be just off and we may accept pretty large positive ones.
3531 if (M == CodeModel::Kernel && Offset > 0)
3537 /// isCalleePop - Determines whether the callee is required to pop its
3538 /// own arguments. Callee pop is necessary to support tail calls.
3539 bool X86::isCalleePop(CallingConv::ID CallingConv,
3540 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3544 switch (CallingConv) {
3547 case CallingConv::X86_StdCall:
3549 case CallingConv::X86_FastCall:
3551 case CallingConv::X86_ThisCall:
3553 case CallingConv::Fast:
3555 case CallingConv::GHC:
3557 case CallingConv::HiPE:
3562 /// \brief Return true if the condition is an unsigned comparison operation.
3563 static bool isX86CCUnsigned(unsigned X86CC) {
3565 default: llvm_unreachable("Invalid integer condition!");
3566 case X86::COND_E: return true;
3567 case X86::COND_G: return false;
3568 case X86::COND_GE: return false;
3569 case X86::COND_L: return false;
3570 case X86::COND_LE: return false;
3571 case X86::COND_NE: return true;
3572 case X86::COND_B: return true;
3573 case X86::COND_A: return true;
3574 case X86::COND_BE: return true;
3575 case X86::COND_AE: return true;
3577 llvm_unreachable("covered switch fell through?!");
3580 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3581 /// specific condition code, returning the condition code and the LHS/RHS of the
3582 /// comparison to make.
3583 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3584 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3586 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3587 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3588 // X > -1 -> X == 0, jump !sign.
3589 RHS = DAG.getConstant(0, RHS.getValueType());
3590 return X86::COND_NS;
3592 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3593 // X < 0 -> X == 0, jump on sign.
3596 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3598 RHS = DAG.getConstant(0, RHS.getValueType());
3599 return X86::COND_LE;
3603 switch (SetCCOpcode) {
3604 default: llvm_unreachable("Invalid integer condition!");
3605 case ISD::SETEQ: return X86::COND_E;
3606 case ISD::SETGT: return X86::COND_G;
3607 case ISD::SETGE: return X86::COND_GE;
3608 case ISD::SETLT: return X86::COND_L;
3609 case ISD::SETLE: return X86::COND_LE;
3610 case ISD::SETNE: return X86::COND_NE;
3611 case ISD::SETULT: return X86::COND_B;
3612 case ISD::SETUGT: return X86::COND_A;
3613 case ISD::SETULE: return X86::COND_BE;
3614 case ISD::SETUGE: return X86::COND_AE;
3618 // First determine if it is required or is profitable to flip the operands.
3620 // If LHS is a foldable load, but RHS is not, flip the condition.
3621 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3622 !ISD::isNON_EXTLoad(RHS.getNode())) {
3623 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3624 std::swap(LHS, RHS);
3627 switch (SetCCOpcode) {
3633 std::swap(LHS, RHS);
3637 // On a floating point condition, the flags are set as follows:
3639 // 0 | 0 | 0 | X > Y
3640 // 0 | 0 | 1 | X < Y
3641 // 1 | 0 | 0 | X == Y
3642 // 1 | 1 | 1 | unordered
3643 switch (SetCCOpcode) {
3644 default: llvm_unreachable("Condcode should be pre-legalized away");
3646 case ISD::SETEQ: return X86::COND_E;
3647 case ISD::SETOLT: // flipped
3649 case ISD::SETGT: return X86::COND_A;
3650 case ISD::SETOLE: // flipped
3652 case ISD::SETGE: return X86::COND_AE;
3653 case ISD::SETUGT: // flipped
3655 case ISD::SETLT: return X86::COND_B;
3656 case ISD::SETUGE: // flipped
3658 case ISD::SETLE: return X86::COND_BE;
3660 case ISD::SETNE: return X86::COND_NE;
3661 case ISD::SETUO: return X86::COND_P;
3662 case ISD::SETO: return X86::COND_NP;
3664 case ISD::SETUNE: return X86::COND_INVALID;
3668 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3669 /// code. Current x86 isa includes the following FP cmov instructions:
3670 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3671 static bool hasFPCMov(unsigned X86CC) {
3687 /// isFPImmLegal - Returns true if the target can instruction select the
3688 /// specified FP immediate natively. If false, the legalizer will
3689 /// materialize the FP immediate as a load from a constant pool.
3690 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3691 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3692 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3698 /// \brief Returns true if it is beneficial to convert a load of a constant
3699 /// to just the constant itself.
3700 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3702 assert(Ty->isIntegerTy());
3704 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3705 if (BitSize == 0 || BitSize > 64)
3710 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3711 /// the specified range (L, H].
3712 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3713 return (Val < 0) || (Val >= Low && Val < Hi);
3716 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3717 /// specified value.
3718 static bool isUndefOrEqual(int Val, int CmpVal) {
3719 return (Val < 0 || Val == CmpVal);
3722 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3723 /// from position Pos and ending in Pos+Size, falls within the specified
3724 /// sequential range (L, L+Pos]. or is undef.
3725 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3726 unsigned Pos, unsigned Size, int Low) {
3727 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3728 if (!isUndefOrEqual(Mask[i], Low))
3733 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3734 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3735 /// the second operand.
3736 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3737 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3738 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3739 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3740 return (Mask[0] < 2 && Mask[1] < 2);
3744 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3745 /// is suitable for input to PSHUFHW.
3746 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3747 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3750 // Lower quadword copied in order or undef.
3751 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3754 // Upper quadword shuffled.
3755 for (unsigned i = 4; i != 8; ++i)
3756 if (!isUndefOrInRange(Mask[i], 4, 8))
3759 if (VT == MVT::v16i16) {
3760 // Lower quadword copied in order or undef.
3761 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3764 // Upper quadword shuffled.
3765 for (unsigned i = 12; i != 16; ++i)
3766 if (!isUndefOrInRange(Mask[i], 12, 16))
3773 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3774 /// is suitable for input to PSHUFLW.
3775 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3776 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3779 // Upper quadword copied in order.
3780 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3783 // Lower quadword shuffled.
3784 for (unsigned i = 0; i != 4; ++i)
3785 if (!isUndefOrInRange(Mask[i], 0, 4))
3788 if (VT == MVT::v16i16) {
3789 // Upper quadword copied in order.
3790 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3793 // Lower quadword shuffled.
3794 for (unsigned i = 8; i != 12; ++i)
3795 if (!isUndefOrInRange(Mask[i], 8, 12))
3802 /// \brief Return true if the mask specifies a shuffle of elements that is
3803 /// suitable for input to intralane (palignr) or interlane (valign) vector
3805 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3806 unsigned NumElts = VT.getVectorNumElements();
3807 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3808 unsigned NumLaneElts = NumElts/NumLanes;
3810 // Do not handle 64-bit element shuffles with palignr.
3811 if (NumLaneElts == 2)
3814 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3816 for (i = 0; i != NumLaneElts; ++i) {
3821 // Lane is all undef, go to next lane
3822 if (i == NumLaneElts)
3825 int Start = Mask[i+l];
3827 // Make sure its in this lane in one of the sources
3828 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3829 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3832 // If not lane 0, then we must match lane 0
3833 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3836 // Correct second source to be contiguous with first source
3837 if (Start >= (int)NumElts)
3838 Start -= NumElts - NumLaneElts;
3840 // Make sure we're shifting in the right direction.
3841 if (Start <= (int)(i+l))
3846 // Check the rest of the elements to see if they are consecutive.
3847 for (++i; i != NumLaneElts; ++i) {
3848 int Idx = Mask[i+l];
3850 // Make sure its in this lane
3851 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3852 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3855 // If not lane 0, then we must match lane 0
3856 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3859 if (Idx >= (int)NumElts)
3860 Idx -= NumElts - NumLaneElts;
3862 if (!isUndefOrEqual(Idx, Start+i))
3871 /// \brief Return true if the node specifies a shuffle of elements that is
3872 /// suitable for input to PALIGNR.
3873 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3874 const X86Subtarget *Subtarget) {
3875 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3876 (VT.is256BitVector() && !Subtarget->hasInt256()))
3877 // FIXME: Add AVX512BW.
3880 return isAlignrMask(Mask, VT, false);
3883 /// \brief Return true if the node specifies a shuffle of elements that is
3884 /// suitable for input to VALIGN.
3885 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
3886 const X86Subtarget *Subtarget) {
3887 // FIXME: Add AVX512VL.
3888 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
3890 return isAlignrMask(Mask, VT, true);
3893 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3894 /// the two vector operands have swapped position.
3895 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3896 unsigned NumElems) {
3897 for (unsigned i = 0; i != NumElems; ++i) {
3901 else if (idx < (int)NumElems)
3902 Mask[i] = idx + NumElems;
3904 Mask[i] = idx - NumElems;
3908 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3909 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3910 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3911 /// reverse of what x86 shuffles want.
3912 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3914 unsigned NumElems = VT.getVectorNumElements();
3915 unsigned NumLanes = VT.getSizeInBits()/128;
3916 unsigned NumLaneElems = NumElems/NumLanes;
3918 if (NumLaneElems != 2 && NumLaneElems != 4)
3921 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3922 bool symetricMaskRequired =
3923 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3925 // VSHUFPSY divides the resulting vector into 4 chunks.
3926 // The sources are also splitted into 4 chunks, and each destination
3927 // chunk must come from a different source chunk.
3929 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3930 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3932 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3933 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3935 // VSHUFPDY divides the resulting vector into 4 chunks.
3936 // The sources are also splitted into 4 chunks, and each destination
3937 // chunk must come from a different source chunk.
3939 // SRC1 => X3 X2 X1 X0
3940 // SRC2 => Y3 Y2 Y1 Y0
3942 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3944 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3945 unsigned HalfLaneElems = NumLaneElems/2;
3946 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3947 for (unsigned i = 0; i != NumLaneElems; ++i) {
3948 int Idx = Mask[i+l];
3949 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3950 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3952 // For VSHUFPSY, the mask of the second half must be the same as the
3953 // first but with the appropriate offsets. This works in the same way as
3954 // VPERMILPS works with masks.
3955 if (!symetricMaskRequired || Idx < 0)
3957 if (MaskVal[i] < 0) {
3958 MaskVal[i] = Idx - l;
3961 if ((signed)(Idx - l) != MaskVal[i])
3969 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3970 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3971 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3972 if (!VT.is128BitVector())
3975 unsigned NumElems = VT.getVectorNumElements();
3980 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3981 return isUndefOrEqual(Mask[0], 6) &&
3982 isUndefOrEqual(Mask[1], 7) &&
3983 isUndefOrEqual(Mask[2], 2) &&
3984 isUndefOrEqual(Mask[3], 3);
3987 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3988 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3990 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3991 if (!VT.is128BitVector())
3994 unsigned NumElems = VT.getVectorNumElements();
3999 return isUndefOrEqual(Mask[0], 2) &&
4000 isUndefOrEqual(Mask[1], 3) &&
4001 isUndefOrEqual(Mask[2], 2) &&
4002 isUndefOrEqual(Mask[3], 3);
4005 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4006 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4007 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4008 if (!VT.is128BitVector())
4011 unsigned NumElems = VT.getVectorNumElements();
4013 if (NumElems != 2 && NumElems != 4)
4016 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4017 if (!isUndefOrEqual(Mask[i], i + NumElems))
4020 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4021 if (!isUndefOrEqual(Mask[i], i))
4027 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4028 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4029 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4030 if (!VT.is128BitVector())
4033 unsigned NumElems = VT.getVectorNumElements();
4035 if (NumElems != 2 && NumElems != 4)
4038 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4039 if (!isUndefOrEqual(Mask[i], i))
4042 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4043 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4049 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4050 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4051 /// i. e: If all but one element come from the same vector.
4052 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4053 // TODO: Deal with AVX's VINSERTPS
4054 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4057 unsigned CorrectPosV1 = 0;
4058 unsigned CorrectPosV2 = 0;
4059 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4060 if (Mask[i] == -1) {
4068 else if (Mask[i] == i + 4)
4072 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4073 // We have 3 elements (undefs count as elements from any vector) from one
4074 // vector, and one from another.
4081 // Some special combinations that can be optimized.
4084 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4085 SelectionDAG &DAG) {
4086 MVT VT = SVOp->getSimpleValueType(0);
4089 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4092 ArrayRef<int> Mask = SVOp->getMask();
4094 // These are the special masks that may be optimized.
4095 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4096 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4097 bool MatchEvenMask = true;
4098 bool MatchOddMask = true;
4099 for (int i=0; i<8; ++i) {
4100 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4101 MatchEvenMask = false;
4102 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4103 MatchOddMask = false;
4106 if (!MatchEvenMask && !MatchOddMask)
4109 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4111 SDValue Op0 = SVOp->getOperand(0);
4112 SDValue Op1 = SVOp->getOperand(1);
4114 if (MatchEvenMask) {
4115 // Shift the second operand right to 32 bits.
4116 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4117 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4119 // Shift the first operand left to 32 bits.
4120 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4121 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4123 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4124 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4127 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4128 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4129 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4130 bool HasInt256, bool V2IsSplat = false) {
4132 assert(VT.getSizeInBits() >= 128 &&
4133 "Unsupported vector type for unpckl");
4135 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4137 unsigned NumOf256BitLanes;
4138 unsigned NumElts = VT.getVectorNumElements();
4139 if (VT.is256BitVector()) {
4140 if (NumElts != 4 && NumElts != 8 &&
4141 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4144 NumOf256BitLanes = 1;
4145 } else if (VT.is512BitVector()) {
4146 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4147 "Unsupported vector type for unpckh");
4149 NumOf256BitLanes = 2;
4152 NumOf256BitLanes = 1;
4155 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4156 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4158 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4159 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4160 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4161 int BitI = Mask[l256*NumEltsInStride+l+i];
4162 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4163 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4165 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4167 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4175 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4176 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4177 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4178 bool HasInt256, bool V2IsSplat = false) {
4179 assert(VT.getSizeInBits() >= 128 &&
4180 "Unsupported vector type for unpckh");
4182 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4184 unsigned NumOf256BitLanes;
4185 unsigned NumElts = VT.getVectorNumElements();
4186 if (VT.is256BitVector()) {
4187 if (NumElts != 4 && NumElts != 8 &&
4188 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4191 NumOf256BitLanes = 1;
4192 } else if (VT.is512BitVector()) {
4193 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4194 "Unsupported vector type for unpckh");
4196 NumOf256BitLanes = 2;
4199 NumOf256BitLanes = 1;
4202 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4203 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4205 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4206 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4207 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4208 int BitI = Mask[l256*NumEltsInStride+l+i];
4209 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4210 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4212 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4214 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4222 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4223 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4225 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4226 unsigned NumElts = VT.getVectorNumElements();
4227 bool Is256BitVec = VT.is256BitVector();
4229 if (VT.is512BitVector())
4231 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4232 "Unsupported vector type for unpckh");
4234 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4235 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4238 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4239 // FIXME: Need a better way to get rid of this, there's no latency difference
4240 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4241 // the former later. We should also remove the "_undef" special mask.
4242 if (NumElts == 4 && Is256BitVec)
4245 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4246 // independently on 128-bit lanes.
4247 unsigned NumLanes = VT.getSizeInBits()/128;
4248 unsigned NumLaneElts = NumElts/NumLanes;
4250 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4251 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4252 int BitI = Mask[l+i];
4253 int BitI1 = Mask[l+i+1];
4255 if (!isUndefOrEqual(BitI, j))
4257 if (!isUndefOrEqual(BitI1, j))
4265 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4266 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4268 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4269 unsigned NumElts = VT.getVectorNumElements();
4271 if (VT.is512BitVector())
4274 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4275 "Unsupported vector type for unpckh");
4277 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4278 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4281 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4282 // independently on 128-bit lanes.
4283 unsigned NumLanes = VT.getSizeInBits()/128;
4284 unsigned NumLaneElts = NumElts/NumLanes;
4286 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l+i];
4289 int BitI1 = Mask[l+i+1];
4290 if (!isUndefOrEqual(BitI, j))
4292 if (!isUndefOrEqual(BitI1, j))
4299 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4300 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4301 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4302 if (!VT.is512BitVector())
4305 unsigned NumElts = VT.getVectorNumElements();
4306 unsigned HalfSize = NumElts/2;
4307 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4308 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4313 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4314 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4322 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4324 /// MOVSD, and MOVD, i.e. setting the lowest element.
4325 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4326 if (VT.getVectorElementType().getSizeInBits() < 32)
4328 if (!VT.is128BitVector())
4331 unsigned NumElts = VT.getVectorNumElements();
4333 if (!isUndefOrEqual(Mask[0], NumElts))
4336 for (unsigned i = 1; i != NumElts; ++i)
4337 if (!isUndefOrEqual(Mask[i], i))
4343 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4344 /// as permutations between 128-bit chunks or halves. As an example: this
4346 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4347 /// The first half comes from the second half of V1 and the second half from the
4348 /// the second half of V2.
4349 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4350 if (!HasFp256 || !VT.is256BitVector())
4353 // The shuffle result is divided into half A and half B. In total the two
4354 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4355 // B must come from C, D, E or F.
4356 unsigned HalfSize = VT.getVectorNumElements()/2;
4357 bool MatchA = false, MatchB = false;
4359 // Check if A comes from one of C, D, E, F.
4360 for (unsigned Half = 0; Half != 4; ++Half) {
4361 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4367 // Check if B comes from one of C, D, E, F.
4368 for (unsigned Half = 0; Half != 4; ++Half) {
4369 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4375 return MatchA && MatchB;
4378 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4379 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4380 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4381 MVT VT = SVOp->getSimpleValueType(0);
4383 unsigned HalfSize = VT.getVectorNumElements()/2;
4385 unsigned FstHalf = 0, SndHalf = 0;
4386 for (unsigned i = 0; i < HalfSize; ++i) {
4387 if (SVOp->getMaskElt(i) > 0) {
4388 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4392 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4393 if (SVOp->getMaskElt(i) > 0) {
4394 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4399 return (FstHalf | (SndHalf << 4));
4402 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4403 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4404 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4408 unsigned NumElts = VT.getVectorNumElements();
4410 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4411 for (unsigned i = 0; i != NumElts; ++i) {
4414 Imm8 |= Mask[i] << (i*2);
4419 unsigned LaneSize = 4;
4420 SmallVector<int, 4> MaskVal(LaneSize, -1);
4422 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4423 for (unsigned i = 0; i != LaneSize; ++i) {
4424 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4428 if (MaskVal[i] < 0) {
4429 MaskVal[i] = Mask[i+l] - l;
4430 Imm8 |= MaskVal[i] << (i*2);
4433 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4440 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4441 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4442 /// Note that VPERMIL mask matching is different depending whether theunderlying
4443 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4444 /// to the same elements of the low, but to the higher half of the source.
4445 /// In VPERMILPD the two lanes could be shuffled independently of each other
4446 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4447 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4448 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4449 if (VT.getSizeInBits() < 256 || EltSize < 32)
4451 bool symetricMaskRequired = (EltSize == 32);
4452 unsigned NumElts = VT.getVectorNumElements();
4454 unsigned NumLanes = VT.getSizeInBits()/128;
4455 unsigned LaneSize = NumElts/NumLanes;
4456 // 2 or 4 elements in one lane
4458 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4459 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4460 for (unsigned i = 0; i != LaneSize; ++i) {
4461 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4463 if (symetricMaskRequired) {
4464 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4465 ExpectedMaskVal[i] = Mask[i+l] - l;
4468 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4476 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4477 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4478 /// element of vector 2 and the other elements to come from vector 1 in order.
4479 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4480 bool V2IsSplat = false, bool V2IsUndef = false) {
4481 if (!VT.is128BitVector())
4484 unsigned NumOps = VT.getVectorNumElements();
4485 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4488 if (!isUndefOrEqual(Mask[0], 0))
4491 for (unsigned i = 1; i != NumOps; ++i)
4492 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4493 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4494 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4500 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4501 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4502 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4503 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4504 const X86Subtarget *Subtarget) {
4505 if (!Subtarget->hasSSE3())
4508 unsigned NumElems = VT.getVectorNumElements();
4510 if ((VT.is128BitVector() && NumElems != 4) ||
4511 (VT.is256BitVector() && NumElems != 8) ||
4512 (VT.is512BitVector() && NumElems != 16))
4515 // "i+1" is the value the indexed mask element must have
4516 for (unsigned i = 0; i != NumElems; i += 2)
4517 if (!isUndefOrEqual(Mask[i], i+1) ||
4518 !isUndefOrEqual(Mask[i+1], i+1))
4524 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4525 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4526 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4527 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4528 const X86Subtarget *Subtarget) {
4529 if (!Subtarget->hasSSE3())
4532 unsigned NumElems = VT.getVectorNumElements();
4534 if ((VT.is128BitVector() && NumElems != 4) ||
4535 (VT.is256BitVector() && NumElems != 8) ||
4536 (VT.is512BitVector() && NumElems != 16))
4539 // "i" is the value the indexed mask element must have
4540 for (unsigned i = 0; i != NumElems; i += 2)
4541 if (!isUndefOrEqual(Mask[i], i) ||
4542 !isUndefOrEqual(Mask[i+1], i))
4548 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4549 /// specifies a shuffle of elements that is suitable for input to 256-bit
4550 /// version of MOVDDUP.
4551 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4552 if (!HasFp256 || !VT.is256BitVector())
4555 unsigned NumElts = VT.getVectorNumElements();
4559 for (unsigned i = 0; i != NumElts/2; ++i)
4560 if (!isUndefOrEqual(Mask[i], 0))
4562 for (unsigned i = NumElts/2; i != NumElts; ++i)
4563 if (!isUndefOrEqual(Mask[i], NumElts/2))
4568 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4569 /// specifies a shuffle of elements that is suitable for input to 128-bit
4570 /// version of MOVDDUP.
4571 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4572 if (!VT.is128BitVector())
4575 unsigned e = VT.getVectorNumElements() / 2;
4576 for (unsigned i = 0; i != e; ++i)
4577 if (!isUndefOrEqual(Mask[i], i))
4579 for (unsigned i = 0; i != e; ++i)
4580 if (!isUndefOrEqual(Mask[e+i], i))
4585 /// isVEXTRACTIndex - Return true if the specified
4586 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4587 /// suitable for instruction that extract 128 or 256 bit vectors
4588 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4589 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4590 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4593 // The index should be aligned on a vecWidth-bit boundary.
4595 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4597 MVT VT = N->getSimpleValueType(0);
4598 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4599 bool Result = (Index * ElSize) % vecWidth == 0;
4604 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4605 /// operand specifies a subvector insert that is suitable for input to
4606 /// insertion of 128 or 256-bit subvectors
4607 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4608 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4609 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4611 // The index should be aligned on a vecWidth-bit boundary.
4613 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4615 MVT VT = N->getSimpleValueType(0);
4616 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4617 bool Result = (Index * ElSize) % vecWidth == 0;
4622 bool X86::isVINSERT128Index(SDNode *N) {
4623 return isVINSERTIndex(N, 128);
4626 bool X86::isVINSERT256Index(SDNode *N) {
4627 return isVINSERTIndex(N, 256);
4630 bool X86::isVEXTRACT128Index(SDNode *N) {
4631 return isVEXTRACTIndex(N, 128);
4634 bool X86::isVEXTRACT256Index(SDNode *N) {
4635 return isVEXTRACTIndex(N, 256);
4638 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4639 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4640 /// Handles 128-bit and 256-bit.
4641 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4642 MVT VT = N->getSimpleValueType(0);
4644 assert((VT.getSizeInBits() >= 128) &&
4645 "Unsupported vector type for PSHUF/SHUFP");
4647 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4648 // independently on 128-bit lanes.
4649 unsigned NumElts = VT.getVectorNumElements();
4650 unsigned NumLanes = VT.getSizeInBits()/128;
4651 unsigned NumLaneElts = NumElts/NumLanes;
4653 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4654 "Only supports 2, 4 or 8 elements per lane");
4656 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4658 for (unsigned i = 0; i != NumElts; ++i) {
4659 int Elt = N->getMaskElt(i);
4660 if (Elt < 0) continue;
4661 Elt &= NumLaneElts - 1;
4662 unsigned ShAmt = (i << Shift) % 8;
4663 Mask |= Elt << ShAmt;
4669 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4670 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4671 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4672 MVT VT = N->getSimpleValueType(0);
4674 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4675 "Unsupported vector type for PSHUFHW");
4677 unsigned NumElts = VT.getVectorNumElements();
4680 for (unsigned l = 0; l != NumElts; l += 8) {
4681 // 8 nodes per lane, but we only care about the last 4.
4682 for (unsigned i = 0; i < 4; ++i) {
4683 int Elt = N->getMaskElt(l+i+4);
4684 if (Elt < 0) continue;
4685 Elt &= 0x3; // only 2-bits.
4686 Mask |= Elt << (i * 2);
4693 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4694 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4695 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4696 MVT VT = N->getSimpleValueType(0);
4698 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4699 "Unsupported vector type for PSHUFHW");
4701 unsigned NumElts = VT.getVectorNumElements();
4704 for (unsigned l = 0; l != NumElts; l += 8) {
4705 // 8 nodes per lane, but we only care about the first 4.
4706 for (unsigned i = 0; i < 4; ++i) {
4707 int Elt = N->getMaskElt(l+i);
4708 if (Elt < 0) continue;
4709 Elt &= 0x3; // only 2-bits
4710 Mask |= Elt << (i * 2);
4717 /// \brief Return the appropriate immediate to shuffle the specified
4718 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4719 /// VALIGN (if Interlane is true) instructions.
4720 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4722 MVT VT = SVOp->getSimpleValueType(0);
4723 unsigned EltSize = InterLane ? 1 :
4724 VT.getVectorElementType().getSizeInBits() >> 3;
4726 unsigned NumElts = VT.getVectorNumElements();
4727 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4728 unsigned NumLaneElts = NumElts/NumLanes;
4732 for (i = 0; i != NumElts; ++i) {
4733 Val = SVOp->getMaskElt(i);
4737 if (Val >= (int)NumElts)
4738 Val -= NumElts - NumLaneElts;
4740 assert(Val - i > 0 && "PALIGNR imm should be positive");
4741 return (Val - i) * EltSize;
4744 /// \brief Return the appropriate immediate to shuffle the specified
4745 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4746 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4747 return getShuffleAlignrImmediate(SVOp, false);
4750 /// \brief Return the appropriate immediate to shuffle the specified
4751 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4752 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4753 return getShuffleAlignrImmediate(SVOp, true);
4757 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4758 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4759 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4760 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4763 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4765 MVT VecVT = N->getOperand(0).getSimpleValueType();
4766 MVT ElVT = VecVT.getVectorElementType();
4768 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4769 return Index / NumElemsPerChunk;
4772 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4773 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4774 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4775 llvm_unreachable("Illegal insert subvector for VINSERT");
4778 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4780 MVT VecVT = N->getSimpleValueType(0);
4781 MVT ElVT = VecVT.getVectorElementType();
4783 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4784 return Index / NumElemsPerChunk;
4787 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4788 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4789 /// and VINSERTI128 instructions.
4790 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4791 return getExtractVEXTRACTImmediate(N, 128);
4794 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4795 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4796 /// and VINSERTI64x4 instructions.
4797 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4798 return getExtractVEXTRACTImmediate(N, 256);
4801 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4802 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4803 /// and VINSERTI128 instructions.
4804 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4805 return getInsertVINSERTImmediate(N, 128);
4808 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4809 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4810 /// and VINSERTI64x4 instructions.
4811 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4812 return getInsertVINSERTImmediate(N, 256);
4815 /// isZero - Returns true if Elt is a constant integer zero
4816 static bool isZero(SDValue V) {
4817 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4818 return C && C->isNullValue();
4821 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4823 bool X86::isZeroNode(SDValue Elt) {
4826 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4827 return CFP->getValueAPF().isPosZero();
4831 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4832 /// match movhlps. The lower half elements should come from upper half of
4833 /// V1 (and in order), and the upper half elements should come from the upper
4834 /// half of V2 (and in order).
4835 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4836 if (!VT.is128BitVector())
4838 if (VT.getVectorNumElements() != 4)
4840 for (unsigned i = 0, e = 2; i != e; ++i)
4841 if (!isUndefOrEqual(Mask[i], i+2))
4843 for (unsigned i = 2; i != 4; ++i)
4844 if (!isUndefOrEqual(Mask[i], i+4))
4849 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4850 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4852 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4853 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4855 N = N->getOperand(0).getNode();
4856 if (!ISD::isNON_EXTLoad(N))
4859 *LD = cast<LoadSDNode>(N);
4863 // Test whether the given value is a vector value which will be legalized
4865 static bool WillBeConstantPoolLoad(SDNode *N) {
4866 if (N->getOpcode() != ISD::BUILD_VECTOR)
4869 // Check for any non-constant elements.
4870 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4871 switch (N->getOperand(i).getNode()->getOpcode()) {
4873 case ISD::ConstantFP:
4880 // Vectors of all-zeros and all-ones are materialized with special
4881 // instructions rather than being loaded.
4882 return !ISD::isBuildVectorAllZeros(N) &&
4883 !ISD::isBuildVectorAllOnes(N);
4886 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4887 /// match movlp{s|d}. The lower half elements should come from lower half of
4888 /// V1 (and in order), and the upper half elements should come from the upper
4889 /// half of V2 (and in order). And since V1 will become the source of the
4890 /// MOVLP, it must be either a vector load or a scalar load to vector.
4891 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4892 ArrayRef<int> Mask, MVT VT) {
4893 if (!VT.is128BitVector())
4896 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4898 // Is V2 is a vector load, don't do this transformation. We will try to use
4899 // load folding shufps op.
4900 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4903 unsigned NumElems = VT.getVectorNumElements();
4905 if (NumElems != 2 && NumElems != 4)
4907 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4908 if (!isUndefOrEqual(Mask[i], i))
4910 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4911 if (!isUndefOrEqual(Mask[i], i+NumElems))
4916 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4917 /// to an zero vector.
4918 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4919 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4920 SDValue V1 = N->getOperand(0);
4921 SDValue V2 = N->getOperand(1);
4922 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4923 for (unsigned i = 0; i != NumElems; ++i) {
4924 int Idx = N->getMaskElt(i);
4925 if (Idx >= (int)NumElems) {
4926 unsigned Opc = V2.getOpcode();
4927 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4929 if (Opc != ISD::BUILD_VECTOR ||
4930 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4932 } else if (Idx >= 0) {
4933 unsigned Opc = V1.getOpcode();
4934 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4936 if (Opc != ISD::BUILD_VECTOR ||
4937 !X86::isZeroNode(V1.getOperand(Idx)))
4944 /// getZeroVector - Returns a vector of specified type with all zero elements.
4946 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4947 SelectionDAG &DAG, SDLoc dl) {
4948 assert(VT.isVector() && "Expected a vector type");
4950 // Always build SSE zero vectors as <4 x i32> bitcasted
4951 // to their dest type. This ensures they get CSE'd.
4953 if (VT.is128BitVector()) { // SSE
4954 if (Subtarget->hasSSE2()) { // SSE2
4955 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4956 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4958 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4959 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4961 } else if (VT.is256BitVector()) { // AVX
4962 if (Subtarget->hasInt256()) { // AVX2
4963 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4964 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4965 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4967 // 256-bit logic and arithmetic instructions in AVX are all
4968 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4969 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4970 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4971 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4973 } else if (VT.is512BitVector()) { // AVX-512
4974 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4975 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4976 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4977 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4978 } else if (VT.getScalarType() == MVT::i1) {
4979 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4980 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4981 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4982 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4984 llvm_unreachable("Unexpected vector type");
4986 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4989 /// getOnesVector - Returns a vector of specified type with all bits set.
4990 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4991 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4992 /// Then bitcast to their original type, ensuring they get CSE'd.
4993 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4995 assert(VT.isVector() && "Expected a vector type");
4997 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4999 if (VT.is256BitVector()) {
5000 if (HasInt256) { // AVX2
5001 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5002 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5004 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5005 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5007 } else if (VT.is128BitVector()) {
5008 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5010 llvm_unreachable("Unexpected vector type");
5012 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5015 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5016 /// that point to V2 points to its first element.
5017 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5018 for (unsigned i = 0; i != NumElems; ++i) {
5019 if (Mask[i] > (int)NumElems) {
5025 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5026 /// operation of specified width.
5027 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5029 unsigned NumElems = VT.getVectorNumElements();
5030 SmallVector<int, 8> Mask;
5031 Mask.push_back(NumElems);
5032 for (unsigned i = 1; i != NumElems; ++i)
5034 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5037 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5038 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5040 unsigned NumElems = VT.getVectorNumElements();
5041 SmallVector<int, 8> Mask;
5042 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5044 Mask.push_back(i + NumElems);
5046 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5049 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5050 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5052 unsigned NumElems = VT.getVectorNumElements();
5053 SmallVector<int, 8> Mask;
5054 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5055 Mask.push_back(i + Half);
5056 Mask.push_back(i + NumElems + Half);
5058 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5061 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5062 // a generic shuffle instruction because the target has no such instructions.
5063 // Generate shuffles which repeat i16 and i8 several times until they can be
5064 // represented by v4f32 and then be manipulated by target suported shuffles.
5065 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5066 MVT VT = V.getSimpleValueType();
5067 int NumElems = VT.getVectorNumElements();
5070 while (NumElems > 4) {
5071 if (EltNo < NumElems/2) {
5072 V = getUnpackl(DAG, dl, VT, V, V);
5074 V = getUnpackh(DAG, dl, VT, V, V);
5075 EltNo -= NumElems/2;
5082 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5083 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5084 MVT VT = V.getSimpleValueType();
5087 if (VT.is128BitVector()) {
5088 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5089 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5090 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5092 } else if (VT.is256BitVector()) {
5093 // To use VPERMILPS to splat scalars, the second half of indicies must
5094 // refer to the higher part, which is a duplication of the lower one,
5095 // because VPERMILPS can only handle in-lane permutations.
5096 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5097 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5099 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5100 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5103 llvm_unreachable("Vector size not supported");
5105 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5108 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5109 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5110 MVT SrcVT = SV->getSimpleValueType(0);
5111 SDValue V1 = SV->getOperand(0);
5114 int EltNo = SV->getSplatIndex();
5115 int NumElems = SrcVT.getVectorNumElements();
5116 bool Is256BitVec = SrcVT.is256BitVector();
5118 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5119 "Unknown how to promote splat for type");
5121 // Extract the 128-bit part containing the splat element and update
5122 // the splat element index when it refers to the higher register.
5124 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5125 if (EltNo >= NumElems/2)
5126 EltNo -= NumElems/2;
5129 // All i16 and i8 vector types can't be used directly by a generic shuffle
5130 // instruction because the target has no such instruction. Generate shuffles
5131 // which repeat i16 and i8 several times until they fit in i32, and then can
5132 // be manipulated by target suported shuffles.
5133 MVT EltVT = SrcVT.getVectorElementType();
5134 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5135 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5137 // Recreate the 256-bit vector and place the same 128-bit vector
5138 // into the low and high part. This is necessary because we want
5139 // to use VPERM* to shuffle the vectors
5141 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5144 return getLegalSplat(DAG, V1, EltNo);
5147 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5148 /// vector of zero or undef vector. This produces a shuffle where the low
5149 /// element of V2 is swizzled into the zero/undef vector, landing at element
5150 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5151 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5153 const X86Subtarget *Subtarget,
5154 SelectionDAG &DAG) {
5155 MVT VT = V2.getSimpleValueType();
5157 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5158 unsigned NumElems = VT.getVectorNumElements();
5159 SmallVector<int, 16> MaskVec;
5160 for (unsigned i = 0; i != NumElems; ++i)
5161 // If this is the insertion idx, put the low elt of V2 here.
5162 MaskVec.push_back(i == Idx ? NumElems : i);
5163 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5166 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5167 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5168 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5169 /// shuffles which use a single input multiple times, and in those cases it will
5170 /// adjust the mask to only have indices within that single input.
5171 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5172 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5173 unsigned NumElems = VT.getVectorNumElements();
5177 bool IsFakeUnary = false;
5178 switch(N->getOpcode()) {
5180 ImmN = N->getOperand(N->getNumOperands()-1);
5181 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5182 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5184 case X86ISD::UNPCKH:
5185 DecodeUNPCKHMask(VT, Mask);
5186 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5188 case X86ISD::UNPCKL:
5189 DecodeUNPCKLMask(VT, Mask);
5190 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5192 case X86ISD::MOVHLPS:
5193 DecodeMOVHLPSMask(NumElems, Mask);
5194 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5196 case X86ISD::MOVLHPS:
5197 DecodeMOVLHPSMask(NumElems, Mask);
5198 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5200 case X86ISD::PALIGNR:
5201 ImmN = N->getOperand(N->getNumOperands()-1);
5202 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5204 case X86ISD::PSHUFD:
5205 case X86ISD::VPERMILP:
5206 ImmN = N->getOperand(N->getNumOperands()-1);
5207 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5210 case X86ISD::PSHUFHW:
5211 ImmN = N->getOperand(N->getNumOperands()-1);
5212 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5215 case X86ISD::PSHUFLW:
5216 ImmN = N->getOperand(N->getNumOperands()-1);
5217 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5220 case X86ISD::PSHUFB: {
5222 SDValue MaskNode = N->getOperand(1);
5223 while (MaskNode->getOpcode() == ISD::BITCAST)
5224 MaskNode = MaskNode->getOperand(0);
5226 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5227 // If we have a build-vector, then things are easy.
5228 EVT VT = MaskNode.getValueType();
5229 assert(VT.isVector() &&
5230 "Can't produce a non-vector with a build_vector!");
5231 if (!VT.isInteger())
5234 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5236 SmallVector<uint64_t, 32> RawMask;
5237 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5238 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5241 APInt MaskElement = CN->getAPIntValue();
5243 // We now have to decode the element which could be any integer size and
5244 // extract each byte of it.
5245 for (int j = 0; j < NumBytesPerElement; ++j) {
5246 // Note that this is x86 and so always little endian: the low byte is
5247 // the first byte of the mask.
5248 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5249 MaskElement = MaskElement.lshr(8);
5252 DecodePSHUFBMask(RawMask, Mask);
5256 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5260 SDValue Ptr = MaskLoad->getBasePtr();
5261 if (Ptr->getOpcode() == X86ISD::Wrapper)
5262 Ptr = Ptr->getOperand(0);
5264 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5265 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5268 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5269 // FIXME: Support AVX-512 here.
5270 if (!C->getType()->isVectorTy() ||
5271 (C->getNumElements() != 16 && C->getNumElements() != 32))
5274 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5275 DecodePSHUFBMask(C, Mask);
5281 case X86ISD::VPERMI:
5282 ImmN = N->getOperand(N->getNumOperands()-1);
5283 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5287 case X86ISD::MOVSD: {
5288 // The index 0 always comes from the first element of the second source,
5289 // this is why MOVSS and MOVSD are used in the first place. The other
5290 // elements come from the other positions of the first source vector
5291 Mask.push_back(NumElems);
5292 for (unsigned i = 1; i != NumElems; ++i) {
5297 case X86ISD::VPERM2X128:
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 if (Mask.empty()) return false;
5302 case X86ISD::MOVDDUP:
5303 case X86ISD::MOVLHPD:
5304 case X86ISD::MOVLPD:
5305 case X86ISD::MOVLPS:
5306 case X86ISD::MOVSHDUP:
5307 case X86ISD::MOVSLDUP:
5308 // Not yet implemented
5310 default: llvm_unreachable("unknown target shuffle node");
5313 // If we have a fake unary shuffle, the shuffle mask is spread across two
5314 // inputs that are actually the same node. Re-map the mask to always point
5315 // into the first input.
5318 if (M >= (int)Mask.size())
5324 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5325 /// element of the result of the vector shuffle.
5326 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5329 return SDValue(); // Limit search depth.
5331 SDValue V = SDValue(N, 0);
5332 EVT VT = V.getValueType();
5333 unsigned Opcode = V.getOpcode();
5335 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5336 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5337 int Elt = SV->getMaskElt(Index);
5340 return DAG.getUNDEF(VT.getVectorElementType());
5342 unsigned NumElems = VT.getVectorNumElements();
5343 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5344 : SV->getOperand(1);
5345 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5348 // Recurse into target specific vector shuffles to find scalars.
5349 if (isTargetShuffle(Opcode)) {
5350 MVT ShufVT = V.getSimpleValueType();
5351 unsigned NumElems = ShufVT.getVectorNumElements();
5352 SmallVector<int, 16> ShuffleMask;
5355 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5358 int Elt = ShuffleMask[Index];
5360 return DAG.getUNDEF(ShufVT.getVectorElementType());
5362 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5364 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5368 // Actual nodes that may contain scalar elements
5369 if (Opcode == ISD::BITCAST) {
5370 V = V.getOperand(0);
5371 EVT SrcVT = V.getValueType();
5372 unsigned NumElems = VT.getVectorNumElements();
5374 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5378 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5379 return (Index == 0) ? V.getOperand(0)
5380 : DAG.getUNDEF(VT.getVectorElementType());
5382 if (V.getOpcode() == ISD::BUILD_VECTOR)
5383 return V.getOperand(Index);
5388 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5389 /// shuffle operation which come from a consecutively from a zero. The
5390 /// search can start in two different directions, from left or right.
5391 /// We count undefs as zeros until PreferredNum is reached.
5392 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5393 unsigned NumElems, bool ZerosFromLeft,
5395 unsigned PreferredNum = -1U) {
5396 unsigned NumZeros = 0;
5397 for (unsigned i = 0; i != NumElems; ++i) {
5398 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5399 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5403 if (X86::isZeroNode(Elt))
5405 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5406 NumZeros = std::min(NumZeros + 1, PreferredNum);
5414 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5415 /// correspond consecutively to elements from one of the vector operands,
5416 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5418 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5419 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5420 unsigned NumElems, unsigned &OpNum) {
5421 bool SeenV1 = false;
5422 bool SeenV2 = false;
5424 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5425 int Idx = SVOp->getMaskElt(i);
5426 // Ignore undef indicies
5430 if (Idx < (int)NumElems)
5435 // Only accept consecutive elements from the same vector
5436 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5440 OpNum = SeenV1 ? 0 : 1;
5444 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5445 /// logical left shift of a vector.
5446 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5447 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5449 SVOp->getSimpleValueType(0).getVectorNumElements();
5450 unsigned NumZeros = getNumOfConsecutiveZeros(
5451 SVOp, NumElems, false /* check zeros from right */, DAG,
5452 SVOp->getMaskElt(0));
5458 // Considering the elements in the mask that are not consecutive zeros,
5459 // check if they consecutively come from only one of the source vectors.
5461 // V1 = {X, A, B, C} 0
5463 // vector_shuffle V1, V2 <1, 2, 3, X>
5465 if (!isShuffleMaskConsecutive(SVOp,
5466 0, // Mask Start Index
5467 NumElems-NumZeros, // Mask End Index(exclusive)
5468 NumZeros, // Where to start looking in the src vector
5469 NumElems, // Number of elements in vector
5470 OpSrc)) // Which source operand ?
5475 ShVal = SVOp->getOperand(OpSrc);
5479 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5480 /// logical left shift of a vector.
5481 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5482 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5484 SVOp->getSimpleValueType(0).getVectorNumElements();
5485 unsigned NumZeros = getNumOfConsecutiveZeros(
5486 SVOp, NumElems, true /* check zeros from left */, DAG,
5487 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5493 // Considering the elements in the mask that are not consecutive zeros,
5494 // check if they consecutively come from only one of the source vectors.
5496 // 0 { A, B, X, X } = V2
5498 // vector_shuffle V1, V2 <X, X, 4, 5>
5500 if (!isShuffleMaskConsecutive(SVOp,
5501 NumZeros, // Mask Start Index
5502 NumElems, // Mask End Index(exclusive)
5503 0, // Where to start looking in the src vector
5504 NumElems, // Number of elements in vector
5505 OpSrc)) // Which source operand ?
5510 ShVal = SVOp->getOperand(OpSrc);
5514 /// isVectorShift - Returns true if the shuffle can be implemented as a
5515 /// logical left or right shift of a vector.
5516 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5517 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5518 // Although the logic below support any bitwidth size, there are no
5519 // shift instructions which handle more than 128-bit vectors.
5520 if (!SVOp->getSimpleValueType(0).is128BitVector())
5523 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5524 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5530 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5532 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5533 unsigned NumNonZero, unsigned NumZero,
5535 const X86Subtarget* Subtarget,
5536 const TargetLowering &TLI) {
5543 for (unsigned i = 0; i < 16; ++i) {
5544 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5545 if (ThisIsNonZero && First) {
5547 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5549 V = DAG.getUNDEF(MVT::v8i16);
5554 SDValue ThisElt, LastElt;
5555 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5556 if (LastIsNonZero) {
5557 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5558 MVT::i16, Op.getOperand(i-1));
5560 if (ThisIsNonZero) {
5561 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5562 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5563 ThisElt, DAG.getConstant(8, MVT::i8));
5565 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5569 if (ThisElt.getNode())
5570 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5571 DAG.getIntPtrConstant(i/2));
5575 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5578 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5580 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5581 unsigned NumNonZero, unsigned NumZero,
5583 const X86Subtarget* Subtarget,
5584 const TargetLowering &TLI) {
5591 for (unsigned i = 0; i < 8; ++i) {
5592 bool isNonZero = (NonZeros & (1 << i)) != 0;
5596 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5598 V = DAG.getUNDEF(MVT::v8i16);
5601 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5602 MVT::v8i16, V, Op.getOperand(i),
5603 DAG.getIntPtrConstant(i));
5610 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5611 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5612 unsigned NonZeros, unsigned NumNonZero,
5613 unsigned NumZero, SelectionDAG &DAG,
5614 const X86Subtarget *Subtarget,
5615 const TargetLowering &TLI) {
5616 // We know there's at least one non-zero element
5617 unsigned FirstNonZeroIdx = 0;
5618 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5619 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5620 X86::isZeroNode(FirstNonZero)) {
5622 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5625 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5626 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5629 SDValue V = FirstNonZero.getOperand(0);
5630 MVT VVT = V.getSimpleValueType();
5631 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5634 unsigned FirstNonZeroDst =
5635 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5636 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5637 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5638 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5640 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5641 SDValue Elem = Op.getOperand(Idx);
5642 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5645 // TODO: What else can be here? Deal with it.
5646 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5649 // TODO: Some optimizations are still possible here
5650 // ex: Getting one element from a vector, and the rest from another.
5651 if (Elem.getOperand(0) != V)
5654 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5657 else if (IncorrectIdx == -1U) {
5661 // There was already one element with an incorrect index.
5662 // We can't optimize this case to an insertps.
5666 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5668 EVT VT = Op.getSimpleValueType();
5669 unsigned ElementMoveMask = 0;
5670 if (IncorrectIdx == -1U)
5671 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5673 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5675 SDValue InsertpsMask =
5676 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5677 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5683 /// getVShift - Return a vector logical shift node.
5685 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5686 unsigned NumBits, SelectionDAG &DAG,
5687 const TargetLowering &TLI, SDLoc dl) {
5688 assert(VT.is128BitVector() && "Unknown type for VShift");
5689 EVT ShVT = MVT::v2i64;
5690 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5691 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5692 return DAG.getNode(ISD::BITCAST, dl, VT,
5693 DAG.getNode(Opc, dl, ShVT, SrcOp,
5694 DAG.getConstant(NumBits,
5695 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5699 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5701 // Check if the scalar load can be widened into a vector load. And if
5702 // the address is "base + cst" see if the cst can be "absorbed" into
5703 // the shuffle mask.
5704 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5705 SDValue Ptr = LD->getBasePtr();
5706 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5708 EVT PVT = LD->getValueType(0);
5709 if (PVT != MVT::i32 && PVT != MVT::f32)
5714 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5715 FI = FINode->getIndex();
5717 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5718 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5719 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5720 Offset = Ptr.getConstantOperandVal(1);
5721 Ptr = Ptr.getOperand(0);
5726 // FIXME: 256-bit vector instructions don't require a strict alignment,
5727 // improve this code to support it better.
5728 unsigned RequiredAlign = VT.getSizeInBits()/8;
5729 SDValue Chain = LD->getChain();
5730 // Make sure the stack object alignment is at least 16 or 32.
5731 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5732 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5733 if (MFI->isFixedObjectIndex(FI)) {
5734 // Can't change the alignment. FIXME: It's possible to compute
5735 // the exact stack offset and reference FI + adjust offset instead.
5736 // If someone *really* cares about this. That's the way to implement it.
5739 MFI->setObjectAlignment(FI, RequiredAlign);
5743 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5744 // Ptr + (Offset & ~15).
5747 if ((Offset % RequiredAlign) & 3)
5749 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5751 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5752 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5754 int EltNo = (Offset - StartOffset) >> 2;
5755 unsigned NumElems = VT.getVectorNumElements();
5757 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5758 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5759 LD->getPointerInfo().getWithOffset(StartOffset),
5760 false, false, false, 0);
5762 SmallVector<int, 8> Mask;
5763 for (unsigned i = 0; i != NumElems; ++i)
5764 Mask.push_back(EltNo);
5766 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5772 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5773 /// vector of type 'VT', see if the elements can be replaced by a single large
5774 /// load which has the same value as a build_vector whose operands are 'elts'.
5776 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5778 /// FIXME: we'd also like to handle the case where the last elements are zero
5779 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5780 /// There's even a handy isZeroNode for that purpose.
5781 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5782 SDLoc &DL, SelectionDAG &DAG,
5783 bool isAfterLegalize) {
5784 EVT EltVT = VT.getVectorElementType();
5785 unsigned NumElems = Elts.size();
5787 LoadSDNode *LDBase = nullptr;
5788 unsigned LastLoadedElt = -1U;
5790 // For each element in the initializer, see if we've found a load or an undef.
5791 // If we don't find an initial load element, or later load elements are
5792 // non-consecutive, bail out.
5793 for (unsigned i = 0; i < NumElems; ++i) {
5794 SDValue Elt = Elts[i];
5796 if (!Elt.getNode() ||
5797 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5800 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5802 LDBase = cast<LoadSDNode>(Elt.getNode());
5806 if (Elt.getOpcode() == ISD::UNDEF)
5809 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5810 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5815 // If we have found an entire vector of loads and undefs, then return a large
5816 // load of the entire vector width starting at the base pointer. If we found
5817 // consecutive loads for the low half, generate a vzext_load node.
5818 if (LastLoadedElt == NumElems - 1) {
5820 if (isAfterLegalize &&
5821 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5824 SDValue NewLd = SDValue();
5826 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5827 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5828 LDBase->getPointerInfo(),
5829 LDBase->isVolatile(), LDBase->isNonTemporal(),
5830 LDBase->isInvariant(), 0);
5831 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5832 LDBase->getPointerInfo(),
5833 LDBase->isVolatile(), LDBase->isNonTemporal(),
5834 LDBase->isInvariant(), LDBase->getAlignment());
5836 if (LDBase->hasAnyUseOfValue(1)) {
5837 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5839 SDValue(NewLd.getNode(), 1));
5840 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5841 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5842 SDValue(NewLd.getNode(), 1));
5847 if (NumElems == 4 && LastLoadedElt == 1 &&
5848 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5849 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5850 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5852 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5853 LDBase->getPointerInfo(),
5854 LDBase->getAlignment(),
5855 false/*isVolatile*/, true/*ReadMem*/,
5858 // Make sure the newly-created LOAD is in the same position as LDBase in
5859 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5860 // update uses of LDBase's output chain to use the TokenFactor.
5861 if (LDBase->hasAnyUseOfValue(1)) {
5862 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5863 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5864 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5865 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5866 SDValue(ResNode.getNode(), 1));
5869 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5874 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5875 /// to generate a splat value for the following cases:
5876 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5877 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5878 /// a scalar load, or a constant.
5879 /// The VBROADCAST node is returned when a pattern is found,
5880 /// or SDValue() otherwise.
5881 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5882 SelectionDAG &DAG) {
5883 if (!Subtarget->hasFp256())
5886 MVT VT = Op.getSimpleValueType();
5889 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5890 "Unsupported vector type for broadcast.");
5895 switch (Op.getOpcode()) {
5897 // Unknown pattern found.
5900 case ISD::BUILD_VECTOR: {
5901 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5902 BitVector UndefElements;
5903 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5905 // We need a splat of a single value to use broadcast, and it doesn't
5906 // make any sense if the value is only in one element of the vector.
5907 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5911 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5912 Ld.getOpcode() == ISD::ConstantFP);
5914 // Make sure that all of the users of a non-constant load are from the
5915 // BUILD_VECTOR node.
5916 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5921 case ISD::VECTOR_SHUFFLE: {
5922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5924 // Shuffles must have a splat mask where the first element is
5926 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5929 SDValue Sc = Op.getOperand(0);
5930 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5931 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5933 if (!Subtarget->hasInt256())
5936 // Use the register form of the broadcast instruction available on AVX2.
5937 if (VT.getSizeInBits() >= 256)
5938 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5939 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5942 Ld = Sc.getOperand(0);
5943 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5944 Ld.getOpcode() == ISD::ConstantFP);
5946 // The scalar_to_vector node and the suspected
5947 // load node must have exactly one user.
5948 // Constants may have multiple users.
5950 // AVX-512 has register version of the broadcast
5951 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5952 Ld.getValueType().getSizeInBits() >= 32;
5953 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5960 bool IsGE256 = (VT.getSizeInBits() >= 256);
5962 // Handle the broadcasting a single constant scalar from the constant pool
5963 // into a vector. On Sandybridge it is still better to load a constant vector
5964 // from the constant pool and not to broadcast it from a scalar.
5965 if (ConstSplatVal && Subtarget->hasInt256()) {
5966 EVT CVT = Ld.getValueType();
5967 assert(!CVT.isVector() && "Must not broadcast a vector type");
5968 unsigned ScalarSize = CVT.getSizeInBits();
5970 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5971 const Constant *C = nullptr;
5972 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5973 C = CI->getConstantIntValue();
5974 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5975 C = CF->getConstantFPValue();
5977 assert(C && "Invalid constant type");
5979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5980 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5981 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5982 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5983 MachinePointerInfo::getConstantPool(),
5984 false, false, false, Alignment);
5986 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5990 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5991 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5993 // Handle AVX2 in-register broadcasts.
5994 if (!IsLoad && Subtarget->hasInt256() &&
5995 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5996 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5998 // The scalar source must be a normal load.
6002 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6003 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6005 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6006 // double since there is no vbroadcastsd xmm
6007 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6008 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6009 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6012 // Unsupported broadcast.
6016 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6017 /// underlying vector and index.
6019 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6021 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6023 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6024 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6027 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6029 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6031 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6032 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6035 // In this case the vector is the extract_subvector expression and the index
6036 // is 2, as specified by the shuffle.
6037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6038 SDValue ShuffleVec = SVOp->getOperand(0);
6039 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6040 assert(ShuffleVecVT.getVectorElementType() ==
6041 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6043 int ShuffleIdx = SVOp->getMaskElt(Idx);
6044 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6045 ExtractedFromVec = ShuffleVec;
6051 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6052 MVT VT = Op.getSimpleValueType();
6054 // Skip if insert_vec_elt is not supported.
6055 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6056 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6060 unsigned NumElems = Op.getNumOperands();
6064 SmallVector<unsigned, 4> InsertIndices;
6065 SmallVector<int, 8> Mask(NumElems, -1);
6067 for (unsigned i = 0; i != NumElems; ++i) {
6068 unsigned Opc = Op.getOperand(i).getOpcode();
6070 if (Opc == ISD::UNDEF)
6073 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6074 // Quit if more than 1 elements need inserting.
6075 if (InsertIndices.size() > 1)
6078 InsertIndices.push_back(i);
6082 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6083 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6084 // Quit if non-constant index.
6085 if (!isa<ConstantSDNode>(ExtIdx))
6087 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6089 // Quit if extracted from vector of different type.
6090 if (ExtractedFromVec.getValueType() != VT)
6093 if (!VecIn1.getNode())
6094 VecIn1 = ExtractedFromVec;
6095 else if (VecIn1 != ExtractedFromVec) {
6096 if (!VecIn2.getNode())
6097 VecIn2 = ExtractedFromVec;
6098 else if (VecIn2 != ExtractedFromVec)
6099 // Quit if more than 2 vectors to shuffle
6103 if (ExtractedFromVec == VecIn1)
6105 else if (ExtractedFromVec == VecIn2)
6106 Mask[i] = Idx + NumElems;
6109 if (!VecIn1.getNode())
6112 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6113 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6114 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6115 unsigned Idx = InsertIndices[i];
6116 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6117 DAG.getIntPtrConstant(Idx));
6123 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6125 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6127 MVT VT = Op.getSimpleValueType();
6128 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6129 "Unexpected type in LowerBUILD_VECTORvXi1!");
6132 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6133 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6134 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6135 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6138 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6139 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6140 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6141 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6144 bool AllContants = true;
6145 uint64_t Immediate = 0;
6146 int NonConstIdx = -1;
6147 bool IsSplat = true;
6148 unsigned NumNonConsts = 0;
6149 unsigned NumConsts = 0;
6150 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6151 SDValue In = Op.getOperand(idx);
6152 if (In.getOpcode() == ISD::UNDEF)
6154 if (!isa<ConstantSDNode>(In)) {
6155 AllContants = false;
6161 if (cast<ConstantSDNode>(In)->getZExtValue())
6162 Immediate |= (1ULL << idx);
6164 if (In != Op.getOperand(0))
6169 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6170 DAG.getConstant(Immediate, MVT::i16));
6171 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6172 DAG.getIntPtrConstant(0));
6175 if (NumNonConsts == 1 && NonConstIdx != 0) {
6178 SDValue VecAsImm = DAG.getConstant(Immediate,
6179 MVT::getIntegerVT(VT.getSizeInBits()));
6180 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6183 DstVec = DAG.getUNDEF(VT);
6184 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6185 Op.getOperand(NonConstIdx),
6186 DAG.getIntPtrConstant(NonConstIdx));
6188 if (!IsSplat && (NonConstIdx != 0))
6189 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6190 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6193 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6194 DAG.getConstant(-1, SelectVT),
6195 DAG.getConstant(0, SelectVT));
6197 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6198 DAG.getConstant((Immediate | 1), SelectVT),
6199 DAG.getConstant(Immediate, SelectVT));
6200 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6203 /// \brief Return true if \p N implements a horizontal binop and return the
6204 /// operands for the horizontal binop into V0 and V1.
6206 /// This is a helper function of PerformBUILD_VECTORCombine.
6207 /// This function checks that the build_vector \p N in input implements a
6208 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6209 /// operation to match.
6210 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6211 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6212 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6215 /// This function only analyzes elements of \p N whose indices are
6216 /// in range [BaseIdx, LastIdx).
6217 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6219 unsigned BaseIdx, unsigned LastIdx,
6220 SDValue &V0, SDValue &V1) {
6221 EVT VT = N->getValueType(0);
6223 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6224 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6225 "Invalid Vector in input!");
6227 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6228 bool CanFold = true;
6229 unsigned ExpectedVExtractIdx = BaseIdx;
6230 unsigned NumElts = LastIdx - BaseIdx;
6231 V0 = DAG.getUNDEF(VT);
6232 V1 = DAG.getUNDEF(VT);
6234 // Check if N implements a horizontal binop.
6235 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6236 SDValue Op = N->getOperand(i + BaseIdx);
6239 if (Op->getOpcode() == ISD::UNDEF) {
6240 // Update the expected vector extract index.
6241 if (i * 2 == NumElts)
6242 ExpectedVExtractIdx = BaseIdx;
6243 ExpectedVExtractIdx += 2;
6247 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6252 SDValue Op0 = Op.getOperand(0);
6253 SDValue Op1 = Op.getOperand(1);
6255 // Try to match the following pattern:
6256 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6257 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6258 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6259 Op0.getOperand(0) == Op1.getOperand(0) &&
6260 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6261 isa<ConstantSDNode>(Op1.getOperand(1)));
6265 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6266 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6268 if (i * 2 < NumElts) {
6269 if (V0.getOpcode() == ISD::UNDEF)
6270 V0 = Op0.getOperand(0);
6272 if (V1.getOpcode() == ISD::UNDEF)
6273 V1 = Op0.getOperand(0);
6274 if (i * 2 == NumElts)
6275 ExpectedVExtractIdx = BaseIdx;
6278 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6279 if (I0 == ExpectedVExtractIdx)
6280 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6281 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6282 // Try to match the following dag sequence:
6283 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6284 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6288 ExpectedVExtractIdx += 2;
6294 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6295 /// a concat_vector.
6297 /// This is a helper function of PerformBUILD_VECTORCombine.
6298 /// This function expects two 256-bit vectors called V0 and V1.
6299 /// At first, each vector is split into two separate 128-bit vectors.
6300 /// Then, the resulting 128-bit vectors are used to implement two
6301 /// horizontal binary operations.
6303 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6305 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6306 /// the two new horizontal binop.
6307 /// When Mode is set, the first horizontal binop dag node would take as input
6308 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6309 /// horizontal binop dag node would take as input the lower 128-bit of V1
6310 /// and the upper 128-bit of V1.
6312 /// HADD V0_LO, V0_HI
6313 /// HADD V1_LO, V1_HI
6315 /// Otherwise, the first horizontal binop dag node takes as input the lower
6316 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6317 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6319 /// HADD V0_LO, V1_LO
6320 /// HADD V0_HI, V1_HI
6322 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6323 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6324 /// the upper 128-bits of the result.
6325 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6326 SDLoc DL, SelectionDAG &DAG,
6327 unsigned X86Opcode, bool Mode,
6328 bool isUndefLO, bool isUndefHI) {
6329 EVT VT = V0.getValueType();
6330 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6331 "Invalid nodes in input!");
6333 unsigned NumElts = VT.getVectorNumElements();
6334 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6335 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6336 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6337 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6338 EVT NewVT = V0_LO.getValueType();
6340 SDValue LO = DAG.getUNDEF(NewVT);
6341 SDValue HI = DAG.getUNDEF(NewVT);
6344 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6345 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6346 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6347 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6348 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6350 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6351 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6352 V1_LO->getOpcode() != ISD::UNDEF))
6353 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6355 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6356 V1_HI->getOpcode() != ISD::UNDEF))
6357 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6360 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6363 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6364 /// sequence of 'vadd + vsub + blendi'.
6365 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6366 const X86Subtarget *Subtarget) {
6368 EVT VT = BV->getValueType(0);
6369 unsigned NumElts = VT.getVectorNumElements();
6370 SDValue InVec0 = DAG.getUNDEF(VT);
6371 SDValue InVec1 = DAG.getUNDEF(VT);
6373 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6374 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6376 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6378 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6381 // Odd-numbered elements in the input build vector are obtained from
6382 // adding two integer/float elements.
6383 // Even-numbered elements in the input build vector are obtained from
6384 // subtracting two integer/float elements.
6385 unsigned ExpectedOpcode = ISD::FSUB;
6386 unsigned NextExpectedOpcode = ISD::FADD;
6387 bool AddFound = false;
6388 bool SubFound = false;
6390 for (unsigned i = 0, e = NumElts; i != e; i++) {
6391 SDValue Op = BV->getOperand(i);
6393 // Skip 'undef' values.
6394 unsigned Opcode = Op.getOpcode();
6395 if (Opcode == ISD::UNDEF) {
6396 std::swap(ExpectedOpcode, NextExpectedOpcode);
6400 // Early exit if we found an unexpected opcode.
6401 if (Opcode != ExpectedOpcode)
6404 SDValue Op0 = Op.getOperand(0);
6405 SDValue Op1 = Op.getOperand(1);
6407 // Try to match the following pattern:
6408 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6409 // Early exit if we cannot match that sequence.
6410 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6411 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6412 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6413 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6414 Op0.getOperand(1) != Op1.getOperand(1))
6417 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6421 // We found a valid add/sub node. Update the information accordingly.
6427 // Update InVec0 and InVec1.
6428 if (InVec0.getOpcode() == ISD::UNDEF)
6429 InVec0 = Op0.getOperand(0);
6430 if (InVec1.getOpcode() == ISD::UNDEF)
6431 InVec1 = Op1.getOperand(0);
6433 // Make sure that operands in input to each add/sub node always
6434 // come from a same pair of vectors.
6435 if (InVec0 != Op0.getOperand(0)) {
6436 if (ExpectedOpcode == ISD::FSUB)
6439 // FADD is commutable. Try to commute the operands
6440 // and then test again.
6441 std::swap(Op0, Op1);
6442 if (InVec0 != Op0.getOperand(0))
6446 if (InVec1 != Op1.getOperand(0))
6449 // Update the pair of expected opcodes.
6450 std::swap(ExpectedOpcode, NextExpectedOpcode);
6453 // Don't try to fold this build_vector into a VSELECT if it has
6454 // too many UNDEF operands.
6455 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6456 InVec1.getOpcode() != ISD::UNDEF) {
6457 // Emit a sequence of vector add and sub followed by a VSELECT.
6458 // The new VSELECT will be lowered into a BLENDI.
6459 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6460 // and emit a single ADDSUB instruction.
6461 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6462 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6464 // Construct the VSELECT mask.
6465 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6466 EVT SVT = MaskVT.getVectorElementType();
6467 unsigned SVTBits = SVT.getSizeInBits();
6468 SmallVector<SDValue, 8> Ops;
6470 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6471 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6472 APInt::getAllOnesValue(SVTBits);
6473 SDValue Constant = DAG.getConstant(Value, SVT);
6474 Ops.push_back(Constant);
6477 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6478 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6484 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6485 const X86Subtarget *Subtarget) {
6487 EVT VT = N->getValueType(0);
6488 unsigned NumElts = VT.getVectorNumElements();
6489 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6490 SDValue InVec0, InVec1;
6492 // Try to match an ADDSUB.
6493 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6494 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6495 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6496 if (Value.getNode())
6500 // Try to match horizontal ADD/SUB.
6501 unsigned NumUndefsLO = 0;
6502 unsigned NumUndefsHI = 0;
6503 unsigned Half = NumElts/2;
6505 // Count the number of UNDEF operands in the build_vector in input.
6506 for (unsigned i = 0, e = Half; i != e; ++i)
6507 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6510 for (unsigned i = Half, e = NumElts; i != e; ++i)
6511 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6514 // Early exit if this is either a build_vector of all UNDEFs or all the
6515 // operands but one are UNDEF.
6516 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6519 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6520 // Try to match an SSE3 float HADD/HSUB.
6521 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6522 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6524 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6525 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6526 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6527 // Try to match an SSSE3 integer HADD/HSUB.
6528 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6529 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6531 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6532 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6535 if (!Subtarget->hasAVX())
6538 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6539 // Try to match an AVX horizontal add/sub of packed single/double
6540 // precision floating point values from 256-bit vectors.
6541 SDValue InVec2, InVec3;
6542 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6543 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6544 ((InVec0.getOpcode() == ISD::UNDEF ||
6545 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6546 ((InVec1.getOpcode() == ISD::UNDEF ||
6547 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6548 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6550 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6551 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6552 ((InVec0.getOpcode() == ISD::UNDEF ||
6553 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6554 ((InVec1.getOpcode() == ISD::UNDEF ||
6555 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6556 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6557 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6558 // Try to match an AVX2 horizontal add/sub of signed integers.
6559 SDValue InVec2, InVec3;
6561 bool CanFold = true;
6563 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6564 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6565 ((InVec0.getOpcode() == ISD::UNDEF ||
6566 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6567 ((InVec1.getOpcode() == ISD::UNDEF ||
6568 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6569 X86Opcode = X86ISD::HADD;
6570 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6571 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6572 ((InVec0.getOpcode() == ISD::UNDEF ||
6573 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6574 ((InVec1.getOpcode() == ISD::UNDEF ||
6575 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6576 X86Opcode = X86ISD::HSUB;
6581 // Fold this build_vector into a single horizontal add/sub.
6582 // Do this only if the target has AVX2.
6583 if (Subtarget->hasAVX2())
6584 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6586 // Do not try to expand this build_vector into a pair of horizontal
6587 // add/sub if we can emit a pair of scalar add/sub.
6588 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6591 // Convert this build_vector into a pair of horizontal binop followed by
6593 bool isUndefLO = NumUndefsLO == Half;
6594 bool isUndefHI = NumUndefsHI == Half;
6595 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6596 isUndefLO, isUndefHI);
6600 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6601 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6603 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6604 X86Opcode = X86ISD::HADD;
6605 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6606 X86Opcode = X86ISD::HSUB;
6607 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6608 X86Opcode = X86ISD::FHADD;
6609 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6610 X86Opcode = X86ISD::FHSUB;
6614 // Don't try to expand this build_vector into a pair of horizontal add/sub
6615 // if we can simply emit a pair of scalar add/sub.
6616 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6619 // Convert this build_vector into two horizontal add/sub followed by
6621 bool isUndefLO = NumUndefsLO == Half;
6622 bool isUndefHI = NumUndefsHI == Half;
6623 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6624 isUndefLO, isUndefHI);
6631 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6634 MVT VT = Op.getSimpleValueType();
6635 MVT ExtVT = VT.getVectorElementType();
6636 unsigned NumElems = Op.getNumOperands();
6638 // Generate vectors for predicate vectors.
6639 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6640 return LowerBUILD_VECTORvXi1(Op, DAG);
6642 // Vectors containing all zeros can be matched by pxor and xorps later
6643 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6644 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6645 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6646 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6649 return getZeroVector(VT, Subtarget, DAG, dl);
6652 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6653 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6654 // vpcmpeqd on 256-bit vectors.
6655 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6656 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6659 if (!VT.is512BitVector())
6660 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6663 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6664 if (Broadcast.getNode())
6667 unsigned EVTBits = ExtVT.getSizeInBits();
6669 unsigned NumZero = 0;
6670 unsigned NumNonZero = 0;
6671 unsigned NonZeros = 0;
6672 bool IsAllConstants = true;
6673 SmallSet<SDValue, 8> Values;
6674 for (unsigned i = 0; i < NumElems; ++i) {
6675 SDValue Elt = Op.getOperand(i);
6676 if (Elt.getOpcode() == ISD::UNDEF)
6679 if (Elt.getOpcode() != ISD::Constant &&
6680 Elt.getOpcode() != ISD::ConstantFP)
6681 IsAllConstants = false;
6682 if (X86::isZeroNode(Elt))
6685 NonZeros |= (1 << i);
6690 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6691 if (NumNonZero == 0)
6692 return DAG.getUNDEF(VT);
6694 // Special case for single non-zero, non-undef, element.
6695 if (NumNonZero == 1) {
6696 unsigned Idx = countTrailingZeros(NonZeros);
6697 SDValue Item = Op.getOperand(Idx);
6699 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6700 // the value are obviously zero, truncate the value to i32 and do the
6701 // insertion that way. Only do this if the value is non-constant or if the
6702 // value is a constant being inserted into element 0. It is cheaper to do
6703 // a constant pool load than it is to do a movd + shuffle.
6704 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6705 (!IsAllConstants || Idx == 0)) {
6706 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6708 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6709 EVT VecVT = MVT::v4i32;
6710 unsigned VecElts = 4;
6712 // Truncate the value (which may itself be a constant) to i32, and
6713 // convert it to a vector with movd (S2V+shuffle to zero extend).
6714 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6715 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6716 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6718 // Now we have our 32-bit value zero extended in the low element of
6719 // a vector. If Idx != 0, swizzle it into place.
6721 SmallVector<int, 4> Mask;
6722 Mask.push_back(Idx);
6723 for (unsigned i = 1; i != VecElts; ++i)
6725 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6728 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6732 // If we have a constant or non-constant insertion into the low element of
6733 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6734 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6735 // depending on what the source datatype is.
6738 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6740 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6741 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6742 if (VT.is256BitVector() || VT.is512BitVector()) {
6743 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6744 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6745 Item, DAG.getIntPtrConstant(0));
6747 assert(VT.is128BitVector() && "Expected an SSE value type!");
6748 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6749 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6750 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6753 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6754 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6755 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6756 if (VT.is256BitVector()) {
6757 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6758 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6760 assert(VT.is128BitVector() && "Expected an SSE value type!");
6761 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6763 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6767 // Is it a vector logical left shift?
6768 if (NumElems == 2 && Idx == 1 &&
6769 X86::isZeroNode(Op.getOperand(0)) &&
6770 !X86::isZeroNode(Op.getOperand(1))) {
6771 unsigned NumBits = VT.getSizeInBits();
6772 return getVShift(true, VT,
6773 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6774 VT, Op.getOperand(1)),
6775 NumBits/2, DAG, *this, dl);
6778 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6781 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6782 // is a non-constant being inserted into an element other than the low one,
6783 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6784 // movd/movss) to move this into the low element, then shuffle it into
6786 if (EVTBits == 32) {
6787 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6789 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6790 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6791 SmallVector<int, 8> MaskVec;
6792 for (unsigned i = 0; i != NumElems; ++i)
6793 MaskVec.push_back(i == Idx ? 0 : 1);
6794 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6798 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6799 if (Values.size() == 1) {
6800 if (EVTBits == 32) {
6801 // Instead of a shuffle like this:
6802 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6803 // Check if it's possible to issue this instead.
6804 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6805 unsigned Idx = countTrailingZeros(NonZeros);
6806 SDValue Item = Op.getOperand(Idx);
6807 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6808 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6813 // A vector full of immediates; various special cases are already
6814 // handled, so this is best done with a single constant-pool load.
6818 // For AVX-length vectors, build the individual 128-bit pieces and use
6819 // shuffles to put them in place.
6820 if (VT.is256BitVector() || VT.is512BitVector()) {
6821 SmallVector<SDValue, 64> V;
6822 for (unsigned i = 0; i != NumElems; ++i)
6823 V.push_back(Op.getOperand(i));
6825 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6827 // Build both the lower and upper subvector.
6828 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6829 makeArrayRef(&V[0], NumElems/2));
6830 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6831 makeArrayRef(&V[NumElems / 2], NumElems/2));
6833 // Recreate the wider vector with the lower and upper part.
6834 if (VT.is256BitVector())
6835 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6836 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6839 // Let legalizer expand 2-wide build_vectors.
6840 if (EVTBits == 64) {
6841 if (NumNonZero == 1) {
6842 // One half is zero or undef.
6843 unsigned Idx = countTrailingZeros(NonZeros);
6844 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6845 Op.getOperand(Idx));
6846 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6851 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6852 if (EVTBits == 8 && NumElems == 16) {
6853 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6855 if (V.getNode()) return V;
6858 if (EVTBits == 16 && NumElems == 8) {
6859 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6861 if (V.getNode()) return V;
6864 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6865 if (EVTBits == 32 && NumElems == 4) {
6866 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6867 NumZero, DAG, Subtarget, *this);
6872 // If element VT is == 32 bits, turn it into a number of shuffles.
6873 SmallVector<SDValue, 8> V(NumElems);
6874 if (NumElems == 4 && NumZero > 0) {
6875 for (unsigned i = 0; i < 4; ++i) {
6876 bool isZero = !(NonZeros & (1 << i));
6878 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6880 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6883 for (unsigned i = 0; i < 2; ++i) {
6884 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6887 V[i] = V[i*2]; // Must be a zero vector.
6890 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6893 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6896 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6901 bool Reverse1 = (NonZeros & 0x3) == 2;
6902 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6906 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6907 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6909 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6912 if (Values.size() > 1 && VT.is128BitVector()) {
6913 // Check for a build vector of consecutive loads.
6914 for (unsigned i = 0; i < NumElems; ++i)
6915 V[i] = Op.getOperand(i);
6917 // Check for elements which are consecutive loads.
6918 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6922 // Check for a build vector from mostly shuffle plus few inserting.
6923 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6927 // For SSE 4.1, use insertps to put the high elements into the low element.
6928 if (getSubtarget()->hasSSE41()) {
6930 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6931 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6933 Result = DAG.getUNDEF(VT);
6935 for (unsigned i = 1; i < NumElems; ++i) {
6936 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6937 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6938 Op.getOperand(i), DAG.getIntPtrConstant(i));
6943 // Otherwise, expand into a number of unpckl*, start by extending each of
6944 // our (non-undef) elements to the full vector width with the element in the
6945 // bottom slot of the vector (which generates no code for SSE).
6946 for (unsigned i = 0; i < NumElems; ++i) {
6947 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6948 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6950 V[i] = DAG.getUNDEF(VT);
6953 // Next, we iteratively mix elements, e.g. for v4f32:
6954 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6955 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6956 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6957 unsigned EltStride = NumElems >> 1;
6958 while (EltStride != 0) {
6959 for (unsigned i = 0; i < EltStride; ++i) {
6960 // If V[i+EltStride] is undef and this is the first round of mixing,
6961 // then it is safe to just drop this shuffle: V[i] is already in the
6962 // right place, the one element (since it's the first round) being
6963 // inserted as undef can be dropped. This isn't safe for successive
6964 // rounds because they will permute elements within both vectors.
6965 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6966 EltStride == NumElems/2)
6969 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6978 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6979 // to create 256-bit vectors from two other 128-bit ones.
6980 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6982 MVT ResVT = Op.getSimpleValueType();
6984 assert((ResVT.is256BitVector() ||
6985 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6987 SDValue V1 = Op.getOperand(0);
6988 SDValue V2 = Op.getOperand(1);
6989 unsigned NumElems = ResVT.getVectorNumElements();
6990 if(ResVT.is256BitVector())
6991 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6993 if (Op.getNumOperands() == 4) {
6994 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6995 ResVT.getVectorNumElements()/2);
6996 SDValue V3 = Op.getOperand(2);
6997 SDValue V4 = Op.getOperand(3);
6998 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6999 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7001 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7004 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7005 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7006 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7007 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7008 Op.getNumOperands() == 4)));
7010 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7011 // from two other 128-bit ones.
7013 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7014 return LowerAVXCONCAT_VECTORS(Op, DAG);
7018 //===----------------------------------------------------------------------===//
7019 // Vector shuffle lowering
7021 // This is an experimental code path for lowering vector shuffles on x86. It is
7022 // designed to handle arbitrary vector shuffles and blends, gracefully
7023 // degrading performance as necessary. It works hard to recognize idiomatic
7024 // shuffles and lower them to optimal instruction patterns without leaving
7025 // a framework that allows reasonably efficient handling of all vector shuffle
7027 //===----------------------------------------------------------------------===//
7029 /// \brief Tiny helper function to identify a no-op mask.
7031 /// This is a somewhat boring predicate function. It checks whether the mask
7032 /// array input, which is assumed to be a single-input shuffle mask of the kind
7033 /// used by the X86 shuffle instructions (not a fully general
7034 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7035 /// in-place shuffle are 'no-op's.
7036 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7037 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7038 if (Mask[i] != -1 && Mask[i] != i)
7043 /// \brief Helper function to classify a mask as a single-input mask.
7045 /// This isn't a generic single-input test because in the vector shuffle
7046 /// lowering we canonicalize single inputs to be the first input operand. This
7047 /// means we can more quickly test for a single input by only checking whether
7048 /// an input from the second operand exists. We also assume that the size of
7049 /// mask corresponds to the size of the input vectors which isn't true in the
7050 /// fully general case.
7051 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7053 if (M >= (int)Mask.size())
7058 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7060 /// This helper function produces an 8-bit shuffle immediate corresponding to
7061 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7062 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7065 /// NB: We rely heavily on "undef" masks preserving the input lane.
7066 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7067 SelectionDAG &DAG) {
7068 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7069 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7070 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7071 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7072 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7075 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7076 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7077 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7078 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7079 return DAG.getConstant(Imm, MVT::i8);
7082 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7084 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7085 /// support for floating point shuffles but not integer shuffles. These
7086 /// instructions will incur a domain crossing penalty on some chips though so
7087 /// it is better to avoid lowering through this for integer vectors where
7089 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7090 const X86Subtarget *Subtarget,
7091 SelectionDAG &DAG) {
7093 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7094 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7095 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7097 ArrayRef<int> Mask = SVOp->getMask();
7098 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7100 if (isSingleInputShuffleMask(Mask)) {
7101 // Straight shuffle of a single input vector. Simulate this by using the
7102 // single input as both of the "inputs" to this instruction..
7103 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7104 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7105 DAG.getConstant(SHUFPDMask, MVT::i8));
7107 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7108 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7110 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7111 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7112 DAG.getConstant(SHUFPDMask, MVT::i8));
7115 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7117 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7118 /// the integer unit to minimize domain crossing penalties. However, for blends
7119 /// it falls back to the floating point shuffle operation with appropriate bit
7121 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7122 const X86Subtarget *Subtarget,
7123 SelectionDAG &DAG) {
7125 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7126 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7127 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7128 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7129 ArrayRef<int> Mask = SVOp->getMask();
7130 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7132 if (isSingleInputShuffleMask(Mask)) {
7133 // Straight shuffle of a single input vector. For everything from SSE2
7134 // onward this has a single fast instruction with no scary immediates.
7135 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7136 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7137 int WidenedMask[4] = {
7138 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7139 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7141 ISD::BITCAST, DL, MVT::v2i64,
7142 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7143 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7146 // We implement this with SHUFPD which is pretty lame because it will likely
7147 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7148 // However, all the alternatives are still more cycles and newer chips don't
7149 // have this problem. It would be really nice if x86 had better shuffles here.
7150 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7151 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7152 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7153 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7156 /// \brief Lower 4-lane 32-bit floating point shuffles.
7158 /// Uses instructions exclusively from the floating point unit to minimize
7159 /// domain crossing penalties, as these are sufficient to implement all v4f32
7161 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7162 const X86Subtarget *Subtarget,
7163 SelectionDAG &DAG) {
7165 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7166 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7167 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7168 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7169 ArrayRef<int> Mask = SVOp->getMask();
7170 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7172 SDValue LowV = V1, HighV = V2;
7173 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7176 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7178 if (NumV2Elements == 0)
7179 // Straight shuffle of a single input vector. We pass the input vector to
7180 // both operands to simulate this with a SHUFPS.
7181 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7182 getV4X86ShuffleImm8ForMask(Mask, DAG));
7184 if (NumV2Elements == 1) {
7186 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7188 // Compute the index adjacent to V2Index and in the same half by toggling
7190 int V2AdjIndex = V2Index ^ 1;
7192 if (Mask[V2AdjIndex] == -1) {
7193 // Handles all the cases where we have a single V2 element and an undef.
7194 // This will only ever happen in the high lanes because we commute the
7195 // vector otherwise.
7197 std::swap(LowV, HighV);
7198 NewMask[V2Index] -= 4;
7200 // Handle the case where the V2 element ends up adjacent to a V1 element.
7201 // To make this work, blend them together as the first step.
7202 int V1Index = V2AdjIndex;
7203 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7204 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7205 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7207 // Now proceed to reconstruct the final blend as we have the necessary
7208 // high or low half formed.
7215 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7216 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7218 } else if (NumV2Elements == 2) {
7219 if (Mask[0] < 4 && Mask[1] < 4) {
7220 // Handle the easy case where we have V1 in the low lanes and V2 in the
7221 // high lanes. We never see this reversed because we sort the shuffle.
7225 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7226 // trying to place elements directly, just blend them and set up the final
7227 // shuffle to place them.
7229 // The first two blend mask elements are for V1, the second two are for
7231 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7232 Mask[2] < 4 ? Mask[2] : Mask[3],
7233 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7234 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7235 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7236 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7238 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7241 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7242 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7243 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7244 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7247 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7248 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7251 /// \brief Lower 4-lane i32 vector shuffles.
7253 /// We try to handle these with integer-domain shuffles where we can, but for
7254 /// blends we use the floating point domain blend instructions.
7255 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7256 const X86Subtarget *Subtarget,
7257 SelectionDAG &DAG) {
7259 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7260 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7261 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7262 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7263 ArrayRef<int> Mask = SVOp->getMask();
7264 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7266 if (isSingleInputShuffleMask(Mask))
7267 // Straight shuffle of a single input vector. For everything from SSE2
7268 // onward this has a single fast instruction with no scary immediates.
7269 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7270 getV4X86ShuffleImm8ForMask(Mask, DAG));
7272 // We implement this with SHUFPS because it can blend from two vectors.
7273 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7274 // up the inputs, bypassing domain shift penalties that we would encur if we
7275 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7277 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7278 DAG.getVectorShuffle(
7280 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7281 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7284 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7285 /// shuffle lowering, and the most complex part.
7287 /// The lowering strategy is to try to form pairs of input lanes which are
7288 /// targeted at the same half of the final vector, and then use a dword shuffle
7289 /// to place them onto the right half, and finally unpack the paired lanes into
7290 /// their final position.
7292 /// The exact breakdown of how to form these dword pairs and align them on the
7293 /// correct sides is really tricky. See the comments within the function for
7294 /// more of the details.
7295 static SDValue lowerV8I16SingleInputVectorShuffle(
7296 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7297 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7298 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7299 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7300 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7302 SmallVector<int, 4> LoInputs;
7303 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7304 [](int M) { return M >= 0; });
7305 std::sort(LoInputs.begin(), LoInputs.end());
7306 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7307 SmallVector<int, 4> HiInputs;
7308 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7309 [](int M) { return M >= 0; });
7310 std::sort(HiInputs.begin(), HiInputs.end());
7311 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7313 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7314 int NumHToL = LoInputs.size() - NumLToL;
7316 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7317 int NumHToH = HiInputs.size() - NumLToH;
7318 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7319 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7320 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7321 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7323 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7324 // such inputs we can swap two of the dwords across the half mark and end up
7325 // with <=2 inputs to each half in each half. Once there, we can fall through
7326 // to the generic code below. For example:
7328 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7329 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7331 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7333 auto balanceSides = [&](ArrayRef<int> ThreeInputs, int OneInput,
7334 int ThreeInputHalfSum, int OneInputHalfOffset) {
7335 // Compute the index of dword with only one word among the three inputs in
7336 // a half by taking the sum of the half with three inputs and subtracting
7337 // the sum of the actual three inputs. The difference is the remaining
7339 int DWordA = (ThreeInputHalfSum -
7340 std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
7342 int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
7344 int PSHUFDMask[] = {0, 1, 2, 3};
7345 PSHUFDMask[DWordA] = DWordB;
7346 PSHUFDMask[DWordB] = DWordA;
7347 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7348 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7349 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7350 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7352 // Adjust the mask to match the new locations of A and B.
7354 if (M != -1 && M/2 == DWordA)
7355 M = 2 * DWordB + M % 2;
7356 else if (M != -1 && M/2 == DWordB)
7357 M = 2 * DWordA + M % 2;
7359 // Recurse back into this routine to re-compute state now that this isn't
7360 // a 3 and 1 problem.
7361 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7364 if (NumLToL == 3 && NumHToL == 1)
7365 return balanceSides(LToLInputs, HToLInputs[0], 0 + 1 + 2 + 3, 4);
7366 else if (NumLToL == 1 && NumHToL == 3)
7367 return balanceSides(HToLInputs, LToLInputs[0], 4 + 5 + 6 + 7, 0);
7368 else if (NumLToH == 1 && NumHToH == 3)
7369 return balanceSides(HToHInputs, LToHInputs[0], 4 + 5 + 6 + 7, 0);
7370 else if (NumLToH == 3 && NumHToH == 1)
7371 return balanceSides(LToHInputs, HToHInputs[0], 0 + 1 + 2 + 3, 4);
7373 // At this point there are at most two inputs to the low and high halves from
7374 // each half. That means the inputs can always be grouped into dwords and
7375 // those dwords can then be moved to the correct half with a dword shuffle.
7376 // We use at most one low and one high word shuffle to collect these paired
7377 // inputs into dwords, and finally a dword shuffle to place them.
7378 int PSHUFLMask[4] = {-1, -1, -1, -1};
7379 int PSHUFHMask[4] = {-1, -1, -1, -1};
7380 int PSHUFDMask[4] = {-1, -1, -1, -1};
7382 // First fix the masks for all the inputs that are staying in their
7383 // original halves. This will then dictate the targets of the cross-half
7385 auto fixInPlaceInputs =
7386 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7387 MutableArrayRef<int> SourceHalfMask,
7388 MutableArrayRef<int> HalfMask, int HalfOffset) {
7389 if (InPlaceInputs.empty())
7391 if (InPlaceInputs.size() == 1) {
7392 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7393 InPlaceInputs[0] - HalfOffset;
7394 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7397 if (IncomingInputs.empty()) {
7398 // Just fix all of the in place inputs.
7399 for (int Input : InPlaceInputs) {
7400 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7401 PSHUFDMask[Input / 2] = Input / 2;
7406 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7407 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7408 InPlaceInputs[0] - HalfOffset;
7409 // Put the second input next to the first so that they are packed into
7410 // a dword. We find the adjacent index by toggling the low bit.
7411 int AdjIndex = InPlaceInputs[0] ^ 1;
7412 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7413 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7414 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7416 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7417 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7419 // Now gather the cross-half inputs and place them into a free dword of
7420 // their target half.
7421 // FIXME: This operation could almost certainly be simplified dramatically to
7422 // look more like the 3-1 fixing operation.
7423 auto moveInputsToRightHalf = [&PSHUFDMask](
7424 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7425 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7426 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7428 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7429 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7431 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7433 int LowWord = Word & ~1;
7434 int HighWord = Word | 1;
7435 return isWordClobbered(SourceHalfMask, LowWord) ||
7436 isWordClobbered(SourceHalfMask, HighWord);
7439 if (IncomingInputs.empty())
7442 if (ExistingInputs.empty()) {
7443 // Map any dwords with inputs from them into the right half.
7444 for (int Input : IncomingInputs) {
7445 // If the source half mask maps over the inputs, turn those into
7446 // swaps and use the swapped lane.
7447 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7448 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7449 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7450 Input - SourceOffset;
7451 // We have to swap the uses in our half mask in one sweep.
7452 for (int &M : HalfMask)
7453 if (M == SourceHalfMask[Input - SourceOffset])
7455 else if (M == Input)
7456 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7458 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7459 Input - SourceOffset &&
7460 "Previous placement doesn't match!");
7462 // Note that this correctly re-maps both when we do a swap and when
7463 // we observe the other side of the swap above. We rely on that to
7464 // avoid swapping the members of the input list directly.
7465 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7468 // Map the input's dword into the correct half.
7469 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7470 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7472 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7474 "Previous placement doesn't match!");
7477 // And just directly shift any other-half mask elements to be same-half
7478 // as we will have mirrored the dword containing the element into the
7479 // same position within that half.
7480 for (int &M : HalfMask)
7481 if (M >= SourceOffset && M < SourceOffset + 4) {
7482 M = M - SourceOffset + DestOffset;
7483 assert(M >= 0 && "This should never wrap below zero!");
7488 // Ensure we have the input in a viable dword of its current half. This
7489 // is particularly tricky because the original position may be clobbered
7490 // by inputs being moved and *staying* in that half.
7491 if (IncomingInputs.size() == 1) {
7492 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7493 int InputFixed = std::find(std::begin(SourceHalfMask),
7494 std::end(SourceHalfMask), -1) -
7495 std::begin(SourceHalfMask) + SourceOffset;
7496 SourceHalfMask[InputFixed - SourceOffset] =
7497 IncomingInputs[0] - SourceOffset;
7498 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7500 IncomingInputs[0] = InputFixed;
7502 } else if (IncomingInputs.size() == 2) {
7503 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7504 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7505 // We have two non-adjacent or clobbered inputs we need to extract from
7506 // the source half. To do this, we need to map them into some adjacent
7507 // dword slot in the source mask.
7508 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
7509 IncomingInputs[1] - SourceOffset};
7511 // If there is a free slot in the source half mask adjacent to one of
7512 // the inputs, place the other input in it. We use (Index XOR 1) to
7513 // compute an adjacent index.
7514 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
7515 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
7516 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
7517 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7518 InputsFixed[1] = InputsFixed[0] ^ 1;
7519 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
7520 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
7521 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
7522 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
7523 InputsFixed[0] = InputsFixed[1] ^ 1;
7524 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
7525 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
7526 // The two inputs are in the same DWord but it is clobbered and the
7527 // adjacent DWord isn't used at all. Move both inputs to the free
7529 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
7530 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
7531 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
7532 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
7534 // The only way we hit this point is if there is no clobbering
7535 // (because there are no off-half inputs to this half) and there is no
7536 // free slot adjacent to one of the inputs. In this case, we have to
7537 // swap an input with a non-input.
7538 for (int i = 0; i < 4; ++i)
7539 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
7540 "We can't handle any clobbers here!");
7541 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
7542 "Cannot have adjacent inputs here!");
7544 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7545 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
7547 // We also have to update the final source mask in this case because
7548 // it may need to undo the above swap.
7549 for (int &M : FinalSourceHalfMask)
7550 if (M == (InputsFixed[0] ^ 1))
7552 else if (M == InputsFixed[1])
7553 M = InputsFixed[0] ^ 1;
7555 InputsFixed[1] = InputsFixed[0] ^ 1;
7558 // Point everything at the fixed inputs.
7559 for (int &M : HalfMask)
7560 if (M == IncomingInputs[0])
7561 M = InputsFixed[0] + SourceOffset;
7562 else if (M == IncomingInputs[1])
7563 M = InputsFixed[1] + SourceOffset;
7565 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
7566 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
7569 llvm_unreachable("Unhandled input size!");
7572 // Now hoist the DWord down to the right half.
7573 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7574 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7575 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7576 for (int &M : HalfMask)
7577 for (int Input : IncomingInputs)
7579 M = FreeDWord * 2 + Input % 2;
7581 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
7582 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7583 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
7584 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7586 // Now enact all the shuffles we've computed to move the inputs into their
7588 if (!isNoopShuffleMask(PSHUFLMask))
7589 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7590 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7591 if (!isNoopShuffleMask(PSHUFHMask))
7592 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7593 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7594 if (!isNoopShuffleMask(PSHUFDMask))
7595 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7596 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7597 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7598 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7600 // At this point, each half should contain all its inputs, and we can then
7601 // just shuffle them into their final position.
7602 assert(std::count_if(LoMask.begin(), LoMask.end(),
7603 [](int M) { return M >= 4; }) == 0 &&
7604 "Failed to lift all the high half inputs to the low mask!");
7605 assert(std::count_if(HiMask.begin(), HiMask.end(),
7606 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7607 "Failed to lift all the low half inputs to the high mask!");
7609 // Do a half shuffle for the low mask.
7610 if (!isNoopShuffleMask(LoMask))
7611 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7612 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7614 // Do a half shuffle with the high mask after shifting its values down.
7615 for (int &M : HiMask)
7618 if (!isNoopShuffleMask(HiMask))
7619 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7620 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7625 /// \brief Detect whether the mask pattern should be lowered through
7628 /// This essentially tests whether viewing the mask as an interleaving of two
7629 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7630 /// lowering it through interleaving is a significantly better strategy.
7631 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7632 int NumEvenInputs[2] = {0, 0};
7633 int NumOddInputs[2] = {0, 0};
7634 int NumLoInputs[2] = {0, 0};
7635 int NumHiInputs[2] = {0, 0};
7636 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7640 int InputIdx = Mask[i] >= Size;
7643 ++NumLoInputs[InputIdx];
7645 ++NumHiInputs[InputIdx];
7648 ++NumEvenInputs[InputIdx];
7650 ++NumOddInputs[InputIdx];
7653 // The minimum number of cross-input results for both the interleaved and
7654 // split cases. If interleaving results in fewer cross-input results, return
7656 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7657 NumEvenInputs[0] + NumOddInputs[1]);
7658 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7659 NumLoInputs[0] + NumHiInputs[1]);
7660 return InterleavedCrosses < SplitCrosses;
7663 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7665 /// This strategy only works when the inputs from each vector fit into a single
7666 /// half of that vector, and generally there are not so many inputs as to leave
7667 /// the in-place shuffles required highly constrained (and thus expensive). It
7668 /// shifts all the inputs into a single side of both input vectors and then
7669 /// uses an unpack to interleave these inputs in a single vector. At that
7670 /// point, we will fall back on the generic single input shuffle lowering.
7671 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7673 MutableArrayRef<int> Mask,
7674 const X86Subtarget *Subtarget,
7675 SelectionDAG &DAG) {
7676 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7677 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7678 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7679 for (int i = 0; i < 8; ++i)
7680 if (Mask[i] >= 0 && Mask[i] < 4)
7681 LoV1Inputs.push_back(i);
7682 else if (Mask[i] >= 4 && Mask[i] < 8)
7683 HiV1Inputs.push_back(i);
7684 else if (Mask[i] >= 8 && Mask[i] < 12)
7685 LoV2Inputs.push_back(i);
7686 else if (Mask[i] >= 12)
7687 HiV2Inputs.push_back(i);
7689 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7690 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7693 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7694 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7695 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7697 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7698 HiV1Inputs.size() + HiV2Inputs.size();
7700 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7701 ArrayRef<int> HiInputs, bool MoveToLo,
7703 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7704 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7705 if (BadInputs.empty())
7708 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7709 int MoveOffset = MoveToLo ? 0 : 4;
7711 if (GoodInputs.empty()) {
7712 for (int BadInput : BadInputs) {
7713 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7714 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7717 if (GoodInputs.size() == 2) {
7718 // If the low inputs are spread across two dwords, pack them into
7720 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
7721 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
7722 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
7723 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
7725 // Otherwise pin the good inputs.
7726 for (int GoodInput : GoodInputs)
7727 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7730 if (BadInputs.size() == 2) {
7731 // If we have two bad inputs then there may be either one or two good
7732 // inputs fixed in place. Find a fixed input, and then find the *other*
7733 // two adjacent indices by using modular arithmetic.
7735 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
7736 [](int M) { return M >= 0; }) -
7737 std::begin(MoveMask);
7739 (((GoodMaskIdx - MoveOffset) & ~1) + 2 % 4) + MoveOffset;
7740 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7741 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7742 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7743 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
7744 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7745 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
7747 assert(BadInputs.size() == 1 && "All sizes handled");
7748 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
7749 std::end(MoveMask), -1) -
7750 std::begin(MoveMask);
7751 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7752 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7756 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7759 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7761 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7764 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7765 // cross-half traffic in the final shuffle.
7767 // Munge the mask to be a single-input mask after the unpack merges the
7771 M = 2 * (M % 4) + (M / 8);
7773 return DAG.getVectorShuffle(
7774 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7775 DL, MVT::v8i16, V1, V2),
7776 DAG.getUNDEF(MVT::v8i16), Mask);
7779 /// \brief Generic lowering of 8-lane i16 shuffles.
7781 /// This handles both single-input shuffles and combined shuffle/blends with
7782 /// two inputs. The single input shuffles are immediately delegated to
7783 /// a dedicated lowering routine.
7785 /// The blends are lowered in one of three fundamental ways. If there are few
7786 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7787 /// of the input is significantly cheaper when lowered as an interleaving of
7788 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7789 /// halves of the inputs separately (making them have relatively few inputs)
7790 /// and then concatenate them.
7791 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7792 const X86Subtarget *Subtarget,
7793 SelectionDAG &DAG) {
7795 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7796 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7797 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7799 ArrayRef<int> OrigMask = SVOp->getMask();
7800 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7801 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7802 MutableArrayRef<int> Mask(MaskStorage);
7804 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7806 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7807 auto isV2 = [](int M) { return M >= 8; };
7809 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7810 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7812 if (NumV2Inputs == 0)
7813 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7815 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7816 "to be V1-input shuffles.");
7818 if (NumV1Inputs + NumV2Inputs <= 4)
7819 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7821 // Check whether an interleaving lowering is likely to be more efficient.
7822 // This isn't perfect but it is a strong heuristic that tends to work well on
7823 // the kinds of shuffles that show up in practice.
7825 // FIXME: Handle 1x, 2x, and 4x interleaving.
7826 if (shouldLowerAsInterleaving(Mask)) {
7827 // FIXME: Figure out whether we should pack these into the low or high
7830 int EMask[8], OMask[8];
7831 for (int i = 0; i < 4; ++i) {
7832 EMask[i] = Mask[2*i];
7833 OMask[i] = Mask[2*i + 1];
7838 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7839 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7841 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7844 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7845 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7847 for (int i = 0; i < 4; ++i) {
7848 LoBlendMask[i] = Mask[i];
7849 HiBlendMask[i] = Mask[i + 4];
7852 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7853 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7854 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7855 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7857 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7858 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7861 /// \brief Check whether a compaction lowering can be done by dropping even
7862 /// elements and compute how many times even elements must be dropped.
7864 /// This handles shuffles which take every Nth element where N is a power of
7865 /// two. Example shuffle masks:
7867 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
7868 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
7869 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
7870 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
7871 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
7872 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
7874 /// Any of these lanes can of course be undef.
7876 /// This routine only supports N <= 3.
7877 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
7880 /// \returns N above, or the number of times even elements must be dropped if
7881 /// there is such a number. Otherwise returns zero.
7882 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
7883 // Figure out whether we're looping over two inputs or just one.
7884 bool IsSingleInput = isSingleInputShuffleMask(Mask);
7886 // The modulus for the shuffle vector entries is based on whether this is
7887 // a single input or not.
7888 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
7889 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
7890 "We should only be called with masks with a power-of-2 size!");
7892 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
7894 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
7895 // and 2^3 simultaneously. This is because we may have ambiguity with
7896 // partially undef inputs.
7897 bool ViableForN[3] = {true, true, true};
7899 for (int i = 0, e = Mask.size(); i < e; ++i) {
7900 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
7905 bool IsAnyViable = false;
7906 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
7907 if (ViableForN[j]) {
7910 // The shuffle mask must be equal to (i * 2^N) % M.
7911 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
7914 ViableForN[j] = false;
7916 // Early exit if we exhaust the possible powers of two.
7921 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
7925 // Return 0 as there is no viable power of two.
7929 /// \brief Generic lowering of v16i8 shuffles.
7931 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7932 /// detect any complexity reducing interleaving. If that doesn't help, it uses
7933 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
7934 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
7936 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7937 const X86Subtarget *Subtarget,
7938 SelectionDAG &DAG) {
7940 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7941 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7942 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7943 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7944 ArrayRef<int> OrigMask = SVOp->getMask();
7945 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
7946 int MaskStorage[16] = {
7947 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7948 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
7949 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
7950 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
7951 MutableArrayRef<int> Mask(MaskStorage);
7952 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
7953 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
7955 // For single-input shuffles, there are some nicer lowering tricks we can use.
7956 if (isSingleInputShuffleMask(Mask)) {
7957 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
7958 // Notably, this handles splat and partial-splat shuffles more efficiently.
7959 // However, it only makes sense if the pre-duplication shuffle simplifies
7960 // things significantly. Currently, this means we need to be able to
7961 // express the pre-duplication shuffle as an i16 shuffle.
7963 // FIXME: We should check for other patterns which can be widened into an
7964 // i16 shuffle as well.
7965 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
7966 for (int i = 0; i < 16; i += 2) {
7967 if (Mask[i] != Mask[i + 1])
7972 auto tryToWidenViaDuplication = [&]() -> SDValue {
7973 if (!canWidenViaDuplication(Mask))
7975 SmallVector<int, 4> LoInputs;
7976 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
7977 [](int M) { return M >= 0 && M < 8; });
7978 std::sort(LoInputs.begin(), LoInputs.end());
7979 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
7981 SmallVector<int, 4> HiInputs;
7982 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
7983 [](int M) { return M >= 8; });
7984 std::sort(HiInputs.begin(), HiInputs.end());
7985 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
7988 bool TargetLo = LoInputs.size() >= HiInputs.size();
7989 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
7990 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
7992 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7993 SmallDenseMap<int, int, 8> LaneMap;
7994 for (int I : InPlaceInputs) {
7995 PreDupI16Shuffle[I/2] = I/2;
7998 int j = TargetLo ? 0 : 4, je = j + 4;
7999 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8000 // Check if j is already a shuffle of this input. This happens when
8001 // there are two adjacent bytes after we move the low one.
8002 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8003 // If we haven't yet mapped the input, search for a slot into which
8005 while (j < je && PreDupI16Shuffle[j] != -1)
8009 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8012 // Map this input with the i16 shuffle.
8013 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8016 // Update the lane map based on the mapping we ended up with.
8017 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8020 ISD::BITCAST, DL, MVT::v16i8,
8021 DAG.getVectorShuffle(MVT::v8i16, DL,
8022 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8023 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8025 // Unpack the bytes to form the i16s that will be shuffled into place.
8026 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8027 MVT::v16i8, V1, V1);
8029 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8030 for (int i = 0; i < 16; i += 2) {
8032 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8033 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8036 ISD::BITCAST, DL, MVT::v16i8,
8037 DAG.getVectorShuffle(MVT::v8i16, DL,
8038 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8039 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8041 if (SDValue V = tryToWidenViaDuplication())
8045 // Check whether an interleaving lowering is likely to be more efficient.
8046 // This isn't perfect but it is a strong heuristic that tends to work well on
8047 // the kinds of shuffles that show up in practice.
8049 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8050 if (shouldLowerAsInterleaving(Mask)) {
8051 // FIXME: Figure out whether we should pack these into the low or high
8054 int EMask[16], OMask[16];
8055 for (int i = 0; i < 8; ++i) {
8056 EMask[i] = Mask[2*i];
8057 OMask[i] = Mask[2*i + 1];
8062 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8063 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8065 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8068 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8069 // with PSHUFB. It is important to do this before we attempt to generate any
8070 // blends but after all of the single-input lowerings. If the single input
8071 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8072 // want to preserve that and we can DAG combine any longer sequences into
8073 // a PSHUFB in the end. But once we start blending from multiple inputs,
8074 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8075 // and there are *very* few patterns that would actually be faster than the
8076 // PSHUFB approach because of its ability to zero lanes.
8078 // FIXME: The only exceptions to the above are blends which are exact
8079 // interleavings with direct instructions supporting them. We currently don't
8080 // handle those well here.
8081 if (Subtarget->hasSSSE3()) {
8084 for (int i = 0; i < 16; ++i)
8085 if (Mask[i] == -1) {
8086 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8088 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8090 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8092 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8093 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8094 if (isSingleInputShuffleMask(Mask))
8095 return V1; // Single inputs are easy.
8097 // Otherwise, blend the two.
8098 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8099 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8100 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8103 // Check whether a compaction lowering can be done. This handles shuffles
8104 // which take every Nth element for some even N. See the helper function for
8107 // We special case these as they can be particularly efficiently handled with
8108 // the PACKUSB instruction on x86 and they show up in common patterns of
8109 // rearranging bytes to truncate wide elements.
8110 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8111 // NumEvenDrops is the power of two stride of the elements. Another way of
8112 // thinking about it is that we need to drop the even elements this many
8113 // times to get the original input.
8114 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8116 // First we need to zero all the dropped bytes.
8117 assert(NumEvenDrops <= 3 &&
8118 "No support for dropping even elements more than 3 times.");
8119 // We use the mask type to pick which bytes are preserved based on how many
8120 // elements are dropped.
8121 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8122 SDValue ByteClearMask =
8123 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8124 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8125 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8127 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8129 // Now pack things back together.
8130 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8131 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8132 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8133 for (int i = 1; i < NumEvenDrops; ++i) {
8134 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8135 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8141 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8142 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8143 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8144 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8146 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8147 MutableArrayRef<int> V1HalfBlendMask,
8148 MutableArrayRef<int> V2HalfBlendMask) {
8149 for (int i = 0; i < 8; ++i)
8150 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8151 V1HalfBlendMask[i] = HalfMask[i];
8153 } else if (HalfMask[i] >= 16) {
8154 V2HalfBlendMask[i] = HalfMask[i] - 16;
8155 HalfMask[i] = i + 8;
8158 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8159 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8161 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8163 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8164 MutableArrayRef<int> HiBlendMask) {
8166 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8167 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8169 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8170 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8171 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8172 [](int M) { return M >= 0 && M % 2 == 1; })) {
8173 // Use a mask to drop the high bytes.
8174 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8175 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8176 DAG.getConstant(0x00FF, MVT::v8i16));
8178 // This will be a single vector shuffle instead of a blend so nuke V2.
8179 V2 = DAG.getUNDEF(MVT::v8i16);
8181 // Squash the masks to point directly into V1.
8182 for (int &M : LoBlendMask)
8185 for (int &M : HiBlendMask)
8189 // Otherwise just unpack the low half of V into V1 and the high half into
8190 // V2 so that we can blend them as i16s.
8191 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8192 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8193 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8194 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8197 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8198 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8199 return std::make_pair(BlendedLo, BlendedHi);
8201 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8202 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8203 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8205 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8206 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8208 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8211 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8213 /// This routine breaks down the specific type of 128-bit shuffle and
8214 /// dispatches to the lowering routines accordingly.
8215 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8216 MVT VT, const X86Subtarget *Subtarget,
8217 SelectionDAG &DAG) {
8218 switch (VT.SimpleTy) {
8220 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8222 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8224 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8226 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8228 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8230 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8233 llvm_unreachable("Unimplemented!");
8237 /// \brief Tiny helper function to test whether adjacent masks are sequential.
8238 static bool areAdjacentMasksSequential(ArrayRef<int> Mask) {
8239 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8240 if (Mask[i] + 1 != Mask[i+1])
8246 /// \brief Top-level lowering for x86 vector shuffles.
8248 /// This handles decomposition, canonicalization, and lowering of all x86
8249 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8250 /// above in helper routines. The canonicalization attempts to widen shuffles
8251 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8252 /// s.t. only one of the two inputs needs to be tested, etc.
8253 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8254 SelectionDAG &DAG) {
8255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8256 ArrayRef<int> Mask = SVOp->getMask();
8257 SDValue V1 = Op.getOperand(0);
8258 SDValue V2 = Op.getOperand(1);
8259 MVT VT = Op.getSimpleValueType();
8260 int NumElements = VT.getVectorNumElements();
8263 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8265 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8266 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8267 if (V1IsUndef && V2IsUndef)
8268 return DAG.getUNDEF(VT);
8270 // When we create a shuffle node we put the UNDEF node to second operand,
8271 // but in some cases the first operand may be transformed to UNDEF.
8272 // In this case we should just commute the node.
8274 return DAG.getCommutedVectorShuffle(*SVOp);
8276 // Check for non-undef masks pointing at an undef vector and make the masks
8277 // undef as well. This makes it easier to match the shuffle based solely on
8281 if (M >= NumElements) {
8282 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8283 for (int &M : NewMask)
8284 if (M >= NumElements)
8286 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8289 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8290 // lanes but wider integers. We cap this to not form integers larger than i64
8291 // but it might be interesting to form i128 integers to handle flipping the
8292 // low and high halves of AVX 256-bit vectors.
8293 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8294 areAdjacentMasksSequential(Mask)) {
8295 SmallVector<int, 8> NewMask;
8296 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8297 NewMask.push_back(Mask[i] / 2);
8299 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8300 VT.getVectorNumElements() / 2);
8301 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8302 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8303 return DAG.getNode(ISD::BITCAST, dl, VT,
8304 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8307 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8308 for (int M : SVOp->getMask())
8311 else if (M < NumElements)
8316 // Commute the shuffle as needed such that more elements come from V1 than
8317 // V2. This allows us to match the shuffle pattern strictly on how many
8318 // elements come from V1 without handling the symmetric cases.
8319 if (NumV2Elements > NumV1Elements)
8320 return DAG.getCommutedVectorShuffle(*SVOp);
8322 // When the number of V1 and V2 elements are the same, try to minimize the
8323 // number of uses of V2 in the low half of the vector.
8324 if (NumV1Elements == NumV2Elements) {
8325 int LowV1Elements = 0, LowV2Elements = 0;
8326 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8327 if (M >= NumElements)
8331 if (LowV2Elements > LowV1Elements)
8332 return DAG.getCommutedVectorShuffle(*SVOp);
8335 // For each vector width, delegate to a specialized lowering routine.
8336 if (VT.getSizeInBits() == 128)
8337 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8339 llvm_unreachable("Unimplemented!");
8343 //===----------------------------------------------------------------------===//
8344 // Legacy vector shuffle lowering
8346 // This code is the legacy code handling vector shuffles until the above
8347 // replaces its functionality and performance.
8348 //===----------------------------------------------------------------------===//
8350 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8351 bool hasInt256, unsigned *MaskOut = nullptr) {
8352 MVT EltVT = VT.getVectorElementType();
8354 // There is no blend with immediate in AVX-512.
8355 if (VT.is512BitVector())
8358 if (!hasSSE41 || EltVT == MVT::i8)
8360 if (!hasInt256 && VT == MVT::v16i16)
8363 unsigned MaskValue = 0;
8364 unsigned NumElems = VT.getVectorNumElements();
8365 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8366 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8367 unsigned NumElemsInLane = NumElems / NumLanes;
8369 // Blend for v16i16 should be symetric for the both lanes.
8370 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8372 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8373 int EltIdx = MaskVals[i];
8375 if ((EltIdx < 0 || EltIdx == (int)i) &&
8376 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8379 if (((unsigned)EltIdx == (i + NumElems)) &&
8380 (SndLaneEltIdx < 0 ||
8381 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8382 MaskValue |= (1 << i);
8388 *MaskOut = MaskValue;
8392 // Try to lower a shuffle node into a simple blend instruction.
8393 // This function assumes isBlendMask returns true for this
8394 // SuffleVectorSDNode
8395 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8397 const X86Subtarget *Subtarget,
8398 SelectionDAG &DAG) {
8399 MVT VT = SVOp->getSimpleValueType(0);
8400 MVT EltVT = VT.getVectorElementType();
8401 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8402 Subtarget->hasInt256() && "Trying to lower a "
8403 "VECTOR_SHUFFLE to a Blend but "
8404 "with the wrong mask"));
8405 SDValue V1 = SVOp->getOperand(0);
8406 SDValue V2 = SVOp->getOperand(1);
8408 unsigned NumElems = VT.getVectorNumElements();
8410 // Convert i32 vectors to floating point if it is not AVX2.
8411 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8413 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8414 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8416 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8417 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8420 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8421 DAG.getConstant(MaskValue, MVT::i32));
8422 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8425 /// In vector type \p VT, return true if the element at index \p InputIdx
8426 /// falls on a different 128-bit lane than \p OutputIdx.
8427 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8428 unsigned OutputIdx) {
8429 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8430 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8433 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8434 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8435 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8436 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8438 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8439 SelectionDAG &DAG) {
8440 MVT VT = V1.getSimpleValueType();
8441 assert(VT.is128BitVector() || VT.is256BitVector());
8443 MVT EltVT = VT.getVectorElementType();
8444 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8445 unsigned NumElts = VT.getVectorNumElements();
8447 SmallVector<SDValue, 32> PshufbMask;
8448 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8449 int InputIdx = MaskVals[OutputIdx];
8450 unsigned InputByteIdx;
8452 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8453 InputByteIdx = 0x80;
8455 // Cross lane is not allowed.
8456 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8458 InputByteIdx = InputIdx * EltSizeInBytes;
8459 // Index is an byte offset within the 128-bit lane.
8460 InputByteIdx &= 0xf;
8463 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8464 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8465 if (InputByteIdx != 0x80)
8470 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8472 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8473 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8474 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8477 // v8i16 shuffles - Prefer shuffles in the following order:
8478 // 1. [all] pshuflw, pshufhw, optional move
8479 // 2. [ssse3] 1 x pshufb
8480 // 3. [ssse3] 2 x pshufb + 1 x por
8481 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8483 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8484 SelectionDAG &DAG) {
8485 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8486 SDValue V1 = SVOp->getOperand(0);
8487 SDValue V2 = SVOp->getOperand(1);
8489 SmallVector<int, 8> MaskVals;
8491 // Determine if more than 1 of the words in each of the low and high quadwords
8492 // of the result come from the same quadword of one of the two inputs. Undef
8493 // mask values count as coming from any quadword, for better codegen.
8495 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8496 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8497 unsigned LoQuad[] = { 0, 0, 0, 0 };
8498 unsigned HiQuad[] = { 0, 0, 0, 0 };
8499 // Indices of quads used.
8500 std::bitset<4> InputQuads;
8501 for (unsigned i = 0; i < 8; ++i) {
8502 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8503 int EltIdx = SVOp->getMaskElt(i);
8504 MaskVals.push_back(EltIdx);
8513 InputQuads.set(EltIdx / 4);
8516 int BestLoQuad = -1;
8517 unsigned MaxQuad = 1;
8518 for (unsigned i = 0; i < 4; ++i) {
8519 if (LoQuad[i] > MaxQuad) {
8521 MaxQuad = LoQuad[i];
8525 int BestHiQuad = -1;
8527 for (unsigned i = 0; i < 4; ++i) {
8528 if (HiQuad[i] > MaxQuad) {
8530 MaxQuad = HiQuad[i];
8534 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8535 // of the two input vectors, shuffle them into one input vector so only a
8536 // single pshufb instruction is necessary. If there are more than 2 input
8537 // quads, disable the next transformation since it does not help SSSE3.
8538 bool V1Used = InputQuads[0] || InputQuads[1];
8539 bool V2Used = InputQuads[2] || InputQuads[3];
8540 if (Subtarget->hasSSSE3()) {
8541 if (InputQuads.count() == 2 && V1Used && V2Used) {
8542 BestLoQuad = InputQuads[0] ? 0 : 1;
8543 BestHiQuad = InputQuads[2] ? 2 : 3;
8545 if (InputQuads.count() > 2) {
8551 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8552 // the shuffle mask. If a quad is scored as -1, that means that it contains
8553 // words from all 4 input quadwords.
8555 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8557 BestLoQuad < 0 ? 0 : BestLoQuad,
8558 BestHiQuad < 0 ? 1 : BestHiQuad
8560 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8561 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8562 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8563 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8565 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8566 // source words for the shuffle, to aid later transformations.
8567 bool AllWordsInNewV = true;
8568 bool InOrder[2] = { true, true };
8569 for (unsigned i = 0; i != 8; ++i) {
8570 int idx = MaskVals[i];
8572 InOrder[i/4] = false;
8573 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8575 AllWordsInNewV = false;
8579 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8580 if (AllWordsInNewV) {
8581 for (int i = 0; i != 8; ++i) {
8582 int idx = MaskVals[i];
8585 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8586 if ((idx != i) && idx < 4)
8588 if ((idx != i) && idx > 3)
8597 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8598 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8599 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8600 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8601 unsigned TargetMask = 0;
8602 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8603 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8604 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8605 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8606 getShufflePSHUFLWImmediate(SVOp);
8607 V1 = NewV.getOperand(0);
8608 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8612 // Promote splats to a larger type which usually leads to more efficient code.
8613 // FIXME: Is this true if pshufb is available?
8614 if (SVOp->isSplat())
8615 return PromoteSplat(SVOp, DAG);
8617 // If we have SSSE3, and all words of the result are from 1 input vector,
8618 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8619 // is present, fall back to case 4.
8620 if (Subtarget->hasSSSE3()) {
8621 SmallVector<SDValue,16> pshufbMask;
8623 // If we have elements from both input vectors, set the high bit of the
8624 // shuffle mask element to zero out elements that come from V2 in the V1
8625 // mask, and elements that come from V1 in the V2 mask, so that the two
8626 // results can be OR'd together.
8627 bool TwoInputs = V1Used && V2Used;
8628 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8630 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8632 // Calculate the shuffle mask for the second input, shuffle it, and
8633 // OR it with the first shuffled input.
8634 CommuteVectorShuffleMask(MaskVals, 8);
8635 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8636 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8637 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8640 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8641 // and update MaskVals with new element order.
8642 std::bitset<8> InOrder;
8643 if (BestLoQuad >= 0) {
8644 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8645 for (int i = 0; i != 4; ++i) {
8646 int idx = MaskVals[i];
8649 } else if ((idx / 4) == BestLoQuad) {
8654 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8657 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8658 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8659 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8661 getShufflePSHUFLWImmediate(SVOp), DAG);
8665 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8666 // and update MaskVals with the new element order.
8667 if (BestHiQuad >= 0) {
8668 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8669 for (unsigned i = 4; i != 8; ++i) {
8670 int idx = MaskVals[i];
8673 } else if ((idx / 4) == BestHiQuad) {
8674 MaskV[i] = (idx & 3) + 4;
8678 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8681 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8682 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8683 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8685 getShufflePSHUFHWImmediate(SVOp), DAG);
8689 // In case BestHi & BestLo were both -1, which means each quadword has a word
8690 // from each of the four input quadwords, calculate the InOrder bitvector now
8691 // before falling through to the insert/extract cleanup.
8692 if (BestLoQuad == -1 && BestHiQuad == -1) {
8694 for (int i = 0; i != 8; ++i)
8695 if (MaskVals[i] < 0 || MaskVals[i] == i)
8699 // The other elements are put in the right place using pextrw and pinsrw.
8700 for (unsigned i = 0; i != 8; ++i) {
8703 int EltIdx = MaskVals[i];
8706 SDValue ExtOp = (EltIdx < 8) ?
8707 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8708 DAG.getIntPtrConstant(EltIdx)) :
8709 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8710 DAG.getIntPtrConstant(EltIdx - 8));
8711 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8712 DAG.getIntPtrConstant(i));
8717 /// \brief v16i16 shuffles
8719 /// FIXME: We only support generation of a single pshufb currently. We can
8720 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8721 /// well (e.g 2 x pshufb + 1 x por).
8723 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8724 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8725 SDValue V1 = SVOp->getOperand(0);
8726 SDValue V2 = SVOp->getOperand(1);
8729 if (V2.getOpcode() != ISD::UNDEF)
8732 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8733 return getPSHUFB(MaskVals, V1, dl, DAG);
8736 // v16i8 shuffles - Prefer shuffles in the following order:
8737 // 1. [ssse3] 1 x pshufb
8738 // 2. [ssse3] 2 x pshufb + 1 x por
8739 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8740 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8741 const X86Subtarget* Subtarget,
8742 SelectionDAG &DAG) {
8743 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8744 SDValue V1 = SVOp->getOperand(0);
8745 SDValue V2 = SVOp->getOperand(1);
8747 ArrayRef<int> MaskVals = SVOp->getMask();
8749 // Promote splats to a larger type which usually leads to more efficient code.
8750 // FIXME: Is this true if pshufb is available?
8751 if (SVOp->isSplat())
8752 return PromoteSplat(SVOp, DAG);
8754 // If we have SSSE3, case 1 is generated when all result bytes come from
8755 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8756 // present, fall back to case 3.
8758 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8759 if (Subtarget->hasSSSE3()) {
8760 SmallVector<SDValue,16> pshufbMask;
8762 // If all result elements are from one input vector, then only translate
8763 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8765 // Otherwise, we have elements from both input vectors, and must zero out
8766 // elements that come from V2 in the first mask, and V1 in the second mask
8767 // so that we can OR them together.
8768 for (unsigned i = 0; i != 16; ++i) {
8769 int EltIdx = MaskVals[i];
8770 if (EltIdx < 0 || EltIdx >= 16)
8772 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8774 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8775 DAG.getNode(ISD::BUILD_VECTOR, dl,
8776 MVT::v16i8, pshufbMask));
8778 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8779 // the 2nd operand if it's undefined or zero.
8780 if (V2.getOpcode() == ISD::UNDEF ||
8781 ISD::isBuildVectorAllZeros(V2.getNode()))
8784 // Calculate the shuffle mask for the second input, shuffle it, and
8785 // OR it with the first shuffled input.
8787 for (unsigned i = 0; i != 16; ++i) {
8788 int EltIdx = MaskVals[i];
8789 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8790 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8792 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8793 DAG.getNode(ISD::BUILD_VECTOR, dl,
8794 MVT::v16i8, pshufbMask));
8795 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8798 // No SSSE3 - Calculate in place words and then fix all out of place words
8799 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8800 // the 16 different words that comprise the two doublequadword input vectors.
8801 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8802 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8804 for (int i = 0; i != 8; ++i) {
8805 int Elt0 = MaskVals[i*2];
8806 int Elt1 = MaskVals[i*2+1];
8808 // This word of the result is all undef, skip it.
8809 if (Elt0 < 0 && Elt1 < 0)
8812 // This word of the result is already in the correct place, skip it.
8813 if ((Elt0 == i*2) && (Elt1 == i*2+1))
8816 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8817 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8820 // If Elt0 and Elt1 are defined, are consecutive, and can be load
8821 // using a single extract together, load it and store it.
8822 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
8823 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8824 DAG.getIntPtrConstant(Elt1 / 2));
8825 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8826 DAG.getIntPtrConstant(i));
8830 // If Elt1 is defined, extract it from the appropriate source. If the
8831 // source byte is not also odd, shift the extracted word left 8 bits
8832 // otherwise clear the bottom 8 bits if we need to do an or.
8834 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8835 DAG.getIntPtrConstant(Elt1 / 2));
8836 if ((Elt1 & 1) == 0)
8837 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
8839 TLI.getShiftAmountTy(InsElt.getValueType())));
8841 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
8842 DAG.getConstant(0xFF00, MVT::i16));
8844 // If Elt0 is defined, extract it from the appropriate source. If the
8845 // source byte is not also even, shift the extracted word right 8 bits. If
8846 // Elt1 was also defined, OR the extracted values together before
8847 // inserting them in the result.
8849 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
8850 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
8851 if ((Elt0 & 1) != 0)
8852 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8854 TLI.getShiftAmountTy(InsElt0.getValueType())));
8856 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
8857 DAG.getConstant(0x00FF, MVT::i16));
8858 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
8861 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8862 DAG.getIntPtrConstant(i));
8864 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8867 // v32i8 shuffles - Translate to VPSHUFB if possible.
8869 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
8870 const X86Subtarget *Subtarget,
8871 SelectionDAG &DAG) {
8872 MVT VT = SVOp->getSimpleValueType(0);
8873 SDValue V1 = SVOp->getOperand(0);
8874 SDValue V2 = SVOp->getOperand(1);
8876 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8878 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8879 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
8880 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8882 // VPSHUFB may be generated if
8883 // (1) one of input vector is undefined or zeroinitializer.
8884 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
8885 // And (2) the mask indexes don't cross the 128-bit lane.
8886 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
8887 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
8890 if (V1IsAllZero && !V2IsAllZero) {
8891 CommuteVectorShuffleMask(MaskVals, 32);
8894 return getPSHUFB(MaskVals, V1, dl, DAG);
8897 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8898 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8899 /// done when every pair / quad of shuffle mask elements point to elements in
8900 /// the right sequence. e.g.
8901 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
8903 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
8904 SelectionDAG &DAG) {
8905 MVT VT = SVOp->getSimpleValueType(0);
8907 unsigned NumElems = VT.getVectorNumElements();
8910 switch (VT.SimpleTy) {
8911 default: llvm_unreachable("Unexpected!");
8914 return SDValue(SVOp, 0);
8915 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
8916 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8917 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8918 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8919 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8920 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
8923 SmallVector<int, 8> MaskVec;
8924 for (unsigned i = 0; i != NumElems; i += Scale) {
8926 for (unsigned j = 0; j != Scale; ++j) {
8927 int EltIdx = SVOp->getMaskElt(i+j);
8931 StartIdx = (EltIdx / Scale);
8932 if (EltIdx != (int)(StartIdx*Scale + j))
8935 MaskVec.push_back(StartIdx);
8938 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
8939 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8940 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8943 /// getVZextMovL - Return a zero-extending vector move low node.
8945 static SDValue getVZextMovL(MVT VT, MVT OpVT,
8946 SDValue SrcOp, SelectionDAG &DAG,
8947 const X86Subtarget *Subtarget, SDLoc dl) {
8948 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
8949 LoadSDNode *LD = nullptr;
8950 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
8951 LD = dyn_cast<LoadSDNode>(SrcOp);
8953 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
8955 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
8956 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
8957 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8958 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
8959 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
8961 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8962 return DAG.getNode(ISD::BITCAST, dl, VT,
8963 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8964 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8972 return DAG.getNode(ISD::BITCAST, dl, VT,
8973 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8974 DAG.getNode(ISD::BITCAST, dl,
8978 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
8979 /// which could not be matched by any known target speficic shuffle
8981 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8983 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
8984 if (NewOp.getNode())
8987 MVT VT = SVOp->getSimpleValueType(0);
8989 unsigned NumElems = VT.getVectorNumElements();
8990 unsigned NumLaneElems = NumElems / 2;
8993 MVT EltVT = VT.getVectorElementType();
8994 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
8997 SmallVector<int, 16> Mask;
8998 for (unsigned l = 0; l < 2; ++l) {
8999 // Build a shuffle mask for the output, discovering on the fly which
9000 // input vectors to use as shuffle operands (recorded in InputUsed).
9001 // If building a suitable shuffle vector proves too hard, then bail
9002 // out with UseBuildVector set.
9003 bool UseBuildVector = false;
9004 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
9005 unsigned LaneStart = l * NumLaneElems;
9006 for (unsigned i = 0; i != NumLaneElems; ++i) {
9007 // The mask element. This indexes into the input.
9008 int Idx = SVOp->getMaskElt(i+LaneStart);
9010 // the mask element does not index into any input vector.
9015 // The input vector this mask element indexes into.
9016 int Input = Idx / NumLaneElems;
9018 // Turn the index into an offset from the start of the input vector.
9019 Idx -= Input * NumLaneElems;
9021 // Find or create a shuffle vector operand to hold this input.
9023 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
9024 if (InputUsed[OpNo] == Input)
9025 // This input vector is already an operand.
9027 if (InputUsed[OpNo] < 0) {
9028 // Create a new operand for this input vector.
9029 InputUsed[OpNo] = Input;
9034 if (OpNo >= array_lengthof(InputUsed)) {
9035 // More than two input vectors used! Give up on trying to create a
9036 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
9037 UseBuildVector = true;
9041 // Add the mask index for the new shuffle vector.
9042 Mask.push_back(Idx + OpNo * NumLaneElems);
9045 if (UseBuildVector) {
9046 SmallVector<SDValue, 16> SVOps;
9047 for (unsigned i = 0; i != NumLaneElems; ++i) {
9048 // The mask element. This indexes into the input.
9049 int Idx = SVOp->getMaskElt(i+LaneStart);
9051 SVOps.push_back(DAG.getUNDEF(EltVT));
9055 // The input vector this mask element indexes into.
9056 int Input = Idx / NumElems;
9058 // Turn the index into an offset from the start of the input vector.
9059 Idx -= Input * NumElems;
9061 // Extract the vector element by hand.
9062 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
9063 SVOp->getOperand(Input),
9064 DAG.getIntPtrConstant(Idx)));
9067 // Construct the output using a BUILD_VECTOR.
9068 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
9069 } else if (InputUsed[0] < 0) {
9070 // No input vectors were used! The result is undefined.
9071 Output[l] = DAG.getUNDEF(NVT);
9073 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
9074 (InputUsed[0] % 2) * NumLaneElems,
9076 // If only one input was used, use an undefined vector for the other.
9077 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
9078 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
9079 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
9080 // At least one input vector was used. Create a new shuffle vector.
9081 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9087 // Concatenate the result back
9088 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
9091 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9092 /// 4 elements, and match them with several different shuffle types.
9094 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9095 SDValue V1 = SVOp->getOperand(0);
9096 SDValue V2 = SVOp->getOperand(1);
9098 MVT VT = SVOp->getSimpleValueType(0);
9100 assert(VT.is128BitVector() && "Unsupported vector size");
9102 std::pair<int, int> Locs[4];
9103 int Mask1[] = { -1, -1, -1, -1 };
9104 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9108 for (unsigned i = 0; i != 4; ++i) {
9109 int Idx = PermMask[i];
9111 Locs[i] = std::make_pair(-1, -1);
9113 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9115 Locs[i] = std::make_pair(0, NumLo);
9119 Locs[i] = std::make_pair(1, NumHi);
9121 Mask1[2+NumHi] = Idx;
9127 if (NumLo <= 2 && NumHi <= 2) {
9128 // If no more than two elements come from either vector. This can be
9129 // implemented with two shuffles. First shuffle gather the elements.
9130 // The second shuffle, which takes the first shuffle as both of its
9131 // vector operands, put the elements into the right order.
9132 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9134 int Mask2[] = { -1, -1, -1, -1 };
9136 for (unsigned i = 0; i != 4; ++i)
9137 if (Locs[i].first != -1) {
9138 unsigned Idx = (i < 2) ? 0 : 4;
9139 Idx += Locs[i].first * 2 + Locs[i].second;
9143 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9146 if (NumLo == 3 || NumHi == 3) {
9147 // Otherwise, we must have three elements from one vector, call it X, and
9148 // one element from the other, call it Y. First, use a shufps to build an
9149 // intermediate vector with the one element from Y and the element from X
9150 // that will be in the same half in the final destination (the indexes don't
9151 // matter). Then, use a shufps to build the final vector, taking the half
9152 // containing the element from Y from the intermediate, and the other half
9155 // Normalize it so the 3 elements come from V1.
9156 CommuteVectorShuffleMask(PermMask, 4);
9160 // Find the element from V2.
9162 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9163 int Val = PermMask[HiIndex];
9170 Mask1[0] = PermMask[HiIndex];
9172 Mask1[2] = PermMask[HiIndex^1];
9174 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9177 Mask1[0] = PermMask[0];
9178 Mask1[1] = PermMask[1];
9179 Mask1[2] = HiIndex & 1 ? 6 : 4;
9180 Mask1[3] = HiIndex & 1 ? 4 : 6;
9181 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9184 Mask1[0] = HiIndex & 1 ? 2 : 0;
9185 Mask1[1] = HiIndex & 1 ? 0 : 2;
9186 Mask1[2] = PermMask[2];
9187 Mask1[3] = PermMask[3];
9192 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9195 // Break it into (shuffle shuffle_hi, shuffle_lo).
9196 int LoMask[] = { -1, -1, -1, -1 };
9197 int HiMask[] = { -1, -1, -1, -1 };
9199 int *MaskPtr = LoMask;
9200 unsigned MaskIdx = 0;
9203 for (unsigned i = 0; i != 4; ++i) {
9210 int Idx = PermMask[i];
9212 Locs[i] = std::make_pair(-1, -1);
9213 } else if (Idx < 4) {
9214 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9215 MaskPtr[LoIdx] = Idx;
9218 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9219 MaskPtr[HiIdx] = Idx;
9224 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9225 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9226 int MaskOps[] = { -1, -1, -1, -1 };
9227 for (unsigned i = 0; i != 4; ++i)
9228 if (Locs[i].first != -1)
9229 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9230 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9233 static bool MayFoldVectorLoad(SDValue V) {
9234 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9235 V = V.getOperand(0);
9237 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9238 V = V.getOperand(0);
9239 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9240 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9241 // BUILD_VECTOR (load), undef
9242 V = V.getOperand(0);
9244 return MayFoldLoad(V);
9248 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9249 MVT VT = Op.getSimpleValueType();
9251 // Canonizalize to v2f64.
9252 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9253 return DAG.getNode(ISD::BITCAST, dl, VT,
9254 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9259 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9261 SDValue V1 = Op.getOperand(0);
9262 SDValue V2 = Op.getOperand(1);
9263 MVT VT = Op.getSimpleValueType();
9265 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9267 if (HasSSE2 && VT == MVT::v2f64)
9268 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9270 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9271 return DAG.getNode(ISD::BITCAST, dl, VT,
9272 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9273 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9274 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9278 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9279 SDValue V1 = Op.getOperand(0);
9280 SDValue V2 = Op.getOperand(1);
9281 MVT VT = Op.getSimpleValueType();
9283 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9284 "unsupported shuffle type");
9286 if (V2.getOpcode() == ISD::UNDEF)
9290 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9294 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9295 SDValue V1 = Op.getOperand(0);
9296 SDValue V2 = Op.getOperand(1);
9297 MVT VT = Op.getSimpleValueType();
9298 unsigned NumElems = VT.getVectorNumElements();
9300 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9301 // operand of these instructions is only memory, so check if there's a
9302 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9304 bool CanFoldLoad = false;
9306 // Trivial case, when V2 comes from a load.
9307 if (MayFoldVectorLoad(V2))
9310 // When V1 is a load, it can be folded later into a store in isel, example:
9311 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9313 // (MOVLPSmr addr:$src1, VR128:$src2)
9314 // So, recognize this potential and also use MOVLPS or MOVLPD
9315 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9318 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9320 if (HasSSE2 && NumElems == 2)
9321 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9324 // If we don't care about the second element, proceed to use movss.
9325 if (SVOp->getMaskElt(1) != -1)
9326 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9329 // movl and movlp will both match v2i64, but v2i64 is never matched by
9330 // movl earlier because we make it strict to avoid messing with the movlp load
9331 // folding logic (see the code above getMOVLP call). Match it here then,
9332 // this is horrible, but will stay like this until we move all shuffle
9333 // matching to x86 specific nodes. Note that for the 1st condition all
9334 // types are matched with movsd.
9336 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9337 // as to remove this logic from here, as much as possible
9338 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9339 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9340 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9343 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9345 // Invert the operand order and use SHUFPS to match it.
9346 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9347 getShuffleSHUFImmediate(SVOp), DAG);
9350 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9351 SelectionDAG &DAG) {
9353 MVT VT = Load->getSimpleValueType(0);
9354 MVT EVT = VT.getVectorElementType();
9355 SDValue Addr = Load->getOperand(1);
9356 SDValue NewAddr = DAG.getNode(
9357 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9358 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9361 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9362 DAG.getMachineFunction().getMachineMemOperand(
9363 Load->getMemOperand(), 0, EVT.getStoreSize()));
9367 // It is only safe to call this function if isINSERTPSMask is true for
9368 // this shufflevector mask.
9369 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9370 SelectionDAG &DAG) {
9371 // Generate an insertps instruction when inserting an f32 from memory onto a
9372 // v4f32 or when copying a member from one v4f32 to another.
9373 // We also use it for transferring i32 from one register to another,
9374 // since it simply copies the same bits.
9375 // If we're transferring an i32 from memory to a specific element in a
9376 // register, we output a generic DAG that will match the PINSRD
9378 MVT VT = SVOp->getSimpleValueType(0);
9379 MVT EVT = VT.getVectorElementType();
9380 SDValue V1 = SVOp->getOperand(0);
9381 SDValue V2 = SVOp->getOperand(1);
9382 auto Mask = SVOp->getMask();
9383 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9384 "unsupported vector type for insertps/pinsrd");
9386 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9387 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9388 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9396 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9399 // If we have 1 element from each vector, we have to check if we're
9400 // changing V1's element's place. If so, we're done. Otherwise, we
9401 // should assume we're changing V2's element's place and behave
9403 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9404 assert(DestIndex <= INT32_MAX && "truncated destination index");
9405 if (FromV1 == FromV2 &&
9406 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
9410 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9413 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9414 "More than one element from V1 and from V2, or no elements from one "
9415 "of the vectors. This case should not have returned true from "
9420 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9423 // Get an index into the source vector in the range [0,4) (the mask is
9424 // in the range [0,8) because it can address V1 and V2)
9425 unsigned SrcIndex = Mask[DestIndex] % 4;
9426 if (MayFoldLoad(From)) {
9427 // Trivial case, when From comes from a load and is only used by the
9428 // shuffle. Make it use insertps from the vector that we need from that
9431 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9432 if (!NewLoad.getNode())
9435 if (EVT == MVT::f32) {
9436 // Create this as a scalar to vector to match the instruction pattern.
9437 SDValue LoadScalarToVector =
9438 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9439 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9440 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9442 } else { // EVT == MVT::i32
9443 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9444 // instruction, to match the PINSRD instruction, which loads an i32 to a
9445 // certain vector element.
9446 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9447 DAG.getConstant(DestIndex, MVT::i32));
9451 // Vector-element-to-vector
9452 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9453 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9456 // Reduce a vector shuffle to zext.
9457 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9458 SelectionDAG &DAG) {
9459 // PMOVZX is only available from SSE41.
9460 if (!Subtarget->hasSSE41())
9463 MVT VT = Op.getSimpleValueType();
9465 // Only AVX2 support 256-bit vector integer extending.
9466 if (!Subtarget->hasInt256() && VT.is256BitVector())
9469 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9471 SDValue V1 = Op.getOperand(0);
9472 SDValue V2 = Op.getOperand(1);
9473 unsigned NumElems = VT.getVectorNumElements();
9475 // Extending is an unary operation and the element type of the source vector
9476 // won't be equal to or larger than i64.
9477 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9478 VT.getVectorElementType() == MVT::i64)
9481 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9482 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9483 while ((1U << Shift) < NumElems) {
9484 if (SVOp->getMaskElt(1U << Shift) == 1)
9487 // The maximal ratio is 8, i.e. from i8 to i64.
9492 // Check the shuffle mask.
9493 unsigned Mask = (1U << Shift) - 1;
9494 for (unsigned i = 0; i != NumElems; ++i) {
9495 int EltIdx = SVOp->getMaskElt(i);
9496 if ((i & Mask) != 0 && EltIdx != -1)
9498 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9502 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9503 MVT NeVT = MVT::getIntegerVT(NBits);
9504 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9506 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9509 // Simplify the operand as it's prepared to be fed into shuffle.
9510 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9511 if (V1.getOpcode() == ISD::BITCAST &&
9512 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9513 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9514 V1.getOperand(0).getOperand(0)
9515 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9516 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9517 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9518 ConstantSDNode *CIdx =
9519 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9520 // If it's foldable, i.e. normal load with single use, we will let code
9521 // selection to fold it. Otherwise, we will short the conversion sequence.
9522 if (CIdx && CIdx->getZExtValue() == 0 &&
9523 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9524 MVT FullVT = V.getSimpleValueType();
9525 MVT V1VT = V1.getSimpleValueType();
9526 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9527 // The "ext_vec_elt" node is wider than the result node.
9528 // In this case we should extract subvector from V.
9529 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9530 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9531 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9532 FullVT.getVectorNumElements()/Ratio);
9533 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9534 DAG.getIntPtrConstant(0));
9536 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9540 return DAG.getNode(ISD::BITCAST, DL, VT,
9541 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9544 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9545 SelectionDAG &DAG) {
9546 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9547 MVT VT = Op.getSimpleValueType();
9549 SDValue V1 = Op.getOperand(0);
9550 SDValue V2 = Op.getOperand(1);
9552 if (isZeroShuffle(SVOp))
9553 return getZeroVector(VT, Subtarget, DAG, dl);
9555 // Handle splat operations
9556 if (SVOp->isSplat()) {
9557 // Use vbroadcast whenever the splat comes from a foldable load
9558 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9559 if (Broadcast.getNode())
9563 // Check integer expanding shuffles.
9564 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9565 if (NewOp.getNode())
9568 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9570 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9572 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9573 if (NewOp.getNode())
9574 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9575 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9576 // FIXME: Figure out a cleaner way to do this.
9577 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9578 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9579 if (NewOp.getNode()) {
9580 MVT NewVT = NewOp.getSimpleValueType();
9581 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9582 NewVT, true, false))
9583 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9586 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9587 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9588 if (NewOp.getNode()) {
9589 MVT NewVT = NewOp.getSimpleValueType();
9590 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9591 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9600 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9601 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9602 SDValue V1 = Op.getOperand(0);
9603 SDValue V2 = Op.getOperand(1);
9604 MVT VT = Op.getSimpleValueType();
9606 unsigned NumElems = VT.getVectorNumElements();
9607 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9608 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9609 bool V1IsSplat = false;
9610 bool V2IsSplat = false;
9611 bool HasSSE2 = Subtarget->hasSSE2();
9612 bool HasFp256 = Subtarget->hasFp256();
9613 bool HasInt256 = Subtarget->hasInt256();
9614 MachineFunction &MF = DAG.getMachineFunction();
9615 bool OptForSize = MF.getFunction()->getAttributes().
9616 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9618 // Check if we should use the experimental vector shuffle lowering. If so,
9619 // delegate completely to that code path.
9620 if (ExperimentalVectorShuffleLowering)
9621 return lowerVectorShuffle(Op, Subtarget, DAG);
9623 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9625 if (V1IsUndef && V2IsUndef)
9626 return DAG.getUNDEF(VT);
9628 // When we create a shuffle node we put the UNDEF node to second operand,
9629 // but in some cases the first operand may be transformed to UNDEF.
9630 // In this case we should just commute the node.
9632 return DAG.getCommutedVectorShuffle(*SVOp);
9634 // Vector shuffle lowering takes 3 steps:
9636 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9637 // narrowing and commutation of operands should be handled.
9638 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9640 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9641 // so the shuffle can be broken into other shuffles and the legalizer can
9642 // try the lowering again.
9644 // The general idea is that no vector_shuffle operation should be left to
9645 // be matched during isel, all of them must be converted to a target specific
9648 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9649 // narrowing and commutation of operands should be handled. The actual code
9650 // doesn't include all of those, work in progress...
9651 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9652 if (NewOp.getNode())
9655 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9657 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9658 // unpckh_undef). Only use pshufd if speed is more important than size.
9659 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9660 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9661 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9662 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9664 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9665 V2IsUndef && MayFoldVectorLoad(V1))
9666 return getMOVDDup(Op, dl, V1, DAG);
9668 if (isMOVHLPS_v_undef_Mask(M, VT))
9669 return getMOVHighToLow(Op, dl, DAG);
9671 // Use to match splats
9672 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9673 (VT == MVT::v2f64 || VT == MVT::v2i64))
9674 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9676 if (isPSHUFDMask(M, VT)) {
9677 // The actual implementation will match the mask in the if above and then
9678 // during isel it can match several different instructions, not only pshufd
9679 // as its name says, sad but true, emulate the behavior for now...
9680 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9681 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9683 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9685 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9686 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9688 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9689 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9692 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9696 if (isPALIGNRMask(M, VT, Subtarget))
9697 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9698 getShufflePALIGNRImmediate(SVOp),
9701 if (isVALIGNMask(M, VT, Subtarget))
9702 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
9703 getShuffleVALIGNImmediate(SVOp),
9706 // Check if this can be converted into a logical shift.
9707 bool isLeft = false;
9710 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9711 if (isShift && ShVal.hasOneUse()) {
9712 // If the shifted value has multiple uses, it may be cheaper to use
9713 // v_set0 + movlhps or movhlps, etc.
9714 MVT EltVT = VT.getVectorElementType();
9715 ShAmt *= EltVT.getSizeInBits();
9716 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9719 if (isMOVLMask(M, VT)) {
9720 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9721 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9722 if (!isMOVLPMask(M, VT)) {
9723 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9724 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9726 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9727 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9731 // FIXME: fold these into legal mask.
9732 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9733 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9735 if (isMOVHLPSMask(M, VT))
9736 return getMOVHighToLow(Op, dl, DAG);
9738 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9739 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9741 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9742 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9744 if (isMOVLPMask(M, VT))
9745 return getMOVLP(Op, dl, DAG, HasSSE2);
9747 if (ShouldXformToMOVHLPS(M, VT) ||
9748 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9749 return DAG.getCommutedVectorShuffle(*SVOp);
9752 // No better options. Use a vshldq / vsrldq.
9753 MVT EltVT = VT.getVectorElementType();
9754 ShAmt *= EltVT.getSizeInBits();
9755 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9758 bool Commuted = false;
9759 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9760 // 1,1,1,1 -> v8i16 though.
9761 BitVector UndefElements;
9762 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9763 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9765 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9766 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9769 // Canonicalize the splat or undef, if present, to be on the RHS.
9770 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9771 CommuteVectorShuffleMask(M, NumElems);
9773 std::swap(V1IsSplat, V2IsSplat);
9777 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9778 // Shuffling low element of v1 into undef, just return v1.
9781 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9782 // the instruction selector will not match, so get a canonical MOVL with
9783 // swapped operands to undo the commute.
9784 return getMOVL(DAG, dl, VT, V2, V1);
9787 if (isUNPCKLMask(M, VT, HasInt256))
9788 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9790 if (isUNPCKHMask(M, VT, HasInt256))
9791 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9794 // Normalize mask so all entries that point to V2 points to its first
9795 // element then try to match unpck{h|l} again. If match, return a
9796 // new vector_shuffle with the corrected mask.p
9797 SmallVector<int, 8> NewMask(M.begin(), M.end());
9798 NormalizeMask(NewMask, NumElems);
9799 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9800 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9801 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9802 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9806 // Commute is back and try unpck* again.
9807 // FIXME: this seems wrong.
9808 CommuteVectorShuffleMask(M, NumElems);
9810 std::swap(V1IsSplat, V2IsSplat);
9812 if (isUNPCKLMask(M, VT, HasInt256))
9813 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9815 if (isUNPCKHMask(M, VT, HasInt256))
9816 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9819 // Normalize the node to match x86 shuffle ops if needed
9820 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9821 return DAG.getCommutedVectorShuffle(*SVOp);
9823 // The checks below are all present in isShuffleMaskLegal, but they are
9824 // inlined here right now to enable us to directly emit target specific
9825 // nodes, and remove one by one until they don't return Op anymore.
9827 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9828 SVOp->getSplatIndex() == 0 && V2IsUndef) {
9829 if (VT == MVT::v2f64 || VT == MVT::v2i64)
9830 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9833 if (isPSHUFHWMask(M, VT, HasInt256))
9834 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9835 getShufflePSHUFHWImmediate(SVOp),
9838 if (isPSHUFLWMask(M, VT, HasInt256))
9839 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9840 getShufflePSHUFLWImmediate(SVOp),
9844 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9846 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9848 if (isSHUFPMask(M, VT))
9849 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9850 getShuffleSHUFImmediate(SVOp), DAG);
9852 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9853 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9854 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9855 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9857 //===--------------------------------------------------------------------===//
9858 // Generate target specific nodes for 128 or 256-bit shuffles only
9859 // supported in the AVX instruction set.
9862 // Handle VMOVDDUPY permutations
9863 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9864 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9866 // Handle VPERMILPS/D* permutations
9867 if (isVPERMILPMask(M, VT)) {
9868 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9869 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9870 getShuffleSHUFImmediate(SVOp), DAG);
9871 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9872 getShuffleSHUFImmediate(SVOp), DAG);
9876 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9877 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9878 Idx*(NumElems/2), DAG, dl);
9880 // Handle VPERM2F128/VPERM2I128 permutations
9881 if (isVPERM2X128Mask(M, VT, HasFp256))
9882 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9883 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9885 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9886 return getINSERTPS(SVOp, dl, DAG);
9889 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9890 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9892 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9893 VT.is512BitVector()) {
9894 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9895 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9896 SmallVector<SDValue, 16> permclMask;
9897 for (unsigned i = 0; i != NumElems; ++i) {
9898 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9901 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9903 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9904 return DAG.getNode(X86ISD::VPERMV, dl, VT,
9905 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9906 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9907 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9910 //===--------------------------------------------------------------------===//
9911 // Since no target specific shuffle was selected for this generic one,
9912 // lower it into other known shuffles. FIXME: this isn't true yet, but
9913 // this is the plan.
9916 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9917 if (VT == MVT::v8i16) {
9918 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9919 if (NewOp.getNode())
9923 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9924 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9925 if (NewOp.getNode())
9929 if (VT == MVT::v16i8) {
9930 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9931 if (NewOp.getNode())
9935 if (VT == MVT::v32i8) {
9936 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9937 if (NewOp.getNode())
9941 // Handle all 128-bit wide vectors with 4 elements, and match them with
9942 // several different shuffle types.
9943 if (NumElems == 4 && VT.is128BitVector())
9944 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9946 // Handle general 256-bit shuffles
9947 if (VT.is256BitVector())
9948 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9953 // This function assumes its argument is a BUILD_VECTOR of constants or
9954 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
9956 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
9957 unsigned &MaskValue) {
9959 unsigned NumElems = BuildVector->getNumOperands();
9960 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9961 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9962 unsigned NumElemsInLane = NumElems / NumLanes;
9964 // Blend for v16i16 should be symetric for the both lanes.
9965 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9966 SDValue EltCond = BuildVector->getOperand(i);
9967 SDValue SndLaneEltCond =
9968 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
9970 int Lane1Cond = -1, Lane2Cond = -1;
9971 if (isa<ConstantSDNode>(EltCond))
9972 Lane1Cond = !isZero(EltCond);
9973 if (isa<ConstantSDNode>(SndLaneEltCond))
9974 Lane2Cond = !isZero(SndLaneEltCond);
9976 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
9977 // Lane1Cond != 0, means we want the first argument.
9978 // Lane1Cond == 0, means we want the second argument.
9979 // The encoding of this argument is 0 for the first argument, 1
9980 // for the second. Therefore, invert the condition.
9981 MaskValue |= !Lane1Cond << i;
9982 else if (Lane1Cond < 0)
9983 MaskValue |= !Lane2Cond << i;
9990 // Try to lower a vselect node into a simple blend instruction.
9991 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
9992 SelectionDAG &DAG) {
9993 SDValue Cond = Op.getOperand(0);
9994 SDValue LHS = Op.getOperand(1);
9995 SDValue RHS = Op.getOperand(2);
9997 MVT VT = Op.getSimpleValueType();
9998 MVT EltVT = VT.getVectorElementType();
9999 unsigned NumElems = VT.getVectorNumElements();
10001 // There is no blend with immediate in AVX-512.
10002 if (VT.is512BitVector())
10005 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
10007 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
10010 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10013 // Check the mask for BLEND and build the value.
10014 unsigned MaskValue = 0;
10015 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
10018 // Convert i32 vectors to floating point if it is not AVX2.
10019 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10021 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10022 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10024 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
10025 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
10028 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
10029 DAG.getConstant(MaskValue, MVT::i32));
10030 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10033 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10034 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
10035 if (BlendOp.getNode())
10038 // Some types for vselect were previously set to Expand, not Legal or
10039 // Custom. Return an empty SDValue so we fall-through to Expand, after
10040 // the Custom lowering phase.
10041 MVT VT = Op.getSimpleValueType();
10042 switch (VT.SimpleTy) {
10050 // We couldn't create a "Blend with immediate" node.
10051 // This node should still be legal, but we'll have to emit a blendv*
10056 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10057 MVT VT = Op.getSimpleValueType();
10060 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10063 if (VT.getSizeInBits() == 8) {
10064 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10065 Op.getOperand(0), Op.getOperand(1));
10066 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10067 DAG.getValueType(VT));
10068 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10071 if (VT.getSizeInBits() == 16) {
10072 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10073 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10075 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10076 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10077 DAG.getNode(ISD::BITCAST, dl,
10080 Op.getOperand(1)));
10081 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10082 Op.getOperand(0), Op.getOperand(1));
10083 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10084 DAG.getValueType(VT));
10085 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10088 if (VT == MVT::f32) {
10089 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10090 // the result back to FR32 register. It's only worth matching if the
10091 // result has a single use which is a store or a bitcast to i32. And in
10092 // the case of a store, it's not worth it if the index is a constant 0,
10093 // because a MOVSSmr can be used instead, which is smaller and faster.
10094 if (!Op.hasOneUse())
10096 SDNode *User = *Op.getNode()->use_begin();
10097 if ((User->getOpcode() != ISD::STORE ||
10098 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10099 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10100 (User->getOpcode() != ISD::BITCAST ||
10101 User->getValueType(0) != MVT::i32))
10103 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10104 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10107 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10110 if (VT == MVT::i32 || VT == MVT::i64) {
10111 // ExtractPS/pextrq works with constant index.
10112 if (isa<ConstantSDNode>(Op.getOperand(1)))
10118 /// Extract one bit from mask vector, like v16i1 or v8i1.
10119 /// AVX-512 feature.
10121 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10122 SDValue Vec = Op.getOperand(0);
10124 MVT VecVT = Vec.getSimpleValueType();
10125 SDValue Idx = Op.getOperand(1);
10126 MVT EltVT = Op.getSimpleValueType();
10128 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10130 // variable index can't be handled in mask registers,
10131 // extend vector to VR512
10132 if (!isa<ConstantSDNode>(Idx)) {
10133 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10134 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10135 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10136 ExtVT.getVectorElementType(), Ext, Idx);
10137 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10140 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10141 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10142 unsigned MaxSift = rc->getSize()*8 - 1;
10143 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10144 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10145 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10146 DAG.getConstant(MaxSift, MVT::i8));
10147 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10148 DAG.getIntPtrConstant(0));
10152 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10153 SelectionDAG &DAG) const {
10155 SDValue Vec = Op.getOperand(0);
10156 MVT VecVT = Vec.getSimpleValueType();
10157 SDValue Idx = Op.getOperand(1);
10159 if (Op.getSimpleValueType() == MVT::i1)
10160 return ExtractBitFromMaskVector(Op, DAG);
10162 if (!isa<ConstantSDNode>(Idx)) {
10163 if (VecVT.is512BitVector() ||
10164 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10165 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10168 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10169 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10170 MaskEltVT.getSizeInBits());
10172 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10173 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10174 getZeroVector(MaskVT, Subtarget, DAG, dl),
10175 Idx, DAG.getConstant(0, getPointerTy()));
10176 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10177 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10178 Perm, DAG.getConstant(0, getPointerTy()));
10183 // If this is a 256-bit vector result, first extract the 128-bit vector and
10184 // then extract the element from the 128-bit vector.
10185 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10187 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10188 // Get the 128-bit vector.
10189 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10190 MVT EltVT = VecVT.getVectorElementType();
10192 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10194 //if (IdxVal >= NumElems/2)
10195 // IdxVal -= NumElems/2;
10196 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10197 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10198 DAG.getConstant(IdxVal, MVT::i32));
10201 assert(VecVT.is128BitVector() && "Unexpected vector length");
10203 if (Subtarget->hasSSE41()) {
10204 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10209 MVT VT = Op.getSimpleValueType();
10210 // TODO: handle v16i8.
10211 if (VT.getSizeInBits() == 16) {
10212 SDValue Vec = Op.getOperand(0);
10213 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10215 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10216 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10217 DAG.getNode(ISD::BITCAST, dl,
10219 Op.getOperand(1)));
10220 // Transform it so it match pextrw which produces a 32-bit result.
10221 MVT EltVT = MVT::i32;
10222 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10223 Op.getOperand(0), Op.getOperand(1));
10224 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10225 DAG.getValueType(VT));
10226 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10229 if (VT.getSizeInBits() == 32) {
10230 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10234 // SHUFPS the element to the lowest double word, then movss.
10235 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10236 MVT VVT = Op.getOperand(0).getSimpleValueType();
10237 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10238 DAG.getUNDEF(VVT), Mask);
10239 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10240 DAG.getIntPtrConstant(0));
10243 if (VT.getSizeInBits() == 64) {
10244 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10245 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10246 // to match extract_elt for f64.
10247 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10251 // UNPCKHPD the element to the lowest double word, then movsd.
10252 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10253 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10254 int Mask[2] = { 1, -1 };
10255 MVT VVT = Op.getOperand(0).getSimpleValueType();
10256 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10257 DAG.getUNDEF(VVT), Mask);
10258 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10259 DAG.getIntPtrConstant(0));
10265 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10266 MVT VT = Op.getSimpleValueType();
10267 MVT EltVT = VT.getVectorElementType();
10270 SDValue N0 = Op.getOperand(0);
10271 SDValue N1 = Op.getOperand(1);
10272 SDValue N2 = Op.getOperand(2);
10274 if (!VT.is128BitVector())
10277 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
10278 isa<ConstantSDNode>(N2)) {
10280 if (VT == MVT::v8i16)
10281 Opc = X86ISD::PINSRW;
10282 else if (VT == MVT::v16i8)
10283 Opc = X86ISD::PINSRB;
10285 Opc = X86ISD::PINSRB;
10287 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10289 if (N1.getValueType() != MVT::i32)
10290 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10291 if (N2.getValueType() != MVT::i32)
10292 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10293 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10296 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
10297 // Bits [7:6] of the constant are the source select. This will always be
10298 // zero here. The DAG Combiner may combine an extract_elt index into these
10299 // bits. For example (insert (extract, 3), 2) could be matched by putting
10300 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10301 // Bits [5:4] of the constant are the destination select. This is the
10302 // value of the incoming immediate.
10303 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10304 // combine either bitwise AND or insert of float 0.0 to set these bits.
10305 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
10306 // Create this as a scalar to vector..
10307 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10308 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10311 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
10312 // PINSR* works with constant index.
10318 /// Insert one bit to mask vector, like v16i1 or v8i1.
10319 /// AVX-512 feature.
10321 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10323 SDValue Vec = Op.getOperand(0);
10324 SDValue Elt = Op.getOperand(1);
10325 SDValue Idx = Op.getOperand(2);
10326 MVT VecVT = Vec.getSimpleValueType();
10328 if (!isa<ConstantSDNode>(Idx)) {
10329 // Non constant index. Extend source and destination,
10330 // insert element and then truncate the result.
10331 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10332 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10333 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10334 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10335 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10336 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10339 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10340 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10341 if (Vec.getOpcode() == ISD::UNDEF)
10342 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10343 DAG.getConstant(IdxVal, MVT::i8));
10344 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10345 unsigned MaxSift = rc->getSize()*8 - 1;
10346 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10347 DAG.getConstant(MaxSift, MVT::i8));
10348 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10349 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10350 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10353 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
10354 MVT VT = Op.getSimpleValueType();
10355 MVT EltVT = VT.getVectorElementType();
10357 if (EltVT == MVT::i1)
10358 return InsertBitToMaskVector(Op, DAG);
10361 SDValue N0 = Op.getOperand(0);
10362 SDValue N1 = Op.getOperand(1);
10363 SDValue N2 = Op.getOperand(2);
10365 // If this is a 256-bit vector result, first extract the 128-bit vector,
10366 // insert the element into the extracted half and then place it back.
10367 if (VT.is256BitVector() || VT.is512BitVector()) {
10368 if (!isa<ConstantSDNode>(N2))
10371 // Get the desired 128-bit vector half.
10372 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10373 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10375 // Insert the element into the desired half.
10376 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10377 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10379 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10380 DAG.getConstant(IdxIn128, MVT::i32));
10382 // Insert the changed part back to the 256-bit vector
10383 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10386 if (Subtarget->hasSSE41())
10387 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10389 if (EltVT == MVT::i8)
10392 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10393 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10394 // as its second argument.
10395 if (N1.getValueType() != MVT::i32)
10396 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10397 if (N2.getValueType() != MVT::i32)
10398 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10399 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10404 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10406 MVT OpVT = Op.getSimpleValueType();
10408 // If this is a 256-bit vector result, first insert into a 128-bit
10409 // vector and then insert into the 256-bit vector.
10410 if (!OpVT.is128BitVector()) {
10411 // Insert into a 128-bit vector.
10412 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10413 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10414 OpVT.getVectorNumElements() / SizeFactor);
10416 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10418 // Insert the 128-bit vector.
10419 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10422 if (OpVT == MVT::v1i64 &&
10423 Op.getOperand(0).getValueType() == MVT::i64)
10424 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10426 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10427 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10428 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10429 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10432 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10433 // a simple subregister reference or explicit instructions to grab
10434 // upper bits of a vector.
10435 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10436 SelectionDAG &DAG) {
10438 SDValue In = Op.getOperand(0);
10439 SDValue Idx = Op.getOperand(1);
10440 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10441 MVT ResVT = Op.getSimpleValueType();
10442 MVT InVT = In.getSimpleValueType();
10444 if (Subtarget->hasFp256()) {
10445 if (ResVT.is128BitVector() &&
10446 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10447 isa<ConstantSDNode>(Idx)) {
10448 return Extract128BitVector(In, IdxVal, DAG, dl);
10450 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10451 isa<ConstantSDNode>(Idx)) {
10452 return Extract256BitVector(In, IdxVal, DAG, dl);
10458 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10459 // simple superregister reference or explicit instructions to insert
10460 // the upper bits of a vector.
10461 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10462 SelectionDAG &DAG) {
10463 if (Subtarget->hasFp256()) {
10464 SDLoc dl(Op.getNode());
10465 SDValue Vec = Op.getNode()->getOperand(0);
10466 SDValue SubVec = Op.getNode()->getOperand(1);
10467 SDValue Idx = Op.getNode()->getOperand(2);
10469 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10470 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10471 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10472 isa<ConstantSDNode>(Idx)) {
10473 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10474 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10477 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10478 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10479 isa<ConstantSDNode>(Idx)) {
10480 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10481 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10487 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10488 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10489 // one of the above mentioned nodes. It has to be wrapped because otherwise
10490 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10491 // be used to form addressing mode. These wrapped nodes will be selected
10494 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10495 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10497 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10498 // global base reg.
10499 unsigned char OpFlag = 0;
10500 unsigned WrapperKind = X86ISD::Wrapper;
10501 CodeModel::Model M = DAG.getTarget().getCodeModel();
10503 if (Subtarget->isPICStyleRIPRel() &&
10504 (M == CodeModel::Small || M == CodeModel::Kernel))
10505 WrapperKind = X86ISD::WrapperRIP;
10506 else if (Subtarget->isPICStyleGOT())
10507 OpFlag = X86II::MO_GOTOFF;
10508 else if (Subtarget->isPICStyleStubPIC())
10509 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10511 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10512 CP->getAlignment(),
10513 CP->getOffset(), OpFlag);
10515 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10516 // With PIC, the address is actually $g + Offset.
10518 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10519 DAG.getNode(X86ISD::GlobalBaseReg,
10520 SDLoc(), getPointerTy()),
10527 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10528 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10530 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10531 // global base reg.
10532 unsigned char OpFlag = 0;
10533 unsigned WrapperKind = X86ISD::Wrapper;
10534 CodeModel::Model M = DAG.getTarget().getCodeModel();
10536 if (Subtarget->isPICStyleRIPRel() &&
10537 (M == CodeModel::Small || M == CodeModel::Kernel))
10538 WrapperKind = X86ISD::WrapperRIP;
10539 else if (Subtarget->isPICStyleGOT())
10540 OpFlag = X86II::MO_GOTOFF;
10541 else if (Subtarget->isPICStyleStubPIC())
10542 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10544 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10547 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10549 // With PIC, the address is actually $g + Offset.
10551 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10552 DAG.getNode(X86ISD::GlobalBaseReg,
10553 SDLoc(), getPointerTy()),
10560 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10561 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10563 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10564 // global base reg.
10565 unsigned char OpFlag = 0;
10566 unsigned WrapperKind = X86ISD::Wrapper;
10567 CodeModel::Model M = DAG.getTarget().getCodeModel();
10569 if (Subtarget->isPICStyleRIPRel() &&
10570 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10571 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10572 OpFlag = X86II::MO_GOTPCREL;
10573 WrapperKind = X86ISD::WrapperRIP;
10574 } else if (Subtarget->isPICStyleGOT()) {
10575 OpFlag = X86II::MO_GOT;
10576 } else if (Subtarget->isPICStyleStubPIC()) {
10577 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10578 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10579 OpFlag = X86II::MO_DARWIN_NONLAZY;
10582 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10585 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10587 // With PIC, the address is actually $g + Offset.
10588 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10589 !Subtarget->is64Bit()) {
10590 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10591 DAG.getNode(X86ISD::GlobalBaseReg,
10592 SDLoc(), getPointerTy()),
10596 // For symbols that require a load from a stub to get the address, emit the
10598 if (isGlobalStubReference(OpFlag))
10599 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10600 MachinePointerInfo::getGOT(), false, false, false, 0);
10606 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10607 // Create the TargetBlockAddressAddress node.
10608 unsigned char OpFlags =
10609 Subtarget->ClassifyBlockAddressReference();
10610 CodeModel::Model M = DAG.getTarget().getCodeModel();
10611 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10612 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10614 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10617 if (Subtarget->isPICStyleRIPRel() &&
10618 (M == CodeModel::Small || M == CodeModel::Kernel))
10619 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10621 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10623 // With PIC, the address is actually $g + Offset.
10624 if (isGlobalRelativeToPICBase(OpFlags)) {
10625 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10626 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10634 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10635 int64_t Offset, SelectionDAG &DAG) const {
10636 // Create the TargetGlobalAddress node, folding in the constant
10637 // offset if it is legal.
10638 unsigned char OpFlags =
10639 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10640 CodeModel::Model M = DAG.getTarget().getCodeModel();
10642 if (OpFlags == X86II::MO_NO_FLAG &&
10643 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10644 // A direct static reference to a global.
10645 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10648 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10651 if (Subtarget->isPICStyleRIPRel() &&
10652 (M == CodeModel::Small || M == CodeModel::Kernel))
10653 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10655 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10657 // With PIC, the address is actually $g + Offset.
10658 if (isGlobalRelativeToPICBase(OpFlags)) {
10659 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10660 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10664 // For globals that require a load from a stub to get the address, emit the
10666 if (isGlobalStubReference(OpFlags))
10667 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10668 MachinePointerInfo::getGOT(), false, false, false, 0);
10670 // If there was a non-zero offset that we didn't fold, create an explicit
10671 // addition for it.
10673 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10674 DAG.getConstant(Offset, getPointerTy()));
10680 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10681 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10682 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10683 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10687 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10688 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10689 unsigned char OperandFlags, bool LocalDynamic = false) {
10690 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10691 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10693 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10694 GA->getValueType(0),
10698 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10702 SDValue Ops[] = { Chain, TGA, *InFlag };
10703 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10705 SDValue Ops[] = { Chain, TGA };
10706 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10709 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10710 MFI->setAdjustsStack(true);
10712 SDValue Flag = Chain.getValue(1);
10713 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10716 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10718 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10721 SDLoc dl(GA); // ? function entry point might be better
10722 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10723 DAG.getNode(X86ISD::GlobalBaseReg,
10724 SDLoc(), PtrVT), InFlag);
10725 InFlag = Chain.getValue(1);
10727 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10730 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10732 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10734 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10735 X86::RAX, X86II::MO_TLSGD);
10738 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10744 // Get the start address of the TLS block for this module.
10745 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10746 .getInfo<X86MachineFunctionInfo>();
10747 MFI->incNumLocalDynamicTLSAccesses();
10751 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10752 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10755 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10756 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10757 InFlag = Chain.getValue(1);
10758 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10759 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10762 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10766 unsigned char OperandFlags = X86II::MO_DTPOFF;
10767 unsigned WrapperKind = X86ISD::Wrapper;
10768 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10769 GA->getValueType(0),
10770 GA->getOffset(), OperandFlags);
10771 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10773 // Add x@dtpoff with the base.
10774 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10777 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10778 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10779 const EVT PtrVT, TLSModel::Model model,
10780 bool is64Bit, bool isPIC) {
10783 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10784 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10785 is64Bit ? 257 : 256));
10787 SDValue ThreadPointer =
10788 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10789 MachinePointerInfo(Ptr), false, false, false, 0);
10791 unsigned char OperandFlags = 0;
10792 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10794 unsigned WrapperKind = X86ISD::Wrapper;
10795 if (model == TLSModel::LocalExec) {
10796 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10797 } else if (model == TLSModel::InitialExec) {
10799 OperandFlags = X86II::MO_GOTTPOFF;
10800 WrapperKind = X86ISD::WrapperRIP;
10802 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10805 llvm_unreachable("Unexpected model");
10808 // emit "addl x@ntpoff,%eax" (local exec)
10809 // or "addl x@indntpoff,%eax" (initial exec)
10810 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10812 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10813 GA->getOffset(), OperandFlags);
10814 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10816 if (model == TLSModel::InitialExec) {
10817 if (isPIC && !is64Bit) {
10818 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10819 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10823 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10824 MachinePointerInfo::getGOT(), false, false, false, 0);
10827 // The address of the thread local variable is the add of the thread
10828 // pointer with the offset of the variable.
10829 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10833 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10835 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10836 const GlobalValue *GV = GA->getGlobal();
10838 if (Subtarget->isTargetELF()) {
10839 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10842 case TLSModel::GeneralDynamic:
10843 if (Subtarget->is64Bit())
10844 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10845 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10846 case TLSModel::LocalDynamic:
10847 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10848 Subtarget->is64Bit());
10849 case TLSModel::InitialExec:
10850 case TLSModel::LocalExec:
10851 return LowerToTLSExecModel(
10852 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10853 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10855 llvm_unreachable("Unknown TLS model.");
10858 if (Subtarget->isTargetDarwin()) {
10859 // Darwin only has one model of TLS. Lower to that.
10860 unsigned char OpFlag = 0;
10861 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10862 X86ISD::WrapperRIP : X86ISD::Wrapper;
10864 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10865 // global base reg.
10866 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10867 !Subtarget->is64Bit();
10869 OpFlag = X86II::MO_TLVP_PIC_BASE;
10871 OpFlag = X86II::MO_TLVP;
10873 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10874 GA->getValueType(0),
10875 GA->getOffset(), OpFlag);
10876 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10878 // With PIC32, the address is actually $g + Offset.
10880 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10881 DAG.getNode(X86ISD::GlobalBaseReg,
10882 SDLoc(), getPointerTy()),
10885 // Lowering the machine isd will make sure everything is in the right
10887 SDValue Chain = DAG.getEntryNode();
10888 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10889 SDValue Args[] = { Chain, Offset };
10890 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10892 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10893 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10894 MFI->setAdjustsStack(true);
10896 // And our return value (tls address) is in the standard call return value
10898 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10899 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10900 Chain.getValue(1));
10903 if (Subtarget->isTargetKnownWindowsMSVC() ||
10904 Subtarget->isTargetWindowsGNU()) {
10905 // Just use the implicit TLS architecture
10906 // Need to generate someting similar to:
10907 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10909 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10910 // mov rcx, qword [rdx+rcx*8]
10911 // mov eax, .tls$:tlsvar
10912 // [rax+rcx] contains the address
10913 // Windows 64bit: gs:0x58
10914 // Windows 32bit: fs:__tls_array
10917 SDValue Chain = DAG.getEntryNode();
10919 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10920 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10921 // use its literal value of 0x2C.
10922 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10923 ? Type::getInt8PtrTy(*DAG.getContext(),
10925 : Type::getInt32PtrTy(*DAG.getContext(),
10929 Subtarget->is64Bit()
10930 ? DAG.getIntPtrConstant(0x58)
10931 : (Subtarget->isTargetWindowsGNU()
10932 ? DAG.getIntPtrConstant(0x2C)
10933 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10935 SDValue ThreadPointer =
10936 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10937 MachinePointerInfo(Ptr), false, false, false, 0);
10939 // Load the _tls_index variable
10940 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10941 if (Subtarget->is64Bit())
10942 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10943 IDX, MachinePointerInfo(), MVT::i32,
10944 false, false, false, 0);
10946 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10947 false, false, false, 0);
10949 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10951 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10953 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10954 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10955 false, false, false, 0);
10957 // Get the offset of start of .tls section
10958 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10959 GA->getValueType(0),
10960 GA->getOffset(), X86II::MO_SECREL);
10961 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10963 // The address of the thread local variable is the add of the thread
10964 // pointer with the offset of the variable.
10965 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10968 llvm_unreachable("TLS not implemented for this target.");
10971 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
10972 /// and take a 2 x i32 value to shift plus a shift amount.
10973 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
10974 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
10975 MVT VT = Op.getSimpleValueType();
10976 unsigned VTBits = VT.getSizeInBits();
10978 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
10979 SDValue ShOpLo = Op.getOperand(0);
10980 SDValue ShOpHi = Op.getOperand(1);
10981 SDValue ShAmt = Op.getOperand(2);
10982 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
10983 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
10985 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10986 DAG.getConstant(VTBits - 1, MVT::i8));
10987 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
10988 DAG.getConstant(VTBits - 1, MVT::i8))
10989 : DAG.getConstant(0, VT);
10991 SDValue Tmp2, Tmp3;
10992 if (Op.getOpcode() == ISD::SHL_PARTS) {
10993 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
10994 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10996 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
10997 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11000 // If the shift amount is larger or equal than the width of a part we can't
11001 // rely on the results of shld/shrd. Insert a test and select the appropriate
11002 // values for large shift amounts.
11003 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11004 DAG.getConstant(VTBits, MVT::i8));
11005 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11006 AndNode, DAG.getConstant(0, MVT::i8));
11009 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11010 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11011 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11013 if (Op.getOpcode() == ISD::SHL_PARTS) {
11014 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11015 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11017 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11018 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11021 SDValue Ops[2] = { Lo, Hi };
11022 return DAG.getMergeValues(Ops, dl);
11025 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11026 SelectionDAG &DAG) const {
11027 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11029 if (SrcVT.isVector())
11032 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11033 "Unknown SINT_TO_FP to lower!");
11035 // These are really Legal; return the operand so the caller accepts it as
11037 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11039 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11040 Subtarget->is64Bit()) {
11045 unsigned Size = SrcVT.getSizeInBits()/8;
11046 MachineFunction &MF = DAG.getMachineFunction();
11047 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11048 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11049 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11051 MachinePointerInfo::getFixedStack(SSFI),
11053 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11056 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11058 SelectionDAG &DAG) const {
11062 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11064 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11066 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11068 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11070 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11071 MachineMemOperand *MMO;
11073 int SSFI = FI->getIndex();
11075 DAG.getMachineFunction()
11076 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11077 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11079 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11080 StackSlot = StackSlot.getOperand(1);
11082 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11083 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11085 Tys, Ops, SrcVT, MMO);
11088 Chain = Result.getValue(1);
11089 SDValue InFlag = Result.getValue(2);
11091 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11092 // shouldn't be necessary except that RFP cannot be live across
11093 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11094 MachineFunction &MF = DAG.getMachineFunction();
11095 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11096 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11097 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11098 Tys = DAG.getVTList(MVT::Other);
11100 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11102 MachineMemOperand *MMO =
11103 DAG.getMachineFunction()
11104 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11105 MachineMemOperand::MOStore, SSFISize, SSFISize);
11107 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11108 Ops, Op.getValueType(), MMO);
11109 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11110 MachinePointerInfo::getFixedStack(SSFI),
11111 false, false, false, 0);
11117 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11118 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11119 SelectionDAG &DAG) const {
11120 // This algorithm is not obvious. Here it is what we're trying to output:
11123 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11124 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11126 haddpd %xmm0, %xmm0
11128 pshufd $0x4e, %xmm0, %xmm1
11134 LLVMContext *Context = DAG.getContext();
11136 // Build some magic constants.
11137 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11138 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11139 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11141 SmallVector<Constant*,2> CV1;
11143 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11144 APInt(64, 0x4330000000000000ULL))));
11146 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11147 APInt(64, 0x4530000000000000ULL))));
11148 Constant *C1 = ConstantVector::get(CV1);
11149 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11151 // Load the 64-bit value into an XMM register.
11152 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11154 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11155 MachinePointerInfo::getConstantPool(),
11156 false, false, false, 16);
11157 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11158 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11161 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11162 MachinePointerInfo::getConstantPool(),
11163 false, false, false, 16);
11164 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11165 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11168 if (Subtarget->hasSSE3()) {
11169 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11170 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11172 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11173 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11175 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11176 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11180 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11181 DAG.getIntPtrConstant(0));
11184 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11185 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11186 SelectionDAG &DAG) const {
11188 // FP constant to bias correct the final result.
11189 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11192 // Load the 32-bit value into an XMM register.
11193 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11196 // Zero out the upper parts of the register.
11197 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11199 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11200 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11201 DAG.getIntPtrConstant(0));
11203 // Or the load with the bias.
11204 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11205 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11206 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11207 MVT::v2f64, Load)),
11208 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11209 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11210 MVT::v2f64, Bias)));
11211 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11212 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11213 DAG.getIntPtrConstant(0));
11215 // Subtract the bias.
11216 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11218 // Handle final rounding.
11219 EVT DestVT = Op.getValueType();
11221 if (DestVT.bitsLT(MVT::f64))
11222 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11223 DAG.getIntPtrConstant(0));
11224 if (DestVT.bitsGT(MVT::f64))
11225 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11227 // Handle final rounding.
11231 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11232 SelectionDAG &DAG) const {
11233 SDValue N0 = Op.getOperand(0);
11234 MVT SVT = N0.getSimpleValueType();
11237 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11238 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11239 "Custom UINT_TO_FP is not supported!");
11241 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11242 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11243 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11246 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11247 SelectionDAG &DAG) const {
11248 SDValue N0 = Op.getOperand(0);
11251 if (Op.getValueType().isVector())
11252 return lowerUINT_TO_FP_vec(Op, DAG);
11254 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11255 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11256 // the optimization here.
11257 if (DAG.SignBitIsZero(N0))
11258 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11260 MVT SrcVT = N0.getSimpleValueType();
11261 MVT DstVT = Op.getSimpleValueType();
11262 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11263 return LowerUINT_TO_FP_i64(Op, DAG);
11264 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11265 return LowerUINT_TO_FP_i32(Op, DAG);
11266 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11269 // Make a 64-bit buffer, and use it to build an FILD.
11270 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11271 if (SrcVT == MVT::i32) {
11272 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11273 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11274 getPointerTy(), StackSlot, WordOff);
11275 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11276 StackSlot, MachinePointerInfo(),
11278 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11279 OffsetSlot, MachinePointerInfo(),
11281 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11285 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11286 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11287 StackSlot, MachinePointerInfo(),
11289 // For i64 source, we need to add the appropriate power of 2 if the input
11290 // was negative. This is the same as the optimization in
11291 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11292 // we must be careful to do the computation in x87 extended precision, not
11293 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11294 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11295 MachineMemOperand *MMO =
11296 DAG.getMachineFunction()
11297 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11298 MachineMemOperand::MOLoad, 8, 8);
11300 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11301 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11302 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11305 APInt FF(32, 0x5F800000ULL);
11307 // Check whether the sign bit is set.
11308 SDValue SignSet = DAG.getSetCC(dl,
11309 getSetCCResultType(*DAG.getContext(), MVT::i64),
11310 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11313 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11314 SDValue FudgePtr = DAG.getConstantPool(
11315 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11318 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11319 SDValue Zero = DAG.getIntPtrConstant(0);
11320 SDValue Four = DAG.getIntPtrConstant(4);
11321 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11323 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11325 // Load the value out, extending it from f32 to f80.
11326 // FIXME: Avoid the extend by constructing the right constant pool?
11327 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11328 FudgePtr, MachinePointerInfo::getConstantPool(),
11329 MVT::f32, false, false, false, 4);
11330 // Extend everything to 80 bits to force it to be done on x87.
11331 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11332 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11335 std::pair<SDValue,SDValue>
11336 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11337 bool IsSigned, bool IsReplace) const {
11340 EVT DstTy = Op.getValueType();
11342 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11343 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11347 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11348 DstTy.getSimpleVT() >= MVT::i16 &&
11349 "Unknown FP_TO_INT to lower!");
11351 // These are really Legal.
11352 if (DstTy == MVT::i32 &&
11353 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11354 return std::make_pair(SDValue(), SDValue());
11355 if (Subtarget->is64Bit() &&
11356 DstTy == MVT::i64 &&
11357 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11358 return std::make_pair(SDValue(), SDValue());
11360 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11361 // stack slot, or into the FTOL runtime function.
11362 MachineFunction &MF = DAG.getMachineFunction();
11363 unsigned MemSize = DstTy.getSizeInBits()/8;
11364 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11365 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11368 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11369 Opc = X86ISD::WIN_FTOL;
11371 switch (DstTy.getSimpleVT().SimpleTy) {
11372 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11373 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11374 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11375 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11378 SDValue Chain = DAG.getEntryNode();
11379 SDValue Value = Op.getOperand(0);
11380 EVT TheVT = Op.getOperand(0).getValueType();
11381 // FIXME This causes a redundant load/store if the SSE-class value is already
11382 // in memory, such as if it is on the callstack.
11383 if (isScalarFPTypeInSSEReg(TheVT)) {
11384 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11385 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11386 MachinePointerInfo::getFixedStack(SSFI),
11388 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11390 Chain, StackSlot, DAG.getValueType(TheVT)
11393 MachineMemOperand *MMO =
11394 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11395 MachineMemOperand::MOLoad, MemSize, MemSize);
11396 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11397 Chain = Value.getValue(1);
11398 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11399 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11402 MachineMemOperand *MMO =
11403 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11404 MachineMemOperand::MOStore, MemSize, MemSize);
11406 if (Opc != X86ISD::WIN_FTOL) {
11407 // Build the FP_TO_INT*_IN_MEM
11408 SDValue Ops[] = { Chain, Value, StackSlot };
11409 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11411 return std::make_pair(FIST, StackSlot);
11413 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11414 DAG.getVTList(MVT::Other, MVT::Glue),
11416 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11417 MVT::i32, ftol.getValue(1));
11418 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11419 MVT::i32, eax.getValue(2));
11420 SDValue Ops[] = { eax, edx };
11421 SDValue pair = IsReplace
11422 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11423 : DAG.getMergeValues(Ops, DL);
11424 return std::make_pair(pair, SDValue());
11428 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11429 const X86Subtarget *Subtarget) {
11430 MVT VT = Op->getSimpleValueType(0);
11431 SDValue In = Op->getOperand(0);
11432 MVT InVT = In.getSimpleValueType();
11435 // Optimize vectors in AVX mode:
11438 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11439 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11440 // Concat upper and lower parts.
11443 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11444 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11445 // Concat upper and lower parts.
11448 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11449 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11450 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11453 if (Subtarget->hasInt256())
11454 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11456 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11457 SDValue Undef = DAG.getUNDEF(InVT);
11458 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11459 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11460 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11462 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11463 VT.getVectorNumElements()/2);
11465 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11466 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11468 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11471 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11472 SelectionDAG &DAG) {
11473 MVT VT = Op->getSimpleValueType(0);
11474 SDValue In = Op->getOperand(0);
11475 MVT InVT = In.getSimpleValueType();
11477 unsigned int NumElts = VT.getVectorNumElements();
11478 if (NumElts != 8 && NumElts != 16)
11481 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11482 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11484 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11485 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11486 // Now we have only mask extension
11487 assert(InVT.getVectorElementType() == MVT::i1);
11488 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11489 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11490 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11491 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11492 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11493 MachinePointerInfo::getConstantPool(),
11494 false, false, false, Alignment);
11496 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11497 if (VT.is512BitVector())
11499 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11502 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11503 SelectionDAG &DAG) {
11504 if (Subtarget->hasFp256()) {
11505 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11513 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11514 SelectionDAG &DAG) {
11516 MVT VT = Op.getSimpleValueType();
11517 SDValue In = Op.getOperand(0);
11518 MVT SVT = In.getSimpleValueType();
11520 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11521 return LowerZERO_EXTEND_AVX512(Op, DAG);
11523 if (Subtarget->hasFp256()) {
11524 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11529 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11530 VT.getVectorNumElements() != SVT.getVectorNumElements());
11534 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11536 MVT VT = Op.getSimpleValueType();
11537 SDValue In = Op.getOperand(0);
11538 MVT InVT = In.getSimpleValueType();
11540 if (VT == MVT::i1) {
11541 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11542 "Invalid scalar TRUNCATE operation");
11543 if (InVT == MVT::i32)
11545 if (InVT.getSizeInBits() == 64)
11546 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11547 else if (InVT.getSizeInBits() < 32)
11548 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11549 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11551 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11552 "Invalid TRUNCATE operation");
11554 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11555 if (VT.getVectorElementType().getSizeInBits() >=8)
11556 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11558 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11559 unsigned NumElts = InVT.getVectorNumElements();
11560 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11561 if (InVT.getSizeInBits() < 512) {
11562 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11563 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11567 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11568 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11569 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11570 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11571 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11572 MachinePointerInfo::getConstantPool(),
11573 false, false, false, Alignment);
11574 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11575 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11576 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11579 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11580 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11581 if (Subtarget->hasInt256()) {
11582 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11583 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11584 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11586 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11587 DAG.getIntPtrConstant(0));
11590 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11591 DAG.getIntPtrConstant(0));
11592 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11593 DAG.getIntPtrConstant(2));
11594 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11595 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11596 static const int ShufMask[] = {0, 2, 4, 6};
11597 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11600 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11601 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11602 if (Subtarget->hasInt256()) {
11603 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11605 SmallVector<SDValue,32> pshufbMask;
11606 for (unsigned i = 0; i < 2; ++i) {
11607 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11608 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11609 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11610 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11611 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11612 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11613 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11614 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11615 for (unsigned j = 0; j < 8; ++j)
11616 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11618 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11619 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11620 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11622 static const int ShufMask[] = {0, 2, -1, -1};
11623 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11625 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11626 DAG.getIntPtrConstant(0));
11627 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11630 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11631 DAG.getIntPtrConstant(0));
11633 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11634 DAG.getIntPtrConstant(4));
11636 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11637 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11639 // The PSHUFB mask:
11640 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11641 -1, -1, -1, -1, -1, -1, -1, -1};
11643 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11644 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11645 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11647 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11648 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11650 // The MOVLHPS Mask:
11651 static const int ShufMask2[] = {0, 1, 4, 5};
11652 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11653 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11656 // Handle truncation of V256 to V128 using shuffles.
11657 if (!VT.is128BitVector() || !InVT.is256BitVector())
11660 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11662 unsigned NumElems = VT.getVectorNumElements();
11663 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11665 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11666 // Prepare truncation shuffle mask
11667 for (unsigned i = 0; i != NumElems; ++i)
11668 MaskVec[i] = i * 2;
11669 SDValue V = DAG.getVectorShuffle(NVT, DL,
11670 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11671 DAG.getUNDEF(NVT), &MaskVec[0]);
11672 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11673 DAG.getIntPtrConstant(0));
11676 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11677 SelectionDAG &DAG) const {
11678 assert(!Op.getSimpleValueType().isVector());
11680 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11681 /*IsSigned=*/ true, /*IsReplace=*/ false);
11682 SDValue FIST = Vals.first, StackSlot = Vals.second;
11683 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11684 if (!FIST.getNode()) return Op;
11686 if (StackSlot.getNode())
11687 // Load the result.
11688 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11689 FIST, StackSlot, MachinePointerInfo(),
11690 false, false, false, 0);
11692 // The node is the result.
11696 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11697 SelectionDAG &DAG) const {
11698 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11699 /*IsSigned=*/ false, /*IsReplace=*/ false);
11700 SDValue FIST = Vals.first, StackSlot = Vals.second;
11701 assert(FIST.getNode() && "Unexpected failure");
11703 if (StackSlot.getNode())
11704 // Load the result.
11705 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11706 FIST, StackSlot, MachinePointerInfo(),
11707 false, false, false, 0);
11709 // The node is the result.
11713 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11715 MVT VT = Op.getSimpleValueType();
11716 SDValue In = Op.getOperand(0);
11717 MVT SVT = In.getSimpleValueType();
11719 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11721 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11722 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11723 In, DAG.getUNDEF(SVT)));
11726 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11727 LLVMContext *Context = DAG.getContext();
11729 MVT VT = Op.getSimpleValueType();
11731 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11732 if (VT.isVector()) {
11733 EltVT = VT.getVectorElementType();
11734 NumElts = VT.getVectorNumElements();
11737 if (EltVT == MVT::f64)
11738 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11739 APInt(64, ~(1ULL << 63))));
11741 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11742 APInt(32, ~(1U << 31))));
11743 C = ConstantVector::getSplat(NumElts, C);
11744 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11745 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11746 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11747 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11748 MachinePointerInfo::getConstantPool(),
11749 false, false, false, Alignment);
11750 if (VT.isVector()) {
11751 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11752 return DAG.getNode(ISD::BITCAST, dl, VT,
11753 DAG.getNode(ISD::AND, dl, ANDVT,
11754 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11756 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11758 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11761 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11762 LLVMContext *Context = DAG.getContext();
11764 MVT VT = Op.getSimpleValueType();
11766 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11767 if (VT.isVector()) {
11768 EltVT = VT.getVectorElementType();
11769 NumElts = VT.getVectorNumElements();
11772 if (EltVT == MVT::f64)
11773 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11774 APInt(64, 1ULL << 63)));
11776 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11777 APInt(32, 1U << 31)));
11778 C = ConstantVector::getSplat(NumElts, C);
11779 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11780 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11781 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11782 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11783 MachinePointerInfo::getConstantPool(),
11784 false, false, false, Alignment);
11785 if (VT.isVector()) {
11786 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11787 return DAG.getNode(ISD::BITCAST, dl, VT,
11788 DAG.getNode(ISD::XOR, dl, XORVT,
11789 DAG.getNode(ISD::BITCAST, dl, XORVT,
11791 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11794 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11797 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11798 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11799 LLVMContext *Context = DAG.getContext();
11800 SDValue Op0 = Op.getOperand(0);
11801 SDValue Op1 = Op.getOperand(1);
11803 MVT VT = Op.getSimpleValueType();
11804 MVT SrcVT = Op1.getSimpleValueType();
11806 // If second operand is smaller, extend it first.
11807 if (SrcVT.bitsLT(VT)) {
11808 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
11811 // And if it is bigger, shrink it first.
11812 if (SrcVT.bitsGT(VT)) {
11813 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
11817 // At this point the operands and the result should have the same
11818 // type, and that won't be f80 since that is not custom lowered.
11820 // First get the sign bit of second operand.
11821 SmallVector<Constant*,4> CV;
11822 if (SrcVT == MVT::f64) {
11823 const fltSemantics &Sem = APFloat::IEEEdouble;
11824 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
11825 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11827 const fltSemantics &Sem = APFloat::IEEEsingle;
11828 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
11829 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11830 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11831 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11833 Constant *C = ConstantVector::get(CV);
11834 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11835 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
11836 MachinePointerInfo::getConstantPool(),
11837 false, false, false, 16);
11838 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
11840 // Shift sign bit right or left if the two operands have different types.
11841 if (SrcVT.bitsGT(VT)) {
11842 // Op0 is MVT::f32, Op1 is MVT::f64.
11843 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
11844 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
11845 DAG.getConstant(32, MVT::i32));
11846 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11847 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
11848 DAG.getIntPtrConstant(0));
11851 // Clear first operand sign bit.
11853 if (VT == MVT::f64) {
11854 const fltSemantics &Sem = APFloat::IEEEdouble;
11855 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11856 APInt(64, ~(1ULL << 63)))));
11857 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11859 const fltSemantics &Sem = APFloat::IEEEsingle;
11860 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11861 APInt(32, ~(1U << 31)))));
11862 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11863 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11864 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11866 C = ConstantVector::get(CV);
11867 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11868 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11869 MachinePointerInfo::getConstantPool(),
11870 false, false, false, 16);
11871 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
11873 // Or the value with the sign bit.
11874 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
11877 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
11878 SDValue N0 = Op.getOperand(0);
11880 MVT VT = Op.getSimpleValueType();
11882 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
11883 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
11884 DAG.getConstant(1, VT));
11885 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
11888 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
11890 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
11891 SelectionDAG &DAG) {
11892 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
11894 if (!Subtarget->hasSSE41())
11897 if (!Op->hasOneUse())
11900 SDNode *N = Op.getNode();
11903 SmallVector<SDValue, 8> Opnds;
11904 DenseMap<SDValue, unsigned> VecInMap;
11905 SmallVector<SDValue, 8> VecIns;
11906 EVT VT = MVT::Other;
11908 // Recognize a special case where a vector is casted into wide integer to
11910 Opnds.push_back(N->getOperand(0));
11911 Opnds.push_back(N->getOperand(1));
11913 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
11914 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
11915 // BFS traverse all OR'd operands.
11916 if (I->getOpcode() == ISD::OR) {
11917 Opnds.push_back(I->getOperand(0));
11918 Opnds.push_back(I->getOperand(1));
11919 // Re-evaluate the number of nodes to be traversed.
11920 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11924 // Quit if a non-EXTRACT_VECTOR_ELT
11925 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11928 // Quit if without a constant index.
11929 SDValue Idx = I->getOperand(1);
11930 if (!isa<ConstantSDNode>(Idx))
11933 SDValue ExtractedFromVec = I->getOperand(0);
11934 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
11935 if (M == VecInMap.end()) {
11936 VT = ExtractedFromVec.getValueType();
11937 // Quit if not 128/256-bit vector.
11938 if (!VT.is128BitVector() && !VT.is256BitVector())
11940 // Quit if not the same type.
11941 if (VecInMap.begin() != VecInMap.end() &&
11942 VT != VecInMap.begin()->first.getValueType())
11944 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
11945 VecIns.push_back(ExtractedFromVec);
11947 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
11950 assert((VT.is128BitVector() || VT.is256BitVector()) &&
11951 "Not extracted from 128-/256-bit vector.");
11953 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
11955 for (DenseMap<SDValue, unsigned>::const_iterator
11956 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
11957 // Quit if not all elements are used.
11958 if (I->second != FullMask)
11962 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11964 // Cast all vectors into TestVT for PTEST.
11965 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
11966 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
11968 // If more than one full vectors are evaluated, OR them first before PTEST.
11969 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
11970 // Each iteration will OR 2 nodes and append the result until there is only
11971 // 1 node left, i.e. the final OR'd value of all vectors.
11972 SDValue LHS = VecIns[Slot];
11973 SDValue RHS = VecIns[Slot + 1];
11974 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11977 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
11978 VecIns.back(), VecIns.back());
11981 /// \brief return true if \c Op has a use that doesn't just read flags.
11982 static bool hasNonFlagsUse(SDValue Op) {
11983 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
11985 SDNode *User = *UI;
11986 unsigned UOpNo = UI.getOperandNo();
11987 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
11988 // Look pass truncate.
11989 UOpNo = User->use_begin().getOperandNo();
11990 User = *User->use_begin();
11993 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11994 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12000 /// Emit nodes that will be selected as "test Op0,Op0", or something
12002 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12003 SelectionDAG &DAG) const {
12004 if (Op.getValueType() == MVT::i1)
12005 // KORTEST instruction should be selected
12006 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12007 DAG.getConstant(0, Op.getValueType()));
12009 // CF and OF aren't always set the way we want. Determine which
12010 // of these we need.
12011 bool NeedCF = false;
12012 bool NeedOF = false;
12015 case X86::COND_A: case X86::COND_AE:
12016 case X86::COND_B: case X86::COND_BE:
12019 case X86::COND_G: case X86::COND_GE:
12020 case X86::COND_L: case X86::COND_LE:
12021 case X86::COND_O: case X86::COND_NO: {
12022 // Check if we really need to set the
12023 // Overflow flag. If NoSignedWrap is present
12024 // that is not actually needed.
12025 switch (Op->getOpcode()) {
12030 const BinaryWithFlagsSDNode *BinNode =
12031 cast<BinaryWithFlagsSDNode>(Op.getNode());
12032 if (BinNode->hasNoSignedWrap())
12042 // See if we can use the EFLAGS value from the operand instead of
12043 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12044 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12045 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12046 // Emit a CMP with 0, which is the TEST pattern.
12047 //if (Op.getValueType() == MVT::i1)
12048 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12049 // DAG.getConstant(0, MVT::i1));
12050 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12051 DAG.getConstant(0, Op.getValueType()));
12053 unsigned Opcode = 0;
12054 unsigned NumOperands = 0;
12056 // Truncate operations may prevent the merge of the SETCC instruction
12057 // and the arithmetic instruction before it. Attempt to truncate the operands
12058 // of the arithmetic instruction and use a reduced bit-width instruction.
12059 bool NeedTruncation = false;
12060 SDValue ArithOp = Op;
12061 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12062 SDValue Arith = Op->getOperand(0);
12063 // Both the trunc and the arithmetic op need to have one user each.
12064 if (Arith->hasOneUse())
12065 switch (Arith.getOpcode()) {
12072 NeedTruncation = true;
12078 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12079 // which may be the result of a CAST. We use the variable 'Op', which is the
12080 // non-casted variable when we check for possible users.
12081 switch (ArithOp.getOpcode()) {
12083 // Due to an isel shortcoming, be conservative if this add is likely to be
12084 // selected as part of a load-modify-store instruction. When the root node
12085 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12086 // uses of other nodes in the match, such as the ADD in this case. This
12087 // leads to the ADD being left around and reselected, with the result being
12088 // two adds in the output. Alas, even if none our users are stores, that
12089 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12090 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12091 // climbing the DAG back to the root, and it doesn't seem to be worth the
12093 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12094 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12095 if (UI->getOpcode() != ISD::CopyToReg &&
12096 UI->getOpcode() != ISD::SETCC &&
12097 UI->getOpcode() != ISD::STORE)
12100 if (ConstantSDNode *C =
12101 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12102 // An add of one will be selected as an INC.
12103 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12104 Opcode = X86ISD::INC;
12109 // An add of negative one (subtract of one) will be selected as a DEC.
12110 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12111 Opcode = X86ISD::DEC;
12117 // Otherwise use a regular EFLAGS-setting add.
12118 Opcode = X86ISD::ADD;
12123 // If we have a constant logical shift that's only used in a comparison
12124 // against zero turn it into an equivalent AND. This allows turning it into
12125 // a TEST instruction later.
12126 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12127 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12128 EVT VT = Op.getValueType();
12129 unsigned BitWidth = VT.getSizeInBits();
12130 unsigned ShAmt = Op->getConstantOperandVal(1);
12131 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12133 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12134 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12135 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12136 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12138 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12139 DAG.getConstant(Mask, VT));
12140 DAG.ReplaceAllUsesWith(Op, New);
12146 // If the primary and result isn't used, don't bother using X86ISD::AND,
12147 // because a TEST instruction will be better.
12148 if (!hasNonFlagsUse(Op))
12154 // Due to the ISEL shortcoming noted above, be conservative if this op is
12155 // likely to be selected as part of a load-modify-store instruction.
12156 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12157 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12158 if (UI->getOpcode() == ISD::STORE)
12161 // Otherwise use a regular EFLAGS-setting instruction.
12162 switch (ArithOp.getOpcode()) {
12163 default: llvm_unreachable("unexpected operator!");
12164 case ISD::SUB: Opcode = X86ISD::SUB; break;
12165 case ISD::XOR: Opcode = X86ISD::XOR; break;
12166 case ISD::AND: Opcode = X86ISD::AND; break;
12168 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12169 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12170 if (EFLAGS.getNode())
12173 Opcode = X86ISD::OR;
12187 return SDValue(Op.getNode(), 1);
12193 // If we found that truncation is beneficial, perform the truncation and
12195 if (NeedTruncation) {
12196 EVT VT = Op.getValueType();
12197 SDValue WideVal = Op->getOperand(0);
12198 EVT WideVT = WideVal.getValueType();
12199 unsigned ConvertedOp = 0;
12200 // Use a target machine opcode to prevent further DAGCombine
12201 // optimizations that may separate the arithmetic operations
12202 // from the setcc node.
12203 switch (WideVal.getOpcode()) {
12205 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12206 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12207 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12208 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12209 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12213 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12214 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12215 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12216 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12217 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12223 // Emit a CMP with 0, which is the TEST pattern.
12224 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12225 DAG.getConstant(0, Op.getValueType()));
12227 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12228 SmallVector<SDValue, 4> Ops;
12229 for (unsigned i = 0; i != NumOperands; ++i)
12230 Ops.push_back(Op.getOperand(i));
12232 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12233 DAG.ReplaceAllUsesWith(Op, New);
12234 return SDValue(New.getNode(), 1);
12237 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12239 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12240 SDLoc dl, SelectionDAG &DAG) const {
12241 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12242 if (C->getAPIntValue() == 0)
12243 return EmitTest(Op0, X86CC, dl, DAG);
12245 if (Op0.getValueType() == MVT::i1)
12246 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12249 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12250 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12251 // Do the comparison at i32 if it's smaller, besides the Atom case.
12252 // This avoids subregister aliasing issues. Keep the smaller reference
12253 // if we're optimizing for size, however, as that'll allow better folding
12254 // of memory operations.
12255 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12256 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12257 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12258 !Subtarget->isAtom()) {
12259 unsigned ExtendOp =
12260 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12261 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12262 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12264 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12265 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12266 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12268 return SDValue(Sub.getNode(), 1);
12270 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12273 /// Convert a comparison if required by the subtarget.
12274 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12275 SelectionDAG &DAG) const {
12276 // If the subtarget does not support the FUCOMI instruction, floating-point
12277 // comparisons have to be converted.
12278 if (Subtarget->hasCMov() ||
12279 Cmp.getOpcode() != X86ISD::CMP ||
12280 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12281 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12284 // The instruction selector will select an FUCOM instruction instead of
12285 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12286 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12287 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12289 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12290 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12291 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12292 DAG.getConstant(8, MVT::i8));
12293 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12294 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12297 static bool isAllOnes(SDValue V) {
12298 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12299 return C && C->isAllOnesValue();
12302 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12303 /// if it's possible.
12304 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12305 SDLoc dl, SelectionDAG &DAG) const {
12306 SDValue Op0 = And.getOperand(0);
12307 SDValue Op1 = And.getOperand(1);
12308 if (Op0.getOpcode() == ISD::TRUNCATE)
12309 Op0 = Op0.getOperand(0);
12310 if (Op1.getOpcode() == ISD::TRUNCATE)
12311 Op1 = Op1.getOperand(0);
12314 if (Op1.getOpcode() == ISD::SHL)
12315 std::swap(Op0, Op1);
12316 if (Op0.getOpcode() == ISD::SHL) {
12317 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12318 if (And00C->getZExtValue() == 1) {
12319 // If we looked past a truncate, check that it's only truncating away
12321 unsigned BitWidth = Op0.getValueSizeInBits();
12322 unsigned AndBitWidth = And.getValueSizeInBits();
12323 if (BitWidth > AndBitWidth) {
12325 DAG.computeKnownBits(Op0, Zeros, Ones);
12326 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12330 RHS = Op0.getOperand(1);
12332 } else if (Op1.getOpcode() == ISD::Constant) {
12333 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12334 uint64_t AndRHSVal = AndRHS->getZExtValue();
12335 SDValue AndLHS = Op0;
12337 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12338 LHS = AndLHS.getOperand(0);
12339 RHS = AndLHS.getOperand(1);
12342 // Use BT if the immediate can't be encoded in a TEST instruction.
12343 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12345 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12349 if (LHS.getNode()) {
12350 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12351 // instruction. Since the shift amount is in-range-or-undefined, we know
12352 // that doing a bittest on the i32 value is ok. We extend to i32 because
12353 // the encoding for the i16 version is larger than the i32 version.
12354 // Also promote i16 to i32 for performance / code size reason.
12355 if (LHS.getValueType() == MVT::i8 ||
12356 LHS.getValueType() == MVT::i16)
12357 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12359 // If the operand types disagree, extend the shift amount to match. Since
12360 // BT ignores high bits (like shifts) we can use anyextend.
12361 if (LHS.getValueType() != RHS.getValueType())
12362 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12364 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12365 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12366 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12367 DAG.getConstant(Cond, MVT::i8), BT);
12373 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12375 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12380 // SSE Condition code mapping:
12389 switch (SetCCOpcode) {
12390 default: llvm_unreachable("Unexpected SETCC condition");
12392 case ISD::SETEQ: SSECC = 0; break;
12394 case ISD::SETGT: Swap = true; // Fallthrough
12396 case ISD::SETOLT: SSECC = 1; break;
12398 case ISD::SETGE: Swap = true; // Fallthrough
12400 case ISD::SETOLE: SSECC = 2; break;
12401 case ISD::SETUO: SSECC = 3; break;
12403 case ISD::SETNE: SSECC = 4; break;
12404 case ISD::SETULE: Swap = true; // Fallthrough
12405 case ISD::SETUGE: SSECC = 5; break;
12406 case ISD::SETULT: Swap = true; // Fallthrough
12407 case ISD::SETUGT: SSECC = 6; break;
12408 case ISD::SETO: SSECC = 7; break;
12410 case ISD::SETONE: SSECC = 8; break;
12413 std::swap(Op0, Op1);
12418 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12419 // ones, and then concatenate the result back.
12420 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12421 MVT VT = Op.getSimpleValueType();
12423 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12424 "Unsupported value type for operation");
12426 unsigned NumElems = VT.getVectorNumElements();
12428 SDValue CC = Op.getOperand(2);
12430 // Extract the LHS vectors
12431 SDValue LHS = Op.getOperand(0);
12432 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12433 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12435 // Extract the RHS vectors
12436 SDValue RHS = Op.getOperand(1);
12437 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12438 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12440 // Issue the operation on the smaller types and concatenate the result back
12441 MVT EltVT = VT.getVectorElementType();
12442 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12443 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12444 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12445 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12448 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12449 const X86Subtarget *Subtarget) {
12450 SDValue Op0 = Op.getOperand(0);
12451 SDValue Op1 = Op.getOperand(1);
12452 SDValue CC = Op.getOperand(2);
12453 MVT VT = Op.getSimpleValueType();
12456 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12457 Op.getValueType().getScalarType() == MVT::i1 &&
12458 "Cannot set masked compare for this operation");
12460 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12462 bool Unsigned = false;
12465 switch (SetCCOpcode) {
12466 default: llvm_unreachable("Unexpected SETCC condition");
12467 case ISD::SETNE: SSECC = 4; break;
12468 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12469 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12470 case ISD::SETLT: Swap = true; //fall-through
12471 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12472 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12473 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12474 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12475 case ISD::SETULE: Unsigned = true; //fall-through
12476 case ISD::SETLE: SSECC = 2; break;
12480 std::swap(Op0, Op1);
12482 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12483 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12484 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12485 DAG.getConstant(SSECC, MVT::i8));
12488 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12489 /// operand \p Op1. If non-trivial (for example because it's not constant)
12490 /// return an empty value.
12491 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12493 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12497 MVT VT = Op1.getSimpleValueType();
12498 MVT EVT = VT.getVectorElementType();
12499 unsigned n = VT.getVectorNumElements();
12500 SmallVector<SDValue, 8> ULTOp1;
12502 for (unsigned i = 0; i < n; ++i) {
12503 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12504 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12507 // Avoid underflow.
12508 APInt Val = Elt->getAPIntValue();
12512 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12515 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12518 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12519 SelectionDAG &DAG) {
12520 SDValue Op0 = Op.getOperand(0);
12521 SDValue Op1 = Op.getOperand(1);
12522 SDValue CC = Op.getOperand(2);
12523 MVT VT = Op.getSimpleValueType();
12524 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12525 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12530 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12531 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12534 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12535 unsigned Opc = X86ISD::CMPP;
12536 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12537 assert(VT.getVectorNumElements() <= 16);
12538 Opc = X86ISD::CMPM;
12540 // In the two special cases we can't handle, emit two comparisons.
12543 unsigned CombineOpc;
12544 if (SetCCOpcode == ISD::SETUEQ) {
12545 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12547 assert(SetCCOpcode == ISD::SETONE);
12548 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12551 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12552 DAG.getConstant(CC0, MVT::i8));
12553 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12554 DAG.getConstant(CC1, MVT::i8));
12555 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12557 // Handle all other FP comparisons here.
12558 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12559 DAG.getConstant(SSECC, MVT::i8));
12562 // Break 256-bit integer vector compare into smaller ones.
12563 if (VT.is256BitVector() && !Subtarget->hasInt256())
12564 return Lower256IntVSETCC(Op, DAG);
12566 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12567 EVT OpVT = Op1.getValueType();
12568 if (Subtarget->hasAVX512()) {
12569 if (Op1.getValueType().is512BitVector() ||
12570 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12571 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12573 // In AVX-512 architecture setcc returns mask with i1 elements,
12574 // But there is no compare instruction for i8 and i16 elements.
12575 // We are not talking about 512-bit operands in this case, these
12576 // types are illegal.
12578 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12579 OpVT.getVectorElementType().getSizeInBits() >= 8))
12580 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12581 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12584 // We are handling one of the integer comparisons here. Since SSE only has
12585 // GT and EQ comparisons for integer, swapping operands and multiple
12586 // operations may be required for some comparisons.
12588 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12589 bool Subus = false;
12591 switch (SetCCOpcode) {
12592 default: llvm_unreachable("Unexpected SETCC condition");
12593 case ISD::SETNE: Invert = true;
12594 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12595 case ISD::SETLT: Swap = true;
12596 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12597 case ISD::SETGE: Swap = true;
12598 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12599 Invert = true; break;
12600 case ISD::SETULT: Swap = true;
12601 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12602 FlipSigns = true; break;
12603 case ISD::SETUGE: Swap = true;
12604 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12605 FlipSigns = true; Invert = true; break;
12608 // Special case: Use min/max operations for SETULE/SETUGE
12609 MVT VET = VT.getVectorElementType();
12611 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12612 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12615 switch (SetCCOpcode) {
12617 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12618 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12621 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12624 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12625 if (!MinMax && hasSubus) {
12626 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12628 // t = psubus Op0, Op1
12629 // pcmpeq t, <0..0>
12630 switch (SetCCOpcode) {
12632 case ISD::SETULT: {
12633 // If the comparison is against a constant we can turn this into a
12634 // setule. With psubus, setule does not require a swap. This is
12635 // beneficial because the constant in the register is no longer
12636 // destructed as the destination so it can be hoisted out of a loop.
12637 // Only do this pre-AVX since vpcmp* is no longer destructive.
12638 if (Subtarget->hasAVX())
12640 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12641 if (ULEOp1.getNode()) {
12643 Subus = true; Invert = false; Swap = false;
12647 // Psubus is better than flip-sign because it requires no inversion.
12648 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12649 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12653 Opc = X86ISD::SUBUS;
12659 std::swap(Op0, Op1);
12661 // Check that the operation in question is available (most are plain SSE2,
12662 // but PCMPGTQ and PCMPEQQ have different requirements).
12663 if (VT == MVT::v2i64) {
12664 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12665 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12667 // First cast everything to the right type.
12668 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12669 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12671 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12672 // bits of the inputs before performing those operations. The lower
12673 // compare is always unsigned.
12676 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12678 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12679 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12680 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12681 Sign, Zero, Sign, Zero);
12683 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12684 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12686 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12687 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12688 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12690 // Create masks for only the low parts/high parts of the 64 bit integers.
12691 static const int MaskHi[] = { 1, 1, 3, 3 };
12692 static const int MaskLo[] = { 0, 0, 2, 2 };
12693 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12694 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12695 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12697 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12698 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12701 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12703 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12706 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12707 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12708 // pcmpeqd + pshufd + pand.
12709 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12711 // First cast everything to the right type.
12712 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12713 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12716 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12718 // Make sure the lower and upper halves are both all-ones.
12719 static const int Mask[] = { 1, 0, 3, 2 };
12720 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12721 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12724 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12726 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12730 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12731 // bits of the inputs before performing those operations.
12733 EVT EltVT = VT.getVectorElementType();
12734 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12735 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12736 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12739 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12741 // If the logical-not of the result is required, perform that now.
12743 Result = DAG.getNOT(dl, Result, VT);
12746 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12749 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12750 getZeroVector(VT, Subtarget, DAG, dl));
12755 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12757 MVT VT = Op.getSimpleValueType();
12759 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12761 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12762 && "SetCC type must be 8-bit or 1-bit integer");
12763 SDValue Op0 = Op.getOperand(0);
12764 SDValue Op1 = Op.getOperand(1);
12766 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12768 // Optimize to BT if possible.
12769 // Lower (X & (1 << N)) == 0 to BT(X, N).
12770 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12771 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12772 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12773 Op1.getOpcode() == ISD::Constant &&
12774 cast<ConstantSDNode>(Op1)->isNullValue() &&
12775 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12776 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12777 if (NewSetCC.getNode())
12781 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12783 if (Op1.getOpcode() == ISD::Constant &&
12784 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12785 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12786 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12788 // If the input is a setcc, then reuse the input setcc or use a new one with
12789 // the inverted condition.
12790 if (Op0.getOpcode() == X86ISD::SETCC) {
12791 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12792 bool Invert = (CC == ISD::SETNE) ^
12793 cast<ConstantSDNode>(Op1)->isNullValue();
12797 CCode = X86::GetOppositeBranchCondition(CCode);
12798 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12799 DAG.getConstant(CCode, MVT::i8),
12800 Op0.getOperand(1));
12802 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12806 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12807 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12808 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12810 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12811 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12814 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12815 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12816 if (X86CC == X86::COND_INVALID)
12819 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12820 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12821 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12822 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12824 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12828 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
12829 static bool isX86LogicalCmp(SDValue Op) {
12830 unsigned Opc = Op.getNode()->getOpcode();
12831 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
12832 Opc == X86ISD::SAHF)
12834 if (Op.getResNo() == 1 &&
12835 (Opc == X86ISD::ADD ||
12836 Opc == X86ISD::SUB ||
12837 Opc == X86ISD::ADC ||
12838 Opc == X86ISD::SBB ||
12839 Opc == X86ISD::SMUL ||
12840 Opc == X86ISD::UMUL ||
12841 Opc == X86ISD::INC ||
12842 Opc == X86ISD::DEC ||
12843 Opc == X86ISD::OR ||
12844 Opc == X86ISD::XOR ||
12845 Opc == X86ISD::AND))
12848 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
12854 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
12855 if (V.getOpcode() != ISD::TRUNCATE)
12858 SDValue VOp0 = V.getOperand(0);
12859 unsigned InBits = VOp0.getValueSizeInBits();
12860 unsigned Bits = V.getValueSizeInBits();
12861 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
12864 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
12865 bool addTest = true;
12866 SDValue Cond = Op.getOperand(0);
12867 SDValue Op1 = Op.getOperand(1);
12868 SDValue Op2 = Op.getOperand(2);
12870 EVT VT = Op1.getValueType();
12873 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12874 // are available. Otherwise fp cmovs get lowered into a less efficient branch
12875 // sequence later on.
12876 if (Cond.getOpcode() == ISD::SETCC &&
12877 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12878 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12879 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12880 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12881 int SSECC = translateX86FSETCC(
12882 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12885 if (Subtarget->hasAVX512()) {
12886 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12887 DAG.getConstant(SSECC, MVT::i8));
12888 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12890 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12891 DAG.getConstant(SSECC, MVT::i8));
12892 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12893 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12894 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12898 if (Cond.getOpcode() == ISD::SETCC) {
12899 SDValue NewCond = LowerSETCC(Cond, DAG);
12900 if (NewCond.getNode())
12904 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12905 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12906 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12907 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12908 if (Cond.getOpcode() == X86ISD::SETCC &&
12909 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12910 isZero(Cond.getOperand(1).getOperand(1))) {
12911 SDValue Cmp = Cond.getOperand(1);
12913 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12915 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12916 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12917 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12919 SDValue CmpOp0 = Cmp.getOperand(0);
12920 // Apply further optimizations for special cases
12921 // (select (x != 0), -1, 0) -> neg & sbb
12922 // (select (x == 0), 0, -1) -> neg & sbb
12923 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12924 if (YC->isNullValue() &&
12925 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12926 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12927 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12928 DAG.getConstant(0, CmpOp0.getValueType()),
12930 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12931 DAG.getConstant(X86::COND_B, MVT::i8),
12932 SDValue(Neg.getNode(), 1));
12936 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12937 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12938 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12940 SDValue Res = // Res = 0 or -1.
12941 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12942 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12944 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12945 Res = DAG.getNOT(DL, Res, Res.getValueType());
12947 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12948 if (!N2C || !N2C->isNullValue())
12949 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12954 // Look past (and (setcc_carry (cmp ...)), 1).
12955 if (Cond.getOpcode() == ISD::AND &&
12956 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12958 if (C && C->getAPIntValue() == 1)
12959 Cond = Cond.getOperand(0);
12962 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12963 // setting operand in place of the X86ISD::SETCC.
12964 unsigned CondOpcode = Cond.getOpcode();
12965 if (CondOpcode == X86ISD::SETCC ||
12966 CondOpcode == X86ISD::SETCC_CARRY) {
12967 CC = Cond.getOperand(0);
12969 SDValue Cmp = Cond.getOperand(1);
12970 unsigned Opc = Cmp.getOpcode();
12971 MVT VT = Op.getSimpleValueType();
12973 bool IllegalFPCMov = false;
12974 if (VT.isFloatingPoint() && !VT.isVector() &&
12975 !isScalarFPTypeInSSEReg(VT)) // FPStack?
12976 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12978 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12979 Opc == X86ISD::BT) { // FIXME
12983 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12984 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12985 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12986 Cond.getOperand(0).getValueType() != MVT::i8)) {
12987 SDValue LHS = Cond.getOperand(0);
12988 SDValue RHS = Cond.getOperand(1);
12989 unsigned X86Opcode;
12992 switch (CondOpcode) {
12993 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12994 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12995 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12996 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12997 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12998 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12999 default: llvm_unreachable("unexpected overflowing operator");
13001 if (CondOpcode == ISD::UMULO)
13002 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13005 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13007 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13009 if (CondOpcode == ISD::UMULO)
13010 Cond = X86Op.getValue(2);
13012 Cond = X86Op.getValue(1);
13014 CC = DAG.getConstant(X86Cond, MVT::i8);
13019 // Look pass the truncate if the high bits are known zero.
13020 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13021 Cond = Cond.getOperand(0);
13023 // We know the result of AND is compared against zero. Try to match
13025 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13026 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13027 if (NewSetCC.getNode()) {
13028 CC = NewSetCC.getOperand(0);
13029 Cond = NewSetCC.getOperand(1);
13036 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13037 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13040 // a < b ? -1 : 0 -> RES = ~setcc_carry
13041 // a < b ? 0 : -1 -> RES = setcc_carry
13042 // a >= b ? -1 : 0 -> RES = setcc_carry
13043 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13044 if (Cond.getOpcode() == X86ISD::SUB) {
13045 Cond = ConvertCmpIfNecessary(Cond, DAG);
13046 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13048 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13049 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13050 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13051 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13052 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13053 return DAG.getNOT(DL, Res, Res.getValueType());
13058 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13059 // widen the cmov and push the truncate through. This avoids introducing a new
13060 // branch during isel and doesn't add any extensions.
13061 if (Op.getValueType() == MVT::i8 &&
13062 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13063 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13064 if (T1.getValueType() == T2.getValueType() &&
13065 // Blacklist CopyFromReg to avoid partial register stalls.
13066 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13067 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13068 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13069 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13073 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13074 // condition is true.
13075 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13076 SDValue Ops[] = { Op2, Op1, CC, Cond };
13077 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13080 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
13081 MVT VT = Op->getSimpleValueType(0);
13082 SDValue In = Op->getOperand(0);
13083 MVT InVT = In.getSimpleValueType();
13086 unsigned int NumElts = VT.getVectorNumElements();
13087 if (NumElts != 8 && NumElts != 16)
13090 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13091 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13094 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13096 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13097 Constant *C = ConstantInt::get(*DAG.getContext(),
13098 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13100 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13101 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13102 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13103 MachinePointerInfo::getConstantPool(),
13104 false, false, false, Alignment);
13105 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13106 if (VT.is512BitVector())
13108 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13111 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13112 SelectionDAG &DAG) {
13113 MVT VT = Op->getSimpleValueType(0);
13114 SDValue In = Op->getOperand(0);
13115 MVT InVT = In.getSimpleValueType();
13118 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13119 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13121 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13122 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13123 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13126 if (Subtarget->hasInt256())
13127 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13129 // Optimize vectors in AVX mode
13130 // Sign extend v8i16 to v8i32 and
13133 // Divide input vector into two parts
13134 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13135 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13136 // concat the vectors to original VT
13138 unsigned NumElems = InVT.getVectorNumElements();
13139 SDValue Undef = DAG.getUNDEF(InVT);
13141 SmallVector<int,8> ShufMask1(NumElems, -1);
13142 for (unsigned i = 0; i != NumElems/2; ++i)
13145 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13147 SmallVector<int,8> ShufMask2(NumElems, -1);
13148 for (unsigned i = 0; i != NumElems/2; ++i)
13149 ShufMask2[i] = i + NumElems/2;
13151 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13153 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13154 VT.getVectorNumElements()/2);
13156 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13157 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13159 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13162 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13163 // may emit an illegal shuffle but the expansion is still better than scalar
13164 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13165 // we'll emit a shuffle and a arithmetic shift.
13166 // TODO: It is possible to support ZExt by zeroing the undef values during
13167 // the shuffle phase or after the shuffle.
13168 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13169 SelectionDAG &DAG) {
13170 MVT RegVT = Op.getSimpleValueType();
13171 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13172 assert(RegVT.isInteger() &&
13173 "We only custom lower integer vector sext loads.");
13175 // Nothing useful we can do without SSE2 shuffles.
13176 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13178 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13180 EVT MemVT = Ld->getMemoryVT();
13181 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13182 unsigned RegSz = RegVT.getSizeInBits();
13184 ISD::LoadExtType Ext = Ld->getExtensionType();
13186 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13187 && "Only anyext and sext are currently implemented.");
13188 assert(MemVT != RegVT && "Cannot extend to the same type");
13189 assert(MemVT.isVector() && "Must load a vector from memory");
13191 unsigned NumElems = RegVT.getVectorNumElements();
13192 unsigned MemSz = MemVT.getSizeInBits();
13193 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13195 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13196 // The only way in which we have a legal 256-bit vector result but not the
13197 // integer 256-bit operations needed to directly lower a sextload is if we
13198 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13199 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13200 // correctly legalized. We do this late to allow the canonical form of
13201 // sextload to persist throughout the rest of the DAG combiner -- it wants
13202 // to fold together any extensions it can, and so will fuse a sign_extend
13203 // of an sextload into an sextload targeting a wider value.
13205 if (MemSz == 128) {
13206 // Just switch this to a normal load.
13207 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13208 "it must be a legal 128-bit vector "
13210 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13211 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13212 Ld->isInvariant(), Ld->getAlignment());
13214 assert(MemSz < 128 &&
13215 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13216 // Do an sext load to a 128-bit vector type. We want to use the same
13217 // number of elements, but elements half as wide. This will end up being
13218 // recursively lowered by this routine, but will succeed as we definitely
13219 // have all the necessary features if we're using AVX1.
13221 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13222 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13224 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13225 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13226 Ld->isNonTemporal(), Ld->isInvariant(),
13227 Ld->getAlignment());
13230 // Replace chain users with the new chain.
13231 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13232 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13234 // Finally, do a normal sign-extend to the desired register.
13235 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13238 // All sizes must be a power of two.
13239 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13240 "Non-power-of-two elements are not custom lowered!");
13242 // Attempt to load the original value using scalar loads.
13243 // Find the largest scalar type that divides the total loaded size.
13244 MVT SclrLoadTy = MVT::i8;
13245 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13246 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13247 MVT Tp = (MVT::SimpleValueType)tp;
13248 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13253 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13254 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13256 SclrLoadTy = MVT::f64;
13258 // Calculate the number of scalar loads that we need to perform
13259 // in order to load our vector from memory.
13260 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13262 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13263 "Can only lower sext loads with a single scalar load!");
13265 unsigned loadRegZize = RegSz;
13266 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13269 // Represent our vector as a sequence of elements which are the
13270 // largest scalar that we can load.
13271 EVT LoadUnitVecVT = EVT::getVectorVT(
13272 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13274 // Represent the data using the same element type that is stored in
13275 // memory. In practice, we ''widen'' MemVT.
13277 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13278 loadRegZize / MemVT.getScalarType().getSizeInBits());
13280 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13281 "Invalid vector type");
13283 // We can't shuffle using an illegal type.
13284 assert(TLI.isTypeLegal(WideVecVT) &&
13285 "We only lower types that form legal widened vector types");
13287 SmallVector<SDValue, 8> Chains;
13288 SDValue Ptr = Ld->getBasePtr();
13289 SDValue Increment =
13290 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13291 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13293 for (unsigned i = 0; i < NumLoads; ++i) {
13294 // Perform a single load.
13295 SDValue ScalarLoad =
13296 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13297 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13298 Ld->getAlignment());
13299 Chains.push_back(ScalarLoad.getValue(1));
13300 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13301 // another round of DAGCombining.
13303 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13305 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13306 ScalarLoad, DAG.getIntPtrConstant(i));
13308 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13311 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13313 // Bitcast the loaded value to a vector of the original element type, in
13314 // the size of the target vector type.
13315 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13316 unsigned SizeRatio = RegSz / MemSz;
13318 if (Ext == ISD::SEXTLOAD) {
13319 // If we have SSE4.1 we can directly emit a VSEXT node.
13320 if (Subtarget->hasSSE41()) {
13321 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13322 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13326 // Otherwise we'll shuffle the small elements in the high bits of the
13327 // larger type and perform an arithmetic shift. If the shift is not legal
13328 // it's better to scalarize.
13329 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13330 "We can't implement an sext load without a arithmetic right shift!");
13332 // Redistribute the loaded elements into the different locations.
13333 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13334 for (unsigned i = 0; i != NumElems; ++i)
13335 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13337 SDValue Shuff = DAG.getVectorShuffle(
13338 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13340 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13342 // Build the arithmetic shift.
13343 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13344 MemVT.getVectorElementType().getSizeInBits();
13346 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13348 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13352 // Redistribute the loaded elements into the different locations.
13353 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13354 for (unsigned i = 0; i != NumElems; ++i)
13355 ShuffleVec[i * SizeRatio] = i;
13357 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13358 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13360 // Bitcast to the requested type.
13361 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13362 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13366 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13367 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13368 // from the AND / OR.
13369 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13370 Opc = Op.getOpcode();
13371 if (Opc != ISD::OR && Opc != ISD::AND)
13373 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13374 Op.getOperand(0).hasOneUse() &&
13375 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13376 Op.getOperand(1).hasOneUse());
13379 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13380 // 1 and that the SETCC node has a single use.
13381 static bool isXor1OfSetCC(SDValue Op) {
13382 if (Op.getOpcode() != ISD::XOR)
13384 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13385 if (N1C && N1C->getAPIntValue() == 1) {
13386 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13387 Op.getOperand(0).hasOneUse();
13392 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13393 bool addTest = true;
13394 SDValue Chain = Op.getOperand(0);
13395 SDValue Cond = Op.getOperand(1);
13396 SDValue Dest = Op.getOperand(2);
13399 bool Inverted = false;
13401 if (Cond.getOpcode() == ISD::SETCC) {
13402 // Check for setcc([su]{add,sub,mul}o == 0).
13403 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13404 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13405 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13406 Cond.getOperand(0).getResNo() == 1 &&
13407 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13408 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13409 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13410 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13411 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13412 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13414 Cond = Cond.getOperand(0);
13416 SDValue NewCond = LowerSETCC(Cond, DAG);
13417 if (NewCond.getNode())
13422 // FIXME: LowerXALUO doesn't handle these!!
13423 else if (Cond.getOpcode() == X86ISD::ADD ||
13424 Cond.getOpcode() == X86ISD::SUB ||
13425 Cond.getOpcode() == X86ISD::SMUL ||
13426 Cond.getOpcode() == X86ISD::UMUL)
13427 Cond = LowerXALUO(Cond, DAG);
13430 // Look pass (and (setcc_carry (cmp ...)), 1).
13431 if (Cond.getOpcode() == ISD::AND &&
13432 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13433 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13434 if (C && C->getAPIntValue() == 1)
13435 Cond = Cond.getOperand(0);
13438 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13439 // setting operand in place of the X86ISD::SETCC.
13440 unsigned CondOpcode = Cond.getOpcode();
13441 if (CondOpcode == X86ISD::SETCC ||
13442 CondOpcode == X86ISD::SETCC_CARRY) {
13443 CC = Cond.getOperand(0);
13445 SDValue Cmp = Cond.getOperand(1);
13446 unsigned Opc = Cmp.getOpcode();
13447 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13448 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13452 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13456 // These can only come from an arithmetic instruction with overflow,
13457 // e.g. SADDO, UADDO.
13458 Cond = Cond.getNode()->getOperand(1);
13464 CondOpcode = Cond.getOpcode();
13465 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13466 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13467 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13468 Cond.getOperand(0).getValueType() != MVT::i8)) {
13469 SDValue LHS = Cond.getOperand(0);
13470 SDValue RHS = Cond.getOperand(1);
13471 unsigned X86Opcode;
13474 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13475 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13477 switch (CondOpcode) {
13478 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13480 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13482 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13485 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13486 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13488 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13490 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13493 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13494 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13495 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13496 default: llvm_unreachable("unexpected overflowing operator");
13499 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13500 if (CondOpcode == ISD::UMULO)
13501 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13504 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13506 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13508 if (CondOpcode == ISD::UMULO)
13509 Cond = X86Op.getValue(2);
13511 Cond = X86Op.getValue(1);
13513 CC = DAG.getConstant(X86Cond, MVT::i8);
13517 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13518 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13519 if (CondOpc == ISD::OR) {
13520 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13521 // two branches instead of an explicit OR instruction with a
13523 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13524 isX86LogicalCmp(Cmp)) {
13525 CC = Cond.getOperand(0).getOperand(0);
13526 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13527 Chain, Dest, CC, Cmp);
13528 CC = Cond.getOperand(1).getOperand(0);
13532 } else { // ISD::AND
13533 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13534 // two branches instead of an explicit AND instruction with a
13535 // separate test. However, we only do this if this block doesn't
13536 // have a fall-through edge, because this requires an explicit
13537 // jmp when the condition is false.
13538 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13539 isX86LogicalCmp(Cmp) &&
13540 Op.getNode()->hasOneUse()) {
13541 X86::CondCode CCode =
13542 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13543 CCode = X86::GetOppositeBranchCondition(CCode);
13544 CC = DAG.getConstant(CCode, MVT::i8);
13545 SDNode *User = *Op.getNode()->use_begin();
13546 // Look for an unconditional branch following this conditional branch.
13547 // We need this because we need to reverse the successors in order
13548 // to implement FCMP_OEQ.
13549 if (User->getOpcode() == ISD::BR) {
13550 SDValue FalseBB = User->getOperand(1);
13552 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13553 assert(NewBR == User);
13557 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13558 Chain, Dest, CC, Cmp);
13559 X86::CondCode CCode =
13560 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13561 CCode = X86::GetOppositeBranchCondition(CCode);
13562 CC = DAG.getConstant(CCode, MVT::i8);
13568 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13569 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13570 // It should be transformed during dag combiner except when the condition
13571 // is set by a arithmetics with overflow node.
13572 X86::CondCode CCode =
13573 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13574 CCode = X86::GetOppositeBranchCondition(CCode);
13575 CC = DAG.getConstant(CCode, MVT::i8);
13576 Cond = Cond.getOperand(0).getOperand(1);
13578 } else if (Cond.getOpcode() == ISD::SETCC &&
13579 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13580 // For FCMP_OEQ, we can emit
13581 // two branches instead of an explicit AND instruction with a
13582 // separate test. However, we only do this if this block doesn't
13583 // have a fall-through edge, because this requires an explicit
13584 // jmp when the condition is false.
13585 if (Op.getNode()->hasOneUse()) {
13586 SDNode *User = *Op.getNode()->use_begin();
13587 // Look for an unconditional branch following this conditional branch.
13588 // We need this because we need to reverse the successors in order
13589 // to implement FCMP_OEQ.
13590 if (User->getOpcode() == ISD::BR) {
13591 SDValue FalseBB = User->getOperand(1);
13593 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13594 assert(NewBR == User);
13598 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13599 Cond.getOperand(0), Cond.getOperand(1));
13600 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13601 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13602 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13603 Chain, Dest, CC, Cmp);
13604 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13609 } else if (Cond.getOpcode() == ISD::SETCC &&
13610 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13611 // For FCMP_UNE, we can emit
13612 // two branches instead of an explicit AND instruction with a
13613 // separate test. However, we only do this if this block doesn't
13614 // have a fall-through edge, because this requires an explicit
13615 // jmp when the condition is false.
13616 if (Op.getNode()->hasOneUse()) {
13617 SDNode *User = *Op.getNode()->use_begin();
13618 // Look for an unconditional branch following this conditional branch.
13619 // We need this because we need to reverse the successors in order
13620 // to implement FCMP_UNE.
13621 if (User->getOpcode() == ISD::BR) {
13622 SDValue FalseBB = User->getOperand(1);
13624 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13625 assert(NewBR == User);
13628 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13629 Cond.getOperand(0), Cond.getOperand(1));
13630 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13631 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13632 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13633 Chain, Dest, CC, Cmp);
13634 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13644 // Look pass the truncate if the high bits are known zero.
13645 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13646 Cond = Cond.getOperand(0);
13648 // We know the result of AND is compared against zero. Try to match
13650 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13651 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13652 if (NewSetCC.getNode()) {
13653 CC = NewSetCC.getOperand(0);
13654 Cond = NewSetCC.getOperand(1);
13661 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13662 CC = DAG.getConstant(X86Cond, MVT::i8);
13663 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13665 Cond = ConvertCmpIfNecessary(Cond, DAG);
13666 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13667 Chain, Dest, CC, Cond);
13670 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13671 // Calls to _alloca is needed to probe the stack when allocating more than 4k
13672 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13673 // that the guard pages used by the OS virtual memory manager are allocated in
13674 // correct sequence.
13676 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13677 SelectionDAG &DAG) const {
13678 MachineFunction &MF = DAG.getMachineFunction();
13679 bool SplitStack = MF.shouldSplitStack();
13680 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13685 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13686 SDNode* Node = Op.getNode();
13688 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13689 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13690 " not tell us which reg is the stack pointer!");
13691 EVT VT = Node->getValueType(0);
13692 SDValue Tmp1 = SDValue(Node, 0);
13693 SDValue Tmp2 = SDValue(Node, 1);
13694 SDValue Tmp3 = Node->getOperand(2);
13695 SDValue Chain = Tmp1.getOperand(0);
13697 // Chain the dynamic stack allocation so that it doesn't modify the stack
13698 // pointer when other instructions are using the stack.
13699 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13702 SDValue Size = Tmp2.getOperand(1);
13703 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13704 Chain = SP.getValue(1);
13705 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13706 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
13707 unsigned StackAlign = TFI.getStackAlignment();
13708 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13709 if (Align > StackAlign)
13710 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13711 DAG.getConstant(-(uint64_t)Align, VT));
13712 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13714 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13715 DAG.getIntPtrConstant(0, true), SDValue(),
13718 SDValue Ops[2] = { Tmp1, Tmp2 };
13719 return DAG.getMergeValues(Ops, dl);
13723 SDValue Chain = Op.getOperand(0);
13724 SDValue Size = Op.getOperand(1);
13725 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13726 EVT VT = Op.getNode()->getValueType(0);
13728 bool Is64Bit = Subtarget->is64Bit();
13729 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13732 MachineRegisterInfo &MRI = MF.getRegInfo();
13735 // The 64 bit implementation of segmented stacks needs to clobber both r10
13736 // r11. This makes it impossible to use it along with nested parameters.
13737 const Function *F = MF.getFunction();
13739 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13741 if (I->hasNestAttr())
13742 report_fatal_error("Cannot use segmented stacks with functions that "
13743 "have nested arguments.");
13746 const TargetRegisterClass *AddrRegClass =
13747 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13748 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13749 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13750 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13751 DAG.getRegister(Vreg, SPTy));
13752 SDValue Ops1[2] = { Value, Chain };
13753 return DAG.getMergeValues(Ops1, dl);
13756 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13758 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13759 Flag = Chain.getValue(1);
13760 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13762 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13764 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
13765 DAG.getSubtarget().getRegisterInfo());
13766 unsigned SPReg = RegInfo->getStackRegister();
13767 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13768 Chain = SP.getValue(1);
13771 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13772 DAG.getConstant(-(uint64_t)Align, VT));
13773 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13776 SDValue Ops1[2] = { SP, Chain };
13777 return DAG.getMergeValues(Ops1, dl);
13781 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13782 MachineFunction &MF = DAG.getMachineFunction();
13783 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13785 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13788 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13789 // vastart just stores the address of the VarArgsFrameIndex slot into the
13790 // memory location argument.
13791 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13793 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13794 MachinePointerInfo(SV), false, false, 0);
13798 // gp_offset (0 - 6 * 8)
13799 // fp_offset (48 - 48 + 8 * 16)
13800 // overflow_arg_area (point to parameters coming in memory).
13802 SmallVector<SDValue, 8> MemOps;
13803 SDValue FIN = Op.getOperand(1);
13805 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13806 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13808 FIN, MachinePointerInfo(SV), false, false, 0);
13809 MemOps.push_back(Store);
13812 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13813 FIN, DAG.getIntPtrConstant(4));
13814 Store = DAG.getStore(Op.getOperand(0), DL,
13815 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13817 FIN, MachinePointerInfo(SV, 4), false, false, 0);
13818 MemOps.push_back(Store);
13820 // Store ptr to overflow_arg_area
13821 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13822 FIN, DAG.getIntPtrConstant(4));
13823 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13825 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13826 MachinePointerInfo(SV, 8),
13828 MemOps.push_back(Store);
13830 // Store ptr to reg_save_area.
13831 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13832 FIN, DAG.getIntPtrConstant(8));
13833 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13835 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13836 MachinePointerInfo(SV, 16), false, false, 0);
13837 MemOps.push_back(Store);
13838 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13841 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
13842 assert(Subtarget->is64Bit() &&
13843 "LowerVAARG only handles 64-bit va_arg!");
13844 assert((Subtarget->isTargetLinux() ||
13845 Subtarget->isTargetDarwin()) &&
13846 "Unhandled target in LowerVAARG");
13847 assert(Op.getNode()->getNumOperands() == 4);
13848 SDValue Chain = Op.getOperand(0);
13849 SDValue SrcPtr = Op.getOperand(1);
13850 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13851 unsigned Align = Op.getConstantOperandVal(3);
13854 EVT ArgVT = Op.getNode()->getValueType(0);
13855 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13856 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13859 // Decide which area this value should be read from.
13860 // TODO: Implement the AMD64 ABI in its entirety. This simple
13861 // selection mechanism works only for the basic types.
13862 if (ArgVT == MVT::f80) {
13863 llvm_unreachable("va_arg for f80 not yet implemented");
13864 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13865 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13866 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13867 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13869 llvm_unreachable("Unhandled argument type in LowerVAARG");
13872 if (ArgMode == 2) {
13873 // Sanity Check: Make sure using fp_offset makes sense.
13874 assert(!DAG.getTarget().Options.UseSoftFloat &&
13875 !(DAG.getMachineFunction()
13876 .getFunction()->getAttributes()
13877 .hasAttribute(AttributeSet::FunctionIndex,
13878 Attribute::NoImplicitFloat)) &&
13879 Subtarget->hasSSE1());
13882 // Insert VAARG_64 node into the DAG
13883 // VAARG_64 returns two values: Variable Argument Address, Chain
13884 SmallVector<SDValue, 11> InstOps;
13885 InstOps.push_back(Chain);
13886 InstOps.push_back(SrcPtr);
13887 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13888 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13889 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13890 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13891 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13892 VTs, InstOps, MVT::i64,
13893 MachinePointerInfo(SV),
13895 /*Volatile=*/false,
13897 /*WriteMem=*/true);
13898 Chain = VAARG.getValue(1);
13900 // Load the next argument and return it
13901 return DAG.getLoad(ArgVT, dl,
13904 MachinePointerInfo(),
13905 false, false, false, 0);
13908 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
13909 SelectionDAG &DAG) {
13910 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
13911 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
13912 SDValue Chain = Op.getOperand(0);
13913 SDValue DstPtr = Op.getOperand(1);
13914 SDValue SrcPtr = Op.getOperand(2);
13915 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
13916 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
13919 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
13920 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
13922 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
13925 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
13926 // amount is a constant. Takes immediate version of shift as input.
13927 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
13928 SDValue SrcOp, uint64_t ShiftAmt,
13929 SelectionDAG &DAG) {
13930 MVT ElementType = VT.getVectorElementType();
13932 // Fold this packed shift into its first operand if ShiftAmt is 0.
13936 // Check for ShiftAmt >= element width
13937 if (ShiftAmt >= ElementType.getSizeInBits()) {
13938 if (Opc == X86ISD::VSRAI)
13939 ShiftAmt = ElementType.getSizeInBits() - 1;
13941 return DAG.getConstant(0, VT);
13944 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
13945 && "Unknown target vector shift-by-constant node");
13947 // Fold this packed vector shift into a build vector if SrcOp is a
13948 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
13949 if (VT == SrcOp.getSimpleValueType() &&
13950 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
13951 SmallVector<SDValue, 8> Elts;
13952 unsigned NumElts = SrcOp->getNumOperands();
13953 ConstantSDNode *ND;
13956 default: llvm_unreachable(nullptr);
13957 case X86ISD::VSHLI:
13958 for (unsigned i=0; i!=NumElts; ++i) {
13959 SDValue CurrentOp = SrcOp->getOperand(i);
13960 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13961 Elts.push_back(CurrentOp);
13964 ND = cast<ConstantSDNode>(CurrentOp);
13965 const APInt &C = ND->getAPIntValue();
13966 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
13969 case X86ISD::VSRLI:
13970 for (unsigned i=0; i!=NumElts; ++i) {
13971 SDValue CurrentOp = SrcOp->getOperand(i);
13972 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13973 Elts.push_back(CurrentOp);
13976 ND = cast<ConstantSDNode>(CurrentOp);
13977 const APInt &C = ND->getAPIntValue();
13978 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
13981 case X86ISD::VSRAI:
13982 for (unsigned i=0; i!=NumElts; ++i) {
13983 SDValue CurrentOp = SrcOp->getOperand(i);
13984 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13985 Elts.push_back(CurrentOp);
13988 ND = cast<ConstantSDNode>(CurrentOp);
13989 const APInt &C = ND->getAPIntValue();
13990 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
13995 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13998 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14001 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14002 // may or may not be a constant. Takes immediate version of shift as input.
14003 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14004 SDValue SrcOp, SDValue ShAmt,
14005 SelectionDAG &DAG) {
14006 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
14008 // Catch shift-by-constant.
14009 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14010 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14011 CShAmt->getZExtValue(), DAG);
14013 // Change opcode to non-immediate version
14015 default: llvm_unreachable("Unknown target vector shift node");
14016 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14017 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14018 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14021 // Need to build a vector containing shift amount
14022 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
14025 ShOps[1] = DAG.getConstant(0, MVT::i32);
14026 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
14027 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
14029 // The return type has to be a 128-bit type with the same element
14030 // type as the input type.
14031 MVT EltVT = VT.getVectorElementType();
14032 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14034 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14035 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14038 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
14040 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14042 default: return SDValue(); // Don't custom lower most intrinsics.
14043 // Comparison intrinsics.
14044 case Intrinsic::x86_sse_comieq_ss:
14045 case Intrinsic::x86_sse_comilt_ss:
14046 case Intrinsic::x86_sse_comile_ss:
14047 case Intrinsic::x86_sse_comigt_ss:
14048 case Intrinsic::x86_sse_comige_ss:
14049 case Intrinsic::x86_sse_comineq_ss:
14050 case Intrinsic::x86_sse_ucomieq_ss:
14051 case Intrinsic::x86_sse_ucomilt_ss:
14052 case Intrinsic::x86_sse_ucomile_ss:
14053 case Intrinsic::x86_sse_ucomigt_ss:
14054 case Intrinsic::x86_sse_ucomige_ss:
14055 case Intrinsic::x86_sse_ucomineq_ss:
14056 case Intrinsic::x86_sse2_comieq_sd:
14057 case Intrinsic::x86_sse2_comilt_sd:
14058 case Intrinsic::x86_sse2_comile_sd:
14059 case Intrinsic::x86_sse2_comigt_sd:
14060 case Intrinsic::x86_sse2_comige_sd:
14061 case Intrinsic::x86_sse2_comineq_sd:
14062 case Intrinsic::x86_sse2_ucomieq_sd:
14063 case Intrinsic::x86_sse2_ucomilt_sd:
14064 case Intrinsic::x86_sse2_ucomile_sd:
14065 case Intrinsic::x86_sse2_ucomigt_sd:
14066 case Intrinsic::x86_sse2_ucomige_sd:
14067 case Intrinsic::x86_sse2_ucomineq_sd: {
14071 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14072 case Intrinsic::x86_sse_comieq_ss:
14073 case Intrinsic::x86_sse2_comieq_sd:
14074 Opc = X86ISD::COMI;
14077 case Intrinsic::x86_sse_comilt_ss:
14078 case Intrinsic::x86_sse2_comilt_sd:
14079 Opc = X86ISD::COMI;
14082 case Intrinsic::x86_sse_comile_ss:
14083 case Intrinsic::x86_sse2_comile_sd:
14084 Opc = X86ISD::COMI;
14087 case Intrinsic::x86_sse_comigt_ss:
14088 case Intrinsic::x86_sse2_comigt_sd:
14089 Opc = X86ISD::COMI;
14092 case Intrinsic::x86_sse_comige_ss:
14093 case Intrinsic::x86_sse2_comige_sd:
14094 Opc = X86ISD::COMI;
14097 case Intrinsic::x86_sse_comineq_ss:
14098 case Intrinsic::x86_sse2_comineq_sd:
14099 Opc = X86ISD::COMI;
14102 case Intrinsic::x86_sse_ucomieq_ss:
14103 case Intrinsic::x86_sse2_ucomieq_sd:
14104 Opc = X86ISD::UCOMI;
14107 case Intrinsic::x86_sse_ucomilt_ss:
14108 case Intrinsic::x86_sse2_ucomilt_sd:
14109 Opc = X86ISD::UCOMI;
14112 case Intrinsic::x86_sse_ucomile_ss:
14113 case Intrinsic::x86_sse2_ucomile_sd:
14114 Opc = X86ISD::UCOMI;
14117 case Intrinsic::x86_sse_ucomigt_ss:
14118 case Intrinsic::x86_sse2_ucomigt_sd:
14119 Opc = X86ISD::UCOMI;
14122 case Intrinsic::x86_sse_ucomige_ss:
14123 case Intrinsic::x86_sse2_ucomige_sd:
14124 Opc = X86ISD::UCOMI;
14127 case Intrinsic::x86_sse_ucomineq_ss:
14128 case Intrinsic::x86_sse2_ucomineq_sd:
14129 Opc = X86ISD::UCOMI;
14134 SDValue LHS = Op.getOperand(1);
14135 SDValue RHS = Op.getOperand(2);
14136 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14137 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14138 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
14139 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14140 DAG.getConstant(X86CC, MVT::i8), Cond);
14141 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14144 // Arithmetic intrinsics.
14145 case Intrinsic::x86_sse2_pmulu_dq:
14146 case Intrinsic::x86_avx2_pmulu_dq:
14147 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14148 Op.getOperand(1), Op.getOperand(2));
14150 case Intrinsic::x86_sse41_pmuldq:
14151 case Intrinsic::x86_avx2_pmul_dq:
14152 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14153 Op.getOperand(1), Op.getOperand(2));
14155 case Intrinsic::x86_sse2_pmulhu_w:
14156 case Intrinsic::x86_avx2_pmulhu_w:
14157 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14158 Op.getOperand(1), Op.getOperand(2));
14160 case Intrinsic::x86_sse2_pmulh_w:
14161 case Intrinsic::x86_avx2_pmulh_w:
14162 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14163 Op.getOperand(1), Op.getOperand(2));
14165 // SSE2/AVX2 sub with unsigned saturation intrinsics
14166 case Intrinsic::x86_sse2_psubus_b:
14167 case Intrinsic::x86_sse2_psubus_w:
14168 case Intrinsic::x86_avx2_psubus_b:
14169 case Intrinsic::x86_avx2_psubus_w:
14170 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
14171 Op.getOperand(1), Op.getOperand(2));
14173 // SSE3/AVX horizontal add/sub intrinsics
14174 case Intrinsic::x86_sse3_hadd_ps:
14175 case Intrinsic::x86_sse3_hadd_pd:
14176 case Intrinsic::x86_avx_hadd_ps_256:
14177 case Intrinsic::x86_avx_hadd_pd_256:
14178 case Intrinsic::x86_sse3_hsub_ps:
14179 case Intrinsic::x86_sse3_hsub_pd:
14180 case Intrinsic::x86_avx_hsub_ps_256:
14181 case Intrinsic::x86_avx_hsub_pd_256:
14182 case Intrinsic::x86_ssse3_phadd_w_128:
14183 case Intrinsic::x86_ssse3_phadd_d_128:
14184 case Intrinsic::x86_avx2_phadd_w:
14185 case Intrinsic::x86_avx2_phadd_d:
14186 case Intrinsic::x86_ssse3_phsub_w_128:
14187 case Intrinsic::x86_ssse3_phsub_d_128:
14188 case Intrinsic::x86_avx2_phsub_w:
14189 case Intrinsic::x86_avx2_phsub_d: {
14192 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14193 case Intrinsic::x86_sse3_hadd_ps:
14194 case Intrinsic::x86_sse3_hadd_pd:
14195 case Intrinsic::x86_avx_hadd_ps_256:
14196 case Intrinsic::x86_avx_hadd_pd_256:
14197 Opcode = X86ISD::FHADD;
14199 case Intrinsic::x86_sse3_hsub_ps:
14200 case Intrinsic::x86_sse3_hsub_pd:
14201 case Intrinsic::x86_avx_hsub_ps_256:
14202 case Intrinsic::x86_avx_hsub_pd_256:
14203 Opcode = X86ISD::FHSUB;
14205 case Intrinsic::x86_ssse3_phadd_w_128:
14206 case Intrinsic::x86_ssse3_phadd_d_128:
14207 case Intrinsic::x86_avx2_phadd_w:
14208 case Intrinsic::x86_avx2_phadd_d:
14209 Opcode = X86ISD::HADD;
14211 case Intrinsic::x86_ssse3_phsub_w_128:
14212 case Intrinsic::x86_ssse3_phsub_d_128:
14213 case Intrinsic::x86_avx2_phsub_w:
14214 case Intrinsic::x86_avx2_phsub_d:
14215 Opcode = X86ISD::HSUB;
14218 return DAG.getNode(Opcode, dl, Op.getValueType(),
14219 Op.getOperand(1), Op.getOperand(2));
14222 // SSE2/SSE41/AVX2 integer max/min intrinsics.
14223 case Intrinsic::x86_sse2_pmaxu_b:
14224 case Intrinsic::x86_sse41_pmaxuw:
14225 case Intrinsic::x86_sse41_pmaxud:
14226 case Intrinsic::x86_avx2_pmaxu_b:
14227 case Intrinsic::x86_avx2_pmaxu_w:
14228 case Intrinsic::x86_avx2_pmaxu_d:
14229 case Intrinsic::x86_sse2_pminu_b:
14230 case Intrinsic::x86_sse41_pminuw:
14231 case Intrinsic::x86_sse41_pminud:
14232 case Intrinsic::x86_avx2_pminu_b:
14233 case Intrinsic::x86_avx2_pminu_w:
14234 case Intrinsic::x86_avx2_pminu_d:
14235 case Intrinsic::x86_sse41_pmaxsb:
14236 case Intrinsic::x86_sse2_pmaxs_w:
14237 case Intrinsic::x86_sse41_pmaxsd:
14238 case Intrinsic::x86_avx2_pmaxs_b:
14239 case Intrinsic::x86_avx2_pmaxs_w:
14240 case Intrinsic::x86_avx2_pmaxs_d:
14241 case Intrinsic::x86_sse41_pminsb:
14242 case Intrinsic::x86_sse2_pmins_w:
14243 case Intrinsic::x86_sse41_pminsd:
14244 case Intrinsic::x86_avx2_pmins_b:
14245 case Intrinsic::x86_avx2_pmins_w:
14246 case Intrinsic::x86_avx2_pmins_d: {
14249 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14250 case Intrinsic::x86_sse2_pmaxu_b:
14251 case Intrinsic::x86_sse41_pmaxuw:
14252 case Intrinsic::x86_sse41_pmaxud:
14253 case Intrinsic::x86_avx2_pmaxu_b:
14254 case Intrinsic::x86_avx2_pmaxu_w:
14255 case Intrinsic::x86_avx2_pmaxu_d:
14256 Opcode = X86ISD::UMAX;
14258 case Intrinsic::x86_sse2_pminu_b:
14259 case Intrinsic::x86_sse41_pminuw:
14260 case Intrinsic::x86_sse41_pminud:
14261 case Intrinsic::x86_avx2_pminu_b:
14262 case Intrinsic::x86_avx2_pminu_w:
14263 case Intrinsic::x86_avx2_pminu_d:
14264 Opcode = X86ISD::UMIN;
14266 case Intrinsic::x86_sse41_pmaxsb:
14267 case Intrinsic::x86_sse2_pmaxs_w:
14268 case Intrinsic::x86_sse41_pmaxsd:
14269 case Intrinsic::x86_avx2_pmaxs_b:
14270 case Intrinsic::x86_avx2_pmaxs_w:
14271 case Intrinsic::x86_avx2_pmaxs_d:
14272 Opcode = X86ISD::SMAX;
14274 case Intrinsic::x86_sse41_pminsb:
14275 case Intrinsic::x86_sse2_pmins_w:
14276 case Intrinsic::x86_sse41_pminsd:
14277 case Intrinsic::x86_avx2_pmins_b:
14278 case Intrinsic::x86_avx2_pmins_w:
14279 case Intrinsic::x86_avx2_pmins_d:
14280 Opcode = X86ISD::SMIN;
14283 return DAG.getNode(Opcode, dl, Op.getValueType(),
14284 Op.getOperand(1), Op.getOperand(2));
14287 // SSE/SSE2/AVX floating point max/min intrinsics.
14288 case Intrinsic::x86_sse_max_ps:
14289 case Intrinsic::x86_sse2_max_pd:
14290 case Intrinsic::x86_avx_max_ps_256:
14291 case Intrinsic::x86_avx_max_pd_256:
14292 case Intrinsic::x86_sse_min_ps:
14293 case Intrinsic::x86_sse2_min_pd:
14294 case Intrinsic::x86_avx_min_ps_256:
14295 case Intrinsic::x86_avx_min_pd_256: {
14298 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14299 case Intrinsic::x86_sse_max_ps:
14300 case Intrinsic::x86_sse2_max_pd:
14301 case Intrinsic::x86_avx_max_ps_256:
14302 case Intrinsic::x86_avx_max_pd_256:
14303 Opcode = X86ISD::FMAX;
14305 case Intrinsic::x86_sse_min_ps:
14306 case Intrinsic::x86_sse2_min_pd:
14307 case Intrinsic::x86_avx_min_ps_256:
14308 case Intrinsic::x86_avx_min_pd_256:
14309 Opcode = X86ISD::FMIN;
14312 return DAG.getNode(Opcode, dl, Op.getValueType(),
14313 Op.getOperand(1), Op.getOperand(2));
14316 // AVX2 variable shift intrinsics
14317 case Intrinsic::x86_avx2_psllv_d:
14318 case Intrinsic::x86_avx2_psllv_q:
14319 case Intrinsic::x86_avx2_psllv_d_256:
14320 case Intrinsic::x86_avx2_psllv_q_256:
14321 case Intrinsic::x86_avx2_psrlv_d:
14322 case Intrinsic::x86_avx2_psrlv_q:
14323 case Intrinsic::x86_avx2_psrlv_d_256:
14324 case Intrinsic::x86_avx2_psrlv_q_256:
14325 case Intrinsic::x86_avx2_psrav_d:
14326 case Intrinsic::x86_avx2_psrav_d_256: {
14329 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14330 case Intrinsic::x86_avx2_psllv_d:
14331 case Intrinsic::x86_avx2_psllv_q:
14332 case Intrinsic::x86_avx2_psllv_d_256:
14333 case Intrinsic::x86_avx2_psllv_q_256:
14336 case Intrinsic::x86_avx2_psrlv_d:
14337 case Intrinsic::x86_avx2_psrlv_q:
14338 case Intrinsic::x86_avx2_psrlv_d_256:
14339 case Intrinsic::x86_avx2_psrlv_q_256:
14342 case Intrinsic::x86_avx2_psrav_d:
14343 case Intrinsic::x86_avx2_psrav_d_256:
14347 return DAG.getNode(Opcode, dl, Op.getValueType(),
14348 Op.getOperand(1), Op.getOperand(2));
14351 case Intrinsic::x86_sse2_packssdw_128:
14352 case Intrinsic::x86_sse2_packsswb_128:
14353 case Intrinsic::x86_avx2_packssdw:
14354 case Intrinsic::x86_avx2_packsswb:
14355 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14356 Op.getOperand(1), Op.getOperand(2));
14358 case Intrinsic::x86_sse2_packuswb_128:
14359 case Intrinsic::x86_sse41_packusdw:
14360 case Intrinsic::x86_avx2_packuswb:
14361 case Intrinsic::x86_avx2_packusdw:
14362 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14363 Op.getOperand(1), Op.getOperand(2));
14365 case Intrinsic::x86_ssse3_pshuf_b_128:
14366 case Intrinsic::x86_avx2_pshuf_b:
14367 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14368 Op.getOperand(1), Op.getOperand(2));
14370 case Intrinsic::x86_sse2_pshuf_d:
14371 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14372 Op.getOperand(1), Op.getOperand(2));
14374 case Intrinsic::x86_sse2_pshufl_w:
14375 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14376 Op.getOperand(1), Op.getOperand(2));
14378 case Intrinsic::x86_sse2_pshufh_w:
14379 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14380 Op.getOperand(1), Op.getOperand(2));
14382 case Intrinsic::x86_ssse3_psign_b_128:
14383 case Intrinsic::x86_ssse3_psign_w_128:
14384 case Intrinsic::x86_ssse3_psign_d_128:
14385 case Intrinsic::x86_avx2_psign_b:
14386 case Intrinsic::x86_avx2_psign_w:
14387 case Intrinsic::x86_avx2_psign_d:
14388 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14389 Op.getOperand(1), Op.getOperand(2));
14391 case Intrinsic::x86_sse41_insertps:
14392 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
14393 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14395 case Intrinsic::x86_avx_vperm2f128_ps_256:
14396 case Intrinsic::x86_avx_vperm2f128_pd_256:
14397 case Intrinsic::x86_avx_vperm2f128_si_256:
14398 case Intrinsic::x86_avx2_vperm2i128:
14399 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
14400 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14402 case Intrinsic::x86_avx2_permd:
14403 case Intrinsic::x86_avx2_permps:
14404 // Operands intentionally swapped. Mask is last operand to intrinsic,
14405 // but second operand for node/instruction.
14406 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14407 Op.getOperand(2), Op.getOperand(1));
14409 case Intrinsic::x86_sse_sqrt_ps:
14410 case Intrinsic::x86_sse2_sqrt_pd:
14411 case Intrinsic::x86_avx_sqrt_ps_256:
14412 case Intrinsic::x86_avx_sqrt_pd_256:
14413 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
14415 // ptest and testp intrinsics. The intrinsic these come from are designed to
14416 // return an integer value, not just an instruction so lower it to the ptest
14417 // or testp pattern and a setcc for the result.
14418 case Intrinsic::x86_sse41_ptestz:
14419 case Intrinsic::x86_sse41_ptestc:
14420 case Intrinsic::x86_sse41_ptestnzc:
14421 case Intrinsic::x86_avx_ptestz_256:
14422 case Intrinsic::x86_avx_ptestc_256:
14423 case Intrinsic::x86_avx_ptestnzc_256:
14424 case Intrinsic::x86_avx_vtestz_ps:
14425 case Intrinsic::x86_avx_vtestc_ps:
14426 case Intrinsic::x86_avx_vtestnzc_ps:
14427 case Intrinsic::x86_avx_vtestz_pd:
14428 case Intrinsic::x86_avx_vtestc_pd:
14429 case Intrinsic::x86_avx_vtestnzc_pd:
14430 case Intrinsic::x86_avx_vtestz_ps_256:
14431 case Intrinsic::x86_avx_vtestc_ps_256:
14432 case Intrinsic::x86_avx_vtestnzc_ps_256:
14433 case Intrinsic::x86_avx_vtestz_pd_256:
14434 case Intrinsic::x86_avx_vtestc_pd_256:
14435 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14436 bool IsTestPacked = false;
14439 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14440 case Intrinsic::x86_avx_vtestz_ps:
14441 case Intrinsic::x86_avx_vtestz_pd:
14442 case Intrinsic::x86_avx_vtestz_ps_256:
14443 case Intrinsic::x86_avx_vtestz_pd_256:
14444 IsTestPacked = true; // Fallthrough
14445 case Intrinsic::x86_sse41_ptestz:
14446 case Intrinsic::x86_avx_ptestz_256:
14448 X86CC = X86::COND_E;
14450 case Intrinsic::x86_avx_vtestc_ps:
14451 case Intrinsic::x86_avx_vtestc_pd:
14452 case Intrinsic::x86_avx_vtestc_ps_256:
14453 case Intrinsic::x86_avx_vtestc_pd_256:
14454 IsTestPacked = true; // Fallthrough
14455 case Intrinsic::x86_sse41_ptestc:
14456 case Intrinsic::x86_avx_ptestc_256:
14458 X86CC = X86::COND_B;
14460 case Intrinsic::x86_avx_vtestnzc_ps:
14461 case Intrinsic::x86_avx_vtestnzc_pd:
14462 case Intrinsic::x86_avx_vtestnzc_ps_256:
14463 case Intrinsic::x86_avx_vtestnzc_pd_256:
14464 IsTestPacked = true; // Fallthrough
14465 case Intrinsic::x86_sse41_ptestnzc:
14466 case Intrinsic::x86_avx_ptestnzc_256:
14468 X86CC = X86::COND_A;
14472 SDValue LHS = Op.getOperand(1);
14473 SDValue RHS = Op.getOperand(2);
14474 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14475 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14476 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14477 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14478 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14480 case Intrinsic::x86_avx512_kortestz_w:
14481 case Intrinsic::x86_avx512_kortestc_w: {
14482 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14483 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14484 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14485 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14486 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14487 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14488 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14491 // SSE/AVX shift intrinsics
14492 case Intrinsic::x86_sse2_psll_w:
14493 case Intrinsic::x86_sse2_psll_d:
14494 case Intrinsic::x86_sse2_psll_q:
14495 case Intrinsic::x86_avx2_psll_w:
14496 case Intrinsic::x86_avx2_psll_d:
14497 case Intrinsic::x86_avx2_psll_q:
14498 case Intrinsic::x86_sse2_psrl_w:
14499 case Intrinsic::x86_sse2_psrl_d:
14500 case Intrinsic::x86_sse2_psrl_q:
14501 case Intrinsic::x86_avx2_psrl_w:
14502 case Intrinsic::x86_avx2_psrl_d:
14503 case Intrinsic::x86_avx2_psrl_q:
14504 case Intrinsic::x86_sse2_psra_w:
14505 case Intrinsic::x86_sse2_psra_d:
14506 case Intrinsic::x86_avx2_psra_w:
14507 case Intrinsic::x86_avx2_psra_d: {
14510 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14511 case Intrinsic::x86_sse2_psll_w:
14512 case Intrinsic::x86_sse2_psll_d:
14513 case Intrinsic::x86_sse2_psll_q:
14514 case Intrinsic::x86_avx2_psll_w:
14515 case Intrinsic::x86_avx2_psll_d:
14516 case Intrinsic::x86_avx2_psll_q:
14517 Opcode = X86ISD::VSHL;
14519 case Intrinsic::x86_sse2_psrl_w:
14520 case Intrinsic::x86_sse2_psrl_d:
14521 case Intrinsic::x86_sse2_psrl_q:
14522 case Intrinsic::x86_avx2_psrl_w:
14523 case Intrinsic::x86_avx2_psrl_d:
14524 case Intrinsic::x86_avx2_psrl_q:
14525 Opcode = X86ISD::VSRL;
14527 case Intrinsic::x86_sse2_psra_w:
14528 case Intrinsic::x86_sse2_psra_d:
14529 case Intrinsic::x86_avx2_psra_w:
14530 case Intrinsic::x86_avx2_psra_d:
14531 Opcode = X86ISD::VSRA;
14534 return DAG.getNode(Opcode, dl, Op.getValueType(),
14535 Op.getOperand(1), Op.getOperand(2));
14538 // SSE/AVX immediate shift intrinsics
14539 case Intrinsic::x86_sse2_pslli_w:
14540 case Intrinsic::x86_sse2_pslli_d:
14541 case Intrinsic::x86_sse2_pslli_q:
14542 case Intrinsic::x86_avx2_pslli_w:
14543 case Intrinsic::x86_avx2_pslli_d:
14544 case Intrinsic::x86_avx2_pslli_q:
14545 case Intrinsic::x86_sse2_psrli_w:
14546 case Intrinsic::x86_sse2_psrli_d:
14547 case Intrinsic::x86_sse2_psrli_q:
14548 case Intrinsic::x86_avx2_psrli_w:
14549 case Intrinsic::x86_avx2_psrli_d:
14550 case Intrinsic::x86_avx2_psrli_q:
14551 case Intrinsic::x86_sse2_psrai_w:
14552 case Intrinsic::x86_sse2_psrai_d:
14553 case Intrinsic::x86_avx2_psrai_w:
14554 case Intrinsic::x86_avx2_psrai_d: {
14557 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14558 case Intrinsic::x86_sse2_pslli_w:
14559 case Intrinsic::x86_sse2_pslli_d:
14560 case Intrinsic::x86_sse2_pslli_q:
14561 case Intrinsic::x86_avx2_pslli_w:
14562 case Intrinsic::x86_avx2_pslli_d:
14563 case Intrinsic::x86_avx2_pslli_q:
14564 Opcode = X86ISD::VSHLI;
14566 case Intrinsic::x86_sse2_psrli_w:
14567 case Intrinsic::x86_sse2_psrli_d:
14568 case Intrinsic::x86_sse2_psrli_q:
14569 case Intrinsic::x86_avx2_psrli_w:
14570 case Intrinsic::x86_avx2_psrli_d:
14571 case Intrinsic::x86_avx2_psrli_q:
14572 Opcode = X86ISD::VSRLI;
14574 case Intrinsic::x86_sse2_psrai_w:
14575 case Intrinsic::x86_sse2_psrai_d:
14576 case Intrinsic::x86_avx2_psrai_w:
14577 case Intrinsic::x86_avx2_psrai_d:
14578 Opcode = X86ISD::VSRAI;
14581 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
14582 Op.getOperand(1), Op.getOperand(2), DAG);
14585 case Intrinsic::x86_sse42_pcmpistria128:
14586 case Intrinsic::x86_sse42_pcmpestria128:
14587 case Intrinsic::x86_sse42_pcmpistric128:
14588 case Intrinsic::x86_sse42_pcmpestric128:
14589 case Intrinsic::x86_sse42_pcmpistrio128:
14590 case Intrinsic::x86_sse42_pcmpestrio128:
14591 case Intrinsic::x86_sse42_pcmpistris128:
14592 case Intrinsic::x86_sse42_pcmpestris128:
14593 case Intrinsic::x86_sse42_pcmpistriz128:
14594 case Intrinsic::x86_sse42_pcmpestriz128: {
14598 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14599 case Intrinsic::x86_sse42_pcmpistria128:
14600 Opcode = X86ISD::PCMPISTRI;
14601 X86CC = X86::COND_A;
14603 case Intrinsic::x86_sse42_pcmpestria128:
14604 Opcode = X86ISD::PCMPESTRI;
14605 X86CC = X86::COND_A;
14607 case Intrinsic::x86_sse42_pcmpistric128:
14608 Opcode = X86ISD::PCMPISTRI;
14609 X86CC = X86::COND_B;
14611 case Intrinsic::x86_sse42_pcmpestric128:
14612 Opcode = X86ISD::PCMPESTRI;
14613 X86CC = X86::COND_B;
14615 case Intrinsic::x86_sse42_pcmpistrio128:
14616 Opcode = X86ISD::PCMPISTRI;
14617 X86CC = X86::COND_O;
14619 case Intrinsic::x86_sse42_pcmpestrio128:
14620 Opcode = X86ISD::PCMPESTRI;
14621 X86CC = X86::COND_O;
14623 case Intrinsic::x86_sse42_pcmpistris128:
14624 Opcode = X86ISD::PCMPISTRI;
14625 X86CC = X86::COND_S;
14627 case Intrinsic::x86_sse42_pcmpestris128:
14628 Opcode = X86ISD::PCMPESTRI;
14629 X86CC = X86::COND_S;
14631 case Intrinsic::x86_sse42_pcmpistriz128:
14632 Opcode = X86ISD::PCMPISTRI;
14633 X86CC = X86::COND_E;
14635 case Intrinsic::x86_sse42_pcmpestriz128:
14636 Opcode = X86ISD::PCMPESTRI;
14637 X86CC = X86::COND_E;
14640 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14641 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14642 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14643 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14644 DAG.getConstant(X86CC, MVT::i8),
14645 SDValue(PCMP.getNode(), 1));
14646 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14649 case Intrinsic::x86_sse42_pcmpistri128:
14650 case Intrinsic::x86_sse42_pcmpestri128: {
14652 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14653 Opcode = X86ISD::PCMPISTRI;
14655 Opcode = X86ISD::PCMPESTRI;
14657 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14658 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14659 return DAG.getNode(Opcode, dl, VTs, NewOps);
14661 case Intrinsic::x86_fma_vfmadd_ps:
14662 case Intrinsic::x86_fma_vfmadd_pd:
14663 case Intrinsic::x86_fma_vfmsub_ps:
14664 case Intrinsic::x86_fma_vfmsub_pd:
14665 case Intrinsic::x86_fma_vfnmadd_ps:
14666 case Intrinsic::x86_fma_vfnmadd_pd:
14667 case Intrinsic::x86_fma_vfnmsub_ps:
14668 case Intrinsic::x86_fma_vfnmsub_pd:
14669 case Intrinsic::x86_fma_vfmaddsub_ps:
14670 case Intrinsic::x86_fma_vfmaddsub_pd:
14671 case Intrinsic::x86_fma_vfmsubadd_ps:
14672 case Intrinsic::x86_fma_vfmsubadd_pd:
14673 case Intrinsic::x86_fma_vfmadd_ps_256:
14674 case Intrinsic::x86_fma_vfmadd_pd_256:
14675 case Intrinsic::x86_fma_vfmsub_ps_256:
14676 case Intrinsic::x86_fma_vfmsub_pd_256:
14677 case Intrinsic::x86_fma_vfnmadd_ps_256:
14678 case Intrinsic::x86_fma_vfnmadd_pd_256:
14679 case Intrinsic::x86_fma_vfnmsub_ps_256:
14680 case Intrinsic::x86_fma_vfnmsub_pd_256:
14681 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14682 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14683 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14684 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14685 case Intrinsic::x86_fma_vfmadd_ps_512:
14686 case Intrinsic::x86_fma_vfmadd_pd_512:
14687 case Intrinsic::x86_fma_vfmsub_ps_512:
14688 case Intrinsic::x86_fma_vfmsub_pd_512:
14689 case Intrinsic::x86_fma_vfnmadd_ps_512:
14690 case Intrinsic::x86_fma_vfnmadd_pd_512:
14691 case Intrinsic::x86_fma_vfnmsub_ps_512:
14692 case Intrinsic::x86_fma_vfnmsub_pd_512:
14693 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14694 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14695 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14696 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
14699 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14700 case Intrinsic::x86_fma_vfmadd_ps:
14701 case Intrinsic::x86_fma_vfmadd_pd:
14702 case Intrinsic::x86_fma_vfmadd_ps_256:
14703 case Intrinsic::x86_fma_vfmadd_pd_256:
14704 case Intrinsic::x86_fma_vfmadd_ps_512:
14705 case Intrinsic::x86_fma_vfmadd_pd_512:
14706 Opc = X86ISD::FMADD;
14708 case Intrinsic::x86_fma_vfmsub_ps:
14709 case Intrinsic::x86_fma_vfmsub_pd:
14710 case Intrinsic::x86_fma_vfmsub_ps_256:
14711 case Intrinsic::x86_fma_vfmsub_pd_256:
14712 case Intrinsic::x86_fma_vfmsub_ps_512:
14713 case Intrinsic::x86_fma_vfmsub_pd_512:
14714 Opc = X86ISD::FMSUB;
14716 case Intrinsic::x86_fma_vfnmadd_ps:
14717 case Intrinsic::x86_fma_vfnmadd_pd:
14718 case Intrinsic::x86_fma_vfnmadd_ps_256:
14719 case Intrinsic::x86_fma_vfnmadd_pd_256:
14720 case Intrinsic::x86_fma_vfnmadd_ps_512:
14721 case Intrinsic::x86_fma_vfnmadd_pd_512:
14722 Opc = X86ISD::FNMADD;
14724 case Intrinsic::x86_fma_vfnmsub_ps:
14725 case Intrinsic::x86_fma_vfnmsub_pd:
14726 case Intrinsic::x86_fma_vfnmsub_ps_256:
14727 case Intrinsic::x86_fma_vfnmsub_pd_256:
14728 case Intrinsic::x86_fma_vfnmsub_ps_512:
14729 case Intrinsic::x86_fma_vfnmsub_pd_512:
14730 Opc = X86ISD::FNMSUB;
14732 case Intrinsic::x86_fma_vfmaddsub_ps:
14733 case Intrinsic::x86_fma_vfmaddsub_pd:
14734 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14735 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14736 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14737 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14738 Opc = X86ISD::FMADDSUB;
14740 case Intrinsic::x86_fma_vfmsubadd_ps:
14741 case Intrinsic::x86_fma_vfmsubadd_pd:
14742 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14743 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14744 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14745 case Intrinsic::x86_fma_vfmsubadd_pd_512:
14746 Opc = X86ISD::FMSUBADD;
14750 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
14751 Op.getOperand(2), Op.getOperand(3));
14756 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14757 SDValue Src, SDValue Mask, SDValue Base,
14758 SDValue Index, SDValue ScaleOp, SDValue Chain,
14759 const X86Subtarget * Subtarget) {
14761 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14762 assert(C && "Invalid scale type");
14763 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14764 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14765 Index.getSimpleValueType().getVectorNumElements());
14767 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14769 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14771 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14772 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14773 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14774 SDValue Segment = DAG.getRegister(0, MVT::i32);
14775 if (Src.getOpcode() == ISD::UNDEF)
14776 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14777 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14778 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14779 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14780 return DAG.getMergeValues(RetOps, dl);
14783 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14784 SDValue Src, SDValue Mask, SDValue Base,
14785 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14788 assert(C && "Invalid scale type");
14789 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14790 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14791 SDValue Segment = DAG.getRegister(0, MVT::i32);
14792 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14793 Index.getSimpleValueType().getVectorNumElements());
14795 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14797 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14799 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14800 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14801 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14802 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14803 return SDValue(Res, 1);
14806 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14807 SDValue Mask, SDValue Base, SDValue Index,
14808 SDValue ScaleOp, SDValue Chain) {
14810 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14811 assert(C && "Invalid scale type");
14812 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14813 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14814 SDValue Segment = DAG.getRegister(0, MVT::i32);
14816 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14818 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14820 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14822 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14823 //SDVTList VTs = DAG.getVTList(MVT::Other);
14824 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14825 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14826 return SDValue(Res, 0);
14829 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14830 // read performance monitor counters (x86_rdpmc).
14831 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14832 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14833 SmallVectorImpl<SDValue> &Results) {
14834 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14835 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14838 // The ECX register is used to select the index of the performance counter
14840 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14842 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14844 // Reads the content of a 64-bit performance counter and returns it in the
14845 // registers EDX:EAX.
14846 if (Subtarget->is64Bit()) {
14847 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14848 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14851 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14852 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14855 Chain = HI.getValue(1);
14857 if (Subtarget->is64Bit()) {
14858 // The EAX register is loaded with the low-order 32 bits. The EDX register
14859 // is loaded with the supported high-order bits of the counter.
14860 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14861 DAG.getConstant(32, MVT::i8));
14862 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14863 Results.push_back(Chain);
14867 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14868 SDValue Ops[] = { LO, HI };
14869 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14870 Results.push_back(Pair);
14871 Results.push_back(Chain);
14874 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14875 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14876 // also used to custom lower READCYCLECOUNTER nodes.
14877 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14878 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14879 SmallVectorImpl<SDValue> &Results) {
14880 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14881 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14884 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14885 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14886 // and the EAX register is loaded with the low-order 32 bits.
14887 if (Subtarget->is64Bit()) {
14888 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14889 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14892 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14893 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14896 SDValue Chain = HI.getValue(1);
14898 if (Opcode == X86ISD::RDTSCP_DAG) {
14899 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14901 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14902 // the ECX register. Add 'ecx' explicitly to the chain.
14903 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14905 // Explicitly store the content of ECX at the location passed in input
14906 // to the 'rdtscp' intrinsic.
14907 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14908 MachinePointerInfo(), false, false, 0);
14911 if (Subtarget->is64Bit()) {
14912 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14913 // the EAX register is loaded with the low-order 32 bits.
14914 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14915 DAG.getConstant(32, MVT::i8));
14916 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14917 Results.push_back(Chain);
14921 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14922 SDValue Ops[] = { LO, HI };
14923 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14924 Results.push_back(Pair);
14925 Results.push_back(Chain);
14928 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14929 SelectionDAG &DAG) {
14930 SmallVector<SDValue, 2> Results;
14932 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14934 return DAG.getMergeValues(Results, DL);
14937 enum IntrinsicType {
14938 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
14941 struct IntrinsicData {
14942 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
14943 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
14944 IntrinsicType Type;
14949 std::map < unsigned, IntrinsicData> IntrMap;
14950 static void InitIntinsicsMap() {
14951 static bool Initialized = false;
14954 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14955 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14956 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14957 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14958 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
14959 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
14960 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
14961 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
14962 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
14963 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
14964 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
14965 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
14966 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
14967 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
14968 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
14969 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
14970 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
14971 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
14973 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
14974 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
14975 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
14976 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
14977 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
14978 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
14979 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
14980 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
14981 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
14982 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
14983 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
14984 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
14985 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
14986 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
14987 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
14988 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
14990 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
14991 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
14992 X86::VGATHERPF1QPSm)));
14993 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
14994 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
14995 X86::VGATHERPF1QPDm)));
14996 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
14997 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
14998 X86::VGATHERPF1DPDm)));
14999 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
15000 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
15001 X86::VGATHERPF1DPSm)));
15002 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
15003 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
15004 X86::VSCATTERPF1QPSm)));
15005 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
15006 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
15007 X86::VSCATTERPF1QPDm)));
15008 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
15009 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
15010 X86::VSCATTERPF1DPDm)));
15011 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
15012 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
15013 X86::VSCATTERPF1DPSm)));
15014 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
15015 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15016 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
15017 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15018 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
15019 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15020 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
15021 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15022 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
15023 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15024 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
15025 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15026 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
15027 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
15028 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
15029 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
15030 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
15031 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
15032 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
15033 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
15034 Initialized = true;
15037 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15038 SelectionDAG &DAG) {
15039 InitIntinsicsMap();
15040 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15041 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
15042 if (itr == IntrMap.end())
15046 IntrinsicData Intr = itr->second;
15047 switch(Intr.Type) {
15050 // Emit the node with the right value type.
15051 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15052 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
15054 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15055 // Otherwise return the value from Rand, which is always 0, casted to i32.
15056 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15057 DAG.getConstant(1, Op->getValueType(1)),
15058 DAG.getConstant(X86::COND_B, MVT::i32),
15059 SDValue(Result.getNode(), 1) };
15060 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15061 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15064 // Return { result, isValid, chain }.
15065 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15066 SDValue(Result.getNode(), 2));
15069 //gather(v1, mask, index, base, scale);
15070 SDValue Chain = Op.getOperand(0);
15071 SDValue Src = Op.getOperand(2);
15072 SDValue Base = Op.getOperand(3);
15073 SDValue Index = Op.getOperand(4);
15074 SDValue Mask = Op.getOperand(5);
15075 SDValue Scale = Op.getOperand(6);
15076 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15080 //scatter(base, mask, index, v1, scale);
15081 SDValue Chain = Op.getOperand(0);
15082 SDValue Base = Op.getOperand(2);
15083 SDValue Mask = Op.getOperand(3);
15084 SDValue Index = Op.getOperand(4);
15085 SDValue Src = Op.getOperand(5);
15086 SDValue Scale = Op.getOperand(6);
15087 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15090 SDValue Hint = Op.getOperand(6);
15092 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15093 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15094 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15095 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
15096 SDValue Chain = Op.getOperand(0);
15097 SDValue Mask = Op.getOperand(2);
15098 SDValue Index = Op.getOperand(3);
15099 SDValue Base = Op.getOperand(4);
15100 SDValue Scale = Op.getOperand(5);
15101 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15103 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15105 SmallVector<SDValue, 2> Results;
15106 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
15107 return DAG.getMergeValues(Results, dl);
15109 // Read Performance Monitoring Counters.
15111 SmallVector<SDValue, 2> Results;
15112 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15113 return DAG.getMergeValues(Results, dl);
15115 // XTEST intrinsics.
15117 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15118 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
15119 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15120 DAG.getConstant(X86::COND_NE, MVT::i8),
15122 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15123 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15124 Ret, SDValue(InTrans.getNode(), 1));
15127 llvm_unreachable("Unknown Intrinsic Type");
15130 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15131 SelectionDAG &DAG) const {
15132 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15133 MFI->setReturnAddressIsTaken(true);
15135 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15138 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15140 EVT PtrVT = getPointerTy();
15143 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15144 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15145 DAG.getSubtarget().getRegisterInfo());
15146 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15147 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15148 DAG.getNode(ISD::ADD, dl, PtrVT,
15149 FrameAddr, Offset),
15150 MachinePointerInfo(), false, false, false, 0);
15153 // Just load the return address.
15154 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15155 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15156 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15159 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15160 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15161 MFI->setFrameAddressIsTaken(true);
15163 EVT VT = Op.getValueType();
15164 SDLoc dl(Op); // FIXME probably not meaningful
15165 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15166 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15167 DAG.getSubtarget().getRegisterInfo());
15168 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15169 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15170 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15171 "Invalid Frame Register!");
15172 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15174 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15175 MachinePointerInfo(),
15176 false, false, false, 0);
15180 // FIXME? Maybe this could be a TableGen attribute on some registers and
15181 // this table could be generated automatically from RegInfo.
15182 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15184 unsigned Reg = StringSwitch<unsigned>(RegName)
15185 .Case("esp", X86::ESP)
15186 .Case("rsp", X86::RSP)
15190 report_fatal_error("Invalid register name global variable");
15193 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15194 SelectionDAG &DAG) const {
15195 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15196 DAG.getSubtarget().getRegisterInfo());
15197 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15200 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15201 SDValue Chain = Op.getOperand(0);
15202 SDValue Offset = Op.getOperand(1);
15203 SDValue Handler = Op.getOperand(2);
15206 EVT PtrVT = getPointerTy();
15207 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15208 DAG.getSubtarget().getRegisterInfo());
15209 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15210 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15211 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15212 "Invalid Frame Register!");
15213 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15214 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15216 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15217 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15218 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15219 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15221 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15223 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15224 DAG.getRegister(StoreAddrReg, PtrVT));
15227 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15228 SelectionDAG &DAG) const {
15230 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15231 DAG.getVTList(MVT::i32, MVT::Other),
15232 Op.getOperand(0), Op.getOperand(1));
15235 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15236 SelectionDAG &DAG) const {
15238 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15239 Op.getOperand(0), Op.getOperand(1));
15242 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15243 return Op.getOperand(0);
15246 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15247 SelectionDAG &DAG) const {
15248 SDValue Root = Op.getOperand(0);
15249 SDValue Trmp = Op.getOperand(1); // trampoline
15250 SDValue FPtr = Op.getOperand(2); // nested function
15251 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15254 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15255 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15257 if (Subtarget->is64Bit()) {
15258 SDValue OutChains[6];
15260 // Large code-model.
15261 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15262 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15264 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15265 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15267 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15269 // Load the pointer to the nested function into R11.
15270 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15271 SDValue Addr = Trmp;
15272 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15273 Addr, MachinePointerInfo(TrmpAddr),
15276 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15277 DAG.getConstant(2, MVT::i64));
15278 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15279 MachinePointerInfo(TrmpAddr, 2),
15282 // Load the 'nest' parameter value into R10.
15283 // R10 is specified in X86CallingConv.td
15284 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15285 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15286 DAG.getConstant(10, MVT::i64));
15287 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15288 Addr, MachinePointerInfo(TrmpAddr, 10),
15291 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15292 DAG.getConstant(12, MVT::i64));
15293 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15294 MachinePointerInfo(TrmpAddr, 12),
15297 // Jump to the nested function.
15298 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15299 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15300 DAG.getConstant(20, MVT::i64));
15301 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15302 Addr, MachinePointerInfo(TrmpAddr, 20),
15305 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15306 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15307 DAG.getConstant(22, MVT::i64));
15308 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15309 MachinePointerInfo(TrmpAddr, 22),
15312 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15314 const Function *Func =
15315 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15316 CallingConv::ID CC = Func->getCallingConv();
15321 llvm_unreachable("Unsupported calling convention");
15322 case CallingConv::C:
15323 case CallingConv::X86_StdCall: {
15324 // Pass 'nest' parameter in ECX.
15325 // Must be kept in sync with X86CallingConv.td
15326 NestReg = X86::ECX;
15328 // Check that ECX wasn't needed by an 'inreg' parameter.
15329 FunctionType *FTy = Func->getFunctionType();
15330 const AttributeSet &Attrs = Func->getAttributes();
15332 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15333 unsigned InRegCount = 0;
15336 for (FunctionType::param_iterator I = FTy->param_begin(),
15337 E = FTy->param_end(); I != E; ++I, ++Idx)
15338 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15339 // FIXME: should only count parameters that are lowered to integers.
15340 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15342 if (InRegCount > 2) {
15343 report_fatal_error("Nest register in use - reduce number of inreg"
15349 case CallingConv::X86_FastCall:
15350 case CallingConv::X86_ThisCall:
15351 case CallingConv::Fast:
15352 // Pass 'nest' parameter in EAX.
15353 // Must be kept in sync with X86CallingConv.td
15354 NestReg = X86::EAX;
15358 SDValue OutChains[4];
15359 SDValue Addr, Disp;
15361 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15362 DAG.getConstant(10, MVT::i32));
15363 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15365 // This is storing the opcode for MOV32ri.
15366 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15367 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15368 OutChains[0] = DAG.getStore(Root, dl,
15369 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15370 Trmp, MachinePointerInfo(TrmpAddr),
15373 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15374 DAG.getConstant(1, MVT::i32));
15375 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15376 MachinePointerInfo(TrmpAddr, 1),
15379 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15380 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15381 DAG.getConstant(5, MVT::i32));
15382 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15383 MachinePointerInfo(TrmpAddr, 5),
15386 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15387 DAG.getConstant(6, MVT::i32));
15388 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15389 MachinePointerInfo(TrmpAddr, 6),
15392 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15396 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15397 SelectionDAG &DAG) const {
15399 The rounding mode is in bits 11:10 of FPSR, and has the following
15401 00 Round to nearest
15406 FLT_ROUNDS, on the other hand, expects the following:
15413 To perform the conversion, we do:
15414 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15417 MachineFunction &MF = DAG.getMachineFunction();
15418 const TargetMachine &TM = MF.getTarget();
15419 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15420 unsigned StackAlignment = TFI.getStackAlignment();
15421 MVT VT = Op.getSimpleValueType();
15424 // Save FP Control Word to stack slot
15425 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15426 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15428 MachineMemOperand *MMO =
15429 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15430 MachineMemOperand::MOStore, 2, 2);
15432 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15433 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15434 DAG.getVTList(MVT::Other),
15435 Ops, MVT::i16, MMO);
15437 // Load FP Control Word from stack slot
15438 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15439 MachinePointerInfo(), false, false, false, 0);
15441 // Transform as necessary
15443 DAG.getNode(ISD::SRL, DL, MVT::i16,
15444 DAG.getNode(ISD::AND, DL, MVT::i16,
15445 CWD, DAG.getConstant(0x800, MVT::i16)),
15446 DAG.getConstant(11, MVT::i8));
15448 DAG.getNode(ISD::SRL, DL, MVT::i16,
15449 DAG.getNode(ISD::AND, DL, MVT::i16,
15450 CWD, DAG.getConstant(0x400, MVT::i16)),
15451 DAG.getConstant(9, MVT::i8));
15454 DAG.getNode(ISD::AND, DL, MVT::i16,
15455 DAG.getNode(ISD::ADD, DL, MVT::i16,
15456 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15457 DAG.getConstant(1, MVT::i16)),
15458 DAG.getConstant(3, MVT::i16));
15460 return DAG.getNode((VT.getSizeInBits() < 16 ?
15461 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15464 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15465 MVT VT = Op.getSimpleValueType();
15467 unsigned NumBits = VT.getSizeInBits();
15470 Op = Op.getOperand(0);
15471 if (VT == MVT::i8) {
15472 // Zero extend to i32 since there is not an i8 bsr.
15474 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15477 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15478 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15479 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15481 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15484 DAG.getConstant(NumBits+NumBits-1, OpVT),
15485 DAG.getConstant(X86::COND_E, MVT::i8),
15488 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15490 // Finally xor with NumBits-1.
15491 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15494 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15498 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15499 MVT VT = Op.getSimpleValueType();
15501 unsigned NumBits = VT.getSizeInBits();
15504 Op = Op.getOperand(0);
15505 if (VT == MVT::i8) {
15506 // Zero extend to i32 since there is not an i8 bsr.
15508 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15511 // Issue a bsr (scan bits in reverse).
15512 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15513 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15515 // And xor with NumBits-1.
15516 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15519 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15523 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15524 MVT VT = Op.getSimpleValueType();
15525 unsigned NumBits = VT.getSizeInBits();
15527 Op = Op.getOperand(0);
15529 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15530 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15531 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15533 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15536 DAG.getConstant(NumBits, VT),
15537 DAG.getConstant(X86::COND_E, MVT::i8),
15540 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15543 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15544 // ones, and then concatenate the result back.
15545 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15546 MVT VT = Op.getSimpleValueType();
15548 assert(VT.is256BitVector() && VT.isInteger() &&
15549 "Unsupported value type for operation");
15551 unsigned NumElems = VT.getVectorNumElements();
15554 // Extract the LHS vectors
15555 SDValue LHS = Op.getOperand(0);
15556 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15557 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15559 // Extract the RHS vectors
15560 SDValue RHS = Op.getOperand(1);
15561 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15562 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15564 MVT EltVT = VT.getVectorElementType();
15565 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15567 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15568 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15569 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15572 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15573 assert(Op.getSimpleValueType().is256BitVector() &&
15574 Op.getSimpleValueType().isInteger() &&
15575 "Only handle AVX 256-bit vector integer operation");
15576 return Lower256IntArith(Op, DAG);
15579 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15580 assert(Op.getSimpleValueType().is256BitVector() &&
15581 Op.getSimpleValueType().isInteger() &&
15582 "Only handle AVX 256-bit vector integer operation");
15583 return Lower256IntArith(Op, DAG);
15586 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15587 SelectionDAG &DAG) {
15589 MVT VT = Op.getSimpleValueType();
15591 // Decompose 256-bit ops into smaller 128-bit ops.
15592 if (VT.is256BitVector() && !Subtarget->hasInt256())
15593 return Lower256IntArith(Op, DAG);
15595 SDValue A = Op.getOperand(0);
15596 SDValue B = Op.getOperand(1);
15598 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15599 if (VT == MVT::v4i32) {
15600 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15601 "Should not custom lower when pmuldq is available!");
15603 // Extract the odd parts.
15604 static const int UnpackMask[] = { 1, -1, 3, -1 };
15605 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15606 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15608 // Multiply the even parts.
15609 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15610 // Now multiply odd parts.
15611 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15613 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15614 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15616 // Merge the two vectors back together with a shuffle. This expands into 2
15618 static const int ShufMask[] = { 0, 4, 2, 6 };
15619 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15622 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15623 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15625 // Ahi = psrlqi(a, 32);
15626 // Bhi = psrlqi(b, 32);
15628 // AloBlo = pmuludq(a, b);
15629 // AloBhi = pmuludq(a, Bhi);
15630 // AhiBlo = pmuludq(Ahi, b);
15632 // AloBhi = psllqi(AloBhi, 32);
15633 // AhiBlo = psllqi(AhiBlo, 32);
15634 // return AloBlo + AloBhi + AhiBlo;
15636 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15637 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15639 // Bit cast to 32-bit vectors for MULUDQ
15640 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15641 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15642 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15643 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15644 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15645 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15647 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15648 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15649 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15651 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15652 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15654 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15655 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15658 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15659 assert(Subtarget->isTargetWin64() && "Unexpected target");
15660 EVT VT = Op.getValueType();
15661 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15662 "Unexpected return type for lowering");
15666 switch (Op->getOpcode()) {
15667 default: llvm_unreachable("Unexpected request for libcall!");
15668 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15669 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15670 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15671 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15672 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15673 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15677 SDValue InChain = DAG.getEntryNode();
15679 TargetLowering::ArgListTy Args;
15680 TargetLowering::ArgListEntry Entry;
15681 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15682 EVT ArgVT = Op->getOperand(i).getValueType();
15683 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15684 "Unexpected argument type for lowering");
15685 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15686 Entry.Node = StackPtr;
15687 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15689 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15690 Entry.Ty = PointerType::get(ArgTy,0);
15691 Entry.isSExt = false;
15692 Entry.isZExt = false;
15693 Args.push_back(Entry);
15696 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15699 TargetLowering::CallLoweringInfo CLI(DAG);
15700 CLI.setDebugLoc(dl).setChain(InChain)
15701 .setCallee(getLibcallCallingConv(LC),
15702 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15703 Callee, std::move(Args), 0)
15704 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15706 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15707 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15710 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15711 SelectionDAG &DAG) {
15712 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15713 EVT VT = Op0.getValueType();
15716 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15717 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15719 // PMULxD operations multiply each even value (starting at 0) of LHS with
15720 // the related value of RHS and produce a widen result.
15721 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15722 // => <2 x i64> <ae|cg>
15724 // In other word, to have all the results, we need to perform two PMULxD:
15725 // 1. one with the even values.
15726 // 2. one with the odd values.
15727 // To achieve #2, with need to place the odd values at an even position.
15729 // Place the odd value at an even position (basically, shift all values 1
15730 // step to the left):
15731 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15732 // <a|b|c|d> => <b|undef|d|undef>
15733 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15734 // <e|f|g|h> => <f|undef|h|undef>
15735 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15737 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15739 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15740 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15742 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15743 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15744 // => <2 x i64> <ae|cg>
15745 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15746 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15747 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15748 // => <2 x i64> <bf|dh>
15749 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15750 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15752 // Shuffle it back into the right order.
15753 SDValue Highs, Lows;
15754 if (VT == MVT::v8i32) {
15755 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15756 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15757 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15758 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15760 const int HighMask[] = {1, 5, 3, 7};
15761 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15762 const int LowMask[] = {1, 4, 2, 6};
15763 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15766 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15767 // unsigned multiply.
15768 if (IsSigned && !Subtarget->hasSSE41()) {
15770 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15771 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15772 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15773 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15774 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15776 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15777 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15780 // The first result of MUL_LOHI is actually the low value, followed by the
15782 SDValue Ops[] = {Lows, Highs};
15783 return DAG.getMergeValues(Ops, dl);
15786 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15787 const X86Subtarget *Subtarget) {
15788 MVT VT = Op.getSimpleValueType();
15790 SDValue R = Op.getOperand(0);
15791 SDValue Amt = Op.getOperand(1);
15793 // Optimize shl/srl/sra with constant shift amount.
15794 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15795 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15796 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15798 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15799 (Subtarget->hasInt256() &&
15800 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15801 (Subtarget->hasAVX512() &&
15802 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15803 if (Op.getOpcode() == ISD::SHL)
15804 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15806 if (Op.getOpcode() == ISD::SRL)
15807 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15809 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15810 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15814 if (VT == MVT::v16i8) {
15815 if (Op.getOpcode() == ISD::SHL) {
15816 // Make a large shift.
15817 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15818 MVT::v8i16, R, ShiftAmt,
15820 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15821 // Zero out the rightmost bits.
15822 SmallVector<SDValue, 16> V(16,
15823 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15825 return DAG.getNode(ISD::AND, dl, VT, SHL,
15826 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15828 if (Op.getOpcode() == ISD::SRL) {
15829 // Make a large shift.
15830 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15831 MVT::v8i16, R, ShiftAmt,
15833 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15834 // Zero out the leftmost bits.
15835 SmallVector<SDValue, 16> V(16,
15836 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15838 return DAG.getNode(ISD::AND, dl, VT, SRL,
15839 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15841 if (Op.getOpcode() == ISD::SRA) {
15842 if (ShiftAmt == 7) {
15843 // R s>> 7 === R s< 0
15844 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15845 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15848 // R s>> a === ((R u>> a) ^ m) - m
15849 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15850 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15852 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15853 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15854 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15857 llvm_unreachable("Unknown shift opcode.");
15860 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15861 if (Op.getOpcode() == ISD::SHL) {
15862 // Make a large shift.
15863 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15864 MVT::v16i16, R, ShiftAmt,
15866 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15867 // Zero out the rightmost bits.
15868 SmallVector<SDValue, 32> V(32,
15869 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15871 return DAG.getNode(ISD::AND, dl, VT, SHL,
15872 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15874 if (Op.getOpcode() == ISD::SRL) {
15875 // Make a large shift.
15876 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15877 MVT::v16i16, R, ShiftAmt,
15879 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15880 // Zero out the leftmost bits.
15881 SmallVector<SDValue, 32> V(32,
15882 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15884 return DAG.getNode(ISD::AND, dl, VT, SRL,
15885 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15887 if (Op.getOpcode() == ISD::SRA) {
15888 if (ShiftAmt == 7) {
15889 // R s>> 7 === R s< 0
15890 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15891 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15894 // R s>> a === ((R u>> a) ^ m) - m
15895 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15896 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
15898 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15899 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15900 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15903 llvm_unreachable("Unknown shift opcode.");
15908 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15909 if (!Subtarget->is64Bit() &&
15910 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15911 Amt.getOpcode() == ISD::BITCAST &&
15912 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15913 Amt = Amt.getOperand(0);
15914 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15915 VT.getVectorNumElements();
15916 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15917 uint64_t ShiftAmt = 0;
15918 for (unsigned i = 0; i != Ratio; ++i) {
15919 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15923 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15925 // Check remaining shift amounts.
15926 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15927 uint64_t ShAmt = 0;
15928 for (unsigned j = 0; j != Ratio; ++j) {
15929 ConstantSDNode *C =
15930 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15934 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15936 if (ShAmt != ShiftAmt)
15939 switch (Op.getOpcode()) {
15941 llvm_unreachable("Unknown shift opcode!");
15943 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15946 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15949 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15957 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15958 const X86Subtarget* Subtarget) {
15959 MVT VT = Op.getSimpleValueType();
15961 SDValue R = Op.getOperand(0);
15962 SDValue Amt = Op.getOperand(1);
15964 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15965 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15966 (Subtarget->hasInt256() &&
15967 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15968 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15969 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15971 EVT EltVT = VT.getVectorElementType();
15973 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15974 unsigned NumElts = VT.getVectorNumElements();
15976 for (i = 0; i != NumElts; ++i) {
15977 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
15981 for (j = i; j != NumElts; ++j) {
15982 SDValue Arg = Amt.getOperand(j);
15983 if (Arg.getOpcode() == ISD::UNDEF) continue;
15984 if (Arg != Amt.getOperand(i))
15987 if (i != NumElts && j == NumElts)
15988 BaseShAmt = Amt.getOperand(i);
15990 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15991 Amt = Amt.getOperand(0);
15992 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
15993 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
15994 SDValue InVec = Amt.getOperand(0);
15995 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15996 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15998 for (; i != NumElts; ++i) {
15999 SDValue Arg = InVec.getOperand(i);
16000 if (Arg.getOpcode() == ISD::UNDEF) continue;
16004 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16005 if (ConstantSDNode *C =
16006 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16007 unsigned SplatIdx =
16008 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16009 if (C->getZExtValue() == SplatIdx)
16010 BaseShAmt = InVec.getOperand(1);
16013 if (!BaseShAmt.getNode())
16014 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16015 DAG.getIntPtrConstant(0));
16019 if (BaseShAmt.getNode()) {
16020 if (EltVT.bitsGT(MVT::i32))
16021 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16022 else if (EltVT.bitsLT(MVT::i32))
16023 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16025 switch (Op.getOpcode()) {
16027 llvm_unreachable("Unknown shift opcode!");
16029 switch (VT.SimpleTy) {
16030 default: return SDValue();
16039 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16042 switch (VT.SimpleTy) {
16043 default: return SDValue();
16050 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16053 switch (VT.SimpleTy) {
16054 default: return SDValue();
16063 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16069 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16070 if (!Subtarget->is64Bit() &&
16071 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16072 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16073 Amt.getOpcode() == ISD::BITCAST &&
16074 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16075 Amt = Amt.getOperand(0);
16076 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16077 VT.getVectorNumElements();
16078 std::vector<SDValue> Vals(Ratio);
16079 for (unsigned i = 0; i != Ratio; ++i)
16080 Vals[i] = Amt.getOperand(i);
16081 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16082 for (unsigned j = 0; j != Ratio; ++j)
16083 if (Vals[j] != Amt.getOperand(i + j))
16086 switch (Op.getOpcode()) {
16088 llvm_unreachable("Unknown shift opcode!");
16090 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16092 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16094 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16101 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16102 SelectionDAG &DAG) {
16103 MVT VT = Op.getSimpleValueType();
16105 SDValue R = Op.getOperand(0);
16106 SDValue Amt = Op.getOperand(1);
16109 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16110 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16112 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16116 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16120 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16122 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16123 if (Subtarget->hasInt256()) {
16124 if (Op.getOpcode() == ISD::SRL &&
16125 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16126 VT == MVT::v4i64 || VT == MVT::v8i32))
16128 if (Op.getOpcode() == ISD::SHL &&
16129 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16130 VT == MVT::v4i64 || VT == MVT::v8i32))
16132 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16136 // If possible, lower this packed shift into a vector multiply instead of
16137 // expanding it into a sequence of scalar shifts.
16138 // Do this only if the vector shift count is a constant build_vector.
16139 if (Op.getOpcode() == ISD::SHL &&
16140 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16141 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16142 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16143 SmallVector<SDValue, 8> Elts;
16144 EVT SVT = VT.getScalarType();
16145 unsigned SVTBits = SVT.getSizeInBits();
16146 const APInt &One = APInt(SVTBits, 1);
16147 unsigned NumElems = VT.getVectorNumElements();
16149 for (unsigned i=0; i !=NumElems; ++i) {
16150 SDValue Op = Amt->getOperand(i);
16151 if (Op->getOpcode() == ISD::UNDEF) {
16152 Elts.push_back(Op);
16156 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16157 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16158 uint64_t ShAmt = C.getZExtValue();
16159 if (ShAmt >= SVTBits) {
16160 Elts.push_back(DAG.getUNDEF(SVT));
16163 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16165 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16166 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16169 // Lower SHL with variable shift amount.
16170 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16171 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16173 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16174 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16175 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16176 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16179 // If possible, lower this shift as a sequence of two shifts by
16180 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16182 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16184 // Could be rewritten as:
16185 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16187 // The advantage is that the two shifts from the example would be
16188 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16189 // the vector shift into four scalar shifts plus four pairs of vector
16191 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16192 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16193 unsigned TargetOpcode = X86ISD::MOVSS;
16194 bool CanBeSimplified;
16195 // The splat value for the first packed shift (the 'X' from the example).
16196 SDValue Amt1 = Amt->getOperand(0);
16197 // The splat value for the second packed shift (the 'Y' from the example).
16198 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16199 Amt->getOperand(2);
16201 // See if it is possible to replace this node with a sequence of
16202 // two shifts followed by a MOVSS/MOVSD
16203 if (VT == MVT::v4i32) {
16204 // Check if it is legal to use a MOVSS.
16205 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16206 Amt2 == Amt->getOperand(3);
16207 if (!CanBeSimplified) {
16208 // Otherwise, check if we can still simplify this node using a MOVSD.
16209 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16210 Amt->getOperand(2) == Amt->getOperand(3);
16211 TargetOpcode = X86ISD::MOVSD;
16212 Amt2 = Amt->getOperand(2);
16215 // Do similar checks for the case where the machine value type
16217 CanBeSimplified = Amt1 == Amt->getOperand(1);
16218 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16219 CanBeSimplified = Amt2 == Amt->getOperand(i);
16221 if (!CanBeSimplified) {
16222 TargetOpcode = X86ISD::MOVSD;
16223 CanBeSimplified = true;
16224 Amt2 = Amt->getOperand(4);
16225 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16226 CanBeSimplified = Amt1 == Amt->getOperand(i);
16227 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16228 CanBeSimplified = Amt2 == Amt->getOperand(j);
16232 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16233 isa<ConstantSDNode>(Amt2)) {
16234 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16235 EVT CastVT = MVT::v4i32;
16237 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16238 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16240 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16241 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16242 if (TargetOpcode == X86ISD::MOVSD)
16243 CastVT = MVT::v2i64;
16244 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16245 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16246 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16248 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16252 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16253 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16256 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16257 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16259 // Turn 'a' into a mask suitable for VSELECT
16260 SDValue VSelM = DAG.getConstant(0x80, VT);
16261 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16262 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16264 SDValue CM1 = DAG.getConstant(0x0f, VT);
16265 SDValue CM2 = DAG.getConstant(0x3f, VT);
16267 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16268 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16269 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16270 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16271 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16274 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16275 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16276 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16278 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16279 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16280 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16281 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16282 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16285 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16286 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16287 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16289 // return VSELECT(r, r+r, a);
16290 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16291 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16295 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16296 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16297 // solution better.
16298 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16299 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16301 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16302 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16303 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16304 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16305 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16308 // Decompose 256-bit shifts into smaller 128-bit shifts.
16309 if (VT.is256BitVector()) {
16310 unsigned NumElems = VT.getVectorNumElements();
16311 MVT EltVT = VT.getVectorElementType();
16312 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16314 // Extract the two vectors
16315 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16316 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16318 // Recreate the shift amount vectors
16319 SDValue Amt1, Amt2;
16320 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16321 // Constant shift amount
16322 SmallVector<SDValue, 4> Amt1Csts;
16323 SmallVector<SDValue, 4> Amt2Csts;
16324 for (unsigned i = 0; i != NumElems/2; ++i)
16325 Amt1Csts.push_back(Amt->getOperand(i));
16326 for (unsigned i = NumElems/2; i != NumElems; ++i)
16327 Amt2Csts.push_back(Amt->getOperand(i));
16329 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16330 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16332 // Variable shift amount
16333 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16334 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16337 // Issue new vector shifts for the smaller types
16338 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16339 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16341 // Concatenate the result back
16342 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16348 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16349 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16350 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16351 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16352 // has only one use.
16353 SDNode *N = Op.getNode();
16354 SDValue LHS = N->getOperand(0);
16355 SDValue RHS = N->getOperand(1);
16356 unsigned BaseOp = 0;
16359 switch (Op.getOpcode()) {
16360 default: llvm_unreachable("Unknown ovf instruction!");
16362 // A subtract of one will be selected as a INC. Note that INC doesn't
16363 // set CF, so we can't do this for UADDO.
16364 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16366 BaseOp = X86ISD::INC;
16367 Cond = X86::COND_O;
16370 BaseOp = X86ISD::ADD;
16371 Cond = X86::COND_O;
16374 BaseOp = X86ISD::ADD;
16375 Cond = X86::COND_B;
16378 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16379 // set CF, so we can't do this for USUBO.
16380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16382 BaseOp = X86ISD::DEC;
16383 Cond = X86::COND_O;
16386 BaseOp = X86ISD::SUB;
16387 Cond = X86::COND_O;
16390 BaseOp = X86ISD::SUB;
16391 Cond = X86::COND_B;
16394 BaseOp = X86ISD::SMUL;
16395 Cond = X86::COND_O;
16397 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16398 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16400 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16403 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16404 DAG.getConstant(X86::COND_O, MVT::i32),
16405 SDValue(Sum.getNode(), 2));
16407 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16411 // Also sets EFLAGS.
16412 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16413 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16416 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16417 DAG.getConstant(Cond, MVT::i32),
16418 SDValue(Sum.getNode(), 1));
16420 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16423 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16424 SelectionDAG &DAG) const {
16426 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16427 MVT VT = Op.getSimpleValueType();
16429 if (!Subtarget->hasSSE2() || !VT.isVector())
16432 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16433 ExtraVT.getScalarType().getSizeInBits();
16435 switch (VT.SimpleTy) {
16436 default: return SDValue();
16439 if (!Subtarget->hasFp256())
16441 if (!Subtarget->hasInt256()) {
16442 // needs to be split
16443 unsigned NumElems = VT.getVectorNumElements();
16445 // Extract the LHS vectors
16446 SDValue LHS = Op.getOperand(0);
16447 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16448 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16450 MVT EltVT = VT.getVectorElementType();
16451 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16453 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16454 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16455 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16457 SDValue Extra = DAG.getValueType(ExtraVT);
16459 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16460 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16462 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16467 SDValue Op0 = Op.getOperand(0);
16468 SDValue Op00 = Op0.getOperand(0);
16470 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
16471 if (Op0.getOpcode() == ISD::BITCAST &&
16472 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
16473 // (sext (vzext x)) -> (vsext x)
16474 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
16475 if (Tmp1.getNode()) {
16476 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16477 // This folding is only valid when the in-reg type is a vector of i8,
16479 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
16480 ExtraEltVT == MVT::i32) {
16481 SDValue Tmp1Op0 = Tmp1.getOperand(0);
16482 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
16483 "This optimization is invalid without a VZEXT.");
16484 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
16490 // If the above didn't work, then just use Shift-Left + Shift-Right.
16491 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
16493 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
16499 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16500 SelectionDAG &DAG) {
16502 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16503 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16504 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16505 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16507 // The only fence that needs an instruction is a sequentially-consistent
16508 // cross-thread fence.
16509 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16510 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16511 // no-sse2). There isn't any reason to disable it if the target processor
16513 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16514 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16516 SDValue Chain = Op.getOperand(0);
16517 SDValue Zero = DAG.getConstant(0, MVT::i32);
16519 DAG.getRegister(X86::ESP, MVT::i32), // Base
16520 DAG.getTargetConstant(1, MVT::i8), // Scale
16521 DAG.getRegister(0, MVT::i32), // Index
16522 DAG.getTargetConstant(0, MVT::i32), // Disp
16523 DAG.getRegister(0, MVT::i32), // Segment.
16527 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16528 return SDValue(Res, 0);
16531 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16532 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16535 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16536 SelectionDAG &DAG) {
16537 MVT T = Op.getSimpleValueType();
16541 switch(T.SimpleTy) {
16542 default: llvm_unreachable("Invalid value type!");
16543 case MVT::i8: Reg = X86::AL; size = 1; break;
16544 case MVT::i16: Reg = X86::AX; size = 2; break;
16545 case MVT::i32: Reg = X86::EAX; size = 4; break;
16547 assert(Subtarget->is64Bit() && "Node not type legal!");
16548 Reg = X86::RAX; size = 8;
16551 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16552 Op.getOperand(2), SDValue());
16553 SDValue Ops[] = { cpIn.getValue(0),
16556 DAG.getTargetConstant(size, MVT::i8),
16557 cpIn.getValue(1) };
16558 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16559 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16560 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16564 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16565 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16566 MVT::i32, cpOut.getValue(2));
16567 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16568 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16570 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16571 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16572 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16576 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16577 SelectionDAG &DAG) {
16578 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16579 MVT DstVT = Op.getSimpleValueType();
16581 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16582 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16583 if (DstVT != MVT::f64)
16584 // This conversion needs to be expanded.
16587 SDValue InVec = Op->getOperand(0);
16589 unsigned NumElts = SrcVT.getVectorNumElements();
16590 EVT SVT = SrcVT.getVectorElementType();
16592 // Widen the vector in input in the case of MVT::v2i32.
16593 // Example: from MVT::v2i32 to MVT::v4i32.
16594 SmallVector<SDValue, 16> Elts;
16595 for (unsigned i = 0, e = NumElts; i != e; ++i)
16596 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16597 DAG.getIntPtrConstant(i)));
16599 // Explicitly mark the extra elements as Undef.
16600 SDValue Undef = DAG.getUNDEF(SVT);
16601 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16602 Elts.push_back(Undef);
16604 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16605 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16606 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16607 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16608 DAG.getIntPtrConstant(0));
16611 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16612 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16613 assert((DstVT == MVT::i64 ||
16614 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16615 "Unexpected custom BITCAST");
16616 // i64 <=> MMX conversions are Legal.
16617 if (SrcVT==MVT::i64 && DstVT.isVector())
16619 if (DstVT==MVT::i64 && SrcVT.isVector())
16621 // MMX <=> MMX conversions are Legal.
16622 if (SrcVT.isVector() && DstVT.isVector())
16624 // All other conversions need to be expanded.
16628 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16629 SDNode *Node = Op.getNode();
16631 EVT T = Node->getValueType(0);
16632 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16633 DAG.getConstant(0, T), Node->getOperand(2));
16634 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16635 cast<AtomicSDNode>(Node)->getMemoryVT(),
16636 Node->getOperand(0),
16637 Node->getOperand(1), negOp,
16638 cast<AtomicSDNode>(Node)->getMemOperand(),
16639 cast<AtomicSDNode>(Node)->getOrdering(),
16640 cast<AtomicSDNode>(Node)->getSynchScope());
16643 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16644 SDNode *Node = Op.getNode();
16646 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16648 // Convert seq_cst store -> xchg
16649 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16650 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16651 // (The only way to get a 16-byte store is cmpxchg16b)
16652 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16653 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16654 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16655 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16656 cast<AtomicSDNode>(Node)->getMemoryVT(),
16657 Node->getOperand(0),
16658 Node->getOperand(1), Node->getOperand(2),
16659 cast<AtomicSDNode>(Node)->getMemOperand(),
16660 cast<AtomicSDNode>(Node)->getOrdering(),
16661 cast<AtomicSDNode>(Node)->getSynchScope());
16662 return Swap.getValue(1);
16664 // Other atomic stores have a simple pattern.
16668 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16669 EVT VT = Op.getNode()->getSimpleValueType(0);
16671 // Let legalize expand this if it isn't a legal type yet.
16672 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16675 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16678 bool ExtraOp = false;
16679 switch (Op.getOpcode()) {
16680 default: llvm_unreachable("Invalid code");
16681 case ISD::ADDC: Opc = X86ISD::ADD; break;
16682 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16683 case ISD::SUBC: Opc = X86ISD::SUB; break;
16684 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16688 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16690 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16691 Op.getOperand(1), Op.getOperand(2));
16694 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16695 SelectionDAG &DAG) {
16696 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16698 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16699 // which returns the values as { float, float } (in XMM0) or
16700 // { double, double } (which is returned in XMM0, XMM1).
16702 SDValue Arg = Op.getOperand(0);
16703 EVT ArgVT = Arg.getValueType();
16704 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16706 TargetLowering::ArgListTy Args;
16707 TargetLowering::ArgListEntry Entry;
16711 Entry.isSExt = false;
16712 Entry.isZExt = false;
16713 Args.push_back(Entry);
16715 bool isF64 = ArgVT == MVT::f64;
16716 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16717 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16718 // the results are returned via SRet in memory.
16719 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16721 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16723 Type *RetTy = isF64
16724 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16725 : (Type*)VectorType::get(ArgTy, 4);
16727 TargetLowering::CallLoweringInfo CLI(DAG);
16728 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16729 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16731 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16734 // Returned in xmm0 and xmm1.
16735 return CallResult.first;
16737 // Returned in bits 0:31 and 32:64 xmm0.
16738 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16739 CallResult.first, DAG.getIntPtrConstant(0));
16740 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16741 CallResult.first, DAG.getIntPtrConstant(1));
16742 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16743 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16746 /// LowerOperation - Provide custom lowering hooks for some operations.
16748 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16749 switch (Op.getOpcode()) {
16750 default: llvm_unreachable("Should not custom lower this!");
16751 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16752 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16753 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16754 return LowerCMP_SWAP(Op, Subtarget, DAG);
16755 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16756 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16757 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16758 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16759 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16760 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16761 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16762 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16763 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16764 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16765 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16766 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16767 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16768 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16769 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16770 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16771 case ISD::SHL_PARTS:
16772 case ISD::SRA_PARTS:
16773 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16774 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16775 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16776 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16777 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16778 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16779 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16780 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16781 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16782 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16783 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
16784 case ISD::FABS: return LowerFABS(Op, DAG);
16785 case ISD::FNEG: return LowerFNEG(Op, DAG);
16786 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16787 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16788 case ISD::SETCC: return LowerSETCC(Op, DAG);
16789 case ISD::SELECT: return LowerSELECT(Op, DAG);
16790 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16791 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16792 case ISD::VASTART: return LowerVASTART(Op, DAG);
16793 case ISD::VAARG: return LowerVAARG(Op, DAG);
16794 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16795 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16796 case ISD::INTRINSIC_VOID:
16797 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16798 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16799 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16800 case ISD::FRAME_TO_ARGS_OFFSET:
16801 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16802 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16803 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16804 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16805 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16806 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16807 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16808 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16809 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16810 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16811 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16812 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16813 case ISD::UMUL_LOHI:
16814 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16817 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16823 case ISD::UMULO: return LowerXALUO(Op, DAG);
16824 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16825 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16829 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16830 case ISD::ADD: return LowerADD(Op, DAG);
16831 case ISD::SUB: return LowerSUB(Op, DAG);
16832 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16836 static void ReplaceATOMIC_LOAD(SDNode *Node,
16837 SmallVectorImpl<SDValue> &Results,
16838 SelectionDAG &DAG) {
16840 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16842 // Convert wide load -> cmpxchg8b/cmpxchg16b
16843 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16844 // (The only way to get a 16-byte load is cmpxchg16b)
16845 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16846 SDValue Zero = DAG.getConstant(0, VT);
16847 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16849 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16850 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16851 cast<AtomicSDNode>(Node)->getMemOperand(),
16852 cast<AtomicSDNode>(Node)->getOrdering(),
16853 cast<AtomicSDNode>(Node)->getOrdering(),
16854 cast<AtomicSDNode>(Node)->getSynchScope());
16855 Results.push_back(Swap.getValue(0));
16856 Results.push_back(Swap.getValue(2));
16859 /// ReplaceNodeResults - Replace a node with an illegal result type
16860 /// with a new node built out of custom code.
16861 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16862 SmallVectorImpl<SDValue>&Results,
16863 SelectionDAG &DAG) const {
16865 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16866 switch (N->getOpcode()) {
16868 llvm_unreachable("Do not know how to custom type legalize this operation!");
16869 case ISD::SIGN_EXTEND_INREG:
16874 // We don't want to expand or promote these.
16881 case ISD::UDIVREM: {
16882 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16883 Results.push_back(V);
16886 case ISD::FP_TO_SINT:
16887 case ISD::FP_TO_UINT: {
16888 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16890 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16893 std::pair<SDValue,SDValue> Vals =
16894 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16895 SDValue FIST = Vals.first, StackSlot = Vals.second;
16896 if (FIST.getNode()) {
16897 EVT VT = N->getValueType(0);
16898 // Return a load from the stack slot.
16899 if (StackSlot.getNode())
16900 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16901 MachinePointerInfo(),
16902 false, false, false, 0));
16904 Results.push_back(FIST);
16908 case ISD::UINT_TO_FP: {
16909 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16910 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16911 N->getValueType(0) != MVT::v2f32)
16913 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16915 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16917 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16918 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16919 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16920 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16921 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16922 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16925 case ISD::FP_ROUND: {
16926 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16928 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16929 Results.push_back(V);
16932 case ISD::INTRINSIC_W_CHAIN: {
16933 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16935 default : llvm_unreachable("Do not know how to custom type "
16936 "legalize this intrinsic operation!");
16937 case Intrinsic::x86_rdtsc:
16938 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16940 case Intrinsic::x86_rdtscp:
16941 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16943 case Intrinsic::x86_rdpmc:
16944 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16947 case ISD::READCYCLECOUNTER: {
16948 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16951 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16952 EVT T = N->getValueType(0);
16953 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16954 bool Regs64bit = T == MVT::i128;
16955 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16956 SDValue cpInL, cpInH;
16957 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16958 DAG.getConstant(0, HalfT));
16959 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16960 DAG.getConstant(1, HalfT));
16961 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16962 Regs64bit ? X86::RAX : X86::EAX,
16964 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16965 Regs64bit ? X86::RDX : X86::EDX,
16966 cpInH, cpInL.getValue(1));
16967 SDValue swapInL, swapInH;
16968 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16969 DAG.getConstant(0, HalfT));
16970 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16971 DAG.getConstant(1, HalfT));
16972 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16973 Regs64bit ? X86::RBX : X86::EBX,
16974 swapInL, cpInH.getValue(1));
16975 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16976 Regs64bit ? X86::RCX : X86::ECX,
16977 swapInH, swapInL.getValue(1));
16978 SDValue Ops[] = { swapInH.getValue(0),
16980 swapInH.getValue(1) };
16981 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16982 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16983 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16984 X86ISD::LCMPXCHG8_DAG;
16985 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16986 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16987 Regs64bit ? X86::RAX : X86::EAX,
16988 HalfT, Result.getValue(1));
16989 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16990 Regs64bit ? X86::RDX : X86::EDX,
16991 HalfT, cpOutL.getValue(2));
16992 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16994 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16995 MVT::i32, cpOutH.getValue(2));
16997 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16998 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16999 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17001 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17002 Results.push_back(Success);
17003 Results.push_back(EFLAGS.getValue(1));
17006 case ISD::ATOMIC_SWAP:
17007 case ISD::ATOMIC_LOAD_ADD:
17008 case ISD::ATOMIC_LOAD_SUB:
17009 case ISD::ATOMIC_LOAD_AND:
17010 case ISD::ATOMIC_LOAD_OR:
17011 case ISD::ATOMIC_LOAD_XOR:
17012 case ISD::ATOMIC_LOAD_NAND:
17013 case ISD::ATOMIC_LOAD_MIN:
17014 case ISD::ATOMIC_LOAD_MAX:
17015 case ISD::ATOMIC_LOAD_UMIN:
17016 case ISD::ATOMIC_LOAD_UMAX:
17017 // Delegate to generic TypeLegalization. Situations we can really handle
17018 // should have already been dealt with by X86AtomicExpandPass.cpp.
17020 case ISD::ATOMIC_LOAD: {
17021 ReplaceATOMIC_LOAD(N, Results, DAG);
17024 case ISD::BITCAST: {
17025 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17026 EVT DstVT = N->getValueType(0);
17027 EVT SrcVT = N->getOperand(0)->getValueType(0);
17029 if (SrcVT != MVT::f64 ||
17030 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17033 unsigned NumElts = DstVT.getVectorNumElements();
17034 EVT SVT = DstVT.getVectorElementType();
17035 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17036 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17037 MVT::v2f64, N->getOperand(0));
17038 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17040 if (ExperimentalVectorWideningLegalization) {
17041 // If we are legalizing vectors by widening, we already have the desired
17042 // legal vector type, just return it.
17043 Results.push_back(ToVecInt);
17047 SmallVector<SDValue, 8> Elts;
17048 for (unsigned i = 0, e = NumElts; i != e; ++i)
17049 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17050 ToVecInt, DAG.getIntPtrConstant(i)));
17052 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17057 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17059 default: return nullptr;
17060 case X86ISD::BSF: return "X86ISD::BSF";
17061 case X86ISD::BSR: return "X86ISD::BSR";
17062 case X86ISD::SHLD: return "X86ISD::SHLD";
17063 case X86ISD::SHRD: return "X86ISD::SHRD";
17064 case X86ISD::FAND: return "X86ISD::FAND";
17065 case X86ISD::FANDN: return "X86ISD::FANDN";
17066 case X86ISD::FOR: return "X86ISD::FOR";
17067 case X86ISD::FXOR: return "X86ISD::FXOR";
17068 case X86ISD::FSRL: return "X86ISD::FSRL";
17069 case X86ISD::FILD: return "X86ISD::FILD";
17070 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17071 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17072 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17073 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17074 case X86ISD::FLD: return "X86ISD::FLD";
17075 case X86ISD::FST: return "X86ISD::FST";
17076 case X86ISD::CALL: return "X86ISD::CALL";
17077 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17078 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17079 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17080 case X86ISD::BT: return "X86ISD::BT";
17081 case X86ISD::CMP: return "X86ISD::CMP";
17082 case X86ISD::COMI: return "X86ISD::COMI";
17083 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17084 case X86ISD::CMPM: return "X86ISD::CMPM";
17085 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17086 case X86ISD::SETCC: return "X86ISD::SETCC";
17087 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17088 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17089 case X86ISD::CMOV: return "X86ISD::CMOV";
17090 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17091 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17092 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17093 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17094 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17095 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17096 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17097 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17098 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17099 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17100 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17101 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17102 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17103 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17104 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17105 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17106 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17107 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17108 case X86ISD::HADD: return "X86ISD::HADD";
17109 case X86ISD::HSUB: return "X86ISD::HSUB";
17110 case X86ISD::FHADD: return "X86ISD::FHADD";
17111 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17112 case X86ISD::UMAX: return "X86ISD::UMAX";
17113 case X86ISD::UMIN: return "X86ISD::UMIN";
17114 case X86ISD::SMAX: return "X86ISD::SMAX";
17115 case X86ISD::SMIN: return "X86ISD::SMIN";
17116 case X86ISD::FMAX: return "X86ISD::FMAX";
17117 case X86ISD::FMIN: return "X86ISD::FMIN";
17118 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17119 case X86ISD::FMINC: return "X86ISD::FMINC";
17120 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17121 case X86ISD::FRCP: return "X86ISD::FRCP";
17122 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17123 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17124 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17125 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17126 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17127 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17128 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17129 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17130 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17131 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17132 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17133 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17134 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17135 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17136 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17137 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17138 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17139 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17140 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17141 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17142 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17143 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17144 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17145 case X86ISD::VSHL: return "X86ISD::VSHL";
17146 case X86ISD::VSRL: return "X86ISD::VSRL";
17147 case X86ISD::VSRA: return "X86ISD::VSRA";
17148 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17149 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17150 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17151 case X86ISD::CMPP: return "X86ISD::CMPP";
17152 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17153 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17154 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17155 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17156 case X86ISD::ADD: return "X86ISD::ADD";
17157 case X86ISD::SUB: return "X86ISD::SUB";
17158 case X86ISD::ADC: return "X86ISD::ADC";
17159 case X86ISD::SBB: return "X86ISD::SBB";
17160 case X86ISD::SMUL: return "X86ISD::SMUL";
17161 case X86ISD::UMUL: return "X86ISD::UMUL";
17162 case X86ISD::INC: return "X86ISD::INC";
17163 case X86ISD::DEC: return "X86ISD::DEC";
17164 case X86ISD::OR: return "X86ISD::OR";
17165 case X86ISD::XOR: return "X86ISD::XOR";
17166 case X86ISD::AND: return "X86ISD::AND";
17167 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17168 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17169 case X86ISD::PTEST: return "X86ISD::PTEST";
17170 case X86ISD::TESTP: return "X86ISD::TESTP";
17171 case X86ISD::TESTM: return "X86ISD::TESTM";
17172 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17173 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17174 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17175 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17176 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17177 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17178 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17179 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17180 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17181 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17182 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17183 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17184 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17185 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17186 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17187 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17188 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17189 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17190 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17191 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17192 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17193 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17194 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17195 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17196 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17197 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17198 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17199 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17200 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17201 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17202 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17203 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17204 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17205 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17206 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17207 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17208 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17209 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17210 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17211 case X86ISD::SAHF: return "X86ISD::SAHF";
17212 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17213 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17214 case X86ISD::FMADD: return "X86ISD::FMADD";
17215 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17216 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17217 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17218 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17219 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17220 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17221 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17222 case X86ISD::XTEST: return "X86ISD::XTEST";
17226 // isLegalAddressingMode - Return true if the addressing mode represented
17227 // by AM is legal for this target, for a load/store of the specified type.
17228 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17230 // X86 supports extremely general addressing modes.
17231 CodeModel::Model M = getTargetMachine().getCodeModel();
17232 Reloc::Model R = getTargetMachine().getRelocationModel();
17234 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17235 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17240 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17242 // If a reference to this global requires an extra load, we can't fold it.
17243 if (isGlobalStubReference(GVFlags))
17246 // If BaseGV requires a register for the PIC base, we cannot also have a
17247 // BaseReg specified.
17248 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17251 // If lower 4G is not available, then we must use rip-relative addressing.
17252 if ((M != CodeModel::Small || R != Reloc::Static) &&
17253 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17257 switch (AM.Scale) {
17263 // These scales always work.
17268 // These scales are formed with basereg+scalereg. Only accept if there is
17273 default: // Other stuff never works.
17280 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17281 unsigned Bits = Ty->getScalarSizeInBits();
17283 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17284 // particularly cheaper than those without.
17288 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17289 // variable shifts just as cheap as scalar ones.
17290 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17293 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17294 // fully general vector.
17298 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17299 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17301 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17302 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17303 return NumBits1 > NumBits2;
17306 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17307 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17310 if (!isTypeLegal(EVT::getEVT(Ty1)))
17313 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17315 // Assuming the caller doesn't have a zeroext or signext return parameter,
17316 // truncation all the way down to i1 is valid.
17320 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17321 return isInt<32>(Imm);
17324 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17325 // Can also use sub to handle negated immediates.
17326 return isInt<32>(Imm);
17329 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17330 if (!VT1.isInteger() || !VT2.isInteger())
17332 unsigned NumBits1 = VT1.getSizeInBits();
17333 unsigned NumBits2 = VT2.getSizeInBits();
17334 return NumBits1 > NumBits2;
17337 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17338 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17339 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17342 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17343 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17344 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17347 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17348 EVT VT1 = Val.getValueType();
17349 if (isZExtFree(VT1, VT2))
17352 if (Val.getOpcode() != ISD::LOAD)
17355 if (!VT1.isSimple() || !VT1.isInteger() ||
17356 !VT2.isSimple() || !VT2.isInteger())
17359 switch (VT1.getSimpleVT().SimpleTy) {
17364 // X86 has 8, 16, and 32-bit zero-extending loads.
17372 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17373 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17376 VT = VT.getScalarType();
17378 if (!VT.isSimple())
17381 switch (VT.getSimpleVT().SimpleTy) {
17392 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17393 // i16 instructions are longer (0x66 prefix) and potentially slower.
17394 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17397 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17398 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17399 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17400 /// are assumed to be legal.
17402 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17404 if (!VT.isSimple())
17407 MVT SVT = VT.getSimpleVT();
17409 // Very little shuffling can be done for 64-bit vectors right now.
17410 if (VT.getSizeInBits() == 64)
17413 // If this is a single-input shuffle with no 128 bit lane crossings we can
17414 // lower it into pshufb.
17415 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17416 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17417 bool isLegal = true;
17418 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17419 if (M[I] >= (int)SVT.getVectorNumElements() ||
17420 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17429 // FIXME: blends, shifts.
17430 return (SVT.getVectorNumElements() == 2 ||
17431 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17432 isMOVLMask(M, SVT) ||
17433 isMOVHLPSMask(M, SVT) ||
17434 isSHUFPMask(M, SVT) ||
17435 isPSHUFDMask(M, SVT) ||
17436 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17437 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17438 isPALIGNRMask(M, SVT, Subtarget) ||
17439 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17440 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17441 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17442 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17443 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17447 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17449 if (!VT.isSimple())
17452 MVT SVT = VT.getSimpleVT();
17453 unsigned NumElts = SVT.getVectorNumElements();
17454 // FIXME: This collection of masks seems suspect.
17457 if (NumElts == 4 && SVT.is128BitVector()) {
17458 return (isMOVLMask(Mask, SVT) ||
17459 isCommutedMOVLMask(Mask, SVT, true) ||
17460 isSHUFPMask(Mask, SVT) ||
17461 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17466 //===----------------------------------------------------------------------===//
17467 // X86 Scheduler Hooks
17468 //===----------------------------------------------------------------------===//
17470 /// Utility function to emit xbegin specifying the start of an RTM region.
17471 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17472 const TargetInstrInfo *TII) {
17473 DebugLoc DL = MI->getDebugLoc();
17475 const BasicBlock *BB = MBB->getBasicBlock();
17476 MachineFunction::iterator I = MBB;
17479 // For the v = xbegin(), we generate
17490 MachineBasicBlock *thisMBB = MBB;
17491 MachineFunction *MF = MBB->getParent();
17492 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17493 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17494 MF->insert(I, mainMBB);
17495 MF->insert(I, sinkMBB);
17497 // Transfer the remainder of BB and its successor edges to sinkMBB.
17498 sinkMBB->splice(sinkMBB->begin(), MBB,
17499 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17500 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17504 // # fallthrough to mainMBB
17505 // # abortion to sinkMBB
17506 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17507 thisMBB->addSuccessor(mainMBB);
17508 thisMBB->addSuccessor(sinkMBB);
17512 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17513 mainMBB->addSuccessor(sinkMBB);
17516 // EAX is live into the sinkMBB
17517 sinkMBB->addLiveIn(X86::EAX);
17518 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17519 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17522 MI->eraseFromParent();
17526 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17527 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17528 // in the .td file.
17529 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17530 const TargetInstrInfo *TII) {
17532 switch (MI->getOpcode()) {
17533 default: llvm_unreachable("illegal opcode!");
17534 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17535 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17536 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17537 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17538 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17539 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17540 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17541 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17544 DebugLoc dl = MI->getDebugLoc();
17545 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17547 unsigned NumArgs = MI->getNumOperands();
17548 for (unsigned i = 1; i < NumArgs; ++i) {
17549 MachineOperand &Op = MI->getOperand(i);
17550 if (!(Op.isReg() && Op.isImplicit()))
17551 MIB.addOperand(Op);
17553 if (MI->hasOneMemOperand())
17554 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17556 BuildMI(*BB, MI, dl,
17557 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17558 .addReg(X86::XMM0);
17560 MI->eraseFromParent();
17564 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17565 // defs in an instruction pattern
17566 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17567 const TargetInstrInfo *TII) {
17569 switch (MI->getOpcode()) {
17570 default: llvm_unreachable("illegal opcode!");
17571 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17572 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17573 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17574 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17575 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17576 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17577 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17578 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17581 DebugLoc dl = MI->getDebugLoc();
17582 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17584 unsigned NumArgs = MI->getNumOperands(); // remove the results
17585 for (unsigned i = 1; i < NumArgs; ++i) {
17586 MachineOperand &Op = MI->getOperand(i);
17587 if (!(Op.isReg() && Op.isImplicit()))
17588 MIB.addOperand(Op);
17590 if (MI->hasOneMemOperand())
17591 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17593 BuildMI(*BB, MI, dl,
17594 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17597 MI->eraseFromParent();
17601 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17602 const TargetInstrInfo *TII,
17603 const X86Subtarget* Subtarget) {
17604 DebugLoc dl = MI->getDebugLoc();
17606 // Address into RAX/EAX, other two args into ECX, EDX.
17607 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17608 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17609 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17610 for (int i = 0; i < X86::AddrNumOperands; ++i)
17611 MIB.addOperand(MI->getOperand(i));
17613 unsigned ValOps = X86::AddrNumOperands;
17614 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17615 .addReg(MI->getOperand(ValOps).getReg());
17616 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17617 .addReg(MI->getOperand(ValOps+1).getReg());
17619 // The instruction doesn't actually take any operands though.
17620 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17622 MI->eraseFromParent(); // The pseudo is gone now.
17626 MachineBasicBlock *
17627 X86TargetLowering::EmitVAARG64WithCustomInserter(
17629 MachineBasicBlock *MBB) const {
17630 // Emit va_arg instruction on X86-64.
17632 // Operands to this pseudo-instruction:
17633 // 0 ) Output : destination address (reg)
17634 // 1-5) Input : va_list address (addr, i64mem)
17635 // 6 ) ArgSize : Size (in bytes) of vararg type
17636 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17637 // 8 ) Align : Alignment of type
17638 // 9 ) EFLAGS (implicit-def)
17640 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17641 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17643 unsigned DestReg = MI->getOperand(0).getReg();
17644 MachineOperand &Base = MI->getOperand(1);
17645 MachineOperand &Scale = MI->getOperand(2);
17646 MachineOperand &Index = MI->getOperand(3);
17647 MachineOperand &Disp = MI->getOperand(4);
17648 MachineOperand &Segment = MI->getOperand(5);
17649 unsigned ArgSize = MI->getOperand(6).getImm();
17650 unsigned ArgMode = MI->getOperand(7).getImm();
17651 unsigned Align = MI->getOperand(8).getImm();
17653 // Memory Reference
17654 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17655 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17656 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17658 // Machine Information
17659 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17660 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17661 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17662 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17663 DebugLoc DL = MI->getDebugLoc();
17665 // struct va_list {
17668 // i64 overflow_area (address)
17669 // i64 reg_save_area (address)
17671 // sizeof(va_list) = 24
17672 // alignment(va_list) = 8
17674 unsigned TotalNumIntRegs = 6;
17675 unsigned TotalNumXMMRegs = 8;
17676 bool UseGPOffset = (ArgMode == 1);
17677 bool UseFPOffset = (ArgMode == 2);
17678 unsigned MaxOffset = TotalNumIntRegs * 8 +
17679 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17681 /* Align ArgSize to a multiple of 8 */
17682 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17683 bool NeedsAlign = (Align > 8);
17685 MachineBasicBlock *thisMBB = MBB;
17686 MachineBasicBlock *overflowMBB;
17687 MachineBasicBlock *offsetMBB;
17688 MachineBasicBlock *endMBB;
17690 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17691 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17692 unsigned OffsetReg = 0;
17694 if (!UseGPOffset && !UseFPOffset) {
17695 // If we only pull from the overflow region, we don't create a branch.
17696 // We don't need to alter control flow.
17697 OffsetDestReg = 0; // unused
17698 OverflowDestReg = DestReg;
17700 offsetMBB = nullptr;
17701 overflowMBB = thisMBB;
17704 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17705 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17706 // If not, pull from overflow_area. (branch to overflowMBB)
17711 // offsetMBB overflowMBB
17716 // Registers for the PHI in endMBB
17717 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17718 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17720 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17721 MachineFunction *MF = MBB->getParent();
17722 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17723 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17724 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17726 MachineFunction::iterator MBBIter = MBB;
17729 // Insert the new basic blocks
17730 MF->insert(MBBIter, offsetMBB);
17731 MF->insert(MBBIter, overflowMBB);
17732 MF->insert(MBBIter, endMBB);
17734 // Transfer the remainder of MBB and its successor edges to endMBB.
17735 endMBB->splice(endMBB->begin(), thisMBB,
17736 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17737 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17739 // Make offsetMBB and overflowMBB successors of thisMBB
17740 thisMBB->addSuccessor(offsetMBB);
17741 thisMBB->addSuccessor(overflowMBB);
17743 // endMBB is a successor of both offsetMBB and overflowMBB
17744 offsetMBB->addSuccessor(endMBB);
17745 overflowMBB->addSuccessor(endMBB);
17747 // Load the offset value into a register
17748 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17749 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17753 .addDisp(Disp, UseFPOffset ? 4 : 0)
17754 .addOperand(Segment)
17755 .setMemRefs(MMOBegin, MMOEnd);
17757 // Check if there is enough room left to pull this argument.
17758 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17760 .addImm(MaxOffset + 8 - ArgSizeA8);
17762 // Branch to "overflowMBB" if offset >= max
17763 // Fall through to "offsetMBB" otherwise
17764 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17765 .addMBB(overflowMBB);
17768 // In offsetMBB, emit code to use the reg_save_area.
17770 assert(OffsetReg != 0);
17772 // Read the reg_save_area address.
17773 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17774 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17779 .addOperand(Segment)
17780 .setMemRefs(MMOBegin, MMOEnd);
17782 // Zero-extend the offset
17783 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17784 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17787 .addImm(X86::sub_32bit);
17789 // Add the offset to the reg_save_area to get the final address.
17790 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17791 .addReg(OffsetReg64)
17792 .addReg(RegSaveReg);
17794 // Compute the offset for the next argument
17795 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17796 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17798 .addImm(UseFPOffset ? 16 : 8);
17800 // Store it back into the va_list.
17801 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17805 .addDisp(Disp, UseFPOffset ? 4 : 0)
17806 .addOperand(Segment)
17807 .addReg(NextOffsetReg)
17808 .setMemRefs(MMOBegin, MMOEnd);
17811 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17816 // Emit code to use overflow area
17819 // Load the overflow_area address into a register.
17820 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17821 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17826 .addOperand(Segment)
17827 .setMemRefs(MMOBegin, MMOEnd);
17829 // If we need to align it, do so. Otherwise, just copy the address
17830 // to OverflowDestReg.
17832 // Align the overflow address
17833 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17834 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17836 // aligned_addr = (addr + (align-1)) & ~(align-1)
17837 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17838 .addReg(OverflowAddrReg)
17841 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17843 .addImm(~(uint64_t)(Align-1));
17845 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17846 .addReg(OverflowAddrReg);
17849 // Compute the next overflow address after this argument.
17850 // (the overflow address should be kept 8-byte aligned)
17851 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17852 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17853 .addReg(OverflowDestReg)
17854 .addImm(ArgSizeA8);
17856 // Store the new overflow address.
17857 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17862 .addOperand(Segment)
17863 .addReg(NextAddrReg)
17864 .setMemRefs(MMOBegin, MMOEnd);
17866 // If we branched, emit the PHI to the front of endMBB.
17868 BuildMI(*endMBB, endMBB->begin(), DL,
17869 TII->get(X86::PHI), DestReg)
17870 .addReg(OffsetDestReg).addMBB(offsetMBB)
17871 .addReg(OverflowDestReg).addMBB(overflowMBB);
17874 // Erase the pseudo instruction
17875 MI->eraseFromParent();
17880 MachineBasicBlock *
17881 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17883 MachineBasicBlock *MBB) const {
17884 // Emit code to save XMM registers to the stack. The ABI says that the
17885 // number of registers to save is given in %al, so it's theoretically
17886 // possible to do an indirect jump trick to avoid saving all of them,
17887 // however this code takes a simpler approach and just executes all
17888 // of the stores if %al is non-zero. It's less code, and it's probably
17889 // easier on the hardware branch predictor, and stores aren't all that
17890 // expensive anyway.
17892 // Create the new basic blocks. One block contains all the XMM stores,
17893 // and one block is the final destination regardless of whether any
17894 // stores were performed.
17895 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17896 MachineFunction *F = MBB->getParent();
17897 MachineFunction::iterator MBBIter = MBB;
17899 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17900 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17901 F->insert(MBBIter, XMMSaveMBB);
17902 F->insert(MBBIter, EndMBB);
17904 // Transfer the remainder of MBB and its successor edges to EndMBB.
17905 EndMBB->splice(EndMBB->begin(), MBB,
17906 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17907 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17909 // The original block will now fall through to the XMM save block.
17910 MBB->addSuccessor(XMMSaveMBB);
17911 // The XMMSaveMBB will fall through to the end block.
17912 XMMSaveMBB->addSuccessor(EndMBB);
17914 // Now add the instructions.
17915 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17916 DebugLoc DL = MI->getDebugLoc();
17918 unsigned CountReg = MI->getOperand(0).getReg();
17919 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17920 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17922 if (!Subtarget->isTargetWin64()) {
17923 // If %al is 0, branch around the XMM save block.
17924 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17925 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17926 MBB->addSuccessor(EndMBB);
17929 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17930 // that was just emitted, but clearly shouldn't be "saved".
17931 assert((MI->getNumOperands() <= 3 ||
17932 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17933 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17934 && "Expected last argument to be EFLAGS");
17935 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17936 // In the XMM save block, save all the XMM argument registers.
17937 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17938 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17939 MachineMemOperand *MMO =
17940 F->getMachineMemOperand(
17941 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17942 MachineMemOperand::MOStore,
17943 /*Size=*/16, /*Align=*/16);
17944 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17945 .addFrameIndex(RegSaveFrameIndex)
17946 .addImm(/*Scale=*/1)
17947 .addReg(/*IndexReg=*/0)
17948 .addImm(/*Disp=*/Offset)
17949 .addReg(/*Segment=*/0)
17950 .addReg(MI->getOperand(i).getReg())
17951 .addMemOperand(MMO);
17954 MI->eraseFromParent(); // The pseudo instruction is gone now.
17959 // The EFLAGS operand of SelectItr might be missing a kill marker
17960 // because there were multiple uses of EFLAGS, and ISel didn't know
17961 // which to mark. Figure out whether SelectItr should have had a
17962 // kill marker, and set it if it should. Returns the correct kill
17964 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
17965 MachineBasicBlock* BB,
17966 const TargetRegisterInfo* TRI) {
17967 // Scan forward through BB for a use/def of EFLAGS.
17968 MachineBasicBlock::iterator miI(std::next(SelectItr));
17969 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
17970 const MachineInstr& mi = *miI;
17971 if (mi.readsRegister(X86::EFLAGS))
17973 if (mi.definesRegister(X86::EFLAGS))
17974 break; // Should have kill-flag - update below.
17977 // If we hit the end of the block, check whether EFLAGS is live into a
17979 if (miI == BB->end()) {
17980 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
17981 sEnd = BB->succ_end();
17982 sItr != sEnd; ++sItr) {
17983 MachineBasicBlock* succ = *sItr;
17984 if (succ->isLiveIn(X86::EFLAGS))
17989 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
17990 // out. SelectMI should have a kill flag on EFLAGS.
17991 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
17995 MachineBasicBlock *
17996 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
17997 MachineBasicBlock *BB) const {
17998 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
17999 DebugLoc DL = MI->getDebugLoc();
18001 // To "insert" a SELECT_CC instruction, we actually have to insert the
18002 // diamond control-flow pattern. The incoming instruction knows the
18003 // destination vreg to set, the condition code register to branch on, the
18004 // true/false values to select between, and a branch opcode to use.
18005 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18006 MachineFunction::iterator It = BB;
18012 // cmpTY ccX, r1, r2
18014 // fallthrough --> copy0MBB
18015 MachineBasicBlock *thisMBB = BB;
18016 MachineFunction *F = BB->getParent();
18017 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18018 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18019 F->insert(It, copy0MBB);
18020 F->insert(It, sinkMBB);
18022 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18023 // live into the sink and copy blocks.
18024 const TargetRegisterInfo *TRI =
18025 BB->getParent()->getSubtarget().getRegisterInfo();
18026 if (!MI->killsRegister(X86::EFLAGS) &&
18027 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18028 copy0MBB->addLiveIn(X86::EFLAGS);
18029 sinkMBB->addLiveIn(X86::EFLAGS);
18032 // Transfer the remainder of BB and its successor edges to sinkMBB.
18033 sinkMBB->splice(sinkMBB->begin(), BB,
18034 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18035 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18037 // Add the true and fallthrough blocks as its successors.
18038 BB->addSuccessor(copy0MBB);
18039 BB->addSuccessor(sinkMBB);
18041 // Create the conditional branch instruction.
18043 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18044 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18047 // %FalseValue = ...
18048 // # fallthrough to sinkMBB
18049 copy0MBB->addSuccessor(sinkMBB);
18052 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18054 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18055 TII->get(X86::PHI), MI->getOperand(0).getReg())
18056 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18057 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18059 MI->eraseFromParent(); // The pseudo instruction is gone now.
18063 MachineBasicBlock *
18064 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18065 bool Is64Bit) const {
18066 MachineFunction *MF = BB->getParent();
18067 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18068 DebugLoc DL = MI->getDebugLoc();
18069 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18071 assert(MF->shouldSplitStack());
18073 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18074 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18077 // ... [Till the alloca]
18078 // If stacklet is not large enough, jump to mallocMBB
18081 // Allocate by subtracting from RSP
18082 // Jump to continueMBB
18085 // Allocate by call to runtime
18089 // [rest of original BB]
18092 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18093 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18094 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18096 MachineRegisterInfo &MRI = MF->getRegInfo();
18097 const TargetRegisterClass *AddrRegClass =
18098 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18100 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18101 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18102 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18103 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18104 sizeVReg = MI->getOperand(1).getReg(),
18105 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18107 MachineFunction::iterator MBBIter = BB;
18110 MF->insert(MBBIter, bumpMBB);
18111 MF->insert(MBBIter, mallocMBB);
18112 MF->insert(MBBIter, continueMBB);
18114 continueMBB->splice(continueMBB->begin(), BB,
18115 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18116 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18118 // Add code to the main basic block to check if the stack limit has been hit,
18119 // and if so, jump to mallocMBB otherwise to bumpMBB.
18120 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18121 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18122 .addReg(tmpSPVReg).addReg(sizeVReg);
18123 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18124 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18125 .addReg(SPLimitVReg);
18126 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18128 // bumpMBB simply decreases the stack pointer, since we know the current
18129 // stacklet has enough space.
18130 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18131 .addReg(SPLimitVReg);
18132 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18133 .addReg(SPLimitVReg);
18134 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18136 // Calls into a routine in libgcc to allocate more space from the heap.
18137 const uint32_t *RegMask = MF->getTarget()
18138 .getSubtargetImpl()
18139 ->getRegisterInfo()
18140 ->getCallPreservedMask(CallingConv::C);
18142 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18144 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18145 .addExternalSymbol("__morestack_allocate_stack_space")
18146 .addRegMask(RegMask)
18147 .addReg(X86::RDI, RegState::Implicit)
18148 .addReg(X86::RAX, RegState::ImplicitDefine);
18150 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18152 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18153 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18154 .addExternalSymbol("__morestack_allocate_stack_space")
18155 .addRegMask(RegMask)
18156 .addReg(X86::EAX, RegState::ImplicitDefine);
18160 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18163 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18164 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18165 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18167 // Set up the CFG correctly.
18168 BB->addSuccessor(bumpMBB);
18169 BB->addSuccessor(mallocMBB);
18170 mallocMBB->addSuccessor(continueMBB);
18171 bumpMBB->addSuccessor(continueMBB);
18173 // Take care of the PHI nodes.
18174 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18175 MI->getOperand(0).getReg())
18176 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18177 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18179 // Delete the original pseudo instruction.
18180 MI->eraseFromParent();
18183 return continueMBB;
18186 MachineBasicBlock *
18187 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18188 MachineBasicBlock *BB) const {
18189 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18190 DebugLoc DL = MI->getDebugLoc();
18192 assert(!Subtarget->isTargetMacho());
18194 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18195 // non-trivial part is impdef of ESP.
18197 if (Subtarget->isTargetWin64()) {
18198 if (Subtarget->isTargetCygMing()) {
18199 // ___chkstk(Mingw64):
18200 // Clobbers R10, R11, RAX and EFLAGS.
18202 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18203 .addExternalSymbol("___chkstk")
18204 .addReg(X86::RAX, RegState::Implicit)
18205 .addReg(X86::RSP, RegState::Implicit)
18206 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18207 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18208 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18210 // __chkstk(MSVCRT): does not update stack pointer.
18211 // Clobbers R10, R11 and EFLAGS.
18212 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18213 .addExternalSymbol("__chkstk")
18214 .addReg(X86::RAX, RegState::Implicit)
18215 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18216 // RAX has the offset to be subtracted from RSP.
18217 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18222 const char *StackProbeSymbol =
18223 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18225 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18226 .addExternalSymbol(StackProbeSymbol)
18227 .addReg(X86::EAX, RegState::Implicit)
18228 .addReg(X86::ESP, RegState::Implicit)
18229 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18230 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18231 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18234 MI->eraseFromParent(); // The pseudo instruction is gone now.
18238 MachineBasicBlock *
18239 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18240 MachineBasicBlock *BB) const {
18241 // This is pretty easy. We're taking the value that we received from
18242 // our load from the relocation, sticking it in either RDI (x86-64)
18243 // or EAX and doing an indirect call. The return value will then
18244 // be in the normal return register.
18245 MachineFunction *F = BB->getParent();
18246 const X86InstrInfo *TII =
18247 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18248 DebugLoc DL = MI->getDebugLoc();
18250 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18251 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18253 // Get a register mask for the lowered call.
18254 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18255 // proper register mask.
18256 const uint32_t *RegMask = F->getTarget()
18257 .getSubtargetImpl()
18258 ->getRegisterInfo()
18259 ->getCallPreservedMask(CallingConv::C);
18260 if (Subtarget->is64Bit()) {
18261 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18262 TII->get(X86::MOV64rm), X86::RDI)
18264 .addImm(0).addReg(0)
18265 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18266 MI->getOperand(3).getTargetFlags())
18268 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18269 addDirectMem(MIB, X86::RDI);
18270 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18271 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18272 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18273 TII->get(X86::MOV32rm), X86::EAX)
18275 .addImm(0).addReg(0)
18276 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18277 MI->getOperand(3).getTargetFlags())
18279 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18280 addDirectMem(MIB, X86::EAX);
18281 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18283 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18284 TII->get(X86::MOV32rm), X86::EAX)
18285 .addReg(TII->getGlobalBaseReg(F))
18286 .addImm(0).addReg(0)
18287 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18288 MI->getOperand(3).getTargetFlags())
18290 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18291 addDirectMem(MIB, X86::EAX);
18292 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18295 MI->eraseFromParent(); // The pseudo instruction is gone now.
18299 MachineBasicBlock *
18300 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18301 MachineBasicBlock *MBB) const {
18302 DebugLoc DL = MI->getDebugLoc();
18303 MachineFunction *MF = MBB->getParent();
18304 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18305 MachineRegisterInfo &MRI = MF->getRegInfo();
18307 const BasicBlock *BB = MBB->getBasicBlock();
18308 MachineFunction::iterator I = MBB;
18311 // Memory Reference
18312 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18313 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18316 unsigned MemOpndSlot = 0;
18318 unsigned CurOp = 0;
18320 DstReg = MI->getOperand(CurOp++).getReg();
18321 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18322 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18323 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18324 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18326 MemOpndSlot = CurOp;
18328 MVT PVT = getPointerTy();
18329 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18330 "Invalid Pointer Size!");
18332 // For v = setjmp(buf), we generate
18335 // buf[LabelOffset] = restoreMBB
18336 // SjLjSetup restoreMBB
18342 // v = phi(main, restore)
18347 MachineBasicBlock *thisMBB = MBB;
18348 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18349 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18350 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18351 MF->insert(I, mainMBB);
18352 MF->insert(I, sinkMBB);
18353 MF->push_back(restoreMBB);
18355 MachineInstrBuilder MIB;
18357 // Transfer the remainder of BB and its successor edges to sinkMBB.
18358 sinkMBB->splice(sinkMBB->begin(), MBB,
18359 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18360 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18363 unsigned PtrStoreOpc = 0;
18364 unsigned LabelReg = 0;
18365 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18366 Reloc::Model RM = MF->getTarget().getRelocationModel();
18367 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18368 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18370 // Prepare IP either in reg or imm.
18371 if (!UseImmLabel) {
18372 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18373 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18374 LabelReg = MRI.createVirtualRegister(PtrRC);
18375 if (Subtarget->is64Bit()) {
18376 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18380 .addMBB(restoreMBB)
18383 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18384 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18385 .addReg(XII->getGlobalBaseReg(MF))
18388 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18392 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18394 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18395 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18396 if (i == X86::AddrDisp)
18397 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18399 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18402 MIB.addReg(LabelReg);
18404 MIB.addMBB(restoreMBB);
18405 MIB.setMemRefs(MMOBegin, MMOEnd);
18407 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18408 .addMBB(restoreMBB);
18410 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18411 MF->getSubtarget().getRegisterInfo());
18412 MIB.addRegMask(RegInfo->getNoPreservedMask());
18413 thisMBB->addSuccessor(mainMBB);
18414 thisMBB->addSuccessor(restoreMBB);
18418 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18419 mainMBB->addSuccessor(sinkMBB);
18422 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18423 TII->get(X86::PHI), DstReg)
18424 .addReg(mainDstReg).addMBB(mainMBB)
18425 .addReg(restoreDstReg).addMBB(restoreMBB);
18428 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18429 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18430 restoreMBB->addSuccessor(sinkMBB);
18432 MI->eraseFromParent();
18436 MachineBasicBlock *
18437 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18438 MachineBasicBlock *MBB) const {
18439 DebugLoc DL = MI->getDebugLoc();
18440 MachineFunction *MF = MBB->getParent();
18441 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18442 MachineRegisterInfo &MRI = MF->getRegInfo();
18444 // Memory Reference
18445 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18446 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18448 MVT PVT = getPointerTy();
18449 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18450 "Invalid Pointer Size!");
18452 const TargetRegisterClass *RC =
18453 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18454 unsigned Tmp = MRI.createVirtualRegister(RC);
18455 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18456 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18457 MF->getSubtarget().getRegisterInfo());
18458 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18459 unsigned SP = RegInfo->getStackRegister();
18461 MachineInstrBuilder MIB;
18463 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18464 const int64_t SPOffset = 2 * PVT.getStoreSize();
18466 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18467 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18470 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18471 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18472 MIB.addOperand(MI->getOperand(i));
18473 MIB.setMemRefs(MMOBegin, MMOEnd);
18475 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18476 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18477 if (i == X86::AddrDisp)
18478 MIB.addDisp(MI->getOperand(i), LabelOffset);
18480 MIB.addOperand(MI->getOperand(i));
18482 MIB.setMemRefs(MMOBegin, MMOEnd);
18484 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18485 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18486 if (i == X86::AddrDisp)
18487 MIB.addDisp(MI->getOperand(i), SPOffset);
18489 MIB.addOperand(MI->getOperand(i));
18491 MIB.setMemRefs(MMOBegin, MMOEnd);
18493 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18495 MI->eraseFromParent();
18499 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18500 // accumulator loops. Writing back to the accumulator allows the coalescer
18501 // to remove extra copies in the loop.
18502 MachineBasicBlock *
18503 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18504 MachineBasicBlock *MBB) const {
18505 MachineOperand &AddendOp = MI->getOperand(3);
18507 // Bail out early if the addend isn't a register - we can't switch these.
18508 if (!AddendOp.isReg())
18511 MachineFunction &MF = *MBB->getParent();
18512 MachineRegisterInfo &MRI = MF.getRegInfo();
18514 // Check whether the addend is defined by a PHI:
18515 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18516 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18517 if (!AddendDef.isPHI())
18520 // Look for the following pattern:
18522 // %addend = phi [%entry, 0], [%loop, %result]
18524 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18528 // %addend = phi [%entry, 0], [%loop, %result]
18530 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18532 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18533 assert(AddendDef.getOperand(i).isReg());
18534 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18535 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18536 if (&PHISrcInst == MI) {
18537 // Found a matching instruction.
18538 unsigned NewFMAOpc = 0;
18539 switch (MI->getOpcode()) {
18540 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18541 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18542 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18543 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18544 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18545 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18546 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18547 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18548 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18549 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18550 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18551 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18552 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18553 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18554 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18555 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18556 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18557 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18558 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18559 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18560 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18561 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18562 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18563 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18564 default: llvm_unreachable("Unrecognized FMA variant.");
18567 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18568 MachineInstrBuilder MIB =
18569 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18570 .addOperand(MI->getOperand(0))
18571 .addOperand(MI->getOperand(3))
18572 .addOperand(MI->getOperand(2))
18573 .addOperand(MI->getOperand(1));
18574 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18575 MI->eraseFromParent();
18582 MachineBasicBlock *
18583 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18584 MachineBasicBlock *BB) const {
18585 switch (MI->getOpcode()) {
18586 default: llvm_unreachable("Unexpected instr type to insert");
18587 case X86::TAILJMPd64:
18588 case X86::TAILJMPr64:
18589 case X86::TAILJMPm64:
18590 llvm_unreachable("TAILJMP64 would not be touched here.");
18591 case X86::TCRETURNdi64:
18592 case X86::TCRETURNri64:
18593 case X86::TCRETURNmi64:
18595 case X86::WIN_ALLOCA:
18596 return EmitLoweredWinAlloca(MI, BB);
18597 case X86::SEG_ALLOCA_32:
18598 return EmitLoweredSegAlloca(MI, BB, false);
18599 case X86::SEG_ALLOCA_64:
18600 return EmitLoweredSegAlloca(MI, BB, true);
18601 case X86::TLSCall_32:
18602 case X86::TLSCall_64:
18603 return EmitLoweredTLSCall(MI, BB);
18604 case X86::CMOV_GR8:
18605 case X86::CMOV_FR32:
18606 case X86::CMOV_FR64:
18607 case X86::CMOV_V4F32:
18608 case X86::CMOV_V2F64:
18609 case X86::CMOV_V2I64:
18610 case X86::CMOV_V8F32:
18611 case X86::CMOV_V4F64:
18612 case X86::CMOV_V4I64:
18613 case X86::CMOV_V16F32:
18614 case X86::CMOV_V8F64:
18615 case X86::CMOV_V8I64:
18616 case X86::CMOV_GR16:
18617 case X86::CMOV_GR32:
18618 case X86::CMOV_RFP32:
18619 case X86::CMOV_RFP64:
18620 case X86::CMOV_RFP80:
18621 return EmitLoweredSelect(MI, BB);
18623 case X86::FP32_TO_INT16_IN_MEM:
18624 case X86::FP32_TO_INT32_IN_MEM:
18625 case X86::FP32_TO_INT64_IN_MEM:
18626 case X86::FP64_TO_INT16_IN_MEM:
18627 case X86::FP64_TO_INT32_IN_MEM:
18628 case X86::FP64_TO_INT64_IN_MEM:
18629 case X86::FP80_TO_INT16_IN_MEM:
18630 case X86::FP80_TO_INT32_IN_MEM:
18631 case X86::FP80_TO_INT64_IN_MEM: {
18632 MachineFunction *F = BB->getParent();
18633 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
18634 DebugLoc DL = MI->getDebugLoc();
18636 // Change the floating point control register to use "round towards zero"
18637 // mode when truncating to an integer value.
18638 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18639 addFrameReference(BuildMI(*BB, MI, DL,
18640 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18642 // Load the old value of the high byte of the control word...
18644 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18645 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18648 // Set the high part to be round to zero...
18649 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18652 // Reload the modified control word now...
18653 addFrameReference(BuildMI(*BB, MI, DL,
18654 TII->get(X86::FLDCW16m)), CWFrameIdx);
18656 // Restore the memory image of control word to original value
18657 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18660 // Get the X86 opcode to use.
18662 switch (MI->getOpcode()) {
18663 default: llvm_unreachable("illegal opcode!");
18664 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18665 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18666 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18667 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18668 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18669 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18670 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18671 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18672 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18676 MachineOperand &Op = MI->getOperand(0);
18678 AM.BaseType = X86AddressMode::RegBase;
18679 AM.Base.Reg = Op.getReg();
18681 AM.BaseType = X86AddressMode::FrameIndexBase;
18682 AM.Base.FrameIndex = Op.getIndex();
18684 Op = MI->getOperand(1);
18686 AM.Scale = Op.getImm();
18687 Op = MI->getOperand(2);
18689 AM.IndexReg = Op.getImm();
18690 Op = MI->getOperand(3);
18691 if (Op.isGlobal()) {
18692 AM.GV = Op.getGlobal();
18694 AM.Disp = Op.getImm();
18696 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18697 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18699 // Reload the original control word now.
18700 addFrameReference(BuildMI(*BB, MI, DL,
18701 TII->get(X86::FLDCW16m)), CWFrameIdx);
18703 MI->eraseFromParent(); // The pseudo instruction is gone now.
18706 // String/text processing lowering.
18707 case X86::PCMPISTRM128REG:
18708 case X86::VPCMPISTRM128REG:
18709 case X86::PCMPISTRM128MEM:
18710 case X86::VPCMPISTRM128MEM:
18711 case X86::PCMPESTRM128REG:
18712 case X86::VPCMPESTRM128REG:
18713 case X86::PCMPESTRM128MEM:
18714 case X86::VPCMPESTRM128MEM:
18715 assert(Subtarget->hasSSE42() &&
18716 "Target must have SSE4.2 or AVX features enabled");
18717 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18719 // String/text processing lowering.
18720 case X86::PCMPISTRIREG:
18721 case X86::VPCMPISTRIREG:
18722 case X86::PCMPISTRIMEM:
18723 case X86::VPCMPISTRIMEM:
18724 case X86::PCMPESTRIREG:
18725 case X86::VPCMPESTRIREG:
18726 case X86::PCMPESTRIMEM:
18727 case X86::VPCMPESTRIMEM:
18728 assert(Subtarget->hasSSE42() &&
18729 "Target must have SSE4.2 or AVX features enabled");
18730 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18732 // Thread synchronization.
18734 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
18739 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18741 case X86::VASTART_SAVE_XMM_REGS:
18742 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18744 case X86::VAARG_64:
18745 return EmitVAARG64WithCustomInserter(MI, BB);
18747 case X86::EH_SjLj_SetJmp32:
18748 case X86::EH_SjLj_SetJmp64:
18749 return emitEHSjLjSetJmp(MI, BB);
18751 case X86::EH_SjLj_LongJmp32:
18752 case X86::EH_SjLj_LongJmp64:
18753 return emitEHSjLjLongJmp(MI, BB);
18755 case TargetOpcode::STACKMAP:
18756 case TargetOpcode::PATCHPOINT:
18757 return emitPatchPoint(MI, BB);
18759 case X86::VFMADDPDr213r:
18760 case X86::VFMADDPSr213r:
18761 case X86::VFMADDSDr213r:
18762 case X86::VFMADDSSr213r:
18763 case X86::VFMSUBPDr213r:
18764 case X86::VFMSUBPSr213r:
18765 case X86::VFMSUBSDr213r:
18766 case X86::VFMSUBSSr213r:
18767 case X86::VFNMADDPDr213r:
18768 case X86::VFNMADDPSr213r:
18769 case X86::VFNMADDSDr213r:
18770 case X86::VFNMADDSSr213r:
18771 case X86::VFNMSUBPDr213r:
18772 case X86::VFNMSUBPSr213r:
18773 case X86::VFNMSUBSDr213r:
18774 case X86::VFNMSUBSSr213r:
18775 case X86::VFMADDPDr213rY:
18776 case X86::VFMADDPSr213rY:
18777 case X86::VFMSUBPDr213rY:
18778 case X86::VFMSUBPSr213rY:
18779 case X86::VFNMADDPDr213rY:
18780 case X86::VFNMADDPSr213rY:
18781 case X86::VFNMSUBPDr213rY:
18782 case X86::VFNMSUBPSr213rY:
18783 return emitFMA3Instr(MI, BB);
18787 //===----------------------------------------------------------------------===//
18788 // X86 Optimization Hooks
18789 //===----------------------------------------------------------------------===//
18791 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18794 const SelectionDAG &DAG,
18795 unsigned Depth) const {
18796 unsigned BitWidth = KnownZero.getBitWidth();
18797 unsigned Opc = Op.getOpcode();
18798 assert((Opc >= ISD::BUILTIN_OP_END ||
18799 Opc == ISD::INTRINSIC_WO_CHAIN ||
18800 Opc == ISD::INTRINSIC_W_CHAIN ||
18801 Opc == ISD::INTRINSIC_VOID) &&
18802 "Should use MaskedValueIsZero if you don't know whether Op"
18803 " is a target node!");
18805 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18819 // These nodes' second result is a boolean.
18820 if (Op.getResNo() == 0)
18823 case X86ISD::SETCC:
18824 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18826 case ISD::INTRINSIC_WO_CHAIN: {
18827 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18828 unsigned NumLoBits = 0;
18831 case Intrinsic::x86_sse_movmsk_ps:
18832 case Intrinsic::x86_avx_movmsk_ps_256:
18833 case Intrinsic::x86_sse2_movmsk_pd:
18834 case Intrinsic::x86_avx_movmsk_pd_256:
18835 case Intrinsic::x86_mmx_pmovmskb:
18836 case Intrinsic::x86_sse2_pmovmskb_128:
18837 case Intrinsic::x86_avx2_pmovmskb: {
18838 // High bits of movmskp{s|d}, pmovmskb are known zero.
18840 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18841 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18842 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18843 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18844 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18845 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18846 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18847 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18849 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18858 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18860 const SelectionDAG &,
18861 unsigned Depth) const {
18862 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18863 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18864 return Op.getValueType().getScalarType().getSizeInBits();
18870 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18871 /// node is a GlobalAddress + offset.
18872 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18873 const GlobalValue* &GA,
18874 int64_t &Offset) const {
18875 if (N->getOpcode() == X86ISD::Wrapper) {
18876 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18877 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18878 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18882 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18885 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18886 /// same as extracting the high 128-bit part of 256-bit vector and then
18887 /// inserting the result into the low part of a new 256-bit vector
18888 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18889 EVT VT = SVOp->getValueType(0);
18890 unsigned NumElems = VT.getVectorNumElements();
18892 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18893 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18894 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18895 SVOp->getMaskElt(j) >= 0)
18901 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18902 /// same as extracting the low 128-bit part of 256-bit vector and then
18903 /// inserting the result into the high part of a new 256-bit vector
18904 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18905 EVT VT = SVOp->getValueType(0);
18906 unsigned NumElems = VT.getVectorNumElements();
18908 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18909 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18910 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18911 SVOp->getMaskElt(j) >= 0)
18917 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18918 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18919 TargetLowering::DAGCombinerInfo &DCI,
18920 const X86Subtarget* Subtarget) {
18922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18923 SDValue V1 = SVOp->getOperand(0);
18924 SDValue V2 = SVOp->getOperand(1);
18925 EVT VT = SVOp->getValueType(0);
18926 unsigned NumElems = VT.getVectorNumElements();
18928 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18929 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18933 // V UNDEF BUILD_VECTOR UNDEF
18935 // CONCAT_VECTOR CONCAT_VECTOR
18938 // RESULT: V + zero extended
18940 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18941 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18942 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18945 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
18948 // To match the shuffle mask, the first half of the mask should
18949 // be exactly the first vector, and all the rest a splat with the
18950 // first element of the second one.
18951 for (unsigned i = 0; i != NumElems/2; ++i)
18952 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
18953 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
18956 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
18957 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
18958 if (Ld->hasNUsesOfValue(1, 0)) {
18959 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
18960 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
18962 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
18964 Ld->getPointerInfo(),
18965 Ld->getAlignment(),
18966 false/*isVolatile*/, true/*ReadMem*/,
18967 false/*WriteMem*/);
18969 // Make sure the newly-created LOAD is in the same position as Ld in
18970 // terms of dependency. We create a TokenFactor for Ld and ResNode,
18971 // and update uses of Ld's output chain to use the TokenFactor.
18972 if (Ld->hasAnyUseOfValue(1)) {
18973 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18974 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
18975 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
18976 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
18977 SDValue(ResNode.getNode(), 1));
18980 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
18984 // Emit a zeroed vector and insert the desired subvector on its
18986 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18987 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
18988 return DCI.CombineTo(N, InsV);
18991 //===--------------------------------------------------------------------===//
18992 // Combine some shuffles into subvector extracts and inserts:
18995 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18996 if (isShuffleHigh128VectorInsertLow(SVOp)) {
18997 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
18998 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
18999 return DCI.CombineTo(N, InsV);
19002 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19003 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19004 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19005 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19006 return DCI.CombineTo(N, InsV);
19012 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19015 /// This is the leaf of the recursive combinine below. When we have found some
19016 /// chain of single-use x86 shuffle instructions and accumulated the combined
19017 /// shuffle mask represented by them, this will try to pattern match that mask
19018 /// into either a single instruction if there is a special purpose instruction
19019 /// for this operation, or into a PSHUFB instruction which is a fully general
19020 /// instruction but should only be used to replace chains over a certain depth.
19021 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19022 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19023 TargetLowering::DAGCombinerInfo &DCI,
19024 const X86Subtarget *Subtarget) {
19025 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19027 // Find the operand that enters the chain. Note that multiple uses are OK
19028 // here, we're not going to remove the operand we find.
19029 SDValue Input = Op.getOperand(0);
19030 while (Input.getOpcode() == ISD::BITCAST)
19031 Input = Input.getOperand(0);
19033 MVT VT = Input.getSimpleValueType();
19034 MVT RootVT = Root.getSimpleValueType();
19037 // Just remove no-op shuffle masks.
19038 if (Mask.size() == 1) {
19039 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19044 // Use the float domain if the operand type is a floating point type.
19045 bool FloatDomain = VT.isFloatingPoint();
19047 // If we don't have access to VEX encodings, the generic PSHUF instructions
19048 // are preferable to some of the specialized forms despite requiring one more
19049 // byte to encode because they can implicitly copy.
19051 // IF we *do* have VEX encodings, than we can use shorter, more specific
19052 // shuffle instructions freely as they can copy due to the extra register
19054 if (Subtarget->hasAVX()) {
19055 // We have both floating point and integer variants of shuffles that dup
19056 // either the low or high half of the vector.
19057 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19058 bool Lo = Mask.equals(0, 0);
19059 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
19060 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
19061 if (Depth == 1 && Root->getOpcode() == Shuffle)
19062 return false; // Nothing to do!
19063 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
19064 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19065 DCI.AddToWorklist(Op.getNode());
19066 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19067 DCI.AddToWorklist(Op.getNode());
19068 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19073 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
19075 // For the integer domain we have specialized instructions for duplicating
19076 // any element size from the low or high half.
19077 if (!FloatDomain &&
19078 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
19079 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19080 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19081 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19082 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19084 bool Lo = Mask[0] == 0;
19085 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19086 if (Depth == 1 && Root->getOpcode() == Shuffle)
19087 return false; // Nothing to do!
19089 switch (Mask.size()) {
19090 case 4: ShuffleVT = MVT::v4i32; break;
19091 case 8: ShuffleVT = MVT::v8i16; break;
19092 case 16: ShuffleVT = MVT::v16i8; break;
19094 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19095 DCI.AddToWorklist(Op.getNode());
19096 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19097 DCI.AddToWorklist(Op.getNode());
19098 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19104 // Don't try to re-form single instruction chains under any circumstances now
19105 // that we've done encoding canonicalization for them.
19109 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19110 // can replace them with a single PSHUFB instruction profitably. Intel's
19111 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19112 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19113 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19114 SmallVector<SDValue, 16> PSHUFBMask;
19115 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19116 int Ratio = 16 / Mask.size();
19117 for (unsigned i = 0; i < 16; ++i) {
19118 int M = Ratio * Mask[i / Ratio] + i % Ratio;
19119 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19121 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19122 DCI.AddToWorklist(Op.getNode());
19123 SDValue PSHUFBMaskOp =
19124 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19125 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19126 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19127 DCI.AddToWorklist(Op.getNode());
19128 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19133 // Failed to find any combines.
19137 /// \brief Fully generic combining of x86 shuffle instructions.
19139 /// This should be the last combine run over the x86 shuffle instructions. Once
19140 /// they have been fully optimized, this will recursively consdier all chains
19141 /// of single-use shuffle instructions, build a generic model of the cumulative
19142 /// shuffle operation, and check for simpler instructions which implement this
19143 /// operation. We use this primarily for two purposes:
19145 /// 1) Collapse generic shuffles to specialized single instructions when
19146 /// equivalent. In most cases, this is just an encoding size win, but
19147 /// sometimes we will collapse multiple generic shuffles into a single
19148 /// special-purpose shuffle.
19149 /// 2) Look for sequences of shuffle instructions with 3 or more total
19150 /// instructions, and replace them with the slightly more expensive SSSE3
19151 /// PSHUFB instruction if available. We do this as the last combining step
19152 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19153 /// a suitable short sequence of other instructions. The PHUFB will either
19154 /// use a register or have to read from memory and so is slightly (but only
19155 /// slightly) more expensive than the other shuffle instructions.
19157 /// Because this is inherently a quadratic operation (for each shuffle in
19158 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19159 /// This should never be an issue in practice as the shuffle lowering doesn't
19160 /// produce sequences of more than 8 instructions.
19162 /// FIXME: We will currently miss some cases where the redundant shuffling
19163 /// would simplify under the threshold for PSHUFB formation because of
19164 /// combine-ordering. To fix this, we should do the redundant instruction
19165 /// combining in this recursive walk.
19166 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19167 ArrayRef<int> IncomingMask, int Depth,
19168 bool HasPSHUFB, SelectionDAG &DAG,
19169 TargetLowering::DAGCombinerInfo &DCI,
19170 const X86Subtarget *Subtarget) {
19171 // Bound the depth of our recursive combine because this is ultimately
19172 // quadratic in nature.
19176 // Directly rip through bitcasts to find the underlying operand.
19177 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19178 Op = Op.getOperand(0);
19180 MVT VT = Op.getSimpleValueType();
19181 if (!VT.isVector())
19182 return false; // Bail if we hit a non-vector.
19183 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19184 // version should be added.
19185 if (VT.getSizeInBits() != 128)
19188 assert(Root.getSimpleValueType().isVector() &&
19189 "Shuffles operate on vector types!");
19190 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19191 "Can only combine shuffles of the same vector register size.");
19193 if (!isTargetShuffle(Op.getOpcode()))
19195 SmallVector<int, 16> OpMask;
19197 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19198 // We only can combine unary shuffles which we can decode the mask for.
19199 if (!HaveMask || !IsUnary)
19202 assert(VT.getVectorNumElements() == OpMask.size() &&
19203 "Different mask size from vector size!");
19205 SmallVector<int, 16> Mask;
19206 Mask.reserve(std::max(OpMask.size(), IncomingMask.size()));
19208 // Merge this shuffle operation's mask into our accumulated mask. This is
19209 // a bit tricky as the shuffle may have a different size from the root.
19210 if (OpMask.size() == IncomingMask.size()) {
19211 for (int M : IncomingMask)
19212 Mask.push_back(OpMask[M]);
19213 } else if (OpMask.size() < IncomingMask.size()) {
19214 assert(IncomingMask.size() % OpMask.size() == 0 &&
19215 "The smaller number of elements must divide the larger.");
19216 int Ratio = IncomingMask.size() / OpMask.size();
19217 for (int M : IncomingMask)
19218 Mask.push_back(Ratio * OpMask[M / Ratio] + M % Ratio);
19220 assert(OpMask.size() > IncomingMask.size() && "All other cases handled!");
19221 assert(OpMask.size() % IncomingMask.size() == 0 &&
19222 "The smaller number of elements must divide the larger.");
19223 int Ratio = OpMask.size() / IncomingMask.size();
19224 for (int i = 0, e = OpMask.size(); i < e; ++i)
19225 Mask.push_back(OpMask[Ratio * IncomingMask[i / Ratio] + i % Ratio]);
19228 // See if we can recurse into the operand to combine more things.
19229 switch (Op.getOpcode()) {
19230 case X86ISD::PSHUFB:
19232 case X86ISD::PSHUFD:
19233 case X86ISD::PSHUFHW:
19234 case X86ISD::PSHUFLW:
19235 if (Op.getOperand(0).hasOneUse() &&
19236 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19237 HasPSHUFB, DAG, DCI, Subtarget))
19241 case X86ISD::UNPCKL:
19242 case X86ISD::UNPCKH:
19243 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19244 // We can't check for single use, we have to check that this shuffle is the only user.
19245 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19246 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19247 HasPSHUFB, DAG, DCI, Subtarget))
19252 // Minor canonicalization of the accumulated shuffle mask to make it easier
19253 // to match below. All this does is detect masks with squential pairs of
19254 // elements, and shrink them to the half-width mask. It does this in a loop
19255 // so it will reduce the size of the mask to the minimal width mask which
19256 // performs an equivalent shuffle.
19257 while (Mask.size() > 1) {
19258 SmallVector<int, 16> NewMask;
19259 for (int i = 0, e = Mask.size()/2; i < e; ++i) {
19260 if (Mask[2*i] % 2 != 0 || Mask[2*i] != Mask[2*i + 1] + 1) {
19264 NewMask.push_back(Mask[2*i] / 2);
19266 if (NewMask.empty())
19268 Mask.swap(NewMask);
19271 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19275 /// \brief Get the PSHUF-style mask from PSHUF node.
19277 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19278 /// PSHUF-style masks that can be reused with such instructions.
19279 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19280 SmallVector<int, 4> Mask;
19282 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19286 switch (N.getOpcode()) {
19287 case X86ISD::PSHUFD:
19289 case X86ISD::PSHUFLW:
19292 case X86ISD::PSHUFHW:
19293 Mask.erase(Mask.begin(), Mask.begin() + 4);
19294 for (int &M : Mask)
19298 llvm_unreachable("No valid shuffle instruction found!");
19302 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19304 /// We walk up the chain and look for a combinable shuffle, skipping over
19305 /// shuffles that we could hoist this shuffle's transformation past without
19306 /// altering anything.
19307 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19309 TargetLowering::DAGCombinerInfo &DCI) {
19310 assert(N.getOpcode() == X86ISD::PSHUFD &&
19311 "Called with something other than an x86 128-bit half shuffle!");
19314 // Walk up a single-use chain looking for a combinable shuffle.
19315 SDValue V = N.getOperand(0);
19316 for (; V.hasOneUse(); V = V.getOperand(0)) {
19317 switch (V.getOpcode()) {
19319 return false; // Nothing combined!
19322 // Skip bitcasts as we always know the type for the target specific
19326 case X86ISD::PSHUFD:
19327 // Found another dword shuffle.
19330 case X86ISD::PSHUFLW:
19331 // Check that the low words (being shuffled) are the identity in the
19332 // dword shuffle, and the high words are self-contained.
19333 if (Mask[0] != 0 || Mask[1] != 1 ||
19334 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19339 case X86ISD::PSHUFHW:
19340 // Check that the high words (being shuffled) are the identity in the
19341 // dword shuffle, and the low words are self-contained.
19342 if (Mask[2] != 2 || Mask[3] != 3 ||
19343 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19348 case X86ISD::UNPCKL:
19349 case X86ISD::UNPCKH:
19350 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19351 // shuffle into a preceding word shuffle.
19352 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19355 // Search for a half-shuffle which we can combine with.
19356 unsigned CombineOp =
19357 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19358 if (V.getOperand(0) != V.getOperand(1) ||
19359 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19361 V = V.getOperand(0);
19363 switch (V.getOpcode()) {
19365 return false; // Nothing to combine.
19367 case X86ISD::PSHUFLW:
19368 case X86ISD::PSHUFHW:
19369 if (V.getOpcode() == CombineOp)
19374 V = V.getOperand(0);
19378 } while (V.hasOneUse());
19381 // Break out of the loop if we break out of the switch.
19385 if (!V.hasOneUse())
19386 // We fell out of the loop without finding a viable combining instruction.
19389 // Record the old value to use in RAUW-ing.
19392 // Merge this node's mask and our incoming mask.
19393 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19394 for (int &M : Mask)
19396 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19397 getV4X86ShuffleImm8ForMask(Mask, DAG));
19399 // It is possible that one of the combinable shuffles was completely absorbed
19400 // by the other, just replace it and revisit all users in that case.
19401 if (Old.getNode() == V.getNode()) {
19402 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
19406 // Replace N with its operand as we're going to combine that shuffle away.
19407 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
19409 // Replace the combinable shuffle with the combined one, updating all users
19410 // so that we re-evaluate the chain here.
19411 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19415 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19417 /// We walk up the chain, skipping shuffles of the other half and looking
19418 /// through shuffles which switch halves trying to find a shuffle of the same
19419 /// pair of dwords.
19420 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19422 TargetLowering::DAGCombinerInfo &DCI) {
19424 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19425 "Called with something other than an x86 128-bit half shuffle!");
19427 unsigned CombineOpcode = N.getOpcode();
19429 // Walk up a single-use chain looking for a combinable shuffle.
19430 SDValue V = N.getOperand(0);
19431 for (; V.hasOneUse(); V = V.getOperand(0)) {
19432 switch (V.getOpcode()) {
19434 return false; // Nothing combined!
19437 // Skip bitcasts as we always know the type for the target specific
19441 case X86ISD::PSHUFLW:
19442 case X86ISD::PSHUFHW:
19443 if (V.getOpcode() == CombineOpcode)
19446 // Other-half shuffles are no-ops.
19449 // Break out of the loop if we break out of the switch.
19453 if (!V.hasOneUse())
19454 // We fell out of the loop without finding a viable combining instruction.
19457 // Combine away the bottom node as its shuffle will be accumulated into
19458 // a preceding shuffle.
19459 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19461 // Record the old value.
19464 // Merge this node's mask and our incoming mask (adjusted to account for all
19465 // the pshufd instructions encountered).
19466 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19467 for (int &M : Mask)
19469 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19470 getV4X86ShuffleImm8ForMask(Mask, DAG));
19472 // Check that the shuffles didn't cancel each other out. If not, we need to
19473 // combine to the new one.
19475 // Replace the combinable shuffle with the combined one, updating all users
19476 // so that we re-evaluate the chain here.
19477 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19482 /// \brief Try to combine x86 target specific shuffles.
19483 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19484 TargetLowering::DAGCombinerInfo &DCI,
19485 const X86Subtarget *Subtarget) {
19487 MVT VT = N.getSimpleValueType();
19488 SmallVector<int, 4> Mask;
19490 switch (N.getOpcode()) {
19491 case X86ISD::PSHUFD:
19492 case X86ISD::PSHUFLW:
19493 case X86ISD::PSHUFHW:
19494 Mask = getPSHUFShuffleMask(N);
19495 assert(Mask.size() == 4);
19501 // Nuke no-op shuffles that show up after combining.
19502 if (isNoopShuffleMask(Mask))
19503 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19505 // Look for simplifications involving one or two shuffle instructions.
19506 SDValue V = N.getOperand(0);
19507 switch (N.getOpcode()) {
19510 case X86ISD::PSHUFLW:
19511 case X86ISD::PSHUFHW:
19512 assert(VT == MVT::v8i16);
19515 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19516 return SDValue(); // We combined away this shuffle, so we're done.
19518 // See if this reduces to a PSHUFD which is no more expensive and can
19519 // combine with more operations.
19520 if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
19521 areAdjacentMasksSequential(Mask)) {
19522 int DMask[] = {-1, -1, -1, -1};
19523 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19524 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19525 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19526 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19527 DCI.AddToWorklist(V.getNode());
19528 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19529 getV4X86ShuffleImm8ForMask(DMask, DAG));
19530 DCI.AddToWorklist(V.getNode());
19531 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19534 // Look for shuffle patterns which can be implemented as a single unpack.
19535 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19536 // only works when we have a PSHUFD followed by two half-shuffles.
19537 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19538 (V.getOpcode() == X86ISD::PSHUFLW ||
19539 V.getOpcode() == X86ISD::PSHUFHW) &&
19540 V.getOpcode() != N.getOpcode() &&
19542 SDValue D = V.getOperand(0);
19543 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19544 D = D.getOperand(0);
19545 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19546 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19547 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19548 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19549 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19551 for (int i = 0; i < 4; ++i) {
19552 WordMask[i + NOffset] = Mask[i] + NOffset;
19553 WordMask[i + VOffset] = VMask[i] + VOffset;
19555 // Map the word mask through the DWord mask.
19557 for (int i = 0; i < 8; ++i)
19558 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19559 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19560 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19561 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19562 std::begin(UnpackLoMask)) ||
19563 std::equal(std::begin(MappedMask), std::end(MappedMask),
19564 std::begin(UnpackHiMask))) {
19565 // We can replace all three shuffles with an unpack.
19566 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19567 DCI.AddToWorklist(V.getNode());
19568 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19570 DL, MVT::v8i16, V, V);
19577 case X86ISD::PSHUFD:
19578 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19579 return SDValue(); // We combined away this shuffle.
19587 /// PerformShuffleCombine - Performs several different shuffle combines.
19588 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19589 TargetLowering::DAGCombinerInfo &DCI,
19590 const X86Subtarget *Subtarget) {
19592 SDValue N0 = N->getOperand(0);
19593 SDValue N1 = N->getOperand(1);
19594 EVT VT = N->getValueType(0);
19596 // Don't create instructions with illegal types after legalize types has run.
19597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19598 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19601 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19602 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19603 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19604 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19606 // During Type Legalization, when promoting illegal vector types,
19607 // the backend might introduce new shuffle dag nodes and bitcasts.
19609 // This code performs the following transformation:
19610 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19611 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19613 // We do this only if both the bitcast and the BINOP dag nodes have
19614 // one use. Also, perform this transformation only if the new binary
19615 // operation is legal. This is to avoid introducing dag nodes that
19616 // potentially need to be further expanded (or custom lowered) into a
19617 // less optimal sequence of dag nodes.
19618 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19619 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19620 N0.getOpcode() == ISD::BITCAST) {
19621 SDValue BC0 = N0.getOperand(0);
19622 EVT SVT = BC0.getValueType();
19623 unsigned Opcode = BC0.getOpcode();
19624 unsigned NumElts = VT.getVectorNumElements();
19626 if (BC0.hasOneUse() && SVT.isVector() &&
19627 SVT.getVectorNumElements() * 2 == NumElts &&
19628 TLI.isOperationLegal(Opcode, VT)) {
19629 bool CanFold = false;
19641 unsigned SVTNumElts = SVT.getVectorNumElements();
19642 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19643 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19644 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19645 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19646 CanFold = SVOp->getMaskElt(i) < 0;
19649 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19650 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19651 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19652 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
19657 // Only handle 128 wide vector from here on.
19658 if (!VT.is128BitVector())
19661 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19662 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
19663 // consecutive, non-overlapping, and in the right order.
19664 SmallVector<SDValue, 16> Elts;
19665 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
19666 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
19668 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
19672 if (isTargetShuffle(N->getOpcode())) {
19674 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
19675 if (Shuffle.getNode())
19678 // Try recursively combining arbitrary sequences of x86 shuffle
19679 // instructions into higher-order shuffles. We do this after combining
19680 // specific PSHUF instruction sequences into their minimal form so that we
19681 // can evaluate how many specialized shuffle instructions are involved in
19682 // a particular chain.
19683 SmallVector<int, 1> NonceMask; // Just a placeholder.
19684 NonceMask.push_back(0);
19685 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
19686 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
19688 return SDValue(); // This routine will use CombineTo to replace N.
19694 /// PerformTruncateCombine - Converts truncate operation to
19695 /// a sequence of vector shuffle operations.
19696 /// It is possible when we truncate 256-bit vector to 128-bit vector
19697 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
19698 TargetLowering::DAGCombinerInfo &DCI,
19699 const X86Subtarget *Subtarget) {
19703 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
19704 /// specific shuffle of a load can be folded into a single element load.
19705 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
19706 /// shuffles have been customed lowered so we need to handle those here.
19707 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
19708 TargetLowering::DAGCombinerInfo &DCI) {
19709 if (DCI.isBeforeLegalizeOps())
19712 SDValue InVec = N->getOperand(0);
19713 SDValue EltNo = N->getOperand(1);
19715 if (!isa<ConstantSDNode>(EltNo))
19718 EVT VT = InVec.getValueType();
19720 bool HasShuffleIntoBitcast = false;
19721 if (InVec.getOpcode() == ISD::BITCAST) {
19722 // Don't duplicate a load with other uses.
19723 if (!InVec.hasOneUse())
19725 EVT BCVT = InVec.getOperand(0).getValueType();
19726 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
19728 InVec = InVec.getOperand(0);
19729 HasShuffleIntoBitcast = true;
19732 if (!isTargetShuffle(InVec.getOpcode()))
19735 // Don't duplicate a load with other uses.
19736 if (!InVec.hasOneUse())
19739 SmallVector<int, 16> ShuffleMask;
19741 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
19745 // Select the input vector, guarding against out of range extract vector.
19746 unsigned NumElems = VT.getVectorNumElements();
19747 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
19748 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
19749 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
19750 : InVec.getOperand(1);
19752 // If inputs to shuffle are the same for both ops, then allow 2 uses
19753 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
19755 if (LdNode.getOpcode() == ISD::BITCAST) {
19756 // Don't duplicate a load with other uses.
19757 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
19760 AllowedUses = 1; // only allow 1 load use if we have a bitcast
19761 LdNode = LdNode.getOperand(0);
19764 if (!ISD::isNormalLoad(LdNode.getNode()))
19767 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
19769 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
19772 if (HasShuffleIntoBitcast) {
19773 // If there's a bitcast before the shuffle, check if the load type and
19774 // alignment is valid.
19775 unsigned Align = LN0->getAlignment();
19776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19777 unsigned NewAlign = TLI.getDataLayout()->
19778 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
19780 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
19784 // All checks match so transform back to vector_shuffle so that DAG combiner
19785 // can finish the job
19788 // Create shuffle node taking into account the case that its a unary shuffle
19789 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
19790 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
19791 InVec.getOperand(0), Shuffle,
19793 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
19794 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
19798 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
19799 /// generation and convert it from being a bunch of shuffles and extracts
19800 /// to a simple store and scalar loads to extract the elements.
19801 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
19802 TargetLowering::DAGCombinerInfo &DCI) {
19803 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
19804 if (NewOp.getNode())
19807 SDValue InputVector = N->getOperand(0);
19809 // Detect whether we are trying to convert from mmx to i32 and the bitcast
19810 // from mmx to v2i32 has a single usage.
19811 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
19812 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
19813 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
19814 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
19815 N->getValueType(0),
19816 InputVector.getNode()->getOperand(0));
19818 // Only operate on vectors of 4 elements, where the alternative shuffling
19819 // gets to be more expensive.
19820 if (InputVector.getValueType() != MVT::v4i32)
19823 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
19824 // single use which is a sign-extend or zero-extend, and all elements are
19826 SmallVector<SDNode *, 4> Uses;
19827 unsigned ExtractedElements = 0;
19828 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
19829 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
19830 if (UI.getUse().getResNo() != InputVector.getResNo())
19833 SDNode *Extract = *UI;
19834 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
19837 if (Extract->getValueType(0) != MVT::i32)
19839 if (!Extract->hasOneUse())
19841 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
19842 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
19844 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
19847 // Record which element was extracted.
19848 ExtractedElements |=
19849 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
19851 Uses.push_back(Extract);
19854 // If not all the elements were used, this may not be worthwhile.
19855 if (ExtractedElements != 15)
19858 // Ok, we've now decided to do the transformation.
19859 SDLoc dl(InputVector);
19861 // Store the value to a temporary stack slot.
19862 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
19863 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
19864 MachinePointerInfo(), false, false, 0);
19866 // Replace each use (extract) with a load of the appropriate element.
19867 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
19868 UE = Uses.end(); UI != UE; ++UI) {
19869 SDNode *Extract = *UI;
19871 // cOMpute the element's address.
19872 SDValue Idx = Extract->getOperand(1);
19874 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
19875 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
19876 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19877 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
19879 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
19880 StackPtr, OffsetVal);
19882 // Load the scalar.
19883 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
19884 ScalarAddr, MachinePointerInfo(),
19885 false, false, false, 0);
19887 // Replace the exact with the load.
19888 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
19891 // The replacement was made in place; don't return anything.
19895 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
19896 static std::pair<unsigned, bool>
19897 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
19898 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
19899 if (!VT.isVector())
19900 return std::make_pair(0, false);
19902 bool NeedSplit = false;
19903 switch (VT.getSimpleVT().SimpleTy) {
19904 default: return std::make_pair(0, false);
19908 if (!Subtarget->hasAVX2())
19910 if (!Subtarget->hasAVX())
19911 return std::make_pair(0, false);
19916 if (!Subtarget->hasSSE2())
19917 return std::make_pair(0, false);
19920 // SSE2 has only a small subset of the operations.
19921 bool hasUnsigned = Subtarget->hasSSE41() ||
19922 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19923 bool hasSigned = Subtarget->hasSSE41() ||
19924 (Subtarget->hasSSE2() && VT == MVT::v8i16);
19926 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19929 // Check for x CC y ? x : y.
19930 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19931 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19936 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19939 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19942 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19945 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19947 // Check for x CC y ? y : x -- a min/max with reversed arms.
19948 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19949 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19954 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19957 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19960 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19963 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19967 return std::make_pair(Opc, NeedSplit);
19971 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
19972 const X86Subtarget *Subtarget) {
19974 SDValue Cond = N->getOperand(0);
19975 SDValue LHS = N->getOperand(1);
19976 SDValue RHS = N->getOperand(2);
19978 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19979 SDValue CondSrc = Cond->getOperand(0);
19980 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
19981 Cond = CondSrc->getOperand(0);
19984 MVT VT = N->getSimpleValueType(0);
19985 MVT EltVT = VT.getVectorElementType();
19986 unsigned NumElems = VT.getVectorNumElements();
19987 // There is no blend with immediate in AVX-512.
19988 if (VT.is512BitVector())
19991 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
19993 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19996 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
19999 unsigned MaskValue = 0;
20000 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20003 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20004 for (unsigned i = 0; i < NumElems; ++i) {
20005 // Be sure we emit undef where we can.
20006 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20007 ShuffleMask[i] = -1;
20009 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20012 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20015 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20017 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20018 TargetLowering::DAGCombinerInfo &DCI,
20019 const X86Subtarget *Subtarget) {
20021 SDValue Cond = N->getOperand(0);
20022 // Get the LHS/RHS of the select.
20023 SDValue LHS = N->getOperand(1);
20024 SDValue RHS = N->getOperand(2);
20025 EVT VT = LHS.getValueType();
20026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20028 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20029 // instructions match the semantics of the common C idiom x<y?x:y but not
20030 // x<=y?x:y, because of how they handle negative zero (which can be
20031 // ignored in unsafe-math mode).
20032 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20033 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20034 (Subtarget->hasSSE2() ||
20035 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20036 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20038 unsigned Opcode = 0;
20039 // Check for x CC y ? x : y.
20040 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20041 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20045 // Converting this to a min would handle NaNs incorrectly, and swapping
20046 // the operands would cause it to handle comparisons between positive
20047 // and negative zero incorrectly.
20048 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20049 if (!DAG.getTarget().Options.UnsafeFPMath &&
20050 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20052 std::swap(LHS, RHS);
20054 Opcode = X86ISD::FMIN;
20057 // Converting this to a min would handle comparisons between positive
20058 // and negative zero incorrectly.
20059 if (!DAG.getTarget().Options.UnsafeFPMath &&
20060 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20062 Opcode = X86ISD::FMIN;
20065 // Converting this to a min would handle both negative zeros and NaNs
20066 // incorrectly, but we can swap the operands to fix both.
20067 std::swap(LHS, RHS);
20071 Opcode = X86ISD::FMIN;
20075 // Converting this to a max would handle comparisons between positive
20076 // and negative zero incorrectly.
20077 if (!DAG.getTarget().Options.UnsafeFPMath &&
20078 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20080 Opcode = X86ISD::FMAX;
20083 // Converting this to a max would handle NaNs incorrectly, and swapping
20084 // the operands would cause it to handle comparisons between positive
20085 // and negative zero incorrectly.
20086 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20087 if (!DAG.getTarget().Options.UnsafeFPMath &&
20088 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20090 std::swap(LHS, RHS);
20092 Opcode = X86ISD::FMAX;
20095 // Converting this to a max would handle both negative zeros and NaNs
20096 // incorrectly, but we can swap the operands to fix both.
20097 std::swap(LHS, RHS);
20101 Opcode = X86ISD::FMAX;
20104 // Check for x CC y ? y : x -- a min/max with reversed arms.
20105 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20106 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20110 // Converting this to a min would handle comparisons between positive
20111 // and negative zero incorrectly, and swapping the operands would
20112 // cause it to handle NaNs incorrectly.
20113 if (!DAG.getTarget().Options.UnsafeFPMath &&
20114 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20115 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20117 std::swap(LHS, RHS);
20119 Opcode = X86ISD::FMIN;
20122 // Converting this to a min would handle NaNs incorrectly.
20123 if (!DAG.getTarget().Options.UnsafeFPMath &&
20124 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20126 Opcode = X86ISD::FMIN;
20129 // Converting this to a min would handle both negative zeros and NaNs
20130 // incorrectly, but we can swap the operands to fix both.
20131 std::swap(LHS, RHS);
20135 Opcode = X86ISD::FMIN;
20139 // Converting this to a max would handle NaNs incorrectly.
20140 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20142 Opcode = X86ISD::FMAX;
20145 // Converting this to a max would handle comparisons between positive
20146 // and negative zero incorrectly, and swapping the operands would
20147 // cause it to handle NaNs incorrectly.
20148 if (!DAG.getTarget().Options.UnsafeFPMath &&
20149 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20150 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20152 std::swap(LHS, RHS);
20154 Opcode = X86ISD::FMAX;
20157 // Converting this to a max would handle both negative zeros and NaNs
20158 // incorrectly, but we can swap the operands to fix both.
20159 std::swap(LHS, RHS);
20163 Opcode = X86ISD::FMAX;
20169 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20172 EVT CondVT = Cond.getValueType();
20173 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20174 CondVT.getVectorElementType() == MVT::i1) {
20175 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20176 // lowering on AVX-512. In this case we convert it to
20177 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20178 // The same situation for all 128 and 256-bit vectors of i8 and i16
20179 EVT OpVT = LHS.getValueType();
20180 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20181 (OpVT.getVectorElementType() == MVT::i8 ||
20182 OpVT.getVectorElementType() == MVT::i16)) {
20183 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20184 DCI.AddToWorklist(Cond.getNode());
20185 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20188 // If this is a select between two integer constants, try to do some
20190 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20191 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20192 // Don't do this for crazy integer types.
20193 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20194 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20195 // so that TrueC (the true value) is larger than FalseC.
20196 bool NeedsCondInvert = false;
20198 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20199 // Efficiently invertible.
20200 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20201 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20202 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20203 NeedsCondInvert = true;
20204 std::swap(TrueC, FalseC);
20207 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20208 if (FalseC->getAPIntValue() == 0 &&
20209 TrueC->getAPIntValue().isPowerOf2()) {
20210 if (NeedsCondInvert) // Invert the condition if needed.
20211 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20212 DAG.getConstant(1, Cond.getValueType()));
20214 // Zero extend the condition if needed.
20215 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20217 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20218 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20219 DAG.getConstant(ShAmt, MVT::i8));
20222 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20223 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20224 if (NeedsCondInvert) // Invert the condition if needed.
20225 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20226 DAG.getConstant(1, Cond.getValueType()));
20228 // Zero extend the condition if needed.
20229 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20230 FalseC->getValueType(0), Cond);
20231 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20232 SDValue(FalseC, 0));
20235 // Optimize cases that will turn into an LEA instruction. This requires
20236 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20237 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20238 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20239 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20241 bool isFastMultiplier = false;
20243 switch ((unsigned char)Diff) {
20245 case 1: // result = add base, cond
20246 case 2: // result = lea base( , cond*2)
20247 case 3: // result = lea base(cond, cond*2)
20248 case 4: // result = lea base( , cond*4)
20249 case 5: // result = lea base(cond, cond*4)
20250 case 8: // result = lea base( , cond*8)
20251 case 9: // result = lea base(cond, cond*8)
20252 isFastMultiplier = true;
20257 if (isFastMultiplier) {
20258 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20259 if (NeedsCondInvert) // Invert the condition if needed.
20260 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20261 DAG.getConstant(1, Cond.getValueType()));
20263 // Zero extend the condition if needed.
20264 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20266 // Scale the condition by the difference.
20268 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20269 DAG.getConstant(Diff, Cond.getValueType()));
20271 // Add the base if non-zero.
20272 if (FalseC->getAPIntValue() != 0)
20273 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20274 SDValue(FalseC, 0));
20281 // Canonicalize max and min:
20282 // (x > y) ? x : y -> (x >= y) ? x : y
20283 // (x < y) ? x : y -> (x <= y) ? x : y
20284 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20285 // the need for an extra compare
20286 // against zero. e.g.
20287 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20289 // testl %edi, %edi
20291 // cmovgl %edi, %eax
20295 // cmovsl %eax, %edi
20296 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20297 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20298 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20299 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20304 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20305 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20306 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20307 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20312 // Early exit check
20313 if (!TLI.isTypeLegal(VT))
20316 // Match VSELECTs into subs with unsigned saturation.
20317 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20318 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20319 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20320 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20321 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20323 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20324 // left side invert the predicate to simplify logic below.
20326 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20328 CC = ISD::getSetCCInverse(CC, true);
20329 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20333 if (Other.getNode() && Other->getNumOperands() == 2 &&
20334 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20335 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20336 SDValue CondRHS = Cond->getOperand(1);
20338 // Look for a general sub with unsigned saturation first.
20339 // x >= y ? x-y : 0 --> subus x, y
20340 // x > y ? x-y : 0 --> subus x, y
20341 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20342 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20343 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20345 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20346 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20347 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20348 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20349 // If the RHS is a constant we have to reverse the const
20350 // canonicalization.
20351 // x > C-1 ? x+-C : 0 --> subus x, C
20352 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20353 CondRHSConst->getAPIntValue() ==
20354 (-OpRHSConst->getAPIntValue() - 1))
20355 return DAG.getNode(
20356 X86ISD::SUBUS, DL, VT, OpLHS,
20357 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20359 // Another special case: If C was a sign bit, the sub has been
20360 // canonicalized into a xor.
20361 // FIXME: Would it be better to use computeKnownBits to determine
20362 // whether it's safe to decanonicalize the xor?
20363 // x s< 0 ? x^C : 0 --> subus x, C
20364 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20365 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20366 OpRHSConst->getAPIntValue().isSignBit())
20367 // Note that we have to rebuild the RHS constant here to ensure we
20368 // don't rely on particular values of undef lanes.
20369 return DAG.getNode(
20370 X86ISD::SUBUS, DL, VT, OpLHS,
20371 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20376 // Try to match a min/max vector operation.
20377 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20378 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20379 unsigned Opc = ret.first;
20380 bool NeedSplit = ret.second;
20382 if (Opc && NeedSplit) {
20383 unsigned NumElems = VT.getVectorNumElements();
20384 // Extract the LHS vectors
20385 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20386 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20388 // Extract the RHS vectors
20389 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20390 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20392 // Create min/max for each subvector
20393 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20394 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20396 // Merge the result
20397 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20399 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20402 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20403 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20404 // Check if SETCC has already been promoted
20405 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20406 // Check that condition value type matches vselect operand type
20409 assert(Cond.getValueType().isVector() &&
20410 "vector select expects a vector selector!");
20412 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20413 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20415 if (!TValIsAllOnes && !FValIsAllZeros) {
20416 // Try invert the condition if true value is not all 1s and false value
20418 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20419 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20421 if (TValIsAllZeros || FValIsAllOnes) {
20422 SDValue CC = Cond.getOperand(2);
20423 ISD::CondCode NewCC =
20424 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20425 Cond.getOperand(0).getValueType().isInteger());
20426 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20427 std::swap(LHS, RHS);
20428 TValIsAllOnes = FValIsAllOnes;
20429 FValIsAllZeros = TValIsAllZeros;
20433 if (TValIsAllOnes || FValIsAllZeros) {
20436 if (TValIsAllOnes && FValIsAllZeros)
20438 else if (TValIsAllOnes)
20439 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20440 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20441 else if (FValIsAllZeros)
20442 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20443 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20445 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20449 // Try to fold this VSELECT into a MOVSS/MOVSD
20450 if (N->getOpcode() == ISD::VSELECT &&
20451 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20452 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20453 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20454 bool CanFold = false;
20455 unsigned NumElems = Cond.getNumOperands();
20459 if (isZero(Cond.getOperand(0))) {
20462 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20463 // fold (vselect <0,-1> -> (movsd A, B)
20464 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20465 CanFold = isAllOnes(Cond.getOperand(i));
20466 } else if (isAllOnes(Cond.getOperand(0))) {
20470 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20471 // fold (vselect <-1,0> -> (movsd B, A)
20472 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20473 CanFold = isZero(Cond.getOperand(i));
20477 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20478 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20479 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20482 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20483 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20484 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20485 // (v2i64 (bitcast B)))))
20487 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20488 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20489 // (v2f64 (bitcast B)))))
20491 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20492 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20493 // (v2i64 (bitcast A)))))
20495 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20496 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20497 // (v2f64 (bitcast A)))))
20499 CanFold = (isZero(Cond.getOperand(0)) &&
20500 isZero(Cond.getOperand(1)) &&
20501 isAllOnes(Cond.getOperand(2)) &&
20502 isAllOnes(Cond.getOperand(3)));
20504 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20505 isAllOnes(Cond.getOperand(1)) &&
20506 isZero(Cond.getOperand(2)) &&
20507 isZero(Cond.getOperand(3))) {
20509 std::swap(LHS, RHS);
20513 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20514 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20515 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20516 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20518 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20524 // If we know that this node is legal then we know that it is going to be
20525 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20526 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20527 // to simplify previous instructions.
20528 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20529 !DCI.isBeforeLegalize() &&
20530 // We explicitly check against v8i16 and v16i16 because, although
20531 // they're marked as Custom, they might only be legal when Cond is a
20532 // build_vector of constants. This will be taken care in a later
20534 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20535 VT != MVT::v8i16)) {
20536 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20538 // Don't optimize vector selects that map to mask-registers.
20542 // Check all uses of that condition operand to check whether it will be
20543 // consumed by non-BLEND instructions, which may depend on all bits are set
20545 for (SDNode::use_iterator I = Cond->use_begin(),
20546 E = Cond->use_end(); I != E; ++I)
20547 if (I->getOpcode() != ISD::VSELECT)
20548 // TODO: Add other opcodes eventually lowered into BLEND.
20551 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20552 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20554 APInt KnownZero, KnownOne;
20555 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20556 DCI.isBeforeLegalizeOps());
20557 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20558 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20559 DCI.CommitTargetLoweringOpt(TLO);
20562 // We should generate an X86ISD::BLENDI from a vselect if its argument
20563 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20564 // constants. This specific pattern gets generated when we split a
20565 // selector for a 512 bit vector in a machine without AVX512 (but with
20566 // 256-bit vectors), during legalization:
20568 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20570 // Iff we find this pattern and the build_vectors are built from
20571 // constants, we translate the vselect into a shuffle_vector that we
20572 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20573 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20574 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20575 if (Shuffle.getNode())
20582 // Check whether a boolean test is testing a boolean value generated by
20583 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20586 // Simplify the following patterns:
20587 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20588 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20589 // to (Op EFLAGS Cond)
20591 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20592 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20593 // to (Op EFLAGS !Cond)
20595 // where Op could be BRCOND or CMOV.
20597 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20598 // Quit if not CMP and SUB with its value result used.
20599 if (Cmp.getOpcode() != X86ISD::CMP &&
20600 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20603 // Quit if not used as a boolean value.
20604 if (CC != X86::COND_E && CC != X86::COND_NE)
20607 // Check CMP operands. One of them should be 0 or 1 and the other should be
20608 // an SetCC or extended from it.
20609 SDValue Op1 = Cmp.getOperand(0);
20610 SDValue Op2 = Cmp.getOperand(1);
20613 const ConstantSDNode* C = nullptr;
20614 bool needOppositeCond = (CC == X86::COND_E);
20615 bool checkAgainstTrue = false; // Is it a comparison against 1?
20617 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20619 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20621 else // Quit if all operands are not constants.
20624 if (C->getZExtValue() == 1) {
20625 needOppositeCond = !needOppositeCond;
20626 checkAgainstTrue = true;
20627 } else if (C->getZExtValue() != 0)
20628 // Quit if the constant is neither 0 or 1.
20631 bool truncatedToBoolWithAnd = false;
20632 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20633 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20634 SetCC.getOpcode() == ISD::TRUNCATE ||
20635 SetCC.getOpcode() == ISD::AND) {
20636 if (SetCC.getOpcode() == ISD::AND) {
20638 ConstantSDNode *CS;
20639 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20640 CS->getZExtValue() == 1)
20642 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20643 CS->getZExtValue() == 1)
20647 SetCC = SetCC.getOperand(OpIdx);
20648 truncatedToBoolWithAnd = true;
20650 SetCC = SetCC.getOperand(0);
20653 switch (SetCC.getOpcode()) {
20654 case X86ISD::SETCC_CARRY:
20655 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
20656 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
20657 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
20658 // truncated to i1 using 'and'.
20659 if (checkAgainstTrue && !truncatedToBoolWithAnd)
20661 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
20662 "Invalid use of SETCC_CARRY!");
20664 case X86ISD::SETCC:
20665 // Set the condition code or opposite one if necessary.
20666 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
20667 if (needOppositeCond)
20668 CC = X86::GetOppositeBranchCondition(CC);
20669 return SetCC.getOperand(1);
20670 case X86ISD::CMOV: {
20671 // Check whether false/true value has canonical one, i.e. 0 or 1.
20672 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
20673 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
20674 // Quit if true value is not a constant.
20677 // Quit if false value is not a constant.
20679 SDValue Op = SetCC.getOperand(0);
20680 // Skip 'zext' or 'trunc' node.
20681 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
20682 Op.getOpcode() == ISD::TRUNCATE)
20683 Op = Op.getOperand(0);
20684 // A special case for rdrand/rdseed, where 0 is set if false cond is
20686 if ((Op.getOpcode() != X86ISD::RDRAND &&
20687 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
20690 // Quit if false value is not the constant 0 or 1.
20691 bool FValIsFalse = true;
20692 if (FVal && FVal->getZExtValue() != 0) {
20693 if (FVal->getZExtValue() != 1)
20695 // If FVal is 1, opposite cond is needed.
20696 needOppositeCond = !needOppositeCond;
20697 FValIsFalse = false;
20699 // Quit if TVal is not the constant opposite of FVal.
20700 if (FValIsFalse && TVal->getZExtValue() != 1)
20702 if (!FValIsFalse && TVal->getZExtValue() != 0)
20704 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
20705 if (needOppositeCond)
20706 CC = X86::GetOppositeBranchCondition(CC);
20707 return SetCC.getOperand(3);
20714 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
20715 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
20716 TargetLowering::DAGCombinerInfo &DCI,
20717 const X86Subtarget *Subtarget) {
20720 // If the flag operand isn't dead, don't touch this CMOV.
20721 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
20724 SDValue FalseOp = N->getOperand(0);
20725 SDValue TrueOp = N->getOperand(1);
20726 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
20727 SDValue Cond = N->getOperand(3);
20729 if (CC == X86::COND_E || CC == X86::COND_NE) {
20730 switch (Cond.getOpcode()) {
20734 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
20735 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
20736 return (CC == X86::COND_E) ? FalseOp : TrueOp;
20742 Flags = checkBoolTestSetCCCombine(Cond, CC);
20743 if (Flags.getNode() &&
20744 // Extra check as FCMOV only supports a subset of X86 cond.
20745 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
20746 SDValue Ops[] = { FalseOp, TrueOp,
20747 DAG.getConstant(CC, MVT::i8), Flags };
20748 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
20751 // If this is a select between two integer constants, try to do some
20752 // optimizations. Note that the operands are ordered the opposite of SELECT
20754 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
20755 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
20756 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
20757 // larger than FalseC (the false value).
20758 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
20759 CC = X86::GetOppositeBranchCondition(CC);
20760 std::swap(TrueC, FalseC);
20761 std::swap(TrueOp, FalseOp);
20764 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
20765 // This is efficient for any integer data type (including i8/i16) and
20767 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
20768 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20769 DAG.getConstant(CC, MVT::i8), Cond);
20771 // Zero extend the condition if needed.
20772 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
20774 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20775 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
20776 DAG.getConstant(ShAmt, MVT::i8));
20777 if (N->getNumValues() == 2) // Dead flag value?
20778 return DCI.CombineTo(N, Cond, SDValue());
20782 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
20783 // for any integer data type, including i8/i16.
20784 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20785 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20786 DAG.getConstant(CC, MVT::i8), Cond);
20788 // Zero extend the condition if needed.
20789 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20790 FalseC->getValueType(0), Cond);
20791 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20792 SDValue(FalseC, 0));
20794 if (N->getNumValues() == 2) // Dead flag value?
20795 return DCI.CombineTo(N, Cond, SDValue());
20799 // Optimize cases that will turn into an LEA instruction. This requires
20800 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20801 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20802 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20803 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20805 bool isFastMultiplier = false;
20807 switch ((unsigned char)Diff) {
20809 case 1: // result = add base, cond
20810 case 2: // result = lea base( , cond*2)
20811 case 3: // result = lea base(cond, cond*2)
20812 case 4: // result = lea base( , cond*4)
20813 case 5: // result = lea base(cond, cond*4)
20814 case 8: // result = lea base( , cond*8)
20815 case 9: // result = lea base(cond, cond*8)
20816 isFastMultiplier = true;
20821 if (isFastMultiplier) {
20822 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20823 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20824 DAG.getConstant(CC, MVT::i8), Cond);
20825 // Zero extend the condition if needed.
20826 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20828 // Scale the condition by the difference.
20830 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20831 DAG.getConstant(Diff, Cond.getValueType()));
20833 // Add the base if non-zero.
20834 if (FalseC->getAPIntValue() != 0)
20835 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20836 SDValue(FalseC, 0));
20837 if (N->getNumValues() == 2) // Dead flag value?
20838 return DCI.CombineTo(N, Cond, SDValue());
20845 // Handle these cases:
20846 // (select (x != c), e, c) -> select (x != c), e, x),
20847 // (select (x == c), c, e) -> select (x == c), x, e)
20848 // where the c is an integer constant, and the "select" is the combination
20849 // of CMOV and CMP.
20851 // The rationale for this change is that the conditional-move from a constant
20852 // needs two instructions, however, conditional-move from a register needs
20853 // only one instruction.
20855 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
20856 // some instruction-combining opportunities. This opt needs to be
20857 // postponed as late as possible.
20859 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
20860 // the DCI.xxxx conditions are provided to postpone the optimization as
20861 // late as possible.
20863 ConstantSDNode *CmpAgainst = nullptr;
20864 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
20865 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
20866 !isa<ConstantSDNode>(Cond.getOperand(0))) {
20868 if (CC == X86::COND_NE &&
20869 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
20870 CC = X86::GetOppositeBranchCondition(CC);
20871 std::swap(TrueOp, FalseOp);
20874 if (CC == X86::COND_E &&
20875 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
20876 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
20877 DAG.getConstant(CC, MVT::i8), Cond };
20878 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
20886 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
20887 const X86Subtarget *Subtarget) {
20888 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
20890 default: return SDValue();
20891 // SSE/AVX/AVX2 blend intrinsics.
20892 case Intrinsic::x86_avx2_pblendvb:
20893 case Intrinsic::x86_avx2_pblendw:
20894 case Intrinsic::x86_avx2_pblendd_128:
20895 case Intrinsic::x86_avx2_pblendd_256:
20896 // Don't try to simplify this intrinsic if we don't have AVX2.
20897 if (!Subtarget->hasAVX2())
20900 case Intrinsic::x86_avx_blend_pd_256:
20901 case Intrinsic::x86_avx_blend_ps_256:
20902 case Intrinsic::x86_avx_blendv_pd_256:
20903 case Intrinsic::x86_avx_blendv_ps_256:
20904 // Don't try to simplify this intrinsic if we don't have AVX.
20905 if (!Subtarget->hasAVX())
20908 case Intrinsic::x86_sse41_pblendw:
20909 case Intrinsic::x86_sse41_blendpd:
20910 case Intrinsic::x86_sse41_blendps:
20911 case Intrinsic::x86_sse41_blendvps:
20912 case Intrinsic::x86_sse41_blendvpd:
20913 case Intrinsic::x86_sse41_pblendvb: {
20914 SDValue Op0 = N->getOperand(1);
20915 SDValue Op1 = N->getOperand(2);
20916 SDValue Mask = N->getOperand(3);
20918 // Don't try to simplify this intrinsic if we don't have SSE4.1.
20919 if (!Subtarget->hasSSE41())
20922 // fold (blend A, A, Mask) -> A
20925 // fold (blend A, B, allZeros) -> A
20926 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
20928 // fold (blend A, B, allOnes) -> B
20929 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
20932 // Simplify the case where the mask is a constant i32 value.
20933 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
20934 if (C->isNullValue())
20936 if (C->isAllOnesValue())
20943 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
20944 case Intrinsic::x86_sse2_psrai_w:
20945 case Intrinsic::x86_sse2_psrai_d:
20946 case Intrinsic::x86_avx2_psrai_w:
20947 case Intrinsic::x86_avx2_psrai_d:
20948 case Intrinsic::x86_sse2_psra_w:
20949 case Intrinsic::x86_sse2_psra_d:
20950 case Intrinsic::x86_avx2_psra_w:
20951 case Intrinsic::x86_avx2_psra_d: {
20952 SDValue Op0 = N->getOperand(1);
20953 SDValue Op1 = N->getOperand(2);
20954 EVT VT = Op0.getValueType();
20955 assert(VT.isVector() && "Expected a vector type!");
20957 if (isa<BuildVectorSDNode>(Op1))
20958 Op1 = Op1.getOperand(0);
20960 if (!isa<ConstantSDNode>(Op1))
20963 EVT SVT = VT.getVectorElementType();
20964 unsigned SVTBits = SVT.getSizeInBits();
20966 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
20967 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
20968 uint64_t ShAmt = C.getZExtValue();
20970 // Don't try to convert this shift into a ISD::SRA if the shift
20971 // count is bigger than or equal to the element size.
20972 if (ShAmt >= SVTBits)
20975 // Trivial case: if the shift count is zero, then fold this
20976 // into the first operand.
20980 // Replace this packed shift intrinsic with a target independent
20982 SDValue Splat = DAG.getConstant(C, VT);
20983 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
20988 /// PerformMulCombine - Optimize a single multiply with constant into two
20989 /// in order to implement it with two cheaper instructions, e.g.
20990 /// LEA + SHL, LEA + LEA.
20991 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
20992 TargetLowering::DAGCombinerInfo &DCI) {
20993 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
20996 EVT VT = N->getValueType(0);
20997 if (VT != MVT::i64)
21000 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21003 uint64_t MulAmt = C->getZExtValue();
21004 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21007 uint64_t MulAmt1 = 0;
21008 uint64_t MulAmt2 = 0;
21009 if ((MulAmt % 9) == 0) {
21011 MulAmt2 = MulAmt / 9;
21012 } else if ((MulAmt % 5) == 0) {
21014 MulAmt2 = MulAmt / 5;
21015 } else if ((MulAmt % 3) == 0) {
21017 MulAmt2 = MulAmt / 3;
21020 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21023 if (isPowerOf2_64(MulAmt2) &&
21024 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21025 // If second multiplifer is pow2, issue it first. We want the multiply by
21026 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21028 std::swap(MulAmt1, MulAmt2);
21031 if (isPowerOf2_64(MulAmt1))
21032 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21033 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21035 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21036 DAG.getConstant(MulAmt1, VT));
21038 if (isPowerOf2_64(MulAmt2))
21039 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21040 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21042 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21043 DAG.getConstant(MulAmt2, VT));
21045 // Do not add new nodes to DAG combiner worklist.
21046 DCI.CombineTo(N, NewMul, false);
21051 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21052 SDValue N0 = N->getOperand(0);
21053 SDValue N1 = N->getOperand(1);
21054 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21055 EVT VT = N0.getValueType();
21057 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21058 // since the result of setcc_c is all zero's or all ones.
21059 if (VT.isInteger() && !VT.isVector() &&
21060 N1C && N0.getOpcode() == ISD::AND &&
21061 N0.getOperand(1).getOpcode() == ISD::Constant) {
21062 SDValue N00 = N0.getOperand(0);
21063 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21064 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21065 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21066 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21067 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21068 APInt ShAmt = N1C->getAPIntValue();
21069 Mask = Mask.shl(ShAmt);
21071 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21072 N00, DAG.getConstant(Mask, VT));
21076 // Hardware support for vector shifts is sparse which makes us scalarize the
21077 // vector operations in many cases. Also, on sandybridge ADD is faster than
21079 // (shl V, 1) -> add V,V
21080 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21081 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21082 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21083 // We shift all of the values by one. In many cases we do not have
21084 // hardware support for this operation. This is better expressed as an ADD
21086 if (N1SplatC->getZExtValue() == 1)
21087 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21093 /// \brief Returns a vector of 0s if the node in input is a vector logical
21094 /// shift by a constant amount which is known to be bigger than or equal
21095 /// to the vector element size in bits.
21096 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21097 const X86Subtarget *Subtarget) {
21098 EVT VT = N->getValueType(0);
21100 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21101 (!Subtarget->hasInt256() ||
21102 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21105 SDValue Amt = N->getOperand(1);
21107 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21108 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21109 APInt ShiftAmt = AmtSplat->getAPIntValue();
21110 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21112 // SSE2/AVX2 logical shifts always return a vector of 0s
21113 // if the shift amount is bigger than or equal to
21114 // the element size. The constant shift amount will be
21115 // encoded as a 8-bit immediate.
21116 if (ShiftAmt.trunc(8).uge(MaxAmount))
21117 return getZeroVector(VT, Subtarget, DAG, DL);
21123 /// PerformShiftCombine - Combine shifts.
21124 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21125 TargetLowering::DAGCombinerInfo &DCI,
21126 const X86Subtarget *Subtarget) {
21127 if (N->getOpcode() == ISD::SHL) {
21128 SDValue V = PerformSHLCombine(N, DAG);
21129 if (V.getNode()) return V;
21132 if (N->getOpcode() != ISD::SRA) {
21133 // Try to fold this logical shift into a zero vector.
21134 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21135 if (V.getNode()) return V;
21141 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21142 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21143 // and friends. Likewise for OR -> CMPNEQSS.
21144 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21145 TargetLowering::DAGCombinerInfo &DCI,
21146 const X86Subtarget *Subtarget) {
21149 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21150 // we're requiring SSE2 for both.
21151 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21152 SDValue N0 = N->getOperand(0);
21153 SDValue N1 = N->getOperand(1);
21154 SDValue CMP0 = N0->getOperand(1);
21155 SDValue CMP1 = N1->getOperand(1);
21158 // The SETCCs should both refer to the same CMP.
21159 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21162 SDValue CMP00 = CMP0->getOperand(0);
21163 SDValue CMP01 = CMP0->getOperand(1);
21164 EVT VT = CMP00.getValueType();
21166 if (VT == MVT::f32 || VT == MVT::f64) {
21167 bool ExpectingFlags = false;
21168 // Check for any users that want flags:
21169 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21170 !ExpectingFlags && UI != UE; ++UI)
21171 switch (UI->getOpcode()) {
21176 ExpectingFlags = true;
21178 case ISD::CopyToReg:
21179 case ISD::SIGN_EXTEND:
21180 case ISD::ZERO_EXTEND:
21181 case ISD::ANY_EXTEND:
21185 if (!ExpectingFlags) {
21186 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21187 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21189 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21190 X86::CondCode tmp = cc0;
21195 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21196 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21197 // FIXME: need symbolic constants for these magic numbers.
21198 // See X86ATTInstPrinter.cpp:printSSECC().
21199 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21200 if (Subtarget->hasAVX512()) {
21201 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21202 CMP01, DAG.getConstant(x86cc, MVT::i8));
21203 if (N->getValueType(0) != MVT::i1)
21204 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21208 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21209 CMP00.getValueType(), CMP00, CMP01,
21210 DAG.getConstant(x86cc, MVT::i8));
21212 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21213 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21215 if (is64BitFP && !Subtarget->is64Bit()) {
21216 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21217 // 64-bit integer, since that's not a legal type. Since
21218 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21219 // bits, but can do this little dance to extract the lowest 32 bits
21220 // and work with those going forward.
21221 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21223 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21225 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21226 Vector32, DAG.getIntPtrConstant(0));
21230 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21231 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21232 DAG.getConstant(1, IntVT));
21233 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21234 return OneBitOfTruth;
21242 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21243 /// so it can be folded inside ANDNP.
21244 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21245 EVT VT = N->getValueType(0);
21247 // Match direct AllOnes for 128 and 256-bit vectors
21248 if (ISD::isBuildVectorAllOnes(N))
21251 // Look through a bit convert.
21252 if (N->getOpcode() == ISD::BITCAST)
21253 N = N->getOperand(0).getNode();
21255 // Sometimes the operand may come from a insert_subvector building a 256-bit
21257 if (VT.is256BitVector() &&
21258 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21259 SDValue V1 = N->getOperand(0);
21260 SDValue V2 = N->getOperand(1);
21262 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21263 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21264 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21265 ISD::isBuildVectorAllOnes(V2.getNode()))
21272 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21273 // register. In most cases we actually compare or select YMM-sized registers
21274 // and mixing the two types creates horrible code. This method optimizes
21275 // some of the transition sequences.
21276 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21277 TargetLowering::DAGCombinerInfo &DCI,
21278 const X86Subtarget *Subtarget) {
21279 EVT VT = N->getValueType(0);
21280 if (!VT.is256BitVector())
21283 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21284 N->getOpcode() == ISD::ZERO_EXTEND ||
21285 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21287 SDValue Narrow = N->getOperand(0);
21288 EVT NarrowVT = Narrow->getValueType(0);
21289 if (!NarrowVT.is128BitVector())
21292 if (Narrow->getOpcode() != ISD::XOR &&
21293 Narrow->getOpcode() != ISD::AND &&
21294 Narrow->getOpcode() != ISD::OR)
21297 SDValue N0 = Narrow->getOperand(0);
21298 SDValue N1 = Narrow->getOperand(1);
21301 // The Left side has to be a trunc.
21302 if (N0.getOpcode() != ISD::TRUNCATE)
21305 // The type of the truncated inputs.
21306 EVT WideVT = N0->getOperand(0)->getValueType(0);
21310 // The right side has to be a 'trunc' or a constant vector.
21311 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21312 ConstantSDNode *RHSConstSplat = nullptr;
21313 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21314 RHSConstSplat = RHSBV->getConstantSplatNode();
21315 if (!RHSTrunc && !RHSConstSplat)
21318 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21320 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21323 // Set N0 and N1 to hold the inputs to the new wide operation.
21324 N0 = N0->getOperand(0);
21325 if (RHSConstSplat) {
21326 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21327 SDValue(RHSConstSplat, 0));
21328 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21329 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21330 } else if (RHSTrunc) {
21331 N1 = N1->getOperand(0);
21334 // Generate the wide operation.
21335 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21336 unsigned Opcode = N->getOpcode();
21338 case ISD::ANY_EXTEND:
21340 case ISD::ZERO_EXTEND: {
21341 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21342 APInt Mask = APInt::getAllOnesValue(InBits);
21343 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21344 return DAG.getNode(ISD::AND, DL, VT,
21345 Op, DAG.getConstant(Mask, VT));
21347 case ISD::SIGN_EXTEND:
21348 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21349 Op, DAG.getValueType(NarrowVT));
21351 llvm_unreachable("Unexpected opcode");
21355 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21356 TargetLowering::DAGCombinerInfo &DCI,
21357 const X86Subtarget *Subtarget) {
21358 EVT VT = N->getValueType(0);
21359 if (DCI.isBeforeLegalizeOps())
21362 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21366 // Create BEXTR instructions
21367 // BEXTR is ((X >> imm) & (2**size-1))
21368 if (VT == MVT::i32 || VT == MVT::i64) {
21369 SDValue N0 = N->getOperand(0);
21370 SDValue N1 = N->getOperand(1);
21373 // Check for BEXTR.
21374 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21375 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21376 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21377 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21378 if (MaskNode && ShiftNode) {
21379 uint64_t Mask = MaskNode->getZExtValue();
21380 uint64_t Shift = ShiftNode->getZExtValue();
21381 if (isMask_64(Mask)) {
21382 uint64_t MaskSize = CountPopulation_64(Mask);
21383 if (Shift + MaskSize <= VT.getSizeInBits())
21384 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21385 DAG.getConstant(Shift | (MaskSize << 8), VT));
21393 // Want to form ANDNP nodes:
21394 // 1) In the hopes of then easily combining them with OR and AND nodes
21395 // to form PBLEND/PSIGN.
21396 // 2) To match ANDN packed intrinsics
21397 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21400 SDValue N0 = N->getOperand(0);
21401 SDValue N1 = N->getOperand(1);
21404 // Check LHS for vnot
21405 if (N0.getOpcode() == ISD::XOR &&
21406 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21407 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21408 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21410 // Check RHS for vnot
21411 if (N1.getOpcode() == ISD::XOR &&
21412 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21413 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21414 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21419 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21420 TargetLowering::DAGCombinerInfo &DCI,
21421 const X86Subtarget *Subtarget) {
21422 if (DCI.isBeforeLegalizeOps())
21425 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21429 SDValue N0 = N->getOperand(0);
21430 SDValue N1 = N->getOperand(1);
21431 EVT VT = N->getValueType(0);
21433 // look for psign/blend
21434 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21435 if (!Subtarget->hasSSSE3() ||
21436 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21439 // Canonicalize pandn to RHS
21440 if (N0.getOpcode() == X86ISD::ANDNP)
21442 // or (and (m, y), (pandn m, x))
21443 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21444 SDValue Mask = N1.getOperand(0);
21445 SDValue X = N1.getOperand(1);
21447 if (N0.getOperand(0) == Mask)
21448 Y = N0.getOperand(1);
21449 if (N0.getOperand(1) == Mask)
21450 Y = N0.getOperand(0);
21452 // Check to see if the mask appeared in both the AND and ANDNP and
21456 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21457 // Look through mask bitcast.
21458 if (Mask.getOpcode() == ISD::BITCAST)
21459 Mask = Mask.getOperand(0);
21460 if (X.getOpcode() == ISD::BITCAST)
21461 X = X.getOperand(0);
21462 if (Y.getOpcode() == ISD::BITCAST)
21463 Y = Y.getOperand(0);
21465 EVT MaskVT = Mask.getValueType();
21467 // Validate that the Mask operand is a vector sra node.
21468 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21469 // there is no psrai.b
21470 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21471 unsigned SraAmt = ~0;
21472 if (Mask.getOpcode() == ISD::SRA) {
21473 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21474 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21475 SraAmt = AmtConst->getZExtValue();
21476 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21477 SDValue SraC = Mask.getOperand(1);
21478 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21480 if ((SraAmt + 1) != EltBits)
21485 // Now we know we at least have a plendvb with the mask val. See if
21486 // we can form a psignb/w/d.
21487 // psign = x.type == y.type == mask.type && y = sub(0, x);
21488 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21489 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21490 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21491 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21492 "Unsupported VT for PSIGN");
21493 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21494 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21496 // PBLENDVB only available on SSE 4.1
21497 if (!Subtarget->hasSSE41())
21500 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21502 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21503 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21504 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21505 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21506 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21510 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21513 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21514 MachineFunction &MF = DAG.getMachineFunction();
21515 bool OptForSize = MF.getFunction()->getAttributes().
21516 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21518 // SHLD/SHRD instructions have lower register pressure, but on some
21519 // platforms they have higher latency than the equivalent
21520 // series of shifts/or that would otherwise be generated.
21521 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21522 // have higher latencies and we are not optimizing for size.
21523 if (!OptForSize && Subtarget->isSHLDSlow())
21526 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21528 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21530 if (!N0.hasOneUse() || !N1.hasOneUse())
21533 SDValue ShAmt0 = N0.getOperand(1);
21534 if (ShAmt0.getValueType() != MVT::i8)
21536 SDValue ShAmt1 = N1.getOperand(1);
21537 if (ShAmt1.getValueType() != MVT::i8)
21539 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21540 ShAmt0 = ShAmt0.getOperand(0);
21541 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21542 ShAmt1 = ShAmt1.getOperand(0);
21545 unsigned Opc = X86ISD::SHLD;
21546 SDValue Op0 = N0.getOperand(0);
21547 SDValue Op1 = N1.getOperand(0);
21548 if (ShAmt0.getOpcode() == ISD::SUB) {
21549 Opc = X86ISD::SHRD;
21550 std::swap(Op0, Op1);
21551 std::swap(ShAmt0, ShAmt1);
21554 unsigned Bits = VT.getSizeInBits();
21555 if (ShAmt1.getOpcode() == ISD::SUB) {
21556 SDValue Sum = ShAmt1.getOperand(0);
21557 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21558 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21559 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21560 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21561 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21562 return DAG.getNode(Opc, DL, VT,
21564 DAG.getNode(ISD::TRUNCATE, DL,
21567 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21568 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21570 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21571 return DAG.getNode(Opc, DL, VT,
21572 N0.getOperand(0), N1.getOperand(0),
21573 DAG.getNode(ISD::TRUNCATE, DL,
21580 // Generate NEG and CMOV for integer abs.
21581 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21582 EVT VT = N->getValueType(0);
21584 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21585 // 8-bit integer abs to NEG and CMOV.
21586 if (VT.isInteger() && VT.getSizeInBits() == 8)
21589 SDValue N0 = N->getOperand(0);
21590 SDValue N1 = N->getOperand(1);
21593 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21594 // and change it to SUB and CMOV.
21595 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21596 N0.getOpcode() == ISD::ADD &&
21597 N0.getOperand(1) == N1 &&
21598 N1.getOpcode() == ISD::SRA &&
21599 N1.getOperand(0) == N0.getOperand(0))
21600 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21601 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21602 // Generate SUB & CMOV.
21603 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21604 DAG.getConstant(0, VT), N0.getOperand(0));
21606 SDValue Ops[] = { N0.getOperand(0), Neg,
21607 DAG.getConstant(X86::COND_GE, MVT::i8),
21608 SDValue(Neg.getNode(), 1) };
21609 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21614 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
21615 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
21616 TargetLowering::DAGCombinerInfo &DCI,
21617 const X86Subtarget *Subtarget) {
21618 if (DCI.isBeforeLegalizeOps())
21621 if (Subtarget->hasCMov()) {
21622 SDValue RV = performIntegerAbsCombine(N, DAG);
21630 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
21631 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
21632 TargetLowering::DAGCombinerInfo &DCI,
21633 const X86Subtarget *Subtarget) {
21634 LoadSDNode *Ld = cast<LoadSDNode>(N);
21635 EVT RegVT = Ld->getValueType(0);
21636 EVT MemVT = Ld->getMemoryVT();
21638 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21640 // On Sandybridge unaligned 256bit loads are inefficient.
21641 ISD::LoadExtType Ext = Ld->getExtensionType();
21642 unsigned Alignment = Ld->getAlignment();
21643 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
21644 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
21645 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
21646 unsigned NumElems = RegVT.getVectorNumElements();
21650 SDValue Ptr = Ld->getBasePtr();
21651 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
21653 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
21655 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21656 Ld->getPointerInfo(), Ld->isVolatile(),
21657 Ld->isNonTemporal(), Ld->isInvariant(),
21659 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21660 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21661 Ld->getPointerInfo(), Ld->isVolatile(),
21662 Ld->isNonTemporal(), Ld->isInvariant(),
21663 std::min(16U, Alignment));
21664 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21666 Load2.getValue(1));
21668 SDValue NewVec = DAG.getUNDEF(RegVT);
21669 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
21670 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
21671 return DCI.CombineTo(N, NewVec, TF, true);
21677 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
21678 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
21679 const X86Subtarget *Subtarget) {
21680 StoreSDNode *St = cast<StoreSDNode>(N);
21681 EVT VT = St->getValue().getValueType();
21682 EVT StVT = St->getMemoryVT();
21684 SDValue StoredVal = St->getOperand(1);
21685 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21687 // If we are saving a concatenation of two XMM registers, perform two stores.
21688 // On Sandy Bridge, 256-bit memory operations are executed by two
21689 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
21690 // memory operation.
21691 unsigned Alignment = St->getAlignment();
21692 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
21693 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
21694 StVT == VT && !IsAligned) {
21695 unsigned NumElems = VT.getVectorNumElements();
21699 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
21700 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
21702 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
21703 SDValue Ptr0 = St->getBasePtr();
21704 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
21706 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
21707 St->getPointerInfo(), St->isVolatile(),
21708 St->isNonTemporal(), Alignment);
21709 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
21710 St->getPointerInfo(), St->isVolatile(),
21711 St->isNonTemporal(),
21712 std::min(16U, Alignment));
21713 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
21716 // Optimize trunc store (of multiple scalars) to shuffle and store.
21717 // First, pack all of the elements in one place. Next, store to memory
21718 // in fewer chunks.
21719 if (St->isTruncatingStore() && VT.isVector()) {
21720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21721 unsigned NumElems = VT.getVectorNumElements();
21722 assert(StVT != VT && "Cannot truncate to the same type");
21723 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
21724 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
21726 // From, To sizes and ElemCount must be pow of two
21727 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
21728 // We are going to use the original vector elt for storing.
21729 // Accumulated smaller vector elements must be a multiple of the store size.
21730 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
21732 unsigned SizeRatio = FromSz / ToSz;
21734 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
21736 // Create a type on which we perform the shuffle
21737 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
21738 StVT.getScalarType(), NumElems*SizeRatio);
21740 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
21742 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
21743 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21744 for (unsigned i = 0; i != NumElems; ++i)
21745 ShuffleVec[i] = i * SizeRatio;
21747 // Can't shuffle using an illegal type.
21748 if (!TLI.isTypeLegal(WideVecVT))
21751 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
21752 DAG.getUNDEF(WideVecVT),
21754 // At this point all of the data is stored at the bottom of the
21755 // register. We now need to save it to mem.
21757 // Find the largest store unit
21758 MVT StoreType = MVT::i8;
21759 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
21760 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
21761 MVT Tp = (MVT::SimpleValueType)tp;
21762 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
21766 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
21767 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
21768 (64 <= NumElems * ToSz))
21769 StoreType = MVT::f64;
21771 // Bitcast the original vector into a vector of store-size units
21772 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21773 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21774 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21775 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21776 SmallVector<SDValue, 8> Chains;
21777 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21778 TLI.getPointerTy());
21779 SDValue Ptr = St->getBasePtr();
21781 // Perform one or more big stores into memory.
21782 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21783 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21784 StoreType, ShuffWide,
21785 DAG.getIntPtrConstant(i));
21786 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21787 St->getPointerInfo(), St->isVolatile(),
21788 St->isNonTemporal(), St->getAlignment());
21789 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21790 Chains.push_back(Ch);
21793 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21796 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21797 // the FP state in cases where an emms may be missing.
21798 // A preferable solution to the general problem is to figure out the right
21799 // places to insert EMMS. This qualifies as a quick hack.
21801 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21802 if (VT.getSizeInBits() != 64)
21805 const Function *F = DAG.getMachineFunction().getFunction();
21806 bool NoImplicitFloatOps = F->getAttributes().
21807 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21808 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21809 && Subtarget->hasSSE2();
21810 if ((VT.isVector() ||
21811 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21812 isa<LoadSDNode>(St->getValue()) &&
21813 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21814 St->getChain().hasOneUse() && !St->isVolatile()) {
21815 SDNode* LdVal = St->getValue().getNode();
21816 LoadSDNode *Ld = nullptr;
21817 int TokenFactorIndex = -1;
21818 SmallVector<SDValue, 8> Ops;
21819 SDNode* ChainVal = St->getChain().getNode();
21820 // Must be a store of a load. We currently handle two cases: the load
21821 // is a direct child, and it's under an intervening TokenFactor. It is
21822 // possible to dig deeper under nested TokenFactors.
21823 if (ChainVal == LdVal)
21824 Ld = cast<LoadSDNode>(St->getChain());
21825 else if (St->getValue().hasOneUse() &&
21826 ChainVal->getOpcode() == ISD::TokenFactor) {
21827 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21828 if (ChainVal->getOperand(i).getNode() == LdVal) {
21829 TokenFactorIndex = i;
21830 Ld = cast<LoadSDNode>(St->getValue());
21832 Ops.push_back(ChainVal->getOperand(i));
21836 if (!Ld || !ISD::isNormalLoad(Ld))
21839 // If this is not the MMX case, i.e. we are just turning i64 load/store
21840 // into f64 load/store, avoid the transformation if there are multiple
21841 // uses of the loaded value.
21842 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21847 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21848 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
21850 if (Subtarget->is64Bit() || F64IsLegal) {
21851 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
21852 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
21853 Ld->getPointerInfo(), Ld->isVolatile(),
21854 Ld->isNonTemporal(), Ld->isInvariant(),
21855 Ld->getAlignment());
21856 SDValue NewChain = NewLd.getValue(1);
21857 if (TokenFactorIndex != -1) {
21858 Ops.push_back(NewChain);
21859 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21861 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
21862 St->getPointerInfo(),
21863 St->isVolatile(), St->isNonTemporal(),
21864 St->getAlignment());
21867 // Otherwise, lower to two pairs of 32-bit loads / stores.
21868 SDValue LoAddr = Ld->getBasePtr();
21869 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
21870 DAG.getConstant(4, MVT::i32));
21872 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
21873 Ld->getPointerInfo(),
21874 Ld->isVolatile(), Ld->isNonTemporal(),
21875 Ld->isInvariant(), Ld->getAlignment());
21876 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
21877 Ld->getPointerInfo().getWithOffset(4),
21878 Ld->isVolatile(), Ld->isNonTemporal(),
21880 MinAlign(Ld->getAlignment(), 4));
21882 SDValue NewChain = LoLd.getValue(1);
21883 if (TokenFactorIndex != -1) {
21884 Ops.push_back(LoLd);
21885 Ops.push_back(HiLd);
21886 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21889 LoAddr = St->getBasePtr();
21890 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
21891 DAG.getConstant(4, MVT::i32));
21893 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
21894 St->getPointerInfo(),
21895 St->isVolatile(), St->isNonTemporal(),
21896 St->getAlignment());
21897 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
21898 St->getPointerInfo().getWithOffset(4),
21900 St->isNonTemporal(),
21901 MinAlign(St->getAlignment(), 4));
21902 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
21907 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
21908 /// and return the operands for the horizontal operation in LHS and RHS. A
21909 /// horizontal operation performs the binary operation on successive elements
21910 /// of its first operand, then on successive elements of its second operand,
21911 /// returning the resulting values in a vector. For example, if
21912 /// A = < float a0, float a1, float a2, float a3 >
21914 /// B = < float b0, float b1, float b2, float b3 >
21915 /// then the result of doing a horizontal operation on A and B is
21916 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
21917 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21918 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21919 /// set to A, RHS to B, and the routine returns 'true'.
21920 /// Note that the binary operation should have the property that if one of the
21921 /// operands is UNDEF then the result is UNDEF.
21922 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21923 // Look for the following pattern: if
21924 // A = < float a0, float a1, float a2, float a3 >
21925 // B = < float b0, float b1, float b2, float b3 >
21927 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21928 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
21929 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21930 // which is A horizontal-op B.
21932 // At least one of the operands should be a vector shuffle.
21933 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21934 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
21937 MVT VT = LHS.getSimpleValueType();
21939 assert((VT.is128BitVector() || VT.is256BitVector()) &&
21940 "Unsupported vector type for horizontal add/sub");
21942 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
21943 // operate independently on 128-bit lanes.
21944 unsigned NumElts = VT.getVectorNumElements();
21945 unsigned NumLanes = VT.getSizeInBits()/128;
21946 unsigned NumLaneElts = NumElts / NumLanes;
21947 assert((NumLaneElts % 2 == 0) &&
21948 "Vector type should have an even number of elements in each lane");
21949 unsigned HalfLaneElts = NumLaneElts/2;
21951 // View LHS in the form
21952 // LHS = VECTOR_SHUFFLE A, B, LMask
21953 // If LHS is not a shuffle then pretend it is the shuffle
21954 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21955 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
21958 SmallVector<int, 16> LMask(NumElts);
21959 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21960 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21961 A = LHS.getOperand(0);
21962 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21963 B = LHS.getOperand(1);
21964 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21965 std::copy(Mask.begin(), Mask.end(), LMask.begin());
21967 if (LHS.getOpcode() != ISD::UNDEF)
21969 for (unsigned i = 0; i != NumElts; ++i)
21973 // Likewise, view RHS in the form
21974 // RHS = VECTOR_SHUFFLE C, D, RMask
21976 SmallVector<int, 16> RMask(NumElts);
21977 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21978 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
21979 C = RHS.getOperand(0);
21980 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
21981 D = RHS.getOperand(1);
21982 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
21983 std::copy(Mask.begin(), Mask.end(), RMask.begin());
21985 if (RHS.getOpcode() != ISD::UNDEF)
21987 for (unsigned i = 0; i != NumElts; ++i)
21991 // Check that the shuffles are both shuffling the same vectors.
21992 if (!(A == C && B == D) && !(A == D && B == C))
21995 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
21996 if (!A.getNode() && !B.getNode())
21999 // If A and B occur in reverse order in RHS, then "swap" them (which means
22000 // rewriting the mask).
22002 CommuteVectorShuffleMask(RMask, NumElts);
22004 // At this point LHS and RHS are equivalent to
22005 // LHS = VECTOR_SHUFFLE A, B, LMask
22006 // RHS = VECTOR_SHUFFLE A, B, RMask
22007 // Check that the masks correspond to performing a horizontal operation.
22008 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22009 for (unsigned i = 0; i != NumLaneElts; ++i) {
22010 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22012 // Ignore any UNDEF components.
22013 if (LIdx < 0 || RIdx < 0 ||
22014 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22015 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22018 // Check that successive elements are being operated on. If not, this is
22019 // not a horizontal operation.
22020 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22021 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22022 if (!(LIdx == Index && RIdx == Index + 1) &&
22023 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22028 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22029 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22033 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22034 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22035 const X86Subtarget *Subtarget) {
22036 EVT VT = N->getValueType(0);
22037 SDValue LHS = N->getOperand(0);
22038 SDValue RHS = N->getOperand(1);
22040 // Try to synthesize horizontal adds from adds of shuffles.
22041 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22042 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22043 isHorizontalBinOp(LHS, RHS, true))
22044 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22048 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22049 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22050 const X86Subtarget *Subtarget) {
22051 EVT VT = N->getValueType(0);
22052 SDValue LHS = N->getOperand(0);
22053 SDValue RHS = N->getOperand(1);
22055 // Try to synthesize horizontal subs from subs of shuffles.
22056 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22057 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22058 isHorizontalBinOp(LHS, RHS, false))
22059 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22063 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22064 /// X86ISD::FXOR nodes.
22065 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22066 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22067 // F[X]OR(0.0, x) -> x
22068 // F[X]OR(x, 0.0) -> x
22069 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22070 if (C->getValueAPF().isPosZero())
22071 return N->getOperand(1);
22072 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22073 if (C->getValueAPF().isPosZero())
22074 return N->getOperand(0);
22078 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22079 /// X86ISD::FMAX nodes.
22080 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22081 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22083 // Only perform optimizations if UnsafeMath is used.
22084 if (!DAG.getTarget().Options.UnsafeFPMath)
22087 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22088 // into FMINC and FMAXC, which are Commutative operations.
22089 unsigned NewOp = 0;
22090 switch (N->getOpcode()) {
22091 default: llvm_unreachable("unknown opcode");
22092 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22093 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22096 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22097 N->getOperand(0), N->getOperand(1));
22100 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22101 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22102 // FAND(0.0, x) -> 0.0
22103 // FAND(x, 0.0) -> 0.0
22104 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22105 if (C->getValueAPF().isPosZero())
22106 return N->getOperand(0);
22107 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22108 if (C->getValueAPF().isPosZero())
22109 return N->getOperand(1);
22113 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22114 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22115 // FANDN(x, 0.0) -> 0.0
22116 // FANDN(0.0, x) -> x
22117 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22118 if (C->getValueAPF().isPosZero())
22119 return N->getOperand(1);
22120 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22121 if (C->getValueAPF().isPosZero())
22122 return N->getOperand(1);
22126 static SDValue PerformBTCombine(SDNode *N,
22128 TargetLowering::DAGCombinerInfo &DCI) {
22129 // BT ignores high bits in the bit index operand.
22130 SDValue Op1 = N->getOperand(1);
22131 if (Op1.hasOneUse()) {
22132 unsigned BitWidth = Op1.getValueSizeInBits();
22133 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22134 APInt KnownZero, KnownOne;
22135 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22136 !DCI.isBeforeLegalizeOps());
22137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22138 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22139 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22140 DCI.CommitTargetLoweringOpt(TLO);
22145 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22146 SDValue Op = N->getOperand(0);
22147 if (Op.getOpcode() == ISD::BITCAST)
22148 Op = Op.getOperand(0);
22149 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22150 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22151 VT.getVectorElementType().getSizeInBits() ==
22152 OpVT.getVectorElementType().getSizeInBits()) {
22153 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22158 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22159 const X86Subtarget *Subtarget) {
22160 EVT VT = N->getValueType(0);
22161 if (!VT.isVector())
22164 SDValue N0 = N->getOperand(0);
22165 SDValue N1 = N->getOperand(1);
22166 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22169 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22170 // both SSE and AVX2 since there is no sign-extended shift right
22171 // operation on a vector with 64-bit elements.
22172 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22173 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22174 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22175 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22176 SDValue N00 = N0.getOperand(0);
22178 // EXTLOAD has a better solution on AVX2,
22179 // it may be replaced with X86ISD::VSEXT node.
22180 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22181 if (!ISD::isNormalLoad(N00.getNode()))
22184 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22185 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22187 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22193 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22194 TargetLowering::DAGCombinerInfo &DCI,
22195 const X86Subtarget *Subtarget) {
22196 if (!DCI.isBeforeLegalizeOps())
22199 if (!Subtarget->hasFp256())
22202 EVT VT = N->getValueType(0);
22203 if (VT.isVector() && VT.getSizeInBits() == 256) {
22204 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22212 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22213 const X86Subtarget* Subtarget) {
22215 EVT VT = N->getValueType(0);
22217 // Let legalize expand this if it isn't a legal type yet.
22218 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22221 EVT ScalarVT = VT.getScalarType();
22222 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22223 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22226 SDValue A = N->getOperand(0);
22227 SDValue B = N->getOperand(1);
22228 SDValue C = N->getOperand(2);
22230 bool NegA = (A.getOpcode() == ISD::FNEG);
22231 bool NegB = (B.getOpcode() == ISD::FNEG);
22232 bool NegC = (C.getOpcode() == ISD::FNEG);
22234 // Negative multiplication when NegA xor NegB
22235 bool NegMul = (NegA != NegB);
22237 A = A.getOperand(0);
22239 B = B.getOperand(0);
22241 C = C.getOperand(0);
22245 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22247 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22249 return DAG.getNode(Opcode, dl, VT, A, B, C);
22252 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22253 TargetLowering::DAGCombinerInfo &DCI,
22254 const X86Subtarget *Subtarget) {
22255 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22256 // (and (i32 x86isd::setcc_carry), 1)
22257 // This eliminates the zext. This transformation is necessary because
22258 // ISD::SETCC is always legalized to i8.
22260 SDValue N0 = N->getOperand(0);
22261 EVT VT = N->getValueType(0);
22263 if (N0.getOpcode() == ISD::AND &&
22265 N0.getOperand(0).hasOneUse()) {
22266 SDValue N00 = N0.getOperand(0);
22267 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22268 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22269 if (!C || C->getZExtValue() != 1)
22271 return DAG.getNode(ISD::AND, dl, VT,
22272 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22273 N00.getOperand(0), N00.getOperand(1)),
22274 DAG.getConstant(1, VT));
22278 if (N0.getOpcode() == ISD::TRUNCATE &&
22280 N0.getOperand(0).hasOneUse()) {
22281 SDValue N00 = N0.getOperand(0);
22282 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22283 return DAG.getNode(ISD::AND, dl, VT,
22284 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22285 N00.getOperand(0), N00.getOperand(1)),
22286 DAG.getConstant(1, VT));
22289 if (VT.is256BitVector()) {
22290 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22298 // Optimize x == -y --> x+y == 0
22299 // x != -y --> x+y != 0
22300 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22301 const X86Subtarget* Subtarget) {
22302 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22303 SDValue LHS = N->getOperand(0);
22304 SDValue RHS = N->getOperand(1);
22305 EVT VT = N->getValueType(0);
22308 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22309 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22310 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22311 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22312 LHS.getValueType(), RHS, LHS.getOperand(1));
22313 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22314 addV, DAG.getConstant(0, addV.getValueType()), CC);
22316 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22318 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22319 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22320 RHS.getValueType(), LHS, RHS.getOperand(1));
22321 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22322 addV, DAG.getConstant(0, addV.getValueType()), CC);
22325 if (VT.getScalarType() == MVT::i1) {
22326 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22327 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22328 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22329 if (!IsSEXT0 && !IsVZero0)
22331 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22332 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22333 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22335 if (!IsSEXT1 && !IsVZero1)
22338 if (IsSEXT0 && IsVZero1) {
22339 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22340 if (CC == ISD::SETEQ)
22341 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22342 return LHS.getOperand(0);
22344 if (IsSEXT1 && IsVZero0) {
22345 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22346 if (CC == ISD::SETEQ)
22347 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22348 return RHS.getOperand(0);
22355 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22356 const X86Subtarget *Subtarget) {
22358 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22359 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22360 "X86insertps is only defined for v4x32");
22362 SDValue Ld = N->getOperand(1);
22363 if (MayFoldLoad(Ld)) {
22364 // Extract the countS bits from the immediate so we can get the proper
22365 // address when narrowing the vector load to a specific element.
22366 // When the second source op is a memory address, interps doesn't use
22367 // countS and just gets an f32 from that address.
22368 unsigned DestIndex =
22369 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22370 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22374 // Create this as a scalar to vector to match the instruction pattern.
22375 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22376 // countS bits are ignored when loading from memory on insertps, which
22377 // means we don't need to explicitly set them to 0.
22378 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22379 LoadScalarToVector, N->getOperand(2));
22382 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22383 // as "sbb reg,reg", since it can be extended without zext and produces
22384 // an all-ones bit which is more useful than 0/1 in some cases.
22385 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22388 return DAG.getNode(ISD::AND, DL, VT,
22389 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22390 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22391 DAG.getConstant(1, VT));
22392 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22393 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22394 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22395 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22398 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22399 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22400 TargetLowering::DAGCombinerInfo &DCI,
22401 const X86Subtarget *Subtarget) {
22403 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22404 SDValue EFLAGS = N->getOperand(1);
22406 if (CC == X86::COND_A) {
22407 // Try to convert COND_A into COND_B in an attempt to facilitate
22408 // materializing "setb reg".
22410 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22411 // cannot take an immediate as its first operand.
22413 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22414 EFLAGS.getValueType().isInteger() &&
22415 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22416 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22417 EFLAGS.getNode()->getVTList(),
22418 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22419 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22420 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22424 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22425 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22427 if (CC == X86::COND_B)
22428 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22432 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22433 if (Flags.getNode()) {
22434 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22435 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22441 // Optimize branch condition evaluation.
22443 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22444 TargetLowering::DAGCombinerInfo &DCI,
22445 const X86Subtarget *Subtarget) {
22447 SDValue Chain = N->getOperand(0);
22448 SDValue Dest = N->getOperand(1);
22449 SDValue EFLAGS = N->getOperand(3);
22450 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22454 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22455 if (Flags.getNode()) {
22456 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22457 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22464 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22465 SelectionDAG &DAG) {
22466 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22467 // optimize away operation when it's from a constant.
22469 // The general transformation is:
22470 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22471 // AND(VECTOR_CMP(x,y), constant2)
22472 // constant2 = UNARYOP(constant)
22474 // Early exit if this isn't a vector operation, the operand of the
22475 // unary operation isn't a bitwise AND, or if the sizes of the operations
22476 // aren't the same.
22477 EVT VT = N->getValueType(0);
22478 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22479 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22480 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22483 // Now check that the other operand of the AND is a constant. We could
22484 // make the transformation for non-constant splats as well, but it's unclear
22485 // that would be a benefit as it would not eliminate any operations, just
22486 // perform one more step in scalar code before moving to the vector unit.
22487 if (BuildVectorSDNode *BV =
22488 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22489 // Bail out if the vector isn't a constant.
22490 if (!BV->isConstant())
22493 // Everything checks out. Build up the new and improved node.
22495 EVT IntVT = BV->getValueType(0);
22496 // Create a new constant of the appropriate type for the transformed
22498 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22499 // The AND node needs bitcasts to/from an integer vector type around it.
22500 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22501 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22502 N->getOperand(0)->getOperand(0), MaskConst);
22503 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22510 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22511 const X86TargetLowering *XTLI) {
22512 // First try to optimize away the conversion entirely when it's
22513 // conditionally from a constant. Vectors only.
22514 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22515 if (Res != SDValue())
22518 // Now move on to more general possibilities.
22519 SDValue Op0 = N->getOperand(0);
22520 EVT InVT = Op0->getValueType(0);
22522 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22523 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22525 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22526 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22527 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22530 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22531 // a 32-bit target where SSE doesn't support i64->FP operations.
22532 if (Op0.getOpcode() == ISD::LOAD) {
22533 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22534 EVT VT = Ld->getValueType(0);
22535 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22536 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22537 !XTLI->getSubtarget()->is64Bit() &&
22539 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22540 Ld->getChain(), Op0, DAG);
22541 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22548 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22549 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22550 X86TargetLowering::DAGCombinerInfo &DCI) {
22551 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22552 // the result is either zero or one (depending on the input carry bit).
22553 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22554 if (X86::isZeroNode(N->getOperand(0)) &&
22555 X86::isZeroNode(N->getOperand(1)) &&
22556 // We don't have a good way to replace an EFLAGS use, so only do this when
22558 SDValue(N, 1).use_empty()) {
22560 EVT VT = N->getValueType(0);
22561 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22562 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22563 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22564 DAG.getConstant(X86::COND_B,MVT::i8),
22566 DAG.getConstant(1, VT));
22567 return DCI.CombineTo(N, Res1, CarryOut);
22573 // fold (add Y, (sete X, 0)) -> adc 0, Y
22574 // (add Y, (setne X, 0)) -> sbb -1, Y
22575 // (sub (sete X, 0), Y) -> sbb 0, Y
22576 // (sub (setne X, 0), Y) -> adc -1, Y
22577 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
22580 // Look through ZExts.
22581 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
22582 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
22585 SDValue SetCC = Ext.getOperand(0);
22586 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
22589 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
22590 if (CC != X86::COND_E && CC != X86::COND_NE)
22593 SDValue Cmp = SetCC.getOperand(1);
22594 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
22595 !X86::isZeroNode(Cmp.getOperand(1)) ||
22596 !Cmp.getOperand(0).getValueType().isInteger())
22599 SDValue CmpOp0 = Cmp.getOperand(0);
22600 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
22601 DAG.getConstant(1, CmpOp0.getValueType()));
22603 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
22604 if (CC == X86::COND_NE)
22605 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
22606 DL, OtherVal.getValueType(), OtherVal,
22607 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
22608 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
22609 DL, OtherVal.getValueType(), OtherVal,
22610 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
22613 /// PerformADDCombine - Do target-specific dag combines on integer adds.
22614 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
22615 const X86Subtarget *Subtarget) {
22616 EVT VT = N->getValueType(0);
22617 SDValue Op0 = N->getOperand(0);
22618 SDValue Op1 = N->getOperand(1);
22620 // Try to synthesize horizontal adds from adds of shuffles.
22621 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22622 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22623 isHorizontalBinOp(Op0, Op1, true))
22624 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
22626 return OptimizeConditionalInDecrement(N, DAG);
22629 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
22630 const X86Subtarget *Subtarget) {
22631 SDValue Op0 = N->getOperand(0);
22632 SDValue Op1 = N->getOperand(1);
22634 // X86 can't encode an immediate LHS of a sub. See if we can push the
22635 // negation into a preceding instruction.
22636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
22637 // If the RHS of the sub is a XOR with one use and a constant, invert the
22638 // immediate. Then add one to the LHS of the sub so we can turn
22639 // X-Y -> X+~Y+1, saving one register.
22640 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
22641 isa<ConstantSDNode>(Op1.getOperand(1))) {
22642 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
22643 EVT VT = Op0.getValueType();
22644 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
22646 DAG.getConstant(~XorC, VT));
22647 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
22648 DAG.getConstant(C->getAPIntValue()+1, VT));
22652 // Try to synthesize horizontal adds from adds of shuffles.
22653 EVT VT = N->getValueType(0);
22654 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22655 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22656 isHorizontalBinOp(Op0, Op1, true))
22657 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
22659 return OptimizeConditionalInDecrement(N, DAG);
22662 /// performVZEXTCombine - Performs build vector combines
22663 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
22664 TargetLowering::DAGCombinerInfo &DCI,
22665 const X86Subtarget *Subtarget) {
22666 // (vzext (bitcast (vzext (x)) -> (vzext x)
22667 SDValue In = N->getOperand(0);
22668 while (In.getOpcode() == ISD::BITCAST)
22669 In = In.getOperand(0);
22671 if (In.getOpcode() != X86ISD::VZEXT)
22674 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
22678 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
22679 DAGCombinerInfo &DCI) const {
22680 SelectionDAG &DAG = DCI.DAG;
22681 switch (N->getOpcode()) {
22683 case ISD::EXTRACT_VECTOR_ELT:
22684 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22686 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22687 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22688 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
22689 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
22690 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
22691 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
22694 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
22695 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
22696 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
22697 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
22698 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
22699 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
22700 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
22701 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
22702 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
22704 case X86ISD::FOR: return PerformFORCombine(N, DAG);
22706 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
22707 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
22708 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
22709 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
22710 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
22711 case ISD::ANY_EXTEND:
22712 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
22713 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22714 case ISD::SIGN_EXTEND_INREG:
22715 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
22716 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
22717 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22718 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
22719 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
22720 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
22721 case X86ISD::SHUFP: // Handle all target specific shuffles
22722 case X86ISD::PALIGNR:
22723 case X86ISD::UNPCKH:
22724 case X86ISD::UNPCKL:
22725 case X86ISD::MOVHLPS:
22726 case X86ISD::MOVLHPS:
22727 case X86ISD::PSHUFB:
22728 case X86ISD::PSHUFD:
22729 case X86ISD::PSHUFHW:
22730 case X86ISD::PSHUFLW:
22731 case X86ISD::MOVSS:
22732 case X86ISD::MOVSD:
22733 case X86ISD::VPERMILP:
22734 case X86ISD::VPERM2X128:
22735 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
22736 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
22737 case ISD::INTRINSIC_WO_CHAIN:
22738 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
22739 case X86ISD::INSERTPS:
22740 return PerformINSERTPSCombine(N, DAG, Subtarget);
22741 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
22747 /// isTypeDesirableForOp - Return true if the target has native support for
22748 /// the specified value type and it is 'desirable' to use the type for the
22749 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
22750 /// instruction encodings are longer and some i16 instructions are slow.
22751 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
22752 if (!isTypeLegal(VT))
22754 if (VT != MVT::i16)
22761 case ISD::SIGN_EXTEND:
22762 case ISD::ZERO_EXTEND:
22763 case ISD::ANY_EXTEND:
22776 /// IsDesirableToPromoteOp - This method query the target whether it is
22777 /// beneficial for dag combiner to promote the specified node. If true, it
22778 /// should return the desired promotion type by reference.
22779 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
22780 EVT VT = Op.getValueType();
22781 if (VT != MVT::i16)
22784 bool Promote = false;
22785 bool Commute = false;
22786 switch (Op.getOpcode()) {
22789 LoadSDNode *LD = cast<LoadSDNode>(Op);
22790 // If the non-extending load has a single use and it's not live out, then it
22791 // might be folded.
22792 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
22793 Op.hasOneUse()*/) {
22794 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
22795 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
22796 // The only case where we'd want to promote LOAD (rather then it being
22797 // promoted as an operand is when it's only use is liveout.
22798 if (UI->getOpcode() != ISD::CopyToReg)
22805 case ISD::SIGN_EXTEND:
22806 case ISD::ZERO_EXTEND:
22807 case ISD::ANY_EXTEND:
22812 SDValue N0 = Op.getOperand(0);
22813 // Look out for (store (shl (load), x)).
22814 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22827 SDValue N0 = Op.getOperand(0);
22828 SDValue N1 = Op.getOperand(1);
22829 if (!Commute && MayFoldLoad(N1))
22831 // Avoid disabling potential load folding opportunities.
22832 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22834 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22844 //===----------------------------------------------------------------------===//
22845 // X86 Inline Assembly Support
22846 //===----------------------------------------------------------------------===//
22849 // Helper to match a string separated by whitespace.
22850 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
22851 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
22853 for (unsigned i = 0, e = args.size(); i != e; ++i) {
22854 StringRef piece(*args[i]);
22855 if (!s.startswith(piece)) // Check if the piece matches.
22858 s = s.substr(piece.size());
22859 StringRef::size_type pos = s.find_first_not_of(" \t");
22860 if (pos == 0) // We matched a prefix.
22868 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
22871 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
22873 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
22874 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
22875 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
22876 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
22878 if (AsmPieces.size() == 3)
22880 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
22887 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
22888 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22890 std::string AsmStr = IA->getAsmString();
22892 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22893 if (!Ty || Ty->getBitWidth() % 16 != 0)
22896 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22897 SmallVector<StringRef, 4> AsmPieces;
22898 SplitString(AsmStr, AsmPieces, ";\n");
22900 switch (AsmPieces.size()) {
22901 default: return false;
22903 // FIXME: this should verify that we are targeting a 486 or better. If not,
22904 // we will turn this bswap into something that will be lowered to logical
22905 // ops instead of emitting the bswap asm. For now, we don't support 486 or
22906 // lower so don't worry about this.
22908 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22909 matchAsm(AsmPieces[0], "bswapl", "$0") ||
22910 matchAsm(AsmPieces[0], "bswapq", "$0") ||
22911 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22912 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22913 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22914 // No need to check constraints, nothing other than the equivalent of
22915 // "=r,0" would be valid here.
22916 return IntrinsicLowering::LowerToByteSwap(CI);
22919 // rorw $$8, ${0:w} --> llvm.bswap.i16
22920 if (CI->getType()->isIntegerTy(16) &&
22921 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22922 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22923 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22925 const std::string &ConstraintsStr = IA->getConstraintString();
22926 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22927 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22928 if (clobbersFlagRegisters(AsmPieces))
22929 return IntrinsicLowering::LowerToByteSwap(CI);
22933 if (CI->getType()->isIntegerTy(32) &&
22934 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22935 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22936 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22937 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22939 const std::string &ConstraintsStr = IA->getConstraintString();
22940 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22941 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22942 if (clobbersFlagRegisters(AsmPieces))
22943 return IntrinsicLowering::LowerToByteSwap(CI);
22946 if (CI->getType()->isIntegerTy(64)) {
22947 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22948 if (Constraints.size() >= 2 &&
22949 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22950 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22951 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22952 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22953 matchAsm(AsmPieces[1], "bswap", "%edx") &&
22954 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22955 return IntrinsicLowering::LowerToByteSwap(CI);
22963 /// getConstraintType - Given a constraint letter, return the type of
22964 /// constraint it is for this target.
22965 X86TargetLowering::ConstraintType
22966 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
22967 if (Constraint.size() == 1) {
22968 switch (Constraint[0]) {
22979 return C_RegisterClass;
23003 return TargetLowering::getConstraintType(Constraint);
23006 /// Examine constraint type and operand type and determine a weight value.
23007 /// This object must already have been set up with the operand type
23008 /// and the current alternative constraint selected.
23009 TargetLowering::ConstraintWeight
23010 X86TargetLowering::getSingleConstraintMatchWeight(
23011 AsmOperandInfo &info, const char *constraint) const {
23012 ConstraintWeight weight = CW_Invalid;
23013 Value *CallOperandVal = info.CallOperandVal;
23014 // If we don't have a value, we can't do a match,
23015 // but allow it at the lowest weight.
23016 if (!CallOperandVal)
23018 Type *type = CallOperandVal->getType();
23019 // Look at the constraint type.
23020 switch (*constraint) {
23022 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23033 if (CallOperandVal->getType()->isIntegerTy())
23034 weight = CW_SpecificReg;
23039 if (type->isFloatingPointTy())
23040 weight = CW_SpecificReg;
23043 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23044 weight = CW_SpecificReg;
23048 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23049 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23050 weight = CW_Register;
23053 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23054 if (C->getZExtValue() <= 31)
23055 weight = CW_Constant;
23059 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23060 if (C->getZExtValue() <= 63)
23061 weight = CW_Constant;
23065 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23066 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23067 weight = CW_Constant;
23071 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23072 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23073 weight = CW_Constant;
23077 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23078 if (C->getZExtValue() <= 3)
23079 weight = CW_Constant;
23083 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23084 if (C->getZExtValue() <= 0xff)
23085 weight = CW_Constant;
23090 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23091 weight = CW_Constant;
23095 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23096 if ((C->getSExtValue() >= -0x80000000LL) &&
23097 (C->getSExtValue() <= 0x7fffffffLL))
23098 weight = CW_Constant;
23102 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23103 if (C->getZExtValue() <= 0xffffffff)
23104 weight = CW_Constant;
23111 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23112 /// with another that has more specific requirements based on the type of the
23113 /// corresponding operand.
23114 const char *X86TargetLowering::
23115 LowerXConstraint(EVT ConstraintVT) const {
23116 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23117 // 'f' like normal targets.
23118 if (ConstraintVT.isFloatingPoint()) {
23119 if (Subtarget->hasSSE2())
23121 if (Subtarget->hasSSE1())
23125 return TargetLowering::LowerXConstraint(ConstraintVT);
23128 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23129 /// vector. If it is invalid, don't add anything to Ops.
23130 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23131 std::string &Constraint,
23132 std::vector<SDValue>&Ops,
23133 SelectionDAG &DAG) const {
23136 // Only support length 1 constraints for now.
23137 if (Constraint.length() > 1) return;
23139 char ConstraintLetter = Constraint[0];
23140 switch (ConstraintLetter) {
23143 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23144 if (C->getZExtValue() <= 31) {
23145 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23152 if (C->getZExtValue() <= 63) {
23153 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23160 if (isInt<8>(C->getSExtValue())) {
23161 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23167 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23168 if (C->getZExtValue() <= 255) {
23169 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23175 // 32-bit signed value
23176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23177 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23178 C->getSExtValue())) {
23179 // Widen to 64 bits here to get it sign extended.
23180 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23183 // FIXME gcc accepts some relocatable values here too, but only in certain
23184 // memory models; it's complicated.
23189 // 32-bit unsigned value
23190 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23191 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23192 C->getZExtValue())) {
23193 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23197 // FIXME gcc accepts some relocatable values here too, but only in certain
23198 // memory models; it's complicated.
23202 // Literal immediates are always ok.
23203 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23204 // Widen to 64 bits here to get it sign extended.
23205 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23209 // In any sort of PIC mode addresses need to be computed at runtime by
23210 // adding in a register or some sort of table lookup. These can't
23211 // be used as immediates.
23212 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23215 // If we are in non-pic codegen mode, we allow the address of a global (with
23216 // an optional displacement) to be used with 'i'.
23217 GlobalAddressSDNode *GA = nullptr;
23218 int64_t Offset = 0;
23220 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23222 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23223 Offset += GA->getOffset();
23225 } else if (Op.getOpcode() == ISD::ADD) {
23226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23227 Offset += C->getZExtValue();
23228 Op = Op.getOperand(0);
23231 } else if (Op.getOpcode() == ISD::SUB) {
23232 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23233 Offset += -C->getZExtValue();
23234 Op = Op.getOperand(0);
23239 // Otherwise, this isn't something we can handle, reject it.
23243 const GlobalValue *GV = GA->getGlobal();
23244 // If we require an extra load to get this address, as in PIC mode, we
23245 // can't accept it.
23246 if (isGlobalStubReference(
23247 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23250 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23251 GA->getValueType(0), Offset);
23256 if (Result.getNode()) {
23257 Ops.push_back(Result);
23260 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23263 std::pair<unsigned, const TargetRegisterClass*>
23264 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23266 // First, see if this is a constraint that directly corresponds to an LLVM
23268 if (Constraint.size() == 1) {
23269 // GCC Constraint Letters
23270 switch (Constraint[0]) {
23272 // TODO: Slight differences here in allocation order and leaving
23273 // RIP in the class. Do they matter any more here than they do
23274 // in the normal allocation?
23275 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23276 if (Subtarget->is64Bit()) {
23277 if (VT == MVT::i32 || VT == MVT::f32)
23278 return std::make_pair(0U, &X86::GR32RegClass);
23279 if (VT == MVT::i16)
23280 return std::make_pair(0U, &X86::GR16RegClass);
23281 if (VT == MVT::i8 || VT == MVT::i1)
23282 return std::make_pair(0U, &X86::GR8RegClass);
23283 if (VT == MVT::i64 || VT == MVT::f64)
23284 return std::make_pair(0U, &X86::GR64RegClass);
23287 // 32-bit fallthrough
23288 case 'Q': // Q_REGS
23289 if (VT == MVT::i32 || VT == MVT::f32)
23290 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23291 if (VT == MVT::i16)
23292 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23293 if (VT == MVT::i8 || VT == MVT::i1)
23294 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23295 if (VT == MVT::i64)
23296 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23298 case 'r': // GENERAL_REGS
23299 case 'l': // INDEX_REGS
23300 if (VT == MVT::i8 || VT == MVT::i1)
23301 return std::make_pair(0U, &X86::GR8RegClass);
23302 if (VT == MVT::i16)
23303 return std::make_pair(0U, &X86::GR16RegClass);
23304 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23305 return std::make_pair(0U, &X86::GR32RegClass);
23306 return std::make_pair(0U, &X86::GR64RegClass);
23307 case 'R': // LEGACY_REGS
23308 if (VT == MVT::i8 || VT == MVT::i1)
23309 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23310 if (VT == MVT::i16)
23311 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23312 if (VT == MVT::i32 || !Subtarget->is64Bit())
23313 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23314 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23315 case 'f': // FP Stack registers.
23316 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23317 // value to the correct fpstack register class.
23318 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23319 return std::make_pair(0U, &X86::RFP32RegClass);
23320 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23321 return std::make_pair(0U, &X86::RFP64RegClass);
23322 return std::make_pair(0U, &X86::RFP80RegClass);
23323 case 'y': // MMX_REGS if MMX allowed.
23324 if (!Subtarget->hasMMX()) break;
23325 return std::make_pair(0U, &X86::VR64RegClass);
23326 case 'Y': // SSE_REGS if SSE2 allowed
23327 if (!Subtarget->hasSSE2()) break;
23329 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23330 if (!Subtarget->hasSSE1()) break;
23332 switch (VT.SimpleTy) {
23334 // Scalar SSE types.
23337 return std::make_pair(0U, &X86::FR32RegClass);
23340 return std::make_pair(0U, &X86::FR64RegClass);
23348 return std::make_pair(0U, &X86::VR128RegClass);
23356 return std::make_pair(0U, &X86::VR256RegClass);
23361 return std::make_pair(0U, &X86::VR512RegClass);
23367 // Use the default implementation in TargetLowering to convert the register
23368 // constraint into a member of a register class.
23369 std::pair<unsigned, const TargetRegisterClass*> Res;
23370 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23372 // Not found as a standard register?
23374 // Map st(0) -> st(7) -> ST0
23375 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23376 tolower(Constraint[1]) == 's' &&
23377 tolower(Constraint[2]) == 't' &&
23378 Constraint[3] == '(' &&
23379 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23380 Constraint[5] == ')' &&
23381 Constraint[6] == '}') {
23383 Res.first = X86::FP0+Constraint[4]-'0';
23384 Res.second = &X86::RFP80RegClass;
23388 // GCC allows "st(0)" to be called just plain "st".
23389 if (StringRef("{st}").equals_lower(Constraint)) {
23390 Res.first = X86::FP0;
23391 Res.second = &X86::RFP80RegClass;
23396 if (StringRef("{flags}").equals_lower(Constraint)) {
23397 Res.first = X86::EFLAGS;
23398 Res.second = &X86::CCRRegClass;
23402 // 'A' means EAX + EDX.
23403 if (Constraint == "A") {
23404 Res.first = X86::EAX;
23405 Res.second = &X86::GR32_ADRegClass;
23411 // Otherwise, check to see if this is a register class of the wrong value
23412 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23413 // turn into {ax},{dx}.
23414 if (Res.second->hasType(VT))
23415 return Res; // Correct type already, nothing to do.
23417 // All of the single-register GCC register classes map their values onto
23418 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23419 // really want an 8-bit or 32-bit register, map to the appropriate register
23420 // class and return the appropriate register.
23421 if (Res.second == &X86::GR16RegClass) {
23422 if (VT == MVT::i8 || VT == MVT::i1) {
23423 unsigned DestReg = 0;
23424 switch (Res.first) {
23426 case X86::AX: DestReg = X86::AL; break;
23427 case X86::DX: DestReg = X86::DL; break;
23428 case X86::CX: DestReg = X86::CL; break;
23429 case X86::BX: DestReg = X86::BL; break;
23432 Res.first = DestReg;
23433 Res.second = &X86::GR8RegClass;
23435 } else if (VT == MVT::i32 || VT == MVT::f32) {
23436 unsigned DestReg = 0;
23437 switch (Res.first) {
23439 case X86::AX: DestReg = X86::EAX; break;
23440 case X86::DX: DestReg = X86::EDX; break;
23441 case X86::CX: DestReg = X86::ECX; break;
23442 case X86::BX: DestReg = X86::EBX; break;
23443 case X86::SI: DestReg = X86::ESI; break;
23444 case X86::DI: DestReg = X86::EDI; break;
23445 case X86::BP: DestReg = X86::EBP; break;
23446 case X86::SP: DestReg = X86::ESP; break;
23449 Res.first = DestReg;
23450 Res.second = &X86::GR32RegClass;
23452 } else if (VT == MVT::i64 || VT == MVT::f64) {
23453 unsigned DestReg = 0;
23454 switch (Res.first) {
23456 case X86::AX: DestReg = X86::RAX; break;
23457 case X86::DX: DestReg = X86::RDX; break;
23458 case X86::CX: DestReg = X86::RCX; break;
23459 case X86::BX: DestReg = X86::RBX; break;
23460 case X86::SI: DestReg = X86::RSI; break;
23461 case X86::DI: DestReg = X86::RDI; break;
23462 case X86::BP: DestReg = X86::RBP; break;
23463 case X86::SP: DestReg = X86::RSP; break;
23466 Res.first = DestReg;
23467 Res.second = &X86::GR64RegClass;
23470 } else if (Res.second == &X86::FR32RegClass ||
23471 Res.second == &X86::FR64RegClass ||
23472 Res.second == &X86::VR128RegClass ||
23473 Res.second == &X86::VR256RegClass ||
23474 Res.second == &X86::FR32XRegClass ||
23475 Res.second == &X86::FR64XRegClass ||
23476 Res.second == &X86::VR128XRegClass ||
23477 Res.second == &X86::VR256XRegClass ||
23478 Res.second == &X86::VR512RegClass) {
23479 // Handle references to XMM physical registers that got mapped into the
23480 // wrong class. This can happen with constraints like {xmm0} where the
23481 // target independent register mapper will just pick the first match it can
23482 // find, ignoring the required type.
23484 if (VT == MVT::f32 || VT == MVT::i32)
23485 Res.second = &X86::FR32RegClass;
23486 else if (VT == MVT::f64 || VT == MVT::i64)
23487 Res.second = &X86::FR64RegClass;
23488 else if (X86::VR128RegClass.hasType(VT))
23489 Res.second = &X86::VR128RegClass;
23490 else if (X86::VR256RegClass.hasType(VT))
23491 Res.second = &X86::VR256RegClass;
23492 else if (X86::VR512RegClass.hasType(VT))
23493 Res.second = &X86::VR512RegClass;
23499 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23501 // Scaling factors are not free at all.
23502 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23503 // will take 2 allocations in the out of order engine instead of 1
23504 // for plain addressing mode, i.e. inst (reg1).
23506 // vaddps (%rsi,%drx), %ymm0, %ymm1
23507 // Requires two allocations (one for the load, one for the computation)
23509 // vaddps (%rsi), %ymm0, %ymm1
23510 // Requires just 1 allocation, i.e., freeing allocations for other operations
23511 // and having less micro operations to execute.
23513 // For some X86 architectures, this is even worse because for instance for
23514 // stores, the complex addressing mode forces the instruction to use the
23515 // "load" ports instead of the dedicated "store" port.
23516 // E.g., on Haswell:
23517 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23518 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23519 if (isLegalAddressingMode(AM, Ty))
23520 // Scale represents reg2 * scale, thus account for 1
23521 // as soon as we use a second register.
23522 return AM.Scale != 0;
23526 bool X86TargetLowering::isTargetFTOL() const {
23527 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();