1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/VectorExtras.h"
27 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/StringExtras.h"
39 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
40 : TargetLowering(TM) {
41 Subtarget = &TM.getSubtarget<X86Subtarget>();
42 X86ScalarSSE = Subtarget->hasSSE2();
43 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
45 // Set up the TargetLowering object.
47 // X86 is weird, it always uses i8 for shift amounts and setcc results.
48 setShiftAmountType(MVT::i8);
49 setSetCCResultType(MVT::i8);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
51 setSchedulingPreference(SchedulingForRegPressure);
52 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
53 setStackPointerRegisterToSaveRestore(X86StackPtr);
55 if (Subtarget->isTargetDarwin()) {
56 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
57 setUseUnderscoreSetJmp(false);
58 setUseUnderscoreLongJmp(false);
59 } else if (Subtarget->isTargetMingw()) {
60 // MS runtime is weird: it exports _setjmp, but longjmp!
61 setUseUnderscoreSetJmp(true);
62 setUseUnderscoreLongJmp(false);
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
68 // Set up the register classes.
69 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
70 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
71 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
72 if (Subtarget->is64Bit())
73 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
75 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
77 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
79 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
80 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
81 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
83 if (Subtarget->is64Bit()) {
84 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
85 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
88 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
89 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
91 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
94 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
96 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
97 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
98 // SSE has no i16 to fp conversion, only i32
100 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
102 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
103 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
106 if (!Subtarget->is64Bit()) {
107 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
108 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
109 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
112 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
114 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
115 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
118 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
120 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
124 // Handle FP_TO_UINT by promoting the destination to a larger signed
126 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
127 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
128 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
130 if (Subtarget->is64Bit()) {
131 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
132 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
134 if (X86ScalarSSE && !Subtarget->hasSSE3())
135 // Expand FP_TO_UINT into a select.
136 // FIXME: We would like to use a Custom expander here eventually to do
137 // the optimal thing for SSE vs. the default expansion in the legalizer.
138 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
140 // With SSE3 we can use fisttpll to convert to a signed i64.
141 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
144 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
146 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
147 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
150 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
151 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
152 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
153 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
154 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
155 if (Subtarget->is64Bit())
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
160 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
161 setOperationAction(ISD::FREM , MVT::f64 , Expand);
163 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
164 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
165 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
166 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
167 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
168 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
169 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
170 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
171 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
172 if (Subtarget->is64Bit()) {
173 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
175 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
178 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
179 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
181 // These should be promoted to a larger select which is supported.
182 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
183 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
184 // X86 wants to expand cmov itself.
185 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
186 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
187 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
188 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
189 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
190 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
191 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
192 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
193 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
194 if (Subtarget->is64Bit()) {
195 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
196 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
198 // X86 ret instruction may pop stack.
199 setOperationAction(ISD::RET , MVT::Other, Custom);
201 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
202 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
203 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
204 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
205 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
206 if (Subtarget->is64Bit()) {
207 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
208 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
209 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
210 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
212 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
213 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
214 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
215 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
216 // X86 wants to expand memset / memcpy itself.
217 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
218 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
220 // We don't have line number support yet.
221 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
222 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
223 // FIXME - use subtarget debug flags
224 if (!Subtarget->isTargetDarwin() &&
225 !Subtarget->isTargetELF() &&
226 !Subtarget->isTargetCygMing())
227 setOperationAction(ISD::LABEL, MVT::Other, Expand);
229 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
230 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
231 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
232 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
233 if (Subtarget->is64Bit()) {
235 setExceptionPointerRegister(X86::RAX);
236 setExceptionSelectorRegister(X86::RDX);
238 setExceptionPointerRegister(X86::EAX);
239 setExceptionSelectorRegister(X86::EDX);
242 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
243 setOperationAction(ISD::VASTART , MVT::Other, Custom);
244 setOperationAction(ISD::VAARG , MVT::Other, Expand);
245 setOperationAction(ISD::VAEND , MVT::Other, Expand);
246 if (Subtarget->is64Bit())
247 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
249 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
251 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
252 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
253 if (Subtarget->is64Bit())
254 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
255 if (Subtarget->isTargetCygMing())
256 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
258 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
261 // Set up the FP register classes.
262 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
263 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
265 // Use ANDPD to simulate FABS.
266 setOperationAction(ISD::FABS , MVT::f64, Custom);
267 setOperationAction(ISD::FABS , MVT::f32, Custom);
269 // Use XORP to simulate FNEG.
270 setOperationAction(ISD::FNEG , MVT::f64, Custom);
271 setOperationAction(ISD::FNEG , MVT::f32, Custom);
273 // Use ANDPD and ORPD to simulate FCOPYSIGN.
274 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
275 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
277 // We don't support sin/cos/fmod
278 setOperationAction(ISD::FSIN , MVT::f64, Expand);
279 setOperationAction(ISD::FCOS , MVT::f64, Expand);
280 setOperationAction(ISD::FREM , MVT::f64, Expand);
281 setOperationAction(ISD::FSIN , MVT::f32, Expand);
282 setOperationAction(ISD::FCOS , MVT::f32, Expand);
283 setOperationAction(ISD::FREM , MVT::f32, Expand);
285 // Expand FP immediates into loads from the stack, except for the special
287 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
288 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
289 addLegalFPImmediate(+0.0); // xorps / xorpd
291 // Set up the FP register classes.
292 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
293 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
295 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
296 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
297 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
298 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
299 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand);
302 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
303 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
306 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
307 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
308 addLegalFPImmediate(+0.0); // FLD0
309 addLegalFPImmediate(+1.0); // FLD1
310 addLegalFPImmediate(-0.0); // FLD0/FCHS
311 addLegalFPImmediate(-1.0); // FLD1/FCHS
314 // First set operation action for all vector types to expand. Then we
315 // will selectively turn on ones that can be effectively codegen'd.
316 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
317 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
318 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
319 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
320 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
321 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
322 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
323 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
324 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
325 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
326 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
327 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
328 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
329 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
330 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
331 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
333 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
336 if (Subtarget->hasMMX()) {
337 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
338 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
339 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
340 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
342 // FIXME: add MMX packed arithmetics
344 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
345 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
346 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
347 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
349 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
350 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
351 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
353 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
354 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
356 setOperationAction(ISD::AND, MVT::v8i8, Promote);
357 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
358 setOperationAction(ISD::AND, MVT::v4i16, Promote);
359 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
360 setOperationAction(ISD::AND, MVT::v2i32, Promote);
361 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
362 setOperationAction(ISD::AND, MVT::v1i64, Legal);
364 setOperationAction(ISD::OR, MVT::v8i8, Promote);
365 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
366 setOperationAction(ISD::OR, MVT::v4i16, Promote);
367 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
368 setOperationAction(ISD::OR, MVT::v2i32, Promote);
369 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
370 setOperationAction(ISD::OR, MVT::v1i64, Legal);
372 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
373 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
374 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
375 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
376 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
377 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
378 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
380 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
381 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
382 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
383 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
384 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
385 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
386 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
388 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
389 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
390 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
391 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
393 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
394 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
395 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
396 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
398 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
399 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
400 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
401 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
404 if (Subtarget->hasSSE1()) {
405 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
407 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
408 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
409 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
410 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
411 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
412 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
413 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
414 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
415 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
418 if (Subtarget->hasSSE2()) {
419 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
420 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
421 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
422 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
423 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
425 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
426 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
427 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
428 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
429 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
430 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
431 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
432 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
433 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
434 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
435 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
436 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
437 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
439 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
440 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
441 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
442 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
443 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
444 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
446 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
447 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
448 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
449 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
452 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
453 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
454 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
455 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
459 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
460 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
461 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
462 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
463 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
464 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
465 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
466 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
467 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
468 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
469 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
470 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
473 // Custom lower v2i64 and v2f64 selects.
474 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
475 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
476 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
477 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
480 // We want to custom lower some of our intrinsics.
481 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
483 // We have target-specific dag combine patterns for the following nodes:
484 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
485 setTargetDAGCombine(ISD::SELECT);
487 computeRegisterProperties();
489 // FIXME: These should be based on subtarget info. Plus, the values should
490 // be smaller when we are in optimizing for size mode.
491 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
492 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
493 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
494 allowUnalignedMemoryAccesses = true; // x86 supports it!
498 //===----------------------------------------------------------------------===//
499 // Return Value Calling Convention Implementation
500 //===----------------------------------------------------------------------===//
502 #include "X86GenCallingConv.inc"
504 /// LowerRET - Lower an ISD::RET node.
505 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
506 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
508 SmallVector<CCValAssign, 16> RVLocs;
509 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
510 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
511 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
512 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
515 // If this is the first return lowered for this function, add the regs to the
516 // liveout set for the function.
517 if (DAG.getMachineFunction().liveout_empty()) {
518 for (unsigned i = 0; i != RVLocs.size(); ++i)
519 if (RVLocs[i].isRegLoc())
520 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
523 SDOperand Chain = Op.getOperand(0);
526 // Copy the result values into the output registers.
527 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
528 RVLocs[0].getLocReg() != X86::ST0) {
529 for (unsigned i = 0; i != RVLocs.size(); ++i) {
530 CCValAssign &VA = RVLocs[i];
531 assert(VA.isRegLoc() && "Can only return in registers!");
532 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
534 Flag = Chain.getValue(1);
537 // We need to handle a destination of ST0 specially, because it isn't really
539 SDOperand Value = Op.getOperand(1);
541 // If this is an FP return with ScalarSSE, we need to move the value from
542 // an XMM register onto the fp-stack.
546 // If this is a load into a scalarsse value, don't store the loaded value
547 // back to the stack, only to reload it: just replace the scalar-sse load.
548 if (ISD::isNON_EXTLoad(Value.Val) &&
549 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
550 Chain = Value.getOperand(0);
551 MemLoc = Value.getOperand(1);
553 // Spill the value to memory and reload it into top of stack.
554 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
555 MachineFunction &MF = DAG.getMachineFunction();
556 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
557 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
558 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
560 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other);
561 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
562 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
563 Chain = Value.getValue(1);
566 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
567 SDOperand Ops[] = { Chain, Value };
568 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
569 Flag = Chain.getValue(1);
572 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
574 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
576 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
580 /// LowerCallResult - Lower the result values of an ISD::CALL into the
581 /// appropriate copies out of appropriate physical registers. This assumes that
582 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
583 /// being lowered. The returns a SDNode with the same number of values as the
585 SDNode *X86TargetLowering::
586 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
587 unsigned CallingConv, SelectionDAG &DAG) {
589 // Assign locations to each value returned by this call.
590 SmallVector<CCValAssign, 16> RVLocs;
591 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
592 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
593 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
596 SmallVector<SDOperand, 8> ResultVals;
598 // Copy all of the result registers out of their specified physreg.
599 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
600 for (unsigned i = 0; i != RVLocs.size(); ++i) {
601 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
602 RVLocs[i].getValVT(), InFlag).getValue(1);
603 InFlag = Chain.getValue(2);
604 ResultVals.push_back(Chain.getValue(0));
607 // Copies from the FP stack are special, as ST0 isn't a valid register
608 // before the fp stackifier runs.
610 // Copy ST0 into an RFP register with FP_GET_RESULT.
611 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other, MVT::Flag);
612 SDOperand GROps[] = { Chain, InFlag };
613 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
614 Chain = RetVal.getValue(1);
615 InFlag = RetVal.getValue(2);
617 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
620 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
621 // shouldn't be necessary except that RFP cannot be live across
622 // multiple blocks. When stackifier is fixed, they can be uncoupled.
623 MachineFunction &MF = DAG.getMachineFunction();
624 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
625 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
627 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag
629 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
630 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0);
631 Chain = RetVal.getValue(1);
633 ResultVals.push_back(RetVal);
636 // Merge everything together with a MERGE_VALUES node.
637 ResultVals.push_back(Chain);
638 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
639 &ResultVals[0], ResultVals.size()).Val;
643 //===----------------------------------------------------------------------===//
644 // C & StdCall Calling Convention implementation
645 //===----------------------------------------------------------------------===//
646 // StdCall calling convention seems to be standard for many Windows' API
647 // routines and around. It differs from C calling convention just a little:
648 // callee should clean up the stack, not caller. Symbols should be also
649 // decorated in some fancy way :) It doesn't support any vector arguments.
651 /// AddLiveIn - This helper function adds the specified physical register to the
652 /// MachineFunction as a live in value. It also creates a corresponding virtual
654 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
655 const TargetRegisterClass *RC) {
656 assert(RC->contains(PReg) && "Not the correct regclass!");
657 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
658 MF.addLiveIn(PReg, VReg);
662 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
664 unsigned NumArgs = Op.Val->getNumValues() - 1;
665 MachineFunction &MF = DAG.getMachineFunction();
666 MachineFrameInfo *MFI = MF.getFrameInfo();
667 SDOperand Root = Op.getOperand(0);
668 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
670 // Assign locations to all of the incoming arguments.
671 SmallVector<CCValAssign, 16> ArgLocs;
672 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
673 getTargetMachine(), ArgLocs);
674 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
676 SmallVector<SDOperand, 8> ArgValues;
677 unsigned LastVal = ~0U;
678 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
679 CCValAssign &VA = ArgLocs[i];
680 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
682 assert(VA.getValNo() != LastVal &&
683 "Don't support value assigned to multiple locs yet");
684 LastVal = VA.getValNo();
687 MVT::ValueType RegVT = VA.getLocVT();
688 TargetRegisterClass *RC;
689 if (RegVT == MVT::i32)
690 RC = X86::GR32RegisterClass;
692 assert(MVT::isVector(RegVT));
693 RC = X86::VR128RegisterClass;
696 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
697 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
699 // If this is an 8 or 16-bit value, it is really passed promoted to 32
700 // bits. Insert an assert[sz]ext to capture this, then truncate to the
702 if (VA.getLocInfo() == CCValAssign::SExt)
703 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
704 DAG.getValueType(VA.getValVT()));
705 else if (VA.getLocInfo() == CCValAssign::ZExt)
706 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
707 DAG.getValueType(VA.getValVT()));
709 if (VA.getLocInfo() != CCValAssign::Full)
710 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
712 ArgValues.push_back(ArgValue);
714 assert(VA.isMemLoc());
716 // Create the nodes corresponding to a load from this parameter slot.
717 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
718 VA.getLocMemOffset());
719 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
720 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
724 unsigned StackSize = CCInfo.getNextStackOffset();
726 ArgValues.push_back(Root);
728 // If the function takes variable number of arguments, make a frame index for
729 // the start of the first vararg value... for expansion of llvm.va_start.
731 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
733 if (isStdCall && !isVarArg) {
734 BytesToPopOnReturn = StackSize; // Callee pops everything..
735 BytesCallerReserves = 0;
737 BytesToPopOnReturn = 0; // Callee pops nothing.
739 // If this is an sret function, the return should pop the hidden pointer.
741 (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
742 ISD::ParamFlags::StructReturn))
743 BytesToPopOnReturn = 4;
745 BytesCallerReserves = StackSize;
748 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
749 ReturnAddrIndex = 0; // No return address slot generated yet.
751 MF.getInfo<X86MachineFunctionInfo>()
752 ->setBytesToPopOnReturn(BytesToPopOnReturn);
754 // Return the new list of results.
755 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
756 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
759 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
761 SDOperand Chain = Op.getOperand(0);
762 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
763 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
764 SDOperand Callee = Op.getOperand(4);
765 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
767 // Analyze operands of the call, assigning locations to each operand.
768 SmallVector<CCValAssign, 16> ArgLocs;
769 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
770 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
772 // Get a count of how many bytes are to be pushed on the stack.
773 unsigned NumBytes = CCInfo.getNextStackOffset();
775 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
777 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
778 SmallVector<SDOperand, 8> MemOpChains;
782 // Walk the register/memloc assignments, inserting copies/loads.
783 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
784 CCValAssign &VA = ArgLocs[i];
785 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
787 // Promote the value if needed.
788 switch (VA.getLocInfo()) {
789 default: assert(0 && "Unknown loc info!");
790 case CCValAssign::Full: break;
791 case CCValAssign::SExt:
792 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
794 case CCValAssign::ZExt:
795 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
797 case CCValAssign::AExt:
798 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
803 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
805 assert(VA.isMemLoc());
806 if (StackPtr.Val == 0)
807 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
808 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
809 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
810 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
814 // If the first argument is an sret pointer, remember it.
815 bool isSRet = NumOps &&
816 (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
817 ISD::ParamFlags::StructReturn);
819 if (!MemOpChains.empty())
820 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
821 &MemOpChains[0], MemOpChains.size());
823 // Build a sequence of copy-to-reg nodes chained together with token chain
824 // and flag operands which copy the outgoing args into registers.
826 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
827 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
829 InFlag = Chain.getValue(1);
832 // ELF / PIC requires GOT in the EBX register before function calls via PLT
834 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
835 Subtarget->isPICStyleGOT()) {
836 Chain = DAG.getCopyToReg(Chain, X86::EBX,
837 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
839 InFlag = Chain.getValue(1);
842 // If the callee is a GlobalAddress node (quite common, every direct call is)
843 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
844 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
845 // We should use extra load for direct calls to dllimported functions in
847 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
848 getTargetMachine(), true))
849 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
850 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
851 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
853 // Returns a chain & a flag for retval copy to use.
854 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
855 SmallVector<SDOperand, 8> Ops;
856 Ops.push_back(Chain);
857 Ops.push_back(Callee);
859 // Add argument registers to the end of the list so that they are known live
861 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
862 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
863 RegsToPass[i].second.getValueType()));
865 // Add an implicit use GOT pointer in EBX.
866 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
867 Subtarget->isPICStyleGOT())
868 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
871 Ops.push_back(InFlag);
873 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
874 NodeTys, &Ops[0], Ops.size());
875 InFlag = Chain.getValue(1);
877 // Create the CALLSEQ_END node.
878 unsigned NumBytesForCalleeToPush = 0;
880 if (CC == CallingConv::X86_StdCall) {
882 NumBytesForCalleeToPush = isSRet ? 4 : 0;
884 NumBytesForCalleeToPush = NumBytes;
886 // If this is is a call to a struct-return function, the callee
887 // pops the hidden struct pointer, so we have to push it back.
888 // This is common for Darwin/X86, Linux & Mingw32 targets.
889 NumBytesForCalleeToPush = isSRet ? 4 : 0;
892 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
894 Ops.push_back(Chain);
895 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
896 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
897 Ops.push_back(InFlag);
898 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
899 InFlag = Chain.getValue(1);
901 // Handle result values, copying them out of physregs into vregs that we
903 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
907 //===----------------------------------------------------------------------===//
908 // FastCall Calling Convention implementation
909 //===----------------------------------------------------------------------===//
911 // The X86 'fastcall' calling convention passes up to two integer arguments in
912 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
913 // and requires that the callee pop its arguments off the stack (allowing proper
914 // tail calls), and has the same return value conventions as C calling convs.
916 // This calling convention always arranges for the callee pop value to be 8n+4
917 // bytes, which is needed for tail recursion elimination and stack alignment
920 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
921 MachineFunction &MF = DAG.getMachineFunction();
922 MachineFrameInfo *MFI = MF.getFrameInfo();
923 SDOperand Root = Op.getOperand(0);
924 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
926 // Assign locations to all of the incoming arguments.
927 SmallVector<CCValAssign, 16> ArgLocs;
928 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
929 getTargetMachine(), ArgLocs);
930 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
932 SmallVector<SDOperand, 8> ArgValues;
933 unsigned LastVal = ~0U;
934 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
935 CCValAssign &VA = ArgLocs[i];
936 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
938 assert(VA.getValNo() != LastVal &&
939 "Don't support value assigned to multiple locs yet");
940 LastVal = VA.getValNo();
943 MVT::ValueType RegVT = VA.getLocVT();
944 TargetRegisterClass *RC;
945 if (RegVT == MVT::i32)
946 RC = X86::GR32RegisterClass;
948 assert(MVT::isVector(RegVT));
949 RC = X86::VR128RegisterClass;
952 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
953 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
955 // If this is an 8 or 16-bit value, it is really passed promoted to 32
956 // bits. Insert an assert[sz]ext to capture this, then truncate to the
958 if (VA.getLocInfo() == CCValAssign::SExt)
959 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
960 DAG.getValueType(VA.getValVT()));
961 else if (VA.getLocInfo() == CCValAssign::ZExt)
962 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
963 DAG.getValueType(VA.getValVT()));
965 if (VA.getLocInfo() != CCValAssign::Full)
966 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
968 ArgValues.push_back(ArgValue);
970 assert(VA.isMemLoc());
972 // Create the nodes corresponding to a load from this parameter slot.
973 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
974 VA.getLocMemOffset());
975 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
976 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
980 ArgValues.push_back(Root);
982 unsigned StackSize = CCInfo.getNextStackOffset();
984 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
985 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
986 // arguments and the arguments after the retaddr has been pushed are aligned.
987 if ((StackSize & 7) == 0)
991 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
992 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
993 ReturnAddrIndex = 0; // No return address slot generated yet.
994 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
995 BytesCallerReserves = 0;
997 MF.getInfo<X86MachineFunctionInfo>()
998 ->setBytesToPopOnReturn(BytesToPopOnReturn);
1000 // Return the new list of results.
1001 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1002 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1005 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1007 SDOperand Chain = Op.getOperand(0);
1008 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1009 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1010 SDOperand Callee = Op.getOperand(4);
1012 // Analyze operands of the call, assigning locations to each operand.
1013 SmallVector<CCValAssign, 16> ArgLocs;
1014 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1015 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
1017 // Get a count of how many bytes are to be pushed on the stack.
1018 unsigned NumBytes = CCInfo.getNextStackOffset();
1020 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1021 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1022 // arguments and the arguments after the retaddr has been pushed are aligned.
1023 if ((NumBytes & 7) == 0)
1027 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1029 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1030 SmallVector<SDOperand, 8> MemOpChains;
1034 // Walk the register/memloc assignments, inserting copies/loads.
1035 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1036 CCValAssign &VA = ArgLocs[i];
1037 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1039 // Promote the value if needed.
1040 switch (VA.getLocInfo()) {
1041 default: assert(0 && "Unknown loc info!");
1042 case CCValAssign::Full: break;
1043 case CCValAssign::SExt:
1044 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1046 case CCValAssign::ZExt:
1047 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1049 case CCValAssign::AExt:
1050 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1054 if (VA.isRegLoc()) {
1055 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1057 assert(VA.isMemLoc());
1058 if (StackPtr.Val == 0)
1059 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1060 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1061 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1062 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1066 if (!MemOpChains.empty())
1067 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1068 &MemOpChains[0], MemOpChains.size());
1070 // Build a sequence of copy-to-reg nodes chained together with token chain
1071 // and flag operands which copy the outgoing args into registers.
1073 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1074 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1076 InFlag = Chain.getValue(1);
1079 // If the callee is a GlobalAddress node (quite common, every direct call is)
1080 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1081 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1082 // We should use extra load for direct calls to dllimported functions in
1084 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1085 getTargetMachine(), true))
1086 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1087 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1088 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1090 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1092 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1093 Subtarget->isPICStyleGOT()) {
1094 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1095 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1097 InFlag = Chain.getValue(1);
1100 // Returns a chain & a flag for retval copy to use.
1101 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1102 SmallVector<SDOperand, 8> Ops;
1103 Ops.push_back(Chain);
1104 Ops.push_back(Callee);
1106 // Add argument registers to the end of the list so that they are known live
1108 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1109 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1110 RegsToPass[i].second.getValueType()));
1112 // Add an implicit use GOT pointer in EBX.
1113 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1114 Subtarget->isPICStyleGOT())
1115 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1118 Ops.push_back(InFlag);
1120 // FIXME: Do not generate X86ISD::TAILCALL for now.
1121 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1122 NodeTys, &Ops[0], Ops.size());
1123 InFlag = Chain.getValue(1);
1125 // Returns a flag for retval copy to use.
1126 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1128 Ops.push_back(Chain);
1129 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1130 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1131 Ops.push_back(InFlag);
1132 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1133 InFlag = Chain.getValue(1);
1135 // Handle result values, copying them out of physregs into vregs that we
1137 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1141 //===----------------------------------------------------------------------===//
1142 // X86-64 C Calling Convention implementation
1143 //===----------------------------------------------------------------------===//
1146 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1147 MachineFunction &MF = DAG.getMachineFunction();
1148 MachineFrameInfo *MFI = MF.getFrameInfo();
1149 SDOperand Root = Op.getOperand(0);
1150 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1152 static const unsigned GPR64ArgRegs[] = {
1153 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1155 static const unsigned XMMArgRegs[] = {
1156 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1157 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1161 // Assign locations to all of the incoming arguments.
1162 SmallVector<CCValAssign, 16> ArgLocs;
1163 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
1164 getTargetMachine(), ArgLocs);
1165 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
1167 SmallVector<SDOperand, 8> ArgValues;
1168 unsigned LastVal = ~0U;
1169 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1170 CCValAssign &VA = ArgLocs[i];
1171 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1173 assert(VA.getValNo() != LastVal &&
1174 "Don't support value assigned to multiple locs yet");
1175 LastVal = VA.getValNo();
1177 if (VA.isRegLoc()) {
1178 MVT::ValueType RegVT = VA.getLocVT();
1179 TargetRegisterClass *RC;
1180 if (RegVT == MVT::i32)
1181 RC = X86::GR32RegisterClass;
1182 else if (RegVT == MVT::i64)
1183 RC = X86::GR64RegisterClass;
1184 else if (RegVT == MVT::f32)
1185 RC = X86::FR32RegisterClass;
1186 else if (RegVT == MVT::f64)
1187 RC = X86::FR64RegisterClass;
1189 assert(MVT::isVector(RegVT));
1190 if (MVT::getSizeInBits(RegVT) == 64) {
1191 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1194 RC = X86::VR128RegisterClass;
1197 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1198 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1200 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1201 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1203 if (VA.getLocInfo() == CCValAssign::SExt)
1204 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1205 DAG.getValueType(VA.getValVT()));
1206 else if (VA.getLocInfo() == CCValAssign::ZExt)
1207 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1208 DAG.getValueType(VA.getValVT()));
1210 if (VA.getLocInfo() != CCValAssign::Full)
1211 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1213 // Handle MMX values passed in GPRs.
1214 if (RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1215 MVT::getSizeInBits(RegVT) == 64)
1216 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1218 ArgValues.push_back(ArgValue);
1220 assert(VA.isMemLoc());
1222 // Create the nodes corresponding to a load from this parameter slot.
1223 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1224 VA.getLocMemOffset());
1225 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1226 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1230 unsigned StackSize = CCInfo.getNextStackOffset();
1232 // If the function takes variable number of arguments, make a frame index for
1233 // the start of the first vararg value... for expansion of llvm.va_start.
1235 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1236 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1238 // For X86-64, if there are vararg parameters that are passed via
1239 // registers, then we must store them to their spots on the stack so they
1240 // may be loaded by deferencing the result of va_next.
1241 VarArgsGPOffset = NumIntRegs * 8;
1242 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1243 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1244 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1246 // Store the integer parameter registers.
1247 SmallVector<SDOperand, 8> MemOps;
1248 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1249 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1250 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1251 for (; NumIntRegs != 6; ++NumIntRegs) {
1252 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1253 X86::GR64RegisterClass);
1254 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1255 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1256 MemOps.push_back(Store);
1257 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1258 DAG.getConstant(8, getPointerTy()));
1261 // Now store the XMM (fp + vector) parameter registers.
1262 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1263 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1264 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1265 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1266 X86::VR128RegisterClass);
1267 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1268 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1269 MemOps.push_back(Store);
1270 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1271 DAG.getConstant(16, getPointerTy()));
1273 if (!MemOps.empty())
1274 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1275 &MemOps[0], MemOps.size());
1278 ArgValues.push_back(Root);
1280 ReturnAddrIndex = 0; // No return address slot generated yet.
1281 BytesToPopOnReturn = 0; // Callee pops nothing.
1282 BytesCallerReserves = StackSize;
1284 // Return the new list of results.
1285 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1286 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1290 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1292 SDOperand Chain = Op.getOperand(0);
1293 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1294 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1295 SDOperand Callee = Op.getOperand(4);
1297 // Analyze operands of the call, assigning locations to each operand.
1298 SmallVector<CCValAssign, 16> ArgLocs;
1299 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1300 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_64_C);
1302 // Get a count of how many bytes are to be pushed on the stack.
1303 unsigned NumBytes = CCInfo.getNextStackOffset();
1304 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1306 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1307 SmallVector<SDOperand, 8> MemOpChains;
1311 // Walk the register/memloc assignments, inserting copies/loads.
1312 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1313 CCValAssign &VA = ArgLocs[i];
1314 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1316 // Promote the value if needed.
1317 switch (VA.getLocInfo()) {
1318 default: assert(0 && "Unknown loc info!");
1319 case CCValAssign::Full: break;
1320 case CCValAssign::SExt:
1321 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1323 case CCValAssign::ZExt:
1324 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1326 case CCValAssign::AExt:
1327 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1331 if (VA.isRegLoc()) {
1332 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1334 assert(VA.isMemLoc());
1335 if (StackPtr.Val == 0)
1336 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1337 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1338 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1339 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1343 if (!MemOpChains.empty())
1344 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1345 &MemOpChains[0], MemOpChains.size());
1347 // Build a sequence of copy-to-reg nodes chained together with token chain
1348 // and flag operands which copy the outgoing args into registers.
1350 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1351 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1353 InFlag = Chain.getValue(1);
1357 // From AMD64 ABI document:
1358 // For calls that may call functions that use varargs or stdargs
1359 // (prototype-less calls or calls to functions containing ellipsis (...) in
1360 // the declaration) %al is used as hidden argument to specify the number
1361 // of SSE registers used. The contents of %al do not need to match exactly
1362 // the number of registers, but must be an ubound on the number of SSE
1363 // registers used and is in the range 0 - 8 inclusive.
1365 // Count the number of XMM registers allocated.
1366 static const unsigned XMMArgRegs[] = {
1367 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1368 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1370 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1372 Chain = DAG.getCopyToReg(Chain, X86::AL,
1373 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1374 InFlag = Chain.getValue(1);
1377 // If the callee is a GlobalAddress node (quite common, every direct call is)
1378 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1379 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1380 // We should use extra load for direct calls to dllimported functions in
1382 if (getTargetMachine().getCodeModel() != CodeModel::Large
1383 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1384 getTargetMachine(), true))
1385 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1386 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1387 if (getTargetMachine().getCodeModel() != CodeModel::Large)
1388 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1390 // Returns a chain & a flag for retval copy to use.
1391 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1392 SmallVector<SDOperand, 8> Ops;
1393 Ops.push_back(Chain);
1394 Ops.push_back(Callee);
1396 // Add argument registers to the end of the list so that they are known live
1398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1399 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1400 RegsToPass[i].second.getValueType()));
1403 Ops.push_back(InFlag);
1405 // FIXME: Do not generate X86ISD::TAILCALL for now.
1406 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1407 NodeTys, &Ops[0], Ops.size());
1408 InFlag = Chain.getValue(1);
1410 // Returns a flag for retval copy to use.
1411 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1413 Ops.push_back(Chain);
1414 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1415 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1416 Ops.push_back(InFlag);
1417 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1418 InFlag = Chain.getValue(1);
1420 // Handle result values, copying them out of physregs into vregs that we
1422 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1426 //===----------------------------------------------------------------------===//
1427 // Other Lowering Hooks
1428 //===----------------------------------------------------------------------===//
1431 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1432 if (ReturnAddrIndex == 0) {
1433 // Set up a frame object for the return address.
1434 MachineFunction &MF = DAG.getMachineFunction();
1435 if (Subtarget->is64Bit())
1436 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1438 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1441 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1446 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1447 /// specific condition code. It returns a false if it cannot do a direct
1448 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1450 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1451 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1452 SelectionDAG &DAG) {
1453 X86CC = X86::COND_INVALID;
1455 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1456 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1457 // X > -1 -> X == 0, jump !sign.
1458 RHS = DAG.getConstant(0, RHS.getValueType());
1459 X86CC = X86::COND_NS;
1461 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1462 // X < 0 -> X == 0, jump on sign.
1463 X86CC = X86::COND_S;
1468 switch (SetCCOpcode) {
1470 case ISD::SETEQ: X86CC = X86::COND_E; break;
1471 case ISD::SETGT: X86CC = X86::COND_G; break;
1472 case ISD::SETGE: X86CC = X86::COND_GE; break;
1473 case ISD::SETLT: X86CC = X86::COND_L; break;
1474 case ISD::SETLE: X86CC = X86::COND_LE; break;
1475 case ISD::SETNE: X86CC = X86::COND_NE; break;
1476 case ISD::SETULT: X86CC = X86::COND_B; break;
1477 case ISD::SETUGT: X86CC = X86::COND_A; break;
1478 case ISD::SETULE: X86CC = X86::COND_BE; break;
1479 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1482 // On a floating point condition, the flags are set as follows:
1484 // 0 | 0 | 0 | X > Y
1485 // 0 | 0 | 1 | X < Y
1486 // 1 | 0 | 0 | X == Y
1487 // 1 | 1 | 1 | unordered
1489 switch (SetCCOpcode) {
1492 case ISD::SETEQ: X86CC = X86::COND_E; break;
1493 case ISD::SETOLT: Flip = true; // Fallthrough
1495 case ISD::SETGT: X86CC = X86::COND_A; break;
1496 case ISD::SETOLE: Flip = true; // Fallthrough
1498 case ISD::SETGE: X86CC = X86::COND_AE; break;
1499 case ISD::SETUGT: Flip = true; // Fallthrough
1501 case ISD::SETLT: X86CC = X86::COND_B; break;
1502 case ISD::SETUGE: Flip = true; // Fallthrough
1504 case ISD::SETLE: X86CC = X86::COND_BE; break;
1506 case ISD::SETNE: X86CC = X86::COND_NE; break;
1507 case ISD::SETUO: X86CC = X86::COND_P; break;
1508 case ISD::SETO: X86CC = X86::COND_NP; break;
1511 std::swap(LHS, RHS);
1514 return X86CC != X86::COND_INVALID;
1517 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1518 /// code. Current x86 isa includes the following FP cmov instructions:
1519 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1520 static bool hasFPCMov(unsigned X86CC) {
1536 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1537 /// true if Op is undef or if its value falls within the specified range (L, H].
1538 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1539 if (Op.getOpcode() == ISD::UNDEF)
1542 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1543 return (Val >= Low && Val < Hi);
1546 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1547 /// true if Op is undef or if its value equal to the specified value.
1548 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1549 if (Op.getOpcode() == ISD::UNDEF)
1551 return cast<ConstantSDNode>(Op)->getValue() == Val;
1554 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1555 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1556 bool X86::isPSHUFDMask(SDNode *N) {
1557 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1559 if (N->getNumOperands() != 4)
1562 // Check if the value doesn't reference the second vector.
1563 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1564 SDOperand Arg = N->getOperand(i);
1565 if (Arg.getOpcode() == ISD::UNDEF) continue;
1566 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1567 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
1574 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1575 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1576 bool X86::isPSHUFHWMask(SDNode *N) {
1577 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1579 if (N->getNumOperands() != 8)
1582 // Lower quadword copied in order.
1583 for (unsigned i = 0; i != 4; ++i) {
1584 SDOperand Arg = N->getOperand(i);
1585 if (Arg.getOpcode() == ISD::UNDEF) continue;
1586 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1587 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1591 // Upper quadword shuffled.
1592 for (unsigned i = 4; i != 8; ++i) {
1593 SDOperand Arg = N->getOperand(i);
1594 if (Arg.getOpcode() == ISD::UNDEF) continue;
1595 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1596 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1597 if (Val < 4 || Val > 7)
1604 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1605 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1606 bool X86::isPSHUFLWMask(SDNode *N) {
1607 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1609 if (N->getNumOperands() != 8)
1612 // Upper quadword copied in order.
1613 for (unsigned i = 4; i != 8; ++i)
1614 if (!isUndefOrEqual(N->getOperand(i), i))
1617 // Lower quadword shuffled.
1618 for (unsigned i = 0; i != 4; ++i)
1619 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1625 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1626 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1627 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1628 if (NumElems != 2 && NumElems != 4) return false;
1630 unsigned Half = NumElems / 2;
1631 for (unsigned i = 0; i < Half; ++i)
1632 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1634 for (unsigned i = Half; i < NumElems; ++i)
1635 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1641 bool X86::isSHUFPMask(SDNode *N) {
1642 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1643 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1646 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
1647 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1648 /// half elements to come from vector 1 (which would equal the dest.) and
1649 /// the upper half to come from vector 2.
1650 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1651 if (NumOps != 2 && NumOps != 4) return false;
1653 unsigned Half = NumOps / 2;
1654 for (unsigned i = 0; i < Half; ++i)
1655 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1657 for (unsigned i = Half; i < NumOps; ++i)
1658 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1663 static bool isCommutedSHUFP(SDNode *N) {
1664 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1665 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1668 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1669 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1670 bool X86::isMOVHLPSMask(SDNode *N) {
1671 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1673 if (N->getNumOperands() != 4)
1676 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1677 return isUndefOrEqual(N->getOperand(0), 6) &&
1678 isUndefOrEqual(N->getOperand(1), 7) &&
1679 isUndefOrEqual(N->getOperand(2), 2) &&
1680 isUndefOrEqual(N->getOperand(3), 3);
1683 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1684 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1686 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1687 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1689 if (N->getNumOperands() != 4)
1692 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1693 return isUndefOrEqual(N->getOperand(0), 2) &&
1694 isUndefOrEqual(N->getOperand(1), 3) &&
1695 isUndefOrEqual(N->getOperand(2), 2) &&
1696 isUndefOrEqual(N->getOperand(3), 3);
1699 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1700 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1701 bool X86::isMOVLPMask(SDNode *N) {
1702 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1704 unsigned NumElems = N->getNumOperands();
1705 if (NumElems != 2 && NumElems != 4)
1708 for (unsigned i = 0; i < NumElems/2; ++i)
1709 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1712 for (unsigned i = NumElems/2; i < NumElems; ++i)
1713 if (!isUndefOrEqual(N->getOperand(i), i))
1719 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1720 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1722 bool X86::isMOVHPMask(SDNode *N) {
1723 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1725 unsigned NumElems = N->getNumOperands();
1726 if (NumElems != 2 && NumElems != 4)
1729 for (unsigned i = 0; i < NumElems/2; ++i)
1730 if (!isUndefOrEqual(N->getOperand(i), i))
1733 for (unsigned i = 0; i < NumElems/2; ++i) {
1734 SDOperand Arg = N->getOperand(i + NumElems/2);
1735 if (!isUndefOrEqual(Arg, i + NumElems))
1742 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1743 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1744 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1745 bool V2IsSplat = false) {
1746 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1749 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1750 SDOperand BitI = Elts[i];
1751 SDOperand BitI1 = Elts[i+1];
1752 if (!isUndefOrEqual(BitI, j))
1755 if (isUndefOrEqual(BitI1, NumElts))
1758 if (!isUndefOrEqual(BitI1, j + NumElts))
1766 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1767 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1768 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1771 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1772 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1773 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
1774 bool V2IsSplat = false) {
1775 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1778 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1779 SDOperand BitI = Elts[i];
1780 SDOperand BitI1 = Elts[i+1];
1781 if (!isUndefOrEqual(BitI, j + NumElts/2))
1784 if (isUndefOrEqual(BitI1, NumElts))
1787 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
1795 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1796 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1797 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1800 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1801 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1803 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1804 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1806 unsigned NumElems = N->getNumOperands();
1807 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1810 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1811 SDOperand BitI = N->getOperand(i);
1812 SDOperand BitI1 = N->getOperand(i+1);
1814 if (!isUndefOrEqual(BitI, j))
1816 if (!isUndefOrEqual(BitI1, j))
1823 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
1824 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
1826 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
1827 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1829 unsigned NumElems = N->getNumOperands();
1830 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1833 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
1834 SDOperand BitI = N->getOperand(i);
1835 SDOperand BitI1 = N->getOperand(i + 1);
1837 if (!isUndefOrEqual(BitI, j))
1839 if (!isUndefOrEqual(BitI1, j))
1846 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
1847 /// specifies a shuffle of elements that is suitable for input to MOVSS,
1848 /// MOVSD, and MOVD, i.e. setting the lowest element.
1849 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
1850 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1853 if (!isUndefOrEqual(Elts[0], NumElts))
1856 for (unsigned i = 1; i < NumElts; ++i) {
1857 if (!isUndefOrEqual(Elts[i], i))
1864 bool X86::isMOVLMask(SDNode *N) {
1865 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1866 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
1869 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
1870 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
1871 /// element of vector 2 and the other elements to come from vector 1 in order.
1872 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
1873 bool V2IsSplat = false,
1874 bool V2IsUndef = false) {
1875 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
1878 if (!isUndefOrEqual(Ops[0], 0))
1881 for (unsigned i = 1; i < NumOps; ++i) {
1882 SDOperand Arg = Ops[i];
1883 if (!(isUndefOrEqual(Arg, i+NumOps) ||
1884 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
1885 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
1892 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
1893 bool V2IsUndef = false) {
1894 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1895 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
1896 V2IsSplat, V2IsUndef);
1899 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1900 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
1901 bool X86::isMOVSHDUPMask(SDNode *N) {
1902 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1904 if (N->getNumOperands() != 4)
1907 // Expect 1, 1, 3, 3
1908 for (unsigned i = 0; i < 2; ++i) {
1909 SDOperand Arg = N->getOperand(i);
1910 if (Arg.getOpcode() == ISD::UNDEF) continue;
1911 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1912 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1913 if (Val != 1) return false;
1917 for (unsigned i = 2; i < 4; ++i) {
1918 SDOperand Arg = N->getOperand(i);
1919 if (Arg.getOpcode() == ISD::UNDEF) continue;
1920 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1921 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1922 if (Val != 3) return false;
1926 // Don't use movshdup if it can be done with a shufps.
1930 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1931 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
1932 bool X86::isMOVSLDUPMask(SDNode *N) {
1933 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1935 if (N->getNumOperands() != 4)
1938 // Expect 0, 0, 2, 2
1939 for (unsigned i = 0; i < 2; ++i) {
1940 SDOperand Arg = N->getOperand(i);
1941 if (Arg.getOpcode() == ISD::UNDEF) continue;
1942 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1943 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1944 if (Val != 0) return false;
1948 for (unsigned i = 2; i < 4; ++i) {
1949 SDOperand Arg = N->getOperand(i);
1950 if (Arg.getOpcode() == ISD::UNDEF) continue;
1951 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1952 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1953 if (Val != 2) return false;
1957 // Don't use movshdup if it can be done with a shufps.
1961 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
1962 /// specifies a identity operation on the LHS or RHS.
1963 static bool isIdentityMask(SDNode *N, bool RHS = false) {
1964 unsigned NumElems = N->getNumOperands();
1965 for (unsigned i = 0; i < NumElems; ++i)
1966 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
1971 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
1972 /// a splat of a single element.
1973 static bool isSplatMask(SDNode *N) {
1974 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1976 // This is a splat operation if each element of the permute is the same, and
1977 // if the value doesn't reference the second vector.
1978 unsigned NumElems = N->getNumOperands();
1979 SDOperand ElementBase;
1981 for (; i != NumElems; ++i) {
1982 SDOperand Elt = N->getOperand(i);
1983 if (isa<ConstantSDNode>(Elt)) {
1989 if (!ElementBase.Val)
1992 for (; i != NumElems; ++i) {
1993 SDOperand Arg = N->getOperand(i);
1994 if (Arg.getOpcode() == ISD::UNDEF) continue;
1995 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1996 if (Arg != ElementBase) return false;
1999 // Make sure it is a splat of the first vector operand.
2000 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2003 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2004 /// a splat of a single element and it's a 2 or 4 element mask.
2005 bool X86::isSplatMask(SDNode *N) {
2006 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2008 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2009 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2011 return ::isSplatMask(N);
2014 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2015 /// specifies a splat of zero element.
2016 bool X86::isSplatLoMask(SDNode *N) {
2017 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2019 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2020 if (!isUndefOrEqual(N->getOperand(i), 0))
2025 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2026 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2028 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2029 unsigned NumOperands = N->getNumOperands();
2030 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2032 for (unsigned i = 0; i < NumOperands; ++i) {
2034 SDOperand Arg = N->getOperand(NumOperands-i-1);
2035 if (Arg.getOpcode() != ISD::UNDEF)
2036 Val = cast<ConstantSDNode>(Arg)->getValue();
2037 if (Val >= NumOperands) Val -= NumOperands;
2039 if (i != NumOperands - 1)
2046 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2047 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2049 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2051 // 8 nodes, but we only care about the last 4.
2052 for (unsigned i = 7; i >= 4; --i) {
2054 SDOperand Arg = N->getOperand(i);
2055 if (Arg.getOpcode() != ISD::UNDEF)
2056 Val = cast<ConstantSDNode>(Arg)->getValue();
2065 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2066 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2068 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2070 // 8 nodes, but we only care about the first 4.
2071 for (int i = 3; i >= 0; --i) {
2073 SDOperand Arg = N->getOperand(i);
2074 if (Arg.getOpcode() != ISD::UNDEF)
2075 Val = cast<ConstantSDNode>(Arg)->getValue();
2084 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2085 /// specifies a 8 element shuffle that can be broken into a pair of
2086 /// PSHUFHW and PSHUFLW.
2087 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2088 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2090 if (N->getNumOperands() != 8)
2093 // Lower quadword shuffled.
2094 for (unsigned i = 0; i != 4; ++i) {
2095 SDOperand Arg = N->getOperand(i);
2096 if (Arg.getOpcode() == ISD::UNDEF) continue;
2097 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2098 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2103 // Upper quadword shuffled.
2104 for (unsigned i = 4; i != 8; ++i) {
2105 SDOperand Arg = N->getOperand(i);
2106 if (Arg.getOpcode() == ISD::UNDEF) continue;
2107 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2108 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2109 if (Val < 4 || Val > 7)
2116 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2117 /// values in ther permute mask.
2118 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2119 SDOperand &V2, SDOperand &Mask,
2120 SelectionDAG &DAG) {
2121 MVT::ValueType VT = Op.getValueType();
2122 MVT::ValueType MaskVT = Mask.getValueType();
2123 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2124 unsigned NumElems = Mask.getNumOperands();
2125 SmallVector<SDOperand, 8> MaskVec;
2127 for (unsigned i = 0; i != NumElems; ++i) {
2128 SDOperand Arg = Mask.getOperand(i);
2129 if (Arg.getOpcode() == ISD::UNDEF) {
2130 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2133 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2134 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2136 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2138 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2142 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2143 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2146 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2147 /// match movhlps. The lower half elements should come from upper half of
2148 /// V1 (and in order), and the upper half elements should come from the upper
2149 /// half of V2 (and in order).
2150 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2151 unsigned NumElems = Mask->getNumOperands();
2154 for (unsigned i = 0, e = 2; i != e; ++i)
2155 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2157 for (unsigned i = 2; i != 4; ++i)
2158 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2163 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2164 /// is promoted to a vector.
2165 static inline bool isScalarLoadToVector(SDNode *N) {
2166 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2167 N = N->getOperand(0).Val;
2168 return ISD::isNON_EXTLoad(N);
2173 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2174 /// match movlp{s|d}. The lower half elements should come from lower half of
2175 /// V1 (and in order), and the upper half elements should come from the upper
2176 /// half of V2 (and in order). And since V1 will become the source of the
2177 /// MOVLP, it must be either a vector load or a scalar load to vector.
2178 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2179 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2181 // Is V2 is a vector load, don't do this transformation. We will try to use
2182 // load folding shufps op.
2183 if (ISD::isNON_EXTLoad(V2))
2186 unsigned NumElems = Mask->getNumOperands();
2187 if (NumElems != 2 && NumElems != 4)
2189 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2190 if (!isUndefOrEqual(Mask->getOperand(i), i))
2192 for (unsigned i = NumElems/2; i != NumElems; ++i)
2193 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2198 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2200 static bool isSplatVector(SDNode *N) {
2201 if (N->getOpcode() != ISD::BUILD_VECTOR)
2204 SDOperand SplatValue = N->getOperand(0);
2205 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2206 if (N->getOperand(i) != SplatValue)
2211 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2213 static bool isUndefShuffle(SDNode *N) {
2214 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2217 SDOperand V1 = N->getOperand(0);
2218 SDOperand V2 = N->getOperand(1);
2219 SDOperand Mask = N->getOperand(2);
2220 unsigned NumElems = Mask.getNumOperands();
2221 for (unsigned i = 0; i != NumElems; ++i) {
2222 SDOperand Arg = Mask.getOperand(i);
2223 if (Arg.getOpcode() != ISD::UNDEF) {
2224 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2225 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2227 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2234 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2236 static inline bool isZeroNode(SDOperand Elt) {
2237 return ((isa<ConstantSDNode>(Elt) &&
2238 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2239 (isa<ConstantFPSDNode>(Elt) &&
2240 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2243 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2244 /// to an zero vector.
2245 static bool isZeroShuffle(SDNode *N) {
2246 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2249 SDOperand V1 = N->getOperand(0);
2250 SDOperand V2 = N->getOperand(1);
2251 SDOperand Mask = N->getOperand(2);
2252 unsigned NumElems = Mask.getNumOperands();
2253 for (unsigned i = 0; i != NumElems; ++i) {
2254 SDOperand Arg = Mask.getOperand(i);
2255 if (Arg.getOpcode() != ISD::UNDEF) {
2256 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2257 if (Idx < NumElems) {
2258 unsigned Opc = V1.Val->getOpcode();
2259 if (Opc == ISD::UNDEF)
2261 if (Opc != ISD::BUILD_VECTOR ||
2262 !isZeroNode(V1.Val->getOperand(Idx)))
2264 } else if (Idx >= NumElems) {
2265 unsigned Opc = V2.Val->getOpcode();
2266 if (Opc == ISD::UNDEF)
2268 if (Opc != ISD::BUILD_VECTOR ||
2269 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2277 /// getZeroVector - Returns a vector of specified type with all zero elements.
2279 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2280 assert(MVT::isVector(VT) && "Expected a vector type");
2281 unsigned NumElems = MVT::getVectorNumElements(VT);
2282 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2283 bool isFP = MVT::isFloatingPoint(EVT);
2284 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2285 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2286 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2289 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2290 /// that point to V2 points to its first element.
2291 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2292 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2294 bool Changed = false;
2295 SmallVector<SDOperand, 8> MaskVec;
2296 unsigned NumElems = Mask.getNumOperands();
2297 for (unsigned i = 0; i != NumElems; ++i) {
2298 SDOperand Arg = Mask.getOperand(i);
2299 if (Arg.getOpcode() != ISD::UNDEF) {
2300 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2301 if (Val > NumElems) {
2302 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2306 MaskVec.push_back(Arg);
2310 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2311 &MaskVec[0], MaskVec.size());
2315 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2316 /// operation of specified width.
2317 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2318 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2319 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2321 SmallVector<SDOperand, 8> MaskVec;
2322 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2323 for (unsigned i = 1; i != NumElems; ++i)
2324 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2325 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2328 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2329 /// of specified width.
2330 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2331 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2332 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2333 SmallVector<SDOperand, 8> MaskVec;
2334 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2335 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2336 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2338 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2341 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2342 /// of specified width.
2343 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2344 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2345 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2346 unsigned Half = NumElems/2;
2347 SmallVector<SDOperand, 8> MaskVec;
2348 for (unsigned i = 0; i != Half; ++i) {
2349 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2350 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2352 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2355 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2357 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2358 SDOperand V1 = Op.getOperand(0);
2359 SDOperand Mask = Op.getOperand(2);
2360 MVT::ValueType VT = Op.getValueType();
2361 unsigned NumElems = Mask.getNumOperands();
2362 Mask = getUnpacklMask(NumElems, DAG);
2363 while (NumElems != 4) {
2364 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2367 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2369 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2370 Mask = getZeroVector(MaskVT, DAG);
2371 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2372 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2373 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2376 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2377 /// vector of zero or undef vector.
2378 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2379 unsigned NumElems, unsigned Idx,
2380 bool isZero, SelectionDAG &DAG) {
2381 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2382 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2383 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2384 SDOperand Zero = DAG.getConstant(0, EVT);
2385 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2386 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2387 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2388 &MaskVec[0], MaskVec.size());
2389 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2392 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2394 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2395 unsigned NumNonZero, unsigned NumZero,
2396 SelectionDAG &DAG, TargetLowering &TLI) {
2402 for (unsigned i = 0; i < 16; ++i) {
2403 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2404 if (ThisIsNonZero && First) {
2406 V = getZeroVector(MVT::v8i16, DAG);
2408 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2413 SDOperand ThisElt(0, 0), LastElt(0, 0);
2414 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2415 if (LastIsNonZero) {
2416 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2418 if (ThisIsNonZero) {
2419 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2420 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2421 ThisElt, DAG.getConstant(8, MVT::i8));
2423 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2428 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2429 DAG.getConstant(i/2, TLI.getPointerTy()));
2433 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2436 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2438 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2439 unsigned NumNonZero, unsigned NumZero,
2440 SelectionDAG &DAG, TargetLowering &TLI) {
2446 for (unsigned i = 0; i < 8; ++i) {
2447 bool isNonZero = (NonZeros & (1 << i)) != 0;
2451 V = getZeroVector(MVT::v8i16, DAG);
2453 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2456 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2457 DAG.getConstant(i, TLI.getPointerTy()));
2465 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2466 // All zero's are handled with pxor.
2467 if (ISD::isBuildVectorAllZeros(Op.Val))
2470 // All one's are handled with pcmpeqd.
2471 if (ISD::isBuildVectorAllOnes(Op.Val))
2474 MVT::ValueType VT = Op.getValueType();
2475 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2476 unsigned EVTBits = MVT::getSizeInBits(EVT);
2478 unsigned NumElems = Op.getNumOperands();
2479 unsigned NumZero = 0;
2480 unsigned NumNonZero = 0;
2481 unsigned NonZeros = 0;
2482 std::set<SDOperand> Values;
2483 for (unsigned i = 0; i < NumElems; ++i) {
2484 SDOperand Elt = Op.getOperand(i);
2485 if (Elt.getOpcode() != ISD::UNDEF) {
2487 if (isZeroNode(Elt))
2490 NonZeros |= (1 << i);
2496 if (NumNonZero == 0) {
2498 // All undef vector. Return an UNDEF.
2499 return DAG.getNode(ISD::UNDEF, VT);
2501 // A mix of zero and undef. Return a zero vector.
2502 return getZeroVector(VT, DAG);
2505 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2506 if (Values.size() == 1)
2509 // Special case for single non-zero element.
2510 if (NumNonZero == 1) {
2511 unsigned Idx = CountTrailingZeros_32(NonZeros);
2512 SDOperand Item = Op.getOperand(Idx);
2513 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2515 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2516 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2519 if (EVTBits == 32) {
2520 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2521 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2523 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2524 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2525 SmallVector<SDOperand, 8> MaskVec;
2526 for (unsigned i = 0; i < NumElems; i++)
2527 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2528 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2529 &MaskVec[0], MaskVec.size());
2530 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2531 DAG.getNode(ISD::UNDEF, VT), Mask);
2535 // Let legalizer expand 2-wide build_vectors.
2539 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2540 if (EVTBits == 8 && NumElems == 16) {
2541 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2543 if (V.Val) return V;
2546 if (EVTBits == 16 && NumElems == 8) {
2547 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2549 if (V.Val) return V;
2552 // If element VT is == 32 bits, turn it into a number of shuffles.
2553 SmallVector<SDOperand, 8> V;
2555 if (NumElems == 4 && NumZero > 0) {
2556 for (unsigned i = 0; i < 4; ++i) {
2557 bool isZero = !(NonZeros & (1 << i));
2559 V[i] = getZeroVector(VT, DAG);
2561 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2564 for (unsigned i = 0; i < 2; ++i) {
2565 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2568 V[i] = V[i*2]; // Must be a zero vector.
2571 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2572 getMOVLMask(NumElems, DAG));
2575 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2576 getMOVLMask(NumElems, DAG));
2579 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2580 getUnpacklMask(NumElems, DAG));
2585 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2586 // clears the upper bits.
2587 // FIXME: we can do the same for v4f32 case when we know both parts of
2588 // the lower half come from scalar_to_vector (loadf32). We should do
2589 // that in post legalizer dag combiner with target specific hooks.
2590 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2592 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2593 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2594 SmallVector<SDOperand, 8> MaskVec;
2595 bool Reverse = (NonZeros & 0x3) == 2;
2596 for (unsigned i = 0; i < 2; ++i)
2598 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2600 MaskVec.push_back(DAG.getConstant(i, EVT));
2601 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2602 for (unsigned i = 0; i < 2; ++i)
2604 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2606 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2607 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2608 &MaskVec[0], MaskVec.size());
2609 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2612 if (Values.size() > 2) {
2613 // Expand into a number of unpckl*.
2615 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2616 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2617 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2618 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2619 for (unsigned i = 0; i < NumElems; ++i)
2620 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2622 while (NumElems != 0) {
2623 for (unsigned i = 0; i < NumElems; ++i)
2624 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2635 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2636 SDOperand V1 = Op.getOperand(0);
2637 SDOperand V2 = Op.getOperand(1);
2638 SDOperand PermMask = Op.getOperand(2);
2639 MVT::ValueType VT = Op.getValueType();
2640 unsigned NumElems = PermMask.getNumOperands();
2641 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2642 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2643 bool V1IsSplat = false;
2644 bool V2IsSplat = false;
2646 if (isUndefShuffle(Op.Val))
2647 return DAG.getNode(ISD::UNDEF, VT);
2649 if (isZeroShuffle(Op.Val))
2650 return getZeroVector(VT, DAG);
2652 if (isIdentityMask(PermMask.Val))
2654 else if (isIdentityMask(PermMask.Val, true))
2657 if (isSplatMask(PermMask.Val)) {
2658 if (NumElems <= 4) return Op;
2659 // Promote it to a v4i32 splat.
2660 return PromoteSplat(Op, DAG);
2663 if (X86::isMOVLMask(PermMask.Val))
2664 return (V1IsUndef) ? V2 : Op;
2666 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2667 X86::isMOVSLDUPMask(PermMask.Val) ||
2668 X86::isMOVHLPSMask(PermMask.Val) ||
2669 X86::isMOVHPMask(PermMask.Val) ||
2670 X86::isMOVLPMask(PermMask.Val))
2673 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2674 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
2675 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2677 bool Commuted = false;
2678 V1IsSplat = isSplatVector(V1.Val);
2679 V2IsSplat = isSplatVector(V2.Val);
2680 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
2681 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2682 std::swap(V1IsSplat, V2IsSplat);
2683 std::swap(V1IsUndef, V2IsUndef);
2687 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
2688 if (V2IsUndef) return V1;
2689 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2691 // V2 is a splat, so the mask may be malformed. That is, it may point
2692 // to any V2 element. The instruction selectior won't like this. Get
2693 // a corrected mask and commute to form a proper MOVS{S|D}.
2694 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2695 if (NewMask.Val != PermMask.Val)
2696 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2701 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2702 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2703 X86::isUNPCKLMask(PermMask.Val) ||
2704 X86::isUNPCKHMask(PermMask.Val))
2708 // Normalize mask so all entries that point to V2 points to its first
2709 // element then try to match unpck{h|l} again. If match, return a
2710 // new vector_shuffle with the corrected mask.
2711 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2712 if (NewMask.Val != PermMask.Val) {
2713 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2714 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2715 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2716 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2717 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2718 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2723 // Normalize the node to match x86 shuffle ops if needed
2724 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
2725 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2728 // Commute is back and try unpck* again.
2729 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2730 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2731 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2732 X86::isUNPCKLMask(PermMask.Val) ||
2733 X86::isUNPCKHMask(PermMask.Val))
2737 // If VT is integer, try PSHUF* first, then SHUFP*.
2738 if (MVT::isInteger(VT)) {
2739 if (X86::isPSHUFDMask(PermMask.Val) ||
2740 X86::isPSHUFHWMask(PermMask.Val) ||
2741 X86::isPSHUFLWMask(PermMask.Val)) {
2742 if (V2.getOpcode() != ISD::UNDEF)
2743 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2744 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2748 if (X86::isSHUFPMask(PermMask.Val) &&
2749 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
2752 // Handle v8i16 shuffle high / low shuffle node pair.
2753 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2754 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2755 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2756 SmallVector<SDOperand, 8> MaskVec;
2757 for (unsigned i = 0; i != 4; ++i)
2758 MaskVec.push_back(PermMask.getOperand(i));
2759 for (unsigned i = 4; i != 8; ++i)
2760 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2761 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2762 &MaskVec[0], MaskVec.size());
2763 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2765 for (unsigned i = 0; i != 4; ++i)
2766 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2767 for (unsigned i = 4; i != 8; ++i)
2768 MaskVec.push_back(PermMask.getOperand(i));
2769 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
2770 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2773 // Floating point cases in the other order.
2774 if (X86::isSHUFPMask(PermMask.Val))
2776 if (X86::isPSHUFDMask(PermMask.Val) ||
2777 X86::isPSHUFHWMask(PermMask.Val) ||
2778 X86::isPSHUFLWMask(PermMask.Val)) {
2779 if (V2.getOpcode() != ISD::UNDEF)
2780 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2781 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2786 if (NumElems == 4 &&
2787 // Don't do this for MMX.
2788 MVT::getSizeInBits(VT) != 64) {
2789 MVT::ValueType MaskVT = PermMask.getValueType();
2790 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2791 SmallVector<std::pair<int, int>, 8> Locs;
2792 Locs.reserve(NumElems);
2793 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2794 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2797 // If no more than two elements come from either vector. This can be
2798 // implemented with two shuffles. First shuffle gather the elements.
2799 // The second shuffle, which takes the first shuffle as both of its
2800 // vector operands, put the elements into the right order.
2801 for (unsigned i = 0; i != NumElems; ++i) {
2802 SDOperand Elt = PermMask.getOperand(i);
2803 if (Elt.getOpcode() == ISD::UNDEF) {
2804 Locs[i] = std::make_pair(-1, -1);
2806 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2807 if (Val < NumElems) {
2808 Locs[i] = std::make_pair(0, NumLo);
2812 Locs[i] = std::make_pair(1, NumHi);
2813 if (2+NumHi < NumElems)
2814 Mask1[2+NumHi] = Elt;
2819 if (NumLo <= 2 && NumHi <= 2) {
2820 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2821 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2822 &Mask1[0], Mask1.size()));
2823 for (unsigned i = 0; i != NumElems; ++i) {
2824 if (Locs[i].first == -1)
2827 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
2828 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
2829 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
2833 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
2834 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2835 &Mask2[0], Mask2.size()));
2838 // Break it into (shuffle shuffle_hi, shuffle_lo).
2840 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2841 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2842 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
2843 unsigned MaskIdx = 0;
2845 unsigned HiIdx = NumElems/2;
2846 for (unsigned i = 0; i != NumElems; ++i) {
2847 if (i == NumElems/2) {
2853 SDOperand Elt = PermMask.getOperand(i);
2854 if (Elt.getOpcode() == ISD::UNDEF) {
2855 Locs[i] = std::make_pair(-1, -1);
2856 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
2857 Locs[i] = std::make_pair(MaskIdx, LoIdx);
2858 (*MaskPtr)[LoIdx] = Elt;
2861 Locs[i] = std::make_pair(MaskIdx, HiIdx);
2862 (*MaskPtr)[HiIdx] = Elt;
2867 SDOperand LoShuffle =
2868 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2869 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2870 &LoMask[0], LoMask.size()));
2871 SDOperand HiShuffle =
2872 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2873 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2874 &HiMask[0], HiMask.size()));
2875 SmallVector<SDOperand, 8> MaskOps;
2876 for (unsigned i = 0; i != NumElems; ++i) {
2877 if (Locs[i].first == -1) {
2878 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
2880 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
2881 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
2884 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
2885 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2886 &MaskOps[0], MaskOps.size()));
2893 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2894 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2897 MVT::ValueType VT = Op.getValueType();
2898 // TODO: handle v16i8.
2899 if (MVT::getSizeInBits(VT) == 16) {
2900 // Transform it so it match pextrw which produces a 32-bit result.
2901 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
2902 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
2903 Op.getOperand(0), Op.getOperand(1));
2904 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
2905 DAG.getValueType(VT));
2906 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
2907 } else if (MVT::getSizeInBits(VT) == 32) {
2908 SDOperand Vec = Op.getOperand(0);
2909 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2912 // SHUFPS the element to the lowest double word, then movss.
2913 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2914 SmallVector<SDOperand, 8> IdxVec;
2915 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
2916 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
2917 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
2918 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
2919 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2920 &IdxVec[0], IdxVec.size());
2921 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2922 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2923 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2924 DAG.getConstant(0, getPointerTy()));
2925 } else if (MVT::getSizeInBits(VT) == 64) {
2926 SDOperand Vec = Op.getOperand(0);
2927 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2931 // UNPCKHPD the element to the lowest double word, then movsd.
2932 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
2933 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
2934 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2935 SmallVector<SDOperand, 8> IdxVec;
2936 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
2937 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
2938 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2939 &IdxVec[0], IdxVec.size());
2940 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2941 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2942 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2943 DAG.getConstant(0, getPointerTy()));
2950 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2951 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
2952 // as its second argument.
2953 MVT::ValueType VT = Op.getValueType();
2954 MVT::ValueType BaseVT = MVT::getVectorElementType(VT);
2955 SDOperand N0 = Op.getOperand(0);
2956 SDOperand N1 = Op.getOperand(1);
2957 SDOperand N2 = Op.getOperand(2);
2958 if (MVT::getSizeInBits(BaseVT) == 16) {
2959 if (N1.getValueType() != MVT::i32)
2960 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
2961 if (N2.getValueType() != MVT::i32)
2962 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy());
2963 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
2964 } else if (MVT::getSizeInBits(BaseVT) == 32) {
2965 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
2968 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
2969 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2970 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2971 SmallVector<SDOperand, 8> MaskVec;
2972 MaskVec.push_back(DAG.getConstant(4, BaseVT));
2973 for (unsigned i = 1; i <= 3; ++i)
2974 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2975 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
2976 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2977 &MaskVec[0], MaskVec.size()));
2979 // Use two pinsrw instructions to insert a 32 bit value.
2981 if (MVT::isFloatingPoint(N1.getValueType())) {
2982 if (ISD::isNON_EXTLoad(N1.Val)) {
2983 // Just load directly from f32mem to GR32.
2984 LoadSDNode *LD = cast<LoadSDNode>(N1);
2985 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
2986 LD->getSrcValue(), LD->getSrcValueOffset());
2988 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
2989 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
2990 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
2991 DAG.getConstant(0, getPointerTy()));
2994 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
2995 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2996 DAG.getConstant(Idx, getPointerTy()));
2997 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
2998 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2999 DAG.getConstant(Idx+1, getPointerTy()));
3000 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3008 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3009 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3010 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3013 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3014 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3015 // one of the above mentioned nodes. It has to be wrapped because otherwise
3016 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3017 // be used to form addressing mode. These wrapped nodes will be selected
3020 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3021 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3022 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3024 CP->getAlignment());
3025 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3026 // With PIC, the address is actually $g + Offset.
3027 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3028 !Subtarget->isPICStyleRIPRel()) {
3029 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3030 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3038 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3039 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3040 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3041 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3042 // With PIC, the address is actually $g + Offset.
3043 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3044 !Subtarget->isPICStyleRIPRel()) {
3045 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3046 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3050 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3051 // load the value at address GV, not the value of GV itself. This means that
3052 // the GlobalAddress must be in the base or index register of the address, not
3053 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3054 // The same applies for external symbols during PIC codegen
3055 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3056 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3061 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3063 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3064 const MVT::ValueType PtrVT) {
3066 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3067 DAG.getNode(X86ISD::GlobalBaseReg,
3069 InFlag = Chain.getValue(1);
3071 // emit leal symbol@TLSGD(,%ebx,1), %eax
3072 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3073 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3074 GA->getValueType(0),
3076 SDOperand Ops[] = { Chain, TGA, InFlag };
3077 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3078 InFlag = Result.getValue(2);
3079 Chain = Result.getValue(1);
3081 // call ___tls_get_addr. This function receives its argument in
3082 // the register EAX.
3083 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3084 InFlag = Chain.getValue(1);
3086 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3087 SDOperand Ops1[] = { Chain,
3088 DAG.getTargetExternalSymbol("___tls_get_addr",
3090 DAG.getRegister(X86::EAX, PtrVT),
3091 DAG.getRegister(X86::EBX, PtrVT),
3093 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3094 InFlag = Chain.getValue(1);
3096 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3099 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3100 // "local exec" model.
3102 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3103 const MVT::ValueType PtrVT) {
3104 // Get the Thread Pointer
3105 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3106 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3108 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3109 GA->getValueType(0),
3111 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3113 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3114 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3116 // The address of the thread local variable is the add of the thread
3117 // pointer with the offset of the variable.
3118 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3122 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3123 // TODO: implement the "local dynamic" model
3124 // TODO: implement the "initial exec"model for pic executables
3125 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3126 "TLS not implemented for non-ELF and 64-bit targets");
3127 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3128 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3129 // otherwise use the "Local Exec"TLS Model
3130 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3131 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3133 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3137 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3138 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3139 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3140 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3141 // With PIC, the address is actually $g + Offset.
3142 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3143 !Subtarget->isPICStyleRIPRel()) {
3144 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3145 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3152 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3153 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3154 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3155 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3156 // With PIC, the address is actually $g + Offset.
3157 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3158 !Subtarget->isPICStyleRIPRel()) {
3159 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3160 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3167 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3168 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3169 "Not an i64 shift!");
3170 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3171 SDOperand ShOpLo = Op.getOperand(0);
3172 SDOperand ShOpHi = Op.getOperand(1);
3173 SDOperand ShAmt = Op.getOperand(2);
3174 SDOperand Tmp1 = isSRA ?
3175 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3176 DAG.getConstant(0, MVT::i32);
3178 SDOperand Tmp2, Tmp3;
3179 if (Op.getOpcode() == ISD::SHL_PARTS) {
3180 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3181 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3183 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3184 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3187 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3188 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3189 DAG.getConstant(32, MVT::i8));
3190 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3191 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3194 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3196 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3197 SmallVector<SDOperand, 4> Ops;
3198 if (Op.getOpcode() == ISD::SHL_PARTS) {
3199 Ops.push_back(Tmp2);
3200 Ops.push_back(Tmp3);
3202 Ops.push_back(InFlag);
3203 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3204 InFlag = Hi.getValue(1);
3207 Ops.push_back(Tmp3);
3208 Ops.push_back(Tmp1);
3210 Ops.push_back(InFlag);
3211 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3213 Ops.push_back(Tmp2);
3214 Ops.push_back(Tmp3);
3216 Ops.push_back(InFlag);
3217 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3218 InFlag = Lo.getValue(1);
3221 Ops.push_back(Tmp3);
3222 Ops.push_back(Tmp1);
3224 Ops.push_back(InFlag);
3225 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3228 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3232 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3235 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3236 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3237 Op.getOperand(0).getValueType() >= MVT::i16 &&
3238 "Unknown SINT_TO_FP to lower!");
3241 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3242 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3243 MachineFunction &MF = DAG.getMachineFunction();
3244 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3245 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3246 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3247 StackSlot, NULL, 0);
3252 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3254 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
3255 SmallVector<SDOperand, 8> Ops;
3256 Ops.push_back(Chain);
3257 Ops.push_back(StackSlot);
3258 Ops.push_back(DAG.getValueType(SrcVT));
3259 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3260 Tys, &Ops[0], Ops.size());
3263 Chain = Result.getValue(1);
3264 SDOperand InFlag = Result.getValue(2);
3266 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3267 // shouldn't be necessary except that RFP cannot be live across
3268 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3269 MachineFunction &MF = DAG.getMachineFunction();
3270 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3271 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3272 Tys = DAG.getVTList(MVT::Other);
3273 SmallVector<SDOperand, 8> Ops;
3274 Ops.push_back(Chain);
3275 Ops.push_back(Result);
3276 Ops.push_back(StackSlot);
3277 Ops.push_back(DAG.getValueType(Op.getValueType()));
3278 Ops.push_back(InFlag);
3279 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3280 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3286 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3287 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3288 "Unknown FP_TO_SINT to lower!");
3289 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3291 MachineFunction &MF = DAG.getMachineFunction();
3292 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3293 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3294 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3297 switch (Op.getValueType()) {
3298 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3299 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3300 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3301 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3304 SDOperand Chain = DAG.getEntryNode();
3305 SDOperand Value = Op.getOperand(0);
3307 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3308 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3309 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
3311 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3313 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3314 Chain = Value.getValue(1);
3315 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3316 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3319 // Build the FP_TO_INT*_IN_MEM
3320 SDOperand Ops[] = { Chain, Value, StackSlot };
3321 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3324 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3327 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3328 MVT::ValueType VT = Op.getValueType();
3329 const Type *OpNTy = MVT::getTypeForValueType(VT);
3330 std::vector<Constant*> CV;
3331 if (VT == MVT::f64) {
3332 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3333 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3335 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3336 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3337 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3338 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3340 Constant *CS = ConstantStruct::get(CV);
3341 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3342 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3343 SmallVector<SDOperand, 3> Ops;
3344 Ops.push_back(DAG.getEntryNode());
3345 Ops.push_back(CPIdx);
3346 Ops.push_back(DAG.getSrcValue(NULL));
3347 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3348 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3351 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3352 MVT::ValueType VT = Op.getValueType();
3353 const Type *OpNTy = MVT::getTypeForValueType(VT);
3354 std::vector<Constant*> CV;
3355 if (VT == MVT::f64) {
3356 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3357 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3359 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3360 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3361 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3362 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3364 Constant *CS = ConstantStruct::get(CV);
3365 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3366 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3367 SmallVector<SDOperand, 3> Ops;
3368 Ops.push_back(DAG.getEntryNode());
3369 Ops.push_back(CPIdx);
3370 Ops.push_back(DAG.getSrcValue(NULL));
3371 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3372 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3375 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3376 SDOperand Op0 = Op.getOperand(0);
3377 SDOperand Op1 = Op.getOperand(1);
3378 MVT::ValueType VT = Op.getValueType();
3379 MVT::ValueType SrcVT = Op1.getValueType();
3380 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3382 // If second operand is smaller, extend it first.
3383 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3384 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3388 // First get the sign bit of second operand.
3389 std::vector<Constant*> CV;
3390 if (SrcVT == MVT::f64) {
3391 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63)));
3392 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3394 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31)));
3395 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3396 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3397 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3399 Constant *CS = ConstantStruct::get(CV);
3400 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3401 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
3402 SmallVector<SDOperand, 3> Ops;
3403 Ops.push_back(DAG.getEntryNode());
3404 Ops.push_back(CPIdx);
3405 Ops.push_back(DAG.getSrcValue(NULL));
3406 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3407 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3409 // Shift sign bit right or left if the two operands have different types.
3410 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3411 // Op0 is MVT::f32, Op1 is MVT::f64.
3412 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3413 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3414 DAG.getConstant(32, MVT::i32));
3415 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3416 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3417 DAG.getConstant(0, getPointerTy()));
3420 // Clear first operand sign bit.
3422 if (VT == MVT::f64) {
3423 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63))));
3424 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3426 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31))));
3427 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3428 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3429 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3431 CS = ConstantStruct::get(CV);
3432 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3433 Tys = DAG.getVTList(VT, MVT::Other);
3435 Ops.push_back(DAG.getEntryNode());
3436 Ops.push_back(CPIdx);
3437 Ops.push_back(DAG.getSrcValue(NULL));
3438 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3439 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3441 // Or the value with the sign bit.
3442 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3445 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3447 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3449 SDOperand Op0 = Op.getOperand(0);
3450 SDOperand Op1 = Op.getOperand(1);
3451 SDOperand CC = Op.getOperand(2);
3452 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3453 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3454 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3455 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3458 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3460 SDOperand Ops1[] = { Chain, Op0, Op1 };
3461 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3462 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3463 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3466 assert(isFP && "Illegal integer SetCC!");
3468 SDOperand COps[] = { Chain, Op0, Op1 };
3469 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3471 switch (SetCCOpcode) {
3472 default: assert(false && "Illegal floating point SetCC!");
3473 case ISD::SETOEQ: { // !PF & ZF
3474 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3475 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3476 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3478 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3479 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3481 case ISD::SETUNE: { // PF | !ZF
3482 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3483 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3484 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3486 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3487 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3492 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3493 bool addTest = true;
3494 SDOperand Chain = DAG.getEntryNode();
3495 SDOperand Cond = Op.getOperand(0);
3497 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3499 if (Cond.getOpcode() == ISD::SETCC)
3500 Cond = LowerSETCC(Cond, DAG, Chain);
3502 if (Cond.getOpcode() == X86ISD::SETCC) {
3503 CC = Cond.getOperand(0);
3505 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3506 // (since flag operand cannot be shared). Use it as the condition setting
3507 // operand in place of the X86ISD::SETCC.
3508 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3509 // to use a test instead of duplicating the X86ISD::CMP (for register
3510 // pressure reason)?
3511 SDOperand Cmp = Cond.getOperand(1);
3512 unsigned Opc = Cmp.getOpcode();
3513 bool IllegalFPCMov = !X86ScalarSSE &&
3514 MVT::isFloatingPoint(Op.getValueType()) &&
3515 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3516 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3518 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3519 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3525 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3526 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3527 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3530 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3531 SmallVector<SDOperand, 4> Ops;
3532 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3533 // condition is true.
3534 Ops.push_back(Op.getOperand(2));
3535 Ops.push_back(Op.getOperand(1));
3537 Ops.push_back(Cond.getValue(1));
3538 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3541 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3542 bool addTest = true;
3543 SDOperand Chain = Op.getOperand(0);
3544 SDOperand Cond = Op.getOperand(1);
3545 SDOperand Dest = Op.getOperand(2);
3547 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3549 if (Cond.getOpcode() == ISD::SETCC)
3550 Cond = LowerSETCC(Cond, DAG, Chain);
3552 if (Cond.getOpcode() == X86ISD::SETCC) {
3553 CC = Cond.getOperand(0);
3555 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3556 // (since flag operand cannot be shared). Use it as the condition setting
3557 // operand in place of the X86ISD::SETCC.
3558 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3559 // to use a test instead of duplicating the X86ISD::CMP (for register
3560 // pressure reason)?
3561 SDOperand Cmp = Cond.getOperand(1);
3562 unsigned Opc = Cmp.getOpcode();
3563 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3564 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3565 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3571 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3572 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3573 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3575 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3576 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3579 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3580 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3582 if (Subtarget->is64Bit())
3583 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3585 switch (CallingConv) {
3587 assert(0 && "Unsupported calling convention");
3588 case CallingConv::Fast:
3589 // TODO: Implement fastcc
3591 case CallingConv::C:
3592 case CallingConv::X86_StdCall:
3593 return LowerCCCCallTo(Op, DAG, CallingConv);
3594 case CallingConv::X86_FastCall:
3595 return LowerFastCCCallTo(Op, DAG, CallingConv);
3600 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3601 // Calls to _alloca is needed to probe the stack when allocating more than 4k
3602 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3603 // that the guard pages used by the OS virtual memory manager are allocated in
3604 // correct sequence.
3606 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
3607 SelectionDAG &DAG) {
3608 assert(Subtarget->isTargetCygMing() &&
3609 "This should be used only on Cygwin/Mingw targets");
3612 SDOperand Chain = Op.getOperand(0);
3613 SDOperand Size = Op.getOperand(1);
3614 // FIXME: Ensure alignment here
3618 MVT::ValueType IntPtr = getPointerTy();
3619 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
3621 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
3622 Flag = Chain.getValue(1);
3624 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3625 SDOperand Ops[] = { Chain,
3626 DAG.getTargetExternalSymbol("_alloca", IntPtr),
3627 DAG.getRegister(X86::EAX, IntPtr),
3629 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
3630 Flag = Chain.getValue(1);
3632 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
3634 std::vector<MVT::ValueType> Tys;
3635 Tys.push_back(SPTy);
3636 Tys.push_back(MVT::Other);
3637 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
3638 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
3642 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3643 MachineFunction &MF = DAG.getMachineFunction();
3644 const Function* Fn = MF.getFunction();
3645 if (Fn->hasExternalLinkage() &&
3646 Subtarget->isTargetCygMing() &&
3647 Fn->getName() == "main")
3648 MF.getInfo<X86MachineFunctionInfo>()->setForceFramePointer(true);
3650 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3651 if (Subtarget->is64Bit())
3652 return LowerX86_64CCCArguments(Op, DAG);
3656 assert(0 && "Unsupported calling convention");
3657 case CallingConv::Fast:
3658 // TODO: implement fastcc.
3661 case CallingConv::C:
3662 return LowerCCCArguments(Op, DAG);
3663 case CallingConv::X86_StdCall:
3664 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(StdCall);
3665 return LowerCCCArguments(Op, DAG, true);
3666 case CallingConv::X86_FastCall:
3667 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(FastCall);
3668 return LowerFastCCArguments(Op, DAG);
3672 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3673 SDOperand InFlag(0, 0);
3674 SDOperand Chain = Op.getOperand(0);
3676 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3677 if (Align == 0) Align = 1;
3679 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3680 // If not DWORD aligned, call memset if size is less than the threshold.
3681 // It knows how to align to the right boundary first.
3682 if ((Align & 3) != 0 ||
3683 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3684 MVT::ValueType IntPtr = getPointerTy();
3685 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3686 TargetLowering::ArgListTy Args;
3687 TargetLowering::ArgListEntry Entry;
3688 Entry.Node = Op.getOperand(1);
3689 Entry.Ty = IntPtrTy;
3690 Args.push_back(Entry);
3691 // Extend the unsigned i8 argument to be an int value for the call.
3692 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3693 Entry.Ty = IntPtrTy;
3694 Args.push_back(Entry);
3695 Entry.Node = Op.getOperand(3);
3696 Args.push_back(Entry);
3697 std::pair<SDOperand,SDOperand> CallResult =
3698 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3699 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3700 return CallResult.second;
3705 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3706 unsigned BytesLeft = 0;
3707 bool TwoRepStos = false;
3710 uint64_t Val = ValC->getValue() & 255;
3712 // If the value is a constant, then we can potentially use larger sets.
3713 switch (Align & 3) {
3714 case 2: // WORD aligned
3717 Val = (Val << 8) | Val;
3719 case 0: // DWORD aligned
3722 Val = (Val << 8) | Val;
3723 Val = (Val << 16) | Val;
3724 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3727 Val = (Val << 32) | Val;
3730 default: // Byte aligned
3733 Count = Op.getOperand(3);
3737 if (AVT > MVT::i8) {
3739 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3740 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3741 BytesLeft = I->getValue() % UBytes;
3743 assert(AVT >= MVT::i32 &&
3744 "Do not use rep;stos if not at least DWORD aligned");
3745 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3746 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3751 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3753 InFlag = Chain.getValue(1);
3756 Count = Op.getOperand(3);
3757 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
3758 InFlag = Chain.getValue(1);
3761 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3763 InFlag = Chain.getValue(1);
3764 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3765 Op.getOperand(1), InFlag);
3766 InFlag = Chain.getValue(1);
3768 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3769 SmallVector<SDOperand, 8> Ops;
3770 Ops.push_back(Chain);
3771 Ops.push_back(DAG.getValueType(AVT));
3772 Ops.push_back(InFlag);
3773 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3776 InFlag = Chain.getValue(1);
3777 Count = Op.getOperand(3);
3778 MVT::ValueType CVT = Count.getValueType();
3779 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3780 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3781 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3783 InFlag = Chain.getValue(1);
3784 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3786 Ops.push_back(Chain);
3787 Ops.push_back(DAG.getValueType(MVT::i8));
3788 Ops.push_back(InFlag);
3789 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3790 } else if (BytesLeft) {
3791 // Issue stores for the last 1 - 7 bytes.
3793 unsigned Val = ValC->getValue() & 255;
3794 unsigned Offset = I->getValue() - BytesLeft;
3795 SDOperand DstAddr = Op.getOperand(1);
3796 MVT::ValueType AddrVT = DstAddr.getValueType();
3797 if (BytesLeft >= 4) {
3798 Val = (Val << 8) | Val;
3799 Val = (Val << 16) | Val;
3800 Value = DAG.getConstant(Val, MVT::i32);
3801 Chain = DAG.getStore(Chain, Value,
3802 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3803 DAG.getConstant(Offset, AddrVT)),
3808 if (BytesLeft >= 2) {
3809 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
3810 Chain = DAG.getStore(Chain, Value,
3811 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3812 DAG.getConstant(Offset, AddrVT)),
3817 if (BytesLeft == 1) {
3818 Value = DAG.getConstant(Val, MVT::i8);
3819 Chain = DAG.getStore(Chain, Value,
3820 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3821 DAG.getConstant(Offset, AddrVT)),
3829 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
3830 SDOperand Chain = Op.getOperand(0);
3832 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3833 if (Align == 0) Align = 1;
3835 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3836 // If not DWORD aligned, call memcpy if size is less than the threshold.
3837 // It knows how to align to the right boundary first.
3838 if ((Align & 3) != 0 ||
3839 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3840 MVT::ValueType IntPtr = getPointerTy();
3841 TargetLowering::ArgListTy Args;
3842 TargetLowering::ArgListEntry Entry;
3843 Entry.Ty = getTargetData()->getIntPtrType();
3844 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
3845 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
3846 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
3847 std::pair<SDOperand,SDOperand> CallResult =
3848 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3849 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
3850 return CallResult.second;
3855 unsigned BytesLeft = 0;
3856 bool TwoRepMovs = false;
3857 switch (Align & 3) {
3858 case 2: // WORD aligned
3861 case 0: // DWORD aligned
3863 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
3866 default: // Byte aligned
3868 Count = Op.getOperand(3);
3872 if (AVT > MVT::i8) {
3874 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3875 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3876 BytesLeft = I->getValue() % UBytes;
3878 assert(AVT >= MVT::i32 &&
3879 "Do not use rep;movs if not at least DWORD aligned");
3880 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3881 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3886 SDOperand InFlag(0, 0);
3887 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3889 InFlag = Chain.getValue(1);
3890 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3891 Op.getOperand(1), InFlag);
3892 InFlag = Chain.getValue(1);
3893 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
3894 Op.getOperand(2), InFlag);
3895 InFlag = Chain.getValue(1);
3897 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3898 SmallVector<SDOperand, 8> Ops;
3899 Ops.push_back(Chain);
3900 Ops.push_back(DAG.getValueType(AVT));
3901 Ops.push_back(InFlag);
3902 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3905 InFlag = Chain.getValue(1);
3906 Count = Op.getOperand(3);
3907 MVT::ValueType CVT = Count.getValueType();
3908 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3909 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3910 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3912 InFlag = Chain.getValue(1);
3913 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3915 Ops.push_back(Chain);
3916 Ops.push_back(DAG.getValueType(MVT::i8));
3917 Ops.push_back(InFlag);
3918 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3919 } else if (BytesLeft) {
3920 // Issue loads and stores for the last 1 - 7 bytes.
3921 unsigned Offset = I->getValue() - BytesLeft;
3922 SDOperand DstAddr = Op.getOperand(1);
3923 MVT::ValueType DstVT = DstAddr.getValueType();
3924 SDOperand SrcAddr = Op.getOperand(2);
3925 MVT::ValueType SrcVT = SrcAddr.getValueType();
3927 if (BytesLeft >= 4) {
3928 Value = DAG.getLoad(MVT::i32, Chain,
3929 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3930 DAG.getConstant(Offset, SrcVT)),
3932 Chain = Value.getValue(1);
3933 Chain = DAG.getStore(Chain, Value,
3934 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3935 DAG.getConstant(Offset, DstVT)),
3940 if (BytesLeft >= 2) {
3941 Value = DAG.getLoad(MVT::i16, Chain,
3942 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3943 DAG.getConstant(Offset, SrcVT)),
3945 Chain = Value.getValue(1);
3946 Chain = DAG.getStore(Chain, Value,
3947 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3948 DAG.getConstant(Offset, DstVT)),
3954 if (BytesLeft == 1) {
3955 Value = DAG.getLoad(MVT::i8, Chain,
3956 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3957 DAG.getConstant(Offset, SrcVT)),
3959 Chain = Value.getValue(1);
3960 Chain = DAG.getStore(Chain, Value,
3961 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3962 DAG.getConstant(Offset, DstVT)),
3971 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
3972 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3973 SDOperand TheOp = Op.getOperand(0);
3974 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
3975 if (Subtarget->is64Bit()) {
3976 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
3977 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
3978 MVT::i64, Copy1.getValue(2));
3979 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
3980 DAG.getConstant(32, MVT::i8));
3982 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
3985 Tys = DAG.getVTList(MVT::i64, MVT::Other);
3986 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
3989 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
3990 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
3991 MVT::i32, Copy1.getValue(2));
3992 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
3993 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
3994 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
3997 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
3998 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4000 if (!Subtarget->is64Bit()) {
4001 // vastart just stores the address of the VarArgsFrameIndex slot into the
4002 // memory location argument.
4003 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4004 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4009 // gp_offset (0 - 6 * 8)
4010 // fp_offset (48 - 48 + 8 * 16)
4011 // overflow_arg_area (point to parameters coming in memory).
4013 SmallVector<SDOperand, 8> MemOps;
4014 SDOperand FIN = Op.getOperand(1);
4016 SDOperand Store = DAG.getStore(Op.getOperand(0),
4017 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4018 FIN, SV->getValue(), SV->getOffset());
4019 MemOps.push_back(Store);
4022 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4023 DAG.getConstant(4, getPointerTy()));
4024 Store = DAG.getStore(Op.getOperand(0),
4025 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4026 FIN, SV->getValue(), SV->getOffset());
4027 MemOps.push_back(Store);
4029 // Store ptr to overflow_arg_area
4030 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4031 DAG.getConstant(4, getPointerTy()));
4032 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4033 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4035 MemOps.push_back(Store);
4037 // Store ptr to reg_save_area.
4038 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4039 DAG.getConstant(8, getPointerTy()));
4040 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4041 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4043 MemOps.push_back(Store);
4044 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4047 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4048 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4049 SDOperand Chain = Op.getOperand(0);
4050 SDOperand DstPtr = Op.getOperand(1);
4051 SDOperand SrcPtr = Op.getOperand(2);
4052 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4053 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4055 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4056 SrcSV->getValue(), SrcSV->getOffset());
4057 Chain = SrcPtr.getValue(1);
4058 for (unsigned i = 0; i < 3; ++i) {
4059 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4060 SrcSV->getValue(), SrcSV->getOffset());
4061 Chain = Val.getValue(1);
4062 Chain = DAG.getStore(Chain, Val, DstPtr,
4063 DstSV->getValue(), DstSV->getOffset());
4066 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4067 DAG.getConstant(8, getPointerTy()));
4068 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4069 DAG.getConstant(8, getPointerTy()));
4075 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4076 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4078 default: return SDOperand(); // Don't custom lower most intrinsics.
4079 // Comparison intrinsics.
4080 case Intrinsic::x86_sse_comieq_ss:
4081 case Intrinsic::x86_sse_comilt_ss:
4082 case Intrinsic::x86_sse_comile_ss:
4083 case Intrinsic::x86_sse_comigt_ss:
4084 case Intrinsic::x86_sse_comige_ss:
4085 case Intrinsic::x86_sse_comineq_ss:
4086 case Intrinsic::x86_sse_ucomieq_ss:
4087 case Intrinsic::x86_sse_ucomilt_ss:
4088 case Intrinsic::x86_sse_ucomile_ss:
4089 case Intrinsic::x86_sse_ucomigt_ss:
4090 case Intrinsic::x86_sse_ucomige_ss:
4091 case Intrinsic::x86_sse_ucomineq_ss:
4092 case Intrinsic::x86_sse2_comieq_sd:
4093 case Intrinsic::x86_sse2_comilt_sd:
4094 case Intrinsic::x86_sse2_comile_sd:
4095 case Intrinsic::x86_sse2_comigt_sd:
4096 case Intrinsic::x86_sse2_comige_sd:
4097 case Intrinsic::x86_sse2_comineq_sd:
4098 case Intrinsic::x86_sse2_ucomieq_sd:
4099 case Intrinsic::x86_sse2_ucomilt_sd:
4100 case Intrinsic::x86_sse2_ucomile_sd:
4101 case Intrinsic::x86_sse2_ucomigt_sd:
4102 case Intrinsic::x86_sse2_ucomige_sd:
4103 case Intrinsic::x86_sse2_ucomineq_sd: {
4105 ISD::CondCode CC = ISD::SETCC_INVALID;
4108 case Intrinsic::x86_sse_comieq_ss:
4109 case Intrinsic::x86_sse2_comieq_sd:
4113 case Intrinsic::x86_sse_comilt_ss:
4114 case Intrinsic::x86_sse2_comilt_sd:
4118 case Intrinsic::x86_sse_comile_ss:
4119 case Intrinsic::x86_sse2_comile_sd:
4123 case Intrinsic::x86_sse_comigt_ss:
4124 case Intrinsic::x86_sse2_comigt_sd:
4128 case Intrinsic::x86_sse_comige_ss:
4129 case Intrinsic::x86_sse2_comige_sd:
4133 case Intrinsic::x86_sse_comineq_ss:
4134 case Intrinsic::x86_sse2_comineq_sd:
4138 case Intrinsic::x86_sse_ucomieq_ss:
4139 case Intrinsic::x86_sse2_ucomieq_sd:
4140 Opc = X86ISD::UCOMI;
4143 case Intrinsic::x86_sse_ucomilt_ss:
4144 case Intrinsic::x86_sse2_ucomilt_sd:
4145 Opc = X86ISD::UCOMI;
4148 case Intrinsic::x86_sse_ucomile_ss:
4149 case Intrinsic::x86_sse2_ucomile_sd:
4150 Opc = X86ISD::UCOMI;
4153 case Intrinsic::x86_sse_ucomigt_ss:
4154 case Intrinsic::x86_sse2_ucomigt_sd:
4155 Opc = X86ISD::UCOMI;
4158 case Intrinsic::x86_sse_ucomige_ss:
4159 case Intrinsic::x86_sse2_ucomige_sd:
4160 Opc = X86ISD::UCOMI;
4163 case Intrinsic::x86_sse_ucomineq_ss:
4164 case Intrinsic::x86_sse2_ucomineq_sd:
4165 Opc = X86ISD::UCOMI;
4171 SDOperand LHS = Op.getOperand(1);
4172 SDOperand RHS = Op.getOperand(2);
4173 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4175 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4176 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4177 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4178 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4179 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4180 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4181 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4186 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4187 // Depths > 0 not supported yet!
4188 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4191 // Just load the return address
4192 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4193 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4196 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4197 // Depths > 0 not supported yet!
4198 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4201 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4202 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4203 DAG.getConstant(4, getPointerTy()));
4206 /// LowerOperation - Provide custom lowering hooks for some operations.
4208 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4209 switch (Op.getOpcode()) {
4210 default: assert(0 && "Should not custom lower this!");
4211 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4212 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4213 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4214 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4215 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4216 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4217 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4218 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4219 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4220 case ISD::SHL_PARTS:
4221 case ISD::SRA_PARTS:
4222 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4223 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4224 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4225 case ISD::FABS: return LowerFABS(Op, DAG);
4226 case ISD::FNEG: return LowerFNEG(Op, DAG);
4227 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4228 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4229 case ISD::SELECT: return LowerSELECT(Op, DAG);
4230 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4231 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4232 case ISD::CALL: return LowerCALL(Op, DAG);
4233 case ISD::RET: return LowerRET(Op, DAG);
4234 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4235 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4236 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4237 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4238 case ISD::VASTART: return LowerVASTART(Op, DAG);
4239 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
4240 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4241 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4242 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4243 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
4248 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4250 default: return NULL;
4251 case X86ISD::SHLD: return "X86ISD::SHLD";
4252 case X86ISD::SHRD: return "X86ISD::SHRD";
4253 case X86ISD::FAND: return "X86ISD::FAND";
4254 case X86ISD::FOR: return "X86ISD::FOR";
4255 case X86ISD::FXOR: return "X86ISD::FXOR";
4256 case X86ISD::FSRL: return "X86ISD::FSRL";
4257 case X86ISD::FILD: return "X86ISD::FILD";
4258 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4259 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4260 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4261 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4262 case X86ISD::FLD: return "X86ISD::FLD";
4263 case X86ISD::FST: return "X86ISD::FST";
4264 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4265 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4266 case X86ISD::CALL: return "X86ISD::CALL";
4267 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4268 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4269 case X86ISD::CMP: return "X86ISD::CMP";
4270 case X86ISD::COMI: return "X86ISD::COMI";
4271 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4272 case X86ISD::SETCC: return "X86ISD::SETCC";
4273 case X86ISD::CMOV: return "X86ISD::CMOV";
4274 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4275 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4276 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4277 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4278 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4279 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4280 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4281 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4282 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4283 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4284 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4285 case X86ISD::FMAX: return "X86ISD::FMAX";
4286 case X86ISD::FMIN: return "X86ISD::FMIN";
4287 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
4288 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
4292 // isLegalAddressingMode - Return true if the addressing mode represented
4293 // by AM is legal for this target, for a load/store of the specified type.
4294 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
4295 const Type *Ty) const {
4296 // X86 supports extremely general addressing modes.
4298 // X86 allows a sign-extended 32-bit immediate field as a displacement.
4299 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
4303 // X86-64 only supports addr of globals in small code model.
4304 if (Subtarget->is64Bit() &&
4305 getTargetMachine().getCodeModel() != CodeModel::Small)
4308 // We can only fold this if we don't need a load either.
4309 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
4319 // These scales always work.
4324 // These scales are formed with basereg+scalereg. Only accept if there is
4329 default: // Other stuff never works.
4337 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4338 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4339 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4340 /// are assumed to be legal.
4342 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4343 // Only do shuffles on 128-bit vector types for now.
4344 if (MVT::getSizeInBits(VT) == 64) return false;
4345 return (Mask.Val->getNumOperands() <= 4 ||
4346 isIdentityMask(Mask.Val) ||
4347 isIdentityMask(Mask.Val, true) ||
4348 isSplatMask(Mask.Val) ||
4349 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4350 X86::isUNPCKLMask(Mask.Val) ||
4351 X86::isUNPCKHMask(Mask.Val) ||
4352 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4353 X86::isUNPCKH_v_undef_Mask(Mask.Val));
4356 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4358 SelectionDAG &DAG) const {
4359 unsigned NumElts = BVOps.size();
4360 // Only do shuffles on 128-bit vector types for now.
4361 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4362 if (NumElts == 2) return true;
4364 return (isMOVLMask(&BVOps[0], 4) ||
4365 isCommutedMOVL(&BVOps[0], 4, true) ||
4366 isSHUFPMask(&BVOps[0], 4) ||
4367 isCommutedSHUFP(&BVOps[0], 4));
4372 //===----------------------------------------------------------------------===//
4373 // X86 Scheduler Hooks
4374 //===----------------------------------------------------------------------===//
4377 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4378 MachineBasicBlock *BB) {
4379 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4380 switch (MI->getOpcode()) {
4381 default: assert(false && "Unexpected instr type to insert");
4382 case X86::CMOV_FR32:
4383 case X86::CMOV_FR64:
4384 case X86::CMOV_V4F32:
4385 case X86::CMOV_V2F64:
4386 case X86::CMOV_V2I64: {
4387 // To "insert" a SELECT_CC instruction, we actually have to insert the
4388 // diamond control-flow pattern. The incoming instruction knows the
4389 // destination vreg to set, the condition code register to branch on, the
4390 // true/false values to select between, and a branch opcode to use.
4391 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4392 ilist<MachineBasicBlock>::iterator It = BB;
4398 // cmpTY ccX, r1, r2
4400 // fallthrough --> copy0MBB
4401 MachineBasicBlock *thisMBB = BB;
4402 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4403 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4405 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4406 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4407 MachineFunction *F = BB->getParent();
4408 F->getBasicBlockList().insert(It, copy0MBB);
4409 F->getBasicBlockList().insert(It, sinkMBB);
4410 // Update machine-CFG edges by first adding all successors of the current
4411 // block to the new block which will contain the Phi node for the select.
4412 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4413 e = BB->succ_end(); i != e; ++i)
4414 sinkMBB->addSuccessor(*i);
4415 // Next, remove all successors of the current block, and add the true
4416 // and fallthrough blocks as its successors.
4417 while(!BB->succ_empty())
4418 BB->removeSuccessor(BB->succ_begin());
4419 BB->addSuccessor(copy0MBB);
4420 BB->addSuccessor(sinkMBB);
4423 // %FalseValue = ...
4424 // # fallthrough to sinkMBB
4427 // Update machine-CFG edges
4428 BB->addSuccessor(sinkMBB);
4431 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4434 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4435 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4436 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4438 delete MI; // The pseudo instruction is gone now.
4442 case X86::FP32_TO_INT16_IN_MEM:
4443 case X86::FP32_TO_INT32_IN_MEM:
4444 case X86::FP32_TO_INT64_IN_MEM:
4445 case X86::FP64_TO_INT16_IN_MEM:
4446 case X86::FP64_TO_INT32_IN_MEM:
4447 case X86::FP64_TO_INT64_IN_MEM: {
4448 // Change the floating point control register to use "round towards zero"
4449 // mode when truncating to an integer value.
4450 MachineFunction *F = BB->getParent();
4451 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4452 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4454 // Load the old value of the high byte of the control word...
4456 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4457 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4459 // Set the high part to be round to zero...
4460 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4463 // Reload the modified control word now...
4464 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4466 // Restore the memory image of control word to original value
4467 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4470 // Get the X86 opcode to use.
4472 switch (MI->getOpcode()) {
4473 default: assert(0 && "illegal opcode!");
4474 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
4475 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
4476 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
4477 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
4478 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
4479 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
4483 MachineOperand &Op = MI->getOperand(0);
4484 if (Op.isRegister()) {
4485 AM.BaseType = X86AddressMode::RegBase;
4486 AM.Base.Reg = Op.getReg();
4488 AM.BaseType = X86AddressMode::FrameIndexBase;
4489 AM.Base.FrameIndex = Op.getFrameIndex();
4491 Op = MI->getOperand(1);
4492 if (Op.isImmediate())
4493 AM.Scale = Op.getImm();
4494 Op = MI->getOperand(2);
4495 if (Op.isImmediate())
4496 AM.IndexReg = Op.getImm();
4497 Op = MI->getOperand(3);
4498 if (Op.isGlobalAddress()) {
4499 AM.GV = Op.getGlobal();
4501 AM.Disp = Op.getImm();
4503 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4504 .addReg(MI->getOperand(4).getReg());
4506 // Reload the original control word now.
4507 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4509 delete MI; // The pseudo instruction is gone now.
4515 //===----------------------------------------------------------------------===//
4516 // X86 Optimization Hooks
4517 //===----------------------------------------------------------------------===//
4519 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4521 uint64_t &KnownZero,
4523 const SelectionDAG &DAG,
4524 unsigned Depth) const {
4525 unsigned Opc = Op.getOpcode();
4526 assert((Opc >= ISD::BUILTIN_OP_END ||
4527 Opc == ISD::INTRINSIC_WO_CHAIN ||
4528 Opc == ISD::INTRINSIC_W_CHAIN ||
4529 Opc == ISD::INTRINSIC_VOID) &&
4530 "Should use MaskedValueIsZero if you don't know whether Op"
4531 " is a target node!");
4533 KnownZero = KnownOne = 0; // Don't know anything.
4537 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4542 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4543 /// element of the result of the vector shuffle.
4544 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4545 MVT::ValueType VT = N->getValueType(0);
4546 SDOperand PermMask = N->getOperand(2);
4547 unsigned NumElems = PermMask.getNumOperands();
4548 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4550 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4552 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
4553 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4554 SDOperand Idx = PermMask.getOperand(i);
4555 if (Idx.getOpcode() == ISD::UNDEF)
4556 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
4557 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4562 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4563 /// node is a GlobalAddress + an offset.
4564 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4565 unsigned Opc = N->getOpcode();
4566 if (Opc == X86ISD::Wrapper) {
4567 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4568 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4571 } else if (Opc == ISD::ADD) {
4572 SDOperand N1 = N->getOperand(0);
4573 SDOperand N2 = N->getOperand(1);
4574 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4575 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4577 Offset += V->getSignExtended();
4580 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4581 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4583 Offset += V->getSignExtended();
4591 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4593 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4594 MachineFrameInfo *MFI) {
4595 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4598 SDOperand Loc = N->getOperand(1);
4599 SDOperand BaseLoc = Base->getOperand(1);
4600 if (Loc.getOpcode() == ISD::FrameIndex) {
4601 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4603 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
4604 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4605 int FS = MFI->getObjectSize(FI);
4606 int BFS = MFI->getObjectSize(BFI);
4607 if (FS != BFS || FS != Size) return false;
4608 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4610 GlobalValue *GV1 = NULL;
4611 GlobalValue *GV2 = NULL;
4612 int64_t Offset1 = 0;
4613 int64_t Offset2 = 0;
4614 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4615 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4616 if (isGA1 && isGA2 && GV1 == GV2)
4617 return Offset1 == (Offset2 + Dist*Size);
4623 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4624 const X86Subtarget *Subtarget) {
4627 if (isGAPlusOffset(Base, GV, Offset))
4628 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4630 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4631 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
4633 // Fixed objects do not specify alignment, however the offsets are known.
4634 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4635 (MFI->getObjectOffset(BFI) % 16) == 0);
4637 return MFI->getObjectAlignment(BFI) >= 16;
4643 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4644 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4645 /// if the load addresses are consecutive, non-overlapping, and in the right
4647 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4648 const X86Subtarget *Subtarget) {
4649 MachineFunction &MF = DAG.getMachineFunction();
4650 MachineFrameInfo *MFI = MF.getFrameInfo();
4651 MVT::ValueType VT = N->getValueType(0);
4652 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4653 SDOperand PermMask = N->getOperand(2);
4654 int NumElems = (int)PermMask.getNumOperands();
4655 SDNode *Base = NULL;
4656 for (int i = 0; i < NumElems; ++i) {
4657 SDOperand Idx = PermMask.getOperand(i);
4658 if (Idx.getOpcode() == ISD::UNDEF) {
4659 if (!Base) return SDOperand();
4662 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4663 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4667 else if (!isConsecutiveLoad(Arg.Val, Base,
4668 i, MVT::getSizeInBits(EVT)/8,MFI))
4673 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4675 LoadSDNode *LD = cast<LoadSDNode>(Base);
4676 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4677 LD->getSrcValueOffset());
4679 // Just use movups, it's shorter.
4680 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
4681 SmallVector<SDOperand, 3> Ops;
4682 Ops.push_back(Base->getOperand(0));
4683 Ops.push_back(Base->getOperand(1));
4684 Ops.push_back(Base->getOperand(2));
4685 return DAG.getNode(ISD::BIT_CONVERT, VT,
4686 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
4690 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4691 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4692 const X86Subtarget *Subtarget) {
4693 SDOperand Cond = N->getOperand(0);
4695 // If we have SSE[12] support, try to form min/max nodes.
4696 if (Subtarget->hasSSE2() &&
4697 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4698 if (Cond.getOpcode() == ISD::SETCC) {
4699 // Get the LHS/RHS of the select.
4700 SDOperand LHS = N->getOperand(1);
4701 SDOperand RHS = N->getOperand(2);
4702 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4704 unsigned Opcode = 0;
4705 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4708 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4711 if (!UnsafeFPMath) break;
4713 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4715 Opcode = X86ISD::FMIN;
4718 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4721 if (!UnsafeFPMath) break;
4723 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4725 Opcode = X86ISD::FMAX;
4728 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4731 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4734 if (!UnsafeFPMath) break;
4736 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4738 Opcode = X86ISD::FMIN;
4741 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4744 if (!UnsafeFPMath) break;
4746 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4748 Opcode = X86ISD::FMAX;
4754 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4763 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4764 DAGCombinerInfo &DCI) const {
4765 SelectionDAG &DAG = DCI.DAG;
4766 switch (N->getOpcode()) {
4768 case ISD::VECTOR_SHUFFLE:
4769 return PerformShuffleCombine(N, DAG, Subtarget);
4771 return PerformSELECTCombine(N, DAG, Subtarget);
4777 //===----------------------------------------------------------------------===//
4778 // X86 Inline Assembly Support
4779 //===----------------------------------------------------------------------===//
4781 /// getConstraintType - Given a constraint letter, return the type of
4782 /// constraint it is for this target.
4783 X86TargetLowering::ConstraintType
4784 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
4785 if (Constraint.size() == 1) {
4786 switch (Constraint[0]) {
4795 return C_RegisterClass;
4800 return TargetLowering::getConstraintType(Constraint);
4803 /// isOperandValidForConstraint - Return the specified operand (possibly
4804 /// modified) if the specified SDOperand is valid for the specified target
4805 /// constraint letter, otherwise return null.
4806 SDOperand X86TargetLowering::
4807 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
4808 switch (Constraint) {
4811 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4812 if (C->getValue() <= 31)
4813 return DAG.getTargetConstant(C->getValue(), Op.getValueType());
4815 return SDOperand(0,0);
4817 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4818 if (C->getValue() <= 255)
4819 return DAG.getTargetConstant(C->getValue(), Op.getValueType());
4821 return SDOperand(0,0);
4823 // Literal immediates are always ok.
4824 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op))
4825 return DAG.getTargetConstant(CST->getValue(), Op.getValueType());
4827 // If we are in non-pic codegen mode, we allow the address of a global (with
4828 // an optional displacement) to be used with 'i'.
4829 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
4832 // Match either (GA) or (GA+C)
4834 Offset = GA->getOffset();
4835 } else if (Op.getOpcode() == ISD::ADD) {
4836 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
4837 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
4839 Offset = GA->getOffset()+C->getValue();
4841 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
4842 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
4844 Offset = GA->getOffset()+C->getValue();
4851 // If addressing this global requires a load (e.g. in PIC mode), we can't
4853 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
4855 return SDOperand(0, 0);
4857 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4862 // Otherwise, not valid for this mode.
4863 return SDOperand(0, 0);
4866 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
4869 std::vector<unsigned> X86TargetLowering::
4870 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4871 MVT::ValueType VT) const {
4872 if (Constraint.size() == 1) {
4873 // FIXME: not handling fp-stack yet!
4874 switch (Constraint[0]) { // GCC X86 Constraint Letters
4875 default: break; // Unknown constraint letter
4876 case 'A': // EAX/EDX
4877 if (VT == MVT::i32 || VT == MVT::i64)
4878 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
4880 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
4883 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
4884 else if (VT == MVT::i16)
4885 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
4886 else if (VT == MVT::i8)
4887 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4892 return std::vector<unsigned>();
4895 std::pair<unsigned, const TargetRegisterClass*>
4896 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4897 MVT::ValueType VT) const {
4898 // First, see if this is a constraint that directly corresponds to an LLVM
4900 if (Constraint.size() == 1) {
4901 // GCC Constraint Letters
4902 switch (Constraint[0]) {
4904 case 'r': // GENERAL_REGS
4905 case 'R': // LEGACY_REGS
4906 case 'l': // INDEX_REGS
4907 if (VT == MVT::i64 && Subtarget->is64Bit())
4908 return std::make_pair(0U, X86::GR64RegisterClass);
4910 return std::make_pair(0U, X86::GR32RegisterClass);
4911 else if (VT == MVT::i16)
4912 return std::make_pair(0U, X86::GR16RegisterClass);
4913 else if (VT == MVT::i8)
4914 return std::make_pair(0U, X86::GR8RegisterClass);
4916 case 'y': // MMX_REGS if MMX allowed.
4917 if (!Subtarget->hasMMX()) break;
4918 return std::make_pair(0U, X86::VR64RegisterClass);
4920 case 'Y': // SSE_REGS if SSE2 allowed
4921 if (!Subtarget->hasSSE2()) break;
4923 case 'x': // SSE_REGS if SSE1 allowed
4924 if (!Subtarget->hasSSE1()) break;
4928 // Scalar SSE types.
4931 return std::make_pair(0U, X86::FR32RegisterClass);
4934 return std::make_pair(0U, X86::FR64RegisterClass);
4942 return std::make_pair(0U, X86::VR128RegisterClass);
4948 // Use the default implementation in TargetLowering to convert the register
4949 // constraint into a member of a register class.
4950 std::pair<unsigned, const TargetRegisterClass*> Res;
4951 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4953 // Not found as a standard register?
4954 if (Res.second == 0) {
4955 // GCC calls "st(0)" just plain "st".
4956 if (StringsEqualNoCase("{st}", Constraint)) {
4957 Res.first = X86::ST0;
4958 Res.second = X86::RSTRegisterClass;
4964 // Otherwise, check to see if this is a register class of the wrong value
4965 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
4966 // turn into {ax},{dx}.
4967 if (Res.second->hasType(VT))
4968 return Res; // Correct type already, nothing to do.
4970 // All of the single-register GCC register classes map their values onto
4971 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
4972 // really want an 8-bit or 32-bit register, map to the appropriate register
4973 // class and return the appropriate register.
4974 if (Res.second != X86::GR16RegisterClass)
4977 if (VT == MVT::i8) {
4978 unsigned DestReg = 0;
4979 switch (Res.first) {
4981 case X86::AX: DestReg = X86::AL; break;
4982 case X86::DX: DestReg = X86::DL; break;
4983 case X86::CX: DestReg = X86::CL; break;
4984 case X86::BX: DestReg = X86::BL; break;
4987 Res.first = DestReg;
4988 Res.second = Res.second = X86::GR8RegisterClass;
4990 } else if (VT == MVT::i32) {
4991 unsigned DestReg = 0;
4992 switch (Res.first) {
4994 case X86::AX: DestReg = X86::EAX; break;
4995 case X86::DX: DestReg = X86::EDX; break;
4996 case X86::CX: DestReg = X86::ECX; break;
4997 case X86::BX: DestReg = X86::EBX; break;
4998 case X86::SI: DestReg = X86::ESI; break;
4999 case X86::DI: DestReg = X86::EDI; break;
5000 case X86::BP: DestReg = X86::EBP; break;
5001 case X86::SP: DestReg = X86::ESP; break;
5004 Res.first = DestReg;
5005 Res.second = Res.second = X86::GR32RegisterClass;
5007 } else if (VT == MVT::i64) {
5008 unsigned DestReg = 0;
5009 switch (Res.first) {
5011 case X86::AX: DestReg = X86::RAX; break;
5012 case X86::DX: DestReg = X86::RDX; break;
5013 case X86::CX: DestReg = X86::RCX; break;
5014 case X86::BX: DestReg = X86::RBX; break;
5015 case X86::SI: DestReg = X86::RSI; break;
5016 case X86::DI: DestReg = X86::RDI; break;
5017 case X86::BP: DestReg = X86::RBP; break;
5018 case X86::SP: DestReg = X86::RSP; break;
5021 Res.first = DestReg;
5022 Res.second = Res.second = X86::GR64RegisterClass;