1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!Subtarget->useSoftFloat()) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!Subtarget->useSoftFloat()) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!Subtarget->useSoftFloat()) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
835 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
836 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
837 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
845 // Only provide customized ctpop vector bit twiddling for vector types we
846 // know to perform better than using the popcnt instructions on each vector
847 // element. If popcnt isn't supported, always provide the custom version.
848 if (!Subtarget->hasPOPCNT()) {
849 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
855 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
856 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
857 MVT VT = (MVT::SimpleValueType)i;
858 // Do not attempt to custom lower non-power-of-2 vectors
859 if (!isPowerOf2_32(VT.getVectorNumElements()))
861 // Do not attempt to custom lower non-128-bit vectors
862 if (!VT.is128BitVector())
864 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
865 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
866 setOperationAction(ISD::VSELECT, VT, Custom);
867 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
870 // We support custom legalizing of sext and anyext loads for specific
871 // memory vector types which we can load as a scalar (or sequence of
872 // scalars) and extend in-register to a legal 128-bit vector type. For sext
873 // loads these must work with a single scalar load.
874 for (MVT VT : MVT::integer_vector_valuetypes()) {
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
876 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
887 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
889 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
890 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
891 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
892 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
893 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
895 if (Subtarget->is64Bit()) {
896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
897 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
900 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
901 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
902 MVT VT = (MVT::SimpleValueType)i;
904 // Do not attempt to promote non-128-bit vectors
905 if (!VT.is128BitVector())
908 setOperationAction(ISD::AND, VT, Promote);
909 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
910 setOperationAction(ISD::OR, VT, Promote);
911 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
912 setOperationAction(ISD::XOR, VT, Promote);
913 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
914 setOperationAction(ISD::LOAD, VT, Promote);
915 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
916 setOperationAction(ISD::SELECT, VT, Promote);
917 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
920 // Custom lower v2i64 and v2f64 selects.
921 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
922 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
923 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
924 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
926 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
927 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
929 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
930 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
931 // As there is no 64-bit GPR available, we need build a special custom
932 // sequence to convert from v2i32 to v2f32.
933 if (!Subtarget->is64Bit())
934 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
936 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
937 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
939 for (MVT VT : MVT::fp_vector_valuetypes())
940 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
942 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
943 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
944 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
947 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
948 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
949 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
950 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
951 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
952 setOperationAction(ISD::FRINT, RoundedTy, Legal);
953 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
956 // FIXME: Do we need to handle scalar-to-vector here?
957 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
959 // We directly match byte blends in the backend as they match the VSELECT
961 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
963 // SSE41 brings specific instructions for doing vector sign extend even in
964 // cases where we don't have SRA.
965 for (MVT VT : MVT::integer_vector_valuetypes()) {
966 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
967 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
968 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
971 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
972 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
973 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
974 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
976 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
979 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 // i8 and i16 vectors are custom because the source register and source
987 // source memory operand types are not the same width. f32 vectors are
988 // custom since the immediate controlling the insert encodes additional
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1000 // FIXME: these should be Legal, but that's only for the case where
1001 // the index is constant. For now custom expand to deal with that.
1002 if (Subtarget->is64Bit()) {
1003 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1008 if (Subtarget->hasSSE2()) {
1009 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1010 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1011 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1013 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1014 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1016 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1017 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1019 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1022 // In the customized shift lowering, the legal cases in AVX2 will be
1024 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1025 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1027 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1028 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1033 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1034 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1035 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1036 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1037 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1038 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1039 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1041 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1042 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1043 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1045 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1047 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1048 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1049 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1053 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1054 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1056 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1058 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1060 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1061 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1062 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1063 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1064 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1065 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1066 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1067 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1069 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1071 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1072 // even though v8i16 is a legal type.
1073 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1074 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1075 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1078 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1079 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1081 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1082 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1084 for (MVT VT : MVT::fp_vector_valuetypes())
1085 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1087 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1088 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1090 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1091 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1093 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1094 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1096 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1097 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1098 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1099 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1102 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1103 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1105 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1108 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1109 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1110 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1111 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1112 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1113 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1114 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1115 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1116 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1118 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1119 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1120 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1121 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1122 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1123 setOperationAction(ISD::FMA, MVT::f32, Legal);
1124 setOperationAction(ISD::FMA, MVT::f64, Legal);
1127 if (Subtarget->hasInt256()) {
1128 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1129 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1130 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1131 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1133 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1134 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1135 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1136 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1138 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1139 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1140 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1141 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1143 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1144 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1145 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1146 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1148 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1149 // when we have a 256bit-wide blend with immediate.
1150 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1152 // Only provide customized ctpop vector bit twiddling for vector types we
1153 // know to perform better than using the popcnt instructions on each
1154 // vector element. If popcnt isn't supported, always provide the custom
1156 if (!Subtarget->hasPOPCNT())
1157 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1159 // Custom CTPOP always performs better on natively supported v8i32
1160 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1162 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1163 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1164 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1165 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1166 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1167 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1168 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1170 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1171 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1172 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1173 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1174 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1175 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1177 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1178 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1179 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1180 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1182 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1184 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1185 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1187 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1188 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1189 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1190 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1193 // In the customized shift lowering, the legal cases in AVX2 will be
1195 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1196 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1198 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1199 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1201 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1203 // Custom lower several nodes for 256-bit types.
1204 for (MVT VT : MVT::vector_valuetypes()) {
1205 if (VT.getScalarSizeInBits() >= 32) {
1206 setOperationAction(ISD::MLOAD, VT, Legal);
1207 setOperationAction(ISD::MSTORE, VT, Legal);
1209 // Extract subvector is special because the value type
1210 // (result) is 128-bit but the source is 256-bit wide.
1211 if (VT.is128BitVector()) {
1212 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1214 // Do not attempt to custom lower other non-256-bit vectors
1215 if (!VT.is256BitVector())
1218 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1219 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1220 setOperationAction(ISD::VSELECT, VT, Custom);
1221 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1222 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1223 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1224 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1225 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1228 if (Subtarget->hasInt256())
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1232 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1233 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1234 MVT VT = (MVT::SimpleValueType)i;
1236 // Do not attempt to promote non-256-bit vectors
1237 if (!VT.is256BitVector())
1240 setOperationAction(ISD::AND, VT, Promote);
1241 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1242 setOperationAction(ISD::OR, VT, Promote);
1243 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1244 setOperationAction(ISD::XOR, VT, Promote);
1245 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1246 setOperationAction(ISD::LOAD, VT, Promote);
1247 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1248 setOperationAction(ISD::SELECT, VT, Promote);
1249 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1253 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1254 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1255 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1256 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1257 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1259 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1260 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1261 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1263 for (MVT VT : MVT::fp_vector_valuetypes())
1264 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1266 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1267 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1268 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1269 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1270 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1271 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1272 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1273 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1274 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1275 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1276 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1277 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1279 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1280 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1281 setOperationAction(ISD::XOR, MVT::i1, Legal);
1282 setOperationAction(ISD::OR, MVT::i1, Legal);
1283 setOperationAction(ISD::AND, MVT::i1, Legal);
1284 setOperationAction(ISD::SUB, MVT::i1, Custom);
1285 setOperationAction(ISD::ADD, MVT::i1, Custom);
1286 setOperationAction(ISD::MUL, MVT::i1, Custom);
1287 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1288 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1289 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1290 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1291 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1293 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1294 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1295 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1296 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1297 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1298 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1300 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1301 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1302 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1303 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1304 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1305 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1306 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1307 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1309 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1310 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1311 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1312 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1313 if (Subtarget->is64Bit()) {
1314 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1315 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1316 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1317 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1319 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1320 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1321 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1322 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1323 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1324 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1325 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1326 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1327 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1328 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1329 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1330 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1331 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1332 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1333 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1334 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1336 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1337 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1338 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1339 if (Subtarget->hasDQI()) {
1340 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1341 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1343 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1344 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1345 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1346 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1347 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1348 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1349 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1353 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1355 if (Subtarget->hasDQI()) {
1356 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1357 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1359 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1360 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1362 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1363 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1364 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1365 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1366 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1367 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1368 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1370 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1371 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1373 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1374 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1376 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1377 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1379 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1381 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1382 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1383 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1384 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1385 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1386 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1387 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1388 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1389 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1390 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1391 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1393 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1394 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1396 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1397 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1399 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1401 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1402 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1404 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1405 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1407 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1408 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1410 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1411 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1412 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1413 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1414 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1415 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1417 if (Subtarget->hasCDI()) {
1418 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1419 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1421 if (Subtarget->hasDQI()) {
1422 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1423 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1424 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1426 // Custom lower several nodes.
1427 for (MVT VT : MVT::vector_valuetypes()) {
1428 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1430 setOperationAction(ISD::AND, VT, Legal);
1431 setOperationAction(ISD::OR, VT, Legal);
1432 setOperationAction(ISD::XOR, VT, Legal);
1434 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1435 setOperationAction(ISD::MGATHER, VT, Custom);
1436 setOperationAction(ISD::MSCATTER, VT, Custom);
1438 // Extract subvector is special because the value type
1439 // (result) is 256/128-bit but the source is 512-bit wide.
1440 if (VT.is128BitVector() || VT.is256BitVector()) {
1441 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1443 if (VT.getVectorElementType() == MVT::i1)
1444 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1446 // Do not attempt to custom lower other non-512-bit vectors
1447 if (!VT.is512BitVector())
1450 if (EltSize >= 32) {
1451 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1454 setOperationAction(ISD::VSELECT, VT, Legal);
1455 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1456 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1457 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1458 setOperationAction(ISD::MLOAD, VT, Legal);
1459 setOperationAction(ISD::MSTORE, VT, Legal);
1462 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1463 MVT VT = (MVT::SimpleValueType)i;
1465 // Do not attempt to promote non-512-bit vectors.
1466 if (!VT.is512BitVector())
1469 setOperationAction(ISD::SELECT, VT, Promote);
1470 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1474 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1475 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1476 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1478 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1479 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1481 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1482 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1483 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1484 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1485 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1486 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1487 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1488 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1489 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1490 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1491 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1492 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1493 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1494 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1495 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1496 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1497 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1498 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1499 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1500 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1501 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1502 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1503 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1504 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1505 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1506 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1507 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1509 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1510 const MVT VT = (MVT::SimpleValueType)i;
1512 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1514 // Do not attempt to promote non-512-bit vectors.
1515 if (!VT.is512BitVector())
1519 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1520 setOperationAction(ISD::VSELECT, VT, Legal);
1525 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1526 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1527 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1529 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1530 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1531 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1532 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1533 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1534 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1535 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1536 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1537 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1538 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1540 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1541 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1542 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1543 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1544 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1545 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1546 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1547 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1550 // We want to custom lower some of our intrinsics.
1551 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1552 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1553 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1554 if (!Subtarget->is64Bit())
1555 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1557 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1558 // handle type legalization for these operations here.
1560 // FIXME: We really should do custom legalization for addition and
1561 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1562 // than generic legalization for 64-bit multiplication-with-overflow, though.
1563 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1564 // Add/Sub/Mul with overflow operations are custom lowered.
1566 setOperationAction(ISD::SADDO, VT, Custom);
1567 setOperationAction(ISD::UADDO, VT, Custom);
1568 setOperationAction(ISD::SSUBO, VT, Custom);
1569 setOperationAction(ISD::USUBO, VT, Custom);
1570 setOperationAction(ISD::SMULO, VT, Custom);
1571 setOperationAction(ISD::UMULO, VT, Custom);
1575 if (!Subtarget->is64Bit()) {
1576 // These libcalls are not available in 32-bit.
1577 setLibcallName(RTLIB::SHL_I128, nullptr);
1578 setLibcallName(RTLIB::SRL_I128, nullptr);
1579 setLibcallName(RTLIB::SRA_I128, nullptr);
1582 // Combine sin / cos into one node or libcall if possible.
1583 if (Subtarget->hasSinCos()) {
1584 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1585 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1586 if (Subtarget->isTargetDarwin()) {
1587 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1588 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1589 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1590 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1594 if (Subtarget->isTargetWin64()) {
1595 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1596 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1597 setOperationAction(ISD::SREM, MVT::i128, Custom);
1598 setOperationAction(ISD::UREM, MVT::i128, Custom);
1599 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1600 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1603 // We have target-specific dag combine patterns for the following nodes:
1604 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1605 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1606 setTargetDAGCombine(ISD::BITCAST);
1607 setTargetDAGCombine(ISD::VSELECT);
1608 setTargetDAGCombine(ISD::SELECT);
1609 setTargetDAGCombine(ISD::SHL);
1610 setTargetDAGCombine(ISD::SRA);
1611 setTargetDAGCombine(ISD::SRL);
1612 setTargetDAGCombine(ISD::OR);
1613 setTargetDAGCombine(ISD::AND);
1614 setTargetDAGCombine(ISD::ADD);
1615 setTargetDAGCombine(ISD::FADD);
1616 setTargetDAGCombine(ISD::FSUB);
1617 setTargetDAGCombine(ISD::FMA);
1618 setTargetDAGCombine(ISD::SUB);
1619 setTargetDAGCombine(ISD::LOAD);
1620 setTargetDAGCombine(ISD::MLOAD);
1621 setTargetDAGCombine(ISD::STORE);
1622 setTargetDAGCombine(ISD::MSTORE);
1623 setTargetDAGCombine(ISD::ZERO_EXTEND);
1624 setTargetDAGCombine(ISD::ANY_EXTEND);
1625 setTargetDAGCombine(ISD::SIGN_EXTEND);
1626 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1627 setTargetDAGCombine(ISD::SINT_TO_FP);
1628 setTargetDAGCombine(ISD::SETCC);
1629 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1630 setTargetDAGCombine(ISD::BUILD_VECTOR);
1631 setTargetDAGCombine(ISD::MUL);
1632 setTargetDAGCombine(ISD::XOR);
1634 computeRegisterProperties(Subtarget->getRegisterInfo());
1636 // On Darwin, -Os means optimize for size without hurting performance,
1637 // do not reduce the limit.
1638 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1639 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1640 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1641 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1642 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1643 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1644 setPrefLoopAlignment(4); // 2^4 bytes.
1646 // Predictable cmov don't hurt on atom because it's in-order.
1647 PredictableSelectIsExpensive = !Subtarget->isAtom();
1648 EnableExtLdPromotion = true;
1649 setPrefFunctionAlignment(4); // 2^4 bytes.
1651 verifyIntrinsicTables();
1654 // This has so far only been implemented for 64-bit MachO.
1655 bool X86TargetLowering::useLoadStackGuardNode() const {
1656 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1659 TargetLoweringBase::LegalizeTypeAction
1660 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1661 if (ExperimentalVectorWideningLegalization &&
1662 VT.getVectorNumElements() != 1 &&
1663 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1664 return TypeWidenVector;
1666 return TargetLoweringBase::getPreferredVectorAction(VT);
1669 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1671 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1673 const unsigned NumElts = VT.getVectorNumElements();
1674 const EVT EltVT = VT.getVectorElementType();
1675 if (VT.is512BitVector()) {
1676 if (Subtarget->hasAVX512())
1677 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1678 EltVT == MVT::f32 || EltVT == MVT::f64)
1680 case 8: return MVT::v8i1;
1681 case 16: return MVT::v16i1;
1683 if (Subtarget->hasBWI())
1684 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1686 case 32: return MVT::v32i1;
1687 case 64: return MVT::v64i1;
1691 if (VT.is256BitVector() || VT.is128BitVector()) {
1692 if (Subtarget->hasVLX())
1693 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1694 EltVT == MVT::f32 || EltVT == MVT::f64)
1696 case 2: return MVT::v2i1;
1697 case 4: return MVT::v4i1;
1698 case 8: return MVT::v8i1;
1700 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1701 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1703 case 8: return MVT::v8i1;
1704 case 16: return MVT::v16i1;
1705 case 32: return MVT::v32i1;
1709 return VT.changeVectorElementTypeToInteger();
1712 /// Helper for getByValTypeAlignment to determine
1713 /// the desired ByVal argument alignment.
1714 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1717 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1718 if (VTy->getBitWidth() == 128)
1720 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1721 unsigned EltAlign = 0;
1722 getMaxByValAlign(ATy->getElementType(), EltAlign);
1723 if (EltAlign > MaxAlign)
1724 MaxAlign = EltAlign;
1725 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1726 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1727 unsigned EltAlign = 0;
1728 getMaxByValAlign(STy->getElementType(i), EltAlign);
1729 if (EltAlign > MaxAlign)
1730 MaxAlign = EltAlign;
1737 /// Return the desired alignment for ByVal aggregate
1738 /// function arguments in the caller parameter area. For X86, aggregates
1739 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1740 /// are at 4-byte boundaries.
1741 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1742 if (Subtarget->is64Bit()) {
1743 // Max of 8 and alignment of type.
1744 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1751 if (Subtarget->hasSSE1())
1752 getMaxByValAlign(Ty, Align);
1756 /// Returns the target specific optimal type for load
1757 /// and store operations as a result of memset, memcpy, and memmove
1758 /// lowering. If DstAlign is zero that means it's safe to destination
1759 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1760 /// means there isn't a need to check it against alignment requirement,
1761 /// probably because the source does not need to be loaded. If 'IsMemset' is
1762 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1763 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1764 /// source is constant so it does not need to be loaded.
1765 /// It returns EVT::Other if the type should be determined using generic
1766 /// target-independent logic.
1768 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1769 unsigned DstAlign, unsigned SrcAlign,
1770 bool IsMemset, bool ZeroMemset,
1772 MachineFunction &MF) const {
1773 const Function *F = MF.getFunction();
1774 if ((!IsMemset || ZeroMemset) &&
1775 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1777 (Subtarget->isUnalignedMemAccessFast() ||
1778 ((DstAlign == 0 || DstAlign >= 16) &&
1779 (SrcAlign == 0 || SrcAlign >= 16)))) {
1781 if (Subtarget->hasInt256())
1783 if (Subtarget->hasFp256())
1786 if (Subtarget->hasSSE2())
1788 if (Subtarget->hasSSE1())
1790 } else if (!MemcpyStrSrc && Size >= 8 &&
1791 !Subtarget->is64Bit() &&
1792 Subtarget->hasSSE2()) {
1793 // Do not use f64 to lower memcpy if source is string constant. It's
1794 // better to use i32 to avoid the loads.
1798 if (Subtarget->is64Bit() && Size >= 8)
1803 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1805 return X86ScalarSSEf32;
1806 else if (VT == MVT::f64)
1807 return X86ScalarSSEf64;
1812 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1817 *Fast = Subtarget->isUnalignedMemAccessFast();
1821 /// Return the entry encoding for a jump table in the
1822 /// current function. The returned value is a member of the
1823 /// MachineJumpTableInfo::JTEntryKind enum.
1824 unsigned X86TargetLowering::getJumpTableEncoding() const {
1825 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1827 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1828 Subtarget->isPICStyleGOT())
1829 return MachineJumpTableInfo::EK_Custom32;
1831 // Otherwise, use the normal jump table encoding heuristics.
1832 return TargetLowering::getJumpTableEncoding();
1835 bool X86TargetLowering::useSoftFloat() const {
1836 return Subtarget->useSoftFloat();
1840 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1841 const MachineBasicBlock *MBB,
1842 unsigned uid,MCContext &Ctx) const{
1843 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1844 Subtarget->isPICStyleGOT());
1845 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1847 return MCSymbolRefExpr::create(MBB->getSymbol(),
1848 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1851 /// Returns relocation base for the given PIC jumptable.
1852 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1853 SelectionDAG &DAG) const {
1854 if (!Subtarget->is64Bit())
1855 // This doesn't have SDLoc associated with it, but is not really the
1856 // same as a Register.
1857 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1861 /// This returns the relocation base for the given PIC jumptable,
1862 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1863 const MCExpr *X86TargetLowering::
1864 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1865 MCContext &Ctx) const {
1866 // X86-64 uses RIP relative addressing based on the jump table label.
1867 if (Subtarget->isPICStyleRIPRel())
1868 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1870 // Otherwise, the reference is relative to the PIC base.
1871 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1874 std::pair<const TargetRegisterClass *, uint8_t>
1875 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1877 const TargetRegisterClass *RRC = nullptr;
1879 switch (VT.SimpleTy) {
1881 return TargetLowering::findRepresentativeClass(TRI, VT);
1882 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1883 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1886 RRC = &X86::VR64RegClass;
1888 case MVT::f32: case MVT::f64:
1889 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1890 case MVT::v4f32: case MVT::v2f64:
1891 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1893 RRC = &X86::VR128RegClass;
1896 return std::make_pair(RRC, Cost);
1899 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1900 unsigned &Offset) const {
1901 if (!Subtarget->isTargetLinux())
1904 if (Subtarget->is64Bit()) {
1905 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1907 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1919 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1920 unsigned DestAS) const {
1921 assert(SrcAS != DestAS && "Expected different address spaces!");
1923 return SrcAS < 256 && DestAS < 256;
1926 //===----------------------------------------------------------------------===//
1927 // Return Value Calling Convention Implementation
1928 //===----------------------------------------------------------------------===//
1930 #include "X86GenCallingConv.inc"
1933 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1934 MachineFunction &MF, bool isVarArg,
1935 const SmallVectorImpl<ISD::OutputArg> &Outs,
1936 LLVMContext &Context) const {
1937 SmallVector<CCValAssign, 16> RVLocs;
1938 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1939 return CCInfo.CheckReturn(Outs, RetCC_X86);
1942 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1943 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1948 X86TargetLowering::LowerReturn(SDValue Chain,
1949 CallingConv::ID CallConv, bool isVarArg,
1950 const SmallVectorImpl<ISD::OutputArg> &Outs,
1951 const SmallVectorImpl<SDValue> &OutVals,
1952 SDLoc dl, SelectionDAG &DAG) const {
1953 MachineFunction &MF = DAG.getMachineFunction();
1954 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1956 SmallVector<CCValAssign, 16> RVLocs;
1957 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1958 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1961 SmallVector<SDValue, 6> RetOps;
1962 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1963 // Operand #1 = Bytes To Pop
1964 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1967 // Copy the result values into the output registers.
1968 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1969 CCValAssign &VA = RVLocs[i];
1970 assert(VA.isRegLoc() && "Can only return in registers!");
1971 SDValue ValToCopy = OutVals[i];
1972 EVT ValVT = ValToCopy.getValueType();
1974 // Promote values to the appropriate types.
1975 if (VA.getLocInfo() == CCValAssign::SExt)
1976 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1977 else if (VA.getLocInfo() == CCValAssign::ZExt)
1978 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1979 else if (VA.getLocInfo() == CCValAssign::AExt) {
1980 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1981 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1983 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1985 else if (VA.getLocInfo() == CCValAssign::BCvt)
1986 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1988 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1989 "Unexpected FP-extend for return value.");
1991 // If this is x86-64, and we disabled SSE, we can't return FP values,
1992 // or SSE or MMX vectors.
1993 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1994 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1995 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1996 report_fatal_error("SSE register return with SSE disabled");
1998 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1999 // llvm-gcc has never done it right and no one has noticed, so this
2000 // should be OK for now.
2001 if (ValVT == MVT::f64 &&
2002 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2003 report_fatal_error("SSE2 register return with SSE2 disabled");
2005 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2006 // the RET instruction and handled by the FP Stackifier.
2007 if (VA.getLocReg() == X86::FP0 ||
2008 VA.getLocReg() == X86::FP1) {
2009 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2010 // change the value to the FP stack register class.
2011 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2012 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2013 RetOps.push_back(ValToCopy);
2014 // Don't emit a copytoreg.
2018 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2019 // which is returned in RAX / RDX.
2020 if (Subtarget->is64Bit()) {
2021 if (ValVT == MVT::x86mmx) {
2022 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2023 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2024 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2026 // If we don't have SSE2 available, convert to v4f32 so the generated
2027 // register is legal.
2028 if (!Subtarget->hasSSE2())
2029 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2034 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2035 Flag = Chain.getValue(1);
2036 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2039 // All x86 ABIs require that for returning structs by value we copy
2040 // the sret argument into %rax/%eax (depending on ABI) for the return.
2041 // We saved the argument into a virtual register in the entry block,
2042 // so now we copy the value out and into %rax/%eax.
2044 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2045 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2046 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2047 // either case FuncInfo->setSRetReturnReg() will have been called.
2048 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2049 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2052 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2053 X86::RAX : X86::EAX;
2054 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2055 Flag = Chain.getValue(1);
2057 // RAX/EAX now acts like a return value.
2058 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2061 RetOps[0] = Chain; // Update chain.
2063 // Add the flag if we have it.
2065 RetOps.push_back(Flag);
2067 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2070 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2071 if (N->getNumValues() != 1)
2073 if (!N->hasNUsesOfValue(1, 0))
2076 SDValue TCChain = Chain;
2077 SDNode *Copy = *N->use_begin();
2078 if (Copy->getOpcode() == ISD::CopyToReg) {
2079 // If the copy has a glue operand, we conservatively assume it isn't safe to
2080 // perform a tail call.
2081 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2083 TCChain = Copy->getOperand(0);
2084 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2087 bool HasRet = false;
2088 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2090 if (UI->getOpcode() != X86ISD::RET_FLAG)
2092 // If we are returning more than one value, we can definitely
2093 // not make a tail call see PR19530
2094 if (UI->getNumOperands() > 4)
2096 if (UI->getNumOperands() == 4 &&
2097 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2110 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2111 ISD::NodeType ExtendKind) const {
2113 // TODO: Is this also valid on 32-bit?
2114 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2115 ReturnMVT = MVT::i8;
2117 ReturnMVT = MVT::i32;
2119 EVT MinVT = getRegisterType(Context, ReturnMVT);
2120 return VT.bitsLT(MinVT) ? MinVT : VT;
2123 /// Lower the result values of a call into the
2124 /// appropriate copies out of appropriate physical registers.
2127 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2128 CallingConv::ID CallConv, bool isVarArg,
2129 const SmallVectorImpl<ISD::InputArg> &Ins,
2130 SDLoc dl, SelectionDAG &DAG,
2131 SmallVectorImpl<SDValue> &InVals) const {
2133 // Assign locations to each value returned by this call.
2134 SmallVector<CCValAssign, 16> RVLocs;
2135 bool Is64Bit = Subtarget->is64Bit();
2136 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2138 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2140 // Copy all of the result registers out of their specified physreg.
2141 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2142 CCValAssign &VA = RVLocs[i];
2143 EVT CopyVT = VA.getLocVT();
2145 // If this is x86-64, and we disabled SSE, we can't return FP values
2146 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2147 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2148 report_fatal_error("SSE register return with SSE disabled");
2151 // If we prefer to use the value in xmm registers, copy it out as f80 and
2152 // use a truncate to move it from fp stack reg to xmm reg.
2153 bool RoundAfterCopy = false;
2154 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2155 isScalarFPTypeInSSEReg(VA.getValVT())) {
2157 RoundAfterCopy = (CopyVT != VA.getLocVT());
2160 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2161 CopyVT, InFlag).getValue(1);
2162 SDValue Val = Chain.getValue(0);
2165 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2166 // This truncation won't change the value.
2167 DAG.getIntPtrConstant(1, dl));
2169 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2170 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2172 InFlag = Chain.getValue(2);
2173 InVals.push_back(Val);
2179 //===----------------------------------------------------------------------===//
2180 // C & StdCall & Fast Calling Convention implementation
2181 //===----------------------------------------------------------------------===//
2182 // StdCall calling convention seems to be standard for many Windows' API
2183 // routines and around. It differs from C calling convention just a little:
2184 // callee should clean up the stack, not caller. Symbols should be also
2185 // decorated in some fancy way :) It doesn't support any vector arguments.
2186 // For info on fast calling convention see Fast Calling Convention (tail call)
2187 // implementation LowerX86_32FastCCCallTo.
2189 /// CallIsStructReturn - Determines whether a call uses struct return
2191 enum StructReturnType {
2196 static StructReturnType
2197 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2199 return NotStructReturn;
2201 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2202 if (!Flags.isSRet())
2203 return NotStructReturn;
2204 if (Flags.isInReg())
2205 return RegStructReturn;
2206 return StackStructReturn;
2209 /// Determines whether a function uses struct return semantics.
2210 static StructReturnType
2211 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2213 return NotStructReturn;
2215 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2216 if (!Flags.isSRet())
2217 return NotStructReturn;
2218 if (Flags.isInReg())
2219 return RegStructReturn;
2220 return StackStructReturn;
2223 /// Make a copy of an aggregate at address specified by "Src" to address
2224 /// "Dst" with size and alignment information specified by the specific
2225 /// parameter attribute. The copy will be passed as a byval function parameter.
2227 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2228 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2230 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2232 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2233 /*isVolatile*/false, /*AlwaysInline=*/true,
2234 /*isTailCall*/false,
2235 MachinePointerInfo(), MachinePointerInfo());
2238 /// Return true if the calling convention is one that
2239 /// supports tail call optimization.
2240 static bool IsTailCallConvention(CallingConv::ID CC) {
2241 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2242 CC == CallingConv::HiPE);
2245 /// \brief Return true if the calling convention is a C calling convention.
2246 static bool IsCCallConvention(CallingConv::ID CC) {
2247 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2248 CC == CallingConv::X86_64_SysV);
2251 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2252 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2256 CallingConv::ID CalleeCC = CS.getCallingConv();
2257 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2263 /// Return true if the function is being made into
2264 /// a tailcall target by changing its ABI.
2265 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2266 bool GuaranteedTailCallOpt) {
2267 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2271 X86TargetLowering::LowerMemArgument(SDValue Chain,
2272 CallingConv::ID CallConv,
2273 const SmallVectorImpl<ISD::InputArg> &Ins,
2274 SDLoc dl, SelectionDAG &DAG,
2275 const CCValAssign &VA,
2276 MachineFrameInfo *MFI,
2278 // Create the nodes corresponding to a load from this parameter slot.
2279 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2280 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2281 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2282 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2285 // If value is passed by pointer we have address passed instead of the value
2287 bool ExtendedInMem = VA.isExtInLoc() &&
2288 VA.getValVT().getScalarType() == MVT::i1;
2290 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2291 ValVT = VA.getLocVT();
2293 ValVT = VA.getValVT();
2295 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2296 // changed with more analysis.
2297 // In case of tail call optimization mark all arguments mutable. Since they
2298 // could be overwritten by lowering of arguments in case of a tail call.
2299 if (Flags.isByVal()) {
2300 unsigned Bytes = Flags.getByValSize();
2301 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2302 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2303 return DAG.getFrameIndex(FI, getPointerTy());
2305 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2306 VA.getLocMemOffset(), isImmutable);
2307 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2308 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2309 MachinePointerInfo::getFixedStack(FI),
2310 false, false, false, 0);
2311 return ExtendedInMem ?
2312 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2316 // FIXME: Get this from tablegen.
2317 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2318 const X86Subtarget *Subtarget) {
2319 assert(Subtarget->is64Bit());
2321 if (Subtarget->isCallingConvWin64(CallConv)) {
2322 static const MCPhysReg GPR64ArgRegsWin64[] = {
2323 X86::RCX, X86::RDX, X86::R8, X86::R9
2325 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2328 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2329 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2331 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2334 // FIXME: Get this from tablegen.
2335 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2336 CallingConv::ID CallConv,
2337 const X86Subtarget *Subtarget) {
2338 assert(Subtarget->is64Bit());
2339 if (Subtarget->isCallingConvWin64(CallConv)) {
2340 // The XMM registers which might contain var arg parameters are shadowed
2341 // in their paired GPR. So we only need to save the GPR to their home
2343 // TODO: __vectorcall will change this.
2347 const Function *Fn = MF.getFunction();
2348 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2349 bool isSoftFloat = Subtarget->useSoftFloat();
2350 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2351 "SSE register cannot be used when SSE is disabled!");
2352 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2353 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2357 static const MCPhysReg XMMArgRegs64Bit[] = {
2358 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2359 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2361 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2365 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2366 CallingConv::ID CallConv,
2368 const SmallVectorImpl<ISD::InputArg> &Ins,
2371 SmallVectorImpl<SDValue> &InVals)
2373 MachineFunction &MF = DAG.getMachineFunction();
2374 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2375 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2377 const Function* Fn = MF.getFunction();
2378 if (Fn->hasExternalLinkage() &&
2379 Subtarget->isTargetCygMing() &&
2380 Fn->getName() == "main")
2381 FuncInfo->setForceFramePointer(true);
2383 MachineFrameInfo *MFI = MF.getFrameInfo();
2384 bool Is64Bit = Subtarget->is64Bit();
2385 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2387 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2388 "Var args not supported with calling convention fastcc, ghc or hipe");
2390 // Assign locations to all of the incoming arguments.
2391 SmallVector<CCValAssign, 16> ArgLocs;
2392 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2394 // Allocate shadow area for Win64
2396 CCInfo.AllocateStack(32, 8);
2398 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2400 unsigned LastVal = ~0U;
2402 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2403 CCValAssign &VA = ArgLocs[i];
2404 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2406 assert(VA.getValNo() != LastVal &&
2407 "Don't support value assigned to multiple locs yet");
2409 LastVal = VA.getValNo();
2411 if (VA.isRegLoc()) {
2412 EVT RegVT = VA.getLocVT();
2413 const TargetRegisterClass *RC;
2414 if (RegVT == MVT::i32)
2415 RC = &X86::GR32RegClass;
2416 else if (Is64Bit && RegVT == MVT::i64)
2417 RC = &X86::GR64RegClass;
2418 else if (RegVT == MVT::f32)
2419 RC = &X86::FR32RegClass;
2420 else if (RegVT == MVT::f64)
2421 RC = &X86::FR64RegClass;
2422 else if (RegVT.is512BitVector())
2423 RC = &X86::VR512RegClass;
2424 else if (RegVT.is256BitVector())
2425 RC = &X86::VR256RegClass;
2426 else if (RegVT.is128BitVector())
2427 RC = &X86::VR128RegClass;
2428 else if (RegVT == MVT::x86mmx)
2429 RC = &X86::VR64RegClass;
2430 else if (RegVT == MVT::i1)
2431 RC = &X86::VK1RegClass;
2432 else if (RegVT == MVT::v8i1)
2433 RC = &X86::VK8RegClass;
2434 else if (RegVT == MVT::v16i1)
2435 RC = &X86::VK16RegClass;
2436 else if (RegVT == MVT::v32i1)
2437 RC = &X86::VK32RegClass;
2438 else if (RegVT == MVT::v64i1)
2439 RC = &X86::VK64RegClass;
2441 llvm_unreachable("Unknown argument type!");
2443 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2444 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2446 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2447 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2449 if (VA.getLocInfo() == CCValAssign::SExt)
2450 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2451 DAG.getValueType(VA.getValVT()));
2452 else if (VA.getLocInfo() == CCValAssign::ZExt)
2453 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2454 DAG.getValueType(VA.getValVT()));
2455 else if (VA.getLocInfo() == CCValAssign::BCvt)
2456 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2458 if (VA.isExtInLoc()) {
2459 // Handle MMX values passed in XMM regs.
2460 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2461 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2463 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2466 assert(VA.isMemLoc());
2467 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2470 // If value is passed via pointer - do a load.
2471 if (VA.getLocInfo() == CCValAssign::Indirect)
2472 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2473 MachinePointerInfo(), false, false, false, 0);
2475 InVals.push_back(ArgValue);
2478 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2479 // All x86 ABIs require that for returning structs by value we copy the
2480 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2481 // the argument into a virtual register so that we can access it from the
2483 if (Ins[i].Flags.isSRet()) {
2484 unsigned Reg = FuncInfo->getSRetReturnReg();
2486 MVT PtrTy = getPointerTy();
2487 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2488 FuncInfo->setSRetReturnReg(Reg);
2490 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2491 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2496 unsigned StackSize = CCInfo.getNextStackOffset();
2497 // Align stack specially for tail calls.
2498 if (FuncIsMadeTailCallSafe(CallConv,
2499 MF.getTarget().Options.GuaranteedTailCallOpt))
2500 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2502 // If the function takes variable number of arguments, make a frame index for
2503 // the start of the first vararg value... for expansion of llvm.va_start. We
2504 // can skip this if there are no va_start calls.
2505 if (MFI->hasVAStart() &&
2506 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2507 CallConv != CallingConv::X86_ThisCall))) {
2508 FuncInfo->setVarArgsFrameIndex(
2509 MFI->CreateFixedObject(1, StackSize, true));
2512 MachineModuleInfo &MMI = MF.getMMI();
2513 const Function *WinEHParent = nullptr;
2514 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2515 WinEHParent = MMI.getWinEHParent(Fn);
2516 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2517 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2519 // Figure out if XMM registers are in use.
2520 assert(!(Subtarget->useSoftFloat() &&
2521 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2522 "SSE register cannot be used when SSE is disabled!");
2524 // 64-bit calling conventions support varargs and register parameters, so we
2525 // have to do extra work to spill them in the prologue.
2526 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2527 // Find the first unallocated argument registers.
2528 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2529 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2530 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2531 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2532 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2533 "SSE register cannot be used when SSE is disabled!");
2535 // Gather all the live in physical registers.
2536 SmallVector<SDValue, 6> LiveGPRs;
2537 SmallVector<SDValue, 8> LiveXMMRegs;
2539 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2540 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2542 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2544 if (!ArgXMMs.empty()) {
2545 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2546 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2547 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2548 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2549 LiveXMMRegs.push_back(
2550 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2555 // Get to the caller-allocated home save location. Add 8 to account
2556 // for the return address.
2557 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2558 FuncInfo->setRegSaveFrameIndex(
2559 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2560 // Fixup to set vararg frame on shadow area (4 x i64).
2562 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2564 // For X86-64, if there are vararg parameters that are passed via
2565 // registers, then we must store them to their spots on the stack so
2566 // they may be loaded by deferencing the result of va_next.
2567 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2568 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2569 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2570 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2573 // Store the integer parameter registers.
2574 SmallVector<SDValue, 8> MemOps;
2575 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2577 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2578 for (SDValue Val : LiveGPRs) {
2579 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2580 DAG.getIntPtrConstant(Offset, dl));
2582 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2583 MachinePointerInfo::getFixedStack(
2584 FuncInfo->getRegSaveFrameIndex(), Offset),
2586 MemOps.push_back(Store);
2590 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2591 // Now store the XMM (fp + vector) parameter registers.
2592 SmallVector<SDValue, 12> SaveXMMOps;
2593 SaveXMMOps.push_back(Chain);
2594 SaveXMMOps.push_back(ALVal);
2595 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2596 FuncInfo->getRegSaveFrameIndex(), dl));
2597 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2598 FuncInfo->getVarArgsFPOffset(), dl));
2599 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2601 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2602 MVT::Other, SaveXMMOps));
2605 if (!MemOps.empty())
2606 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2607 } else if (IsWinEHOutlined) {
2608 // Get to the caller-allocated home save location. Add 8 to account
2609 // for the return address.
2610 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2611 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2612 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2614 MMI.getWinEHFuncInfo(Fn)
2615 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2616 FuncInfo->getRegSaveFrameIndex();
2618 // Store the second integer parameter (rdx) into rsp+16 relative to the
2619 // stack pointer at the entry of the function.
2621 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2622 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2623 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2624 Chain = DAG.getStore(
2625 Val.getValue(1), dl, Val, RSFIN,
2626 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2627 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2630 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2631 // Find the largest legal vector type.
2632 MVT VecVT = MVT::Other;
2633 // FIXME: Only some x86_32 calling conventions support AVX512.
2634 if (Subtarget->hasAVX512() &&
2635 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2636 CallConv == CallingConv::Intel_OCL_BI)))
2637 VecVT = MVT::v16f32;
2638 else if (Subtarget->hasAVX())
2640 else if (Subtarget->hasSSE2())
2643 // We forward some GPRs and some vector types.
2644 SmallVector<MVT, 2> RegParmTypes;
2645 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2646 RegParmTypes.push_back(IntVT);
2647 if (VecVT != MVT::Other)
2648 RegParmTypes.push_back(VecVT);
2650 // Compute the set of forwarded registers. The rest are scratch.
2651 SmallVectorImpl<ForwardedRegister> &Forwards =
2652 FuncInfo->getForwardedMustTailRegParms();
2653 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2655 // Conservatively forward AL on x86_64, since it might be used for varargs.
2656 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2657 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2658 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2661 // Copy all forwards from physical to virtual registers.
2662 for (ForwardedRegister &F : Forwards) {
2663 // FIXME: Can we use a less constrained schedule?
2664 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2665 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2666 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2670 // Some CCs need callee pop.
2671 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2672 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2673 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2675 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2676 // If this is an sret function, the return should pop the hidden pointer.
2677 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2678 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2679 argsAreStructReturn(Ins) == StackStructReturn)
2680 FuncInfo->setBytesToPopOnReturn(4);
2684 // RegSaveFrameIndex is X86-64 only.
2685 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2686 if (CallConv == CallingConv::X86_FastCall ||
2687 CallConv == CallingConv::X86_ThisCall)
2688 // fastcc functions can't have varargs.
2689 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2692 FuncInfo->setArgumentStackSize(StackSize);
2694 if (IsWinEHParent) {
2695 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2696 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2697 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2698 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2699 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2700 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2701 /*isVolatile=*/true,
2702 /*isNonTemporal=*/false, /*Alignment=*/0);
2709 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2710 SDValue StackPtr, SDValue Arg,
2711 SDLoc dl, SelectionDAG &DAG,
2712 const CCValAssign &VA,
2713 ISD::ArgFlagsTy Flags) const {
2714 unsigned LocMemOffset = VA.getLocMemOffset();
2715 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2716 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2717 if (Flags.isByVal())
2718 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2720 return DAG.getStore(Chain, dl, Arg, PtrOff,
2721 MachinePointerInfo::getStack(LocMemOffset),
2725 /// Emit a load of return address if tail call
2726 /// optimization is performed and it is required.
2728 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2729 SDValue &OutRetAddr, SDValue Chain,
2730 bool IsTailCall, bool Is64Bit,
2731 int FPDiff, SDLoc dl) const {
2732 // Adjust the Return address stack slot.
2733 EVT VT = getPointerTy();
2734 OutRetAddr = getReturnAddressFrameIndex(DAG);
2736 // Load the "old" Return address.
2737 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2738 false, false, false, 0);
2739 return SDValue(OutRetAddr.getNode(), 1);
2742 /// Emit a store of the return address if tail call
2743 /// optimization is performed and it is required (FPDiff!=0).
2744 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2745 SDValue Chain, SDValue RetAddrFrIdx,
2746 EVT PtrVT, unsigned SlotSize,
2747 int FPDiff, SDLoc dl) {
2748 // Store the return address to the appropriate stack slot.
2749 if (!FPDiff) return Chain;
2750 // Calculate the new stack slot for the return address.
2751 int NewReturnAddrFI =
2752 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2754 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2755 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2756 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2762 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2763 SmallVectorImpl<SDValue> &InVals) const {
2764 SelectionDAG &DAG = CLI.DAG;
2766 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2767 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2768 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2769 SDValue Chain = CLI.Chain;
2770 SDValue Callee = CLI.Callee;
2771 CallingConv::ID CallConv = CLI.CallConv;
2772 bool &isTailCall = CLI.IsTailCall;
2773 bool isVarArg = CLI.IsVarArg;
2775 MachineFunction &MF = DAG.getMachineFunction();
2776 bool Is64Bit = Subtarget->is64Bit();
2777 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2778 StructReturnType SR = callIsStructReturn(Outs);
2779 bool IsSibcall = false;
2780 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2782 if (MF.getTarget().Options.DisableTailCalls)
2785 if (Subtarget->isPICStyleGOT() &&
2786 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2787 // If we are using a GOT, disable tail calls to external symbols with
2788 // default visibility. Tail calling such a symbol requires using a GOT
2789 // relocation, which forces early binding of the symbol. This breaks code
2790 // that require lazy function symbol resolution. Using musttail or
2791 // GuaranteedTailCallOpt will override this.
2792 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2793 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2794 G->getGlobal()->hasDefaultVisibility()))
2798 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2800 // Force this to be a tail call. The verifier rules are enough to ensure
2801 // that we can lower this successfully without moving the return address
2804 } else if (isTailCall) {
2805 // Check if it's really possible to do a tail call.
2806 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2807 isVarArg, SR != NotStructReturn,
2808 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2809 Outs, OutVals, Ins, DAG);
2811 // Sibcalls are automatically detected tailcalls which do not require
2813 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2820 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2821 "Var args not supported with calling convention fastcc, ghc or hipe");
2823 // Analyze operands of the call, assigning locations to each operand.
2824 SmallVector<CCValAssign, 16> ArgLocs;
2825 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2827 // Allocate shadow area for Win64
2829 CCInfo.AllocateStack(32, 8);
2831 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2833 // Get a count of how many bytes are to be pushed on the stack.
2834 unsigned NumBytes = CCInfo.getNextStackOffset();
2836 // This is a sibcall. The memory operands are available in caller's
2837 // own caller's stack.
2839 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2840 IsTailCallConvention(CallConv))
2841 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2844 if (isTailCall && !IsSibcall && !IsMustTail) {
2845 // Lower arguments at fp - stackoffset + fpdiff.
2846 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2848 FPDiff = NumBytesCallerPushed - NumBytes;
2850 // Set the delta of movement of the returnaddr stackslot.
2851 // But only set if delta is greater than previous delta.
2852 if (FPDiff < X86Info->getTCReturnAddrDelta())
2853 X86Info->setTCReturnAddrDelta(FPDiff);
2856 unsigned NumBytesToPush = NumBytes;
2857 unsigned NumBytesToPop = NumBytes;
2859 // If we have an inalloca argument, all stack space has already been allocated
2860 // for us and be right at the top of the stack. We don't support multiple
2861 // arguments passed in memory when using inalloca.
2862 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2864 if (!ArgLocs.back().isMemLoc())
2865 report_fatal_error("cannot use inalloca attribute on a register "
2867 if (ArgLocs.back().getLocMemOffset() != 0)
2868 report_fatal_error("any parameter with the inalloca attribute must be "
2869 "the only memory argument");
2873 Chain = DAG.getCALLSEQ_START(
2874 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2876 SDValue RetAddrFrIdx;
2877 // Load return address for tail calls.
2878 if (isTailCall && FPDiff)
2879 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2880 Is64Bit, FPDiff, dl);
2882 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2883 SmallVector<SDValue, 8> MemOpChains;
2886 // Walk the register/memloc assignments, inserting copies/loads. In the case
2887 // of tail call optimization arguments are handle later.
2888 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2889 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2890 // Skip inalloca arguments, they have already been written.
2891 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2892 if (Flags.isInAlloca())
2895 CCValAssign &VA = ArgLocs[i];
2896 EVT RegVT = VA.getLocVT();
2897 SDValue Arg = OutVals[i];
2898 bool isByVal = Flags.isByVal();
2900 // Promote the value if needed.
2901 switch (VA.getLocInfo()) {
2902 default: llvm_unreachable("Unknown loc info!");
2903 case CCValAssign::Full: break;
2904 case CCValAssign::SExt:
2905 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2907 case CCValAssign::ZExt:
2908 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2910 case CCValAssign::AExt:
2911 if (Arg.getValueType().isVector() &&
2912 Arg.getValueType().getScalarType() == MVT::i1)
2913 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2914 else if (RegVT.is128BitVector()) {
2915 // Special case: passing MMX values in XMM registers.
2916 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2917 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2918 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2920 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2922 case CCValAssign::BCvt:
2923 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2925 case CCValAssign::Indirect: {
2926 // Store the argument.
2927 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2928 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2929 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2930 MachinePointerInfo::getFixedStack(FI),
2937 if (VA.isRegLoc()) {
2938 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2939 if (isVarArg && IsWin64) {
2940 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2941 // shadow reg if callee is a varargs function.
2942 unsigned ShadowReg = 0;
2943 switch (VA.getLocReg()) {
2944 case X86::XMM0: ShadowReg = X86::RCX; break;
2945 case X86::XMM1: ShadowReg = X86::RDX; break;
2946 case X86::XMM2: ShadowReg = X86::R8; break;
2947 case X86::XMM3: ShadowReg = X86::R9; break;
2950 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2952 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2953 assert(VA.isMemLoc());
2954 if (!StackPtr.getNode())
2955 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2957 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2958 dl, DAG, VA, Flags));
2962 if (!MemOpChains.empty())
2963 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2965 if (Subtarget->isPICStyleGOT()) {
2966 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2969 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2970 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2972 // If we are tail calling and generating PIC/GOT style code load the
2973 // address of the callee into ECX. The value in ecx is used as target of
2974 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2975 // for tail calls on PIC/GOT architectures. Normally we would just put the
2976 // address of GOT into ebx and then call target@PLT. But for tail calls
2977 // ebx would be restored (since ebx is callee saved) before jumping to the
2980 // Note: The actual moving to ECX is done further down.
2981 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2982 if (G && !G->getGlobal()->hasLocalLinkage() &&
2983 G->getGlobal()->hasDefaultVisibility())
2984 Callee = LowerGlobalAddress(Callee, DAG);
2985 else if (isa<ExternalSymbolSDNode>(Callee))
2986 Callee = LowerExternalSymbol(Callee, DAG);
2990 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2991 // From AMD64 ABI document:
2992 // For calls that may call functions that use varargs or stdargs
2993 // (prototype-less calls or calls to functions containing ellipsis (...) in
2994 // the declaration) %al is used as hidden argument to specify the number
2995 // of SSE registers used. The contents of %al do not need to match exactly
2996 // the number of registers, but must be an ubound on the number of SSE
2997 // registers used and is in the range 0 - 8 inclusive.
2999 // Count the number of XMM registers allocated.
3000 static const MCPhysReg XMMArgRegs[] = {
3001 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3002 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3004 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3005 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3006 && "SSE registers cannot be used when SSE is disabled");
3008 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3009 DAG.getConstant(NumXMMRegs, dl,
3013 if (isVarArg && IsMustTail) {
3014 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3015 for (const auto &F : Forwards) {
3016 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3017 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3021 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3022 // don't need this because the eligibility check rejects calls that require
3023 // shuffling arguments passed in memory.
3024 if (!IsSibcall && isTailCall) {
3025 // Force all the incoming stack arguments to be loaded from the stack
3026 // before any new outgoing arguments are stored to the stack, because the
3027 // outgoing stack slots may alias the incoming argument stack slots, and
3028 // the alias isn't otherwise explicit. This is slightly more conservative
3029 // than necessary, because it means that each store effectively depends
3030 // on every argument instead of just those arguments it would clobber.
3031 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3033 SmallVector<SDValue, 8> MemOpChains2;
3036 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3037 CCValAssign &VA = ArgLocs[i];
3040 assert(VA.isMemLoc());
3041 SDValue Arg = OutVals[i];
3042 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3043 // Skip inalloca arguments. They don't require any work.
3044 if (Flags.isInAlloca())
3046 // Create frame index.
3047 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3048 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3049 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3050 FIN = DAG.getFrameIndex(FI, getPointerTy());
3052 if (Flags.isByVal()) {
3053 // Copy relative to framepointer.
3054 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3055 if (!StackPtr.getNode())
3056 StackPtr = DAG.getCopyFromReg(Chain, dl,
3057 RegInfo->getStackRegister(),
3059 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3061 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3065 // Store relative to framepointer.
3066 MemOpChains2.push_back(
3067 DAG.getStore(ArgChain, dl, Arg, FIN,
3068 MachinePointerInfo::getFixedStack(FI),
3073 if (!MemOpChains2.empty())
3074 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3076 // Store the return address to the appropriate stack slot.
3077 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3078 getPointerTy(), RegInfo->getSlotSize(),
3082 // Build a sequence of copy-to-reg nodes chained together with token chain
3083 // and flag operands which copy the outgoing args into registers.
3085 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3086 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3087 RegsToPass[i].second, InFlag);
3088 InFlag = Chain.getValue(1);
3091 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3092 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3093 // In the 64-bit large code model, we have to make all calls
3094 // through a register, since the call instruction's 32-bit
3095 // pc-relative offset may not be large enough to hold the whole
3097 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3098 // If the callee is a GlobalAddress node (quite common, every direct call
3099 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3101 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3103 // We should use extra load for direct calls to dllimported functions in
3105 const GlobalValue *GV = G->getGlobal();
3106 if (!GV->hasDLLImportStorageClass()) {
3107 unsigned char OpFlags = 0;
3108 bool ExtraLoad = false;
3109 unsigned WrapperKind = ISD::DELETED_NODE;
3111 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3112 // external symbols most go through the PLT in PIC mode. If the symbol
3113 // has hidden or protected visibility, or if it is static or local, then
3114 // we don't need to use the PLT - we can directly call it.
3115 if (Subtarget->isTargetELF() &&
3116 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3117 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3118 OpFlags = X86II::MO_PLT;
3119 } else if (Subtarget->isPICStyleStubAny() &&
3120 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3121 (!Subtarget->getTargetTriple().isMacOSX() ||
3122 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3123 // PC-relative references to external symbols should go through $stub,
3124 // unless we're building with the leopard linker or later, which
3125 // automatically synthesizes these stubs.
3126 OpFlags = X86II::MO_DARWIN_STUB;
3127 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3128 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3129 // If the function is marked as non-lazy, generate an indirect call
3130 // which loads from the GOT directly. This avoids runtime overhead
3131 // at the cost of eager binding (and one extra byte of encoding).
3132 OpFlags = X86II::MO_GOTPCREL;
3133 WrapperKind = X86ISD::WrapperRIP;
3137 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3138 G->getOffset(), OpFlags);
3140 // Add a wrapper if needed.
3141 if (WrapperKind != ISD::DELETED_NODE)
3142 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3143 // Add extra indirection if needed.
3145 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3146 MachinePointerInfo::getGOT(),
3147 false, false, false, 0);
3149 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3150 unsigned char OpFlags = 0;
3152 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3153 // external symbols should go through the PLT.
3154 if (Subtarget->isTargetELF() &&
3155 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3156 OpFlags = X86II::MO_PLT;
3157 } else if (Subtarget->isPICStyleStubAny() &&
3158 (!Subtarget->getTargetTriple().isMacOSX() ||
3159 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3160 // PC-relative references to external symbols should go through $stub,
3161 // unless we're building with the leopard linker or later, which
3162 // automatically synthesizes these stubs.
3163 OpFlags = X86II::MO_DARWIN_STUB;
3166 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3168 } else if (Subtarget->isTarget64BitILP32() &&
3169 Callee->getValueType(0) == MVT::i32) {
3170 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3171 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3174 // Returns a chain & a flag for retval copy to use.
3175 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3176 SmallVector<SDValue, 8> Ops;
3178 if (!IsSibcall && isTailCall) {
3179 Chain = DAG.getCALLSEQ_END(Chain,
3180 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3181 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3182 InFlag = Chain.getValue(1);
3185 Ops.push_back(Chain);
3186 Ops.push_back(Callee);
3189 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3191 // Add argument registers to the end of the list so that they are known live
3193 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3194 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3195 RegsToPass[i].second.getValueType()));
3197 // Add a register mask operand representing the call-preserved registers.
3198 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3199 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3200 assert(Mask && "Missing call preserved mask for calling convention");
3201 Ops.push_back(DAG.getRegisterMask(Mask));
3203 if (InFlag.getNode())
3204 Ops.push_back(InFlag);
3208 //// If this is the first return lowered for this function, add the regs
3209 //// to the liveout set for the function.
3210 // This isn't right, although it's probably harmless on x86; liveouts
3211 // should be computed from returns not tail calls. Consider a void
3212 // function making a tail call to a function returning int.
3213 MF.getFrameInfo()->setHasTailCall();
3214 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3217 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3218 InFlag = Chain.getValue(1);
3220 // Create the CALLSEQ_END node.
3221 unsigned NumBytesForCalleeToPop;
3222 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3223 DAG.getTarget().Options.GuaranteedTailCallOpt))
3224 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3225 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3226 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3227 SR == StackStructReturn)
3228 // If this is a call to a struct-return function, the callee
3229 // pops the hidden struct pointer, so we have to push it back.
3230 // This is common for Darwin/X86, Linux & Mingw32 targets.
3231 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3232 NumBytesForCalleeToPop = 4;
3234 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3236 // Returns a flag for retval copy to use.
3238 Chain = DAG.getCALLSEQ_END(Chain,
3239 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3240 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3243 InFlag = Chain.getValue(1);
3246 // Handle result values, copying them out of physregs into vregs that we
3248 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3249 Ins, dl, DAG, InVals);
3252 //===----------------------------------------------------------------------===//
3253 // Fast Calling Convention (tail call) implementation
3254 //===----------------------------------------------------------------------===//
3256 // Like std call, callee cleans arguments, convention except that ECX is
3257 // reserved for storing the tail called function address. Only 2 registers are
3258 // free for argument passing (inreg). Tail call optimization is performed
3260 // * tailcallopt is enabled
3261 // * caller/callee are fastcc
3262 // On X86_64 architecture with GOT-style position independent code only local
3263 // (within module) calls are supported at the moment.
3264 // To keep the stack aligned according to platform abi the function
3265 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3266 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3267 // If a tail called function callee has more arguments than the caller the
3268 // caller needs to make sure that there is room to move the RETADDR to. This is
3269 // achieved by reserving an area the size of the argument delta right after the
3270 // original RETADDR, but before the saved framepointer or the spilled registers
3271 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3283 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3284 /// for a 16 byte align requirement.
3286 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3287 SelectionDAG& DAG) const {
3288 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3289 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3290 unsigned StackAlignment = TFI.getStackAlignment();
3291 uint64_t AlignMask = StackAlignment - 1;
3292 int64_t Offset = StackSize;
3293 unsigned SlotSize = RegInfo->getSlotSize();
3294 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3295 // Number smaller than 12 so just add the difference.
3296 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3298 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3299 Offset = ((~AlignMask) & Offset) + StackAlignment +
3300 (StackAlignment-SlotSize);
3305 /// MatchingStackOffset - Return true if the given stack call argument is
3306 /// already available in the same position (relatively) of the caller's
3307 /// incoming argument stack.
3309 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3310 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3311 const X86InstrInfo *TII) {
3312 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3314 if (Arg.getOpcode() == ISD::CopyFromReg) {
3315 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3316 if (!TargetRegisterInfo::isVirtualRegister(VR))
3318 MachineInstr *Def = MRI->getVRegDef(VR);
3321 if (!Flags.isByVal()) {
3322 if (!TII->isLoadFromStackSlot(Def, FI))
3325 unsigned Opcode = Def->getOpcode();
3326 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3327 Opcode == X86::LEA64_32r) &&
3328 Def->getOperand(1).isFI()) {
3329 FI = Def->getOperand(1).getIndex();
3330 Bytes = Flags.getByValSize();
3334 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3335 if (Flags.isByVal())
3336 // ByVal argument is passed in as a pointer but it's now being
3337 // dereferenced. e.g.
3338 // define @foo(%struct.X* %A) {
3339 // tail call @bar(%struct.X* byval %A)
3342 SDValue Ptr = Ld->getBasePtr();
3343 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3346 FI = FINode->getIndex();
3347 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3348 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3349 FI = FINode->getIndex();
3350 Bytes = Flags.getByValSize();
3354 assert(FI != INT_MAX);
3355 if (!MFI->isFixedObjectIndex(FI))
3357 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3360 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3361 /// for tail call optimization. Targets which want to do tail call
3362 /// optimization should implement this function.
3364 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3365 CallingConv::ID CalleeCC,
3367 bool isCalleeStructRet,
3368 bool isCallerStructRet,
3370 const SmallVectorImpl<ISD::OutputArg> &Outs,
3371 const SmallVectorImpl<SDValue> &OutVals,
3372 const SmallVectorImpl<ISD::InputArg> &Ins,
3373 SelectionDAG &DAG) const {
3374 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3377 // If -tailcallopt is specified, make fastcc functions tail-callable.
3378 const MachineFunction &MF = DAG.getMachineFunction();
3379 const Function *CallerF = MF.getFunction();
3381 // If the function return type is x86_fp80 and the callee return type is not,
3382 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3383 // perform a tailcall optimization here.
3384 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3387 CallingConv::ID CallerCC = CallerF->getCallingConv();
3388 bool CCMatch = CallerCC == CalleeCC;
3389 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3390 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3392 // Win64 functions have extra shadow space for argument homing. Don't do the
3393 // sibcall if the caller and callee have mismatched expectations for this
3395 if (IsCalleeWin64 != IsCallerWin64)
3398 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3399 if (IsTailCallConvention(CalleeCC) && CCMatch)
3404 // Look for obvious safe cases to perform tail call optimization that do not
3405 // require ABI changes. This is what gcc calls sibcall.
3407 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3408 // emit a special epilogue.
3409 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3410 if (RegInfo->needsStackRealignment(MF))
3413 // Also avoid sibcall optimization if either caller or callee uses struct
3414 // return semantics.
3415 if (isCalleeStructRet || isCallerStructRet)
3418 // An stdcall/thiscall caller is expected to clean up its arguments; the
3419 // callee isn't going to do that.
3420 // FIXME: this is more restrictive than needed. We could produce a tailcall
3421 // when the stack adjustment matches. For example, with a thiscall that takes
3422 // only one argument.
3423 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3424 CallerCC == CallingConv::X86_ThisCall))
3427 // Do not sibcall optimize vararg calls unless all arguments are passed via
3429 if (isVarArg && !Outs.empty()) {
3431 // Optimizing for varargs on Win64 is unlikely to be safe without
3432 // additional testing.
3433 if (IsCalleeWin64 || IsCallerWin64)
3436 SmallVector<CCValAssign, 16> ArgLocs;
3437 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3440 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3441 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3442 if (!ArgLocs[i].isRegLoc())
3446 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3447 // stack. Therefore, if it's not used by the call it is not safe to optimize
3448 // this into a sibcall.
3449 bool Unused = false;
3450 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3457 SmallVector<CCValAssign, 16> RVLocs;
3458 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3460 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3461 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3462 CCValAssign &VA = RVLocs[i];
3463 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3468 // If the calling conventions do not match, then we'd better make sure the
3469 // results are returned in the same way as what the caller expects.
3471 SmallVector<CCValAssign, 16> RVLocs1;
3472 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3474 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3476 SmallVector<CCValAssign, 16> RVLocs2;
3477 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3479 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3481 if (RVLocs1.size() != RVLocs2.size())
3483 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3484 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3486 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3488 if (RVLocs1[i].isRegLoc()) {
3489 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3492 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3498 // If the callee takes no arguments then go on to check the results of the
3500 if (!Outs.empty()) {
3501 // Check if stack adjustment is needed. For now, do not do this if any
3502 // argument is passed on the stack.
3503 SmallVector<CCValAssign, 16> ArgLocs;
3504 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3507 // Allocate shadow area for Win64
3509 CCInfo.AllocateStack(32, 8);
3511 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3512 if (CCInfo.getNextStackOffset()) {
3513 MachineFunction &MF = DAG.getMachineFunction();
3514 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3517 // Check if the arguments are already laid out in the right way as
3518 // the caller's fixed stack objects.
3519 MachineFrameInfo *MFI = MF.getFrameInfo();
3520 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3521 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3522 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3523 CCValAssign &VA = ArgLocs[i];
3524 SDValue Arg = OutVals[i];
3525 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3526 if (VA.getLocInfo() == CCValAssign::Indirect)
3528 if (!VA.isRegLoc()) {
3529 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3536 // If the tailcall address may be in a register, then make sure it's
3537 // possible to register allocate for it. In 32-bit, the call address can
3538 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3539 // callee-saved registers are restored. These happen to be the same
3540 // registers used to pass 'inreg' arguments so watch out for those.
3541 if (!Subtarget->is64Bit() &&
3542 ((!isa<GlobalAddressSDNode>(Callee) &&
3543 !isa<ExternalSymbolSDNode>(Callee)) ||
3544 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3545 unsigned NumInRegs = 0;
3546 // In PIC we need an extra register to formulate the address computation
3548 unsigned MaxInRegs =
3549 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3551 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3552 CCValAssign &VA = ArgLocs[i];
3555 unsigned Reg = VA.getLocReg();
3558 case X86::EAX: case X86::EDX: case X86::ECX:
3559 if (++NumInRegs == MaxInRegs)
3571 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3572 const TargetLibraryInfo *libInfo) const {
3573 return X86::createFastISel(funcInfo, libInfo);
3576 //===----------------------------------------------------------------------===//
3577 // Other Lowering Hooks
3578 //===----------------------------------------------------------------------===//
3580 static bool MayFoldLoad(SDValue Op) {
3581 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3584 static bool MayFoldIntoStore(SDValue Op) {
3585 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3588 static bool isTargetShuffle(unsigned Opcode) {
3590 default: return false;
3591 case X86ISD::BLENDI:
3592 case X86ISD::PSHUFB:
3593 case X86ISD::PSHUFD:
3594 case X86ISD::PSHUFHW:
3595 case X86ISD::PSHUFLW:
3597 case X86ISD::PALIGNR:
3598 case X86ISD::MOVLHPS:
3599 case X86ISD::MOVLHPD:
3600 case X86ISD::MOVHLPS:
3601 case X86ISD::MOVLPS:
3602 case X86ISD::MOVLPD:
3603 case X86ISD::MOVSHDUP:
3604 case X86ISD::MOVSLDUP:
3605 case X86ISD::MOVDDUP:
3608 case X86ISD::UNPCKL:
3609 case X86ISD::UNPCKH:
3610 case X86ISD::VPERMILPI:
3611 case X86ISD::VPERM2X128:
3612 case X86ISD::VPERMI:
3617 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3618 SDValue V1, unsigned TargetMask,
3619 SelectionDAG &DAG) {
3621 default: llvm_unreachable("Unknown x86 shuffle node");
3622 case X86ISD::PSHUFD:
3623 case X86ISD::PSHUFHW:
3624 case X86ISD::PSHUFLW:
3625 case X86ISD::VPERMILPI:
3626 case X86ISD::VPERMI:
3627 return DAG.getNode(Opc, dl, VT, V1,
3628 DAG.getConstant(TargetMask, dl, MVT::i8));
3632 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3633 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3635 default: llvm_unreachable("Unknown x86 shuffle node");
3636 case X86ISD::MOVLHPS:
3637 case X86ISD::MOVLHPD:
3638 case X86ISD::MOVHLPS:
3639 case X86ISD::MOVLPS:
3640 case X86ISD::MOVLPD:
3643 case X86ISD::UNPCKL:
3644 case X86ISD::UNPCKH:
3645 return DAG.getNode(Opc, dl, VT, V1, V2);
3649 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3650 MachineFunction &MF = DAG.getMachineFunction();
3651 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3652 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3653 int ReturnAddrIndex = FuncInfo->getRAIndex();
3655 if (ReturnAddrIndex == 0) {
3656 // Set up a frame object for the return address.
3657 unsigned SlotSize = RegInfo->getSlotSize();
3658 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3661 FuncInfo->setRAIndex(ReturnAddrIndex);
3664 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3667 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3668 bool hasSymbolicDisplacement) {
3669 // Offset should fit into 32 bit immediate field.
3670 if (!isInt<32>(Offset))
3673 // If we don't have a symbolic displacement - we don't have any extra
3675 if (!hasSymbolicDisplacement)
3678 // FIXME: Some tweaks might be needed for medium code model.
3679 if (M != CodeModel::Small && M != CodeModel::Kernel)
3682 // For small code model we assume that latest object is 16MB before end of 31
3683 // bits boundary. We may also accept pretty large negative constants knowing
3684 // that all objects are in the positive half of address space.
3685 if (M == CodeModel::Small && Offset < 16*1024*1024)
3688 // For kernel code model we know that all object resist in the negative half
3689 // of 32bits address space. We may not accept negative offsets, since they may
3690 // be just off and we may accept pretty large positive ones.
3691 if (M == CodeModel::Kernel && Offset >= 0)
3697 /// isCalleePop - Determines whether the callee is required to pop its
3698 /// own arguments. Callee pop is necessary to support tail calls.
3699 bool X86::isCalleePop(CallingConv::ID CallingConv,
3700 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3701 switch (CallingConv) {
3704 case CallingConv::X86_StdCall:
3705 case CallingConv::X86_FastCall:
3706 case CallingConv::X86_ThisCall:
3708 case CallingConv::Fast:
3709 case CallingConv::GHC:
3710 case CallingConv::HiPE:
3717 /// \brief Return true if the condition is an unsigned comparison operation.
3718 static bool isX86CCUnsigned(unsigned X86CC) {
3720 default: llvm_unreachable("Invalid integer condition!");
3721 case X86::COND_E: return true;
3722 case X86::COND_G: return false;
3723 case X86::COND_GE: return false;
3724 case X86::COND_L: return false;
3725 case X86::COND_LE: return false;
3726 case X86::COND_NE: return true;
3727 case X86::COND_B: return true;
3728 case X86::COND_A: return true;
3729 case X86::COND_BE: return true;
3730 case X86::COND_AE: return true;
3732 llvm_unreachable("covered switch fell through?!");
3735 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3736 /// specific condition code, returning the condition code and the LHS/RHS of the
3737 /// comparison to make.
3738 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3739 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3741 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3742 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3743 // X > -1 -> X == 0, jump !sign.
3744 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3745 return X86::COND_NS;
3747 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3748 // X < 0 -> X == 0, jump on sign.
3751 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3753 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3754 return X86::COND_LE;
3758 switch (SetCCOpcode) {
3759 default: llvm_unreachable("Invalid integer condition!");
3760 case ISD::SETEQ: return X86::COND_E;
3761 case ISD::SETGT: return X86::COND_G;
3762 case ISD::SETGE: return X86::COND_GE;
3763 case ISD::SETLT: return X86::COND_L;
3764 case ISD::SETLE: return X86::COND_LE;
3765 case ISD::SETNE: return X86::COND_NE;
3766 case ISD::SETULT: return X86::COND_B;
3767 case ISD::SETUGT: return X86::COND_A;
3768 case ISD::SETULE: return X86::COND_BE;
3769 case ISD::SETUGE: return X86::COND_AE;
3773 // First determine if it is required or is profitable to flip the operands.
3775 // If LHS is a foldable load, but RHS is not, flip the condition.
3776 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3777 !ISD::isNON_EXTLoad(RHS.getNode())) {
3778 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3779 std::swap(LHS, RHS);
3782 switch (SetCCOpcode) {
3788 std::swap(LHS, RHS);
3792 // On a floating point condition, the flags are set as follows:
3794 // 0 | 0 | 0 | X > Y
3795 // 0 | 0 | 1 | X < Y
3796 // 1 | 0 | 0 | X == Y
3797 // 1 | 1 | 1 | unordered
3798 switch (SetCCOpcode) {
3799 default: llvm_unreachable("Condcode should be pre-legalized away");
3801 case ISD::SETEQ: return X86::COND_E;
3802 case ISD::SETOLT: // flipped
3804 case ISD::SETGT: return X86::COND_A;
3805 case ISD::SETOLE: // flipped
3807 case ISD::SETGE: return X86::COND_AE;
3808 case ISD::SETUGT: // flipped
3810 case ISD::SETLT: return X86::COND_B;
3811 case ISD::SETUGE: // flipped
3813 case ISD::SETLE: return X86::COND_BE;
3815 case ISD::SETNE: return X86::COND_NE;
3816 case ISD::SETUO: return X86::COND_P;
3817 case ISD::SETO: return X86::COND_NP;
3819 case ISD::SETUNE: return X86::COND_INVALID;
3823 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3824 /// code. Current x86 isa includes the following FP cmov instructions:
3825 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3826 static bool hasFPCMov(unsigned X86CC) {
3842 /// isFPImmLegal - Returns true if the target can instruction select the
3843 /// specified FP immediate natively. If false, the legalizer will
3844 /// materialize the FP immediate as a load from a constant pool.
3845 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3846 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3847 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3853 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3854 ISD::LoadExtType ExtTy,
3856 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3857 // relocation target a movq or addq instruction: don't let the load shrink.
3858 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3859 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3860 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3861 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3865 /// \brief Returns true if it is beneficial to convert a load of a constant
3866 /// to just the constant itself.
3867 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3869 assert(Ty->isIntegerTy());
3871 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3872 if (BitSize == 0 || BitSize > 64)
3877 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3878 unsigned Index) const {
3879 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3882 return (Index == 0 || Index == ResVT.getVectorNumElements());
3885 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3886 // Speculate cttz only if we can directly use TZCNT.
3887 return Subtarget->hasBMI();
3890 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3891 // Speculate ctlz only if we can directly use LZCNT.
3892 return Subtarget->hasLZCNT();
3895 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3896 /// the specified range (L, H].
3897 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3898 return (Val < 0) || (Val >= Low && Val < Hi);
3901 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3902 /// specified value.
3903 static bool isUndefOrEqual(int Val, int CmpVal) {
3904 return (Val < 0 || Val == CmpVal);
3907 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3908 /// from position Pos and ending in Pos+Size, falls within the specified
3909 /// sequential range (Low, Low+Size]. or is undef.
3910 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3911 unsigned Pos, unsigned Size, int Low) {
3912 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3913 if (!isUndefOrEqual(Mask[i], Low))
3918 /// isVEXTRACTIndex - Return true if the specified
3919 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3920 /// suitable for instruction that extract 128 or 256 bit vectors
3921 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3922 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3923 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3926 // The index should be aligned on a vecWidth-bit boundary.
3928 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3930 MVT VT = N->getSimpleValueType(0);
3931 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3932 bool Result = (Index * ElSize) % vecWidth == 0;
3937 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3938 /// operand specifies a subvector insert that is suitable for input to
3939 /// insertion of 128 or 256-bit subvectors
3940 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3941 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3942 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3944 // The index should be aligned on a vecWidth-bit boundary.
3946 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3948 MVT VT = N->getSimpleValueType(0);
3949 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3950 bool Result = (Index * ElSize) % vecWidth == 0;
3955 bool X86::isVINSERT128Index(SDNode *N) {
3956 return isVINSERTIndex(N, 128);
3959 bool X86::isVINSERT256Index(SDNode *N) {
3960 return isVINSERTIndex(N, 256);
3963 bool X86::isVEXTRACT128Index(SDNode *N) {
3964 return isVEXTRACTIndex(N, 128);
3967 bool X86::isVEXTRACT256Index(SDNode *N) {
3968 return isVEXTRACTIndex(N, 256);
3971 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3972 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3973 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3974 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3977 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3979 MVT VecVT = N->getOperand(0).getSimpleValueType();
3980 MVT ElVT = VecVT.getVectorElementType();
3982 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3983 return Index / NumElemsPerChunk;
3986 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3987 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3988 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3989 llvm_unreachable("Illegal insert subvector for VINSERT");
3992 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3994 MVT VecVT = N->getSimpleValueType(0);
3995 MVT ElVT = VecVT.getVectorElementType();
3997 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3998 return Index / NumElemsPerChunk;
4001 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4002 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4003 /// and VINSERTI128 instructions.
4004 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4005 return getExtractVEXTRACTImmediate(N, 128);
4008 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4009 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4010 /// and VINSERTI64x4 instructions.
4011 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4012 return getExtractVEXTRACTImmediate(N, 256);
4015 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4016 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4017 /// and VINSERTI128 instructions.
4018 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4019 return getInsertVINSERTImmediate(N, 128);
4022 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4023 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4024 /// and VINSERTI64x4 instructions.
4025 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4026 return getInsertVINSERTImmediate(N, 256);
4029 /// isZero - Returns true if Elt is a constant integer zero
4030 static bool isZero(SDValue V) {
4031 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4032 return C && C->isNullValue();
4035 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4037 bool X86::isZeroNode(SDValue Elt) {
4040 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4041 return CFP->getValueAPF().isPosZero();
4045 /// getZeroVector - Returns a vector of specified type with all zero elements.
4047 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4048 SelectionDAG &DAG, SDLoc dl) {
4049 assert(VT.isVector() && "Expected a vector type");
4051 // Always build SSE zero vectors as <4 x i32> bitcasted
4052 // to their dest type. This ensures they get CSE'd.
4054 if (VT.is128BitVector()) { // SSE
4055 if (Subtarget->hasSSE2()) { // SSE2
4056 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4057 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4059 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4060 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4062 } else if (VT.is256BitVector()) { // AVX
4063 if (Subtarget->hasInt256()) { // AVX2
4064 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4065 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4066 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4068 // 256-bit logic and arithmetic instructions in AVX are all
4069 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4070 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4071 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4074 } else if (VT.is512BitVector()) { // AVX-512
4075 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4077 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4079 } else if (VT.getScalarType() == MVT::i1) {
4081 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4082 && "Unexpected vector type");
4083 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4084 && "Unexpected vector type");
4085 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4086 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4087 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4089 llvm_unreachable("Unexpected vector type");
4091 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4094 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4095 SelectionDAG &DAG, SDLoc dl,
4096 unsigned vectorWidth) {
4097 assert((vectorWidth == 128 || vectorWidth == 256) &&
4098 "Unsupported vector width");
4099 EVT VT = Vec.getValueType();
4100 EVT ElVT = VT.getVectorElementType();
4101 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4102 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4103 VT.getVectorNumElements()/Factor);
4105 // Extract from UNDEF is UNDEF.
4106 if (Vec.getOpcode() == ISD::UNDEF)
4107 return DAG.getUNDEF(ResultVT);
4109 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4110 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4112 // This is the index of the first element of the vectorWidth-bit chunk
4114 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4117 // If the input is a buildvector just emit a smaller one.
4118 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4119 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4120 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4123 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4124 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4127 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4128 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4129 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4130 /// instructions or a simple subregister reference. Idx is an index in the
4131 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4132 /// lowering EXTRACT_VECTOR_ELT operations easier.
4133 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4134 SelectionDAG &DAG, SDLoc dl) {
4135 assert((Vec.getValueType().is256BitVector() ||
4136 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4140 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4141 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4142 SelectionDAG &DAG, SDLoc dl) {
4143 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4144 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4147 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4148 unsigned IdxVal, SelectionDAG &DAG,
4149 SDLoc dl, unsigned vectorWidth) {
4150 assert((vectorWidth == 128 || vectorWidth == 256) &&
4151 "Unsupported vector width");
4152 // Inserting UNDEF is Result
4153 if (Vec.getOpcode() == ISD::UNDEF)
4155 EVT VT = Vec.getValueType();
4156 EVT ElVT = VT.getVectorElementType();
4157 EVT ResultVT = Result.getValueType();
4159 // Insert the relevant vectorWidth bits.
4160 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4162 // This is the index of the first element of the vectorWidth-bit chunk
4164 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4167 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4168 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4171 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4172 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4173 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4174 /// simple superregister reference. Idx is an index in the 128 bits
4175 /// we want. It need not be aligned to a 128-bit boundary. That makes
4176 /// lowering INSERT_VECTOR_ELT operations easier.
4177 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4178 SelectionDAG &DAG, SDLoc dl) {
4179 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4181 // For insertion into the zero index (low half) of a 256-bit vector, it is
4182 // more efficient to generate a blend with immediate instead of an insert*128.
4183 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4184 // extend the subvector to the size of the result vector. Make sure that
4185 // we are not recursing on that node by checking for undef here.
4186 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4187 Result.getOpcode() != ISD::UNDEF) {
4188 EVT ResultVT = Result.getValueType();
4189 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4190 SDValue Undef = DAG.getUNDEF(ResultVT);
4191 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4194 // The blend instruction, and therefore its mask, depend on the data type.
4195 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4196 if (ScalarType.isFloatingPoint()) {
4197 // Choose either vblendps (float) or vblendpd (double).
4198 unsigned ScalarSize = ScalarType.getSizeInBits();
4199 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4200 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4201 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4202 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4205 const X86Subtarget &Subtarget =
4206 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4208 // AVX2 is needed for 256-bit integer blend support.
4209 // Integers must be cast to 32-bit because there is only vpblendd;
4210 // vpblendw can't be used for this because it has a handicapped mask.
4212 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4213 // is still more efficient than using the wrong domain vinsertf128 that
4214 // will be created by InsertSubVector().
4215 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4217 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4218 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4219 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4220 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4223 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4226 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4227 SelectionDAG &DAG, SDLoc dl) {
4228 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4229 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4232 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4233 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4234 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4235 /// large BUILD_VECTORS.
4236 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4237 unsigned NumElems, SelectionDAG &DAG,
4239 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4240 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4243 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4244 unsigned NumElems, SelectionDAG &DAG,
4246 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4247 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4250 /// getOnesVector - Returns a vector of specified type with all bits set.
4251 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4252 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4253 /// Then bitcast to their original type, ensuring they get CSE'd.
4254 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4256 assert(VT.isVector() && "Expected a vector type");
4258 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4260 if (VT.is256BitVector()) {
4261 if (HasInt256) { // AVX2
4262 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4263 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4265 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4266 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4268 } else if (VT.is128BitVector()) {
4269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4271 llvm_unreachable("Unexpected vector type");
4273 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4276 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4277 /// operation of specified width.
4278 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4280 unsigned NumElems = VT.getVectorNumElements();
4281 SmallVector<int, 8> Mask;
4282 Mask.push_back(NumElems);
4283 for (unsigned i = 1; i != NumElems; ++i)
4285 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4288 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4289 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4291 unsigned NumElems = VT.getVectorNumElements();
4292 SmallVector<int, 8> Mask;
4293 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4295 Mask.push_back(i + NumElems);
4297 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4300 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4301 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4303 unsigned NumElems = VT.getVectorNumElements();
4304 SmallVector<int, 8> Mask;
4305 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4306 Mask.push_back(i + Half);
4307 Mask.push_back(i + NumElems + Half);
4309 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4312 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4313 /// vector of zero or undef vector. This produces a shuffle where the low
4314 /// element of V2 is swizzled into the zero/undef vector, landing at element
4315 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4316 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4318 const X86Subtarget *Subtarget,
4319 SelectionDAG &DAG) {
4320 MVT VT = V2.getSimpleValueType();
4322 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4323 unsigned NumElems = VT.getVectorNumElements();
4324 SmallVector<int, 16> MaskVec;
4325 for (unsigned i = 0; i != NumElems; ++i)
4326 // If this is the insertion idx, put the low elt of V2 here.
4327 MaskVec.push_back(i == Idx ? NumElems : i);
4328 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4331 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4332 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4333 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4334 /// shuffles which use a single input multiple times, and in those cases it will
4335 /// adjust the mask to only have indices within that single input.
4336 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4337 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4338 unsigned NumElems = VT.getVectorNumElements();
4342 bool IsFakeUnary = false;
4343 switch(N->getOpcode()) {
4344 case X86ISD::BLENDI:
4345 ImmN = N->getOperand(N->getNumOperands()-1);
4346 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4349 ImmN = N->getOperand(N->getNumOperands()-1);
4350 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4351 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4353 case X86ISD::UNPCKH:
4354 DecodeUNPCKHMask(VT, Mask);
4355 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4357 case X86ISD::UNPCKL:
4358 DecodeUNPCKLMask(VT, Mask);
4359 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4361 case X86ISD::MOVHLPS:
4362 DecodeMOVHLPSMask(NumElems, Mask);
4363 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4365 case X86ISD::MOVLHPS:
4366 DecodeMOVLHPSMask(NumElems, Mask);
4367 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4369 case X86ISD::PALIGNR:
4370 ImmN = N->getOperand(N->getNumOperands()-1);
4371 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4373 case X86ISD::PSHUFD:
4374 case X86ISD::VPERMILPI:
4375 ImmN = N->getOperand(N->getNumOperands()-1);
4376 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4379 case X86ISD::PSHUFHW:
4380 ImmN = N->getOperand(N->getNumOperands()-1);
4381 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4384 case X86ISD::PSHUFLW:
4385 ImmN = N->getOperand(N->getNumOperands()-1);
4386 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4389 case X86ISD::PSHUFB: {
4391 SDValue MaskNode = N->getOperand(1);
4392 while (MaskNode->getOpcode() == ISD::BITCAST)
4393 MaskNode = MaskNode->getOperand(0);
4395 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4396 // If we have a build-vector, then things are easy.
4397 EVT VT = MaskNode.getValueType();
4398 assert(VT.isVector() &&
4399 "Can't produce a non-vector with a build_vector!");
4400 if (!VT.isInteger())
4403 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4405 SmallVector<uint64_t, 32> RawMask;
4406 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4407 SDValue Op = MaskNode->getOperand(i);
4408 if (Op->getOpcode() == ISD::UNDEF) {
4409 RawMask.push_back((uint64_t)SM_SentinelUndef);
4412 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4415 APInt MaskElement = CN->getAPIntValue();
4417 // We now have to decode the element which could be any integer size and
4418 // extract each byte of it.
4419 for (int j = 0; j < NumBytesPerElement; ++j) {
4420 // Note that this is x86 and so always little endian: the low byte is
4421 // the first byte of the mask.
4422 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4423 MaskElement = MaskElement.lshr(8);
4426 DecodePSHUFBMask(RawMask, Mask);
4430 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4434 SDValue Ptr = MaskLoad->getBasePtr();
4435 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4436 Ptr->getOpcode() == X86ISD::WrapperRIP)
4437 Ptr = Ptr->getOperand(0);
4439 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4440 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4443 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4444 DecodePSHUFBMask(C, Mask);
4452 case X86ISD::VPERMI:
4453 ImmN = N->getOperand(N->getNumOperands()-1);
4454 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4459 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4461 case X86ISD::VPERM2X128:
4462 ImmN = N->getOperand(N->getNumOperands()-1);
4463 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4464 if (Mask.empty()) return false;
4466 case X86ISD::MOVSLDUP:
4467 DecodeMOVSLDUPMask(VT, Mask);
4470 case X86ISD::MOVSHDUP:
4471 DecodeMOVSHDUPMask(VT, Mask);
4474 case X86ISD::MOVDDUP:
4475 DecodeMOVDDUPMask(VT, Mask);
4478 case X86ISD::MOVLHPD:
4479 case X86ISD::MOVLPD:
4480 case X86ISD::MOVLPS:
4481 // Not yet implemented
4483 default: llvm_unreachable("unknown target shuffle node");
4486 // If we have a fake unary shuffle, the shuffle mask is spread across two
4487 // inputs that are actually the same node. Re-map the mask to always point
4488 // into the first input.
4491 if (M >= (int)Mask.size())
4497 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4498 /// element of the result of the vector shuffle.
4499 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4502 return SDValue(); // Limit search depth.
4504 SDValue V = SDValue(N, 0);
4505 EVT VT = V.getValueType();
4506 unsigned Opcode = V.getOpcode();
4508 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4509 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4510 int Elt = SV->getMaskElt(Index);
4513 return DAG.getUNDEF(VT.getVectorElementType());
4515 unsigned NumElems = VT.getVectorNumElements();
4516 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4517 : SV->getOperand(1);
4518 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4521 // Recurse into target specific vector shuffles to find scalars.
4522 if (isTargetShuffle(Opcode)) {
4523 MVT ShufVT = V.getSimpleValueType();
4524 unsigned NumElems = ShufVT.getVectorNumElements();
4525 SmallVector<int, 16> ShuffleMask;
4528 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4531 int Elt = ShuffleMask[Index];
4533 return DAG.getUNDEF(ShufVT.getVectorElementType());
4535 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4537 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4541 // Actual nodes that may contain scalar elements
4542 if (Opcode == ISD::BITCAST) {
4543 V = V.getOperand(0);
4544 EVT SrcVT = V.getValueType();
4545 unsigned NumElems = VT.getVectorNumElements();
4547 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4551 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4552 return (Index == 0) ? V.getOperand(0)
4553 : DAG.getUNDEF(VT.getVectorElementType());
4555 if (V.getOpcode() == ISD::BUILD_VECTOR)
4556 return V.getOperand(Index);
4561 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4563 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4564 unsigned NumNonZero, unsigned NumZero,
4566 const X86Subtarget* Subtarget,
4567 const TargetLowering &TLI) {
4575 // SSE4.1 - use PINSRB to insert each byte directly.
4576 if (Subtarget->hasSSE41()) {
4577 for (unsigned i = 0; i < 16; ++i) {
4578 bool isNonZero = (NonZeros & (1 << i)) != 0;
4582 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4584 V = DAG.getUNDEF(MVT::v16i8);
4587 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4588 MVT::v16i8, V, Op.getOperand(i),
4589 DAG.getIntPtrConstant(i, dl));
4596 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4597 for (unsigned i = 0; i < 16; ++i) {
4598 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4599 if (ThisIsNonZero && First) {
4601 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4603 V = DAG.getUNDEF(MVT::v8i16);
4608 SDValue ThisElt, LastElt;
4609 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4610 if (LastIsNonZero) {
4611 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4612 MVT::i16, Op.getOperand(i-1));
4614 if (ThisIsNonZero) {
4615 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4616 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4617 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4619 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4623 if (ThisElt.getNode())
4624 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4625 DAG.getIntPtrConstant(i/2, dl));
4629 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4632 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4634 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4635 unsigned NumNonZero, unsigned NumZero,
4637 const X86Subtarget* Subtarget,
4638 const TargetLowering &TLI) {
4645 for (unsigned i = 0; i < 8; ++i) {
4646 bool isNonZero = (NonZeros & (1 << i)) != 0;
4650 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4652 V = DAG.getUNDEF(MVT::v8i16);
4655 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4656 MVT::v8i16, V, Op.getOperand(i),
4657 DAG.getIntPtrConstant(i, dl));
4664 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4665 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4666 const X86Subtarget *Subtarget,
4667 const TargetLowering &TLI) {
4668 // Find all zeroable elements.
4669 std::bitset<4> Zeroable;
4670 for (int i=0; i < 4; ++i) {
4671 SDValue Elt = Op->getOperand(i);
4672 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4674 assert(Zeroable.size() - Zeroable.count() > 1 &&
4675 "We expect at least two non-zero elements!");
4677 // We only know how to deal with build_vector nodes where elements are either
4678 // zeroable or extract_vector_elt with constant index.
4679 SDValue FirstNonZero;
4680 unsigned FirstNonZeroIdx;
4681 for (unsigned i=0; i < 4; ++i) {
4684 SDValue Elt = Op->getOperand(i);
4685 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4686 !isa<ConstantSDNode>(Elt.getOperand(1)))
4688 // Make sure that this node is extracting from a 128-bit vector.
4689 MVT VT = Elt.getOperand(0).getSimpleValueType();
4690 if (!VT.is128BitVector())
4692 if (!FirstNonZero.getNode()) {
4694 FirstNonZeroIdx = i;
4698 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4699 SDValue V1 = FirstNonZero.getOperand(0);
4700 MVT VT = V1.getSimpleValueType();
4702 // See if this build_vector can be lowered as a blend with zero.
4704 unsigned EltMaskIdx, EltIdx;
4706 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4707 if (Zeroable[EltIdx]) {
4708 // The zero vector will be on the right hand side.
4709 Mask[EltIdx] = EltIdx+4;
4713 Elt = Op->getOperand(EltIdx);
4714 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4715 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4716 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4718 Mask[EltIdx] = EltIdx;
4722 // Let the shuffle legalizer deal with blend operations.
4723 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4724 if (V1.getSimpleValueType() != VT)
4725 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4726 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4729 // See if we can lower this build_vector to a INSERTPS.
4730 if (!Subtarget->hasSSE41())
4733 SDValue V2 = Elt.getOperand(0);
4734 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4737 bool CanFold = true;
4738 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4742 SDValue Current = Op->getOperand(i);
4743 SDValue SrcVector = Current->getOperand(0);
4746 CanFold = SrcVector == V1 &&
4747 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4753 assert(V1.getNode() && "Expected at least two non-zero elements!");
4754 if (V1.getSimpleValueType() != MVT::v4f32)
4755 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4756 if (V2.getSimpleValueType() != MVT::v4f32)
4757 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4759 // Ok, we can emit an INSERTPS instruction.
4760 unsigned ZMask = Zeroable.to_ulong();
4762 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4763 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4765 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4766 DAG.getIntPtrConstant(InsertPSMask, DL));
4767 return DAG.getNode(ISD::BITCAST, DL, VT, Result);
4770 /// Return a vector logical shift node.
4771 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4772 unsigned NumBits, SelectionDAG &DAG,
4773 const TargetLowering &TLI, SDLoc dl) {
4774 assert(VT.is128BitVector() && "Unknown type for VShift");
4775 MVT ShVT = MVT::v2i64;
4776 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4777 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4778 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4779 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4780 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4781 return DAG.getNode(ISD::BITCAST, dl, VT,
4782 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4786 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4788 // Check if the scalar load can be widened into a vector load. And if
4789 // the address is "base + cst" see if the cst can be "absorbed" into
4790 // the shuffle mask.
4791 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4792 SDValue Ptr = LD->getBasePtr();
4793 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4795 EVT PVT = LD->getValueType(0);
4796 if (PVT != MVT::i32 && PVT != MVT::f32)
4801 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4802 FI = FINode->getIndex();
4804 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4805 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4806 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4807 Offset = Ptr.getConstantOperandVal(1);
4808 Ptr = Ptr.getOperand(0);
4813 // FIXME: 256-bit vector instructions don't require a strict alignment,
4814 // improve this code to support it better.
4815 unsigned RequiredAlign = VT.getSizeInBits()/8;
4816 SDValue Chain = LD->getChain();
4817 // Make sure the stack object alignment is at least 16 or 32.
4818 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4819 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4820 if (MFI->isFixedObjectIndex(FI)) {
4821 // Can't change the alignment. FIXME: It's possible to compute
4822 // the exact stack offset and reference FI + adjust offset instead.
4823 // If someone *really* cares about this. That's the way to implement it.
4826 MFI->setObjectAlignment(FI, RequiredAlign);
4830 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4831 // Ptr + (Offset & ~15).
4834 if ((Offset % RequiredAlign) & 3)
4836 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4839 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4840 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4843 int EltNo = (Offset - StartOffset) >> 2;
4844 unsigned NumElems = VT.getVectorNumElements();
4846 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4847 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4848 LD->getPointerInfo().getWithOffset(StartOffset),
4849 false, false, false, 0);
4851 SmallVector<int, 8> Mask(NumElems, EltNo);
4853 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4859 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4860 /// elements can be replaced by a single large load which has the same value as
4861 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4863 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4865 /// FIXME: we'd also like to handle the case where the last elements are zero
4866 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4867 /// There's even a handy isZeroNode for that purpose.
4868 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4869 SDLoc &DL, SelectionDAG &DAG,
4870 bool isAfterLegalize) {
4871 unsigned NumElems = Elts.size();
4873 LoadSDNode *LDBase = nullptr;
4874 unsigned LastLoadedElt = -1U;
4876 // For each element in the initializer, see if we've found a load or an undef.
4877 // If we don't find an initial load element, or later load elements are
4878 // non-consecutive, bail out.
4879 for (unsigned i = 0; i < NumElems; ++i) {
4880 SDValue Elt = Elts[i];
4881 // Look through a bitcast.
4882 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4883 Elt = Elt.getOperand(0);
4884 if (!Elt.getNode() ||
4885 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4888 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4890 LDBase = cast<LoadSDNode>(Elt.getNode());
4894 if (Elt.getOpcode() == ISD::UNDEF)
4897 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4898 EVT LdVT = Elt.getValueType();
4899 // Each loaded element must be the correct fractional portion of the
4900 // requested vector load.
4901 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4903 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4908 // If we have found an entire vector of loads and undefs, then return a large
4909 // load of the entire vector width starting at the base pointer. If we found
4910 // consecutive loads for the low half, generate a vzext_load node.
4911 if (LastLoadedElt == NumElems - 1) {
4912 assert(LDBase && "Did not find base load for merging consecutive loads");
4913 EVT EltVT = LDBase->getValueType(0);
4914 // Ensure that the input vector size for the merged loads matches the
4915 // cumulative size of the input elements.
4916 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4919 if (isAfterLegalize &&
4920 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4923 SDValue NewLd = SDValue();
4925 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4926 LDBase->getPointerInfo(), LDBase->isVolatile(),
4927 LDBase->isNonTemporal(), LDBase->isInvariant(),
4928 LDBase->getAlignment());
4930 if (LDBase->hasAnyUseOfValue(1)) {
4931 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4933 SDValue(NewLd.getNode(), 1));
4934 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4935 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4936 SDValue(NewLd.getNode(), 1));
4942 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4943 //of a v4i32 / v4f32. It's probably worth generalizing.
4944 EVT EltVT = VT.getVectorElementType();
4945 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4946 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4947 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4948 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4950 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4951 LDBase->getPointerInfo(),
4952 LDBase->getAlignment(),
4953 false/*isVolatile*/, true/*ReadMem*/,
4956 // Make sure the newly-created LOAD is in the same position as LDBase in
4957 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4958 // update uses of LDBase's output chain to use the TokenFactor.
4959 if (LDBase->hasAnyUseOfValue(1)) {
4960 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4961 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4962 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4963 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4964 SDValue(ResNode.getNode(), 1));
4967 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4972 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4973 /// to generate a splat value for the following cases:
4974 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4975 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4976 /// a scalar load, or a constant.
4977 /// The VBROADCAST node is returned when a pattern is found,
4978 /// or SDValue() otherwise.
4979 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4980 SelectionDAG &DAG) {
4981 // VBROADCAST requires AVX.
4982 // TODO: Splats could be generated for non-AVX CPUs using SSE
4983 // instructions, but there's less potential gain for only 128-bit vectors.
4984 if (!Subtarget->hasAVX())
4987 MVT VT = Op.getSimpleValueType();
4990 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4991 "Unsupported vector type for broadcast.");
4996 switch (Op.getOpcode()) {
4998 // Unknown pattern found.
5001 case ISD::BUILD_VECTOR: {
5002 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5003 BitVector UndefElements;
5004 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5006 // We need a splat of a single value to use broadcast, and it doesn't
5007 // make any sense if the value is only in one element of the vector.
5008 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5012 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5013 Ld.getOpcode() == ISD::ConstantFP);
5015 // Make sure that all of the users of a non-constant load are from the
5016 // BUILD_VECTOR node.
5017 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5022 case ISD::VECTOR_SHUFFLE: {
5023 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5025 // Shuffles must have a splat mask where the first element is
5027 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5030 SDValue Sc = Op.getOperand(0);
5031 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5032 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5034 if (!Subtarget->hasInt256())
5037 // Use the register form of the broadcast instruction available on AVX2.
5038 if (VT.getSizeInBits() >= 256)
5039 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5040 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5043 Ld = Sc.getOperand(0);
5044 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5045 Ld.getOpcode() == ISD::ConstantFP);
5047 // The scalar_to_vector node and the suspected
5048 // load node must have exactly one user.
5049 // Constants may have multiple users.
5051 // AVX-512 has register version of the broadcast
5052 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5053 Ld.getValueType().getSizeInBits() >= 32;
5054 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5061 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5062 bool IsGE256 = (VT.getSizeInBits() >= 256);
5064 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5065 // instruction to save 8 or more bytes of constant pool data.
5066 // TODO: If multiple splats are generated to load the same constant,
5067 // it may be detrimental to overall size. There needs to be a way to detect
5068 // that condition to know if this is truly a size win.
5069 const Function *F = DAG.getMachineFunction().getFunction();
5070 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5072 // Handle broadcasting a single constant scalar from the constant pool
5074 // On Sandybridge (no AVX2), it is still better to load a constant vector
5075 // from the constant pool and not to broadcast it from a scalar.
5076 // But override that restriction when optimizing for size.
5077 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5078 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5079 EVT CVT = Ld.getValueType();
5080 assert(!CVT.isVector() && "Must not broadcast a vector type");
5082 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5083 // For size optimization, also splat v2f64 and v2i64, and for size opt
5084 // with AVX2, also splat i8 and i16.
5085 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5086 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5087 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5088 const Constant *C = nullptr;
5089 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5090 C = CI->getConstantIntValue();
5091 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5092 C = CF->getConstantFPValue();
5094 assert(C && "Invalid constant type");
5096 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5097 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5098 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5099 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5100 MachinePointerInfo::getConstantPool(),
5101 false, false, false, Alignment);
5103 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5107 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5109 // Handle AVX2 in-register broadcasts.
5110 if (!IsLoad && Subtarget->hasInt256() &&
5111 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5112 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5114 // The scalar source must be a normal load.
5118 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5119 (Subtarget->hasVLX() && ScalarSize == 64))
5120 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5122 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5123 // double since there is no vbroadcastsd xmm
5124 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5125 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5126 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5129 // Unsupported broadcast.
5133 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5134 /// underlying vector and index.
5136 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5138 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5140 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5141 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5144 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5146 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5148 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5149 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5152 // In this case the vector is the extract_subvector expression and the index
5153 // is 2, as specified by the shuffle.
5154 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5155 SDValue ShuffleVec = SVOp->getOperand(0);
5156 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5157 assert(ShuffleVecVT.getVectorElementType() ==
5158 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5160 int ShuffleIdx = SVOp->getMaskElt(Idx);
5161 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5162 ExtractedFromVec = ShuffleVec;
5168 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5169 MVT VT = Op.getSimpleValueType();
5171 // Skip if insert_vec_elt is not supported.
5172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5173 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5177 unsigned NumElems = Op.getNumOperands();
5181 SmallVector<unsigned, 4> InsertIndices;
5182 SmallVector<int, 8> Mask(NumElems, -1);
5184 for (unsigned i = 0; i != NumElems; ++i) {
5185 unsigned Opc = Op.getOperand(i).getOpcode();
5187 if (Opc == ISD::UNDEF)
5190 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5191 // Quit if more than 1 elements need inserting.
5192 if (InsertIndices.size() > 1)
5195 InsertIndices.push_back(i);
5199 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5200 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5201 // Quit if non-constant index.
5202 if (!isa<ConstantSDNode>(ExtIdx))
5204 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5206 // Quit if extracted from vector of different type.
5207 if (ExtractedFromVec.getValueType() != VT)
5210 if (!VecIn1.getNode())
5211 VecIn1 = ExtractedFromVec;
5212 else if (VecIn1 != ExtractedFromVec) {
5213 if (!VecIn2.getNode())
5214 VecIn2 = ExtractedFromVec;
5215 else if (VecIn2 != ExtractedFromVec)
5216 // Quit if more than 2 vectors to shuffle
5220 if (ExtractedFromVec == VecIn1)
5222 else if (ExtractedFromVec == VecIn2)
5223 Mask[i] = Idx + NumElems;
5226 if (!VecIn1.getNode())
5229 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5230 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5231 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5232 unsigned Idx = InsertIndices[i];
5233 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5234 DAG.getIntPtrConstant(Idx, DL));
5240 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5241 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5242 Op.getScalarValueSizeInBits() == 1 &&
5243 "Can not convert non-constant vector");
5244 uint64_t Immediate = 0;
5245 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5246 SDValue In = Op.getOperand(idx);
5247 if (In.getOpcode() != ISD::UNDEF)
5248 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5252 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5253 return DAG.getConstant(Immediate, dl, VT);
5255 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5257 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5259 MVT VT = Op.getSimpleValueType();
5260 assert((VT.getVectorElementType() == MVT::i1) &&
5261 "Unexpected type in LowerBUILD_VECTORvXi1!");
5264 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5265 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5266 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5267 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5270 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5271 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5272 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5273 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5276 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5277 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5278 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5279 return DAG.getNode(ISD::BITCAST, dl, VT, Imm);
5280 SDValue ExtVec = DAG.getNode(ISD::BITCAST, dl, MVT::v8i1, Imm);
5281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5282 DAG.getIntPtrConstant(0, dl));
5285 // Vector has one or more non-const elements
5286 uint64_t Immediate = 0;
5287 SmallVector<unsigned, 16> NonConstIdx;
5288 bool IsSplat = true;
5289 bool HasConstElts = false;
5291 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5292 SDValue In = Op.getOperand(idx);
5293 if (In.getOpcode() == ISD::UNDEF)
5295 if (!isa<ConstantSDNode>(In))
5296 NonConstIdx.push_back(idx);
5298 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5299 HasConstElts = true;
5303 else if (In != Op.getOperand(SplatIdx))
5307 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5309 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5310 DAG.getConstant(1, dl, VT),
5311 DAG.getConstant(0, dl, VT));
5313 // insert elements one by one
5317 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5318 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5320 else if (HasConstElts)
5321 Imm = DAG.getConstant(0, dl, VT);
5323 Imm = DAG.getUNDEF(VT);
5324 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, Imm);
5327 SDValue ExtVec = DAG.getNode(ISD::BITCAST, dl, MVT::v8i1, Imm);
5328 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5329 DAG.getIntPtrConstant(0, dl));
5332 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5333 unsigned InsertIdx = NonConstIdx[i];
5334 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5335 Op.getOperand(InsertIdx),
5336 DAG.getIntPtrConstant(InsertIdx, dl));
5341 /// \brief Return true if \p N implements a horizontal binop and return the
5342 /// operands for the horizontal binop into V0 and V1.
5344 /// This is a helper function of LowerToHorizontalOp().
5345 /// This function checks that the build_vector \p N in input implements a
5346 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5347 /// operation to match.
5348 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5349 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5350 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5353 /// This function only analyzes elements of \p N whose indices are
5354 /// in range [BaseIdx, LastIdx).
5355 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5357 unsigned BaseIdx, unsigned LastIdx,
5358 SDValue &V0, SDValue &V1) {
5359 EVT VT = N->getValueType(0);
5361 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5362 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5363 "Invalid Vector in input!");
5365 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5366 bool CanFold = true;
5367 unsigned ExpectedVExtractIdx = BaseIdx;
5368 unsigned NumElts = LastIdx - BaseIdx;
5369 V0 = DAG.getUNDEF(VT);
5370 V1 = DAG.getUNDEF(VT);
5372 // Check if N implements a horizontal binop.
5373 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5374 SDValue Op = N->getOperand(i + BaseIdx);
5377 if (Op->getOpcode() == ISD::UNDEF) {
5378 // Update the expected vector extract index.
5379 if (i * 2 == NumElts)
5380 ExpectedVExtractIdx = BaseIdx;
5381 ExpectedVExtractIdx += 2;
5385 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5390 SDValue Op0 = Op.getOperand(0);
5391 SDValue Op1 = Op.getOperand(1);
5393 // Try to match the following pattern:
5394 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5395 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5396 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5397 Op0.getOperand(0) == Op1.getOperand(0) &&
5398 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5399 isa<ConstantSDNode>(Op1.getOperand(1)));
5403 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5404 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5406 if (i * 2 < NumElts) {
5407 if (V0.getOpcode() == ISD::UNDEF) {
5408 V0 = Op0.getOperand(0);
5409 if (V0.getValueType() != VT)
5413 if (V1.getOpcode() == ISD::UNDEF) {
5414 V1 = Op0.getOperand(0);
5415 if (V1.getValueType() != VT)
5418 if (i * 2 == NumElts)
5419 ExpectedVExtractIdx = BaseIdx;
5422 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5423 if (I0 == ExpectedVExtractIdx)
5424 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5425 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5426 // Try to match the following dag sequence:
5427 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5428 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5432 ExpectedVExtractIdx += 2;
5438 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5439 /// a concat_vector.
5441 /// This is a helper function of LowerToHorizontalOp().
5442 /// This function expects two 256-bit vectors called V0 and V1.
5443 /// At first, each vector is split into two separate 128-bit vectors.
5444 /// Then, the resulting 128-bit vectors are used to implement two
5445 /// horizontal binary operations.
5447 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5449 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5450 /// the two new horizontal binop.
5451 /// When Mode is set, the first horizontal binop dag node would take as input
5452 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5453 /// horizontal binop dag node would take as input the lower 128-bit of V1
5454 /// and the upper 128-bit of V1.
5456 /// HADD V0_LO, V0_HI
5457 /// HADD V1_LO, V1_HI
5459 /// Otherwise, the first horizontal binop dag node takes as input the lower
5460 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5461 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5463 /// HADD V0_LO, V1_LO
5464 /// HADD V0_HI, V1_HI
5466 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5467 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5468 /// the upper 128-bits of the result.
5469 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5470 SDLoc DL, SelectionDAG &DAG,
5471 unsigned X86Opcode, bool Mode,
5472 bool isUndefLO, bool isUndefHI) {
5473 EVT VT = V0.getValueType();
5474 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5475 "Invalid nodes in input!");
5477 unsigned NumElts = VT.getVectorNumElements();
5478 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5479 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5480 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5481 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5482 EVT NewVT = V0_LO.getValueType();
5484 SDValue LO = DAG.getUNDEF(NewVT);
5485 SDValue HI = DAG.getUNDEF(NewVT);
5488 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5489 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5490 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5491 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5492 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5494 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5495 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5496 V1_LO->getOpcode() != ISD::UNDEF))
5497 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5499 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5500 V1_HI->getOpcode() != ISD::UNDEF))
5501 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5504 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5507 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5509 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5510 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5511 EVT VT = BV->getValueType(0);
5512 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5513 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5517 unsigned NumElts = VT.getVectorNumElements();
5518 SDValue InVec0 = DAG.getUNDEF(VT);
5519 SDValue InVec1 = DAG.getUNDEF(VT);
5521 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5522 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5524 // Odd-numbered elements in the input build vector are obtained from
5525 // adding two integer/float elements.
5526 // Even-numbered elements in the input build vector are obtained from
5527 // subtracting two integer/float elements.
5528 unsigned ExpectedOpcode = ISD::FSUB;
5529 unsigned NextExpectedOpcode = ISD::FADD;
5530 bool AddFound = false;
5531 bool SubFound = false;
5533 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5534 SDValue Op = BV->getOperand(i);
5536 // Skip 'undef' values.
5537 unsigned Opcode = Op.getOpcode();
5538 if (Opcode == ISD::UNDEF) {
5539 std::swap(ExpectedOpcode, NextExpectedOpcode);
5543 // Early exit if we found an unexpected opcode.
5544 if (Opcode != ExpectedOpcode)
5547 SDValue Op0 = Op.getOperand(0);
5548 SDValue Op1 = Op.getOperand(1);
5550 // Try to match the following pattern:
5551 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5552 // Early exit if we cannot match that sequence.
5553 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5554 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5555 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5556 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5557 Op0.getOperand(1) != Op1.getOperand(1))
5560 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5564 // We found a valid add/sub node. Update the information accordingly.
5570 // Update InVec0 and InVec1.
5571 if (InVec0.getOpcode() == ISD::UNDEF) {
5572 InVec0 = Op0.getOperand(0);
5573 if (InVec0.getValueType() != VT)
5576 if (InVec1.getOpcode() == ISD::UNDEF) {
5577 InVec1 = Op1.getOperand(0);
5578 if (InVec1.getValueType() != VT)
5582 // Make sure that operands in input to each add/sub node always
5583 // come from a same pair of vectors.
5584 if (InVec0 != Op0.getOperand(0)) {
5585 if (ExpectedOpcode == ISD::FSUB)
5588 // FADD is commutable. Try to commute the operands
5589 // and then test again.
5590 std::swap(Op0, Op1);
5591 if (InVec0 != Op0.getOperand(0))
5595 if (InVec1 != Op1.getOperand(0))
5598 // Update the pair of expected opcodes.
5599 std::swap(ExpectedOpcode, NextExpectedOpcode);
5602 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5603 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5604 InVec1.getOpcode() != ISD::UNDEF)
5605 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5610 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5611 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5612 const X86Subtarget *Subtarget,
5613 SelectionDAG &DAG) {
5614 EVT VT = BV->getValueType(0);
5615 unsigned NumElts = VT.getVectorNumElements();
5616 unsigned NumUndefsLO = 0;
5617 unsigned NumUndefsHI = 0;
5618 unsigned Half = NumElts/2;
5620 // Count the number of UNDEF operands in the build_vector in input.
5621 for (unsigned i = 0, e = Half; i != e; ++i)
5622 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5625 for (unsigned i = Half, e = NumElts; i != e; ++i)
5626 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5629 // Early exit if this is either a build_vector of all UNDEFs or all the
5630 // operands but one are UNDEF.
5631 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5635 SDValue InVec0, InVec1;
5636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5637 // Try to match an SSE3 float HADD/HSUB.
5638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5644 // Try to match an SSSE3 integer HADD/HSUB.
5645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5652 if (!Subtarget->hasAVX())
5655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5656 // Try to match an AVX horizontal add/sub of packed single/double
5657 // precision floating point values from 256-bit vectors.
5658 SDValue InVec2, InVec3;
5659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5661 ((InVec0.getOpcode() == ISD::UNDEF ||
5662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5663 ((InVec1.getOpcode() == ISD::UNDEF ||
5664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5669 ((InVec0.getOpcode() == ISD::UNDEF ||
5670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5671 ((InVec1.getOpcode() == ISD::UNDEF ||
5672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5675 // Try to match an AVX2 horizontal add/sub of signed integers.
5676 SDValue InVec2, InVec3;
5678 bool CanFold = true;
5680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5682 ((InVec0.getOpcode() == ISD::UNDEF ||
5683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5684 ((InVec1.getOpcode() == ISD::UNDEF ||
5685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5686 X86Opcode = X86ISD::HADD;
5687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5689 ((InVec0.getOpcode() == ISD::UNDEF ||
5690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5691 ((InVec1.getOpcode() == ISD::UNDEF ||
5692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5693 X86Opcode = X86ISD::HSUB;
5698 // Fold this build_vector into a single horizontal add/sub.
5699 // Do this only if the target has AVX2.
5700 if (Subtarget->hasAVX2())
5701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5703 // Do not try to expand this build_vector into a pair of horizontal
5704 // add/sub if we can emit a pair of scalar add/sub.
5705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5708 // Convert this build_vector into a pair of horizontal binop followed by
5710 bool isUndefLO = NumUndefsLO == Half;
5711 bool isUndefHI = NumUndefsHI == Half;
5712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5713 isUndefLO, isUndefHI);
5717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5721 X86Opcode = X86ISD::HADD;
5722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5723 X86Opcode = X86ISD::HSUB;
5724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5725 X86Opcode = X86ISD::FHADD;
5726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5727 X86Opcode = X86ISD::FHSUB;
5731 // Don't try to expand this build_vector into a pair of horizontal add/sub
5732 // if we can simply emit a pair of scalar add/sub.
5733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5736 // Convert this build_vector into two horizontal add/sub followed by
5738 bool isUndefLO = NumUndefsLO == Half;
5739 bool isUndefHI = NumUndefsHI == Half;
5740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5741 isUndefLO, isUndefHI);
5748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5751 MVT VT = Op.getSimpleValueType();
5752 MVT ExtVT = VT.getVectorElementType();
5753 unsigned NumElems = Op.getNumOperands();
5755 // Generate vectors for predicate vectors.
5756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5757 return LowerBUILD_VECTORvXi1(Op, DAG);
5759 // Vectors containing all zeros can be matched by pxor and xorps later
5760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5766 return getZeroVector(VT, Subtarget, DAG, dl);
5769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5771 // vpcmpeqd on 256-bit vectors.
5772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5776 if (!VT.is512BitVector())
5777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5780 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5781 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5783 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5784 return HorizontalOp;
5785 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5788 unsigned EVTBits = ExtVT.getSizeInBits();
5790 unsigned NumZero = 0;
5791 unsigned NumNonZero = 0;
5792 unsigned NonZeros = 0;
5793 bool IsAllConstants = true;
5794 SmallSet<SDValue, 8> Values;
5795 for (unsigned i = 0; i < NumElems; ++i) {
5796 SDValue Elt = Op.getOperand(i);
5797 if (Elt.getOpcode() == ISD::UNDEF)
5800 if (Elt.getOpcode() != ISD::Constant &&
5801 Elt.getOpcode() != ISD::ConstantFP)
5802 IsAllConstants = false;
5803 if (X86::isZeroNode(Elt))
5806 NonZeros |= (1 << i);
5811 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5812 if (NumNonZero == 0)
5813 return DAG.getUNDEF(VT);
5815 // Special case for single non-zero, non-undef, element.
5816 if (NumNonZero == 1) {
5817 unsigned Idx = countTrailingZeros(NonZeros);
5818 SDValue Item = Op.getOperand(Idx);
5820 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5821 // the value are obviously zero, truncate the value to i32 and do the
5822 // insertion that way. Only do this if the value is non-constant or if the
5823 // value is a constant being inserted into element 0. It is cheaper to do
5824 // a constant pool load than it is to do a movd + shuffle.
5825 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5826 (!IsAllConstants || Idx == 0)) {
5827 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5829 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5830 EVT VecVT = MVT::v4i32;
5832 // Truncate the value (which may itself be a constant) to i32, and
5833 // convert it to a vector with movd (S2V+shuffle to zero extend).
5834 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5835 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5837 ISD::BITCAST, dl, VT,
5838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5842 // If we have a constant or non-constant insertion into the low element of
5843 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5844 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5845 // depending on what the source datatype is.
5848 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5850 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5851 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5852 if (VT.is512BitVector()) {
5853 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5854 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5855 Item, DAG.getIntPtrConstant(0, dl));
5857 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5858 "Expected an SSE value type!");
5859 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5860 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5861 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5864 // We can't directly insert an i8 or i16 into a vector, so zero extend
5866 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5867 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5868 if (VT.is256BitVector()) {
5869 if (Subtarget->hasAVX()) {
5870 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5871 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5873 // Without AVX, we need to extend to a 128-bit vector and then
5874 // insert into the 256-bit vector.
5875 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5876 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5877 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5880 assert(VT.is128BitVector() && "Expected an SSE value type!");
5881 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5882 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5884 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5888 // Is it a vector logical left shift?
5889 if (NumElems == 2 && Idx == 1 &&
5890 X86::isZeroNode(Op.getOperand(0)) &&
5891 !X86::isZeroNode(Op.getOperand(1))) {
5892 unsigned NumBits = VT.getSizeInBits();
5893 return getVShift(true, VT,
5894 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5895 VT, Op.getOperand(1)),
5896 NumBits/2, DAG, *this, dl);
5899 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5902 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5903 // is a non-constant being inserted into an element other than the low one,
5904 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5905 // movd/movss) to move this into the low element, then shuffle it into
5907 if (EVTBits == 32) {
5908 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5909 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5913 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5914 if (Values.size() == 1) {
5915 if (EVTBits == 32) {
5916 // Instead of a shuffle like this:
5917 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5918 // Check if it's possible to issue this instead.
5919 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5920 unsigned Idx = countTrailingZeros(NonZeros);
5921 SDValue Item = Op.getOperand(Idx);
5922 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5923 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5928 // A vector full of immediates; various special cases are already
5929 // handled, so this is best done with a single constant-pool load.
5933 // For AVX-length vectors, see if we can use a vector load to get all of the
5934 // elements, otherwise build the individual 128-bit pieces and use
5935 // shuffles to put them in place.
5936 if (VT.is256BitVector() || VT.is512BitVector()) {
5937 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5939 // Check for a build vector of consecutive loads.
5940 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5943 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5945 // Build both the lower and upper subvector.
5946 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5947 makeArrayRef(&V[0], NumElems/2));
5948 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5949 makeArrayRef(&V[NumElems / 2], NumElems/2));
5951 // Recreate the wider vector with the lower and upper part.
5952 if (VT.is256BitVector())
5953 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5954 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5957 // Let legalizer expand 2-wide build_vectors.
5958 if (EVTBits == 64) {
5959 if (NumNonZero == 1) {
5960 // One half is zero or undef.
5961 unsigned Idx = countTrailingZeros(NonZeros);
5962 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5963 Op.getOperand(Idx));
5964 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5969 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5970 if (EVTBits == 8 && NumElems == 16)
5971 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5975 if (EVTBits == 16 && NumElems == 8)
5976 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5980 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5981 if (EVTBits == 32 && NumElems == 4)
5982 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5985 // If element VT is == 32 bits, turn it into a number of shuffles.
5986 SmallVector<SDValue, 8> V(NumElems);
5987 if (NumElems == 4 && NumZero > 0) {
5988 for (unsigned i = 0; i < 4; ++i) {
5989 bool isZero = !(NonZeros & (1 << i));
5991 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5993 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5996 for (unsigned i = 0; i < 2; ++i) {
5997 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6000 V[i] = V[i*2]; // Must be a zero vector.
6003 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6006 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6009 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6014 bool Reverse1 = (NonZeros & 0x3) == 2;
6015 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6019 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6020 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6022 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6025 if (Values.size() > 1 && VT.is128BitVector()) {
6026 // Check for a build vector of consecutive loads.
6027 for (unsigned i = 0; i < NumElems; ++i)
6028 V[i] = Op.getOperand(i);
6030 // Check for elements which are consecutive loads.
6031 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6034 // Check for a build vector from mostly shuffle plus few inserting.
6035 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6038 // For SSE 4.1, use insertps to put the high elements into the low element.
6039 if (Subtarget->hasSSE41()) {
6041 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6042 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6044 Result = DAG.getUNDEF(VT);
6046 for (unsigned i = 1; i < NumElems; ++i) {
6047 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6048 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6049 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6054 // Otherwise, expand into a number of unpckl*, start by extending each of
6055 // our (non-undef) elements to the full vector width with the element in the
6056 // bottom slot of the vector (which generates no code for SSE).
6057 for (unsigned i = 0; i < NumElems; ++i) {
6058 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6059 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6061 V[i] = DAG.getUNDEF(VT);
6064 // Next, we iteratively mix elements, e.g. for v4f32:
6065 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6066 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6067 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6068 unsigned EltStride = NumElems >> 1;
6069 while (EltStride != 0) {
6070 for (unsigned i = 0; i < EltStride; ++i) {
6071 // If V[i+EltStride] is undef and this is the first round of mixing,
6072 // then it is safe to just drop this shuffle: V[i] is already in the
6073 // right place, the one element (since it's the first round) being
6074 // inserted as undef can be dropped. This isn't safe for successive
6075 // rounds because they will permute elements within both vectors.
6076 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6077 EltStride == NumElems/2)
6080 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6089 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6090 // to create 256-bit vectors from two other 128-bit ones.
6091 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6093 MVT ResVT = Op.getSimpleValueType();
6095 assert((ResVT.is256BitVector() ||
6096 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6098 SDValue V1 = Op.getOperand(0);
6099 SDValue V2 = Op.getOperand(1);
6100 unsigned NumElems = ResVT.getVectorNumElements();
6101 if (ResVT.is256BitVector())
6102 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6104 if (Op.getNumOperands() == 4) {
6105 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6106 ResVT.getVectorNumElements()/2);
6107 SDValue V3 = Op.getOperand(2);
6108 SDValue V4 = Op.getOperand(3);
6109 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6110 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6112 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6115 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6116 const X86Subtarget *Subtarget,
6117 SelectionDAG & DAG) {
6119 MVT ResVT = Op.getSimpleValueType();
6120 unsigned NumOfOperands = Op.getNumOperands();
6122 assert(isPowerOf2_32(NumOfOperands) &&
6123 "Unexpected number of operands in CONCAT_VECTORS");
6125 if (NumOfOperands > 2) {
6126 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6127 ResVT.getVectorNumElements()/2);
6128 SmallVector<SDValue, 2> Ops;
6129 for (unsigned i = 0; i < NumOfOperands/2; i++)
6130 Ops.push_back(Op.getOperand(i));
6131 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6133 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6134 Ops.push_back(Op.getOperand(i));
6135 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6136 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6139 SDValue V1 = Op.getOperand(0);
6140 SDValue V2 = Op.getOperand(1);
6141 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6142 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6144 if (IsZeroV1 && IsZeroV2)
6145 return getZeroVector(ResVT, Subtarget, DAG, dl);
6147 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6148 SDValue Undef = DAG.getUNDEF(ResVT);
6149 unsigned NumElems = ResVT.getVectorNumElements();
6150 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6152 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6153 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6157 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6158 // Zero the upper bits of V1
6159 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6160 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6163 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6166 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6167 const X86Subtarget *Subtarget,
6168 SelectionDAG &DAG) {
6169 MVT VT = Op.getSimpleValueType();
6170 if (VT.getVectorElementType() == MVT::i1)
6171 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6173 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6174 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6175 Op.getNumOperands() == 4)));
6177 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6178 // from two other 128-bit ones.
6180 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6181 return LowerAVXCONCAT_VECTORS(Op, DAG);
6185 //===----------------------------------------------------------------------===//
6186 // Vector shuffle lowering
6188 // This is an experimental code path for lowering vector shuffles on x86. It is
6189 // designed to handle arbitrary vector shuffles and blends, gracefully
6190 // degrading performance as necessary. It works hard to recognize idiomatic
6191 // shuffles and lower them to optimal instruction patterns without leaving
6192 // a framework that allows reasonably efficient handling of all vector shuffle
6194 //===----------------------------------------------------------------------===//
6196 /// \brief Tiny helper function to identify a no-op mask.
6198 /// This is a somewhat boring predicate function. It checks whether the mask
6199 /// array input, which is assumed to be a single-input shuffle mask of the kind
6200 /// used by the X86 shuffle instructions (not a fully general
6201 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6202 /// in-place shuffle are 'no-op's.
6203 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6204 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6205 if (Mask[i] != -1 && Mask[i] != i)
6210 /// \brief Helper function to classify a mask as a single-input mask.
6212 /// This isn't a generic single-input test because in the vector shuffle
6213 /// lowering we canonicalize single inputs to be the first input operand. This
6214 /// means we can more quickly test for a single input by only checking whether
6215 /// an input from the second operand exists. We also assume that the size of
6216 /// mask corresponds to the size of the input vectors which isn't true in the
6217 /// fully general case.
6218 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6220 if (M >= (int)Mask.size())
6225 /// \brief Test whether there are elements crossing 128-bit lanes in this
6228 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6229 /// and we routinely test for these.
6230 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6231 int LaneSize = 128 / VT.getScalarSizeInBits();
6232 int Size = Mask.size();
6233 for (int i = 0; i < Size; ++i)
6234 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6239 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6241 /// This checks a shuffle mask to see if it is performing the same
6242 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6243 /// that it is also not lane-crossing. It may however involve a blend from the
6244 /// same lane of a second vector.
6246 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6247 /// non-trivial to compute in the face of undef lanes. The representation is
6248 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6249 /// entries from both V1 and V2 inputs to the wider mask.
6251 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6252 SmallVectorImpl<int> &RepeatedMask) {
6253 int LaneSize = 128 / VT.getScalarSizeInBits();
6254 RepeatedMask.resize(LaneSize, -1);
6255 int Size = Mask.size();
6256 for (int i = 0; i < Size; ++i) {
6259 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6260 // This entry crosses lanes, so there is no way to model this shuffle.
6263 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6264 if (RepeatedMask[i % LaneSize] == -1)
6265 // This is the first non-undef entry in this slot of a 128-bit lane.
6266 RepeatedMask[i % LaneSize] =
6267 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6268 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6269 // Found a mismatch with the repeated mask.
6275 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6278 /// This is a fast way to test a shuffle mask against a fixed pattern:
6280 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6282 /// It returns true if the mask is exactly as wide as the argument list, and
6283 /// each element of the mask is either -1 (signifying undef) or the value given
6284 /// in the argument.
6285 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6286 ArrayRef<int> ExpectedMask) {
6287 if (Mask.size() != ExpectedMask.size())
6290 int Size = Mask.size();
6292 // If the values are build vectors, we can look through them to find
6293 // equivalent inputs that make the shuffles equivalent.
6294 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6295 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6297 for (int i = 0; i < Size; ++i)
6298 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6299 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6300 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6301 if (!MaskBV || !ExpectedBV ||
6302 MaskBV->getOperand(Mask[i] % Size) !=
6303 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6310 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6312 /// This helper function produces an 8-bit shuffle immediate corresponding to
6313 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6314 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6317 /// NB: We rely heavily on "undef" masks preserving the input lane.
6318 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6319 SelectionDAG &DAG) {
6320 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6321 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6322 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6323 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6324 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6327 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6328 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6329 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6330 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6331 return DAG.getConstant(Imm, DL, MVT::i8);
6334 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6336 /// This is used as a fallback approach when first class blend instructions are
6337 /// unavailable. Currently it is only suitable for integer vectors, but could
6338 /// be generalized for floating point vectors if desirable.
6339 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6340 SDValue V2, ArrayRef<int> Mask,
6341 SelectionDAG &DAG) {
6342 assert(VT.isInteger() && "Only supports integer vector types!");
6343 MVT EltVT = VT.getScalarType();
6344 int NumEltBits = EltVT.getSizeInBits();
6345 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6346 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6348 SmallVector<SDValue, 16> MaskOps;
6349 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6350 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6351 return SDValue(); // Shuffled input!
6352 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6355 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6356 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6357 // We have to cast V2 around.
6358 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6359 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6360 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6361 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6362 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6363 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6366 /// \brief Try to emit a blend instruction for a shuffle.
6368 /// This doesn't do any checks for the availability of instructions for blending
6369 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6370 /// be matched in the backend with the type given. What it does check for is
6371 /// that the shuffle mask is in fact a blend.
6372 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6373 SDValue V2, ArrayRef<int> Mask,
6374 const X86Subtarget *Subtarget,
6375 SelectionDAG &DAG) {
6376 unsigned BlendMask = 0;
6377 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6378 if (Mask[i] >= Size) {
6379 if (Mask[i] != i + Size)
6380 return SDValue(); // Shuffled V2 input!
6381 BlendMask |= 1u << i;
6384 if (Mask[i] >= 0 && Mask[i] != i)
6385 return SDValue(); // Shuffled V1 input!
6387 switch (VT.SimpleTy) {
6392 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6393 DAG.getConstant(BlendMask, DL, MVT::i8));
6397 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6401 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6402 // that instruction.
6403 if (Subtarget->hasAVX2()) {
6404 // Scale the blend by the number of 32-bit dwords per element.
6405 int Scale = VT.getScalarSizeInBits() / 32;
6407 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6408 if (Mask[i] >= Size)
6409 for (int j = 0; j < Scale; ++j)
6410 BlendMask |= 1u << (i * Scale + j);
6412 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6413 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6414 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6415 return DAG.getNode(ISD::BITCAST, DL, VT,
6416 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6417 DAG.getConstant(BlendMask, DL, MVT::i8)));
6421 // For integer shuffles we need to expand the mask and cast the inputs to
6422 // v8i16s prior to blending.
6423 int Scale = 8 / VT.getVectorNumElements();
6425 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6426 if (Mask[i] >= Size)
6427 for (int j = 0; j < Scale; ++j)
6428 BlendMask |= 1u << (i * Scale + j);
6430 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6431 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6432 return DAG.getNode(ISD::BITCAST, DL, VT,
6433 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6434 DAG.getConstant(BlendMask, DL, MVT::i8)));
6438 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6439 SmallVector<int, 8> RepeatedMask;
6440 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6441 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6442 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6444 for (int i = 0; i < 8; ++i)
6445 if (RepeatedMask[i] >= 16)
6446 BlendMask |= 1u << i;
6447 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6448 DAG.getConstant(BlendMask, DL, MVT::i8));
6454 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6455 "256-bit byte-blends require AVX2 support!");
6457 // Scale the blend by the number of bytes per element.
6458 int Scale = VT.getScalarSizeInBits() / 8;
6460 // This form of blend is always done on bytes. Compute the byte vector
6462 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6464 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6465 // mix of LLVM's code generator and the x86 backend. We tell the code
6466 // generator that boolean values in the elements of an x86 vector register
6467 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6468 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6469 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6470 // of the element (the remaining are ignored) and 0 in that high bit would
6471 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6472 // the LLVM model for boolean values in vector elements gets the relevant
6473 // bit set, it is set backwards and over constrained relative to x86's
6475 SmallVector<SDValue, 32> VSELECTMask;
6476 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6477 for (int j = 0; j < Scale; ++j)
6478 VSELECTMask.push_back(
6479 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6480 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6483 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6484 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6486 ISD::BITCAST, DL, VT,
6487 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6488 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6493 llvm_unreachable("Not a supported integer vector type!");
6497 /// \brief Try to lower as a blend of elements from two inputs followed by
6498 /// a single-input permutation.
6500 /// This matches the pattern where we can blend elements from two inputs and
6501 /// then reduce the shuffle to a single-input permutation.
6502 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6505 SelectionDAG &DAG) {
6506 // We build up the blend mask while checking whether a blend is a viable way
6507 // to reduce the shuffle.
6508 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6509 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6511 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6515 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6517 if (BlendMask[Mask[i] % Size] == -1)
6518 BlendMask[Mask[i] % Size] = Mask[i];
6519 else if (BlendMask[Mask[i] % Size] != Mask[i])
6520 return SDValue(); // Can't blend in the needed input!
6522 PermuteMask[i] = Mask[i] % Size;
6525 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6526 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6529 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6530 /// blends and permutes.
6532 /// This matches the extremely common pattern for handling combined
6533 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6534 /// operations. It will try to pick the best arrangement of shuffles and
6536 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6540 SelectionDAG &DAG) {
6541 // Shuffle the input elements into the desired positions in V1 and V2 and
6542 // blend them together.
6543 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6544 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6545 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6546 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6547 if (Mask[i] >= 0 && Mask[i] < Size) {
6548 V1Mask[i] = Mask[i];
6550 } else if (Mask[i] >= Size) {
6551 V2Mask[i] = Mask[i] - Size;
6552 BlendMask[i] = i + Size;
6555 // Try to lower with the simpler initial blend strategy unless one of the
6556 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6557 // shuffle may be able to fold with a load or other benefit. However, when
6558 // we'll have to do 2x as many shuffles in order to achieve this, blending
6559 // first is a better strategy.
6560 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6561 if (SDValue BlendPerm =
6562 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6565 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6566 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6567 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6570 /// \brief Try to lower a vector shuffle as a byte rotation.
6572 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6573 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6574 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6575 /// try to generically lower a vector shuffle through such an pattern. It
6576 /// does not check for the profitability of lowering either as PALIGNR or
6577 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6578 /// This matches shuffle vectors that look like:
6580 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6582 /// Essentially it concatenates V1 and V2, shifts right by some number of
6583 /// elements, and takes the low elements as the result. Note that while this is
6584 /// specified as a *right shift* because x86 is little-endian, it is a *left
6585 /// rotate* of the vector lanes.
6586 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6589 const X86Subtarget *Subtarget,
6590 SelectionDAG &DAG) {
6591 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6593 int NumElts = Mask.size();
6594 int NumLanes = VT.getSizeInBits() / 128;
6595 int NumLaneElts = NumElts / NumLanes;
6597 // We need to detect various ways of spelling a rotation:
6598 // [11, 12, 13, 14, 15, 0, 1, 2]
6599 // [-1, 12, 13, 14, -1, -1, 1, -1]
6600 // [-1, -1, -1, -1, -1, -1, 1, 2]
6601 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6602 // [-1, 4, 5, 6, -1, -1, 9, -1]
6603 // [-1, 4, 5, 6, -1, -1, -1, -1]
6606 for (int l = 0; l < NumElts; l += NumLaneElts) {
6607 for (int i = 0; i < NumLaneElts; ++i) {
6608 if (Mask[l + i] == -1)
6610 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6612 // Get the mod-Size index and lane correct it.
6613 int LaneIdx = (Mask[l + i] % NumElts) - l;
6614 // Make sure it was in this lane.
6615 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6618 // Determine where a rotated vector would have started.
6619 int StartIdx = i - LaneIdx;
6621 // The identity rotation isn't interesting, stop.
6624 // If we found the tail of a vector the rotation must be the missing
6625 // front. If we found the head of a vector, it must be how much of the
6627 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6630 Rotation = CandidateRotation;
6631 else if (Rotation != CandidateRotation)
6632 // The rotations don't match, so we can't match this mask.
6635 // Compute which value this mask is pointing at.
6636 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6638 // Compute which of the two target values this index should be assigned
6639 // to. This reflects whether the high elements are remaining or the low
6640 // elements are remaining.
6641 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6643 // Either set up this value if we've not encountered it before, or check
6644 // that it remains consistent.
6647 else if (TargetV != MaskV)
6648 // This may be a rotation, but it pulls from the inputs in some
6649 // unsupported interleaving.
6654 // Check that we successfully analyzed the mask, and normalize the results.
6655 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6656 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6662 // The actual rotate instruction rotates bytes, so we need to scale the
6663 // rotation based on how many bytes are in the vector lane.
6664 int Scale = 16 / NumLaneElts;
6666 // SSSE3 targets can use the palignr instruction.
6667 if (Subtarget->hasSSSE3()) {
6668 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6669 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6670 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6671 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6673 return DAG.getNode(ISD::BITCAST, DL, VT,
6674 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6675 DAG.getConstant(Rotation * Scale, DL,
6679 assert(VT.getSizeInBits() == 128 &&
6680 "Rotate-based lowering only supports 128-bit lowering!");
6681 assert(Mask.size() <= 16 &&
6682 "Can shuffle at most 16 bytes in a 128-bit vector!");
6684 // Default SSE2 implementation
6685 int LoByteShift = 16 - Rotation * Scale;
6686 int HiByteShift = Rotation * Scale;
6688 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6689 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6690 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6692 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6693 DAG.getConstant(LoByteShift, DL, MVT::i8));
6694 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6695 DAG.getConstant(HiByteShift, DL, MVT::i8));
6696 return DAG.getNode(ISD::BITCAST, DL, VT,
6697 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6700 /// \brief Compute whether each element of a shuffle is zeroable.
6702 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6703 /// Either it is an undef element in the shuffle mask, the element of the input
6704 /// referenced is undef, or the element of the input referenced is known to be
6705 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6706 /// as many lanes with this technique as possible to simplify the remaining
6708 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6709 SDValue V1, SDValue V2) {
6710 SmallBitVector Zeroable(Mask.size(), false);
6712 while (V1.getOpcode() == ISD::BITCAST)
6713 V1 = V1->getOperand(0);
6714 while (V2.getOpcode() == ISD::BITCAST)
6715 V2 = V2->getOperand(0);
6717 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6718 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6720 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6722 // Handle the easy cases.
6723 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6728 // If this is an index into a build_vector node (which has the same number
6729 // of elements), dig out the input value and use it.
6730 SDValue V = M < Size ? V1 : V2;
6731 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6734 SDValue Input = V.getOperand(M % Size);
6735 // The UNDEF opcode check really should be dead code here, but not quite
6736 // worth asserting on (it isn't invalid, just unexpected).
6737 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6744 /// \brief Try to emit a bitmask instruction for a shuffle.
6746 /// This handles cases where we can model a blend exactly as a bitmask due to
6747 /// one of the inputs being zeroable.
6748 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6749 SDValue V2, ArrayRef<int> Mask,
6750 SelectionDAG &DAG) {
6751 MVT EltVT = VT.getScalarType();
6752 int NumEltBits = EltVT.getSizeInBits();
6753 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6754 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6755 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6757 if (EltVT.isFloatingPoint()) {
6758 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6759 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6761 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6762 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6764 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6767 if (Mask[i] % Size != i)
6768 return SDValue(); // Not a blend.
6770 V = Mask[i] < Size ? V1 : V2;
6771 else if (V != (Mask[i] < Size ? V1 : V2))
6772 return SDValue(); // Can only let one input through the mask.
6774 VMaskOps[i] = AllOnes;
6777 return SDValue(); // No non-zeroable elements!
6779 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6780 V = DAG.getNode(VT.isFloatingPoint()
6781 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6786 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6788 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6789 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6790 /// matches elements from one of the input vectors shuffled to the left or
6791 /// right with zeroable elements 'shifted in'. It handles both the strictly
6792 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6795 /// PSHL : (little-endian) left bit shift.
6796 /// [ zz, 0, zz, 2 ]
6797 /// [ -1, 4, zz, -1 ]
6798 /// PSRL : (little-endian) right bit shift.
6800 /// [ -1, -1, 7, zz]
6801 /// PSLLDQ : (little-endian) left byte shift
6802 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6803 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6804 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6805 /// PSRLDQ : (little-endian) right byte shift
6806 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6807 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6808 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6809 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6810 SDValue V2, ArrayRef<int> Mask,
6811 SelectionDAG &DAG) {
6812 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6814 int Size = Mask.size();
6815 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6817 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6818 for (int i = 0; i < Size; i += Scale)
6819 for (int j = 0; j < Shift; ++j)
6820 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6826 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6827 for (int i = 0; i != Size; i += Scale) {
6828 unsigned Pos = Left ? i + Shift : i;
6829 unsigned Low = Left ? i : i + Shift;
6830 unsigned Len = Scale - Shift;
6831 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6832 Low + (V == V1 ? 0 : Size)))
6836 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6837 bool ByteShift = ShiftEltBits > 64;
6838 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6839 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6840 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6842 // Normalize the scale for byte shifts to still produce an i64 element
6844 Scale = ByteShift ? Scale / 2 : Scale;
6846 // We need to round trip through the appropriate type for the shift.
6847 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6848 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6849 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6850 "Illegal integer vector type");
6851 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6853 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6854 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6855 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6858 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6859 // keep doubling the size of the integer elements up to that. We can
6860 // then shift the elements of the integer vector by whole multiples of
6861 // their width within the elements of the larger integer vector. Test each
6862 // multiple to see if we can find a match with the moved element indices
6863 // and that the shifted in elements are all zeroable.
6864 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6865 for (int Shift = 1; Shift != Scale; ++Shift)
6866 for (bool Left : {true, false})
6867 if (CheckZeros(Shift, Scale, Left))
6868 for (SDValue V : {V1, V2})
6869 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6876 /// \brief Lower a vector shuffle as a zero or any extension.
6878 /// Given a specific number of elements, element bit width, and extension
6879 /// stride, produce either a zero or any extension based on the available
6880 /// features of the subtarget.
6881 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6882 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6883 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6884 assert(Scale > 1 && "Need a scale to extend.");
6885 int NumElements = VT.getVectorNumElements();
6886 int EltBits = VT.getScalarSizeInBits();
6887 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6888 "Only 8, 16, and 32 bit elements can be extended.");
6889 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6891 // Found a valid zext mask! Try various lowering strategies based on the
6892 // input type and available ISA extensions.
6893 if (Subtarget->hasSSE41()) {
6894 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6895 NumElements / Scale);
6896 return DAG.getNode(ISD::BITCAST, DL, VT,
6897 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6900 // For any extends we can cheat for larger element sizes and use shuffle
6901 // instructions that can fold with a load and/or copy.
6902 if (AnyExt && EltBits == 32) {
6903 int PSHUFDMask[4] = {0, -1, 1, -1};
6905 ISD::BITCAST, DL, VT,
6906 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6907 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6908 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6910 if (AnyExt && EltBits == 16 && Scale > 2) {
6911 int PSHUFDMask[4] = {0, -1, 0, -1};
6912 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6913 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6914 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6915 int PSHUFHWMask[4] = {1, -1, -1, -1};
6917 ISD::BITCAST, DL, VT,
6918 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6919 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6920 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6923 // If this would require more than 2 unpack instructions to expand, use
6924 // pshufb when available. We can only use more than 2 unpack instructions
6925 // when zero extending i8 elements which also makes it easier to use pshufb.
6926 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6927 assert(NumElements == 16 && "Unexpected byte vector width!");
6928 SDValue PSHUFBMask[16];
6929 for (int i = 0; i < 16; ++i)
6931 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6932 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6933 return DAG.getNode(ISD::BITCAST, DL, VT,
6934 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6935 DAG.getNode(ISD::BUILD_VECTOR, DL,
6936 MVT::v16i8, PSHUFBMask)));
6939 // Otherwise emit a sequence of unpacks.
6941 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6942 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6943 : getZeroVector(InputVT, Subtarget, DAG, DL);
6944 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6945 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6949 } while (Scale > 1);
6950 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6953 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6955 /// This routine will try to do everything in its power to cleverly lower
6956 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6957 /// check for the profitability of this lowering, it tries to aggressively
6958 /// match this pattern. It will use all of the micro-architectural details it
6959 /// can to emit an efficient lowering. It handles both blends with all-zero
6960 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6961 /// masking out later).
6963 /// The reason we have dedicated lowering for zext-style shuffles is that they
6964 /// are both incredibly common and often quite performance sensitive.
6965 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6966 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6967 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6968 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6970 int Bits = VT.getSizeInBits();
6971 int NumElements = VT.getVectorNumElements();
6972 assert(VT.getScalarSizeInBits() <= 32 &&
6973 "Exceeds 32-bit integer zero extension limit");
6974 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6976 // Define a helper function to check a particular ext-scale and lower to it if
6978 auto Lower = [&](int Scale) -> SDValue {
6981 for (int i = 0; i < NumElements; ++i) {
6983 continue; // Valid anywhere but doesn't tell us anything.
6984 if (i % Scale != 0) {
6985 // Each of the extended elements need to be zeroable.
6989 // We no longer are in the anyext case.
6994 // Each of the base elements needs to be consecutive indices into the
6995 // same input vector.
6996 SDValue V = Mask[i] < NumElements ? V1 : V2;
6999 else if (InputV != V)
7000 return SDValue(); // Flip-flopping inputs.
7002 if (Mask[i] % NumElements != i / Scale)
7003 return SDValue(); // Non-consecutive strided elements.
7006 // If we fail to find an input, we have a zero-shuffle which should always
7007 // have already been handled.
7008 // FIXME: Maybe handle this here in case during blending we end up with one?
7012 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7013 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
7016 // The widest scale possible for extending is to a 64-bit integer.
7017 assert(Bits % 64 == 0 &&
7018 "The number of bits in a vector must be divisible by 64 on x86!");
7019 int NumExtElements = Bits / 64;
7021 // Each iteration, try extending the elements half as much, but into twice as
7023 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7024 assert(NumElements % NumExtElements == 0 &&
7025 "The input vector size must be divisible by the extended size.");
7026 if (SDValue V = Lower(NumElements / NumExtElements))
7030 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7034 // Returns one of the source operands if the shuffle can be reduced to a
7035 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7036 auto CanZExtLowHalf = [&]() {
7037 for (int i = NumElements / 2; i != NumElements; ++i)
7040 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7042 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7047 if (SDValue V = CanZExtLowHalf()) {
7048 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
7049 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7050 return DAG.getNode(ISD::BITCAST, DL, VT, V);
7053 // No viable ext lowering found.
7057 /// \brief Try to get a scalar value for a specific element of a vector.
7059 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7060 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7061 SelectionDAG &DAG) {
7062 MVT VT = V.getSimpleValueType();
7063 MVT EltVT = VT.getVectorElementType();
7064 while (V.getOpcode() == ISD::BITCAST)
7065 V = V.getOperand(0);
7066 // If the bitcasts shift the element size, we can't extract an equivalent
7068 MVT NewVT = V.getSimpleValueType();
7069 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7072 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7073 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7074 // Ensure the scalar operand is the same size as the destination.
7075 // FIXME: Add support for scalar truncation where possible.
7076 SDValue S = V.getOperand(Idx);
7077 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7078 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7084 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7086 /// This is particularly important because the set of instructions varies
7087 /// significantly based on whether the operand is a load or not.
7088 static bool isShuffleFoldableLoad(SDValue V) {
7089 while (V.getOpcode() == ISD::BITCAST)
7090 V = V.getOperand(0);
7092 return ISD::isNON_EXTLoad(V.getNode());
7095 /// \brief Try to lower insertion of a single element into a zero vector.
7097 /// This is a common pattern that we have especially efficient patterns to lower
7098 /// across all subtarget feature sets.
7099 static SDValue lowerVectorShuffleAsElementInsertion(
7100 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7101 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7102 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7104 MVT EltVT = VT.getVectorElementType();
7106 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7107 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7109 bool IsV1Zeroable = true;
7110 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7111 if (i != V2Index && !Zeroable[i]) {
7112 IsV1Zeroable = false;
7116 // Check for a single input from a SCALAR_TO_VECTOR node.
7117 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7118 // all the smarts here sunk into that routine. However, the current
7119 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7120 // vector shuffle lowering is dead.
7121 if (SDValue V2S = getScalarValueForVectorElement(
7122 V2, Mask[V2Index] - Mask.size(), DAG)) {
7123 // We need to zext the scalar if it is smaller than an i32.
7124 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7125 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7126 // Using zext to expand a narrow element won't work for non-zero
7131 // Zero-extend directly to i32.
7133 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7135 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7136 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7137 EltVT == MVT::i16) {
7138 // Either not inserting from the low element of the input or the input
7139 // element size is too small to use VZEXT_MOVL to clear the high bits.
7143 if (!IsV1Zeroable) {
7144 // If V1 can't be treated as a zero vector we have fewer options to lower
7145 // this. We can't support integer vectors or non-zero targets cheaply, and
7146 // the V1 elements can't be permuted in any way.
7147 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7148 if (!VT.isFloatingPoint() || V2Index != 0)
7150 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7151 V1Mask[V2Index] = -1;
7152 if (!isNoopShuffleMask(V1Mask))
7154 // This is essentially a special case blend operation, but if we have
7155 // general purpose blend operations, they are always faster. Bail and let
7156 // the rest of the lowering handle these as blends.
7157 if (Subtarget->hasSSE41())
7160 // Otherwise, use MOVSD or MOVSS.
7161 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7162 "Only two types of floating point element types to handle!");
7163 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7167 // This lowering only works for the low element with floating point vectors.
7168 if (VT.isFloatingPoint() && V2Index != 0)
7171 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7173 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7176 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7177 // the desired position. Otherwise it is more efficient to do a vector
7178 // shift left. We know that we can do a vector shift left because all
7179 // the inputs are zero.
7180 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7181 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7182 V2Shuffle[V2Index] = 0;
7183 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7185 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7187 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7189 V2Index * EltVT.getSizeInBits()/8, DL,
7190 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7191 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7197 /// \brief Try to lower broadcast of a single element.
7199 /// For convenience, this code also bundles all of the subtarget feature set
7200 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7201 /// a convenient way to factor it out.
7202 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7204 const X86Subtarget *Subtarget,
7205 SelectionDAG &DAG) {
7206 if (!Subtarget->hasAVX())
7208 if (VT.isInteger() && !Subtarget->hasAVX2())
7211 // Check that the mask is a broadcast.
7212 int BroadcastIdx = -1;
7214 if (M >= 0 && BroadcastIdx == -1)
7216 else if (M >= 0 && M != BroadcastIdx)
7219 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7220 "a sorted mask where the broadcast "
7223 // Go up the chain of (vector) values to find a scalar load that we can
7224 // combine with the broadcast.
7226 switch (V.getOpcode()) {
7227 case ISD::CONCAT_VECTORS: {
7228 int OperandSize = Mask.size() / V.getNumOperands();
7229 V = V.getOperand(BroadcastIdx / OperandSize);
7230 BroadcastIdx %= OperandSize;
7234 case ISD::INSERT_SUBVECTOR: {
7235 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7236 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7240 int BeginIdx = (int)ConstantIdx->getZExtValue();
7242 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7243 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7244 BroadcastIdx -= BeginIdx;
7255 // Check if this is a broadcast of a scalar. We special case lowering
7256 // for scalars so that we can more effectively fold with loads.
7257 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7258 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7259 V = V.getOperand(BroadcastIdx);
7261 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7262 // Only AVX2 has register broadcasts.
7263 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7265 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7266 // We can't broadcast from a vector register without AVX2, and we can only
7267 // broadcast from the zero-element of a vector register.
7271 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7274 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7275 // INSERTPS when the V1 elements are already in the correct locations
7276 // because otherwise we can just always use two SHUFPS instructions which
7277 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7278 // perform INSERTPS if a single V1 element is out of place and all V2
7279 // elements are zeroable.
7280 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7282 SelectionDAG &DAG) {
7283 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7284 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7285 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7286 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7288 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7291 int V1DstIndex = -1;
7292 int V2DstIndex = -1;
7293 bool V1UsedInPlace = false;
7295 for (int i = 0; i < 4; ++i) {
7296 // Synthesize a zero mask from the zeroable elements (includes undefs).
7302 // Flag if we use any V1 inputs in place.
7304 V1UsedInPlace = true;
7308 // We can only insert a single non-zeroable element.
7309 if (V1DstIndex != -1 || V2DstIndex != -1)
7313 // V1 input out of place for insertion.
7316 // V2 input for insertion.
7321 // Don't bother if we have no (non-zeroable) element for insertion.
7322 if (V1DstIndex == -1 && V2DstIndex == -1)
7325 // Determine element insertion src/dst indices. The src index is from the
7326 // start of the inserted vector, not the start of the concatenated vector.
7327 unsigned V2SrcIndex = 0;
7328 if (V1DstIndex != -1) {
7329 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7330 // and don't use the original V2 at all.
7331 V2SrcIndex = Mask[V1DstIndex];
7332 V2DstIndex = V1DstIndex;
7335 V2SrcIndex = Mask[V2DstIndex] - 4;
7338 // If no V1 inputs are used in place, then the result is created only from
7339 // the zero mask and the V2 insertion - so remove V1 dependency.
7341 V1 = DAG.getUNDEF(MVT::v4f32);
7343 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7344 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7346 // Insert the V2 element into the desired position.
7348 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7349 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7352 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7353 /// UNPCK instruction.
7355 /// This specifically targets cases where we end up with alternating between
7356 /// the two inputs, and so can permute them into something that feeds a single
7357 /// UNPCK instruction. Note that this routine only targets integer vectors
7358 /// because for floating point vectors we have a generalized SHUFPS lowering
7359 /// strategy that handles everything that doesn't *exactly* match an unpack,
7360 /// making this clever lowering unnecessary.
7361 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7362 SDValue V2, ArrayRef<int> Mask,
7363 SelectionDAG &DAG) {
7364 assert(!VT.isFloatingPoint() &&
7365 "This routine only supports integer vectors.");
7366 assert(!isSingleInputShuffleMask(Mask) &&
7367 "This routine should only be used when blending two inputs.");
7368 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7370 int Size = Mask.size();
7372 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7373 return M >= 0 && M % Size < Size / 2;
7375 int NumHiInputs = std::count_if(
7376 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7378 bool UnpackLo = NumLoInputs >= NumHiInputs;
7380 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7381 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7382 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7384 for (int i = 0; i < Size; ++i) {
7388 // Each element of the unpack contains Scale elements from this mask.
7389 int UnpackIdx = i / Scale;
7391 // We only handle the case where V1 feeds the first slots of the unpack.
7392 // We rely on canonicalization to ensure this is the case.
7393 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7396 // Setup the mask for this input. The indexing is tricky as we have to
7397 // handle the unpack stride.
7398 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7399 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7403 // If we will have to shuffle both inputs to use the unpack, check whether
7404 // we can just unpack first and shuffle the result. If so, skip this unpack.
7405 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7406 !isNoopShuffleMask(V2Mask))
7409 // Shuffle the inputs into place.
7410 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7411 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7413 // Cast the inputs to the type we will use to unpack them.
7414 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7415 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7417 // Unpack the inputs and cast the result back to the desired type.
7418 return DAG.getNode(ISD::BITCAST, DL, VT,
7419 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7420 DL, UnpackVT, V1, V2));
7423 // We try each unpack from the largest to the smallest to try and find one
7424 // that fits this mask.
7425 int OrigNumElements = VT.getVectorNumElements();
7426 int OrigScalarSize = VT.getScalarSizeInBits();
7427 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7428 int Scale = ScalarSize / OrigScalarSize;
7429 int NumElements = OrigNumElements / Scale;
7430 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7431 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7435 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7437 if (NumLoInputs == 0 || NumHiInputs == 0) {
7438 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7439 "We have to have *some* inputs!");
7440 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7442 // FIXME: We could consider the total complexity of the permute of each
7443 // possible unpacking. Or at the least we should consider how many
7444 // half-crossings are created.
7445 // FIXME: We could consider commuting the unpacks.
7447 SmallVector<int, 32> PermMask;
7448 PermMask.assign(Size, -1);
7449 for (int i = 0; i < Size; ++i) {
7453 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7456 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7458 return DAG.getVectorShuffle(
7459 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7461 DAG.getUNDEF(VT), PermMask);
7467 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7469 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7470 /// support for floating point shuffles but not integer shuffles. These
7471 /// instructions will incur a domain crossing penalty on some chips though so
7472 /// it is better to avoid lowering through this for integer vectors where
7474 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7475 const X86Subtarget *Subtarget,
7476 SelectionDAG &DAG) {
7478 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7479 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7480 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7481 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7482 ArrayRef<int> Mask = SVOp->getMask();
7483 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7485 if (isSingleInputShuffleMask(Mask)) {
7486 // Use low duplicate instructions for masks that match their pattern.
7487 if (Subtarget->hasSSE3())
7488 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7489 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7491 // Straight shuffle of a single input vector. Simulate this by using the
7492 // single input as both of the "inputs" to this instruction..
7493 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7495 if (Subtarget->hasAVX()) {
7496 // If we have AVX, we can use VPERMILPS which will allow folding a load
7497 // into the shuffle.
7498 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7499 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7502 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7503 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7505 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7506 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7508 // If we have a single input, insert that into V1 if we can do so cheaply.
7509 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7510 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7511 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7513 // Try inverting the insertion since for v2 masks it is easy to do and we
7514 // can't reliably sort the mask one way or the other.
7515 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7516 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7517 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7518 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7522 // Try to use one of the special instruction patterns to handle two common
7523 // blend patterns if a zero-blend above didn't work.
7524 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7525 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7526 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7527 // We can either use a special instruction to load over the low double or
7528 // to move just the low double.
7530 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7532 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7534 if (Subtarget->hasSSE41())
7535 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7539 // Use dedicated unpack instructions for masks that match their pattern.
7540 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7541 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7542 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7543 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7545 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7546 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7547 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7550 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7552 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7553 /// the integer unit to minimize domain crossing penalties. However, for blends
7554 /// it falls back to the floating point shuffle operation with appropriate bit
7556 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7557 const X86Subtarget *Subtarget,
7558 SelectionDAG &DAG) {
7560 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7561 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7562 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7564 ArrayRef<int> Mask = SVOp->getMask();
7565 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7567 if (isSingleInputShuffleMask(Mask)) {
7568 // Check for being able to broadcast a single element.
7569 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7570 Mask, Subtarget, DAG))
7573 // Straight shuffle of a single input vector. For everything from SSE2
7574 // onward this has a single fast instruction with no scary immediates.
7575 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7576 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7577 int WidenedMask[4] = {
7578 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7579 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7581 ISD::BITCAST, DL, MVT::v2i64,
7582 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7583 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7585 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7586 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7587 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7588 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7590 // If we have a blend of two PACKUS operations an the blend aligns with the
7591 // low and half halves, we can just merge the PACKUS operations. This is
7592 // particularly important as it lets us merge shuffles that this routine itself
7594 auto GetPackNode = [](SDValue V) {
7595 while (V.getOpcode() == ISD::BITCAST)
7596 V = V.getOperand(0);
7598 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7600 if (SDValue V1Pack = GetPackNode(V1))
7601 if (SDValue V2Pack = GetPackNode(V2))
7602 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7603 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7604 Mask[0] == 0 ? V1Pack.getOperand(0)
7605 : V1Pack.getOperand(1),
7606 Mask[1] == 2 ? V2Pack.getOperand(0)
7607 : V2Pack.getOperand(1)));
7609 // Try to use shift instructions.
7611 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7614 // When loading a scalar and then shuffling it into a vector we can often do
7615 // the insertion cheaply.
7616 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7617 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7619 // Try inverting the insertion since for v2 masks it is easy to do and we
7620 // can't reliably sort the mask one way or the other.
7621 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7622 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7623 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7626 // We have different paths for blend lowering, but they all must use the
7627 // *exact* same predicate.
7628 bool IsBlendSupported = Subtarget->hasSSE41();
7629 if (IsBlendSupported)
7630 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7634 // Use dedicated unpack instructions for masks that match their pattern.
7635 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7636 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7637 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7638 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7640 // Try to use byte rotation instructions.
7641 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7642 if (Subtarget->hasSSSE3())
7643 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7644 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7647 // If we have direct support for blends, we should lower by decomposing into
7648 // a permute. That will be faster than the domain cross.
7649 if (IsBlendSupported)
7650 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7653 // We implement this with SHUFPD which is pretty lame because it will likely
7654 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7655 // However, all the alternatives are still more cycles and newer chips don't
7656 // have this problem. It would be really nice if x86 had better shuffles here.
7657 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7658 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7659 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7660 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7663 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7665 /// This is used to disable more specialized lowerings when the shufps lowering
7666 /// will happen to be efficient.
7667 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7668 // This routine only handles 128-bit shufps.
7669 assert(Mask.size() == 4 && "Unsupported mask size!");
7671 // To lower with a single SHUFPS we need to have the low half and high half
7672 // each requiring a single input.
7673 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7675 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7681 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7683 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7684 /// It makes no assumptions about whether this is the *best* lowering, it simply
7686 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7687 ArrayRef<int> Mask, SDValue V1,
7688 SDValue V2, SelectionDAG &DAG) {
7689 SDValue LowV = V1, HighV = V2;
7690 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7693 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7695 if (NumV2Elements == 1) {
7697 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7700 // Compute the index adjacent to V2Index and in the same half by toggling
7702 int V2AdjIndex = V2Index ^ 1;
7704 if (Mask[V2AdjIndex] == -1) {
7705 // Handles all the cases where we have a single V2 element and an undef.
7706 // This will only ever happen in the high lanes because we commute the
7707 // vector otherwise.
7709 std::swap(LowV, HighV);
7710 NewMask[V2Index] -= 4;
7712 // Handle the case where the V2 element ends up adjacent to a V1 element.
7713 // To make this work, blend them together as the first step.
7714 int V1Index = V2AdjIndex;
7715 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7716 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7717 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7719 // Now proceed to reconstruct the final blend as we have the necessary
7720 // high or low half formed.
7727 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7728 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7730 } else if (NumV2Elements == 2) {
7731 if (Mask[0] < 4 && Mask[1] < 4) {
7732 // Handle the easy case where we have V1 in the low lanes and V2 in the
7736 } else if (Mask[2] < 4 && Mask[3] < 4) {
7737 // We also handle the reversed case because this utility may get called
7738 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7739 // arrange things in the right direction.
7745 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7746 // trying to place elements directly, just blend them and set up the final
7747 // shuffle to place them.
7749 // The first two blend mask elements are for V1, the second two are for
7751 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7752 Mask[2] < 4 ? Mask[2] : Mask[3],
7753 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7754 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7755 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7756 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7758 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7761 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7762 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7763 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7764 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7767 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7768 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7771 /// \brief Lower 4-lane 32-bit floating point shuffles.
7773 /// Uses instructions exclusively from the floating point unit to minimize
7774 /// domain crossing penalties, as these are sufficient to implement all v4f32
7776 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7777 const X86Subtarget *Subtarget,
7778 SelectionDAG &DAG) {
7780 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7781 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7782 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7783 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7784 ArrayRef<int> Mask = SVOp->getMask();
7785 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7788 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7790 if (NumV2Elements == 0) {
7791 // Check for being able to broadcast a single element.
7792 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7793 Mask, Subtarget, DAG))
7796 // Use even/odd duplicate instructions for masks that match their pattern.
7797 if (Subtarget->hasSSE3()) {
7798 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7799 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7800 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7801 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7804 if (Subtarget->hasAVX()) {
7805 // If we have AVX, we can use VPERMILPS which will allow folding a load
7806 // into the shuffle.
7807 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7808 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7811 // Otherwise, use a straight shuffle of a single input vector. We pass the
7812 // input vector to both operands to simulate this with a SHUFPS.
7813 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7814 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7817 // There are special ways we can lower some single-element blends. However, we
7818 // have custom ways we can lower more complex single-element blends below that
7819 // we defer to if both this and BLENDPS fail to match, so restrict this to
7820 // when the V2 input is targeting element 0 of the mask -- that is the fast
7822 if (NumV2Elements == 1 && Mask[0] >= 4)
7823 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7824 Mask, Subtarget, DAG))
7827 if (Subtarget->hasSSE41()) {
7828 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7832 // Use INSERTPS if we can complete the shuffle efficiently.
7833 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7836 if (!isSingleSHUFPSMask(Mask))
7837 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7838 DL, MVT::v4f32, V1, V2, Mask, DAG))
7842 // Use dedicated unpack instructions for masks that match their pattern.
7843 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7844 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7845 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7846 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7847 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7848 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7849 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7850 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7852 // Otherwise fall back to a SHUFPS lowering strategy.
7853 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7856 /// \brief Lower 4-lane i32 vector shuffles.
7858 /// We try to handle these with integer-domain shuffles where we can, but for
7859 /// blends we use the floating point domain blend instructions.
7860 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7861 const X86Subtarget *Subtarget,
7862 SelectionDAG &DAG) {
7864 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7865 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7866 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7867 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7868 ArrayRef<int> Mask = SVOp->getMask();
7869 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7871 // Whenever we can lower this as a zext, that instruction is strictly faster
7872 // than any alternative. It also allows us to fold memory operands into the
7873 // shuffle in many cases.
7874 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7875 Mask, Subtarget, DAG))
7879 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7881 if (NumV2Elements == 0) {
7882 // Check for being able to broadcast a single element.
7883 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7884 Mask, Subtarget, DAG))
7887 // Straight shuffle of a single input vector. For everything from SSE2
7888 // onward this has a single fast instruction with no scary immediates.
7889 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7890 // but we aren't actually going to use the UNPCK instruction because doing
7891 // so prevents folding a load into this instruction or making a copy.
7892 const int UnpackLoMask[] = {0, 0, 1, 1};
7893 const int UnpackHiMask[] = {2, 2, 3, 3};
7894 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7895 Mask = UnpackLoMask;
7896 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7897 Mask = UnpackHiMask;
7899 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7900 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7903 // Try to use shift instructions.
7905 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7908 // There are special ways we can lower some single-element blends.
7909 if (NumV2Elements == 1)
7910 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7911 Mask, Subtarget, DAG))
7914 // We have different paths for blend lowering, but they all must use the
7915 // *exact* same predicate.
7916 bool IsBlendSupported = Subtarget->hasSSE41();
7917 if (IsBlendSupported)
7918 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7922 if (SDValue Masked =
7923 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7926 // Use dedicated unpack instructions for masks that match their pattern.
7927 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7928 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7929 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7930 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7931 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7932 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7933 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7934 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7936 // Try to use byte rotation instructions.
7937 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7938 if (Subtarget->hasSSSE3())
7939 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7940 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7943 // If we have direct support for blends, we should lower by decomposing into
7944 // a permute. That will be faster than the domain cross.
7945 if (IsBlendSupported)
7946 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7949 // Try to lower by permuting the inputs into an unpack instruction.
7950 if (SDValue Unpack =
7951 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7954 // We implement this with SHUFPS because it can blend from two vectors.
7955 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7956 // up the inputs, bypassing domain shift penalties that we would encur if we
7957 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7959 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7960 DAG.getVectorShuffle(
7962 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7963 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7966 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7967 /// shuffle lowering, and the most complex part.
7969 /// The lowering strategy is to try to form pairs of input lanes which are
7970 /// targeted at the same half of the final vector, and then use a dword shuffle
7971 /// to place them onto the right half, and finally unpack the paired lanes into
7972 /// their final position.
7974 /// The exact breakdown of how to form these dword pairs and align them on the
7975 /// correct sides is really tricky. See the comments within the function for
7976 /// more of the details.
7978 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7979 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7980 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7981 /// vector, form the analogous 128-bit 8-element Mask.
7982 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7983 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7984 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7985 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7986 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7988 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7989 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7990 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7992 SmallVector<int, 4> LoInputs;
7993 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7994 [](int M) { return M >= 0; });
7995 std::sort(LoInputs.begin(), LoInputs.end());
7996 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7997 SmallVector<int, 4> HiInputs;
7998 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7999 [](int M) { return M >= 0; });
8000 std::sort(HiInputs.begin(), HiInputs.end());
8001 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8003 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8004 int NumHToL = LoInputs.size() - NumLToL;
8006 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8007 int NumHToH = HiInputs.size() - NumLToH;
8008 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8009 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8010 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8011 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8013 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8014 // such inputs we can swap two of the dwords across the half mark and end up
8015 // with <=2 inputs to each half in each half. Once there, we can fall through
8016 // to the generic code below. For example:
8018 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8019 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8021 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8022 // and an existing 2-into-2 on the other half. In this case we may have to
8023 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8024 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8025 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8026 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8027 // half than the one we target for fixing) will be fixed when we re-enter this
8028 // path. We will also combine away any sequence of PSHUFD instructions that
8029 // result into a single instruction. Here is an example of the tricky case:
8031 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8032 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8034 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8036 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8037 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8039 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8040 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8042 // The result is fine to be handled by the generic logic.
8043 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8044 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8045 int AOffset, int BOffset) {
8046 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8047 "Must call this with A having 3 or 1 inputs from the A half.");
8048 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8049 "Must call this with B having 1 or 3 inputs from the B half.");
8050 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8051 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8053 // Compute the index of dword with only one word among the three inputs in
8054 // a half by taking the sum of the half with three inputs and subtracting
8055 // the sum of the actual three inputs. The difference is the remaining
8058 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8059 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8060 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8061 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8062 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8063 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8064 int TripleNonInputIdx =
8065 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8066 TripleDWord = TripleNonInputIdx / 2;
8068 // We use xor with one to compute the adjacent DWord to whichever one the
8070 OneInputDWord = (OneInput / 2) ^ 1;
8072 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8073 // and BToA inputs. If there is also such a problem with the BToB and AToB
8074 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8075 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8076 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8077 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8078 // Compute how many inputs will be flipped by swapping these DWords. We
8080 // to balance this to ensure we don't form a 3-1 shuffle in the other
8082 int NumFlippedAToBInputs =
8083 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8084 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8085 int NumFlippedBToBInputs =
8086 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8087 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8088 if ((NumFlippedAToBInputs == 1 &&
8089 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8090 (NumFlippedBToBInputs == 1 &&
8091 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8092 // We choose whether to fix the A half or B half based on whether that
8093 // half has zero flipped inputs. At zero, we may not be able to fix it
8094 // with that half. We also bias towards fixing the B half because that
8095 // will more commonly be the high half, and we have to bias one way.
8096 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8097 ArrayRef<int> Inputs) {
8098 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8099 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8100 PinnedIdx ^ 1) != Inputs.end();
8101 // Determine whether the free index is in the flipped dword or the
8102 // unflipped dword based on where the pinned index is. We use this bit
8103 // in an xor to conditionally select the adjacent dword.
8104 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8105 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8106 FixFreeIdx) != Inputs.end();
8107 if (IsFixIdxInput == IsFixFreeIdxInput)
8109 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8110 FixFreeIdx) != Inputs.end();
8111 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8112 "We need to be changing the number of flipped inputs!");
8113 int PSHUFHalfMask[] = {0, 1, 2, 3};
8114 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8115 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8117 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8120 if (M != -1 && M == FixIdx)
8122 else if (M != -1 && M == FixFreeIdx)
8125 if (NumFlippedBToBInputs != 0) {
8127 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8128 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8130 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8132 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8133 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8138 int PSHUFDMask[] = {0, 1, 2, 3};
8139 PSHUFDMask[ADWord] = BDWord;
8140 PSHUFDMask[BDWord] = ADWord;
8141 V = DAG.getNode(ISD::BITCAST, DL, VT,
8142 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8143 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8144 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8147 // Adjust the mask to match the new locations of A and B.
8149 if (M != -1 && M/2 == ADWord)
8150 M = 2 * BDWord + M % 2;
8151 else if (M != -1 && M/2 == BDWord)
8152 M = 2 * ADWord + M % 2;
8154 // Recurse back into this routine to re-compute state now that this isn't
8155 // a 3 and 1 problem.
8156 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8159 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8160 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8161 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8162 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8164 // At this point there are at most two inputs to the low and high halves from
8165 // each half. That means the inputs can always be grouped into dwords and
8166 // those dwords can then be moved to the correct half with a dword shuffle.
8167 // We use at most one low and one high word shuffle to collect these paired
8168 // inputs into dwords, and finally a dword shuffle to place them.
8169 int PSHUFLMask[4] = {-1, -1, -1, -1};
8170 int PSHUFHMask[4] = {-1, -1, -1, -1};
8171 int PSHUFDMask[4] = {-1, -1, -1, -1};
8173 // First fix the masks for all the inputs that are staying in their
8174 // original halves. This will then dictate the targets of the cross-half
8176 auto fixInPlaceInputs =
8177 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8178 MutableArrayRef<int> SourceHalfMask,
8179 MutableArrayRef<int> HalfMask, int HalfOffset) {
8180 if (InPlaceInputs.empty())
8182 if (InPlaceInputs.size() == 1) {
8183 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8184 InPlaceInputs[0] - HalfOffset;
8185 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8188 if (IncomingInputs.empty()) {
8189 // Just fix all of the in place inputs.
8190 for (int Input : InPlaceInputs) {
8191 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8192 PSHUFDMask[Input / 2] = Input / 2;
8197 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8198 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8199 InPlaceInputs[0] - HalfOffset;
8200 // Put the second input next to the first so that they are packed into
8201 // a dword. We find the adjacent index by toggling the low bit.
8202 int AdjIndex = InPlaceInputs[0] ^ 1;
8203 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8204 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8205 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8207 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8208 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8210 // Now gather the cross-half inputs and place them into a free dword of
8211 // their target half.
8212 // FIXME: This operation could almost certainly be simplified dramatically to
8213 // look more like the 3-1 fixing operation.
8214 auto moveInputsToRightHalf = [&PSHUFDMask](
8215 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8216 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8217 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8219 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8220 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8222 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8224 int LowWord = Word & ~1;
8225 int HighWord = Word | 1;
8226 return isWordClobbered(SourceHalfMask, LowWord) ||
8227 isWordClobbered(SourceHalfMask, HighWord);
8230 if (IncomingInputs.empty())
8233 if (ExistingInputs.empty()) {
8234 // Map any dwords with inputs from them into the right half.
8235 for (int Input : IncomingInputs) {
8236 // If the source half mask maps over the inputs, turn those into
8237 // swaps and use the swapped lane.
8238 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8239 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8240 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8241 Input - SourceOffset;
8242 // We have to swap the uses in our half mask in one sweep.
8243 for (int &M : HalfMask)
8244 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8246 else if (M == Input)
8247 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8249 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8250 Input - SourceOffset &&
8251 "Previous placement doesn't match!");
8253 // Note that this correctly re-maps both when we do a swap and when
8254 // we observe the other side of the swap above. We rely on that to
8255 // avoid swapping the members of the input list directly.
8256 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8259 // Map the input's dword into the correct half.
8260 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8261 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8263 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8265 "Previous placement doesn't match!");
8268 // And just directly shift any other-half mask elements to be same-half
8269 // as we will have mirrored the dword containing the element into the
8270 // same position within that half.
8271 for (int &M : HalfMask)
8272 if (M >= SourceOffset && M < SourceOffset + 4) {
8273 M = M - SourceOffset + DestOffset;
8274 assert(M >= 0 && "This should never wrap below zero!");
8279 // Ensure we have the input in a viable dword of its current half. This
8280 // is particularly tricky because the original position may be clobbered
8281 // by inputs being moved and *staying* in that half.
8282 if (IncomingInputs.size() == 1) {
8283 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8284 int InputFixed = std::find(std::begin(SourceHalfMask),
8285 std::end(SourceHalfMask), -1) -
8286 std::begin(SourceHalfMask) + SourceOffset;
8287 SourceHalfMask[InputFixed - SourceOffset] =
8288 IncomingInputs[0] - SourceOffset;
8289 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8291 IncomingInputs[0] = InputFixed;
8293 } else if (IncomingInputs.size() == 2) {
8294 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8295 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8296 // We have two non-adjacent or clobbered inputs we need to extract from
8297 // the source half. To do this, we need to map them into some adjacent
8298 // dword slot in the source mask.
8299 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8300 IncomingInputs[1] - SourceOffset};
8302 // If there is a free slot in the source half mask adjacent to one of
8303 // the inputs, place the other input in it. We use (Index XOR 1) to
8304 // compute an adjacent index.
8305 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8306 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8307 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8308 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8309 InputsFixed[1] = InputsFixed[0] ^ 1;
8310 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8311 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8312 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8313 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8314 InputsFixed[0] = InputsFixed[1] ^ 1;
8315 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8316 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8317 // The two inputs are in the same DWord but it is clobbered and the
8318 // adjacent DWord isn't used at all. Move both inputs to the free
8320 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8321 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8322 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8323 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8325 // The only way we hit this point is if there is no clobbering
8326 // (because there are no off-half inputs to this half) and there is no
8327 // free slot adjacent to one of the inputs. In this case, we have to
8328 // swap an input with a non-input.
8329 for (int i = 0; i < 4; ++i)
8330 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8331 "We can't handle any clobbers here!");
8332 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8333 "Cannot have adjacent inputs here!");
8335 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8336 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8338 // We also have to update the final source mask in this case because
8339 // it may need to undo the above swap.
8340 for (int &M : FinalSourceHalfMask)
8341 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8342 M = InputsFixed[1] + SourceOffset;
8343 else if (M == InputsFixed[1] + SourceOffset)
8344 M = (InputsFixed[0] ^ 1) + SourceOffset;
8346 InputsFixed[1] = InputsFixed[0] ^ 1;
8349 // Point everything at the fixed inputs.
8350 for (int &M : HalfMask)
8351 if (M == IncomingInputs[0])
8352 M = InputsFixed[0] + SourceOffset;
8353 else if (M == IncomingInputs[1])
8354 M = InputsFixed[1] + SourceOffset;
8356 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8357 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8360 llvm_unreachable("Unhandled input size!");
8363 // Now hoist the DWord down to the right half.
8364 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8365 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8366 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8367 for (int &M : HalfMask)
8368 for (int Input : IncomingInputs)
8370 M = FreeDWord * 2 + Input % 2;
8372 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8373 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8374 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8375 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8377 // Now enact all the shuffles we've computed to move the inputs into their
8379 if (!isNoopShuffleMask(PSHUFLMask))
8380 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8381 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8382 if (!isNoopShuffleMask(PSHUFHMask))
8383 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8384 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8385 if (!isNoopShuffleMask(PSHUFDMask))
8386 V = DAG.getNode(ISD::BITCAST, DL, VT,
8387 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8388 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8389 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8392 // At this point, each half should contain all its inputs, and we can then
8393 // just shuffle them into their final position.
8394 assert(std::count_if(LoMask.begin(), LoMask.end(),
8395 [](int M) { return M >= 4; }) == 0 &&
8396 "Failed to lift all the high half inputs to the low mask!");
8397 assert(std::count_if(HiMask.begin(), HiMask.end(),
8398 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8399 "Failed to lift all the low half inputs to the high mask!");
8401 // Do a half shuffle for the low mask.
8402 if (!isNoopShuffleMask(LoMask))
8403 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8404 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8406 // Do a half shuffle with the high mask after shifting its values down.
8407 for (int &M : HiMask)
8410 if (!isNoopShuffleMask(HiMask))
8411 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8412 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8417 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8418 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8419 SDValue V2, ArrayRef<int> Mask,
8420 SelectionDAG &DAG, bool &V1InUse,
8422 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8428 int Size = Mask.size();
8429 int Scale = 16 / Size;
8430 for (int i = 0; i < 16; ++i) {
8431 if (Mask[i / Scale] == -1) {
8432 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8434 const int ZeroMask = 0x80;
8435 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8437 int V2Idx = Mask[i / Scale] < Size
8439 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8440 if (Zeroable[i / Scale])
8441 V1Idx = V2Idx = ZeroMask;
8442 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8443 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8444 V1InUse |= (ZeroMask != V1Idx);
8445 V2InUse |= (ZeroMask != V2Idx);
8450 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8451 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8452 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8454 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8455 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8456 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8458 // If we need shuffled inputs from both, blend the two.
8460 if (V1InUse && V2InUse)
8461 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8463 V = V1InUse ? V1 : V2;
8465 // Cast the result back to the correct type.
8466 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8469 /// \brief Generic lowering of 8-lane i16 shuffles.
8471 /// This handles both single-input shuffles and combined shuffle/blends with
8472 /// two inputs. The single input shuffles are immediately delegated to
8473 /// a dedicated lowering routine.
8475 /// The blends are lowered in one of three fundamental ways. If there are few
8476 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8477 /// of the input is significantly cheaper when lowered as an interleaving of
8478 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8479 /// halves of the inputs separately (making them have relatively few inputs)
8480 /// and then concatenate them.
8481 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8482 const X86Subtarget *Subtarget,
8483 SelectionDAG &DAG) {
8485 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8486 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8487 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8488 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8489 ArrayRef<int> OrigMask = SVOp->getMask();
8490 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8491 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8492 MutableArrayRef<int> Mask(MaskStorage);
8494 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8496 // Whenever we can lower this as a zext, that instruction is strictly faster
8497 // than any alternative.
8498 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8499 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8502 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8504 auto isV2 = [](int M) { return M >= 8; };
8506 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8508 if (NumV2Inputs == 0) {
8509 // Check for being able to broadcast a single element.
8510 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8511 Mask, Subtarget, DAG))
8514 // Try to use shift instructions.
8516 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8519 // Use dedicated unpack instructions for masks that match their pattern.
8520 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8521 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8522 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8523 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8525 // Try to use byte rotation instructions.
8526 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8527 Mask, Subtarget, DAG))
8530 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8534 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8535 "All single-input shuffles should be canonicalized to be V1-input "
8538 // Try to use shift instructions.
8540 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8543 // There are special ways we can lower some single-element blends.
8544 if (NumV2Inputs == 1)
8545 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8546 Mask, Subtarget, DAG))
8549 // We have different paths for blend lowering, but they all must use the
8550 // *exact* same predicate.
8551 bool IsBlendSupported = Subtarget->hasSSE41();
8552 if (IsBlendSupported)
8553 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8557 if (SDValue Masked =
8558 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8561 // Use dedicated unpack instructions for masks that match their pattern.
8562 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8563 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8564 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8565 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8567 // Try to use byte rotation instructions.
8568 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8569 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8572 if (SDValue BitBlend =
8573 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8576 if (SDValue Unpack =
8577 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8580 // If we can't directly blend but can use PSHUFB, that will be better as it
8581 // can both shuffle and set up the inefficient blend.
8582 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8583 bool V1InUse, V2InUse;
8584 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8588 // We can always bit-blend if we have to so the fallback strategy is to
8589 // decompose into single-input permutes and blends.
8590 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8594 /// \brief Check whether a compaction lowering can be done by dropping even
8595 /// elements and compute how many times even elements must be dropped.
8597 /// This handles shuffles which take every Nth element where N is a power of
8598 /// two. Example shuffle masks:
8600 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8601 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8602 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8603 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8604 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8605 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8607 /// Any of these lanes can of course be undef.
8609 /// This routine only supports N <= 3.
8610 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8613 /// \returns N above, or the number of times even elements must be dropped if
8614 /// there is such a number. Otherwise returns zero.
8615 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8616 // Figure out whether we're looping over two inputs or just one.
8617 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8619 // The modulus for the shuffle vector entries is based on whether this is
8620 // a single input or not.
8621 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8622 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8623 "We should only be called with masks with a power-of-2 size!");
8625 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8627 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8628 // and 2^3 simultaneously. This is because we may have ambiguity with
8629 // partially undef inputs.
8630 bool ViableForN[3] = {true, true, true};
8632 for (int i = 0, e = Mask.size(); i < e; ++i) {
8633 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8638 bool IsAnyViable = false;
8639 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8640 if (ViableForN[j]) {
8643 // The shuffle mask must be equal to (i * 2^N) % M.
8644 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8647 ViableForN[j] = false;
8649 // Early exit if we exhaust the possible powers of two.
8654 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8658 // Return 0 as there is no viable power of two.
8662 /// \brief Generic lowering of v16i8 shuffles.
8664 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8665 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8666 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8667 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8669 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8670 const X86Subtarget *Subtarget,
8671 SelectionDAG &DAG) {
8673 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8674 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8675 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8676 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8677 ArrayRef<int> Mask = SVOp->getMask();
8678 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8680 // Try to use shift instructions.
8682 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8685 // Try to use byte rotation instructions.
8686 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8687 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8690 // Try to use a zext lowering.
8691 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8692 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8696 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8698 // For single-input shuffles, there are some nicer lowering tricks we can use.
8699 if (NumV2Elements == 0) {
8700 // Check for being able to broadcast a single element.
8701 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8702 Mask, Subtarget, DAG))
8705 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8706 // Notably, this handles splat and partial-splat shuffles more efficiently.
8707 // However, it only makes sense if the pre-duplication shuffle simplifies
8708 // things significantly. Currently, this means we need to be able to
8709 // express the pre-duplication shuffle as an i16 shuffle.
8711 // FIXME: We should check for other patterns which can be widened into an
8712 // i16 shuffle as well.
8713 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8714 for (int i = 0; i < 16; i += 2)
8715 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8720 auto tryToWidenViaDuplication = [&]() -> SDValue {
8721 if (!canWidenViaDuplication(Mask))
8723 SmallVector<int, 4> LoInputs;
8724 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8725 [](int M) { return M >= 0 && M < 8; });
8726 std::sort(LoInputs.begin(), LoInputs.end());
8727 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8729 SmallVector<int, 4> HiInputs;
8730 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8731 [](int M) { return M >= 8; });
8732 std::sort(HiInputs.begin(), HiInputs.end());
8733 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8736 bool TargetLo = LoInputs.size() >= HiInputs.size();
8737 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8738 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8740 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8741 SmallDenseMap<int, int, 8> LaneMap;
8742 for (int I : InPlaceInputs) {
8743 PreDupI16Shuffle[I/2] = I/2;
8746 int j = TargetLo ? 0 : 4, je = j + 4;
8747 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8748 // Check if j is already a shuffle of this input. This happens when
8749 // there are two adjacent bytes after we move the low one.
8750 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8751 // If we haven't yet mapped the input, search for a slot into which
8753 while (j < je && PreDupI16Shuffle[j] != -1)
8757 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8760 // Map this input with the i16 shuffle.
8761 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8764 // Update the lane map based on the mapping we ended up with.
8765 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8768 ISD::BITCAST, DL, MVT::v16i8,
8769 DAG.getVectorShuffle(MVT::v8i16, DL,
8770 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8771 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8773 // Unpack the bytes to form the i16s that will be shuffled into place.
8774 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8775 MVT::v16i8, V1, V1);
8777 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8778 for (int i = 0; i < 16; ++i)
8779 if (Mask[i] != -1) {
8780 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8781 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8782 if (PostDupI16Shuffle[i / 2] == -1)
8783 PostDupI16Shuffle[i / 2] = MappedMask;
8785 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8786 "Conflicting entrties in the original shuffle!");
8789 ISD::BITCAST, DL, MVT::v16i8,
8790 DAG.getVectorShuffle(MVT::v8i16, DL,
8791 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8792 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8794 if (SDValue V = tryToWidenViaDuplication())
8798 // Use dedicated unpack instructions for masks that match their pattern.
8799 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8800 0, 16, 1, 17, 2, 18, 3, 19,
8802 4, 20, 5, 21, 6, 22, 7, 23}))
8803 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8804 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8805 8, 24, 9, 25, 10, 26, 11, 27,
8807 12, 28, 13, 29, 14, 30, 15, 31}))
8808 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8810 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8811 // with PSHUFB. It is important to do this before we attempt to generate any
8812 // blends but after all of the single-input lowerings. If the single input
8813 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8814 // want to preserve that and we can DAG combine any longer sequences into
8815 // a PSHUFB in the end. But once we start blending from multiple inputs,
8816 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8817 // and there are *very* few patterns that would actually be faster than the
8818 // PSHUFB approach because of its ability to zero lanes.
8820 // FIXME: The only exceptions to the above are blends which are exact
8821 // interleavings with direct instructions supporting them. We currently don't
8822 // handle those well here.
8823 if (Subtarget->hasSSSE3()) {
8824 bool V1InUse = false;
8825 bool V2InUse = false;
8827 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8828 DAG, V1InUse, V2InUse);
8830 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8831 // do so. This avoids using them to handle blends-with-zero which is
8832 // important as a single pshufb is significantly faster for that.
8833 if (V1InUse && V2InUse) {
8834 if (Subtarget->hasSSE41())
8835 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8836 Mask, Subtarget, DAG))
8839 // We can use an unpack to do the blending rather than an or in some
8840 // cases. Even though the or may be (very minorly) more efficient, we
8841 // preference this lowering because there are common cases where part of
8842 // the complexity of the shuffles goes away when we do the final blend as
8844 // FIXME: It might be worth trying to detect if the unpack-feeding
8845 // shuffles will both be pshufb, in which case we shouldn't bother with
8847 if (SDValue Unpack =
8848 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8855 // There are special ways we can lower some single-element blends.
8856 if (NumV2Elements == 1)
8857 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8858 Mask, Subtarget, DAG))
8861 if (SDValue BitBlend =
8862 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8865 // Check whether a compaction lowering can be done. This handles shuffles
8866 // which take every Nth element for some even N. See the helper function for
8869 // We special case these as they can be particularly efficiently handled with
8870 // the PACKUSB instruction on x86 and they show up in common patterns of
8871 // rearranging bytes to truncate wide elements.
8872 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8873 // NumEvenDrops is the power of two stride of the elements. Another way of
8874 // thinking about it is that we need to drop the even elements this many
8875 // times to get the original input.
8876 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8878 // First we need to zero all the dropped bytes.
8879 assert(NumEvenDrops <= 3 &&
8880 "No support for dropping even elements more than 3 times.");
8881 // We use the mask type to pick which bytes are preserved based on how many
8882 // elements are dropped.
8883 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8884 SDValue ByteClearMask =
8885 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8886 DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8887 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8889 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8891 // Now pack things back together.
8892 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8893 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8894 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8895 for (int i = 1; i < NumEvenDrops; ++i) {
8896 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8897 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8903 // Handle multi-input cases by blending single-input shuffles.
8904 if (NumV2Elements > 0)
8905 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8908 // The fallback path for single-input shuffles widens this into two v8i16
8909 // vectors with unpacks, shuffles those, and then pulls them back together
8913 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8914 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8915 for (int i = 0; i < 16; ++i)
8917 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8919 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8921 SDValue VLoHalf, VHiHalf;
8922 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8923 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8925 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8926 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8927 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8928 [](int M) { return M >= 0 && M % 2 == 1; })) {
8929 // Use a mask to drop the high bytes.
8930 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8931 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8932 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8934 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8935 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8937 // Squash the masks to point directly into VLoHalf.
8938 for (int &M : LoBlendMask)
8941 for (int &M : HiBlendMask)
8945 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8946 // VHiHalf so that we can blend them as i16s.
8947 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8948 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8949 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8950 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8953 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8954 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8956 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8959 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8961 /// This routine breaks down the specific type of 128-bit shuffle and
8962 /// dispatches to the lowering routines accordingly.
8963 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8964 MVT VT, const X86Subtarget *Subtarget,
8965 SelectionDAG &DAG) {
8966 switch (VT.SimpleTy) {
8968 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8970 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8972 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8974 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8976 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8978 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8981 llvm_unreachable("Unimplemented!");
8985 /// \brief Helper function to test whether a shuffle mask could be
8986 /// simplified by widening the elements being shuffled.
8988 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8989 /// leaves it in an unspecified state.
8991 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8992 /// shuffle masks. The latter have the special property of a '-2' representing
8993 /// a zero-ed lane of a vector.
8994 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8995 SmallVectorImpl<int> &WidenedMask) {
8996 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8997 // If both elements are undef, its trivial.
8998 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8999 WidenedMask.push_back(SM_SentinelUndef);
9003 // Check for an undef mask and a mask value properly aligned to fit with
9004 // a pair of values. If we find such a case, use the non-undef mask's value.
9005 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9006 WidenedMask.push_back(Mask[i + 1] / 2);
9009 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9010 WidenedMask.push_back(Mask[i] / 2);
9014 // When zeroing, we need to spread the zeroing across both lanes to widen.
9015 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9016 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9017 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9018 WidenedMask.push_back(SM_SentinelZero);
9024 // Finally check if the two mask values are adjacent and aligned with
9026 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9027 WidenedMask.push_back(Mask[i] / 2);
9031 // Otherwise we can't safely widen the elements used in this shuffle.
9034 assert(WidenedMask.size() == Mask.size() / 2 &&
9035 "Incorrect size of mask after widening the elements!");
9040 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9042 /// This routine just extracts two subvectors, shuffles them independently, and
9043 /// then concatenates them back together. This should work effectively with all
9044 /// AVX vector shuffle types.
9045 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9046 SDValue V2, ArrayRef<int> Mask,
9047 SelectionDAG &DAG) {
9048 assert(VT.getSizeInBits() >= 256 &&
9049 "Only for 256-bit or wider vector shuffles!");
9050 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9051 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9053 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9054 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9056 int NumElements = VT.getVectorNumElements();
9057 int SplitNumElements = NumElements / 2;
9058 MVT ScalarVT = VT.getScalarType();
9059 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9061 // Rather than splitting build-vectors, just build two narrower build
9062 // vectors. This helps shuffling with splats and zeros.
9063 auto SplitVector = [&](SDValue V) {
9064 while (V.getOpcode() == ISD::BITCAST)
9065 V = V->getOperand(0);
9067 MVT OrigVT = V.getSimpleValueType();
9068 int OrigNumElements = OrigVT.getVectorNumElements();
9069 int OrigSplitNumElements = OrigNumElements / 2;
9070 MVT OrigScalarVT = OrigVT.getScalarType();
9071 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9075 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9077 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9078 DAG.getIntPtrConstant(0, DL));
9079 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9080 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9083 SmallVector<SDValue, 16> LoOps, HiOps;
9084 for (int i = 0; i < OrigSplitNumElements; ++i) {
9085 LoOps.push_back(BV->getOperand(i));
9086 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9088 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9089 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9091 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
9092 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
9095 SDValue LoV1, HiV1, LoV2, HiV2;
9096 std::tie(LoV1, HiV1) = SplitVector(V1);
9097 std::tie(LoV2, HiV2) = SplitVector(V2);
9099 // Now create two 4-way blends of these half-width vectors.
9100 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9101 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9102 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9103 for (int i = 0; i < SplitNumElements; ++i) {
9104 int M = HalfMask[i];
9105 if (M >= NumElements) {
9106 if (M >= NumElements + SplitNumElements)
9110 V2BlendMask.push_back(M - NumElements);
9111 V1BlendMask.push_back(-1);
9112 BlendMask.push_back(SplitNumElements + i);
9113 } else if (M >= 0) {
9114 if (M >= SplitNumElements)
9118 V2BlendMask.push_back(-1);
9119 V1BlendMask.push_back(M);
9120 BlendMask.push_back(i);
9122 V2BlendMask.push_back(-1);
9123 V1BlendMask.push_back(-1);
9124 BlendMask.push_back(-1);
9128 // Because the lowering happens after all combining takes place, we need to
9129 // manually combine these blend masks as much as possible so that we create
9130 // a minimal number of high-level vector shuffle nodes.
9132 // First try just blending the halves of V1 or V2.
9133 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9134 return DAG.getUNDEF(SplitVT);
9135 if (!UseLoV2 && !UseHiV2)
9136 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9137 if (!UseLoV1 && !UseHiV1)
9138 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9140 SDValue V1Blend, V2Blend;
9141 if (UseLoV1 && UseHiV1) {
9143 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9145 // We only use half of V1 so map the usage down into the final blend mask.
9146 V1Blend = UseLoV1 ? LoV1 : HiV1;
9147 for (int i = 0; i < SplitNumElements; ++i)
9148 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9149 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9151 if (UseLoV2 && UseHiV2) {
9153 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9155 // We only use half of V2 so map the usage down into the final blend mask.
9156 V2Blend = UseLoV2 ? LoV2 : HiV2;
9157 for (int i = 0; i < SplitNumElements; ++i)
9158 if (BlendMask[i] >= SplitNumElements)
9159 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9161 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9163 SDValue Lo = HalfBlend(LoMask);
9164 SDValue Hi = HalfBlend(HiMask);
9165 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9168 /// \brief Either split a vector in halves or decompose the shuffles and the
9171 /// This is provided as a good fallback for many lowerings of non-single-input
9172 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9173 /// between splitting the shuffle into 128-bit components and stitching those
9174 /// back together vs. extracting the single-input shuffles and blending those
9176 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9177 SDValue V2, ArrayRef<int> Mask,
9178 SelectionDAG &DAG) {
9179 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9180 "lower single-input shuffles as it "
9181 "could then recurse on itself.");
9182 int Size = Mask.size();
9184 // If this can be modeled as a broadcast of two elements followed by a blend,
9185 // prefer that lowering. This is especially important because broadcasts can
9186 // often fold with memory operands.
9187 auto DoBothBroadcast = [&] {
9188 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9191 if (V2BroadcastIdx == -1)
9192 V2BroadcastIdx = M - Size;
9193 else if (M - Size != V2BroadcastIdx)
9195 } else if (M >= 0) {
9196 if (V1BroadcastIdx == -1)
9198 else if (M != V1BroadcastIdx)
9203 if (DoBothBroadcast())
9204 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9207 // If the inputs all stem from a single 128-bit lane of each input, then we
9208 // split them rather than blending because the split will decompose to
9209 // unusually few instructions.
9210 int LaneCount = VT.getSizeInBits() / 128;
9211 int LaneSize = Size / LaneCount;
9212 SmallBitVector LaneInputs[2];
9213 LaneInputs[0].resize(LaneCount, false);
9214 LaneInputs[1].resize(LaneCount, false);
9215 for (int i = 0; i < Size; ++i)
9217 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9218 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9219 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9221 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9222 // that the decomposed single-input shuffles don't end up here.
9223 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9226 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9227 /// a permutation and blend of those lanes.
9229 /// This essentially blends the out-of-lane inputs to each lane into the lane
9230 /// from a permuted copy of the vector. This lowering strategy results in four
9231 /// instructions in the worst case for a single-input cross lane shuffle which
9232 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9233 /// of. Special cases for each particular shuffle pattern should be handled
9234 /// prior to trying this lowering.
9235 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9236 SDValue V1, SDValue V2,
9238 SelectionDAG &DAG) {
9239 // FIXME: This should probably be generalized for 512-bit vectors as well.
9240 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9241 int LaneSize = Mask.size() / 2;
9243 // If there are only inputs from one 128-bit lane, splitting will in fact be
9244 // less expensive. The flags track whether the given lane contains an element
9245 // that crosses to another lane.
9246 bool LaneCrossing[2] = {false, false};
9247 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9248 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9249 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9250 if (!LaneCrossing[0] || !LaneCrossing[1])
9251 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9253 if (isSingleInputShuffleMask(Mask)) {
9254 SmallVector<int, 32> FlippedBlendMask;
9255 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9256 FlippedBlendMask.push_back(
9257 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9259 : Mask[i] % LaneSize +
9260 (i / LaneSize) * LaneSize + Size));
9262 // Flip the vector, and blend the results which should now be in-lane. The
9263 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9264 // 5 for the high source. The value 3 selects the high half of source 2 and
9265 // the value 2 selects the low half of source 2. We only use source 2 to
9266 // allow folding it into a memory operand.
9267 unsigned PERMMask = 3 | 2 << 4;
9268 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9269 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9270 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9273 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9274 // will be handled by the above logic and a blend of the results, much like
9275 // other patterns in AVX.
9276 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9279 /// \brief Handle lowering 2-lane 128-bit shuffles.
9280 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9281 SDValue V2, ArrayRef<int> Mask,
9282 const X86Subtarget *Subtarget,
9283 SelectionDAG &DAG) {
9284 // TODO: If minimizing size and one of the inputs is a zero vector and the
9285 // the zero vector has only one use, we could use a VPERM2X128 to save the
9286 // instruction bytes needed to explicitly generate the zero vector.
9288 // Blends are faster and handle all the non-lane-crossing cases.
9289 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9293 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9294 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9296 // If either input operand is a zero vector, use VPERM2X128 because its mask
9297 // allows us to replace the zero input with an implicit zero.
9298 if (!IsV1Zero && !IsV2Zero) {
9299 // Check for patterns which can be matched with a single insert of a 128-bit
9301 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9302 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9303 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9304 VT.getVectorNumElements() / 2);
9305 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9306 DAG.getIntPtrConstant(0, DL));
9307 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9308 OnlyUsesV1 ? V1 : V2,
9309 DAG.getIntPtrConstant(0, DL));
9310 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9314 // Otherwise form a 128-bit permutation. After accounting for undefs,
9315 // convert the 64-bit shuffle mask selection values into 128-bit
9316 // selection bits by dividing the indexes by 2 and shifting into positions
9317 // defined by a vperm2*128 instruction's immediate control byte.
9319 // The immediate permute control byte looks like this:
9320 // [1:0] - select 128 bits from sources for low half of destination
9322 // [3] - zero low half of destination
9323 // [5:4] - select 128 bits from sources for high half of destination
9325 // [7] - zero high half of destination
9327 int MaskLO = Mask[0];
9328 if (MaskLO == SM_SentinelUndef)
9329 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9331 int MaskHI = Mask[2];
9332 if (MaskHI == SM_SentinelUndef)
9333 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9335 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9337 // If either input is a zero vector, replace it with an undef input.
9338 // Shuffle mask values < 4 are selecting elements of V1.
9339 // Shuffle mask values >= 4 are selecting elements of V2.
9340 // Adjust each half of the permute mask by clearing the half that was
9341 // selecting the zero vector and setting the zero mask bit.
9343 V1 = DAG.getUNDEF(VT);
9345 PermMask = (PermMask & 0xf0) | 0x08;
9347 PermMask = (PermMask & 0x0f) | 0x80;
9350 V2 = DAG.getUNDEF(VT);
9352 PermMask = (PermMask & 0xf0) | 0x08;
9354 PermMask = (PermMask & 0x0f) | 0x80;
9357 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9358 DAG.getConstant(PermMask, DL, MVT::i8));
9361 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9362 /// shuffling each lane.
9364 /// This will only succeed when the result of fixing the 128-bit lanes results
9365 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9366 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9367 /// the lane crosses early and then use simpler shuffles within each lane.
9369 /// FIXME: It might be worthwhile at some point to support this without
9370 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9371 /// in x86 only floating point has interesting non-repeating shuffles, and even
9372 /// those are still *marginally* more expensive.
9373 static SDValue lowerVectorShuffleByMerging128BitLanes(
9374 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9375 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9376 assert(!isSingleInputShuffleMask(Mask) &&
9377 "This is only useful with multiple inputs.");
9379 int Size = Mask.size();
9380 int LaneSize = 128 / VT.getScalarSizeInBits();
9381 int NumLanes = Size / LaneSize;
9382 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9384 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9385 // check whether the in-128-bit lane shuffles share a repeating pattern.
9386 SmallVector<int, 4> Lanes;
9387 Lanes.resize(NumLanes, -1);
9388 SmallVector<int, 4> InLaneMask;
9389 InLaneMask.resize(LaneSize, -1);
9390 for (int i = 0; i < Size; ++i) {
9394 int j = i / LaneSize;
9397 // First entry we've seen for this lane.
9398 Lanes[j] = Mask[i] / LaneSize;
9399 } else if (Lanes[j] != Mask[i] / LaneSize) {
9400 // This doesn't match the lane selected previously!
9404 // Check that within each lane we have a consistent shuffle mask.
9405 int k = i % LaneSize;
9406 if (InLaneMask[k] < 0) {
9407 InLaneMask[k] = Mask[i] % LaneSize;
9408 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9409 // This doesn't fit a repeating in-lane mask.
9414 // First shuffle the lanes into place.
9415 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9416 VT.getSizeInBits() / 64);
9417 SmallVector<int, 8> LaneMask;
9418 LaneMask.resize(NumLanes * 2, -1);
9419 for (int i = 0; i < NumLanes; ++i)
9420 if (Lanes[i] >= 0) {
9421 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9422 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9425 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9426 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9427 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9429 // Cast it back to the type we actually want.
9430 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9432 // Now do a simple shuffle that isn't lane crossing.
9433 SmallVector<int, 8> NewMask;
9434 NewMask.resize(Size, -1);
9435 for (int i = 0; i < Size; ++i)
9437 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9438 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9439 "Must not introduce lane crosses at this point!");
9441 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9444 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9447 /// This returns true if the elements from a particular input are already in the
9448 /// slot required by the given mask and require no permutation.
9449 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9450 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9451 int Size = Mask.size();
9452 for (int i = 0; i < Size; ++i)
9453 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9459 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9461 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9462 /// isn't available.
9463 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9464 const X86Subtarget *Subtarget,
9465 SelectionDAG &DAG) {
9467 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9468 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9469 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9470 ArrayRef<int> Mask = SVOp->getMask();
9471 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9473 SmallVector<int, 4> WidenedMask;
9474 if (canWidenShuffleElements(Mask, WidenedMask))
9475 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9478 if (isSingleInputShuffleMask(Mask)) {
9479 // Check for being able to broadcast a single element.
9480 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9481 Mask, Subtarget, DAG))
9484 // Use low duplicate instructions for masks that match their pattern.
9485 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9486 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9488 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9489 // Non-half-crossing single input shuffles can be lowerid with an
9490 // interleaved permutation.
9491 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9492 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9493 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9494 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9497 // With AVX2 we have direct support for this permutation.
9498 if (Subtarget->hasAVX2())
9499 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9500 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9502 // Otherwise, fall back.
9503 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9507 // X86 has dedicated unpack instructions that can handle specific blend
9508 // operations: UNPCKH and UNPCKL.
9509 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9510 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9511 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9512 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9513 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9514 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9515 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9516 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9518 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9522 // Check if the blend happens to exactly fit that of SHUFPD.
9523 if ((Mask[0] == -1 || Mask[0] < 2) &&
9524 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9525 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9526 (Mask[3] == -1 || Mask[3] >= 6)) {
9527 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9528 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9529 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9530 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9532 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9533 (Mask[1] == -1 || Mask[1] < 2) &&
9534 (Mask[2] == -1 || Mask[2] >= 6) &&
9535 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9536 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9537 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9538 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9539 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9542 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9543 // shuffle. However, if we have AVX2 and either inputs are already in place,
9544 // we will be able to shuffle even across lanes the other input in a single
9545 // instruction so skip this pattern.
9546 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9547 isShuffleMaskInputInPlace(1, Mask))))
9548 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9549 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9552 // If we have AVX2 then we always want to lower with a blend because an v4 we
9553 // can fully permute the elements.
9554 if (Subtarget->hasAVX2())
9555 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9558 // Otherwise fall back on generic lowering.
9559 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9562 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9564 /// This routine is only called when we have AVX2 and thus a reasonable
9565 /// instruction set for v4i64 shuffling..
9566 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9567 const X86Subtarget *Subtarget,
9568 SelectionDAG &DAG) {
9570 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9571 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9573 ArrayRef<int> Mask = SVOp->getMask();
9574 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9575 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9577 SmallVector<int, 4> WidenedMask;
9578 if (canWidenShuffleElements(Mask, WidenedMask))
9579 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9582 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9586 // Check for being able to broadcast a single element.
9587 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9588 Mask, Subtarget, DAG))
9591 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9592 // use lower latency instructions that will operate on both 128-bit lanes.
9593 SmallVector<int, 2> RepeatedMask;
9594 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9595 if (isSingleInputShuffleMask(Mask)) {
9596 int PSHUFDMask[] = {-1, -1, -1, -1};
9597 for (int i = 0; i < 2; ++i)
9598 if (RepeatedMask[i] >= 0) {
9599 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9600 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9603 ISD::BITCAST, DL, MVT::v4i64,
9604 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9605 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9606 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9610 // AVX2 provides a direct instruction for permuting a single input across
9612 if (isSingleInputShuffleMask(Mask))
9613 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9614 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9616 // Try to use shift instructions.
9618 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9621 // Use dedicated unpack instructions for masks that match their pattern.
9622 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9623 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9624 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9625 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9626 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9627 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9628 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9629 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9631 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9632 // shuffle. However, if we have AVX2 and either inputs are already in place,
9633 // we will be able to shuffle even across lanes the other input in a single
9634 // instruction so skip this pattern.
9635 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9636 isShuffleMaskInputInPlace(1, Mask))))
9637 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9638 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9641 // Otherwise fall back on generic blend lowering.
9642 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9646 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9648 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9649 /// isn't available.
9650 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9651 const X86Subtarget *Subtarget,
9652 SelectionDAG &DAG) {
9654 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9655 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9656 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9657 ArrayRef<int> Mask = SVOp->getMask();
9658 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9660 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9664 // Check for being able to broadcast a single element.
9665 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9666 Mask, Subtarget, DAG))
9669 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9670 // options to efficiently lower the shuffle.
9671 SmallVector<int, 4> RepeatedMask;
9672 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9673 assert(RepeatedMask.size() == 4 &&
9674 "Repeated masks must be half the mask width!");
9676 // Use even/odd duplicate instructions for masks that match their pattern.
9677 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9678 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9679 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9680 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9682 if (isSingleInputShuffleMask(Mask))
9683 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9684 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9686 // Use dedicated unpack instructions for masks that match their pattern.
9687 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9688 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9689 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9690 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9691 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9692 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9693 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9694 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9696 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9697 // have already handled any direct blends. We also need to squash the
9698 // repeated mask into a simulated v4f32 mask.
9699 for (int i = 0; i < 4; ++i)
9700 if (RepeatedMask[i] >= 8)
9701 RepeatedMask[i] -= 4;
9702 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9705 // If we have a single input shuffle with different shuffle patterns in the
9706 // two 128-bit lanes use the variable mask to VPERMILPS.
9707 if (isSingleInputShuffleMask(Mask)) {
9708 SDValue VPermMask[8];
9709 for (int i = 0; i < 8; ++i)
9710 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9711 : DAG.getConstant(Mask[i], DL, MVT::i32);
9712 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9714 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9715 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9717 if (Subtarget->hasAVX2())
9718 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9719 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9720 DAG.getNode(ISD::BUILD_VECTOR, DL,
9721 MVT::v8i32, VPermMask)),
9724 // Otherwise, fall back.
9725 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9729 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9731 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9732 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9735 // If we have AVX2 then we always want to lower with a blend because at v8 we
9736 // can fully permute the elements.
9737 if (Subtarget->hasAVX2())
9738 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9741 // Otherwise fall back on generic lowering.
9742 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9745 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9747 /// This routine is only called when we have AVX2 and thus a reasonable
9748 /// instruction set for v8i32 shuffling..
9749 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9750 const X86Subtarget *Subtarget,
9751 SelectionDAG &DAG) {
9753 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9754 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9755 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9756 ArrayRef<int> Mask = SVOp->getMask();
9757 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9758 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9760 // Whenever we can lower this as a zext, that instruction is strictly faster
9761 // than any alternative. It also allows us to fold memory operands into the
9762 // shuffle in many cases.
9763 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9764 Mask, Subtarget, DAG))
9767 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9771 // Check for being able to broadcast a single element.
9772 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9773 Mask, Subtarget, DAG))
9776 // If the shuffle mask is repeated in each 128-bit lane we can use more
9777 // efficient instructions that mirror the shuffles across the two 128-bit
9779 SmallVector<int, 4> RepeatedMask;
9780 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9781 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9782 if (isSingleInputShuffleMask(Mask))
9783 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9784 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9786 // Use dedicated unpack instructions for masks that match their pattern.
9787 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9788 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9789 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9790 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9791 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9792 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9793 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9794 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9797 // Try to use shift instructions.
9799 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9802 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9803 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9806 // If the shuffle patterns aren't repeated but it is a single input, directly
9807 // generate a cross-lane VPERMD instruction.
9808 if (isSingleInputShuffleMask(Mask)) {
9809 SDValue VPermMask[8];
9810 for (int i = 0; i < 8; ++i)
9811 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9812 : DAG.getConstant(Mask[i], DL, MVT::i32);
9814 X86ISD::VPERMV, DL, MVT::v8i32,
9815 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9818 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9820 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9821 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9824 // Otherwise fall back on generic blend lowering.
9825 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9829 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9831 /// This routine is only called when we have AVX2 and thus a reasonable
9832 /// instruction set for v16i16 shuffling..
9833 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9834 const X86Subtarget *Subtarget,
9835 SelectionDAG &DAG) {
9837 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9838 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9839 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9840 ArrayRef<int> Mask = SVOp->getMask();
9841 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9842 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9844 // Whenever we can lower this as a zext, that instruction is strictly faster
9845 // than any alternative. It also allows us to fold memory operands into the
9846 // shuffle in many cases.
9847 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9848 Mask, Subtarget, DAG))
9851 // Check for being able to broadcast a single element.
9852 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9853 Mask, Subtarget, DAG))
9856 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9860 // Use dedicated unpack instructions for masks that match their pattern.
9861 if (isShuffleEquivalent(V1, V2, Mask,
9862 {// First 128-bit lane:
9863 0, 16, 1, 17, 2, 18, 3, 19,
9864 // Second 128-bit lane:
9865 8, 24, 9, 25, 10, 26, 11, 27}))
9866 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9867 if (isShuffleEquivalent(V1, V2, Mask,
9868 {// First 128-bit lane:
9869 4, 20, 5, 21, 6, 22, 7, 23,
9870 // Second 128-bit lane:
9871 12, 28, 13, 29, 14, 30, 15, 31}))
9872 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9874 // Try to use shift instructions.
9876 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9879 // Try to use byte rotation instructions.
9880 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9881 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9884 if (isSingleInputShuffleMask(Mask)) {
9885 // There are no generalized cross-lane shuffle operations available on i16
9887 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9888 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9891 SmallVector<int, 8> RepeatedMask;
9892 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9893 // As this is a single-input shuffle, the repeated mask should be
9894 // a strictly valid v8i16 mask that we can pass through to the v8i16
9895 // lowering to handle even the v16 case.
9896 return lowerV8I16GeneralSingleInputVectorShuffle(
9897 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9900 SDValue PSHUFBMask[32];
9901 for (int i = 0; i < 16; ++i) {
9902 if (Mask[i] == -1) {
9903 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9907 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9908 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9909 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9910 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9913 ISD::BITCAST, DL, MVT::v16i16,
9915 X86ISD::PSHUFB, DL, MVT::v32i8,
9916 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9917 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9920 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9922 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9923 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9926 // Otherwise fall back on generic lowering.
9927 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9930 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9932 /// This routine is only called when we have AVX2 and thus a reasonable
9933 /// instruction set for v32i8 shuffling..
9934 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9935 const X86Subtarget *Subtarget,
9936 SelectionDAG &DAG) {
9938 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9939 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9940 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9941 ArrayRef<int> Mask = SVOp->getMask();
9942 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9943 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9945 // Whenever we can lower this as a zext, that instruction is strictly faster
9946 // than any alternative. It also allows us to fold memory operands into the
9947 // shuffle in many cases.
9948 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9949 Mask, Subtarget, DAG))
9952 // Check for being able to broadcast a single element.
9953 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9954 Mask, Subtarget, DAG))
9957 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9961 // Use dedicated unpack instructions for masks that match their pattern.
9962 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9964 if (isShuffleEquivalent(
9966 {// First 128-bit lane:
9967 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9968 // Second 128-bit lane:
9969 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9970 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9971 if (isShuffleEquivalent(
9973 {// First 128-bit lane:
9974 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9975 // Second 128-bit lane:
9976 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9977 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9979 // Try to use shift instructions.
9981 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9984 // Try to use byte rotation instructions.
9985 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9986 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9989 if (isSingleInputShuffleMask(Mask)) {
9990 // There are no generalized cross-lane shuffle operations available on i8
9992 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9993 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9996 SDValue PSHUFBMask[32];
9997 for (int i = 0; i < 32; ++i)
10000 ? DAG.getUNDEF(MVT::i8)
10001 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10004 return DAG.getNode(
10005 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10006 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10009 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10011 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10012 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10015 // Otherwise fall back on generic lowering.
10016 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10019 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10021 /// This routine either breaks down the specific type of a 256-bit x86 vector
10022 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10023 /// together based on the available instructions.
10024 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10025 MVT VT, const X86Subtarget *Subtarget,
10026 SelectionDAG &DAG) {
10028 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10029 ArrayRef<int> Mask = SVOp->getMask();
10031 // If we have a single input to the zero element, insert that into V1 if we
10032 // can do so cheaply.
10033 int NumElts = VT.getVectorNumElements();
10034 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10035 return M >= NumElts;
10038 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10039 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10040 DL, VT, V1, V2, Mask, Subtarget, DAG))
10043 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10044 // check for those subtargets here and avoid much of the subtarget querying in
10045 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10046 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10047 // floating point types there eventually, just immediately cast everything to
10048 // a float and operate entirely in that domain.
10049 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10050 int ElementBits = VT.getScalarSizeInBits();
10051 if (ElementBits < 32)
10052 // No floating point type available, decompose into 128-bit vectors.
10053 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10055 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10056 VT.getVectorNumElements());
10057 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10058 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10059 return DAG.getNode(ISD::BITCAST, DL, VT,
10060 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10063 switch (VT.SimpleTy) {
10065 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10067 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10069 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10071 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10073 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10075 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10078 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10082 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10083 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10084 const X86Subtarget *Subtarget,
10085 SelectionDAG &DAG) {
10087 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10088 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10089 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10090 ArrayRef<int> Mask = SVOp->getMask();
10091 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10093 // X86 has dedicated unpack instructions that can handle specific blend
10094 // operations: UNPCKH and UNPCKL.
10095 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10096 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10097 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10098 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10100 // FIXME: Implement direct support for this type!
10101 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10104 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10105 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10106 const X86Subtarget *Subtarget,
10107 SelectionDAG &DAG) {
10109 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10110 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10111 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10112 ArrayRef<int> Mask = SVOp->getMask();
10113 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10115 // Use dedicated unpack instructions for masks that match their pattern.
10116 if (isShuffleEquivalent(V1, V2, Mask,
10117 {// First 128-bit lane.
10118 0, 16, 1, 17, 4, 20, 5, 21,
10119 // Second 128-bit lane.
10120 8, 24, 9, 25, 12, 28, 13, 29}))
10121 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10122 if (isShuffleEquivalent(V1, V2, Mask,
10123 {// First 128-bit lane.
10124 2, 18, 3, 19, 6, 22, 7, 23,
10125 // Second 128-bit lane.
10126 10, 26, 11, 27, 14, 30, 15, 31}))
10127 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10129 // FIXME: Implement direct support for this type!
10130 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10133 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10134 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10135 const X86Subtarget *Subtarget,
10136 SelectionDAG &DAG) {
10138 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10139 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10140 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10141 ArrayRef<int> Mask = SVOp->getMask();
10142 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10144 // X86 has dedicated unpack instructions that can handle specific blend
10145 // operations: UNPCKH and UNPCKL.
10146 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10147 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10148 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10149 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10151 // FIXME: Implement direct support for this type!
10152 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10155 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10156 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10157 const X86Subtarget *Subtarget,
10158 SelectionDAG &DAG) {
10160 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10161 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10162 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10163 ArrayRef<int> Mask = SVOp->getMask();
10164 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10166 // Use dedicated unpack instructions for masks that match their pattern.
10167 if (isShuffleEquivalent(V1, V2, Mask,
10168 {// First 128-bit lane.
10169 0, 16, 1, 17, 4, 20, 5, 21,
10170 // Second 128-bit lane.
10171 8, 24, 9, 25, 12, 28, 13, 29}))
10172 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10173 if (isShuffleEquivalent(V1, V2, Mask,
10174 {// First 128-bit lane.
10175 2, 18, 3, 19, 6, 22, 7, 23,
10176 // Second 128-bit lane.
10177 10, 26, 11, 27, 14, 30, 15, 31}))
10178 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10180 // FIXME: Implement direct support for this type!
10181 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10184 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10185 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10186 const X86Subtarget *Subtarget,
10187 SelectionDAG &DAG) {
10189 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10190 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10191 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10192 ArrayRef<int> Mask = SVOp->getMask();
10193 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10194 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10196 // FIXME: Implement direct support for this type!
10197 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10200 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10201 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10202 const X86Subtarget *Subtarget,
10203 SelectionDAG &DAG) {
10205 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10206 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10207 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10208 ArrayRef<int> Mask = SVOp->getMask();
10209 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10210 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10212 // FIXME: Implement direct support for this type!
10213 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10216 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10218 /// This routine either breaks down the specific type of a 512-bit x86 vector
10219 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10220 /// together based on the available instructions.
10221 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10222 MVT VT, const X86Subtarget *Subtarget,
10223 SelectionDAG &DAG) {
10225 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10226 ArrayRef<int> Mask = SVOp->getMask();
10227 assert(Subtarget->hasAVX512() &&
10228 "Cannot lower 512-bit vectors w/ basic ISA!");
10230 // Check for being able to broadcast a single element.
10231 if (SDValue Broadcast =
10232 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10235 // Dispatch to each element type for lowering. If we don't have supprot for
10236 // specific element type shuffles at 512 bits, immediately split them and
10237 // lower them. Each lowering routine of a given type is allowed to assume that
10238 // the requisite ISA extensions for that element type are available.
10239 switch (VT.SimpleTy) {
10241 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10243 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10245 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10247 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10249 if (Subtarget->hasBWI())
10250 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10253 if (Subtarget->hasBWI())
10254 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10258 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10261 // Otherwise fall back on splitting.
10262 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10265 /// \brief Top-level lowering for x86 vector shuffles.
10267 /// This handles decomposition, canonicalization, and lowering of all x86
10268 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10269 /// above in helper routines. The canonicalization attempts to widen shuffles
10270 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10271 /// s.t. only one of the two inputs needs to be tested, etc.
10272 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10273 SelectionDAG &DAG) {
10274 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10275 ArrayRef<int> Mask = SVOp->getMask();
10276 SDValue V1 = Op.getOperand(0);
10277 SDValue V2 = Op.getOperand(1);
10278 MVT VT = Op.getSimpleValueType();
10279 int NumElements = VT.getVectorNumElements();
10282 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10284 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10285 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10286 if (V1IsUndef && V2IsUndef)
10287 return DAG.getUNDEF(VT);
10289 // When we create a shuffle node we put the UNDEF node to second operand,
10290 // but in some cases the first operand may be transformed to UNDEF.
10291 // In this case we should just commute the node.
10293 return DAG.getCommutedVectorShuffle(*SVOp);
10295 // Check for non-undef masks pointing at an undef vector and make the masks
10296 // undef as well. This makes it easier to match the shuffle based solely on
10300 if (M >= NumElements) {
10301 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10302 for (int &M : NewMask)
10303 if (M >= NumElements)
10305 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10308 // We actually see shuffles that are entirely re-arrangements of a set of
10309 // zero inputs. This mostly happens while decomposing complex shuffles into
10310 // simple ones. Directly lower these as a buildvector of zeros.
10311 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10312 if (Zeroable.all())
10313 return getZeroVector(VT, Subtarget, DAG, dl);
10315 // Try to collapse shuffles into using a vector type with fewer elements but
10316 // wider element types. We cap this to not form integers or floating point
10317 // elements wider than 64 bits, but it might be interesting to form i128
10318 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10319 SmallVector<int, 16> WidenedMask;
10320 if (VT.getScalarSizeInBits() < 64 &&
10321 canWidenShuffleElements(Mask, WidenedMask)) {
10322 MVT NewEltVT = VT.isFloatingPoint()
10323 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10324 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10325 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10326 // Make sure that the new vector type is legal. For example, v2f64 isn't
10328 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10329 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10330 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10331 return DAG.getNode(ISD::BITCAST, dl, VT,
10332 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10336 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10337 for (int M : SVOp->getMask())
10339 ++NumUndefElements;
10340 else if (M < NumElements)
10345 // Commute the shuffle as needed such that more elements come from V1 than
10346 // V2. This allows us to match the shuffle pattern strictly on how many
10347 // elements come from V1 without handling the symmetric cases.
10348 if (NumV2Elements > NumV1Elements)
10349 return DAG.getCommutedVectorShuffle(*SVOp);
10351 // When the number of V1 and V2 elements are the same, try to minimize the
10352 // number of uses of V2 in the low half of the vector. When that is tied,
10353 // ensure that the sum of indices for V1 is equal to or lower than the sum
10354 // indices for V2. When those are equal, try to ensure that the number of odd
10355 // indices for V1 is lower than the number of odd indices for V2.
10356 if (NumV1Elements == NumV2Elements) {
10357 int LowV1Elements = 0, LowV2Elements = 0;
10358 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10359 if (M >= NumElements)
10363 if (LowV2Elements > LowV1Elements) {
10364 return DAG.getCommutedVectorShuffle(*SVOp);
10365 } else if (LowV2Elements == LowV1Elements) {
10366 int SumV1Indices = 0, SumV2Indices = 0;
10367 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10368 if (SVOp->getMask()[i] >= NumElements)
10370 else if (SVOp->getMask()[i] >= 0)
10372 if (SumV2Indices < SumV1Indices) {
10373 return DAG.getCommutedVectorShuffle(*SVOp);
10374 } else if (SumV2Indices == SumV1Indices) {
10375 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10376 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10377 if (SVOp->getMask()[i] >= NumElements)
10378 NumV2OddIndices += i % 2;
10379 else if (SVOp->getMask()[i] >= 0)
10380 NumV1OddIndices += i % 2;
10381 if (NumV2OddIndices < NumV1OddIndices)
10382 return DAG.getCommutedVectorShuffle(*SVOp);
10387 // For each vector width, delegate to a specialized lowering routine.
10388 if (VT.getSizeInBits() == 128)
10389 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10391 if (VT.getSizeInBits() == 256)
10392 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10394 // Force AVX-512 vectors to be scalarized for now.
10395 // FIXME: Implement AVX-512 support!
10396 if (VT.getSizeInBits() == 512)
10397 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10399 llvm_unreachable("Unimplemented!");
10402 // This function assumes its argument is a BUILD_VECTOR of constants or
10403 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10405 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10406 unsigned &MaskValue) {
10408 unsigned NumElems = BuildVector->getNumOperands();
10409 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10410 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10411 unsigned NumElemsInLane = NumElems / NumLanes;
10413 // Blend for v16i16 should be symetric for the both lanes.
10414 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10415 SDValue EltCond = BuildVector->getOperand(i);
10416 SDValue SndLaneEltCond =
10417 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10419 int Lane1Cond = -1, Lane2Cond = -1;
10420 if (isa<ConstantSDNode>(EltCond))
10421 Lane1Cond = !isZero(EltCond);
10422 if (isa<ConstantSDNode>(SndLaneEltCond))
10423 Lane2Cond = !isZero(SndLaneEltCond);
10425 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10426 // Lane1Cond != 0, means we want the first argument.
10427 // Lane1Cond == 0, means we want the second argument.
10428 // The encoding of this argument is 0 for the first argument, 1
10429 // for the second. Therefore, invert the condition.
10430 MaskValue |= !Lane1Cond << i;
10431 else if (Lane1Cond < 0)
10432 MaskValue |= !Lane2Cond << i;
10439 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10440 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10441 const X86Subtarget *Subtarget,
10442 SelectionDAG &DAG) {
10443 SDValue Cond = Op.getOperand(0);
10444 SDValue LHS = Op.getOperand(1);
10445 SDValue RHS = Op.getOperand(2);
10447 MVT VT = Op.getSimpleValueType();
10449 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10451 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10453 // Only non-legal VSELECTs reach this lowering, convert those into generic
10454 // shuffles and re-use the shuffle lowering path for blends.
10455 SmallVector<int, 32> Mask;
10456 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10457 SDValue CondElt = CondBV->getOperand(i);
10459 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10461 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10464 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10465 // A vselect where all conditions and data are constants can be optimized into
10466 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10467 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10468 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10469 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10472 // Try to lower this to a blend-style vector shuffle. This can handle all
10473 // constant condition cases.
10474 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10477 // Variable blends are only legal from SSE4.1 onward.
10478 if (!Subtarget->hasSSE41())
10481 // Only some types will be legal on some subtargets. If we can emit a legal
10482 // VSELECT-matching blend, return Op, and but if we need to expand, return
10484 switch (Op.getSimpleValueType().SimpleTy) {
10486 // Most of the vector types have blends past SSE4.1.
10490 // The byte blends for AVX vectors were introduced only in AVX2.
10491 if (Subtarget->hasAVX2())
10498 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10499 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10502 // FIXME: We should custom lower this by fixing the condition and using i8
10508 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10509 MVT VT = Op.getSimpleValueType();
10512 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10515 if (VT.getSizeInBits() == 8) {
10516 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10517 Op.getOperand(0), Op.getOperand(1));
10518 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10519 DAG.getValueType(VT));
10520 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10523 if (VT.getSizeInBits() == 16) {
10524 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10525 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10527 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10528 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10529 DAG.getNode(ISD::BITCAST, dl,
10532 Op.getOperand(1)));
10533 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10534 Op.getOperand(0), Op.getOperand(1));
10535 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10536 DAG.getValueType(VT));
10537 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10540 if (VT == MVT::f32) {
10541 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10542 // the result back to FR32 register. It's only worth matching if the
10543 // result has a single use which is a store or a bitcast to i32. And in
10544 // the case of a store, it's not worth it if the index is a constant 0,
10545 // because a MOVSSmr can be used instead, which is smaller and faster.
10546 if (!Op.hasOneUse())
10548 SDNode *User = *Op.getNode()->use_begin();
10549 if ((User->getOpcode() != ISD::STORE ||
10550 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10551 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10552 (User->getOpcode() != ISD::BITCAST ||
10553 User->getValueType(0) != MVT::i32))
10555 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10556 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10559 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10562 if (VT == MVT::i32 || VT == MVT::i64) {
10563 // ExtractPS/pextrq works with constant index.
10564 if (isa<ConstantSDNode>(Op.getOperand(1)))
10570 /// Extract one bit from mask vector, like v16i1 or v8i1.
10571 /// AVX-512 feature.
10573 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10574 SDValue Vec = Op.getOperand(0);
10576 MVT VecVT = Vec.getSimpleValueType();
10577 SDValue Idx = Op.getOperand(1);
10578 MVT EltVT = Op.getSimpleValueType();
10580 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10581 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10582 "Unexpected vector type in ExtractBitFromMaskVector");
10584 // variable index can't be handled in mask registers,
10585 // extend vector to VR512
10586 if (!isa<ConstantSDNode>(Idx)) {
10587 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10588 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10589 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10590 ExtVT.getVectorElementType(), Ext, Idx);
10591 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10594 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10595 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10596 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10597 rc = getRegClassFor(MVT::v16i1);
10598 unsigned MaxSift = rc->getSize()*8 - 1;
10599 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10600 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10601 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10602 DAG.getConstant(MaxSift, dl, MVT::i8));
10603 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10604 DAG.getIntPtrConstant(0, dl));
10608 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10609 SelectionDAG &DAG) const {
10611 SDValue Vec = Op.getOperand(0);
10612 MVT VecVT = Vec.getSimpleValueType();
10613 SDValue Idx = Op.getOperand(1);
10615 if (Op.getSimpleValueType() == MVT::i1)
10616 return ExtractBitFromMaskVector(Op, DAG);
10618 if (!isa<ConstantSDNode>(Idx)) {
10619 if (VecVT.is512BitVector() ||
10620 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10621 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10624 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10625 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10626 MaskEltVT.getSizeInBits());
10628 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10629 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10630 getZeroVector(MaskVT, Subtarget, DAG, dl),
10631 Idx, DAG.getConstant(0, dl, getPointerTy()));
10632 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10633 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10634 Perm, DAG.getConstant(0, dl, getPointerTy()));
10639 // If this is a 256-bit vector result, first extract the 128-bit vector and
10640 // then extract the element from the 128-bit vector.
10641 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10643 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10644 // Get the 128-bit vector.
10645 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10646 MVT EltVT = VecVT.getVectorElementType();
10648 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10650 //if (IdxVal >= NumElems/2)
10651 // IdxVal -= NumElems/2;
10652 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10653 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10654 DAG.getConstant(IdxVal, dl, MVT::i32));
10657 assert(VecVT.is128BitVector() && "Unexpected vector length");
10659 if (Subtarget->hasSSE41()) {
10660 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10665 MVT VT = Op.getSimpleValueType();
10666 // TODO: handle v16i8.
10667 if (VT.getSizeInBits() == 16) {
10668 SDValue Vec = Op.getOperand(0);
10669 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10671 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10672 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10673 DAG.getNode(ISD::BITCAST, dl,
10675 Op.getOperand(1)));
10676 // Transform it so it match pextrw which produces a 32-bit result.
10677 MVT EltVT = MVT::i32;
10678 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10679 Op.getOperand(0), Op.getOperand(1));
10680 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10681 DAG.getValueType(VT));
10682 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10685 if (VT.getSizeInBits() == 32) {
10686 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10690 // SHUFPS the element to the lowest double word, then movss.
10691 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10692 MVT VVT = Op.getOperand(0).getSimpleValueType();
10693 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10694 DAG.getUNDEF(VVT), Mask);
10695 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10696 DAG.getIntPtrConstant(0, dl));
10699 if (VT.getSizeInBits() == 64) {
10700 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10701 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10702 // to match extract_elt for f64.
10703 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10707 // UNPCKHPD the element to the lowest double word, then movsd.
10708 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10709 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10710 int Mask[2] = { 1, -1 };
10711 MVT VVT = Op.getOperand(0).getSimpleValueType();
10712 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10713 DAG.getUNDEF(VVT), Mask);
10714 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10715 DAG.getIntPtrConstant(0, dl));
10721 /// Insert one bit to mask vector, like v16i1 or v8i1.
10722 /// AVX-512 feature.
10724 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10726 SDValue Vec = Op.getOperand(0);
10727 SDValue Elt = Op.getOperand(1);
10728 SDValue Idx = Op.getOperand(2);
10729 MVT VecVT = Vec.getSimpleValueType();
10731 if (!isa<ConstantSDNode>(Idx)) {
10732 // Non constant index. Extend source and destination,
10733 // insert element and then truncate the result.
10734 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10735 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10736 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10737 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10738 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10739 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10742 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10743 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10745 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10746 DAG.getConstant(IdxVal, dl, MVT::i8));
10747 if (Vec.getOpcode() == ISD::UNDEF)
10749 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10752 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10753 SelectionDAG &DAG) const {
10754 MVT VT = Op.getSimpleValueType();
10755 MVT EltVT = VT.getVectorElementType();
10757 if (EltVT == MVT::i1)
10758 return InsertBitToMaskVector(Op, DAG);
10761 SDValue N0 = Op.getOperand(0);
10762 SDValue N1 = Op.getOperand(1);
10763 SDValue N2 = Op.getOperand(2);
10764 if (!isa<ConstantSDNode>(N2))
10766 auto *N2C = cast<ConstantSDNode>(N2);
10767 unsigned IdxVal = N2C->getZExtValue();
10769 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10770 // into that, and then insert the subvector back into the result.
10771 if (VT.is256BitVector() || VT.is512BitVector()) {
10772 // With a 256-bit vector, we can insert into the zero element efficiently
10773 // using a blend if we have AVX or AVX2 and the right data type.
10774 if (VT.is256BitVector() && IdxVal == 0) {
10775 // TODO: It is worthwhile to cast integer to floating point and back
10776 // and incur a domain crossing penalty if that's what we'll end up
10777 // doing anyway after extracting to a 128-bit vector.
10778 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10779 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10780 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10781 N2 = DAG.getIntPtrConstant(1, dl);
10782 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10786 // Get the desired 128-bit vector chunk.
10787 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10789 // Insert the element into the desired chunk.
10790 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10791 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10793 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10794 DAG.getConstant(IdxIn128, dl, MVT::i32));
10796 // Insert the changed part back into the bigger vector
10797 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10799 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10801 if (Subtarget->hasSSE41()) {
10802 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10804 if (VT == MVT::v8i16) {
10805 Opc = X86ISD::PINSRW;
10807 assert(VT == MVT::v16i8);
10808 Opc = X86ISD::PINSRB;
10811 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10813 if (N1.getValueType() != MVT::i32)
10814 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10815 if (N2.getValueType() != MVT::i32)
10816 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10817 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10820 if (EltVT == MVT::f32) {
10821 // Bits [7:6] of the constant are the source select. This will always be
10822 // zero here. The DAG Combiner may combine an extract_elt index into
10823 // these bits. For example (insert (extract, 3), 2) could be matched by
10824 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10825 // Bits [5:4] of the constant are the destination select. This is the
10826 // value of the incoming immediate.
10827 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10828 // combine either bitwise AND or insert of float 0.0 to set these bits.
10830 const Function *F = DAG.getMachineFunction().getFunction();
10831 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10832 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10833 // If this is an insertion of 32-bits into the low 32-bits of
10834 // a vector, we prefer to generate a blend with immediate rather
10835 // than an insertps. Blends are simpler operations in hardware and so
10836 // will always have equal or better performance than insertps.
10837 // But if optimizing for size and there's a load folding opportunity,
10838 // generate insertps because blendps does not have a 32-bit memory
10840 N2 = DAG.getIntPtrConstant(1, dl);
10841 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10842 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10844 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10845 // Create this as a scalar to vector..
10846 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10847 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10850 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10851 // PINSR* works with constant index.
10856 if (EltVT == MVT::i8)
10859 if (EltVT.getSizeInBits() == 16) {
10860 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10861 // as its second argument.
10862 if (N1.getValueType() != MVT::i32)
10863 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10864 if (N2.getValueType() != MVT::i32)
10865 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10866 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10871 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10873 MVT OpVT = Op.getSimpleValueType();
10875 // If this is a 256-bit vector result, first insert into a 128-bit
10876 // vector and then insert into the 256-bit vector.
10877 if (!OpVT.is128BitVector()) {
10878 // Insert into a 128-bit vector.
10879 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10880 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10881 OpVT.getVectorNumElements() / SizeFactor);
10883 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10885 // Insert the 128-bit vector.
10886 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10889 if (OpVT == MVT::v1i64 &&
10890 Op.getOperand(0).getValueType() == MVT::i64)
10891 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10893 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10894 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10895 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10896 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10899 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10900 // a simple subregister reference or explicit instructions to grab
10901 // upper bits of a vector.
10902 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10903 SelectionDAG &DAG) {
10905 SDValue In = Op.getOperand(0);
10906 SDValue Idx = Op.getOperand(1);
10907 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10908 MVT ResVT = Op.getSimpleValueType();
10909 MVT InVT = In.getSimpleValueType();
10911 if (Subtarget->hasFp256()) {
10912 if (ResVT.is128BitVector() &&
10913 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10914 isa<ConstantSDNode>(Idx)) {
10915 return Extract128BitVector(In, IdxVal, DAG, dl);
10917 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10918 isa<ConstantSDNode>(Idx)) {
10919 return Extract256BitVector(In, IdxVal, DAG, dl);
10925 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10926 // simple superregister reference or explicit instructions to insert
10927 // the upper bits of a vector.
10928 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10929 SelectionDAG &DAG) {
10930 if (!Subtarget->hasAVX())
10934 SDValue Vec = Op.getOperand(0);
10935 SDValue SubVec = Op.getOperand(1);
10936 SDValue Idx = Op.getOperand(2);
10938 if (!isa<ConstantSDNode>(Idx))
10941 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10942 MVT OpVT = Op.getSimpleValueType();
10943 MVT SubVecVT = SubVec.getSimpleValueType();
10945 // Fold two 16-byte subvector loads into one 32-byte load:
10946 // (insert_subvector (insert_subvector undef, (load addr), 0),
10947 // (load addr + 16), Elts/2)
10949 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10950 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10951 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10952 !Subtarget->isUnalignedMem32Slow()) {
10953 SDValue SubVec2 = Vec.getOperand(1);
10954 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10955 if (Idx2->getZExtValue() == 0) {
10956 SDValue Ops[] = { SubVec2, SubVec };
10957 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10964 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10965 SubVecVT.is128BitVector())
10966 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10968 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10969 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10971 if (OpVT.getVectorElementType() == MVT::i1) {
10972 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10974 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10975 SDValue Undef = DAG.getUNDEF(OpVT);
10976 unsigned NumElems = OpVT.getVectorNumElements();
10977 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10979 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10980 // Zero upper bits of the Vec
10981 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10982 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10984 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10986 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10987 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10990 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10992 // Zero upper bits of the Vec2
10993 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10994 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10995 // Zero lower bits of the Vec
10996 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10997 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10998 // Merge them together
10999 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11005 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11006 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11007 // one of the above mentioned nodes. It has to be wrapped because otherwise
11008 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11009 // be used to form addressing mode. These wrapped nodes will be selected
11012 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11013 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11015 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11016 // global base reg.
11017 unsigned char OpFlag = 0;
11018 unsigned WrapperKind = X86ISD::Wrapper;
11019 CodeModel::Model M = DAG.getTarget().getCodeModel();
11021 if (Subtarget->isPICStyleRIPRel() &&
11022 (M == CodeModel::Small || M == CodeModel::Kernel))
11023 WrapperKind = X86ISD::WrapperRIP;
11024 else if (Subtarget->isPICStyleGOT())
11025 OpFlag = X86II::MO_GOTOFF;
11026 else if (Subtarget->isPICStyleStubPIC())
11027 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11029 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11030 CP->getAlignment(),
11031 CP->getOffset(), OpFlag);
11033 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11034 // With PIC, the address is actually $g + Offset.
11036 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11037 DAG.getNode(X86ISD::GlobalBaseReg,
11038 SDLoc(), getPointerTy()),
11045 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11046 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11048 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11049 // global base reg.
11050 unsigned char OpFlag = 0;
11051 unsigned WrapperKind = X86ISD::Wrapper;
11052 CodeModel::Model M = DAG.getTarget().getCodeModel();
11054 if (Subtarget->isPICStyleRIPRel() &&
11055 (M == CodeModel::Small || M == CodeModel::Kernel))
11056 WrapperKind = X86ISD::WrapperRIP;
11057 else if (Subtarget->isPICStyleGOT())
11058 OpFlag = X86II::MO_GOTOFF;
11059 else if (Subtarget->isPICStyleStubPIC())
11060 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11062 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11065 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11067 // With PIC, the address is actually $g + Offset.
11069 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11070 DAG.getNode(X86ISD::GlobalBaseReg,
11071 SDLoc(), getPointerTy()),
11078 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11079 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11081 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11082 // global base reg.
11083 unsigned char OpFlag = 0;
11084 unsigned WrapperKind = X86ISD::Wrapper;
11085 CodeModel::Model M = DAG.getTarget().getCodeModel();
11087 if (Subtarget->isPICStyleRIPRel() &&
11088 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11089 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11090 OpFlag = X86II::MO_GOTPCREL;
11091 WrapperKind = X86ISD::WrapperRIP;
11092 } else if (Subtarget->isPICStyleGOT()) {
11093 OpFlag = X86II::MO_GOT;
11094 } else if (Subtarget->isPICStyleStubPIC()) {
11095 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11096 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11097 OpFlag = X86II::MO_DARWIN_NONLAZY;
11100 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11103 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11105 // With PIC, the address is actually $g + Offset.
11106 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11107 !Subtarget->is64Bit()) {
11108 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11109 DAG.getNode(X86ISD::GlobalBaseReg,
11110 SDLoc(), getPointerTy()),
11114 // For symbols that require a load from a stub to get the address, emit the
11116 if (isGlobalStubReference(OpFlag))
11117 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11118 MachinePointerInfo::getGOT(), false, false, false, 0);
11124 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11125 // Create the TargetBlockAddressAddress node.
11126 unsigned char OpFlags =
11127 Subtarget->ClassifyBlockAddressReference();
11128 CodeModel::Model M = DAG.getTarget().getCodeModel();
11129 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11130 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11132 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11135 if (Subtarget->isPICStyleRIPRel() &&
11136 (M == CodeModel::Small || M == CodeModel::Kernel))
11137 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11139 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11141 // With PIC, the address is actually $g + Offset.
11142 if (isGlobalRelativeToPICBase(OpFlags)) {
11143 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11144 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11152 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11153 int64_t Offset, SelectionDAG &DAG) const {
11154 // Create the TargetGlobalAddress node, folding in the constant
11155 // offset if it is legal.
11156 unsigned char OpFlags =
11157 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11158 CodeModel::Model M = DAG.getTarget().getCodeModel();
11160 if (OpFlags == X86II::MO_NO_FLAG &&
11161 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11162 // A direct static reference to a global.
11163 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11166 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11169 if (Subtarget->isPICStyleRIPRel() &&
11170 (M == CodeModel::Small || M == CodeModel::Kernel))
11171 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11173 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11175 // With PIC, the address is actually $g + Offset.
11176 if (isGlobalRelativeToPICBase(OpFlags)) {
11177 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11178 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11182 // For globals that require a load from a stub to get the address, emit the
11184 if (isGlobalStubReference(OpFlags))
11185 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11186 MachinePointerInfo::getGOT(), false, false, false, 0);
11188 // If there was a non-zero offset that we didn't fold, create an explicit
11189 // addition for it.
11191 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11192 DAG.getConstant(Offset, dl, getPointerTy()));
11198 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11199 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11200 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11201 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11205 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11206 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11207 unsigned char OperandFlags, bool LocalDynamic = false) {
11208 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11209 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11211 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11212 GA->getValueType(0),
11216 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11220 SDValue Ops[] = { Chain, TGA, *InFlag };
11221 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11223 SDValue Ops[] = { Chain, TGA };
11224 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11227 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11228 MFI->setAdjustsStack(true);
11229 MFI->setHasCalls(true);
11231 SDValue Flag = Chain.getValue(1);
11232 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11235 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11237 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11240 SDLoc dl(GA); // ? function entry point might be better
11241 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11242 DAG.getNode(X86ISD::GlobalBaseReg,
11243 SDLoc(), PtrVT), InFlag);
11244 InFlag = Chain.getValue(1);
11246 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11249 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11251 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11253 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11254 X86::RAX, X86II::MO_TLSGD);
11257 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11263 // Get the start address of the TLS block for this module.
11264 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11265 .getInfo<X86MachineFunctionInfo>();
11266 MFI->incNumLocalDynamicTLSAccesses();
11270 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11271 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11274 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11275 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11276 InFlag = Chain.getValue(1);
11277 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11278 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11281 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11285 unsigned char OperandFlags = X86II::MO_DTPOFF;
11286 unsigned WrapperKind = X86ISD::Wrapper;
11287 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11288 GA->getValueType(0),
11289 GA->getOffset(), OperandFlags);
11290 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11292 // Add x@dtpoff with the base.
11293 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11296 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11297 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11298 const EVT PtrVT, TLSModel::Model model,
11299 bool is64Bit, bool isPIC) {
11302 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11303 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11304 is64Bit ? 257 : 256));
11306 SDValue ThreadPointer =
11307 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11308 MachinePointerInfo(Ptr), false, false, false, 0);
11310 unsigned char OperandFlags = 0;
11311 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11313 unsigned WrapperKind = X86ISD::Wrapper;
11314 if (model == TLSModel::LocalExec) {
11315 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11316 } else if (model == TLSModel::InitialExec) {
11318 OperandFlags = X86II::MO_GOTTPOFF;
11319 WrapperKind = X86ISD::WrapperRIP;
11321 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11324 llvm_unreachable("Unexpected model");
11327 // emit "addl x@ntpoff,%eax" (local exec)
11328 // or "addl x@indntpoff,%eax" (initial exec)
11329 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11331 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11332 GA->getOffset(), OperandFlags);
11333 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11335 if (model == TLSModel::InitialExec) {
11336 if (isPIC && !is64Bit) {
11337 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11338 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11342 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11343 MachinePointerInfo::getGOT(), false, false, false, 0);
11346 // The address of the thread local variable is the add of the thread
11347 // pointer with the offset of the variable.
11348 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11352 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11354 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11355 const GlobalValue *GV = GA->getGlobal();
11357 if (Subtarget->isTargetELF()) {
11358 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11360 case TLSModel::GeneralDynamic:
11361 if (Subtarget->is64Bit())
11362 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11363 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11364 case TLSModel::LocalDynamic:
11365 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11366 Subtarget->is64Bit());
11367 case TLSModel::InitialExec:
11368 case TLSModel::LocalExec:
11369 return LowerToTLSExecModel(
11370 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11371 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11373 llvm_unreachable("Unknown TLS model.");
11376 if (Subtarget->isTargetDarwin()) {
11377 // Darwin only has one model of TLS. Lower to that.
11378 unsigned char OpFlag = 0;
11379 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11380 X86ISD::WrapperRIP : X86ISD::Wrapper;
11382 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11383 // global base reg.
11384 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11385 !Subtarget->is64Bit();
11387 OpFlag = X86II::MO_TLVP_PIC_BASE;
11389 OpFlag = X86II::MO_TLVP;
11391 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11392 GA->getValueType(0),
11393 GA->getOffset(), OpFlag);
11394 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11396 // With PIC32, the address is actually $g + Offset.
11398 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11399 DAG.getNode(X86ISD::GlobalBaseReg,
11400 SDLoc(), getPointerTy()),
11403 // Lowering the machine isd will make sure everything is in the right
11405 SDValue Chain = DAG.getEntryNode();
11406 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11407 SDValue Args[] = { Chain, Offset };
11408 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11410 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11411 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11412 MFI->setAdjustsStack(true);
11414 // And our return value (tls address) is in the standard call return value
11416 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11417 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11418 Chain.getValue(1));
11421 if (Subtarget->isTargetKnownWindowsMSVC() ||
11422 Subtarget->isTargetWindowsGNU()) {
11423 // Just use the implicit TLS architecture
11424 // Need to generate someting similar to:
11425 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11427 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11428 // mov rcx, qword [rdx+rcx*8]
11429 // mov eax, .tls$:tlsvar
11430 // [rax+rcx] contains the address
11431 // Windows 64bit: gs:0x58
11432 // Windows 32bit: fs:__tls_array
11435 SDValue Chain = DAG.getEntryNode();
11437 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11438 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11439 // use its literal value of 0x2C.
11440 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11441 ? Type::getInt8PtrTy(*DAG.getContext(),
11443 : Type::getInt32PtrTy(*DAG.getContext(),
11447 Subtarget->is64Bit()
11448 ? DAG.getIntPtrConstant(0x58, dl)
11449 : (Subtarget->isTargetWindowsGNU()
11450 ? DAG.getIntPtrConstant(0x2C, dl)
11451 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11453 SDValue ThreadPointer =
11454 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11455 MachinePointerInfo(Ptr), false, false, false, 0);
11458 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11459 res = ThreadPointer;
11461 // Load the _tls_index variable
11462 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11463 if (Subtarget->is64Bit())
11464 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11465 MachinePointerInfo(), MVT::i32, false, false,
11468 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11469 false, false, false, 0);
11471 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11473 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11475 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11478 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11479 false, false, false, 0);
11481 // Get the offset of start of .tls section
11482 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11483 GA->getValueType(0),
11484 GA->getOffset(), X86II::MO_SECREL);
11485 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11487 // The address of the thread local variable is the add of the thread
11488 // pointer with the offset of the variable.
11489 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11492 llvm_unreachable("TLS not implemented for this target.");
11495 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11496 /// and take a 2 x i32 value to shift plus a shift amount.
11497 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11498 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11499 MVT VT = Op.getSimpleValueType();
11500 unsigned VTBits = VT.getSizeInBits();
11502 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11503 SDValue ShOpLo = Op.getOperand(0);
11504 SDValue ShOpHi = Op.getOperand(1);
11505 SDValue ShAmt = Op.getOperand(2);
11506 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11507 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11509 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11510 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11511 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11512 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11513 : DAG.getConstant(0, dl, VT);
11515 SDValue Tmp2, Tmp3;
11516 if (Op.getOpcode() == ISD::SHL_PARTS) {
11517 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11518 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11520 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11521 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11524 // If the shift amount is larger or equal than the width of a part we can't
11525 // rely on the results of shld/shrd. Insert a test and select the appropriate
11526 // values for large shift amounts.
11527 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11528 DAG.getConstant(VTBits, dl, MVT::i8));
11529 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11530 AndNode, DAG.getConstant(0, dl, MVT::i8));
11533 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11534 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11535 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11537 if (Op.getOpcode() == ISD::SHL_PARTS) {
11538 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11539 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11541 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11542 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11545 SDValue Ops[2] = { Lo, Hi };
11546 return DAG.getMergeValues(Ops, dl);
11549 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11550 SelectionDAG &DAG) const {
11551 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11554 if (SrcVT.isVector()) {
11555 if (SrcVT.getVectorElementType() == MVT::i1) {
11556 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11557 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11558 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11559 Op.getOperand(0)));
11564 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11565 "Unknown SINT_TO_FP to lower!");
11567 // These are really Legal; return the operand so the caller accepts it as
11569 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11571 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11572 Subtarget->is64Bit()) {
11576 unsigned Size = SrcVT.getSizeInBits()/8;
11577 MachineFunction &MF = DAG.getMachineFunction();
11578 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11579 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11580 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11582 MachinePointerInfo::getFixedStack(SSFI),
11584 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11587 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11589 SelectionDAG &DAG) const {
11593 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11595 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11597 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11599 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11601 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11602 MachineMemOperand *MMO;
11604 int SSFI = FI->getIndex();
11606 DAG.getMachineFunction()
11607 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11608 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11610 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11611 StackSlot = StackSlot.getOperand(1);
11613 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11614 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11616 Tys, Ops, SrcVT, MMO);
11619 Chain = Result.getValue(1);
11620 SDValue InFlag = Result.getValue(2);
11622 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11623 // shouldn't be necessary except that RFP cannot be live across
11624 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11625 MachineFunction &MF = DAG.getMachineFunction();
11626 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11627 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11628 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11629 Tys = DAG.getVTList(MVT::Other);
11631 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11633 MachineMemOperand *MMO =
11634 DAG.getMachineFunction()
11635 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11636 MachineMemOperand::MOStore, SSFISize, SSFISize);
11638 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11639 Ops, Op.getValueType(), MMO);
11640 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11641 MachinePointerInfo::getFixedStack(SSFI),
11642 false, false, false, 0);
11648 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11649 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11650 SelectionDAG &DAG) const {
11651 // This algorithm is not obvious. Here it is what we're trying to output:
11654 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11655 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11657 haddpd %xmm0, %xmm0
11659 pshufd $0x4e, %xmm0, %xmm1
11665 LLVMContext *Context = DAG.getContext();
11667 // Build some magic constants.
11668 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11669 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11670 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11672 SmallVector<Constant*,2> CV1;
11674 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11675 APInt(64, 0x4330000000000000ULL))));
11677 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11678 APInt(64, 0x4530000000000000ULL))));
11679 Constant *C1 = ConstantVector::get(CV1);
11680 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11682 // Load the 64-bit value into an XMM register.
11683 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11685 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11686 MachinePointerInfo::getConstantPool(),
11687 false, false, false, 16);
11688 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11689 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11692 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11693 MachinePointerInfo::getConstantPool(),
11694 false, false, false, 16);
11695 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11696 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11699 if (Subtarget->hasSSE3()) {
11700 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11701 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11703 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11704 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11706 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11707 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11711 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11712 DAG.getIntPtrConstant(0, dl));
11715 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11716 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11717 SelectionDAG &DAG) const {
11719 // FP constant to bias correct the final result.
11720 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11723 // Load the 32-bit value into an XMM register.
11724 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11727 // Zero out the upper parts of the register.
11728 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11730 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11731 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11732 DAG.getIntPtrConstant(0, dl));
11734 // Or the load with the bias.
11735 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11736 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11737 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11738 MVT::v2f64, Load)),
11739 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11740 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11741 MVT::v2f64, Bias)));
11742 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11743 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11744 DAG.getIntPtrConstant(0, dl));
11746 // Subtract the bias.
11747 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11749 // Handle final rounding.
11750 EVT DestVT = Op.getValueType();
11752 if (DestVT.bitsLT(MVT::f64))
11753 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11754 DAG.getIntPtrConstant(0, dl));
11755 if (DestVT.bitsGT(MVT::f64))
11756 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11758 // Handle final rounding.
11762 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11763 const X86Subtarget &Subtarget) {
11764 // The algorithm is the following:
11765 // #ifdef __SSE4_1__
11766 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11767 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11768 // (uint4) 0x53000000, 0xaa);
11770 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11771 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11773 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11774 // return (float4) lo + fhi;
11777 SDValue V = Op->getOperand(0);
11778 EVT VecIntVT = V.getValueType();
11779 bool Is128 = VecIntVT == MVT::v4i32;
11780 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11781 // If we convert to something else than the supported type, e.g., to v4f64,
11783 if (VecFloatVT != Op->getValueType(0))
11786 unsigned NumElts = VecIntVT.getVectorNumElements();
11787 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11788 "Unsupported custom type");
11789 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11791 // In the #idef/#else code, we have in common:
11792 // - The vector of constants:
11798 // Create the splat vector for 0x4b000000.
11799 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11800 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11801 CstLow, CstLow, CstLow, CstLow};
11802 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11803 makeArrayRef(&CstLowArray[0], NumElts));
11804 // Create the splat vector for 0x53000000.
11805 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11806 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11807 CstHigh, CstHigh, CstHigh, CstHigh};
11808 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11809 makeArrayRef(&CstHighArray[0], NumElts));
11811 // Create the right shift.
11812 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11813 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11814 CstShift, CstShift, CstShift, CstShift};
11815 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11816 makeArrayRef(&CstShiftArray[0], NumElts));
11817 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11820 if (Subtarget.hasSSE41()) {
11821 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11822 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11823 SDValue VecCstLowBitcast =
11824 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11825 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11826 // Low will be bitcasted right away, so do not bother bitcasting back to its
11828 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11829 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11830 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11831 // (uint4) 0x53000000, 0xaa);
11832 SDValue VecCstHighBitcast =
11833 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11834 SDValue VecShiftBitcast =
11835 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11836 // High will be bitcasted right away, so do not bother bitcasting back to
11837 // its original type.
11838 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11839 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11841 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11842 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11843 CstMask, CstMask, CstMask);
11844 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11845 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11846 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11848 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11849 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11852 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11853 SDValue CstFAdd = DAG.getConstantFP(
11854 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11855 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11856 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11857 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11858 makeArrayRef(&CstFAddArray[0], NumElts));
11860 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11861 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11863 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11864 // return (float4) lo + fhi;
11865 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11866 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11869 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11870 SelectionDAG &DAG) const {
11871 SDValue N0 = Op.getOperand(0);
11872 MVT SVT = N0.getSimpleValueType();
11875 switch (SVT.SimpleTy) {
11877 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11882 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11883 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11884 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11888 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11891 if (Subtarget->hasAVX512())
11892 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11893 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11895 llvm_unreachable(nullptr);
11898 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11899 SelectionDAG &DAG) const {
11900 SDValue N0 = Op.getOperand(0);
11903 if (Op.getValueType().isVector())
11904 return lowerUINT_TO_FP_vec(Op, DAG);
11906 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11907 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11908 // the optimization here.
11909 if (DAG.SignBitIsZero(N0))
11910 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11912 MVT SrcVT = N0.getSimpleValueType();
11913 MVT DstVT = Op.getSimpleValueType();
11914 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11915 return LowerUINT_TO_FP_i64(Op, DAG);
11916 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11917 return LowerUINT_TO_FP_i32(Op, DAG);
11918 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11921 // Make a 64-bit buffer, and use it to build an FILD.
11922 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11923 if (SrcVT == MVT::i32) {
11924 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11925 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11926 getPointerTy(), StackSlot, WordOff);
11927 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11928 StackSlot, MachinePointerInfo(),
11930 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11931 OffsetSlot, MachinePointerInfo(),
11933 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11937 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11938 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11939 StackSlot, MachinePointerInfo(),
11941 // For i64 source, we need to add the appropriate power of 2 if the input
11942 // was negative. This is the same as the optimization in
11943 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11944 // we must be careful to do the computation in x87 extended precision, not
11945 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11946 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11947 MachineMemOperand *MMO =
11948 DAG.getMachineFunction()
11949 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11950 MachineMemOperand::MOLoad, 8, 8);
11952 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11953 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11954 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11957 APInt FF(32, 0x5F800000ULL);
11959 // Check whether the sign bit is set.
11960 SDValue SignSet = DAG.getSetCC(dl,
11961 getSetCCResultType(*DAG.getContext(), MVT::i64),
11963 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11965 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11966 SDValue FudgePtr = DAG.getConstantPool(
11967 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11970 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11971 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11972 SDValue Four = DAG.getIntPtrConstant(4, dl);
11973 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11975 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11977 // Load the value out, extending it from f32 to f80.
11978 // FIXME: Avoid the extend by constructing the right constant pool?
11979 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11980 FudgePtr, MachinePointerInfo::getConstantPool(),
11981 MVT::f32, false, false, false, 4);
11982 // Extend everything to 80 bits to force it to be done on x87.
11983 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11984 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11985 DAG.getIntPtrConstant(0, dl));
11988 std::pair<SDValue,SDValue>
11989 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11990 bool IsSigned, bool IsReplace) const {
11993 EVT DstTy = Op.getValueType();
11995 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11996 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12000 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12001 DstTy.getSimpleVT() >= MVT::i16 &&
12002 "Unknown FP_TO_INT to lower!");
12004 // These are really Legal.
12005 if (DstTy == MVT::i32 &&
12006 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12007 return std::make_pair(SDValue(), SDValue());
12008 if (Subtarget->is64Bit() &&
12009 DstTy == MVT::i64 &&
12010 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12011 return std::make_pair(SDValue(), SDValue());
12013 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12014 // stack slot, or into the FTOL runtime function.
12015 MachineFunction &MF = DAG.getMachineFunction();
12016 unsigned MemSize = DstTy.getSizeInBits()/8;
12017 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12018 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12021 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12022 Opc = X86ISD::WIN_FTOL;
12024 switch (DstTy.getSimpleVT().SimpleTy) {
12025 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12026 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12027 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12028 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12031 SDValue Chain = DAG.getEntryNode();
12032 SDValue Value = Op.getOperand(0);
12033 EVT TheVT = Op.getOperand(0).getValueType();
12034 // FIXME This causes a redundant load/store if the SSE-class value is already
12035 // in memory, such as if it is on the callstack.
12036 if (isScalarFPTypeInSSEReg(TheVT)) {
12037 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12038 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12039 MachinePointerInfo::getFixedStack(SSFI),
12041 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12043 Chain, StackSlot, DAG.getValueType(TheVT)
12046 MachineMemOperand *MMO =
12047 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12048 MachineMemOperand::MOLoad, MemSize, MemSize);
12049 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12050 Chain = Value.getValue(1);
12051 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12052 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12055 MachineMemOperand *MMO =
12056 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12057 MachineMemOperand::MOStore, MemSize, MemSize);
12059 if (Opc != X86ISD::WIN_FTOL) {
12060 // Build the FP_TO_INT*_IN_MEM
12061 SDValue Ops[] = { Chain, Value, StackSlot };
12062 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12064 return std::make_pair(FIST, StackSlot);
12066 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12067 DAG.getVTList(MVT::Other, MVT::Glue),
12069 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12070 MVT::i32, ftol.getValue(1));
12071 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12072 MVT::i32, eax.getValue(2));
12073 SDValue Ops[] = { eax, edx };
12074 SDValue pair = IsReplace
12075 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12076 : DAG.getMergeValues(Ops, DL);
12077 return std::make_pair(pair, SDValue());
12081 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12082 const X86Subtarget *Subtarget) {
12083 MVT VT = Op->getSimpleValueType(0);
12084 SDValue In = Op->getOperand(0);
12085 MVT InVT = In.getSimpleValueType();
12088 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12089 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12091 // Optimize vectors in AVX mode:
12094 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12095 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12096 // Concat upper and lower parts.
12099 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12100 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12101 // Concat upper and lower parts.
12104 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12105 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12106 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12109 if (Subtarget->hasInt256())
12110 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12112 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12113 SDValue Undef = DAG.getUNDEF(InVT);
12114 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12115 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12116 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12118 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12119 VT.getVectorNumElements()/2);
12121 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12122 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12124 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12127 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12128 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12129 MVT VT = Op->getSimpleValueType(0);
12130 SDValue In = Op->getOperand(0);
12131 MVT InVT = In.getSimpleValueType();
12133 unsigned int NumElts = VT.getVectorNumElements();
12134 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12137 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12138 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12140 assert(InVT.getVectorElementType() == MVT::i1);
12141 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12143 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12145 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12147 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12148 if (VT.is512BitVector())
12150 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12153 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12154 SelectionDAG &DAG) {
12155 if (Subtarget->hasFp256()) {
12156 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12164 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12165 SelectionDAG &DAG) {
12167 MVT VT = Op.getSimpleValueType();
12168 SDValue In = Op.getOperand(0);
12169 MVT SVT = In.getSimpleValueType();
12171 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12172 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12174 if (Subtarget->hasFp256()) {
12175 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12180 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12181 VT.getVectorNumElements() != SVT.getVectorNumElements());
12185 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12187 MVT VT = Op.getSimpleValueType();
12188 SDValue In = Op.getOperand(0);
12189 MVT InVT = In.getSimpleValueType();
12191 if (VT == MVT::i1) {
12192 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12193 "Invalid scalar TRUNCATE operation");
12194 if (InVT.getSizeInBits() >= 32)
12196 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12197 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12199 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12200 "Invalid TRUNCATE operation");
12202 // move vector to mask - truncate solution for SKX
12203 if (VT.getVectorElementType() == MVT::i1) {
12204 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12205 Subtarget->hasBWI())
12206 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12207 if ((InVT.is256BitVector() || InVT.is128BitVector())
12208 && InVT.getScalarSizeInBits() <= 16 &&
12209 Subtarget->hasBWI() && Subtarget->hasVLX())
12210 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12211 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12212 Subtarget->hasDQI())
12213 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12214 if ((InVT.is256BitVector() || InVT.is128BitVector())
12215 && InVT.getScalarSizeInBits() >= 32 &&
12216 Subtarget->hasDQI() && Subtarget->hasVLX())
12217 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12219 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12220 if (VT.getVectorElementType().getSizeInBits() >=8)
12221 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12223 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12224 unsigned NumElts = InVT.getVectorNumElements();
12225 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12226 if (InVT.getSizeInBits() < 512) {
12227 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12228 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12233 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12234 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12235 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12238 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12239 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12240 if (Subtarget->hasInt256()) {
12241 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12242 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12243 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12245 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12246 DAG.getIntPtrConstant(0, DL));
12249 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12250 DAG.getIntPtrConstant(0, DL));
12251 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12252 DAG.getIntPtrConstant(2, DL));
12253 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12254 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12255 static const int ShufMask[] = {0, 2, 4, 6};
12256 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12259 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12260 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12261 if (Subtarget->hasInt256()) {
12262 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12264 SmallVector<SDValue,32> pshufbMask;
12265 for (unsigned i = 0; i < 2; ++i) {
12266 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12267 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12268 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12269 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12270 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12271 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12272 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12273 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12274 for (unsigned j = 0; j < 8; ++j)
12275 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12277 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12278 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12279 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12281 static const int ShufMask[] = {0, 2, -1, -1};
12282 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12284 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12285 DAG.getIntPtrConstant(0, DL));
12286 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12289 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12290 DAG.getIntPtrConstant(0, DL));
12292 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12293 DAG.getIntPtrConstant(4, DL));
12295 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12296 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12298 // The PSHUFB mask:
12299 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12300 -1, -1, -1, -1, -1, -1, -1, -1};
12302 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12303 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12304 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12306 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12307 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12309 // The MOVLHPS Mask:
12310 static const int ShufMask2[] = {0, 1, 4, 5};
12311 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12312 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12315 // Handle truncation of V256 to V128 using shuffles.
12316 if (!VT.is128BitVector() || !InVT.is256BitVector())
12319 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12321 unsigned NumElems = VT.getVectorNumElements();
12322 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12324 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12325 // Prepare truncation shuffle mask
12326 for (unsigned i = 0; i != NumElems; ++i)
12327 MaskVec[i] = i * 2;
12328 SDValue V = DAG.getVectorShuffle(NVT, DL,
12329 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12330 DAG.getUNDEF(NVT), &MaskVec[0]);
12331 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12332 DAG.getIntPtrConstant(0, DL));
12335 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12336 SelectionDAG &DAG) const {
12337 assert(!Op.getSimpleValueType().isVector());
12339 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12340 /*IsSigned=*/ true, /*IsReplace=*/ false);
12341 SDValue FIST = Vals.first, StackSlot = Vals.second;
12342 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12343 if (!FIST.getNode()) return Op;
12345 if (StackSlot.getNode())
12346 // Load the result.
12347 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12348 FIST, StackSlot, MachinePointerInfo(),
12349 false, false, false, 0);
12351 // The node is the result.
12355 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12356 SelectionDAG &DAG) const {
12357 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12358 /*IsSigned=*/ false, /*IsReplace=*/ false);
12359 SDValue FIST = Vals.first, StackSlot = Vals.second;
12360 assert(FIST.getNode() && "Unexpected failure");
12362 if (StackSlot.getNode())
12363 // Load the result.
12364 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12365 FIST, StackSlot, MachinePointerInfo(),
12366 false, false, false, 0);
12368 // The node is the result.
12372 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12374 MVT VT = Op.getSimpleValueType();
12375 SDValue In = Op.getOperand(0);
12376 MVT SVT = In.getSimpleValueType();
12378 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12380 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12381 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12382 In, DAG.getUNDEF(SVT)));
12385 /// The only differences between FABS and FNEG are the mask and the logic op.
12386 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12387 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12388 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12389 "Wrong opcode for lowering FABS or FNEG.");
12391 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12393 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12394 // into an FNABS. We'll lower the FABS after that if it is still in use.
12396 for (SDNode *User : Op->uses())
12397 if (User->getOpcode() == ISD::FNEG)
12400 SDValue Op0 = Op.getOperand(0);
12401 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12404 MVT VT = Op.getSimpleValueType();
12405 // Assume scalar op for initialization; update for vector if needed.
12406 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12407 // generate a 16-byte vector constant and logic op even for the scalar case.
12408 // Using a 16-byte mask allows folding the load of the mask with
12409 // the logic op, so it can save (~4 bytes) on code size.
12411 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12412 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12413 // decide if we should generate a 16-byte constant mask when we only need 4 or
12414 // 8 bytes for the scalar case.
12415 if (VT.isVector()) {
12416 EltVT = VT.getVectorElementType();
12417 NumElts = VT.getVectorNumElements();
12420 unsigned EltBits = EltVT.getSizeInBits();
12421 LLVMContext *Context = DAG.getContext();
12422 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12424 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12425 Constant *C = ConstantInt::get(*Context, MaskElt);
12426 C = ConstantVector::getSplat(NumElts, C);
12427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12428 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12429 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12430 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12431 MachinePointerInfo::getConstantPool(),
12432 false, false, false, Alignment);
12434 if (VT.isVector()) {
12435 // For a vector, cast operands to a vector type, perform the logic op,
12436 // and cast the result back to the original value type.
12437 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12438 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12439 SDValue Operand = IsFNABS ?
12440 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12441 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12442 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12443 return DAG.getNode(ISD::BITCAST, dl, VT,
12444 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12447 // If not vector, then scalar.
12448 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12449 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12450 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12453 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12455 LLVMContext *Context = DAG.getContext();
12456 SDValue Op0 = Op.getOperand(0);
12457 SDValue Op1 = Op.getOperand(1);
12459 MVT VT = Op.getSimpleValueType();
12460 MVT SrcVT = Op1.getSimpleValueType();
12462 // If second operand is smaller, extend it first.
12463 if (SrcVT.bitsLT(VT)) {
12464 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12467 // And if it is bigger, shrink it first.
12468 if (SrcVT.bitsGT(VT)) {
12469 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12473 // At this point the operands and the result should have the same
12474 // type, and that won't be f80 since that is not custom lowered.
12476 const fltSemantics &Sem =
12477 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12478 const unsigned SizeInBits = VT.getSizeInBits();
12480 SmallVector<Constant *, 4> CV(
12481 VT == MVT::f64 ? 2 : 4,
12482 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12484 // First, clear all bits but the sign bit from the second operand (sign).
12485 CV[0] = ConstantFP::get(*Context,
12486 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12487 Constant *C = ConstantVector::get(CV);
12488 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12489 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12490 MachinePointerInfo::getConstantPool(),
12491 false, false, false, 16);
12492 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12494 // Next, clear the sign bit from the first operand (magnitude).
12495 // If it's a constant, we can clear it here.
12496 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12497 APFloat APF = Op0CN->getValueAPF();
12498 // If the magnitude is a positive zero, the sign bit alone is enough.
12499 if (APF.isPosZero())
12502 CV[0] = ConstantFP::get(*Context, APF);
12504 CV[0] = ConstantFP::get(
12506 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12508 C = ConstantVector::get(CV);
12509 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12510 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12511 MachinePointerInfo::getConstantPool(),
12512 false, false, false, 16);
12513 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12514 if (!isa<ConstantFPSDNode>(Op0))
12515 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12517 // OR the magnitude value with the sign bit.
12518 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12521 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12522 SDValue N0 = Op.getOperand(0);
12524 MVT VT = Op.getSimpleValueType();
12526 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12527 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12528 DAG.getConstant(1, dl, VT));
12529 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12532 // Check whether an OR'd tree is PTEST-able.
12533 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12534 SelectionDAG &DAG) {
12535 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12537 if (!Subtarget->hasSSE41())
12540 if (!Op->hasOneUse())
12543 SDNode *N = Op.getNode();
12546 SmallVector<SDValue, 8> Opnds;
12547 DenseMap<SDValue, unsigned> VecInMap;
12548 SmallVector<SDValue, 8> VecIns;
12549 EVT VT = MVT::Other;
12551 // Recognize a special case where a vector is casted into wide integer to
12553 Opnds.push_back(N->getOperand(0));
12554 Opnds.push_back(N->getOperand(1));
12556 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12557 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12558 // BFS traverse all OR'd operands.
12559 if (I->getOpcode() == ISD::OR) {
12560 Opnds.push_back(I->getOperand(0));
12561 Opnds.push_back(I->getOperand(1));
12562 // Re-evaluate the number of nodes to be traversed.
12563 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12567 // Quit if a non-EXTRACT_VECTOR_ELT
12568 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12571 // Quit if without a constant index.
12572 SDValue Idx = I->getOperand(1);
12573 if (!isa<ConstantSDNode>(Idx))
12576 SDValue ExtractedFromVec = I->getOperand(0);
12577 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12578 if (M == VecInMap.end()) {
12579 VT = ExtractedFromVec.getValueType();
12580 // Quit if not 128/256-bit vector.
12581 if (!VT.is128BitVector() && !VT.is256BitVector())
12583 // Quit if not the same type.
12584 if (VecInMap.begin() != VecInMap.end() &&
12585 VT != VecInMap.begin()->first.getValueType())
12587 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12588 VecIns.push_back(ExtractedFromVec);
12590 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12593 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12594 "Not extracted from 128-/256-bit vector.");
12596 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12598 for (DenseMap<SDValue, unsigned>::const_iterator
12599 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12600 // Quit if not all elements are used.
12601 if (I->second != FullMask)
12605 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12607 // Cast all vectors into TestVT for PTEST.
12608 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12609 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12611 // If more than one full vectors are evaluated, OR them first before PTEST.
12612 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12613 // Each iteration will OR 2 nodes and append the result until there is only
12614 // 1 node left, i.e. the final OR'd value of all vectors.
12615 SDValue LHS = VecIns[Slot];
12616 SDValue RHS = VecIns[Slot + 1];
12617 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12620 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12621 VecIns.back(), VecIns.back());
12624 /// \brief return true if \c Op has a use that doesn't just read flags.
12625 static bool hasNonFlagsUse(SDValue Op) {
12626 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12628 SDNode *User = *UI;
12629 unsigned UOpNo = UI.getOperandNo();
12630 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12631 // Look pass truncate.
12632 UOpNo = User->use_begin().getOperandNo();
12633 User = *User->use_begin();
12636 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12637 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12643 /// Emit nodes that will be selected as "test Op0,Op0", or something
12645 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12646 SelectionDAG &DAG) const {
12647 if (Op.getValueType() == MVT::i1) {
12648 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12649 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12650 DAG.getConstant(0, dl, MVT::i8));
12652 // CF and OF aren't always set the way we want. Determine which
12653 // of these we need.
12654 bool NeedCF = false;
12655 bool NeedOF = false;
12658 case X86::COND_A: case X86::COND_AE:
12659 case X86::COND_B: case X86::COND_BE:
12662 case X86::COND_G: case X86::COND_GE:
12663 case X86::COND_L: case X86::COND_LE:
12664 case X86::COND_O: case X86::COND_NO: {
12665 // Check if we really need to set the
12666 // Overflow flag. If NoSignedWrap is present
12667 // that is not actually needed.
12668 switch (Op->getOpcode()) {
12673 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12674 if (BinNode->Flags.hasNoSignedWrap())
12684 // See if we can use the EFLAGS value from the operand instead of
12685 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12686 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12687 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12688 // Emit a CMP with 0, which is the TEST pattern.
12689 //if (Op.getValueType() == MVT::i1)
12690 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12691 // DAG.getConstant(0, MVT::i1));
12692 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12693 DAG.getConstant(0, dl, Op.getValueType()));
12695 unsigned Opcode = 0;
12696 unsigned NumOperands = 0;
12698 // Truncate operations may prevent the merge of the SETCC instruction
12699 // and the arithmetic instruction before it. Attempt to truncate the operands
12700 // of the arithmetic instruction and use a reduced bit-width instruction.
12701 bool NeedTruncation = false;
12702 SDValue ArithOp = Op;
12703 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12704 SDValue Arith = Op->getOperand(0);
12705 // Both the trunc and the arithmetic op need to have one user each.
12706 if (Arith->hasOneUse())
12707 switch (Arith.getOpcode()) {
12714 NeedTruncation = true;
12720 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12721 // which may be the result of a CAST. We use the variable 'Op', which is the
12722 // non-casted variable when we check for possible users.
12723 switch (ArithOp.getOpcode()) {
12725 // Due to an isel shortcoming, be conservative if this add is likely to be
12726 // selected as part of a load-modify-store instruction. When the root node
12727 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12728 // uses of other nodes in the match, such as the ADD in this case. This
12729 // leads to the ADD being left around and reselected, with the result being
12730 // two adds in the output. Alas, even if none our users are stores, that
12731 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12732 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12733 // climbing the DAG back to the root, and it doesn't seem to be worth the
12735 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12736 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12737 if (UI->getOpcode() != ISD::CopyToReg &&
12738 UI->getOpcode() != ISD::SETCC &&
12739 UI->getOpcode() != ISD::STORE)
12742 if (ConstantSDNode *C =
12743 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12744 // An add of one will be selected as an INC.
12745 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12746 Opcode = X86ISD::INC;
12751 // An add of negative one (subtract of one) will be selected as a DEC.
12752 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12753 Opcode = X86ISD::DEC;
12759 // Otherwise use a regular EFLAGS-setting add.
12760 Opcode = X86ISD::ADD;
12765 // If we have a constant logical shift that's only used in a comparison
12766 // against zero turn it into an equivalent AND. This allows turning it into
12767 // a TEST instruction later.
12768 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12769 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12770 EVT VT = Op.getValueType();
12771 unsigned BitWidth = VT.getSizeInBits();
12772 unsigned ShAmt = Op->getConstantOperandVal(1);
12773 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12775 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12776 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12777 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12778 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12780 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12781 DAG.getConstant(Mask, dl, VT));
12782 DAG.ReplaceAllUsesWith(Op, New);
12788 // If the primary and result isn't used, don't bother using X86ISD::AND,
12789 // because a TEST instruction will be better.
12790 if (!hasNonFlagsUse(Op))
12796 // Due to the ISEL shortcoming noted above, be conservative if this op is
12797 // likely to be selected as part of a load-modify-store instruction.
12798 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12799 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12800 if (UI->getOpcode() == ISD::STORE)
12803 // Otherwise use a regular EFLAGS-setting instruction.
12804 switch (ArithOp.getOpcode()) {
12805 default: llvm_unreachable("unexpected operator!");
12806 case ISD::SUB: Opcode = X86ISD::SUB; break;
12807 case ISD::XOR: Opcode = X86ISD::XOR; break;
12808 case ISD::AND: Opcode = X86ISD::AND; break;
12810 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12811 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12812 if (EFLAGS.getNode())
12815 Opcode = X86ISD::OR;
12829 return SDValue(Op.getNode(), 1);
12835 // If we found that truncation is beneficial, perform the truncation and
12837 if (NeedTruncation) {
12838 EVT VT = Op.getValueType();
12839 SDValue WideVal = Op->getOperand(0);
12840 EVT WideVT = WideVal.getValueType();
12841 unsigned ConvertedOp = 0;
12842 // Use a target machine opcode to prevent further DAGCombine
12843 // optimizations that may separate the arithmetic operations
12844 // from the setcc node.
12845 switch (WideVal.getOpcode()) {
12847 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12848 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12849 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12850 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12851 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12855 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12856 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12857 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12858 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12859 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12865 // Emit a CMP with 0, which is the TEST pattern.
12866 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12867 DAG.getConstant(0, dl, Op.getValueType()));
12869 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12870 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12872 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12873 DAG.ReplaceAllUsesWith(Op, New);
12874 return SDValue(New.getNode(), 1);
12877 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12879 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12880 SDLoc dl, SelectionDAG &DAG) const {
12881 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12882 if (C->getAPIntValue() == 0)
12883 return EmitTest(Op0, X86CC, dl, DAG);
12885 if (Op0.getValueType() == MVT::i1)
12886 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12889 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12890 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12891 // Do the comparison at i32 if it's smaller, besides the Atom case.
12892 // This avoids subregister aliasing issues. Keep the smaller reference
12893 // if we're optimizing for size, however, as that'll allow better folding
12894 // of memory operations.
12895 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12896 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12897 Attribute::MinSize) &&
12898 !Subtarget->isAtom()) {
12899 unsigned ExtendOp =
12900 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12901 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12902 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12904 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12905 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12906 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12908 return SDValue(Sub.getNode(), 1);
12910 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12913 /// Convert a comparison if required by the subtarget.
12914 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12915 SelectionDAG &DAG) const {
12916 // If the subtarget does not support the FUCOMI instruction, floating-point
12917 // comparisons have to be converted.
12918 if (Subtarget->hasCMov() ||
12919 Cmp.getOpcode() != X86ISD::CMP ||
12920 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12921 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12924 // The instruction selector will select an FUCOM instruction instead of
12925 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12926 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12927 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12929 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12930 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12931 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12932 DAG.getConstant(8, dl, MVT::i8));
12933 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12934 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12937 /// The minimum architected relative accuracy is 2^-12. We need one
12938 /// Newton-Raphson step to have a good float result (24 bits of precision).
12939 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12940 DAGCombinerInfo &DCI,
12941 unsigned &RefinementSteps,
12942 bool &UseOneConstNR) const {
12943 // FIXME: We should use instruction latency models to calculate the cost of
12944 // each potential sequence, but this is very hard to do reliably because
12945 // at least Intel's Core* chips have variable timing based on the number of
12946 // significant digits in the divisor and/or sqrt operand.
12947 if (!Subtarget->useSqrtEst())
12950 EVT VT = Op.getValueType();
12952 // SSE1 has rsqrtss and rsqrtps.
12953 // TODO: Add support for AVX512 (v16f32).
12954 // It is likely not profitable to do this for f64 because a double-precision
12955 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12956 // instructions: convert to single, rsqrtss, convert back to double, refine
12957 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12958 // along with FMA, this could be a throughput win.
12959 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12960 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12961 RefinementSteps = 1;
12962 UseOneConstNR = false;
12963 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12968 /// The minimum architected relative accuracy is 2^-12. We need one
12969 /// Newton-Raphson step to have a good float result (24 bits of precision).
12970 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12971 DAGCombinerInfo &DCI,
12972 unsigned &RefinementSteps) const {
12973 // FIXME: We should use instruction latency models to calculate the cost of
12974 // each potential sequence, but this is very hard to do reliably because
12975 // at least Intel's Core* chips have variable timing based on the number of
12976 // significant digits in the divisor.
12977 if (!Subtarget->useReciprocalEst())
12980 EVT VT = Op.getValueType();
12982 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12983 // TODO: Add support for AVX512 (v16f32).
12984 // It is likely not profitable to do this for f64 because a double-precision
12985 // reciprocal estimate with refinement on x86 prior to FMA requires
12986 // 15 instructions: convert to single, rcpss, convert back to double, refine
12987 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12988 // along with FMA, this could be a throughput win.
12989 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12990 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12991 RefinementSteps = ReciprocalEstimateRefinementSteps;
12992 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12997 /// If we have at least two divisions that use the same divisor, convert to
12998 /// multplication by a reciprocal. This may need to be adjusted for a given
12999 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13000 /// This is because we still need one division to calculate the reciprocal and
13001 /// then we need two multiplies by that reciprocal as replacements for the
13002 /// original divisions.
13003 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13004 return NumUsers > 1;
13007 static bool isAllOnes(SDValue V) {
13008 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13009 return C && C->isAllOnesValue();
13012 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13013 /// if it's possible.
13014 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13015 SDLoc dl, SelectionDAG &DAG) const {
13016 SDValue Op0 = And.getOperand(0);
13017 SDValue Op1 = And.getOperand(1);
13018 if (Op0.getOpcode() == ISD::TRUNCATE)
13019 Op0 = Op0.getOperand(0);
13020 if (Op1.getOpcode() == ISD::TRUNCATE)
13021 Op1 = Op1.getOperand(0);
13024 if (Op1.getOpcode() == ISD::SHL)
13025 std::swap(Op0, Op1);
13026 if (Op0.getOpcode() == ISD::SHL) {
13027 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13028 if (And00C->getZExtValue() == 1) {
13029 // If we looked past a truncate, check that it's only truncating away
13031 unsigned BitWidth = Op0.getValueSizeInBits();
13032 unsigned AndBitWidth = And.getValueSizeInBits();
13033 if (BitWidth > AndBitWidth) {
13035 DAG.computeKnownBits(Op0, Zeros, Ones);
13036 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13040 RHS = Op0.getOperand(1);
13042 } else if (Op1.getOpcode() == ISD::Constant) {
13043 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13044 uint64_t AndRHSVal = AndRHS->getZExtValue();
13045 SDValue AndLHS = Op0;
13047 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13048 LHS = AndLHS.getOperand(0);
13049 RHS = AndLHS.getOperand(1);
13052 // Use BT if the immediate can't be encoded in a TEST instruction.
13053 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13055 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13059 if (LHS.getNode()) {
13060 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13061 // instruction. Since the shift amount is in-range-or-undefined, we know
13062 // that doing a bittest on the i32 value is ok. We extend to i32 because
13063 // the encoding for the i16 version is larger than the i32 version.
13064 // Also promote i16 to i32 for performance / code size reason.
13065 if (LHS.getValueType() == MVT::i8 ||
13066 LHS.getValueType() == MVT::i16)
13067 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13069 // If the operand types disagree, extend the shift amount to match. Since
13070 // BT ignores high bits (like shifts) we can use anyextend.
13071 if (LHS.getValueType() != RHS.getValueType())
13072 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13074 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13075 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13076 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13077 DAG.getConstant(Cond, dl, MVT::i8), BT);
13083 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13085 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13090 // SSE Condition code mapping:
13099 switch (SetCCOpcode) {
13100 default: llvm_unreachable("Unexpected SETCC condition");
13102 case ISD::SETEQ: SSECC = 0; break;
13104 case ISD::SETGT: Swap = true; // Fallthrough
13106 case ISD::SETOLT: SSECC = 1; break;
13108 case ISD::SETGE: Swap = true; // Fallthrough
13110 case ISD::SETOLE: SSECC = 2; break;
13111 case ISD::SETUO: SSECC = 3; break;
13113 case ISD::SETNE: SSECC = 4; break;
13114 case ISD::SETULE: Swap = true; // Fallthrough
13115 case ISD::SETUGE: SSECC = 5; break;
13116 case ISD::SETULT: Swap = true; // Fallthrough
13117 case ISD::SETUGT: SSECC = 6; break;
13118 case ISD::SETO: SSECC = 7; break;
13120 case ISD::SETONE: SSECC = 8; break;
13123 std::swap(Op0, Op1);
13128 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13129 // ones, and then concatenate the result back.
13130 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13131 MVT VT = Op.getSimpleValueType();
13133 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13134 "Unsupported value type for operation");
13136 unsigned NumElems = VT.getVectorNumElements();
13138 SDValue CC = Op.getOperand(2);
13140 // Extract the LHS vectors
13141 SDValue LHS = Op.getOperand(0);
13142 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13143 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13145 // Extract the RHS vectors
13146 SDValue RHS = Op.getOperand(1);
13147 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13148 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13150 // Issue the operation on the smaller types and concatenate the result back
13151 MVT EltVT = VT.getVectorElementType();
13152 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13153 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13154 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13155 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13158 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13159 SDValue Op0 = Op.getOperand(0);
13160 SDValue Op1 = Op.getOperand(1);
13161 SDValue CC = Op.getOperand(2);
13162 MVT VT = Op.getSimpleValueType();
13165 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13166 "Unexpected type for boolean compare operation");
13167 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13168 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13169 DAG.getConstant(-1, dl, VT));
13170 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13171 DAG.getConstant(-1, dl, VT));
13172 switch (SetCCOpcode) {
13173 default: llvm_unreachable("Unexpected SETCC condition");
13175 // (x != y) -> ~(x ^ y)
13176 return DAG.getNode(ISD::XOR, dl, VT,
13177 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13178 DAG.getConstant(-1, dl, VT));
13180 // (x == y) -> (x ^ y)
13181 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13184 // (x > y) -> (x & ~y)
13185 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13188 // (x < y) -> (~x & y)
13189 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13192 // (x <= y) -> (~x | y)
13193 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13196 // (x >=y) -> (x | ~y)
13197 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13201 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13202 const X86Subtarget *Subtarget) {
13203 SDValue Op0 = Op.getOperand(0);
13204 SDValue Op1 = Op.getOperand(1);
13205 SDValue CC = Op.getOperand(2);
13206 MVT VT = Op.getSimpleValueType();
13209 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13210 Op.getValueType().getScalarType() == MVT::i1 &&
13211 "Cannot set masked compare for this operation");
13213 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13215 bool Unsigned = false;
13218 switch (SetCCOpcode) {
13219 default: llvm_unreachable("Unexpected SETCC condition");
13220 case ISD::SETNE: SSECC = 4; break;
13221 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13222 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13223 case ISD::SETLT: Swap = true; //fall-through
13224 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13225 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13226 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13227 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13228 case ISD::SETULE: Unsigned = true; //fall-through
13229 case ISD::SETLE: SSECC = 2; break;
13233 std::swap(Op0, Op1);
13235 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13236 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13237 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13238 DAG.getConstant(SSECC, dl, MVT::i8));
13241 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13242 /// operand \p Op1. If non-trivial (for example because it's not constant)
13243 /// return an empty value.
13244 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13246 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13250 MVT VT = Op1.getSimpleValueType();
13251 MVT EVT = VT.getVectorElementType();
13252 unsigned n = VT.getVectorNumElements();
13253 SmallVector<SDValue, 8> ULTOp1;
13255 for (unsigned i = 0; i < n; ++i) {
13256 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13257 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13260 // Avoid underflow.
13261 APInt Val = Elt->getAPIntValue();
13265 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13268 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13271 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13272 SelectionDAG &DAG) {
13273 SDValue Op0 = Op.getOperand(0);
13274 SDValue Op1 = Op.getOperand(1);
13275 SDValue CC = Op.getOperand(2);
13276 MVT VT = Op.getSimpleValueType();
13277 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13278 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13283 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13284 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13287 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13288 unsigned Opc = X86ISD::CMPP;
13289 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13290 assert(VT.getVectorNumElements() <= 16);
13291 Opc = X86ISD::CMPM;
13293 // In the two special cases we can't handle, emit two comparisons.
13296 unsigned CombineOpc;
13297 if (SetCCOpcode == ISD::SETUEQ) {
13298 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13300 assert(SetCCOpcode == ISD::SETONE);
13301 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13304 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13305 DAG.getConstant(CC0, dl, MVT::i8));
13306 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13307 DAG.getConstant(CC1, dl, MVT::i8));
13308 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13310 // Handle all other FP comparisons here.
13311 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13312 DAG.getConstant(SSECC, dl, MVT::i8));
13315 // Break 256-bit integer vector compare into smaller ones.
13316 if (VT.is256BitVector() && !Subtarget->hasInt256())
13317 return Lower256IntVSETCC(Op, DAG);
13319 EVT OpVT = Op1.getValueType();
13320 if (OpVT.getVectorElementType() == MVT::i1)
13321 return LowerBoolVSETCC_AVX512(Op, DAG);
13323 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13324 if (Subtarget->hasAVX512()) {
13325 if (Op1.getValueType().is512BitVector() ||
13326 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13327 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13328 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13330 // In AVX-512 architecture setcc returns mask with i1 elements,
13331 // But there is no compare instruction for i8 and i16 elements in KNL.
13332 // We are not talking about 512-bit operands in this case, these
13333 // types are illegal.
13335 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13336 OpVT.getVectorElementType().getSizeInBits() >= 8))
13337 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13338 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13341 // We are handling one of the integer comparisons here. Since SSE only has
13342 // GT and EQ comparisons for integer, swapping operands and multiple
13343 // operations may be required for some comparisons.
13345 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13346 bool Subus = false;
13348 switch (SetCCOpcode) {
13349 default: llvm_unreachable("Unexpected SETCC condition");
13350 case ISD::SETNE: Invert = true;
13351 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13352 case ISD::SETLT: Swap = true;
13353 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13354 case ISD::SETGE: Swap = true;
13355 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13356 Invert = true; break;
13357 case ISD::SETULT: Swap = true;
13358 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13359 FlipSigns = true; break;
13360 case ISD::SETUGE: Swap = true;
13361 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13362 FlipSigns = true; Invert = true; break;
13365 // Special case: Use min/max operations for SETULE/SETUGE
13366 MVT VET = VT.getVectorElementType();
13368 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13369 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13372 switch (SetCCOpcode) {
13374 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13375 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13378 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13381 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13382 if (!MinMax && hasSubus) {
13383 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13385 // t = psubus Op0, Op1
13386 // pcmpeq t, <0..0>
13387 switch (SetCCOpcode) {
13389 case ISD::SETULT: {
13390 // If the comparison is against a constant we can turn this into a
13391 // setule. With psubus, setule does not require a swap. This is
13392 // beneficial because the constant in the register is no longer
13393 // destructed as the destination so it can be hoisted out of a loop.
13394 // Only do this pre-AVX since vpcmp* is no longer destructive.
13395 if (Subtarget->hasAVX())
13397 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13398 if (ULEOp1.getNode()) {
13400 Subus = true; Invert = false; Swap = false;
13404 // Psubus is better than flip-sign because it requires no inversion.
13405 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13406 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13410 Opc = X86ISD::SUBUS;
13416 std::swap(Op0, Op1);
13418 // Check that the operation in question is available (most are plain SSE2,
13419 // but PCMPGTQ and PCMPEQQ have different requirements).
13420 if (VT == MVT::v2i64) {
13421 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13422 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13424 // First cast everything to the right type.
13425 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13426 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13428 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13429 // bits of the inputs before performing those operations. The lower
13430 // compare is always unsigned.
13433 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13435 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13436 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13437 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13438 Sign, Zero, Sign, Zero);
13440 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13441 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13443 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13444 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13445 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13447 // Create masks for only the low parts/high parts of the 64 bit integers.
13448 static const int MaskHi[] = { 1, 1, 3, 3 };
13449 static const int MaskLo[] = { 0, 0, 2, 2 };
13450 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13451 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13452 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13454 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13455 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13458 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13460 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13463 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13464 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13465 // pcmpeqd + pshufd + pand.
13466 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13468 // First cast everything to the right type.
13469 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13470 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13473 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13475 // Make sure the lower and upper halves are both all-ones.
13476 static const int Mask[] = { 1, 0, 3, 2 };
13477 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13478 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13481 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13483 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13487 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13488 // bits of the inputs before performing those operations.
13490 EVT EltVT = VT.getVectorElementType();
13491 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13493 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13494 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13497 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13499 // If the logical-not of the result is required, perform that now.
13501 Result = DAG.getNOT(dl, Result, VT);
13504 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13507 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13508 getZeroVector(VT, Subtarget, DAG, dl));
13513 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13515 MVT VT = Op.getSimpleValueType();
13517 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13519 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13520 && "SetCC type must be 8-bit or 1-bit integer");
13521 SDValue Op0 = Op.getOperand(0);
13522 SDValue Op1 = Op.getOperand(1);
13524 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13526 // Optimize to BT if possible.
13527 // Lower (X & (1 << N)) == 0 to BT(X, N).
13528 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13529 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13530 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13531 Op1.getOpcode() == ISD::Constant &&
13532 cast<ConstantSDNode>(Op1)->isNullValue() &&
13533 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13534 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13535 if (NewSetCC.getNode()) {
13537 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13542 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13544 if (Op1.getOpcode() == ISD::Constant &&
13545 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13546 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13547 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13549 // If the input is a setcc, then reuse the input setcc or use a new one with
13550 // the inverted condition.
13551 if (Op0.getOpcode() == X86ISD::SETCC) {
13552 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13553 bool Invert = (CC == ISD::SETNE) ^
13554 cast<ConstantSDNode>(Op1)->isNullValue();
13558 CCode = X86::GetOppositeBranchCondition(CCode);
13559 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13560 DAG.getConstant(CCode, dl, MVT::i8),
13561 Op0.getOperand(1));
13563 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13567 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13568 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13569 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13571 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13572 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13575 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13576 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13577 if (X86CC == X86::COND_INVALID)
13580 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13581 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13582 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13583 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13585 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13589 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13590 static bool isX86LogicalCmp(SDValue Op) {
13591 unsigned Opc = Op.getNode()->getOpcode();
13592 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13593 Opc == X86ISD::SAHF)
13595 if (Op.getResNo() == 1 &&
13596 (Opc == X86ISD::ADD ||
13597 Opc == X86ISD::SUB ||
13598 Opc == X86ISD::ADC ||
13599 Opc == X86ISD::SBB ||
13600 Opc == X86ISD::SMUL ||
13601 Opc == X86ISD::UMUL ||
13602 Opc == X86ISD::INC ||
13603 Opc == X86ISD::DEC ||
13604 Opc == X86ISD::OR ||
13605 Opc == X86ISD::XOR ||
13606 Opc == X86ISD::AND))
13609 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13615 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13616 if (V.getOpcode() != ISD::TRUNCATE)
13619 SDValue VOp0 = V.getOperand(0);
13620 unsigned InBits = VOp0.getValueSizeInBits();
13621 unsigned Bits = V.getValueSizeInBits();
13622 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13625 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13626 bool addTest = true;
13627 SDValue Cond = Op.getOperand(0);
13628 SDValue Op1 = Op.getOperand(1);
13629 SDValue Op2 = Op.getOperand(2);
13631 EVT VT = Op1.getValueType();
13634 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13635 // are available or VBLENDV if AVX is available.
13636 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13637 if (Cond.getOpcode() == ISD::SETCC &&
13638 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13639 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13640 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13641 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13642 int SSECC = translateX86FSETCC(
13643 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13646 if (Subtarget->hasAVX512()) {
13647 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13648 DAG.getConstant(SSECC, DL, MVT::i8));
13649 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13652 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13653 DAG.getConstant(SSECC, DL, MVT::i8));
13655 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13656 // of 3 logic instructions for size savings and potentially speed.
13657 // Unfortunately, there is no scalar form of VBLENDV.
13659 // If either operand is a constant, don't try this. We can expect to
13660 // optimize away at least one of the logic instructions later in that
13661 // case, so that sequence would be faster than a variable blend.
13663 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13664 // uses XMM0 as the selection register. That may need just as many
13665 // instructions as the AND/ANDN/OR sequence due to register moves, so
13668 if (Subtarget->hasAVX() &&
13669 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13671 // Convert to vectors, do a VSELECT, and convert back to scalar.
13672 // All of the conversions should be optimized away.
13674 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13675 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13676 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13677 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13679 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13680 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13682 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13684 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13685 VSel, DAG.getIntPtrConstant(0, DL));
13687 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13688 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13689 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13693 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13695 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13696 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13697 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13698 Op1Scalar = Op1.getOperand(0);
13700 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13701 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13702 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13703 Op2Scalar = Op2.getOperand(0);
13704 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13705 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13706 Op1Scalar.getValueType(),
13707 Cond, Op1Scalar, Op2Scalar);
13708 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13709 return DAG.getNode(ISD::BITCAST, DL, VT, newSelect);
13710 SDValue ExtVec = DAG.getNode(ISD::BITCAST, DL, MVT::v8i1, newSelect);
13711 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13712 DAG.getIntPtrConstant(0, DL));
13716 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13717 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13718 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13719 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13720 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13721 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13722 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13724 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13727 if (Cond.getOpcode() == ISD::SETCC) {
13728 SDValue NewCond = LowerSETCC(Cond, DAG);
13729 if (NewCond.getNode())
13733 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13734 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13735 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13736 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13737 if (Cond.getOpcode() == X86ISD::SETCC &&
13738 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13739 isZero(Cond.getOperand(1).getOperand(1))) {
13740 SDValue Cmp = Cond.getOperand(1);
13742 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13744 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13745 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13746 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13748 SDValue CmpOp0 = Cmp.getOperand(0);
13749 // Apply further optimizations for special cases
13750 // (select (x != 0), -1, 0) -> neg & sbb
13751 // (select (x == 0), 0, -1) -> neg & sbb
13752 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13753 if (YC->isNullValue() &&
13754 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13755 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13756 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13757 DAG.getConstant(0, DL,
13758 CmpOp0.getValueType()),
13760 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13761 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13762 SDValue(Neg.getNode(), 1));
13766 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13767 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13768 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13770 SDValue Res = // Res = 0 or -1.
13771 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13772 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13774 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13775 Res = DAG.getNOT(DL, Res, Res.getValueType());
13777 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13778 if (!N2C || !N2C->isNullValue())
13779 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13784 // Look past (and (setcc_carry (cmp ...)), 1).
13785 if (Cond.getOpcode() == ISD::AND &&
13786 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13788 if (C && C->getAPIntValue() == 1)
13789 Cond = Cond.getOperand(0);
13792 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13793 // setting operand in place of the X86ISD::SETCC.
13794 unsigned CondOpcode = Cond.getOpcode();
13795 if (CondOpcode == X86ISD::SETCC ||
13796 CondOpcode == X86ISD::SETCC_CARRY) {
13797 CC = Cond.getOperand(0);
13799 SDValue Cmp = Cond.getOperand(1);
13800 unsigned Opc = Cmp.getOpcode();
13801 MVT VT = Op.getSimpleValueType();
13803 bool IllegalFPCMov = false;
13804 if (VT.isFloatingPoint() && !VT.isVector() &&
13805 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13806 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13808 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13809 Opc == X86ISD::BT) { // FIXME
13813 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13814 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13815 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13816 Cond.getOperand(0).getValueType() != MVT::i8)) {
13817 SDValue LHS = Cond.getOperand(0);
13818 SDValue RHS = Cond.getOperand(1);
13819 unsigned X86Opcode;
13822 switch (CondOpcode) {
13823 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13824 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13825 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13826 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13827 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13828 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13829 default: llvm_unreachable("unexpected overflowing operator");
13831 if (CondOpcode == ISD::UMULO)
13832 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13835 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13837 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13839 if (CondOpcode == ISD::UMULO)
13840 Cond = X86Op.getValue(2);
13842 Cond = X86Op.getValue(1);
13844 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13849 // Look pass the truncate if the high bits are known zero.
13850 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13851 Cond = Cond.getOperand(0);
13853 // We know the result of AND is compared against zero. Try to match
13855 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13856 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13857 if (NewSetCC.getNode()) {
13858 CC = NewSetCC.getOperand(0);
13859 Cond = NewSetCC.getOperand(1);
13866 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13867 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13870 // a < b ? -1 : 0 -> RES = ~setcc_carry
13871 // a < b ? 0 : -1 -> RES = setcc_carry
13872 // a >= b ? -1 : 0 -> RES = setcc_carry
13873 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13874 if (Cond.getOpcode() == X86ISD::SUB) {
13875 Cond = ConvertCmpIfNecessary(Cond, DAG);
13876 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13878 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13879 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13880 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13881 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13883 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13884 return DAG.getNOT(DL, Res, Res.getValueType());
13889 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13890 // widen the cmov and push the truncate through. This avoids introducing a new
13891 // branch during isel and doesn't add any extensions.
13892 if (Op.getValueType() == MVT::i8 &&
13893 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13894 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13895 if (T1.getValueType() == T2.getValueType() &&
13896 // Blacklist CopyFromReg to avoid partial register stalls.
13897 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13898 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13899 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13900 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13904 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13905 // condition is true.
13906 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13907 SDValue Ops[] = { Op2, Op1, CC, Cond };
13908 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13911 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
13912 const X86Subtarget *Subtarget,
13913 SelectionDAG &DAG) {
13914 MVT VT = Op->getSimpleValueType(0);
13915 SDValue In = Op->getOperand(0);
13916 MVT InVT = In.getSimpleValueType();
13917 MVT VTElt = VT.getVectorElementType();
13918 MVT InVTElt = InVT.getVectorElementType();
13922 if ((InVTElt == MVT::i1) &&
13923 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13924 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13926 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13927 VTElt.getSizeInBits() <= 16)) ||
13929 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13930 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13932 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13933 VTElt.getSizeInBits() >= 32))))
13934 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13936 unsigned int NumElts = VT.getVectorNumElements();
13938 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13941 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13942 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13943 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13944 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13947 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13948 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13950 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
13953 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
13955 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
13956 if (VT.is512BitVector())
13958 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
13961 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
13962 const X86Subtarget *Subtarget,
13963 SelectionDAG &DAG) {
13964 SDValue In = Op->getOperand(0);
13965 MVT VT = Op->getSimpleValueType(0);
13966 MVT InVT = In.getSimpleValueType();
13967 assert(VT.getSizeInBits() == InVT.getSizeInBits());
13969 MVT InSVT = InVT.getScalarType();
13970 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
13972 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13974 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
13979 // SSE41 targets can use the pmovsx* instructions directly.
13980 if (Subtarget->hasSSE41())
13981 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13983 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
13987 // As SRAI is only available on i16/i32 types, we expand only up to i32
13988 // and handle i64 separately.
13989 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
13990 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
13991 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
13992 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
13993 Curr = DAG.getNode(ISD::BITCAST, dl, CurrVT, Curr);
13996 SDValue SignExt = Curr;
13997 if (CurrVT != InVT) {
13998 unsigned SignExtShift =
13999 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14000 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14001 DAG.getConstant(SignExtShift, dl, MVT::i8));
14007 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14008 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14009 DAG.getConstant(31, dl, MVT::i8));
14010 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14011 return DAG.getNode(ISD::BITCAST, dl, VT, Ext);
14017 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14018 SelectionDAG &DAG) {
14019 MVT VT = Op->getSimpleValueType(0);
14020 SDValue In = Op->getOperand(0);
14021 MVT InVT = In.getSimpleValueType();
14024 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14025 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14027 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14028 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14029 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14032 if (Subtarget->hasInt256())
14033 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14035 // Optimize vectors in AVX mode
14036 // Sign extend v8i16 to v8i32 and
14039 // Divide input vector into two parts
14040 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14041 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14042 // concat the vectors to original VT
14044 unsigned NumElems = InVT.getVectorNumElements();
14045 SDValue Undef = DAG.getUNDEF(InVT);
14047 SmallVector<int,8> ShufMask1(NumElems, -1);
14048 for (unsigned i = 0; i != NumElems/2; ++i)
14051 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14053 SmallVector<int,8> ShufMask2(NumElems, -1);
14054 for (unsigned i = 0; i != NumElems/2; ++i)
14055 ShufMask2[i] = i + NumElems/2;
14057 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14059 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14060 VT.getVectorNumElements()/2);
14062 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14063 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14065 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14068 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14069 // may emit an illegal shuffle but the expansion is still better than scalar
14070 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14071 // we'll emit a shuffle and a arithmetic shift.
14072 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14073 // TODO: It is possible to support ZExt by zeroing the undef values during
14074 // the shuffle phase or after the shuffle.
14075 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14076 SelectionDAG &DAG) {
14077 MVT RegVT = Op.getSimpleValueType();
14078 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14079 assert(RegVT.isInteger() &&
14080 "We only custom lower integer vector sext loads.");
14082 // Nothing useful we can do without SSE2 shuffles.
14083 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14085 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14087 EVT MemVT = Ld->getMemoryVT();
14088 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14089 unsigned RegSz = RegVT.getSizeInBits();
14091 ISD::LoadExtType Ext = Ld->getExtensionType();
14093 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14094 && "Only anyext and sext are currently implemented.");
14095 assert(MemVT != RegVT && "Cannot extend to the same type");
14096 assert(MemVT.isVector() && "Must load a vector from memory");
14098 unsigned NumElems = RegVT.getVectorNumElements();
14099 unsigned MemSz = MemVT.getSizeInBits();
14100 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14102 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14103 // The only way in which we have a legal 256-bit vector result but not the
14104 // integer 256-bit operations needed to directly lower a sextload is if we
14105 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14106 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14107 // correctly legalized. We do this late to allow the canonical form of
14108 // sextload to persist throughout the rest of the DAG combiner -- it wants
14109 // to fold together any extensions it can, and so will fuse a sign_extend
14110 // of an sextload into a sextload targeting a wider value.
14112 if (MemSz == 128) {
14113 // Just switch this to a normal load.
14114 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14115 "it must be a legal 128-bit vector "
14117 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14118 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14119 Ld->isInvariant(), Ld->getAlignment());
14121 assert(MemSz < 128 &&
14122 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14123 // Do an sext load to a 128-bit vector type. We want to use the same
14124 // number of elements, but elements half as wide. This will end up being
14125 // recursively lowered by this routine, but will succeed as we definitely
14126 // have all the necessary features if we're using AVX1.
14128 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14129 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14131 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14132 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14133 Ld->isNonTemporal(), Ld->isInvariant(),
14134 Ld->getAlignment());
14137 // Replace chain users with the new chain.
14138 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14139 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14141 // Finally, do a normal sign-extend to the desired register.
14142 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14145 // All sizes must be a power of two.
14146 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14147 "Non-power-of-two elements are not custom lowered!");
14149 // Attempt to load the original value using scalar loads.
14150 // Find the largest scalar type that divides the total loaded size.
14151 MVT SclrLoadTy = MVT::i8;
14152 for (MVT Tp : MVT::integer_valuetypes()) {
14153 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14158 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14159 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14161 SclrLoadTy = MVT::f64;
14163 // Calculate the number of scalar loads that we need to perform
14164 // in order to load our vector from memory.
14165 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14167 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14168 "Can only lower sext loads with a single scalar load!");
14170 unsigned loadRegZize = RegSz;
14171 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14174 // Represent our vector as a sequence of elements which are the
14175 // largest scalar that we can load.
14176 EVT LoadUnitVecVT = EVT::getVectorVT(
14177 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14179 // Represent the data using the same element type that is stored in
14180 // memory. In practice, we ''widen'' MemVT.
14182 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14183 loadRegZize / MemVT.getScalarType().getSizeInBits());
14185 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14186 "Invalid vector type");
14188 // We can't shuffle using an illegal type.
14189 assert(TLI.isTypeLegal(WideVecVT) &&
14190 "We only lower types that form legal widened vector types");
14192 SmallVector<SDValue, 8> Chains;
14193 SDValue Ptr = Ld->getBasePtr();
14194 SDValue Increment =
14195 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14196 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14198 for (unsigned i = 0; i < NumLoads; ++i) {
14199 // Perform a single load.
14200 SDValue ScalarLoad =
14201 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14202 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14203 Ld->getAlignment());
14204 Chains.push_back(ScalarLoad.getValue(1));
14205 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14206 // another round of DAGCombining.
14208 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14210 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14211 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14213 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14216 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14218 // Bitcast the loaded value to a vector of the original element type, in
14219 // the size of the target vector type.
14220 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14221 unsigned SizeRatio = RegSz / MemSz;
14223 if (Ext == ISD::SEXTLOAD) {
14224 // If we have SSE4.1, we can directly emit a VSEXT node.
14225 if (Subtarget->hasSSE41()) {
14226 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14227 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14231 // Otherwise we'll shuffle the small elements in the high bits of the
14232 // larger type and perform an arithmetic shift. If the shift is not legal
14233 // it's better to scalarize.
14234 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14235 "We can't implement a sext load without an arithmetic right shift!");
14237 // Redistribute the loaded elements into the different locations.
14238 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14239 for (unsigned i = 0; i != NumElems; ++i)
14240 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14242 SDValue Shuff = DAG.getVectorShuffle(
14243 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14245 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14247 // Build the arithmetic shift.
14248 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14249 MemVT.getVectorElementType().getSizeInBits();
14251 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14252 DAG.getConstant(Amt, dl, RegVT));
14254 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14258 // Redistribute the loaded elements into the different locations.
14259 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14260 for (unsigned i = 0; i != NumElems; ++i)
14261 ShuffleVec[i * SizeRatio] = i;
14263 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14264 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14266 // Bitcast to the requested type.
14267 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14268 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14272 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14273 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14274 // from the AND / OR.
14275 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14276 Opc = Op.getOpcode();
14277 if (Opc != ISD::OR && Opc != ISD::AND)
14279 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14280 Op.getOperand(0).hasOneUse() &&
14281 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14282 Op.getOperand(1).hasOneUse());
14285 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14286 // 1 and that the SETCC node has a single use.
14287 static bool isXor1OfSetCC(SDValue Op) {
14288 if (Op.getOpcode() != ISD::XOR)
14290 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14291 if (N1C && N1C->getAPIntValue() == 1) {
14292 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14293 Op.getOperand(0).hasOneUse();
14298 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14299 bool addTest = true;
14300 SDValue Chain = Op.getOperand(0);
14301 SDValue Cond = Op.getOperand(1);
14302 SDValue Dest = Op.getOperand(2);
14305 bool Inverted = false;
14307 if (Cond.getOpcode() == ISD::SETCC) {
14308 // Check for setcc([su]{add,sub,mul}o == 0).
14309 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14310 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14311 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14312 Cond.getOperand(0).getResNo() == 1 &&
14313 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14314 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14315 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14316 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14317 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14318 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14320 Cond = Cond.getOperand(0);
14322 SDValue NewCond = LowerSETCC(Cond, DAG);
14323 if (NewCond.getNode())
14328 // FIXME: LowerXALUO doesn't handle these!!
14329 else if (Cond.getOpcode() == X86ISD::ADD ||
14330 Cond.getOpcode() == X86ISD::SUB ||
14331 Cond.getOpcode() == X86ISD::SMUL ||
14332 Cond.getOpcode() == X86ISD::UMUL)
14333 Cond = LowerXALUO(Cond, DAG);
14336 // Look pass (and (setcc_carry (cmp ...)), 1).
14337 if (Cond.getOpcode() == ISD::AND &&
14338 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14339 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14340 if (C && C->getAPIntValue() == 1)
14341 Cond = Cond.getOperand(0);
14344 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14345 // setting operand in place of the X86ISD::SETCC.
14346 unsigned CondOpcode = Cond.getOpcode();
14347 if (CondOpcode == X86ISD::SETCC ||
14348 CondOpcode == X86ISD::SETCC_CARRY) {
14349 CC = Cond.getOperand(0);
14351 SDValue Cmp = Cond.getOperand(1);
14352 unsigned Opc = Cmp.getOpcode();
14353 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14354 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14358 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14362 // These can only come from an arithmetic instruction with overflow,
14363 // e.g. SADDO, UADDO.
14364 Cond = Cond.getNode()->getOperand(1);
14370 CondOpcode = Cond.getOpcode();
14371 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14372 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14373 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14374 Cond.getOperand(0).getValueType() != MVT::i8)) {
14375 SDValue LHS = Cond.getOperand(0);
14376 SDValue RHS = Cond.getOperand(1);
14377 unsigned X86Opcode;
14380 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14381 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14383 switch (CondOpcode) {
14384 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14388 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14391 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14392 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14394 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14396 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14399 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14400 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14401 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14402 default: llvm_unreachable("unexpected overflowing operator");
14405 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14406 if (CondOpcode == ISD::UMULO)
14407 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14410 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14412 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14414 if (CondOpcode == ISD::UMULO)
14415 Cond = X86Op.getValue(2);
14417 Cond = X86Op.getValue(1);
14419 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14423 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14424 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14425 if (CondOpc == ISD::OR) {
14426 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14427 // two branches instead of an explicit OR instruction with a
14429 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14430 isX86LogicalCmp(Cmp)) {
14431 CC = Cond.getOperand(0).getOperand(0);
14432 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14433 Chain, Dest, CC, Cmp);
14434 CC = Cond.getOperand(1).getOperand(0);
14438 } else { // ISD::AND
14439 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14440 // two branches instead of an explicit AND instruction with a
14441 // separate test. However, we only do this if this block doesn't
14442 // have a fall-through edge, because this requires an explicit
14443 // jmp when the condition is false.
14444 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14445 isX86LogicalCmp(Cmp) &&
14446 Op.getNode()->hasOneUse()) {
14447 X86::CondCode CCode =
14448 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14449 CCode = X86::GetOppositeBranchCondition(CCode);
14450 CC = DAG.getConstant(CCode, dl, MVT::i8);
14451 SDNode *User = *Op.getNode()->use_begin();
14452 // Look for an unconditional branch following this conditional branch.
14453 // We need this because we need to reverse the successors in order
14454 // to implement FCMP_OEQ.
14455 if (User->getOpcode() == ISD::BR) {
14456 SDValue FalseBB = User->getOperand(1);
14458 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14459 assert(NewBR == User);
14463 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14464 Chain, Dest, CC, Cmp);
14465 X86::CondCode CCode =
14466 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14467 CCode = X86::GetOppositeBranchCondition(CCode);
14468 CC = DAG.getConstant(CCode, dl, MVT::i8);
14474 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14475 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14476 // It should be transformed during dag combiner except when the condition
14477 // is set by a arithmetics with overflow node.
14478 X86::CondCode CCode =
14479 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14480 CCode = X86::GetOppositeBranchCondition(CCode);
14481 CC = DAG.getConstant(CCode, dl, MVT::i8);
14482 Cond = Cond.getOperand(0).getOperand(1);
14484 } else if (Cond.getOpcode() == ISD::SETCC &&
14485 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14486 // For FCMP_OEQ, we can emit
14487 // two branches instead of an explicit AND instruction with a
14488 // separate test. However, we only do this if this block doesn't
14489 // have a fall-through edge, because this requires an explicit
14490 // jmp when the condition is false.
14491 if (Op.getNode()->hasOneUse()) {
14492 SDNode *User = *Op.getNode()->use_begin();
14493 // Look for an unconditional branch following this conditional branch.
14494 // We need this because we need to reverse the successors in order
14495 // to implement FCMP_OEQ.
14496 if (User->getOpcode() == ISD::BR) {
14497 SDValue FalseBB = User->getOperand(1);
14499 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14500 assert(NewBR == User);
14504 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14505 Cond.getOperand(0), Cond.getOperand(1));
14506 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14507 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14508 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14509 Chain, Dest, CC, Cmp);
14510 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14515 } else if (Cond.getOpcode() == ISD::SETCC &&
14516 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14517 // For FCMP_UNE, we can emit
14518 // two branches instead of an explicit AND instruction with a
14519 // separate test. However, we only do this if this block doesn't
14520 // have a fall-through edge, because this requires an explicit
14521 // jmp when the condition is false.
14522 if (Op.getNode()->hasOneUse()) {
14523 SDNode *User = *Op.getNode()->use_begin();
14524 // Look for an unconditional branch following this conditional branch.
14525 // We need this because we need to reverse the successors in order
14526 // to implement FCMP_UNE.
14527 if (User->getOpcode() == ISD::BR) {
14528 SDValue FalseBB = User->getOperand(1);
14530 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14531 assert(NewBR == User);
14534 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14535 Cond.getOperand(0), Cond.getOperand(1));
14536 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14537 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14538 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14539 Chain, Dest, CC, Cmp);
14540 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14550 // Look pass the truncate if the high bits are known zero.
14551 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14552 Cond = Cond.getOperand(0);
14554 // We know the result of AND is compared against zero. Try to match
14556 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14557 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14558 if (NewSetCC.getNode()) {
14559 CC = NewSetCC.getOperand(0);
14560 Cond = NewSetCC.getOperand(1);
14567 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14568 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14569 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14571 Cond = ConvertCmpIfNecessary(Cond, DAG);
14572 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14573 Chain, Dest, CC, Cond);
14576 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14577 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14578 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14579 // that the guard pages used by the OS virtual memory manager are allocated in
14580 // correct sequence.
14582 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14583 SelectionDAG &DAG) const {
14584 MachineFunction &MF = DAG.getMachineFunction();
14585 bool SplitStack = MF.shouldSplitStack();
14586 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14591 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14592 SDNode* Node = Op.getNode();
14594 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14595 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14596 " not tell us which reg is the stack pointer!");
14597 EVT VT = Node->getValueType(0);
14598 SDValue Tmp1 = SDValue(Node, 0);
14599 SDValue Tmp2 = SDValue(Node, 1);
14600 SDValue Tmp3 = Node->getOperand(2);
14601 SDValue Chain = Tmp1.getOperand(0);
14603 // Chain the dynamic stack allocation so that it doesn't modify the stack
14604 // pointer when other instructions are using the stack.
14605 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14608 SDValue Size = Tmp2.getOperand(1);
14609 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14610 Chain = SP.getValue(1);
14611 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14612 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14613 unsigned StackAlign = TFI.getStackAlignment();
14614 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14615 if (Align > StackAlign)
14616 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14617 DAG.getConstant(-(uint64_t)Align, dl, VT));
14618 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14620 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14621 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14624 SDValue Ops[2] = { Tmp1, Tmp2 };
14625 return DAG.getMergeValues(Ops, dl);
14629 SDValue Chain = Op.getOperand(0);
14630 SDValue Size = Op.getOperand(1);
14631 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14632 EVT VT = Op.getNode()->getValueType(0);
14634 bool Is64Bit = Subtarget->is64Bit();
14635 EVT SPTy = getPointerTy();
14638 MachineRegisterInfo &MRI = MF.getRegInfo();
14641 // The 64 bit implementation of segmented stacks needs to clobber both r10
14642 // r11. This makes it impossible to use it along with nested parameters.
14643 const Function *F = MF.getFunction();
14645 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14647 if (I->hasNestAttr())
14648 report_fatal_error("Cannot use segmented stacks with functions that "
14649 "have nested arguments.");
14652 const TargetRegisterClass *AddrRegClass =
14653 getRegClassFor(getPointerTy());
14654 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14655 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14656 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14657 DAG.getRegister(Vreg, SPTy));
14658 SDValue Ops1[2] = { Value, Chain };
14659 return DAG.getMergeValues(Ops1, dl);
14662 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14664 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14665 Flag = Chain.getValue(1);
14666 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14668 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14670 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14671 unsigned SPReg = RegInfo->getStackRegister();
14672 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14673 Chain = SP.getValue(1);
14676 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14677 DAG.getConstant(-(uint64_t)Align, dl, VT));
14678 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14681 SDValue Ops1[2] = { SP, Chain };
14682 return DAG.getMergeValues(Ops1, dl);
14686 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14687 MachineFunction &MF = DAG.getMachineFunction();
14688 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14690 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14693 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14694 // vastart just stores the address of the VarArgsFrameIndex slot into the
14695 // memory location argument.
14696 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14698 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14699 MachinePointerInfo(SV), false, false, 0);
14703 // gp_offset (0 - 6 * 8)
14704 // fp_offset (48 - 48 + 8 * 16)
14705 // overflow_arg_area (point to parameters coming in memory).
14707 SmallVector<SDValue, 8> MemOps;
14708 SDValue FIN = Op.getOperand(1);
14710 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14711 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14713 FIN, MachinePointerInfo(SV), false, false, 0);
14714 MemOps.push_back(Store);
14717 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14718 FIN, DAG.getIntPtrConstant(4, DL));
14719 Store = DAG.getStore(Op.getOperand(0), DL,
14720 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14722 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14723 MemOps.push_back(Store);
14725 // Store ptr to overflow_arg_area
14726 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14727 FIN, DAG.getIntPtrConstant(4, DL));
14728 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14730 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14731 MachinePointerInfo(SV, 8),
14733 MemOps.push_back(Store);
14735 // Store ptr to reg_save_area.
14736 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14737 FIN, DAG.getIntPtrConstant(8, DL));
14738 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14740 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14741 MachinePointerInfo(SV, 16), false, false, 0);
14742 MemOps.push_back(Store);
14743 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14746 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14747 assert(Subtarget->is64Bit() &&
14748 "LowerVAARG only handles 64-bit va_arg!");
14749 assert((Subtarget->isTargetLinux() ||
14750 Subtarget->isTargetDarwin()) &&
14751 "Unhandled target in LowerVAARG");
14752 assert(Op.getNode()->getNumOperands() == 4);
14753 SDValue Chain = Op.getOperand(0);
14754 SDValue SrcPtr = Op.getOperand(1);
14755 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14756 unsigned Align = Op.getConstantOperandVal(3);
14759 EVT ArgVT = Op.getNode()->getValueType(0);
14760 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14761 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14764 // Decide which area this value should be read from.
14765 // TODO: Implement the AMD64 ABI in its entirety. This simple
14766 // selection mechanism works only for the basic types.
14767 if (ArgVT == MVT::f80) {
14768 llvm_unreachable("va_arg for f80 not yet implemented");
14769 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14770 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14771 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14772 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14774 llvm_unreachable("Unhandled argument type in LowerVAARG");
14777 if (ArgMode == 2) {
14778 // Sanity Check: Make sure using fp_offset makes sense.
14779 assert(!Subtarget->useSoftFloat() &&
14780 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14781 Attribute::NoImplicitFloat)) &&
14782 Subtarget->hasSSE1());
14785 // Insert VAARG_64 node into the DAG
14786 // VAARG_64 returns two values: Variable Argument Address, Chain
14787 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14788 DAG.getConstant(ArgMode, dl, MVT::i8),
14789 DAG.getConstant(Align, dl, MVT::i32)};
14790 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14791 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14792 VTs, InstOps, MVT::i64,
14793 MachinePointerInfo(SV),
14795 /*Volatile=*/false,
14797 /*WriteMem=*/true);
14798 Chain = VAARG.getValue(1);
14800 // Load the next argument and return it
14801 return DAG.getLoad(ArgVT, dl,
14804 MachinePointerInfo(),
14805 false, false, false, 0);
14808 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14809 SelectionDAG &DAG) {
14810 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14811 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14812 SDValue Chain = Op.getOperand(0);
14813 SDValue DstPtr = Op.getOperand(1);
14814 SDValue SrcPtr = Op.getOperand(2);
14815 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14816 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14819 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14820 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14822 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14825 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14826 // amount is a constant. Takes immediate version of shift as input.
14827 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14828 SDValue SrcOp, uint64_t ShiftAmt,
14829 SelectionDAG &DAG) {
14830 MVT ElementType = VT.getVectorElementType();
14832 // Fold this packed shift into its first operand if ShiftAmt is 0.
14836 // Check for ShiftAmt >= element width
14837 if (ShiftAmt >= ElementType.getSizeInBits()) {
14838 if (Opc == X86ISD::VSRAI)
14839 ShiftAmt = ElementType.getSizeInBits() - 1;
14841 return DAG.getConstant(0, dl, VT);
14844 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14845 && "Unknown target vector shift-by-constant node");
14847 // Fold this packed vector shift into a build vector if SrcOp is a
14848 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14849 if (VT == SrcOp.getSimpleValueType() &&
14850 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14851 SmallVector<SDValue, 8> Elts;
14852 unsigned NumElts = SrcOp->getNumOperands();
14853 ConstantSDNode *ND;
14856 default: llvm_unreachable(nullptr);
14857 case X86ISD::VSHLI:
14858 for (unsigned i=0; i!=NumElts; ++i) {
14859 SDValue CurrentOp = SrcOp->getOperand(i);
14860 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14861 Elts.push_back(CurrentOp);
14864 ND = cast<ConstantSDNode>(CurrentOp);
14865 const APInt &C = ND->getAPIntValue();
14866 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14869 case X86ISD::VSRLI:
14870 for (unsigned i=0; i!=NumElts; ++i) {
14871 SDValue CurrentOp = SrcOp->getOperand(i);
14872 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14873 Elts.push_back(CurrentOp);
14876 ND = cast<ConstantSDNode>(CurrentOp);
14877 const APInt &C = ND->getAPIntValue();
14878 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14881 case X86ISD::VSRAI:
14882 for (unsigned i=0; i!=NumElts; ++i) {
14883 SDValue CurrentOp = SrcOp->getOperand(i);
14884 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14885 Elts.push_back(CurrentOp);
14888 ND = cast<ConstantSDNode>(CurrentOp);
14889 const APInt &C = ND->getAPIntValue();
14890 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14895 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14898 return DAG.getNode(Opc, dl, VT, SrcOp,
14899 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14902 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14903 // may or may not be a constant. Takes immediate version of shift as input.
14904 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14905 SDValue SrcOp, SDValue ShAmt,
14906 SelectionDAG &DAG) {
14907 MVT SVT = ShAmt.getSimpleValueType();
14908 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14910 // Catch shift-by-constant.
14911 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14912 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14913 CShAmt->getZExtValue(), DAG);
14915 // Change opcode to non-immediate version
14917 default: llvm_unreachable("Unknown target vector shift node");
14918 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14919 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14920 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14923 const X86Subtarget &Subtarget =
14924 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14925 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14926 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14927 // Let the shuffle legalizer expand this shift amount node.
14928 SDValue Op0 = ShAmt.getOperand(0);
14929 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14930 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14932 // Need to build a vector containing shift amount.
14933 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14934 SmallVector<SDValue, 4> ShOps;
14935 ShOps.push_back(ShAmt);
14936 if (SVT == MVT::i32) {
14937 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14938 ShOps.push_back(DAG.getUNDEF(SVT));
14940 ShOps.push_back(DAG.getUNDEF(SVT));
14942 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14943 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14946 // The return type has to be a 128-bit type with the same element
14947 // type as the input type.
14948 MVT EltVT = VT.getVectorElementType();
14949 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14951 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14952 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14955 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14956 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14957 /// necessary casting for \p Mask when lowering masking intrinsics.
14958 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14959 SDValue PreservedSrc,
14960 const X86Subtarget *Subtarget,
14961 SelectionDAG &DAG) {
14962 EVT VT = Op.getValueType();
14963 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14964 MVT::i1, VT.getVectorNumElements());
14965 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14966 Mask.getValueType().getSizeInBits());
14969 assert(MaskVT.isSimple() && "invalid mask type");
14971 if (isAllOnes(Mask))
14974 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14975 // are extracted by EXTRACT_SUBVECTOR.
14976 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14977 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14978 DAG.getIntPtrConstant(0, dl));
14980 switch (Op.getOpcode()) {
14982 case X86ISD::PCMPEQM:
14983 case X86ISD::PCMPGTM:
14985 case X86ISD::CMPMU:
14986 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14988 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14989 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14990 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14993 /// \brief Creates an SDNode for a predicated scalar operation.
14994 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14995 /// The mask is comming as MVT::i8 and it should be truncated
14996 /// to MVT::i1 while lowering masking intrinsics.
14997 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14998 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14999 /// a scalar instruction.
15000 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15001 SDValue PreservedSrc,
15002 const X86Subtarget *Subtarget,
15003 SelectionDAG &DAG) {
15004 if (isAllOnes(Mask))
15007 EVT VT = Op.getValueType();
15009 // The mask should be of type MVT::i1
15010 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15012 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15013 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15014 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15017 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15018 SelectionDAG &DAG) {
15020 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15021 EVT VT = Op.getValueType();
15022 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15024 switch(IntrData->Type) {
15025 case INTR_TYPE_1OP:
15026 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15027 case INTR_TYPE_2OP:
15028 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15030 case INTR_TYPE_3OP:
15031 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15032 Op.getOperand(2), Op.getOperand(3));
15033 case INTR_TYPE_1OP_MASK_RM: {
15034 SDValue Src = Op.getOperand(1);
15035 SDValue Src0 = Op.getOperand(2);
15036 SDValue Mask = Op.getOperand(3);
15037 SDValue RoundingMode = Op.getOperand(4);
15038 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15040 Mask, Src0, Subtarget, DAG);
15042 case INTR_TYPE_SCALAR_MASK_RM: {
15043 SDValue Src1 = Op.getOperand(1);
15044 SDValue Src2 = Op.getOperand(2);
15045 SDValue Src0 = Op.getOperand(3);
15046 SDValue Mask = Op.getOperand(4);
15047 // There are 2 kinds of intrinsics in this group:
15048 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15049 // (2) With rounding mode and sae - 7 operands.
15050 if (Op.getNumOperands() == 6) {
15051 SDValue Sae = Op.getOperand(5);
15052 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15053 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15055 Mask, Src0, Subtarget, DAG);
15057 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15058 SDValue RoundingMode = Op.getOperand(5);
15059 SDValue Sae = Op.getOperand(6);
15060 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15061 RoundingMode, Sae),
15062 Mask, Src0, Subtarget, DAG);
15064 case INTR_TYPE_2OP_MASK: {
15065 SDValue Src1 = Op.getOperand(1);
15066 SDValue Src2 = Op.getOperand(2);
15067 SDValue PassThru = Op.getOperand(3);
15068 SDValue Mask = Op.getOperand(4);
15069 // We specify 2 possible opcodes for intrinsics with rounding modes.
15070 // First, we check if the intrinsic may have non-default rounding mode,
15071 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15072 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15073 if (IntrWithRoundingModeOpcode != 0) {
15074 SDValue Rnd = Op.getOperand(5);
15075 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15076 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15077 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15078 dl, Op.getValueType(),
15080 Mask, PassThru, Subtarget, DAG);
15083 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15085 Mask, PassThru, Subtarget, DAG);
15087 case FMA_OP_MASK: {
15088 SDValue Src1 = Op.getOperand(1);
15089 SDValue Src2 = Op.getOperand(2);
15090 SDValue Src3 = Op.getOperand(3);
15091 SDValue Mask = Op.getOperand(4);
15092 // We specify 2 possible opcodes for intrinsics with rounding modes.
15093 // First, we check if the intrinsic may have non-default rounding mode,
15094 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15095 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15096 if (IntrWithRoundingModeOpcode != 0) {
15097 SDValue Rnd = Op.getOperand(5);
15098 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15099 X86::STATIC_ROUNDING::CUR_DIRECTION)
15100 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15101 dl, Op.getValueType(),
15102 Src1, Src2, Src3, Rnd),
15103 Mask, Src1, Subtarget, DAG);
15105 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15106 dl, Op.getValueType(),
15108 Mask, Src1, Subtarget, DAG);
15111 case CMP_MASK_CC: {
15112 // Comparison intrinsics with masks.
15113 // Example of transformation:
15114 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15115 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15117 // (v8i1 (insert_subvector undef,
15118 // (v2i1 (and (PCMPEQM %a, %b),
15119 // (extract_subvector
15120 // (v8i1 (bitcast %mask)), 0))), 0))))
15121 EVT VT = Op.getOperand(1).getValueType();
15122 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15123 VT.getVectorNumElements());
15124 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15125 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15126 Mask.getValueType().getSizeInBits());
15128 if (IntrData->Type == CMP_MASK_CC) {
15129 SDValue CC = Op.getOperand(3);
15130 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15131 // We specify 2 possible opcodes for intrinsics with rounding modes.
15132 // First, we check if the intrinsic may have non-default rounding mode,
15133 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15134 if (IntrData->Opc1 != 0) {
15135 SDValue Rnd = Op.getOperand(5);
15136 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15137 X86::STATIC_ROUNDING::CUR_DIRECTION)
15138 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15139 Op.getOperand(2), CC, Rnd);
15141 //default rounding mode
15143 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15144 Op.getOperand(2), CC);
15147 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15148 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15151 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15152 DAG.getTargetConstant(0, dl,
15155 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15156 DAG.getUNDEF(BitcastVT), CmpMask,
15157 DAG.getIntPtrConstant(0, dl));
15158 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
15160 case COMI: { // Comparison intrinsics
15161 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15162 SDValue LHS = Op.getOperand(1);
15163 SDValue RHS = Op.getOperand(2);
15164 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15165 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15166 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15167 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15168 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15169 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15172 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15173 Op.getOperand(1), Op.getOperand(2), DAG);
15175 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15176 Op.getSimpleValueType(),
15178 Op.getOperand(2), DAG),
15179 Op.getOperand(4), Op.getOperand(3), Subtarget,
15181 case COMPRESS_EXPAND_IN_REG: {
15182 SDValue Mask = Op.getOperand(3);
15183 SDValue DataToCompress = Op.getOperand(1);
15184 SDValue PassThru = Op.getOperand(2);
15185 if (isAllOnes(Mask)) // return data as is
15186 return Op.getOperand(1);
15187 EVT VT = Op.getValueType();
15188 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15189 VT.getVectorNumElements());
15190 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15191 Mask.getValueType().getSizeInBits());
15193 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15194 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15195 DAG.getIntPtrConstant(0, dl));
15197 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15201 SDValue Mask = Op.getOperand(3);
15202 EVT VT = Op.getValueType();
15203 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15204 VT.getVectorNumElements());
15205 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15206 Mask.getValueType().getSizeInBits());
15208 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15209 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15210 DAG.getIntPtrConstant(0, dl));
15211 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15220 default: return SDValue(); // Don't custom lower most intrinsics.
15222 case Intrinsic::x86_avx2_permd:
15223 case Intrinsic::x86_avx2_permps:
15224 // Operands intentionally swapped. Mask is last operand to intrinsic,
15225 // but second operand for node/instruction.
15226 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15227 Op.getOperand(2), Op.getOperand(1));
15229 case Intrinsic::x86_avx512_mask_valign_q_512:
15230 case Intrinsic::x86_avx512_mask_valign_d_512:
15231 // Vector source operands are swapped.
15232 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15233 Op.getValueType(), Op.getOperand(2),
15236 Op.getOperand(5), Op.getOperand(4),
15239 // ptest and testp intrinsics. The intrinsic these come from are designed to
15240 // return an integer value, not just an instruction so lower it to the ptest
15241 // or testp pattern and a setcc for the result.
15242 case Intrinsic::x86_sse41_ptestz:
15243 case Intrinsic::x86_sse41_ptestc:
15244 case Intrinsic::x86_sse41_ptestnzc:
15245 case Intrinsic::x86_avx_ptestz_256:
15246 case Intrinsic::x86_avx_ptestc_256:
15247 case Intrinsic::x86_avx_ptestnzc_256:
15248 case Intrinsic::x86_avx_vtestz_ps:
15249 case Intrinsic::x86_avx_vtestc_ps:
15250 case Intrinsic::x86_avx_vtestnzc_ps:
15251 case Intrinsic::x86_avx_vtestz_pd:
15252 case Intrinsic::x86_avx_vtestc_pd:
15253 case Intrinsic::x86_avx_vtestnzc_pd:
15254 case Intrinsic::x86_avx_vtestz_ps_256:
15255 case Intrinsic::x86_avx_vtestc_ps_256:
15256 case Intrinsic::x86_avx_vtestnzc_ps_256:
15257 case Intrinsic::x86_avx_vtestz_pd_256:
15258 case Intrinsic::x86_avx_vtestc_pd_256:
15259 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15260 bool IsTestPacked = false;
15263 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15264 case Intrinsic::x86_avx_vtestz_ps:
15265 case Intrinsic::x86_avx_vtestz_pd:
15266 case Intrinsic::x86_avx_vtestz_ps_256:
15267 case Intrinsic::x86_avx_vtestz_pd_256:
15268 IsTestPacked = true; // Fallthrough
15269 case Intrinsic::x86_sse41_ptestz:
15270 case Intrinsic::x86_avx_ptestz_256:
15272 X86CC = X86::COND_E;
15274 case Intrinsic::x86_avx_vtestc_ps:
15275 case Intrinsic::x86_avx_vtestc_pd:
15276 case Intrinsic::x86_avx_vtestc_ps_256:
15277 case Intrinsic::x86_avx_vtestc_pd_256:
15278 IsTestPacked = true; // Fallthrough
15279 case Intrinsic::x86_sse41_ptestc:
15280 case Intrinsic::x86_avx_ptestc_256:
15282 X86CC = X86::COND_B;
15284 case Intrinsic::x86_avx_vtestnzc_ps:
15285 case Intrinsic::x86_avx_vtestnzc_pd:
15286 case Intrinsic::x86_avx_vtestnzc_ps_256:
15287 case Intrinsic::x86_avx_vtestnzc_pd_256:
15288 IsTestPacked = true; // Fallthrough
15289 case Intrinsic::x86_sse41_ptestnzc:
15290 case Intrinsic::x86_avx_ptestnzc_256:
15292 X86CC = X86::COND_A;
15296 SDValue LHS = Op.getOperand(1);
15297 SDValue RHS = Op.getOperand(2);
15298 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15299 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15300 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15301 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15302 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15304 case Intrinsic::x86_avx512_kortestz_w:
15305 case Intrinsic::x86_avx512_kortestc_w: {
15306 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15307 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15308 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15309 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15310 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15311 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15312 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15315 case Intrinsic::x86_sse42_pcmpistria128:
15316 case Intrinsic::x86_sse42_pcmpestria128:
15317 case Intrinsic::x86_sse42_pcmpistric128:
15318 case Intrinsic::x86_sse42_pcmpestric128:
15319 case Intrinsic::x86_sse42_pcmpistrio128:
15320 case Intrinsic::x86_sse42_pcmpestrio128:
15321 case Intrinsic::x86_sse42_pcmpistris128:
15322 case Intrinsic::x86_sse42_pcmpestris128:
15323 case Intrinsic::x86_sse42_pcmpistriz128:
15324 case Intrinsic::x86_sse42_pcmpestriz128: {
15328 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15329 case Intrinsic::x86_sse42_pcmpistria128:
15330 Opcode = X86ISD::PCMPISTRI;
15331 X86CC = X86::COND_A;
15333 case Intrinsic::x86_sse42_pcmpestria128:
15334 Opcode = X86ISD::PCMPESTRI;
15335 X86CC = X86::COND_A;
15337 case Intrinsic::x86_sse42_pcmpistric128:
15338 Opcode = X86ISD::PCMPISTRI;
15339 X86CC = X86::COND_B;
15341 case Intrinsic::x86_sse42_pcmpestric128:
15342 Opcode = X86ISD::PCMPESTRI;
15343 X86CC = X86::COND_B;
15345 case Intrinsic::x86_sse42_pcmpistrio128:
15346 Opcode = X86ISD::PCMPISTRI;
15347 X86CC = X86::COND_O;
15349 case Intrinsic::x86_sse42_pcmpestrio128:
15350 Opcode = X86ISD::PCMPESTRI;
15351 X86CC = X86::COND_O;
15353 case Intrinsic::x86_sse42_pcmpistris128:
15354 Opcode = X86ISD::PCMPISTRI;
15355 X86CC = X86::COND_S;
15357 case Intrinsic::x86_sse42_pcmpestris128:
15358 Opcode = X86ISD::PCMPESTRI;
15359 X86CC = X86::COND_S;
15361 case Intrinsic::x86_sse42_pcmpistriz128:
15362 Opcode = X86ISD::PCMPISTRI;
15363 X86CC = X86::COND_E;
15365 case Intrinsic::x86_sse42_pcmpestriz128:
15366 Opcode = X86ISD::PCMPESTRI;
15367 X86CC = X86::COND_E;
15370 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15371 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15372 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15373 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15374 DAG.getConstant(X86CC, dl, MVT::i8),
15375 SDValue(PCMP.getNode(), 1));
15376 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15379 case Intrinsic::x86_sse42_pcmpistri128:
15380 case Intrinsic::x86_sse42_pcmpestri128: {
15382 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15383 Opcode = X86ISD::PCMPISTRI;
15385 Opcode = X86ISD::PCMPESTRI;
15387 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15388 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15389 return DAG.getNode(Opcode, dl, VTs, NewOps);
15392 case Intrinsic::x86_seh_lsda: {
15393 // Compute the symbol for the LSDA. We know it'll get emitted later.
15394 MachineFunction &MF = DAG.getMachineFunction();
15395 SDValue Op1 = Op.getOperand(1);
15396 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15397 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15398 GlobalValue::getRealLinkageName(Fn->getName()));
15399 StringRef Name = LSDASym->getName();
15400 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
15402 // Generate a simple absolute symbol reference. This intrinsic is only
15403 // supported on 32-bit Windows, which isn't PIC.
15405 DAG.getTargetExternalSymbol(Name.data(), VT, X86II::MO_NOPREFIX);
15406 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15411 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15412 SDValue Src, SDValue Mask, SDValue Base,
15413 SDValue Index, SDValue ScaleOp, SDValue Chain,
15414 const X86Subtarget * Subtarget) {
15416 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15417 assert(C && "Invalid scale type");
15418 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15419 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15420 Index.getSimpleValueType().getVectorNumElements());
15422 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15424 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15426 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15427 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15428 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15429 SDValue Segment = DAG.getRegister(0, MVT::i32);
15430 if (Src.getOpcode() == ISD::UNDEF)
15431 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15432 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15433 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15434 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15435 return DAG.getMergeValues(RetOps, dl);
15438 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15439 SDValue Src, SDValue Mask, SDValue Base,
15440 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15442 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15443 assert(C && "Invalid scale type");
15444 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15445 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15446 SDValue Segment = DAG.getRegister(0, MVT::i32);
15447 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15448 Index.getSimpleValueType().getVectorNumElements());
15450 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15452 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15454 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15455 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15456 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15457 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15458 return SDValue(Res, 1);
15461 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15462 SDValue Mask, SDValue Base, SDValue Index,
15463 SDValue ScaleOp, SDValue Chain) {
15465 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15466 assert(C && "Invalid scale type");
15467 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15468 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15469 SDValue Segment = DAG.getRegister(0, MVT::i32);
15471 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15473 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15475 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15477 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15478 //SDVTList VTs = DAG.getVTList(MVT::Other);
15479 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15480 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15481 return SDValue(Res, 0);
15484 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15485 // read performance monitor counters (x86_rdpmc).
15486 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15487 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15488 SmallVectorImpl<SDValue> &Results) {
15489 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15490 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15493 // The ECX register is used to select the index of the performance counter
15495 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15497 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15499 // Reads the content of a 64-bit performance counter and returns it in the
15500 // registers EDX:EAX.
15501 if (Subtarget->is64Bit()) {
15502 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15503 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15506 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15507 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15510 Chain = HI.getValue(1);
15512 if (Subtarget->is64Bit()) {
15513 // The EAX register is loaded with the low-order 32 bits. The EDX register
15514 // is loaded with the supported high-order bits of the counter.
15515 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15516 DAG.getConstant(32, DL, MVT::i8));
15517 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15518 Results.push_back(Chain);
15522 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15523 SDValue Ops[] = { LO, HI };
15524 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15525 Results.push_back(Pair);
15526 Results.push_back(Chain);
15529 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15530 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15531 // also used to custom lower READCYCLECOUNTER nodes.
15532 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15533 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15534 SmallVectorImpl<SDValue> &Results) {
15535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15536 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15539 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15540 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15541 // and the EAX register is loaded with the low-order 32 bits.
15542 if (Subtarget->is64Bit()) {
15543 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15544 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15547 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15548 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15551 SDValue Chain = HI.getValue(1);
15553 if (Opcode == X86ISD::RDTSCP_DAG) {
15554 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15556 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15557 // the ECX register. Add 'ecx' explicitly to the chain.
15558 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15560 // Explicitly store the content of ECX at the location passed in input
15561 // to the 'rdtscp' intrinsic.
15562 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15563 MachinePointerInfo(), false, false, 0);
15566 if (Subtarget->is64Bit()) {
15567 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15568 // the EAX register is loaded with the low-order 32 bits.
15569 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15570 DAG.getConstant(32, DL, MVT::i8));
15571 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15572 Results.push_back(Chain);
15576 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15577 SDValue Ops[] = { LO, HI };
15578 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15579 Results.push_back(Pair);
15580 Results.push_back(Chain);
15583 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15584 SelectionDAG &DAG) {
15585 SmallVector<SDValue, 2> Results;
15587 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15589 return DAG.getMergeValues(Results, DL);
15593 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15594 SelectionDAG &DAG) {
15595 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15597 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15602 switch(IntrData->Type) {
15604 llvm_unreachable("Unknown Intrinsic Type");
15608 // Emit the node with the right value type.
15609 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15610 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15612 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15613 // Otherwise return the value from Rand, which is always 0, casted to i32.
15614 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15615 DAG.getConstant(1, dl, Op->getValueType(1)),
15616 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15617 SDValue(Result.getNode(), 1) };
15618 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15619 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15622 // Return { result, isValid, chain }.
15623 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15624 SDValue(Result.getNode(), 2));
15627 //gather(v1, mask, index, base, scale);
15628 SDValue Chain = Op.getOperand(0);
15629 SDValue Src = Op.getOperand(2);
15630 SDValue Base = Op.getOperand(3);
15631 SDValue Index = Op.getOperand(4);
15632 SDValue Mask = Op.getOperand(5);
15633 SDValue Scale = Op.getOperand(6);
15634 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15638 //scatter(base, mask, index, v1, scale);
15639 SDValue Chain = Op.getOperand(0);
15640 SDValue Base = Op.getOperand(2);
15641 SDValue Mask = Op.getOperand(3);
15642 SDValue Index = Op.getOperand(4);
15643 SDValue Src = Op.getOperand(5);
15644 SDValue Scale = Op.getOperand(6);
15645 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15649 SDValue Hint = Op.getOperand(6);
15650 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15651 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15652 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15653 SDValue Chain = Op.getOperand(0);
15654 SDValue Mask = Op.getOperand(2);
15655 SDValue Index = Op.getOperand(3);
15656 SDValue Base = Op.getOperand(4);
15657 SDValue Scale = Op.getOperand(5);
15658 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15660 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15662 SmallVector<SDValue, 2> Results;
15663 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15665 return DAG.getMergeValues(Results, dl);
15667 // Read Performance Monitoring Counters.
15669 SmallVector<SDValue, 2> Results;
15670 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15671 return DAG.getMergeValues(Results, dl);
15673 // XTEST intrinsics.
15675 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15676 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15677 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15678 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15680 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15681 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15682 Ret, SDValue(InTrans.getNode(), 1));
15686 SmallVector<SDValue, 2> Results;
15687 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15688 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15689 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15690 DAG.getConstant(-1, dl, MVT::i8));
15691 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15692 Op.getOperand(4), GenCF.getValue(1));
15693 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15694 Op.getOperand(5), MachinePointerInfo(),
15696 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15697 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15699 Results.push_back(SetCC);
15700 Results.push_back(Store);
15701 return DAG.getMergeValues(Results, dl);
15703 case COMPRESS_TO_MEM: {
15705 SDValue Mask = Op.getOperand(4);
15706 SDValue DataToCompress = Op.getOperand(3);
15707 SDValue Addr = Op.getOperand(2);
15708 SDValue Chain = Op.getOperand(0);
15710 if (isAllOnes(Mask)) // return just a store
15711 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15712 MachinePointerInfo(), false, false, 0);
15714 EVT VT = DataToCompress.getValueType();
15715 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15716 VT.getVectorNumElements());
15717 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15718 Mask.getValueType().getSizeInBits());
15719 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15720 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15721 DAG.getIntPtrConstant(0, dl));
15723 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15724 DataToCompress, DAG.getUNDEF(VT));
15725 return DAG.getStore(Chain, dl, Compressed, Addr,
15726 MachinePointerInfo(), false, false, 0);
15728 case EXPAND_FROM_MEM: {
15730 SDValue Mask = Op.getOperand(4);
15731 SDValue PathThru = Op.getOperand(3);
15732 SDValue Addr = Op.getOperand(2);
15733 SDValue Chain = Op.getOperand(0);
15734 EVT VT = Op.getValueType();
15736 if (isAllOnes(Mask)) // return just a load
15737 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15739 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15740 VT.getVectorNumElements());
15741 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15742 Mask.getValueType().getSizeInBits());
15743 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15744 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15745 DAG.getIntPtrConstant(0, dl));
15747 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15748 false, false, false, 0);
15750 SDValue Results[] = {
15751 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15753 return DAG.getMergeValues(Results, dl);
15758 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15759 SelectionDAG &DAG) const {
15760 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15761 MFI->setReturnAddressIsTaken(true);
15763 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15766 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15768 EVT PtrVT = getPointerTy();
15771 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15772 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15773 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15774 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15775 DAG.getNode(ISD::ADD, dl, PtrVT,
15776 FrameAddr, Offset),
15777 MachinePointerInfo(), false, false, false, 0);
15780 // Just load the return address.
15781 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15782 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15783 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15786 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15787 MachineFunction &MF = DAG.getMachineFunction();
15788 MachineFrameInfo *MFI = MF.getFrameInfo();
15789 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15790 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15791 EVT VT = Op.getValueType();
15793 MFI->setFrameAddressIsTaken(true);
15795 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15796 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15797 // is not possible to crawl up the stack without looking at the unwind codes
15799 int FrameAddrIndex = FuncInfo->getFAIndex();
15800 if (!FrameAddrIndex) {
15801 // Set up a frame object for the return address.
15802 unsigned SlotSize = RegInfo->getSlotSize();
15803 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15804 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15805 FuncInfo->setFAIndex(FrameAddrIndex);
15807 return DAG.getFrameIndex(FrameAddrIndex, VT);
15810 unsigned FrameReg =
15811 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15812 SDLoc dl(Op); // FIXME probably not meaningful
15813 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15814 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15815 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15816 "Invalid Frame Register!");
15817 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15819 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15820 MachinePointerInfo(),
15821 false, false, false, 0);
15825 // FIXME? Maybe this could be a TableGen attribute on some registers and
15826 // this table could be generated automatically from RegInfo.
15827 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15829 unsigned Reg = StringSwitch<unsigned>(RegName)
15830 .Case("esp", X86::ESP)
15831 .Case("rsp", X86::RSP)
15835 report_fatal_error("Invalid register name global variable");
15838 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15839 SelectionDAG &DAG) const {
15840 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15841 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15844 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15845 SDValue Chain = Op.getOperand(0);
15846 SDValue Offset = Op.getOperand(1);
15847 SDValue Handler = Op.getOperand(2);
15850 EVT PtrVT = getPointerTy();
15851 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15852 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15853 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15854 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15855 "Invalid Frame Register!");
15856 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15857 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15859 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15860 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15862 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15863 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15865 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15867 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15868 DAG.getRegister(StoreAddrReg, PtrVT));
15871 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15872 SelectionDAG &DAG) const {
15874 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15875 DAG.getVTList(MVT::i32, MVT::Other),
15876 Op.getOperand(0), Op.getOperand(1));
15879 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15880 SelectionDAG &DAG) const {
15882 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15883 Op.getOperand(0), Op.getOperand(1));
15886 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15887 return Op.getOperand(0);
15890 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15891 SelectionDAG &DAG) const {
15892 SDValue Root = Op.getOperand(0);
15893 SDValue Trmp = Op.getOperand(1); // trampoline
15894 SDValue FPtr = Op.getOperand(2); // nested function
15895 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15898 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15899 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15901 if (Subtarget->is64Bit()) {
15902 SDValue OutChains[6];
15904 // Large code-model.
15905 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15906 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15908 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15909 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15911 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15913 // Load the pointer to the nested function into R11.
15914 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15915 SDValue Addr = Trmp;
15916 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15917 Addr, MachinePointerInfo(TrmpAddr),
15920 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15921 DAG.getConstant(2, dl, MVT::i64));
15922 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15923 MachinePointerInfo(TrmpAddr, 2),
15926 // Load the 'nest' parameter value into R10.
15927 // R10 is specified in X86CallingConv.td
15928 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15929 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15930 DAG.getConstant(10, dl, MVT::i64));
15931 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15932 Addr, MachinePointerInfo(TrmpAddr, 10),
15935 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15936 DAG.getConstant(12, dl, MVT::i64));
15937 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15938 MachinePointerInfo(TrmpAddr, 12),
15941 // Jump to the nested function.
15942 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15943 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15944 DAG.getConstant(20, dl, MVT::i64));
15945 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15946 Addr, MachinePointerInfo(TrmpAddr, 20),
15949 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15950 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15951 DAG.getConstant(22, dl, MVT::i64));
15952 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
15953 Addr, MachinePointerInfo(TrmpAddr, 22),
15956 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15958 const Function *Func =
15959 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15960 CallingConv::ID CC = Func->getCallingConv();
15965 llvm_unreachable("Unsupported calling convention");
15966 case CallingConv::C:
15967 case CallingConv::X86_StdCall: {
15968 // Pass 'nest' parameter in ECX.
15969 // Must be kept in sync with X86CallingConv.td
15970 NestReg = X86::ECX;
15972 // Check that ECX wasn't needed by an 'inreg' parameter.
15973 FunctionType *FTy = Func->getFunctionType();
15974 const AttributeSet &Attrs = Func->getAttributes();
15976 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15977 unsigned InRegCount = 0;
15980 for (FunctionType::param_iterator I = FTy->param_begin(),
15981 E = FTy->param_end(); I != E; ++I, ++Idx)
15982 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15983 // FIXME: should only count parameters that are lowered to integers.
15984 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15986 if (InRegCount > 2) {
15987 report_fatal_error("Nest register in use - reduce number of inreg"
15993 case CallingConv::X86_FastCall:
15994 case CallingConv::X86_ThisCall:
15995 case CallingConv::Fast:
15996 // Pass 'nest' parameter in EAX.
15997 // Must be kept in sync with X86CallingConv.td
15998 NestReg = X86::EAX;
16002 SDValue OutChains[4];
16003 SDValue Addr, Disp;
16005 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16006 DAG.getConstant(10, dl, MVT::i32));
16007 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16009 // This is storing the opcode for MOV32ri.
16010 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16011 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16012 OutChains[0] = DAG.getStore(Root, dl,
16013 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16014 Trmp, MachinePointerInfo(TrmpAddr),
16017 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16018 DAG.getConstant(1, dl, MVT::i32));
16019 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16020 MachinePointerInfo(TrmpAddr, 1),
16023 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16024 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16025 DAG.getConstant(5, dl, MVT::i32));
16026 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16027 Addr, MachinePointerInfo(TrmpAddr, 5),
16030 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16031 DAG.getConstant(6, dl, MVT::i32));
16032 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16033 MachinePointerInfo(TrmpAddr, 6),
16036 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16040 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16041 SelectionDAG &DAG) const {
16043 The rounding mode is in bits 11:10 of FPSR, and has the following
16045 00 Round to nearest
16050 FLT_ROUNDS, on the other hand, expects the following:
16057 To perform the conversion, we do:
16058 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16061 MachineFunction &MF = DAG.getMachineFunction();
16062 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16063 unsigned StackAlignment = TFI.getStackAlignment();
16064 MVT VT = Op.getSimpleValueType();
16067 // Save FP Control Word to stack slot
16068 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16069 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16071 MachineMemOperand *MMO =
16072 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16073 MachineMemOperand::MOStore, 2, 2);
16075 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16076 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16077 DAG.getVTList(MVT::Other),
16078 Ops, MVT::i16, MMO);
16080 // Load FP Control Word from stack slot
16081 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16082 MachinePointerInfo(), false, false, false, 0);
16084 // Transform as necessary
16086 DAG.getNode(ISD::SRL, DL, MVT::i16,
16087 DAG.getNode(ISD::AND, DL, MVT::i16,
16088 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16089 DAG.getConstant(11, DL, MVT::i8));
16091 DAG.getNode(ISD::SRL, DL, MVT::i16,
16092 DAG.getNode(ISD::AND, DL, MVT::i16,
16093 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16094 DAG.getConstant(9, DL, MVT::i8));
16097 DAG.getNode(ISD::AND, DL, MVT::i16,
16098 DAG.getNode(ISD::ADD, DL, MVT::i16,
16099 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16100 DAG.getConstant(1, DL, MVT::i16)),
16101 DAG.getConstant(3, DL, MVT::i16));
16103 return DAG.getNode((VT.getSizeInBits() < 16 ?
16104 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16107 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16108 MVT VT = Op.getSimpleValueType();
16110 unsigned NumBits = VT.getSizeInBits();
16113 Op = Op.getOperand(0);
16114 if (VT == MVT::i8) {
16115 // Zero extend to i32 since there is not an i8 bsr.
16117 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16120 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16121 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16122 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16124 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16127 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16128 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16131 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16133 // Finally xor with NumBits-1.
16134 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16135 DAG.getConstant(NumBits - 1, dl, OpVT));
16138 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16142 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16143 MVT VT = Op.getSimpleValueType();
16145 unsigned NumBits = VT.getSizeInBits();
16148 Op = Op.getOperand(0);
16149 if (VT == MVT::i8) {
16150 // Zero extend to i32 since there is not an i8 bsr.
16152 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16155 // Issue a bsr (scan bits in reverse).
16156 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16157 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16159 // And xor with NumBits-1.
16160 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16161 DAG.getConstant(NumBits - 1, dl, OpVT));
16164 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16168 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16169 MVT VT = Op.getSimpleValueType();
16170 unsigned NumBits = VT.getSizeInBits();
16172 Op = Op.getOperand(0);
16174 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16175 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16176 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16178 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16181 DAG.getConstant(NumBits, dl, VT),
16182 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16185 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16188 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16189 // ones, and then concatenate the result back.
16190 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16191 MVT VT = Op.getSimpleValueType();
16193 assert(VT.is256BitVector() && VT.isInteger() &&
16194 "Unsupported value type for operation");
16196 unsigned NumElems = VT.getVectorNumElements();
16199 // Extract the LHS vectors
16200 SDValue LHS = Op.getOperand(0);
16201 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16202 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16204 // Extract the RHS vectors
16205 SDValue RHS = Op.getOperand(1);
16206 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16207 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16209 MVT EltVT = VT.getVectorElementType();
16210 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16212 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16213 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16214 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16217 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16218 if (Op.getValueType() == MVT::i1)
16219 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16220 Op.getOperand(0), Op.getOperand(1));
16221 assert(Op.getSimpleValueType().is256BitVector() &&
16222 Op.getSimpleValueType().isInteger() &&
16223 "Only handle AVX 256-bit vector integer operation");
16224 return Lower256IntArith(Op, DAG);
16227 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16228 if (Op.getValueType() == MVT::i1)
16229 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16230 Op.getOperand(0), Op.getOperand(1));
16231 assert(Op.getSimpleValueType().is256BitVector() &&
16232 Op.getSimpleValueType().isInteger() &&
16233 "Only handle AVX 256-bit vector integer operation");
16234 return Lower256IntArith(Op, DAG);
16237 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16238 SelectionDAG &DAG) {
16240 MVT VT = Op.getSimpleValueType();
16243 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16245 // Decompose 256-bit ops into smaller 128-bit ops.
16246 if (VT.is256BitVector() && !Subtarget->hasInt256())
16247 return Lower256IntArith(Op, DAG);
16249 SDValue A = Op.getOperand(0);
16250 SDValue B = Op.getOperand(1);
16252 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16253 // pairs, multiply and truncate.
16254 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16255 if (Subtarget->hasInt256()) {
16256 if (VT == MVT::v32i8) {
16257 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16258 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16259 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16260 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16261 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16262 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16263 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16264 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16265 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16266 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16269 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16270 return DAG.getNode(
16271 ISD::TRUNCATE, dl, VT,
16272 DAG.getNode(ISD::MUL, dl, ExVT,
16273 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16274 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16277 assert(VT == MVT::v16i8 &&
16278 "Pre-AVX2 support only supports v16i8 multiplication");
16279 MVT ExVT = MVT::v8i16;
16281 // Extract the lo parts and sign extend to i16
16283 if (Subtarget->hasSSE41()) {
16284 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16285 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16287 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16288 -1, 4, -1, 5, -1, 6, -1, 7};
16289 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16290 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16291 ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);
16292 BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);
16293 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16294 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16297 // Extract the hi parts and sign extend to i16
16299 if (Subtarget->hasSSE41()) {
16300 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16301 -1, -1, -1, -1, -1, -1, -1, -1};
16302 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16303 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16304 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16305 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16307 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16308 -1, 12, -1, 13, -1, 14, -1, 15};
16309 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16310 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16311 AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);
16312 BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);
16313 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16314 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16317 // Multiply, mask the lower 8bits of the lo/hi results and pack
16318 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16319 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16320 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16321 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16322 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16325 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16326 if (VT == MVT::v4i32) {
16327 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16328 "Should not custom lower when pmuldq is available!");
16330 // Extract the odd parts.
16331 static const int UnpackMask[] = { 1, -1, 3, -1 };
16332 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16333 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16335 // Multiply the even parts.
16336 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16337 // Now multiply odd parts.
16338 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16340 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16341 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16343 // Merge the two vectors back together with a shuffle. This expands into 2
16345 static const int ShufMask[] = { 0, 4, 2, 6 };
16346 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16349 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16350 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16352 // Ahi = psrlqi(a, 32);
16353 // Bhi = psrlqi(b, 32);
16355 // AloBlo = pmuludq(a, b);
16356 // AloBhi = pmuludq(a, Bhi);
16357 // AhiBlo = pmuludq(Ahi, b);
16359 // AloBhi = psllqi(AloBhi, 32);
16360 // AhiBlo = psllqi(AhiBlo, 32);
16361 // return AloBlo + AloBhi + AhiBlo;
16363 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16364 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16366 // Bit cast to 32-bit vectors for MULUDQ
16367 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16368 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16369 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16370 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16371 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16372 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16374 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16375 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16376 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16378 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16379 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16381 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16382 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16385 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16386 assert(Subtarget->isTargetWin64() && "Unexpected target");
16387 EVT VT = Op.getValueType();
16388 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16389 "Unexpected return type for lowering");
16393 switch (Op->getOpcode()) {
16394 default: llvm_unreachable("Unexpected request for libcall!");
16395 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16396 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16397 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16398 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16399 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16400 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16404 SDValue InChain = DAG.getEntryNode();
16406 TargetLowering::ArgListTy Args;
16407 TargetLowering::ArgListEntry Entry;
16408 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16409 EVT ArgVT = Op->getOperand(i).getValueType();
16410 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16411 "Unexpected argument type for lowering");
16412 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16413 Entry.Node = StackPtr;
16414 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16416 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16417 Entry.Ty = PointerType::get(ArgTy,0);
16418 Entry.isSExt = false;
16419 Entry.isZExt = false;
16420 Args.push_back(Entry);
16423 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16426 TargetLowering::CallLoweringInfo CLI(DAG);
16427 CLI.setDebugLoc(dl).setChain(InChain)
16428 .setCallee(getLibcallCallingConv(LC),
16429 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16430 Callee, std::move(Args), 0)
16431 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16433 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16434 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16437 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16438 SelectionDAG &DAG) {
16439 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16440 EVT VT = Op0.getValueType();
16443 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16444 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16446 // PMULxD operations multiply each even value (starting at 0) of LHS with
16447 // the related value of RHS and produce a widen result.
16448 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16449 // => <2 x i64> <ae|cg>
16451 // In other word, to have all the results, we need to perform two PMULxD:
16452 // 1. one with the even values.
16453 // 2. one with the odd values.
16454 // To achieve #2, with need to place the odd values at an even position.
16456 // Place the odd value at an even position (basically, shift all values 1
16457 // step to the left):
16458 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16459 // <a|b|c|d> => <b|undef|d|undef>
16460 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16461 // <e|f|g|h> => <f|undef|h|undef>
16462 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16464 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16466 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16467 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16469 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16470 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16471 // => <2 x i64> <ae|cg>
16472 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16473 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16474 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16475 // => <2 x i64> <bf|dh>
16476 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16477 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16479 // Shuffle it back into the right order.
16480 SDValue Highs, Lows;
16481 if (VT == MVT::v8i32) {
16482 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16483 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16484 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16485 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16487 const int HighMask[] = {1, 5, 3, 7};
16488 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16489 const int LowMask[] = {0, 4, 2, 6};
16490 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16493 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16494 // unsigned multiply.
16495 if (IsSigned && !Subtarget->hasSSE41()) {
16497 DAG.getConstant(31, dl,
16498 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16499 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16500 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16501 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16502 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16504 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16505 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16508 // The first result of MUL_LOHI is actually the low value, followed by the
16510 SDValue Ops[] = {Lows, Highs};
16511 return DAG.getMergeValues(Ops, dl);
16514 // Return true if the requred (according to Opcode) shift-imm form is natively
16515 // supported by the Subtarget
16516 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16518 if (VT.getScalarSizeInBits() < 16)
16521 if (VT.is512BitVector() &&
16522 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16525 bool LShift = VT.is128BitVector() ||
16526 (VT.is256BitVector() && Subtarget->hasInt256());
16528 bool AShift = LShift && (Subtarget->hasVLX() ||
16529 (VT != MVT::v2i64 && VT != MVT::v4i64));
16530 return (Opcode == ISD::SRA) ? AShift : LShift;
16533 // The shift amount is a variable, but it is the same for all vector lanes.
16534 // These instrcutions are defined together with shift-immediate.
16536 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16538 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16541 // Return true if the requred (according to Opcode) variable-shift form is
16542 // natively supported by the Subtarget
16543 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16546 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16549 // vXi16 supported only on AVX-512, BWI
16550 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16553 if (VT.is512BitVector() || Subtarget->hasVLX())
16556 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16557 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16558 return (Opcode == ISD::SRA) ? AShift : LShift;
16561 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16562 const X86Subtarget *Subtarget) {
16563 MVT VT = Op.getSimpleValueType();
16565 SDValue R = Op.getOperand(0);
16566 SDValue Amt = Op.getOperand(1);
16568 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16569 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16571 // Optimize shl/srl/sra with constant shift amount.
16572 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16573 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16574 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16576 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16577 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16579 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16580 unsigned NumElts = VT.getVectorNumElements();
16581 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16583 if (Op.getOpcode() == ISD::SHL) {
16584 // Simple i8 add case
16586 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16588 // Make a large shift.
16589 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16591 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16592 // Zero out the rightmost bits.
16593 SmallVector<SDValue, 32> V(
16594 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16595 return DAG.getNode(ISD::AND, dl, VT, SHL,
16596 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16598 if (Op.getOpcode() == ISD::SRL) {
16599 // Make a large shift.
16600 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16602 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16603 // Zero out the leftmost bits.
16604 SmallVector<SDValue, 32> V(
16605 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16606 return DAG.getNode(ISD::AND, dl, VT, SRL,
16607 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16609 if (Op.getOpcode() == ISD::SRA) {
16610 if (ShiftAmt == 7) {
16611 // R s>> 7 === R s< 0
16612 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16613 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16616 // R s>> a === ((R u>> a) ^ m) - m
16617 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16618 SmallVector<SDValue, 32> V(NumElts,
16619 DAG.getConstant(128 >> ShiftAmt, dl,
16621 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16622 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16623 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16626 llvm_unreachable("Unknown shift opcode.");
16631 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16632 if (!Subtarget->is64Bit() &&
16633 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16634 Amt.getOpcode() == ISD::BITCAST &&
16635 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16636 Amt = Amt.getOperand(0);
16637 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16638 VT.getVectorNumElements();
16639 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16640 uint64_t ShiftAmt = 0;
16641 for (unsigned i = 0; i != Ratio; ++i) {
16642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16646 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16648 // Check remaining shift amounts.
16649 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16650 uint64_t ShAmt = 0;
16651 for (unsigned j = 0; j != Ratio; ++j) {
16652 ConstantSDNode *C =
16653 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16657 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16659 if (ShAmt != ShiftAmt)
16662 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16668 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16669 const X86Subtarget* Subtarget) {
16670 MVT VT = Op.getSimpleValueType();
16672 SDValue R = Op.getOperand(0);
16673 SDValue Amt = Op.getOperand(1);
16675 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16676 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16678 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16679 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16681 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16683 EVT EltVT = VT.getVectorElementType();
16685 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16686 // Check if this build_vector node is doing a splat.
16687 // If so, then set BaseShAmt equal to the splat value.
16688 BaseShAmt = BV->getSplatValue();
16689 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16690 BaseShAmt = SDValue();
16692 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16693 Amt = Amt.getOperand(0);
16695 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16696 if (SVN && SVN->isSplat()) {
16697 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16698 SDValue InVec = Amt.getOperand(0);
16699 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16700 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16701 "Unexpected shuffle index found!");
16702 BaseShAmt = InVec.getOperand(SplatIdx);
16703 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16704 if (ConstantSDNode *C =
16705 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16706 if (C->getZExtValue() == SplatIdx)
16707 BaseShAmt = InVec.getOperand(1);
16712 // Avoid introducing an extract element from a shuffle.
16713 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16714 DAG.getIntPtrConstant(SplatIdx, dl));
16718 if (BaseShAmt.getNode()) {
16719 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16720 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16721 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16722 else if (EltVT.bitsLT(MVT::i32))
16723 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16725 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16729 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16730 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16731 Amt.getOpcode() == ISD::BITCAST &&
16732 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16733 Amt = Amt.getOperand(0);
16734 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16735 VT.getVectorNumElements();
16736 std::vector<SDValue> Vals(Ratio);
16737 for (unsigned i = 0; i != Ratio; ++i)
16738 Vals[i] = Amt.getOperand(i);
16739 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16740 for (unsigned j = 0; j != Ratio; ++j)
16741 if (Vals[j] != Amt.getOperand(i + j))
16744 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16749 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16750 SelectionDAG &DAG) {
16751 MVT VT = Op.getSimpleValueType();
16753 SDValue R = Op.getOperand(0);
16754 SDValue Amt = Op.getOperand(1);
16756 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16757 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16759 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16762 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16765 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16768 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16769 // shifts per-lane and then shuffle the partial results back together.
16770 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16771 // Splat the shift amounts so the scalar shifts above will catch it.
16772 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16773 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16774 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16775 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16776 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16779 // If possible, lower this packed shift into a vector multiply instead of
16780 // expanding it into a sequence of scalar shifts.
16781 // Do this only if the vector shift count is a constant build_vector.
16782 if (Op.getOpcode() == ISD::SHL &&
16783 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16784 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16785 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16786 SmallVector<SDValue, 8> Elts;
16787 EVT SVT = VT.getScalarType();
16788 unsigned SVTBits = SVT.getSizeInBits();
16789 const APInt &One = APInt(SVTBits, 1);
16790 unsigned NumElems = VT.getVectorNumElements();
16792 for (unsigned i=0; i !=NumElems; ++i) {
16793 SDValue Op = Amt->getOperand(i);
16794 if (Op->getOpcode() == ISD::UNDEF) {
16795 Elts.push_back(Op);
16799 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16800 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16801 uint64_t ShAmt = C.getZExtValue();
16802 if (ShAmt >= SVTBits) {
16803 Elts.push_back(DAG.getUNDEF(SVT));
16806 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16808 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16809 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16812 // Lower SHL with variable shift amount.
16813 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16814 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16816 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16817 DAG.getConstant(0x3f800000U, dl, VT));
16818 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16819 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16820 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16823 // If possible, lower this shift as a sequence of two shifts by
16824 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16826 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16828 // Could be rewritten as:
16829 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16831 // The advantage is that the two shifts from the example would be
16832 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16833 // the vector shift into four scalar shifts plus four pairs of vector
16835 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16836 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16837 unsigned TargetOpcode = X86ISD::MOVSS;
16838 bool CanBeSimplified;
16839 // The splat value for the first packed shift (the 'X' from the example).
16840 SDValue Amt1 = Amt->getOperand(0);
16841 // The splat value for the second packed shift (the 'Y' from the example).
16842 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16843 Amt->getOperand(2);
16845 // See if it is possible to replace this node with a sequence of
16846 // two shifts followed by a MOVSS/MOVSD
16847 if (VT == MVT::v4i32) {
16848 // Check if it is legal to use a MOVSS.
16849 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16850 Amt2 == Amt->getOperand(3);
16851 if (!CanBeSimplified) {
16852 // Otherwise, check if we can still simplify this node using a MOVSD.
16853 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16854 Amt->getOperand(2) == Amt->getOperand(3);
16855 TargetOpcode = X86ISD::MOVSD;
16856 Amt2 = Amt->getOperand(2);
16859 // Do similar checks for the case where the machine value type
16861 CanBeSimplified = Amt1 == Amt->getOperand(1);
16862 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16863 CanBeSimplified = Amt2 == Amt->getOperand(i);
16865 if (!CanBeSimplified) {
16866 TargetOpcode = X86ISD::MOVSD;
16867 CanBeSimplified = true;
16868 Amt2 = Amt->getOperand(4);
16869 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16870 CanBeSimplified = Amt1 == Amt->getOperand(i);
16871 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16872 CanBeSimplified = Amt2 == Amt->getOperand(j);
16876 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16877 isa<ConstantSDNode>(Amt2)) {
16878 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16879 EVT CastVT = MVT::v4i32;
16881 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16882 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16884 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16885 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16886 if (TargetOpcode == X86ISD::MOVSD)
16887 CastVT = MVT::v2i64;
16888 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16889 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16890 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16892 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16896 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16897 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
16898 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
16900 SDValue VSelM = DAG.getConstant(0x80, dl, VT);
16901 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16902 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16904 // r = VSELECT(r, shl(r, 4), a);
16905 SDValue M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(4, dl, VT));
16906 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16909 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16910 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16911 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16913 // r = VSELECT(r, shl(r, 2), a);
16914 M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(2, dl, VT));
16915 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16918 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16919 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16920 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16922 // return VSELECT(r, r+r, a);
16923 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16924 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16928 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16929 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16930 // solution better.
16931 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16932 MVT ExtVT = MVT::v8i32;
16934 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16935 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
16936 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
16937 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16938 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
16941 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
16942 MVT ExtVT = MVT::v8i32;
16943 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
16944 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
16945 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
16946 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
16947 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
16948 ALo = DAG.getNode(ISD::BITCAST, dl, ExtVT, ALo);
16949 AHi = DAG.getNode(ISD::BITCAST, dl, ExtVT, AHi);
16950 RLo = DAG.getNode(ISD::BITCAST, dl, ExtVT, RLo);
16951 RHi = DAG.getNode(ISD::BITCAST, dl, ExtVT, RHi);
16952 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
16953 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
16954 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
16955 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
16956 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
16959 // Decompose 256-bit shifts into smaller 128-bit shifts.
16960 if (VT.is256BitVector()) {
16961 unsigned NumElems = VT.getVectorNumElements();
16962 MVT EltVT = VT.getVectorElementType();
16963 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16965 // Extract the two vectors
16966 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16967 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16969 // Recreate the shift amount vectors
16970 SDValue Amt1, Amt2;
16971 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16972 // Constant shift amount
16973 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16974 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16975 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16977 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16978 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16980 // Variable shift amount
16981 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16982 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16985 // Issue new vector shifts for the smaller types
16986 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16987 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16989 // Concatenate the result back
16990 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16996 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16997 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16998 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16999 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17000 // has only one use.
17001 SDNode *N = Op.getNode();
17002 SDValue LHS = N->getOperand(0);
17003 SDValue RHS = N->getOperand(1);
17004 unsigned BaseOp = 0;
17007 switch (Op.getOpcode()) {
17008 default: llvm_unreachable("Unknown ovf instruction!");
17010 // A subtract of one will be selected as a INC. Note that INC doesn't
17011 // set CF, so we can't do this for UADDO.
17012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17014 BaseOp = X86ISD::INC;
17015 Cond = X86::COND_O;
17018 BaseOp = X86ISD::ADD;
17019 Cond = X86::COND_O;
17022 BaseOp = X86ISD::ADD;
17023 Cond = X86::COND_B;
17026 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17027 // set CF, so we can't do this for USUBO.
17028 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17030 BaseOp = X86ISD::DEC;
17031 Cond = X86::COND_O;
17034 BaseOp = X86ISD::SUB;
17035 Cond = X86::COND_O;
17038 BaseOp = X86ISD::SUB;
17039 Cond = X86::COND_B;
17042 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17043 Cond = X86::COND_O;
17045 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17046 if (N->getValueType(0) == MVT::i8) {
17047 BaseOp = X86ISD::UMUL8;
17048 Cond = X86::COND_O;
17051 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17053 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17056 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17057 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17058 SDValue(Sum.getNode(), 2));
17060 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17064 // Also sets EFLAGS.
17065 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17066 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17069 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17070 DAG.getConstant(Cond, DL, MVT::i32),
17071 SDValue(Sum.getNode(), 1));
17073 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17076 /// Returns true if the operand type is exactly twice the native width, and
17077 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17078 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17079 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17080 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17081 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17084 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17085 else if (OpWidth == 128)
17086 return Subtarget->hasCmpxchg16b();
17091 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17092 return needsCmpXchgNb(SI->getValueOperand()->getType());
17095 // Note: this turns large loads into lock cmpxchg8b/16b.
17096 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17097 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17098 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17099 return needsCmpXchgNb(PTy->getElementType());
17102 TargetLoweringBase::AtomicRMWExpansionKind
17103 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17104 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17105 const Type *MemType = AI->getType();
17107 // If the operand is too big, we must see if cmpxchg8/16b is available
17108 // and default to library calls otherwise.
17109 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17110 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17111 : AtomicRMWExpansionKind::None;
17114 AtomicRMWInst::BinOp Op = AI->getOperation();
17117 llvm_unreachable("Unknown atomic operation");
17118 case AtomicRMWInst::Xchg:
17119 case AtomicRMWInst::Add:
17120 case AtomicRMWInst::Sub:
17121 // It's better to use xadd, xsub or xchg for these in all cases.
17122 return AtomicRMWExpansionKind::None;
17123 case AtomicRMWInst::Or:
17124 case AtomicRMWInst::And:
17125 case AtomicRMWInst::Xor:
17126 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17127 // prefix to a normal instruction for these operations.
17128 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17129 : AtomicRMWExpansionKind::None;
17130 case AtomicRMWInst::Nand:
17131 case AtomicRMWInst::Max:
17132 case AtomicRMWInst::Min:
17133 case AtomicRMWInst::UMax:
17134 case AtomicRMWInst::UMin:
17135 // These always require a non-trivial set of data operations on x86. We must
17136 // use a cmpxchg loop.
17137 return AtomicRMWExpansionKind::CmpXChg;
17141 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17142 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17143 // no-sse2). There isn't any reason to disable it if the target processor
17145 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17149 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17150 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17151 const Type *MemType = AI->getType();
17152 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17153 // there is no benefit in turning such RMWs into loads, and it is actually
17154 // harmful as it introduces a mfence.
17155 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17158 auto Builder = IRBuilder<>(AI);
17159 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17160 auto SynchScope = AI->getSynchScope();
17161 // We must restrict the ordering to avoid generating loads with Release or
17162 // ReleaseAcquire orderings.
17163 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17164 auto Ptr = AI->getPointerOperand();
17166 // Before the load we need a fence. Here is an example lifted from
17167 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17170 // x.store(1, relaxed);
17171 // r1 = y.fetch_add(0, release);
17173 // y.fetch_add(42, acquire);
17174 // r2 = x.load(relaxed);
17175 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17176 // lowered to just a load without a fence. A mfence flushes the store buffer,
17177 // making the optimization clearly correct.
17178 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17179 // otherwise, we might be able to be more agressive on relaxed idempotent
17180 // rmw. In practice, they do not look useful, so we don't try to be
17181 // especially clever.
17182 if (SynchScope == SingleThread)
17183 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17184 // the IR level, so we must wrap it in an intrinsic.
17187 if (!hasMFENCE(*Subtarget))
17188 // FIXME: it might make sense to use a locked operation here but on a
17189 // different cache-line to prevent cache-line bouncing. In practice it
17190 // is probably a small win, and x86 processors without mfence are rare
17191 // enough that we do not bother.
17195 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17196 Builder.CreateCall(MFence, {});
17198 // Finally we can emit the atomic load.
17199 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17200 AI->getType()->getPrimitiveSizeInBits());
17201 Loaded->setAtomic(Order, SynchScope);
17202 AI->replaceAllUsesWith(Loaded);
17203 AI->eraseFromParent();
17207 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17208 SelectionDAG &DAG) {
17210 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17211 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17212 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17213 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17215 // The only fence that needs an instruction is a sequentially-consistent
17216 // cross-thread fence.
17217 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17218 if (hasMFENCE(*Subtarget))
17219 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17221 SDValue Chain = Op.getOperand(0);
17222 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17224 DAG.getRegister(X86::ESP, MVT::i32), // Base
17225 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17226 DAG.getRegister(0, MVT::i32), // Index
17227 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17228 DAG.getRegister(0, MVT::i32), // Segment.
17232 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17233 return SDValue(Res, 0);
17236 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17237 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17240 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17241 SelectionDAG &DAG) {
17242 MVT T = Op.getSimpleValueType();
17246 switch(T.SimpleTy) {
17247 default: llvm_unreachable("Invalid value type!");
17248 case MVT::i8: Reg = X86::AL; size = 1; break;
17249 case MVT::i16: Reg = X86::AX; size = 2; break;
17250 case MVT::i32: Reg = X86::EAX; size = 4; break;
17252 assert(Subtarget->is64Bit() && "Node not type legal!");
17253 Reg = X86::RAX; size = 8;
17256 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17257 Op.getOperand(2), SDValue());
17258 SDValue Ops[] = { cpIn.getValue(0),
17261 DAG.getTargetConstant(size, DL, MVT::i8),
17262 cpIn.getValue(1) };
17263 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17264 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17265 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17269 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17270 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17271 MVT::i32, cpOut.getValue(2));
17272 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17273 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17276 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17277 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17278 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17282 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17283 SelectionDAG &DAG) {
17284 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17285 MVT DstVT = Op.getSimpleValueType();
17287 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17288 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17289 if (DstVT != MVT::f64)
17290 // This conversion needs to be expanded.
17293 SDValue InVec = Op->getOperand(0);
17295 unsigned NumElts = SrcVT.getVectorNumElements();
17296 EVT SVT = SrcVT.getVectorElementType();
17298 // Widen the vector in input in the case of MVT::v2i32.
17299 // Example: from MVT::v2i32 to MVT::v4i32.
17300 SmallVector<SDValue, 16> Elts;
17301 for (unsigned i = 0, e = NumElts; i != e; ++i)
17302 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17303 DAG.getIntPtrConstant(i, dl)));
17305 // Explicitly mark the extra elements as Undef.
17306 Elts.append(NumElts, DAG.getUNDEF(SVT));
17308 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17309 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17310 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17311 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17312 DAG.getIntPtrConstant(0, dl));
17315 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17316 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17317 assert((DstVT == MVT::i64 ||
17318 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17319 "Unexpected custom BITCAST");
17320 // i64 <=> MMX conversions are Legal.
17321 if (SrcVT==MVT::i64 && DstVT.isVector())
17323 if (DstVT==MVT::i64 && SrcVT.isVector())
17325 // MMX <=> MMX conversions are Legal.
17326 if (SrcVT.isVector() && DstVT.isVector())
17328 // All other conversions need to be expanded.
17332 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
17333 const X86Subtarget *Subtarget,
17334 SelectionDAG &DAG) {
17335 MVT VT = Op.getSimpleValueType();
17336 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17337 "CTPOP lowering only implemented for 128/256-bit wide vector types");
17339 int VecSize = VT.getSizeInBits();
17340 int NumElts = VT.getVectorNumElements();
17341 MVT EltVT = VT.getVectorElementType();
17342 int Len = EltVT.getSizeInBits();
17344 // This is the vectorized version of the "best" algorithm from
17345 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17346 // with a minor tweak to use a series of adds + shifts instead of vector
17347 // multiplications. Implemented for all integer vector types.
17349 // FIXME: Use strategies from http://wm.ite.pl/articles/sse-popcount.html
17351 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), DL,
17353 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), DL,
17355 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), DL,
17360 // v = v - ((v >> 1) & 0x55555555...)
17361 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, DL, EltVT));
17362 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ones);
17363 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, V, OnesV);
17365 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
17366 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Mask55);
17367 SDValue And = DAG.getNode(ISD::AND, DL, Srl.getValueType(), Srl, M55);
17369 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
17371 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17372 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
17373 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Mask33);
17374 SDValue AndLHS = DAG.getNode(ISD::AND, DL, M33.getValueType(), V, M33);
17376 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, DL, EltVT));
17377 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Twos);
17378 Srl = DAG.getNode(ISD::SRL, DL, VT, V, TwosV);
17379 SDValue AndRHS = DAG.getNode(ISD::AND, DL, M33.getValueType(), Srl, M33);
17381 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
17383 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17384 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, DL, EltVT));
17385 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Fours);
17386 Srl = DAG.getNode(ISD::SRL, DL, VT, V, FoursV);
17387 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
17389 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
17390 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Mask0F);
17392 V = DAG.getNode(ISD::AND, DL, M0F.getValueType(), Add, M0F);
17394 // At this point, V contains the byte-wise population count, and we are
17395 // merely doing a horizontal sum if necessary to get the wider element
17398 // FIXME: There is a different lowering strategy above for the horizontal sum
17399 // of byte-wise population counts. This one and that one should be merged,
17400 // using the fastest of the two for each size.
17401 MVT ByteVT = MVT::getVectorVT(MVT::i8, VecSize / 8);
17402 MVT ShiftVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
17403 V = DAG.getNode(ISD::BITCAST, DL, ByteVT, V);
17404 SmallVector<SDValue, 8> Csts;
17405 assert(Len <= 64 && "We don't support element sizes of more than 64 bits!");
17406 assert(isPowerOf2_32(Len) && "Only power of two element sizes supported!");
17407 for (int i = Len; i > 8; i /= 2) {
17408 Csts.assign(VecSize / 64, DAG.getConstant(i / 2, DL, MVT::i64));
17409 SDValue Shl = DAG.getNode(
17410 ISD::SHL, DL, ShiftVT, DAG.getNode(ISD::BITCAST, DL, ShiftVT, V),
17411 DAG.getNode(ISD::BUILD_VECTOR, DL, ShiftVT, Csts));
17412 V = DAG.getNode(ISD::ADD, DL, ByteVT, V,
17413 DAG.getNode(ISD::BITCAST, DL, ByteVT, Shl));
17416 // The high byte now contains the sum of the element bytes. Shift it right
17417 // (if needed) to make it the low byte.
17418 V = DAG.getNode(ISD::BITCAST, DL, VT, V);
17420 Csts.assign(NumElts, DAG.getConstant(Len - 8, DL, EltVT));
17421 V = DAG.getNode(ISD::SRL, DL, VT, V,
17422 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Csts));
17428 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17429 SelectionDAG &DAG) {
17430 MVT VT = Op.getSimpleValueType();
17431 // FIXME: Need to add AVX-512 support here!
17432 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17433 "Unknown CTPOP type to handle");
17434 SDLoc DL(Op.getNode());
17435 SDValue Op0 = Op.getOperand(0);
17437 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
17438 unsigned NumElems = VT.getVectorNumElements();
17440 // Extract each 128-bit vector, compute pop count and concat the result.
17441 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
17442 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
17444 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
17445 LowerVectorCTPOPBitmath(LHS, DL, Subtarget, DAG),
17446 LowerVectorCTPOPBitmath(RHS, DL, Subtarget, DAG));
17449 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
17452 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17453 SelectionDAG &DAG) {
17454 assert(Op.getValueType().isVector() &&
17455 "We only do custom lowering for vector population count.");
17456 return LowerVectorCTPOP(Op, Subtarget, DAG);
17459 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17460 SDNode *Node = Op.getNode();
17462 EVT T = Node->getValueType(0);
17463 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17464 DAG.getConstant(0, dl, T), Node->getOperand(2));
17465 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17466 cast<AtomicSDNode>(Node)->getMemoryVT(),
17467 Node->getOperand(0),
17468 Node->getOperand(1), negOp,
17469 cast<AtomicSDNode>(Node)->getMemOperand(),
17470 cast<AtomicSDNode>(Node)->getOrdering(),
17471 cast<AtomicSDNode>(Node)->getSynchScope());
17474 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17475 SDNode *Node = Op.getNode();
17477 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17479 // Convert seq_cst store -> xchg
17480 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17481 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17482 // (The only way to get a 16-byte store is cmpxchg16b)
17483 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17484 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17485 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17486 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17487 cast<AtomicSDNode>(Node)->getMemoryVT(),
17488 Node->getOperand(0),
17489 Node->getOperand(1), Node->getOperand(2),
17490 cast<AtomicSDNode>(Node)->getMemOperand(),
17491 cast<AtomicSDNode>(Node)->getOrdering(),
17492 cast<AtomicSDNode>(Node)->getSynchScope());
17493 return Swap.getValue(1);
17495 // Other atomic stores have a simple pattern.
17499 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17500 EVT VT = Op.getNode()->getSimpleValueType(0);
17502 // Let legalize expand this if it isn't a legal type yet.
17503 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17506 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17509 bool ExtraOp = false;
17510 switch (Op.getOpcode()) {
17511 default: llvm_unreachable("Invalid code");
17512 case ISD::ADDC: Opc = X86ISD::ADD; break;
17513 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17514 case ISD::SUBC: Opc = X86ISD::SUB; break;
17515 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17519 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17521 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17522 Op.getOperand(1), Op.getOperand(2));
17525 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17526 SelectionDAG &DAG) {
17527 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17529 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17530 // which returns the values as { float, float } (in XMM0) or
17531 // { double, double } (which is returned in XMM0, XMM1).
17533 SDValue Arg = Op.getOperand(0);
17534 EVT ArgVT = Arg.getValueType();
17535 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17537 TargetLowering::ArgListTy Args;
17538 TargetLowering::ArgListEntry Entry;
17542 Entry.isSExt = false;
17543 Entry.isZExt = false;
17544 Args.push_back(Entry);
17546 bool isF64 = ArgVT == MVT::f64;
17547 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17548 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17549 // the results are returned via SRet in memory.
17550 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17551 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17552 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17554 Type *RetTy = isF64
17555 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17556 : (Type*)VectorType::get(ArgTy, 4);
17558 TargetLowering::CallLoweringInfo CLI(DAG);
17559 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17560 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17562 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17565 // Returned in xmm0 and xmm1.
17566 return CallResult.first;
17568 // Returned in bits 0:31 and 32:64 xmm0.
17569 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17570 CallResult.first, DAG.getIntPtrConstant(0, dl));
17571 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17572 CallResult.first, DAG.getIntPtrConstant(1, dl));
17573 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17574 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17577 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17578 SelectionDAG &DAG) {
17579 assert(Subtarget->hasAVX512() &&
17580 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17582 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17583 EVT VT = N->getValue().getValueType();
17584 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17587 // X86 scatter kills mask register, so its type should be added to
17588 // the list of return values
17589 if (N->getNumValues() == 1) {
17590 SDValue Index = N->getIndex();
17591 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17592 !Index.getValueType().is512BitVector())
17593 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17595 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17596 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17597 N->getOperand(3), Index };
17599 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17600 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17601 return SDValue(NewScatter.getNode(), 0);
17606 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17607 SelectionDAG &DAG) {
17608 assert(Subtarget->hasAVX512() &&
17609 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17611 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17612 EVT VT = Op.getValueType();
17613 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17616 SDValue Index = N->getIndex();
17617 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17618 !Index.getValueType().is512BitVector()) {
17619 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17620 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17621 N->getOperand(3), Index };
17622 DAG.UpdateNodeOperands(N, Ops);
17627 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
17628 SelectionDAG &DAG) const {
17629 // TODO: Eventually, the lowering of these nodes should be informed by or
17630 // deferred to the GC strategy for the function in which they appear. For
17631 // now, however, they must be lowered to something. Since they are logically
17632 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17633 // require special handling for these nodes), lower them as literal NOOPs for
17635 SmallVector<SDValue, 2> Ops;
17637 Ops.push_back(Op.getOperand(0));
17638 if (Op->getGluedNode())
17639 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17642 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17643 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17648 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
17649 SelectionDAG &DAG) const {
17650 // TODO: Eventually, the lowering of these nodes should be informed by or
17651 // deferred to the GC strategy for the function in which they appear. For
17652 // now, however, they must be lowered to something. Since they are logically
17653 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17654 // require special handling for these nodes), lower them as literal NOOPs for
17656 SmallVector<SDValue, 2> Ops;
17658 Ops.push_back(Op.getOperand(0));
17659 if (Op->getGluedNode())
17660 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17663 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17664 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17669 /// LowerOperation - Provide custom lowering hooks for some operations.
17671 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17672 switch (Op.getOpcode()) {
17673 default: llvm_unreachable("Should not custom lower this!");
17674 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17675 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17676 return LowerCMP_SWAP(Op, Subtarget, DAG);
17677 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17678 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17679 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17680 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17681 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17682 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17683 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17684 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17685 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17686 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17687 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17688 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17689 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17690 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17691 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17692 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17693 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17694 case ISD::SHL_PARTS:
17695 case ISD::SRA_PARTS:
17696 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17697 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17698 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17699 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17700 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17701 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17702 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17703 case ISD::SIGN_EXTEND_VECTOR_INREG:
17704 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
17705 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17706 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17707 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17708 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17710 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17711 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17712 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17713 case ISD::SETCC: return LowerSETCC(Op, DAG);
17714 case ISD::SELECT: return LowerSELECT(Op, DAG);
17715 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17716 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17717 case ISD::VASTART: return LowerVASTART(Op, DAG);
17718 case ISD::VAARG: return LowerVAARG(Op, DAG);
17719 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17720 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17721 case ISD::INTRINSIC_VOID:
17722 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17723 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17724 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17725 case ISD::FRAME_TO_ARGS_OFFSET:
17726 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17727 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17728 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17729 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17730 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17731 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17732 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17733 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17734 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17735 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17736 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17737 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17738 case ISD::UMUL_LOHI:
17739 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17742 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17748 case ISD::UMULO: return LowerXALUO(Op, DAG);
17749 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17750 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17754 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17755 case ISD::ADD: return LowerADD(Op, DAG);
17756 case ISD::SUB: return LowerSUB(Op, DAG);
17757 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17758 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
17759 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
17760 case ISD::GC_TRANSITION_START:
17761 return LowerGC_TRANSITION_START(Op, DAG);
17762 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
17766 /// ReplaceNodeResults - Replace a node with an illegal result type
17767 /// with a new node built out of custom code.
17768 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17769 SmallVectorImpl<SDValue>&Results,
17770 SelectionDAG &DAG) const {
17772 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17773 switch (N->getOpcode()) {
17775 llvm_unreachable("Do not know how to custom type legalize this operation!");
17776 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17777 case X86ISD::FMINC:
17779 case X86ISD::FMAXC:
17780 case X86ISD::FMAX: {
17781 EVT VT = N->getValueType(0);
17782 if (VT != MVT::v2f32)
17783 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17784 SDValue UNDEF = DAG.getUNDEF(VT);
17785 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17786 N->getOperand(0), UNDEF);
17787 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17788 N->getOperand(1), UNDEF);
17789 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17792 case ISD::SIGN_EXTEND_INREG:
17797 // We don't want to expand or promote these.
17804 case ISD::UDIVREM: {
17805 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17806 Results.push_back(V);
17809 case ISD::FP_TO_SINT:
17810 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
17811 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
17812 if (N->getOperand(0).getValueType() == MVT::f16)
17815 case ISD::FP_TO_UINT: {
17816 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17818 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17821 std::pair<SDValue,SDValue> Vals =
17822 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17823 SDValue FIST = Vals.first, StackSlot = Vals.second;
17824 if (FIST.getNode()) {
17825 EVT VT = N->getValueType(0);
17826 // Return a load from the stack slot.
17827 if (StackSlot.getNode())
17828 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17829 MachinePointerInfo(),
17830 false, false, false, 0));
17832 Results.push_back(FIST);
17836 case ISD::UINT_TO_FP: {
17837 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17838 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17839 N->getValueType(0) != MVT::v2f32)
17841 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17843 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
17845 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17846 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17847 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17848 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17849 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17850 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17853 case ISD::FP_ROUND: {
17854 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17856 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17857 Results.push_back(V);
17860 case ISD::FP_EXTEND: {
17861 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
17862 // No other ValueType for FP_EXTEND should reach this point.
17863 assert(N->getValueType(0) == MVT::v2f32 &&
17864 "Do not know how to legalize this Node");
17867 case ISD::INTRINSIC_W_CHAIN: {
17868 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17870 default : llvm_unreachable("Do not know how to custom type "
17871 "legalize this intrinsic operation!");
17872 case Intrinsic::x86_rdtsc:
17873 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17875 case Intrinsic::x86_rdtscp:
17876 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17878 case Intrinsic::x86_rdpmc:
17879 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17882 case ISD::READCYCLECOUNTER: {
17883 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17886 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17887 EVT T = N->getValueType(0);
17888 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17889 bool Regs64bit = T == MVT::i128;
17890 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17891 SDValue cpInL, cpInH;
17892 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17893 DAG.getConstant(0, dl, HalfT));
17894 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17895 DAG.getConstant(1, dl, HalfT));
17896 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17897 Regs64bit ? X86::RAX : X86::EAX,
17899 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17900 Regs64bit ? X86::RDX : X86::EDX,
17901 cpInH, cpInL.getValue(1));
17902 SDValue swapInL, swapInH;
17903 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17904 DAG.getConstant(0, dl, HalfT));
17905 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17906 DAG.getConstant(1, dl, HalfT));
17907 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17908 Regs64bit ? X86::RBX : X86::EBX,
17909 swapInL, cpInH.getValue(1));
17910 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17911 Regs64bit ? X86::RCX : X86::ECX,
17912 swapInH, swapInL.getValue(1));
17913 SDValue Ops[] = { swapInH.getValue(0),
17915 swapInH.getValue(1) };
17916 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17917 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17918 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17919 X86ISD::LCMPXCHG8_DAG;
17920 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17921 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17922 Regs64bit ? X86::RAX : X86::EAX,
17923 HalfT, Result.getValue(1));
17924 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17925 Regs64bit ? X86::RDX : X86::EDX,
17926 HalfT, cpOutL.getValue(2));
17927 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17929 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17930 MVT::i32, cpOutH.getValue(2));
17932 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17933 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
17934 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17936 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17937 Results.push_back(Success);
17938 Results.push_back(EFLAGS.getValue(1));
17941 case ISD::ATOMIC_SWAP:
17942 case ISD::ATOMIC_LOAD_ADD:
17943 case ISD::ATOMIC_LOAD_SUB:
17944 case ISD::ATOMIC_LOAD_AND:
17945 case ISD::ATOMIC_LOAD_OR:
17946 case ISD::ATOMIC_LOAD_XOR:
17947 case ISD::ATOMIC_LOAD_NAND:
17948 case ISD::ATOMIC_LOAD_MIN:
17949 case ISD::ATOMIC_LOAD_MAX:
17950 case ISD::ATOMIC_LOAD_UMIN:
17951 case ISD::ATOMIC_LOAD_UMAX:
17952 case ISD::ATOMIC_LOAD: {
17953 // Delegate to generic TypeLegalization. Situations we can really handle
17954 // should have already been dealt with by AtomicExpandPass.cpp.
17957 case ISD::BITCAST: {
17958 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17959 EVT DstVT = N->getValueType(0);
17960 EVT SrcVT = N->getOperand(0)->getValueType(0);
17962 if (SrcVT != MVT::f64 ||
17963 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17966 unsigned NumElts = DstVT.getVectorNumElements();
17967 EVT SVT = DstVT.getVectorElementType();
17968 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17969 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17970 MVT::v2f64, N->getOperand(0));
17971 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17973 if (ExperimentalVectorWideningLegalization) {
17974 // If we are legalizing vectors by widening, we already have the desired
17975 // legal vector type, just return it.
17976 Results.push_back(ToVecInt);
17980 SmallVector<SDValue, 8> Elts;
17981 for (unsigned i = 0, e = NumElts; i != e; ++i)
17982 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17983 ToVecInt, DAG.getIntPtrConstant(i, dl)));
17985 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17990 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17991 switch ((X86ISD::NodeType)Opcode) {
17992 case X86ISD::FIRST_NUMBER: break;
17993 case X86ISD::BSF: return "X86ISD::BSF";
17994 case X86ISD::BSR: return "X86ISD::BSR";
17995 case X86ISD::SHLD: return "X86ISD::SHLD";
17996 case X86ISD::SHRD: return "X86ISD::SHRD";
17997 case X86ISD::FAND: return "X86ISD::FAND";
17998 case X86ISD::FANDN: return "X86ISD::FANDN";
17999 case X86ISD::FOR: return "X86ISD::FOR";
18000 case X86ISD::FXOR: return "X86ISD::FXOR";
18001 case X86ISD::FSRL: return "X86ISD::FSRL";
18002 case X86ISD::FILD: return "X86ISD::FILD";
18003 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18004 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18005 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18006 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18007 case X86ISD::FLD: return "X86ISD::FLD";
18008 case X86ISD::FST: return "X86ISD::FST";
18009 case X86ISD::CALL: return "X86ISD::CALL";
18010 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18011 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18012 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18013 case X86ISD::BT: return "X86ISD::BT";
18014 case X86ISD::CMP: return "X86ISD::CMP";
18015 case X86ISD::COMI: return "X86ISD::COMI";
18016 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18017 case X86ISD::CMPM: return "X86ISD::CMPM";
18018 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18019 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18020 case X86ISD::SETCC: return "X86ISD::SETCC";
18021 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18022 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18023 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18024 case X86ISD::CMOV: return "X86ISD::CMOV";
18025 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18026 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18027 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18028 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18029 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18030 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18031 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18032 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18033 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18034 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18035 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18036 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18037 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18038 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18039 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18040 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18041 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18042 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18043 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18044 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18045 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18046 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18047 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18048 case X86ISD::HADD: return "X86ISD::HADD";
18049 case X86ISD::HSUB: return "X86ISD::HSUB";
18050 case X86ISD::FHADD: return "X86ISD::FHADD";
18051 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18052 case X86ISD::UMAX: return "X86ISD::UMAX";
18053 case X86ISD::UMIN: return "X86ISD::UMIN";
18054 case X86ISD::SMAX: return "X86ISD::SMAX";
18055 case X86ISD::SMIN: return "X86ISD::SMIN";
18056 case X86ISD::FMAX: return "X86ISD::FMAX";
18057 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18058 case X86ISD::FMIN: return "X86ISD::FMIN";
18059 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18060 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18061 case X86ISD::FMINC: return "X86ISD::FMINC";
18062 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18063 case X86ISD::FRCP: return "X86ISD::FRCP";
18064 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18065 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18066 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18067 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18068 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18069 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18070 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18071 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18072 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18073 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18074 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18075 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18076 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18077 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18078 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18079 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18080 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18081 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18082 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18083 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18084 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18085 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18086 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18087 case X86ISD::VSHL: return "X86ISD::VSHL";
18088 case X86ISD::VSRL: return "X86ISD::VSRL";
18089 case X86ISD::VSRA: return "X86ISD::VSRA";
18090 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18091 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18092 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18093 case X86ISD::CMPP: return "X86ISD::CMPP";
18094 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18095 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18096 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18097 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18098 case X86ISD::ADD: return "X86ISD::ADD";
18099 case X86ISD::SUB: return "X86ISD::SUB";
18100 case X86ISD::ADC: return "X86ISD::ADC";
18101 case X86ISD::SBB: return "X86ISD::SBB";
18102 case X86ISD::SMUL: return "X86ISD::SMUL";
18103 case X86ISD::UMUL: return "X86ISD::UMUL";
18104 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18105 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18106 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18107 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18108 case X86ISD::INC: return "X86ISD::INC";
18109 case X86ISD::DEC: return "X86ISD::DEC";
18110 case X86ISD::OR: return "X86ISD::OR";
18111 case X86ISD::XOR: return "X86ISD::XOR";
18112 case X86ISD::AND: return "X86ISD::AND";
18113 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18114 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18115 case X86ISD::PTEST: return "X86ISD::PTEST";
18116 case X86ISD::TESTP: return "X86ISD::TESTP";
18117 case X86ISD::TESTM: return "X86ISD::TESTM";
18118 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18119 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18120 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18121 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18122 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18123 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18124 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18125 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18126 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18127 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18128 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18129 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18130 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18131 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18132 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18133 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18134 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18135 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18136 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18137 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18138 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18139 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18140 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18141 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18142 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18143 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18144 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18145 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18146 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18147 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18148 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18149 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18150 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18151 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18152 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18153 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18154 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18155 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18156 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18157 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18158 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18159 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18160 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18161 case X86ISD::SAHF: return "X86ISD::SAHF";
18162 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18163 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18164 case X86ISD::FMADD: return "X86ISD::FMADD";
18165 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18166 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18167 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18168 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18169 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18170 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18171 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18172 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18173 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18174 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18175 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18176 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18177 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18178 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18179 case X86ISD::XTEST: return "X86ISD::XTEST";
18180 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18181 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18182 case X86ISD::SELECT: return "X86ISD::SELECT";
18183 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18184 case X86ISD::RCP28: return "X86ISD::RCP28";
18185 case X86ISD::EXP2: return "X86ISD::EXP2";
18186 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18187 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18188 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18189 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18190 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18191 case X86ISD::ADDS: return "X86ISD::ADDS";
18192 case X86ISD::SUBS: return "X86ISD::SUBS";
18197 // isLegalAddressingMode - Return true if the addressing mode represented
18198 // by AM is legal for this target, for a load/store of the specified type.
18199 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18201 // X86 supports extremely general addressing modes.
18202 CodeModel::Model M = getTargetMachine().getCodeModel();
18203 Reloc::Model R = getTargetMachine().getRelocationModel();
18205 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18206 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18211 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18213 // If a reference to this global requires an extra load, we can't fold it.
18214 if (isGlobalStubReference(GVFlags))
18217 // If BaseGV requires a register for the PIC base, we cannot also have a
18218 // BaseReg specified.
18219 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18222 // If lower 4G is not available, then we must use rip-relative addressing.
18223 if ((M != CodeModel::Small || R != Reloc::Static) &&
18224 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18228 switch (AM.Scale) {
18234 // These scales always work.
18239 // These scales are formed with basereg+scalereg. Only accept if there is
18244 default: // Other stuff never works.
18251 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18252 unsigned Bits = Ty->getScalarSizeInBits();
18254 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18255 // particularly cheaper than those without.
18259 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18260 // variable shifts just as cheap as scalar ones.
18261 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18264 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18265 // fully general vector.
18269 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18270 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18272 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18273 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18274 return NumBits1 > NumBits2;
18277 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18278 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18281 if (!isTypeLegal(EVT::getEVT(Ty1)))
18284 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18286 // Assuming the caller doesn't have a zeroext or signext return parameter,
18287 // truncation all the way down to i1 is valid.
18291 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18292 return isInt<32>(Imm);
18295 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18296 // Can also use sub to handle negated immediates.
18297 return isInt<32>(Imm);
18300 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18301 if (!VT1.isInteger() || !VT2.isInteger())
18303 unsigned NumBits1 = VT1.getSizeInBits();
18304 unsigned NumBits2 = VT2.getSizeInBits();
18305 return NumBits1 > NumBits2;
18308 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18309 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18310 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18313 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18314 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18315 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18318 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18319 EVT VT1 = Val.getValueType();
18320 if (isZExtFree(VT1, VT2))
18323 if (Val.getOpcode() != ISD::LOAD)
18326 if (!VT1.isSimple() || !VT1.isInteger() ||
18327 !VT2.isSimple() || !VT2.isInteger())
18330 switch (VT1.getSimpleVT().SimpleTy) {
18335 // X86 has 8, 16, and 32-bit zero-extending loads.
18342 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18345 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18346 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18349 VT = VT.getScalarType();
18351 if (!VT.isSimple())
18354 switch (VT.getSimpleVT().SimpleTy) {
18365 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18366 // i16 instructions are longer (0x66 prefix) and potentially slower.
18367 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18370 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18371 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18372 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18373 /// are assumed to be legal.
18375 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18377 if (!VT.isSimple())
18380 // Not for i1 vectors
18381 if (VT.getScalarType() == MVT::i1)
18384 // Very little shuffling can be done for 64-bit vectors right now.
18385 if (VT.getSizeInBits() == 64)
18388 // We only care that the types being shuffled are legal. The lowering can
18389 // handle any possible shuffle mask that results.
18390 return isTypeLegal(VT.getSimpleVT());
18394 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18396 // Just delegate to the generic legality, clear masks aren't special.
18397 return isShuffleMaskLegal(Mask, VT);
18400 //===----------------------------------------------------------------------===//
18401 // X86 Scheduler Hooks
18402 //===----------------------------------------------------------------------===//
18404 /// Utility function to emit xbegin specifying the start of an RTM region.
18405 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18406 const TargetInstrInfo *TII) {
18407 DebugLoc DL = MI->getDebugLoc();
18409 const BasicBlock *BB = MBB->getBasicBlock();
18410 MachineFunction::iterator I = MBB;
18413 // For the v = xbegin(), we generate
18424 MachineBasicBlock *thisMBB = MBB;
18425 MachineFunction *MF = MBB->getParent();
18426 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18427 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18428 MF->insert(I, mainMBB);
18429 MF->insert(I, sinkMBB);
18431 // Transfer the remainder of BB and its successor edges to sinkMBB.
18432 sinkMBB->splice(sinkMBB->begin(), MBB,
18433 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18434 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18438 // # fallthrough to mainMBB
18439 // # abortion to sinkMBB
18440 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18441 thisMBB->addSuccessor(mainMBB);
18442 thisMBB->addSuccessor(sinkMBB);
18446 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18447 mainMBB->addSuccessor(sinkMBB);
18450 // EAX is live into the sinkMBB
18451 sinkMBB->addLiveIn(X86::EAX);
18452 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18453 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18456 MI->eraseFromParent();
18460 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18461 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18462 // in the .td file.
18463 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18464 const TargetInstrInfo *TII) {
18466 switch (MI->getOpcode()) {
18467 default: llvm_unreachable("illegal opcode!");
18468 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18469 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18470 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18471 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18472 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18473 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18474 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18475 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18478 DebugLoc dl = MI->getDebugLoc();
18479 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18481 unsigned NumArgs = MI->getNumOperands();
18482 for (unsigned i = 1; i < NumArgs; ++i) {
18483 MachineOperand &Op = MI->getOperand(i);
18484 if (!(Op.isReg() && Op.isImplicit()))
18485 MIB.addOperand(Op);
18487 if (MI->hasOneMemOperand())
18488 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18490 BuildMI(*BB, MI, dl,
18491 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18492 .addReg(X86::XMM0);
18494 MI->eraseFromParent();
18498 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18499 // defs in an instruction pattern
18500 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18501 const TargetInstrInfo *TII) {
18503 switch (MI->getOpcode()) {
18504 default: llvm_unreachable("illegal opcode!");
18505 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18506 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18507 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18508 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18509 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18510 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18511 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18512 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18515 DebugLoc dl = MI->getDebugLoc();
18516 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18518 unsigned NumArgs = MI->getNumOperands(); // remove the results
18519 for (unsigned i = 1; i < NumArgs; ++i) {
18520 MachineOperand &Op = MI->getOperand(i);
18521 if (!(Op.isReg() && Op.isImplicit()))
18522 MIB.addOperand(Op);
18524 if (MI->hasOneMemOperand())
18525 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18527 BuildMI(*BB, MI, dl,
18528 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18531 MI->eraseFromParent();
18535 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18536 const X86Subtarget *Subtarget) {
18537 DebugLoc dl = MI->getDebugLoc();
18538 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18539 // Address into RAX/EAX, other two args into ECX, EDX.
18540 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18541 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18542 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18543 for (int i = 0; i < X86::AddrNumOperands; ++i)
18544 MIB.addOperand(MI->getOperand(i));
18546 unsigned ValOps = X86::AddrNumOperands;
18547 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18548 .addReg(MI->getOperand(ValOps).getReg());
18549 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18550 .addReg(MI->getOperand(ValOps+1).getReg());
18552 // The instruction doesn't actually take any operands though.
18553 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18555 MI->eraseFromParent(); // The pseudo is gone now.
18559 MachineBasicBlock *
18560 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18561 MachineBasicBlock *MBB) const {
18562 // Emit va_arg instruction on X86-64.
18564 // Operands to this pseudo-instruction:
18565 // 0 ) Output : destination address (reg)
18566 // 1-5) Input : va_list address (addr, i64mem)
18567 // 6 ) ArgSize : Size (in bytes) of vararg type
18568 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18569 // 8 ) Align : Alignment of type
18570 // 9 ) EFLAGS (implicit-def)
18572 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18573 static_assert(X86::AddrNumOperands == 5,
18574 "VAARG_64 assumes 5 address operands");
18576 unsigned DestReg = MI->getOperand(0).getReg();
18577 MachineOperand &Base = MI->getOperand(1);
18578 MachineOperand &Scale = MI->getOperand(2);
18579 MachineOperand &Index = MI->getOperand(3);
18580 MachineOperand &Disp = MI->getOperand(4);
18581 MachineOperand &Segment = MI->getOperand(5);
18582 unsigned ArgSize = MI->getOperand(6).getImm();
18583 unsigned ArgMode = MI->getOperand(7).getImm();
18584 unsigned Align = MI->getOperand(8).getImm();
18586 // Memory Reference
18587 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18588 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18589 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18591 // Machine Information
18592 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18593 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18594 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18595 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18596 DebugLoc DL = MI->getDebugLoc();
18598 // struct va_list {
18601 // i64 overflow_area (address)
18602 // i64 reg_save_area (address)
18604 // sizeof(va_list) = 24
18605 // alignment(va_list) = 8
18607 unsigned TotalNumIntRegs = 6;
18608 unsigned TotalNumXMMRegs = 8;
18609 bool UseGPOffset = (ArgMode == 1);
18610 bool UseFPOffset = (ArgMode == 2);
18611 unsigned MaxOffset = TotalNumIntRegs * 8 +
18612 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18614 /* Align ArgSize to a multiple of 8 */
18615 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18616 bool NeedsAlign = (Align > 8);
18618 MachineBasicBlock *thisMBB = MBB;
18619 MachineBasicBlock *overflowMBB;
18620 MachineBasicBlock *offsetMBB;
18621 MachineBasicBlock *endMBB;
18623 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18624 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18625 unsigned OffsetReg = 0;
18627 if (!UseGPOffset && !UseFPOffset) {
18628 // If we only pull from the overflow region, we don't create a branch.
18629 // We don't need to alter control flow.
18630 OffsetDestReg = 0; // unused
18631 OverflowDestReg = DestReg;
18633 offsetMBB = nullptr;
18634 overflowMBB = thisMBB;
18637 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18638 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18639 // If not, pull from overflow_area. (branch to overflowMBB)
18644 // offsetMBB overflowMBB
18649 // Registers for the PHI in endMBB
18650 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18651 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18653 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18654 MachineFunction *MF = MBB->getParent();
18655 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18656 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18657 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18659 MachineFunction::iterator MBBIter = MBB;
18662 // Insert the new basic blocks
18663 MF->insert(MBBIter, offsetMBB);
18664 MF->insert(MBBIter, overflowMBB);
18665 MF->insert(MBBIter, endMBB);
18667 // Transfer the remainder of MBB and its successor edges to endMBB.
18668 endMBB->splice(endMBB->begin(), thisMBB,
18669 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18670 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18672 // Make offsetMBB and overflowMBB successors of thisMBB
18673 thisMBB->addSuccessor(offsetMBB);
18674 thisMBB->addSuccessor(overflowMBB);
18676 // endMBB is a successor of both offsetMBB and overflowMBB
18677 offsetMBB->addSuccessor(endMBB);
18678 overflowMBB->addSuccessor(endMBB);
18680 // Load the offset value into a register
18681 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18682 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18686 .addDisp(Disp, UseFPOffset ? 4 : 0)
18687 .addOperand(Segment)
18688 .setMemRefs(MMOBegin, MMOEnd);
18690 // Check if there is enough room left to pull this argument.
18691 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18693 .addImm(MaxOffset + 8 - ArgSizeA8);
18695 // Branch to "overflowMBB" if offset >= max
18696 // Fall through to "offsetMBB" otherwise
18697 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18698 .addMBB(overflowMBB);
18701 // In offsetMBB, emit code to use the reg_save_area.
18703 assert(OffsetReg != 0);
18705 // Read the reg_save_area address.
18706 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18707 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18712 .addOperand(Segment)
18713 .setMemRefs(MMOBegin, MMOEnd);
18715 // Zero-extend the offset
18716 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18717 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18720 .addImm(X86::sub_32bit);
18722 // Add the offset to the reg_save_area to get the final address.
18723 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18724 .addReg(OffsetReg64)
18725 .addReg(RegSaveReg);
18727 // Compute the offset for the next argument
18728 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18729 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18731 .addImm(UseFPOffset ? 16 : 8);
18733 // Store it back into the va_list.
18734 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18738 .addDisp(Disp, UseFPOffset ? 4 : 0)
18739 .addOperand(Segment)
18740 .addReg(NextOffsetReg)
18741 .setMemRefs(MMOBegin, MMOEnd);
18744 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18749 // Emit code to use overflow area
18752 // Load the overflow_area address into a register.
18753 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18754 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18759 .addOperand(Segment)
18760 .setMemRefs(MMOBegin, MMOEnd);
18762 // If we need to align it, do so. Otherwise, just copy the address
18763 // to OverflowDestReg.
18765 // Align the overflow address
18766 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18767 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18769 // aligned_addr = (addr + (align-1)) & ~(align-1)
18770 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18771 .addReg(OverflowAddrReg)
18774 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18776 .addImm(~(uint64_t)(Align-1));
18778 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18779 .addReg(OverflowAddrReg);
18782 // Compute the next overflow address after this argument.
18783 // (the overflow address should be kept 8-byte aligned)
18784 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18785 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18786 .addReg(OverflowDestReg)
18787 .addImm(ArgSizeA8);
18789 // Store the new overflow address.
18790 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18795 .addOperand(Segment)
18796 .addReg(NextAddrReg)
18797 .setMemRefs(MMOBegin, MMOEnd);
18799 // If we branched, emit the PHI to the front of endMBB.
18801 BuildMI(*endMBB, endMBB->begin(), DL,
18802 TII->get(X86::PHI), DestReg)
18803 .addReg(OffsetDestReg).addMBB(offsetMBB)
18804 .addReg(OverflowDestReg).addMBB(overflowMBB);
18807 // Erase the pseudo instruction
18808 MI->eraseFromParent();
18813 MachineBasicBlock *
18814 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18816 MachineBasicBlock *MBB) const {
18817 // Emit code to save XMM registers to the stack. The ABI says that the
18818 // number of registers to save is given in %al, so it's theoretically
18819 // possible to do an indirect jump trick to avoid saving all of them,
18820 // however this code takes a simpler approach and just executes all
18821 // of the stores if %al is non-zero. It's less code, and it's probably
18822 // easier on the hardware branch predictor, and stores aren't all that
18823 // expensive anyway.
18825 // Create the new basic blocks. One block contains all the XMM stores,
18826 // and one block is the final destination regardless of whether any
18827 // stores were performed.
18828 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18829 MachineFunction *F = MBB->getParent();
18830 MachineFunction::iterator MBBIter = MBB;
18832 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18833 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18834 F->insert(MBBIter, XMMSaveMBB);
18835 F->insert(MBBIter, EndMBB);
18837 // Transfer the remainder of MBB and its successor edges to EndMBB.
18838 EndMBB->splice(EndMBB->begin(), MBB,
18839 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18840 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18842 // The original block will now fall through to the XMM save block.
18843 MBB->addSuccessor(XMMSaveMBB);
18844 // The XMMSaveMBB will fall through to the end block.
18845 XMMSaveMBB->addSuccessor(EndMBB);
18847 // Now add the instructions.
18848 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18849 DebugLoc DL = MI->getDebugLoc();
18851 unsigned CountReg = MI->getOperand(0).getReg();
18852 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18853 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18855 if (!Subtarget->isTargetWin64()) {
18856 // If %al is 0, branch around the XMM save block.
18857 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18858 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18859 MBB->addSuccessor(EndMBB);
18862 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18863 // that was just emitted, but clearly shouldn't be "saved".
18864 assert((MI->getNumOperands() <= 3 ||
18865 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18866 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18867 && "Expected last argument to be EFLAGS");
18868 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18869 // In the XMM save block, save all the XMM argument registers.
18870 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18871 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18872 MachineMemOperand *MMO =
18873 F->getMachineMemOperand(
18874 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18875 MachineMemOperand::MOStore,
18876 /*Size=*/16, /*Align=*/16);
18877 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18878 .addFrameIndex(RegSaveFrameIndex)
18879 .addImm(/*Scale=*/1)
18880 .addReg(/*IndexReg=*/0)
18881 .addImm(/*Disp=*/Offset)
18882 .addReg(/*Segment=*/0)
18883 .addReg(MI->getOperand(i).getReg())
18884 .addMemOperand(MMO);
18887 MI->eraseFromParent(); // The pseudo instruction is gone now.
18892 // The EFLAGS operand of SelectItr might be missing a kill marker
18893 // because there were multiple uses of EFLAGS, and ISel didn't know
18894 // which to mark. Figure out whether SelectItr should have had a
18895 // kill marker, and set it if it should. Returns the correct kill
18897 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18898 MachineBasicBlock* BB,
18899 const TargetRegisterInfo* TRI) {
18900 // Scan forward through BB for a use/def of EFLAGS.
18901 MachineBasicBlock::iterator miI(std::next(SelectItr));
18902 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18903 const MachineInstr& mi = *miI;
18904 if (mi.readsRegister(X86::EFLAGS))
18906 if (mi.definesRegister(X86::EFLAGS))
18907 break; // Should have kill-flag - update below.
18910 // If we hit the end of the block, check whether EFLAGS is live into a
18912 if (miI == BB->end()) {
18913 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18914 sEnd = BB->succ_end();
18915 sItr != sEnd; ++sItr) {
18916 MachineBasicBlock* succ = *sItr;
18917 if (succ->isLiveIn(X86::EFLAGS))
18922 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18923 // out. SelectMI should have a kill flag on EFLAGS.
18924 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18928 MachineBasicBlock *
18929 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18930 MachineBasicBlock *BB) const {
18931 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18932 DebugLoc DL = MI->getDebugLoc();
18934 // To "insert" a SELECT_CC instruction, we actually have to insert the
18935 // diamond control-flow pattern. The incoming instruction knows the
18936 // destination vreg to set, the condition code register to branch on, the
18937 // true/false values to select between, and a branch opcode to use.
18938 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18939 MachineFunction::iterator It = BB;
18945 // cmpTY ccX, r1, r2
18947 // fallthrough --> copy0MBB
18948 MachineBasicBlock *thisMBB = BB;
18949 MachineFunction *F = BB->getParent();
18951 // We also lower double CMOVs:
18952 // (CMOV (CMOV F, T, cc1), T, cc2)
18953 // to two successives branches. For that, we look for another CMOV as the
18954 // following instruction.
18956 // Without this, we would add a PHI between the two jumps, which ends up
18957 // creating a few copies all around. For instance, for
18959 // (sitofp (zext (fcmp une)))
18961 // we would generate:
18963 // ucomiss %xmm1, %xmm0
18964 // movss <1.0f>, %xmm0
18965 // movaps %xmm0, %xmm1
18967 // xorps %xmm1, %xmm1
18970 // movaps %xmm1, %xmm0
18974 // because this custom-inserter would have generated:
18986 // A: X = ...; Y = ...
18988 // C: Z = PHI [X, A], [Y, B]
18990 // E: PHI [X, C], [Z, D]
18992 // If we lower both CMOVs in a single step, we can instead generate:
19004 // A: X = ...; Y = ...
19006 // E: PHI [X, A], [X, C], [Y, D]
19008 // Which, in our sitofp/fcmp example, gives us something like:
19010 // ucomiss %xmm1, %xmm0
19011 // movss <1.0f>, %xmm0
19014 // xorps %xmm0, %xmm0
19018 MachineInstr *NextCMOV = nullptr;
19019 MachineBasicBlock::iterator NextMIIt =
19020 std::next(MachineBasicBlock::iterator(MI));
19021 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19022 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19023 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19024 NextCMOV = &*NextMIIt;
19026 MachineBasicBlock *jcc1MBB = nullptr;
19028 // If we have a double CMOV, we lower it to two successive branches to
19029 // the same block. EFLAGS is used by both, so mark it as live in the second.
19031 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19032 F->insert(It, jcc1MBB);
19033 jcc1MBB->addLiveIn(X86::EFLAGS);
19036 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19037 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19038 F->insert(It, copy0MBB);
19039 F->insert(It, sinkMBB);
19041 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19042 // live into the sink and copy blocks.
19043 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19045 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19046 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19047 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19048 copy0MBB->addLiveIn(X86::EFLAGS);
19049 sinkMBB->addLiveIn(X86::EFLAGS);
19052 // Transfer the remainder of BB and its successor edges to sinkMBB.
19053 sinkMBB->splice(sinkMBB->begin(), BB,
19054 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19055 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19057 // Add the true and fallthrough blocks as its successors.
19059 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19060 BB->addSuccessor(jcc1MBB);
19062 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19063 // jump to the sinkMBB.
19064 jcc1MBB->addSuccessor(copy0MBB);
19065 jcc1MBB->addSuccessor(sinkMBB);
19067 BB->addSuccessor(copy0MBB);
19070 // The true block target of the first (or only) branch is always sinkMBB.
19071 BB->addSuccessor(sinkMBB);
19073 // Create the conditional branch instruction.
19075 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19076 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19079 unsigned Opc2 = X86::GetCondBranchFromCond(
19080 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19081 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19085 // %FalseValue = ...
19086 // # fallthrough to sinkMBB
19087 copy0MBB->addSuccessor(sinkMBB);
19090 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19092 MachineInstrBuilder MIB =
19093 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19094 MI->getOperand(0).getReg())
19095 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19096 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19098 // If we have a double CMOV, the second Jcc provides the same incoming
19099 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19101 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19102 // Copy the PHI result to the register defined by the second CMOV.
19103 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19104 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19105 .addReg(MI->getOperand(0).getReg());
19106 NextCMOV->eraseFromParent();
19109 MI->eraseFromParent(); // The pseudo instruction is gone now.
19113 MachineBasicBlock *
19114 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19115 MachineBasicBlock *BB) const {
19116 MachineFunction *MF = BB->getParent();
19117 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19118 DebugLoc DL = MI->getDebugLoc();
19119 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19121 assert(MF->shouldSplitStack());
19123 const bool Is64Bit = Subtarget->is64Bit();
19124 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19126 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19127 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19130 // ... [Till the alloca]
19131 // If stacklet is not large enough, jump to mallocMBB
19134 // Allocate by subtracting from RSP
19135 // Jump to continueMBB
19138 // Allocate by call to runtime
19142 // [rest of original BB]
19145 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19146 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19147 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19149 MachineRegisterInfo &MRI = MF->getRegInfo();
19150 const TargetRegisterClass *AddrRegClass =
19151 getRegClassFor(getPointerTy());
19153 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19154 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19155 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19156 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19157 sizeVReg = MI->getOperand(1).getReg(),
19158 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19160 MachineFunction::iterator MBBIter = BB;
19163 MF->insert(MBBIter, bumpMBB);
19164 MF->insert(MBBIter, mallocMBB);
19165 MF->insert(MBBIter, continueMBB);
19167 continueMBB->splice(continueMBB->begin(), BB,
19168 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19169 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19171 // Add code to the main basic block to check if the stack limit has been hit,
19172 // and if so, jump to mallocMBB otherwise to bumpMBB.
19173 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19174 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19175 .addReg(tmpSPVReg).addReg(sizeVReg);
19176 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19177 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19178 .addReg(SPLimitVReg);
19179 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19181 // bumpMBB simply decreases the stack pointer, since we know the current
19182 // stacklet has enough space.
19183 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19184 .addReg(SPLimitVReg);
19185 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19186 .addReg(SPLimitVReg);
19187 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19189 // Calls into a routine in libgcc to allocate more space from the heap.
19190 const uint32_t *RegMask =
19191 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19193 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19195 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19196 .addExternalSymbol("__morestack_allocate_stack_space")
19197 .addRegMask(RegMask)
19198 .addReg(X86::RDI, RegState::Implicit)
19199 .addReg(X86::RAX, RegState::ImplicitDefine);
19200 } else if (Is64Bit) {
19201 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19203 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19204 .addExternalSymbol("__morestack_allocate_stack_space")
19205 .addRegMask(RegMask)
19206 .addReg(X86::EDI, RegState::Implicit)
19207 .addReg(X86::EAX, RegState::ImplicitDefine);
19209 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19211 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19212 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19213 .addExternalSymbol("__morestack_allocate_stack_space")
19214 .addRegMask(RegMask)
19215 .addReg(X86::EAX, RegState::ImplicitDefine);
19219 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19222 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19223 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19224 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19226 // Set up the CFG correctly.
19227 BB->addSuccessor(bumpMBB);
19228 BB->addSuccessor(mallocMBB);
19229 mallocMBB->addSuccessor(continueMBB);
19230 bumpMBB->addSuccessor(continueMBB);
19232 // Take care of the PHI nodes.
19233 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19234 MI->getOperand(0).getReg())
19235 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19236 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19238 // Delete the original pseudo instruction.
19239 MI->eraseFromParent();
19242 return continueMBB;
19245 MachineBasicBlock *
19246 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19247 MachineBasicBlock *BB) const {
19248 DebugLoc DL = MI->getDebugLoc();
19250 assert(!Subtarget->isTargetMachO());
19252 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19254 MI->eraseFromParent(); // The pseudo instruction is gone now.
19258 MachineBasicBlock *
19259 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19260 MachineBasicBlock *BB) const {
19261 // This is pretty easy. We're taking the value that we received from
19262 // our load from the relocation, sticking it in either RDI (x86-64)
19263 // or EAX and doing an indirect call. The return value will then
19264 // be in the normal return register.
19265 MachineFunction *F = BB->getParent();
19266 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19267 DebugLoc DL = MI->getDebugLoc();
19269 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19270 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19272 // Get a register mask for the lowered call.
19273 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19274 // proper register mask.
19275 const uint32_t *RegMask =
19276 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19277 if (Subtarget->is64Bit()) {
19278 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19279 TII->get(X86::MOV64rm), X86::RDI)
19281 .addImm(0).addReg(0)
19282 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19283 MI->getOperand(3).getTargetFlags())
19285 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19286 addDirectMem(MIB, X86::RDI);
19287 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19288 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19289 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19290 TII->get(X86::MOV32rm), X86::EAX)
19292 .addImm(0).addReg(0)
19293 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19294 MI->getOperand(3).getTargetFlags())
19296 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19297 addDirectMem(MIB, X86::EAX);
19298 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19300 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19301 TII->get(X86::MOV32rm), X86::EAX)
19302 .addReg(TII->getGlobalBaseReg(F))
19303 .addImm(0).addReg(0)
19304 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19305 MI->getOperand(3).getTargetFlags())
19307 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19308 addDirectMem(MIB, X86::EAX);
19309 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19312 MI->eraseFromParent(); // The pseudo instruction is gone now.
19316 MachineBasicBlock *
19317 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19318 MachineBasicBlock *MBB) const {
19319 DebugLoc DL = MI->getDebugLoc();
19320 MachineFunction *MF = MBB->getParent();
19321 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19322 MachineRegisterInfo &MRI = MF->getRegInfo();
19324 const BasicBlock *BB = MBB->getBasicBlock();
19325 MachineFunction::iterator I = MBB;
19328 // Memory Reference
19329 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19330 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19333 unsigned MemOpndSlot = 0;
19335 unsigned CurOp = 0;
19337 DstReg = MI->getOperand(CurOp++).getReg();
19338 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19339 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19340 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19341 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19343 MemOpndSlot = CurOp;
19345 MVT PVT = getPointerTy();
19346 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19347 "Invalid Pointer Size!");
19349 // For v = setjmp(buf), we generate
19352 // buf[LabelOffset] = restoreMBB
19353 // SjLjSetup restoreMBB
19359 // v = phi(main, restore)
19362 // if base pointer being used, load it from frame
19365 MachineBasicBlock *thisMBB = MBB;
19366 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19367 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19368 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19369 MF->insert(I, mainMBB);
19370 MF->insert(I, sinkMBB);
19371 MF->push_back(restoreMBB);
19373 MachineInstrBuilder MIB;
19375 // Transfer the remainder of BB and its successor edges to sinkMBB.
19376 sinkMBB->splice(sinkMBB->begin(), MBB,
19377 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19378 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19381 unsigned PtrStoreOpc = 0;
19382 unsigned LabelReg = 0;
19383 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19384 Reloc::Model RM = MF->getTarget().getRelocationModel();
19385 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19386 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19388 // Prepare IP either in reg or imm.
19389 if (!UseImmLabel) {
19390 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19391 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19392 LabelReg = MRI.createVirtualRegister(PtrRC);
19393 if (Subtarget->is64Bit()) {
19394 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19398 .addMBB(restoreMBB)
19401 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19402 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19403 .addReg(XII->getGlobalBaseReg(MF))
19406 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19410 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19412 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19413 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19414 if (i == X86::AddrDisp)
19415 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19417 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19420 MIB.addReg(LabelReg);
19422 MIB.addMBB(restoreMBB);
19423 MIB.setMemRefs(MMOBegin, MMOEnd);
19425 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19426 .addMBB(restoreMBB);
19428 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19429 MIB.addRegMask(RegInfo->getNoPreservedMask());
19430 thisMBB->addSuccessor(mainMBB);
19431 thisMBB->addSuccessor(restoreMBB);
19435 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19436 mainMBB->addSuccessor(sinkMBB);
19439 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19440 TII->get(X86::PHI), DstReg)
19441 .addReg(mainDstReg).addMBB(mainMBB)
19442 .addReg(restoreDstReg).addMBB(restoreMBB);
19445 if (RegInfo->hasBasePointer(*MF)) {
19446 const bool Uses64BitFramePtr =
19447 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19448 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19449 X86FI->setRestoreBasePointer(MF);
19450 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19451 unsigned BasePtr = RegInfo->getBaseRegister();
19452 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19453 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19454 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19455 .setMIFlag(MachineInstr::FrameSetup);
19457 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19458 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19459 restoreMBB->addSuccessor(sinkMBB);
19461 MI->eraseFromParent();
19465 MachineBasicBlock *
19466 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19467 MachineBasicBlock *MBB) const {
19468 DebugLoc DL = MI->getDebugLoc();
19469 MachineFunction *MF = MBB->getParent();
19470 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19471 MachineRegisterInfo &MRI = MF->getRegInfo();
19473 // Memory Reference
19474 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19475 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19477 MVT PVT = getPointerTy();
19478 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19479 "Invalid Pointer Size!");
19481 const TargetRegisterClass *RC =
19482 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19483 unsigned Tmp = MRI.createVirtualRegister(RC);
19484 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19485 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19486 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19487 unsigned SP = RegInfo->getStackRegister();
19489 MachineInstrBuilder MIB;
19491 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19492 const int64_t SPOffset = 2 * PVT.getStoreSize();
19494 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19495 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19498 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19499 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19500 MIB.addOperand(MI->getOperand(i));
19501 MIB.setMemRefs(MMOBegin, MMOEnd);
19503 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19504 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19505 if (i == X86::AddrDisp)
19506 MIB.addDisp(MI->getOperand(i), LabelOffset);
19508 MIB.addOperand(MI->getOperand(i));
19510 MIB.setMemRefs(MMOBegin, MMOEnd);
19512 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19513 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19514 if (i == X86::AddrDisp)
19515 MIB.addDisp(MI->getOperand(i), SPOffset);
19517 MIB.addOperand(MI->getOperand(i));
19519 MIB.setMemRefs(MMOBegin, MMOEnd);
19521 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19523 MI->eraseFromParent();
19527 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19528 // accumulator loops. Writing back to the accumulator allows the coalescer
19529 // to remove extra copies in the loop.
19530 MachineBasicBlock *
19531 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19532 MachineBasicBlock *MBB) const {
19533 MachineOperand &AddendOp = MI->getOperand(3);
19535 // Bail out early if the addend isn't a register - we can't switch these.
19536 if (!AddendOp.isReg())
19539 MachineFunction &MF = *MBB->getParent();
19540 MachineRegisterInfo &MRI = MF.getRegInfo();
19542 // Check whether the addend is defined by a PHI:
19543 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19544 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19545 if (!AddendDef.isPHI())
19548 // Look for the following pattern:
19550 // %addend = phi [%entry, 0], [%loop, %result]
19552 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19556 // %addend = phi [%entry, 0], [%loop, %result]
19558 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19560 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19561 assert(AddendDef.getOperand(i).isReg());
19562 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19563 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19564 if (&PHISrcInst == MI) {
19565 // Found a matching instruction.
19566 unsigned NewFMAOpc = 0;
19567 switch (MI->getOpcode()) {
19568 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19569 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19570 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19571 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19572 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19573 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19574 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19575 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19576 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19577 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19578 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19579 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19580 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19581 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19582 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19583 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19584 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19585 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19586 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19587 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19589 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19590 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19591 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19592 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19593 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19594 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19595 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19596 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19597 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19598 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19599 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19600 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19601 default: llvm_unreachable("Unrecognized FMA variant.");
19604 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19605 MachineInstrBuilder MIB =
19606 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19607 .addOperand(MI->getOperand(0))
19608 .addOperand(MI->getOperand(3))
19609 .addOperand(MI->getOperand(2))
19610 .addOperand(MI->getOperand(1));
19611 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19612 MI->eraseFromParent();
19619 MachineBasicBlock *
19620 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19621 MachineBasicBlock *BB) const {
19622 switch (MI->getOpcode()) {
19623 default: llvm_unreachable("Unexpected instr type to insert");
19624 case X86::TAILJMPd64:
19625 case X86::TAILJMPr64:
19626 case X86::TAILJMPm64:
19627 case X86::TAILJMPd64_REX:
19628 case X86::TAILJMPr64_REX:
19629 case X86::TAILJMPm64_REX:
19630 llvm_unreachable("TAILJMP64 would not be touched here.");
19631 case X86::TCRETURNdi64:
19632 case X86::TCRETURNri64:
19633 case X86::TCRETURNmi64:
19635 case X86::WIN_ALLOCA:
19636 return EmitLoweredWinAlloca(MI, BB);
19637 case X86::SEG_ALLOCA_32:
19638 case X86::SEG_ALLOCA_64:
19639 return EmitLoweredSegAlloca(MI, BB);
19640 case X86::TLSCall_32:
19641 case X86::TLSCall_64:
19642 return EmitLoweredTLSCall(MI, BB);
19643 case X86::CMOV_GR8:
19644 case X86::CMOV_FR32:
19645 case X86::CMOV_FR64:
19646 case X86::CMOV_V4F32:
19647 case X86::CMOV_V2F64:
19648 case X86::CMOV_V2I64:
19649 case X86::CMOV_V8F32:
19650 case X86::CMOV_V4F64:
19651 case X86::CMOV_V4I64:
19652 case X86::CMOV_V16F32:
19653 case X86::CMOV_V8F64:
19654 case X86::CMOV_V8I64:
19655 case X86::CMOV_GR16:
19656 case X86::CMOV_GR32:
19657 case X86::CMOV_RFP32:
19658 case X86::CMOV_RFP64:
19659 case X86::CMOV_RFP80:
19660 case X86::CMOV_V8I1:
19661 case X86::CMOV_V16I1:
19662 case X86::CMOV_V32I1:
19663 case X86::CMOV_V64I1:
19664 return EmitLoweredSelect(MI, BB);
19666 case X86::FP32_TO_INT16_IN_MEM:
19667 case X86::FP32_TO_INT32_IN_MEM:
19668 case X86::FP32_TO_INT64_IN_MEM:
19669 case X86::FP64_TO_INT16_IN_MEM:
19670 case X86::FP64_TO_INT32_IN_MEM:
19671 case X86::FP64_TO_INT64_IN_MEM:
19672 case X86::FP80_TO_INT16_IN_MEM:
19673 case X86::FP80_TO_INT32_IN_MEM:
19674 case X86::FP80_TO_INT64_IN_MEM: {
19675 MachineFunction *F = BB->getParent();
19676 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19677 DebugLoc DL = MI->getDebugLoc();
19679 // Change the floating point control register to use "round towards zero"
19680 // mode when truncating to an integer value.
19681 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19682 addFrameReference(BuildMI(*BB, MI, DL,
19683 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19685 // Load the old value of the high byte of the control word...
19687 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19688 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19691 // Set the high part to be round to zero...
19692 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19695 // Reload the modified control word now...
19696 addFrameReference(BuildMI(*BB, MI, DL,
19697 TII->get(X86::FLDCW16m)), CWFrameIdx);
19699 // Restore the memory image of control word to original value
19700 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19703 // Get the X86 opcode to use.
19705 switch (MI->getOpcode()) {
19706 default: llvm_unreachable("illegal opcode!");
19707 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19708 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19709 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19710 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19711 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19712 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19713 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19714 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19715 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19719 MachineOperand &Op = MI->getOperand(0);
19721 AM.BaseType = X86AddressMode::RegBase;
19722 AM.Base.Reg = Op.getReg();
19724 AM.BaseType = X86AddressMode::FrameIndexBase;
19725 AM.Base.FrameIndex = Op.getIndex();
19727 Op = MI->getOperand(1);
19729 AM.Scale = Op.getImm();
19730 Op = MI->getOperand(2);
19732 AM.IndexReg = Op.getImm();
19733 Op = MI->getOperand(3);
19734 if (Op.isGlobal()) {
19735 AM.GV = Op.getGlobal();
19737 AM.Disp = Op.getImm();
19739 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19740 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19742 // Reload the original control word now.
19743 addFrameReference(BuildMI(*BB, MI, DL,
19744 TII->get(X86::FLDCW16m)), CWFrameIdx);
19746 MI->eraseFromParent(); // The pseudo instruction is gone now.
19749 // String/text processing lowering.
19750 case X86::PCMPISTRM128REG:
19751 case X86::VPCMPISTRM128REG:
19752 case X86::PCMPISTRM128MEM:
19753 case X86::VPCMPISTRM128MEM:
19754 case X86::PCMPESTRM128REG:
19755 case X86::VPCMPESTRM128REG:
19756 case X86::PCMPESTRM128MEM:
19757 case X86::VPCMPESTRM128MEM:
19758 assert(Subtarget->hasSSE42() &&
19759 "Target must have SSE4.2 or AVX features enabled");
19760 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19762 // String/text processing lowering.
19763 case X86::PCMPISTRIREG:
19764 case X86::VPCMPISTRIREG:
19765 case X86::PCMPISTRIMEM:
19766 case X86::VPCMPISTRIMEM:
19767 case X86::PCMPESTRIREG:
19768 case X86::VPCMPESTRIREG:
19769 case X86::PCMPESTRIMEM:
19770 case X86::VPCMPESTRIMEM:
19771 assert(Subtarget->hasSSE42() &&
19772 "Target must have SSE4.2 or AVX features enabled");
19773 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19775 // Thread synchronization.
19777 return EmitMonitor(MI, BB, Subtarget);
19781 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19783 case X86::VASTART_SAVE_XMM_REGS:
19784 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19786 case X86::VAARG_64:
19787 return EmitVAARG64WithCustomInserter(MI, BB);
19789 case X86::EH_SjLj_SetJmp32:
19790 case X86::EH_SjLj_SetJmp64:
19791 return emitEHSjLjSetJmp(MI, BB);
19793 case X86::EH_SjLj_LongJmp32:
19794 case X86::EH_SjLj_LongJmp64:
19795 return emitEHSjLjLongJmp(MI, BB);
19797 case TargetOpcode::STATEPOINT:
19798 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19799 // this point in the process. We diverge later.
19800 return emitPatchPoint(MI, BB);
19802 case TargetOpcode::STACKMAP:
19803 case TargetOpcode::PATCHPOINT:
19804 return emitPatchPoint(MI, BB);
19806 case X86::VFMADDPDr213r:
19807 case X86::VFMADDPSr213r:
19808 case X86::VFMADDSDr213r:
19809 case X86::VFMADDSSr213r:
19810 case X86::VFMSUBPDr213r:
19811 case X86::VFMSUBPSr213r:
19812 case X86::VFMSUBSDr213r:
19813 case X86::VFMSUBSSr213r:
19814 case X86::VFNMADDPDr213r:
19815 case X86::VFNMADDPSr213r:
19816 case X86::VFNMADDSDr213r:
19817 case X86::VFNMADDSSr213r:
19818 case X86::VFNMSUBPDr213r:
19819 case X86::VFNMSUBPSr213r:
19820 case X86::VFNMSUBSDr213r:
19821 case X86::VFNMSUBSSr213r:
19822 case X86::VFMADDSUBPDr213r:
19823 case X86::VFMADDSUBPSr213r:
19824 case X86::VFMSUBADDPDr213r:
19825 case X86::VFMSUBADDPSr213r:
19826 case X86::VFMADDPDr213rY:
19827 case X86::VFMADDPSr213rY:
19828 case X86::VFMSUBPDr213rY:
19829 case X86::VFMSUBPSr213rY:
19830 case X86::VFNMADDPDr213rY:
19831 case X86::VFNMADDPSr213rY:
19832 case X86::VFNMSUBPDr213rY:
19833 case X86::VFNMSUBPSr213rY:
19834 case X86::VFMADDSUBPDr213rY:
19835 case X86::VFMADDSUBPSr213rY:
19836 case X86::VFMSUBADDPDr213rY:
19837 case X86::VFMSUBADDPSr213rY:
19838 return emitFMA3Instr(MI, BB);
19842 //===----------------------------------------------------------------------===//
19843 // X86 Optimization Hooks
19844 //===----------------------------------------------------------------------===//
19846 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19849 const SelectionDAG &DAG,
19850 unsigned Depth) const {
19851 unsigned BitWidth = KnownZero.getBitWidth();
19852 unsigned Opc = Op.getOpcode();
19853 assert((Opc >= ISD::BUILTIN_OP_END ||
19854 Opc == ISD::INTRINSIC_WO_CHAIN ||
19855 Opc == ISD::INTRINSIC_W_CHAIN ||
19856 Opc == ISD::INTRINSIC_VOID) &&
19857 "Should use MaskedValueIsZero if you don't know whether Op"
19858 " is a target node!");
19860 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19874 // These nodes' second result is a boolean.
19875 if (Op.getResNo() == 0)
19878 case X86ISD::SETCC:
19879 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19881 case ISD::INTRINSIC_WO_CHAIN: {
19882 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19883 unsigned NumLoBits = 0;
19886 case Intrinsic::x86_sse_movmsk_ps:
19887 case Intrinsic::x86_avx_movmsk_ps_256:
19888 case Intrinsic::x86_sse2_movmsk_pd:
19889 case Intrinsic::x86_avx_movmsk_pd_256:
19890 case Intrinsic::x86_mmx_pmovmskb:
19891 case Intrinsic::x86_sse2_pmovmskb_128:
19892 case Intrinsic::x86_avx2_pmovmskb: {
19893 // High bits of movmskp{s|d}, pmovmskb are known zero.
19895 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19896 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19897 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19898 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19899 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19900 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19901 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19902 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19904 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19913 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19915 const SelectionDAG &,
19916 unsigned Depth) const {
19917 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19918 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19919 return Op.getValueType().getScalarType().getSizeInBits();
19925 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19926 /// node is a GlobalAddress + offset.
19927 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19928 const GlobalValue* &GA,
19929 int64_t &Offset) const {
19930 if (N->getOpcode() == X86ISD::Wrapper) {
19931 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19932 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19933 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19937 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19940 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19941 /// same as extracting the high 128-bit part of 256-bit vector and then
19942 /// inserting the result into the low part of a new 256-bit vector
19943 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19944 EVT VT = SVOp->getValueType(0);
19945 unsigned NumElems = VT.getVectorNumElements();
19947 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19948 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19949 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19950 SVOp->getMaskElt(j) >= 0)
19956 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19957 /// same as extracting the low 128-bit part of 256-bit vector and then
19958 /// inserting the result into the high part of a new 256-bit vector
19959 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19960 EVT VT = SVOp->getValueType(0);
19961 unsigned NumElems = VT.getVectorNumElements();
19963 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19964 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19965 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19966 SVOp->getMaskElt(j) >= 0)
19972 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19973 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19974 TargetLowering::DAGCombinerInfo &DCI,
19975 const X86Subtarget* Subtarget) {
19977 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19978 SDValue V1 = SVOp->getOperand(0);
19979 SDValue V2 = SVOp->getOperand(1);
19980 EVT VT = SVOp->getValueType(0);
19981 unsigned NumElems = VT.getVectorNumElements();
19983 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19984 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19988 // V UNDEF BUILD_VECTOR UNDEF
19990 // CONCAT_VECTOR CONCAT_VECTOR
19993 // RESULT: V + zero extended
19995 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19996 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19997 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20000 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20003 // To match the shuffle mask, the first half of the mask should
20004 // be exactly the first vector, and all the rest a splat with the
20005 // first element of the second one.
20006 for (unsigned i = 0; i != NumElems/2; ++i)
20007 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20008 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20011 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20012 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20013 if (Ld->hasNUsesOfValue(1, 0)) {
20014 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20015 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20017 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20019 Ld->getPointerInfo(),
20020 Ld->getAlignment(),
20021 false/*isVolatile*/, true/*ReadMem*/,
20022 false/*WriteMem*/);
20024 // Make sure the newly-created LOAD is in the same position as Ld in
20025 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20026 // and update uses of Ld's output chain to use the TokenFactor.
20027 if (Ld->hasAnyUseOfValue(1)) {
20028 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20029 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20030 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20031 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20032 SDValue(ResNode.getNode(), 1));
20035 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20039 // Emit a zeroed vector and insert the desired subvector on its
20041 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20042 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20043 return DCI.CombineTo(N, InsV);
20046 //===--------------------------------------------------------------------===//
20047 // Combine some shuffles into subvector extracts and inserts:
20050 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20051 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20052 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20053 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20054 return DCI.CombineTo(N, InsV);
20057 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20058 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20059 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20060 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20061 return DCI.CombineTo(N, InsV);
20067 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20070 /// This is the leaf of the recursive combinine below. When we have found some
20071 /// chain of single-use x86 shuffle instructions and accumulated the combined
20072 /// shuffle mask represented by them, this will try to pattern match that mask
20073 /// into either a single instruction if there is a special purpose instruction
20074 /// for this operation, or into a PSHUFB instruction which is a fully general
20075 /// instruction but should only be used to replace chains over a certain depth.
20076 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20077 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20078 TargetLowering::DAGCombinerInfo &DCI,
20079 const X86Subtarget *Subtarget) {
20080 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20082 // Find the operand that enters the chain. Note that multiple uses are OK
20083 // here, we're not going to remove the operand we find.
20084 SDValue Input = Op.getOperand(0);
20085 while (Input.getOpcode() == ISD::BITCAST)
20086 Input = Input.getOperand(0);
20088 MVT VT = Input.getSimpleValueType();
20089 MVT RootVT = Root.getSimpleValueType();
20092 // Just remove no-op shuffle masks.
20093 if (Mask.size() == 1) {
20094 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20099 // Use the float domain if the operand type is a floating point type.
20100 bool FloatDomain = VT.isFloatingPoint();
20102 // For floating point shuffles, we don't have free copies in the shuffle
20103 // instructions or the ability to load as part of the instruction, so
20104 // canonicalize their shuffles to UNPCK or MOV variants.
20106 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20107 // vectors because it can have a load folded into it that UNPCK cannot. This
20108 // doesn't preclude something switching to the shorter encoding post-RA.
20110 // FIXME: Should teach these routines about AVX vector widths.
20111 if (FloatDomain && VT.getSizeInBits() == 128) {
20112 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20113 bool Lo = Mask.equals({0, 0});
20116 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20117 // is no slower than UNPCKLPD but has the option to fold the input operand
20118 // into even an unaligned memory load.
20119 if (Lo && Subtarget->hasSSE3()) {
20120 Shuffle = X86ISD::MOVDDUP;
20121 ShuffleVT = MVT::v2f64;
20123 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20124 // than the UNPCK variants.
20125 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20126 ShuffleVT = MVT::v4f32;
20128 if (Depth == 1 && Root->getOpcode() == Shuffle)
20129 return false; // Nothing to do!
20130 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20131 DCI.AddToWorklist(Op.getNode());
20132 if (Shuffle == X86ISD::MOVDDUP)
20133 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20135 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20136 DCI.AddToWorklist(Op.getNode());
20137 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20141 if (Subtarget->hasSSE3() &&
20142 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20143 bool Lo = Mask.equals({0, 0, 2, 2});
20144 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20145 MVT ShuffleVT = MVT::v4f32;
20146 if (Depth == 1 && Root->getOpcode() == Shuffle)
20147 return false; // Nothing to do!
20148 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20149 DCI.AddToWorklist(Op.getNode());
20150 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20151 DCI.AddToWorklist(Op.getNode());
20152 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20156 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20157 bool Lo = Mask.equals({0, 0, 1, 1});
20158 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20159 MVT ShuffleVT = MVT::v4f32;
20160 if (Depth == 1 && Root->getOpcode() == Shuffle)
20161 return false; // Nothing to do!
20162 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20163 DCI.AddToWorklist(Op.getNode());
20164 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20165 DCI.AddToWorklist(Op.getNode());
20166 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20172 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20173 // variants as none of these have single-instruction variants that are
20174 // superior to the UNPCK formulation.
20175 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20176 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20177 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20178 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20180 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20181 bool Lo = Mask[0] == 0;
20182 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20183 if (Depth == 1 && Root->getOpcode() == Shuffle)
20184 return false; // Nothing to do!
20186 switch (Mask.size()) {
20188 ShuffleVT = MVT::v8i16;
20191 ShuffleVT = MVT::v16i8;
20194 llvm_unreachable("Impossible mask size!");
20196 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20197 DCI.AddToWorklist(Op.getNode());
20198 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20199 DCI.AddToWorklist(Op.getNode());
20200 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20205 // Don't try to re-form single instruction chains under any circumstances now
20206 // that we've done encoding canonicalization for them.
20210 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20211 // can replace them with a single PSHUFB instruction profitably. Intel's
20212 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20213 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20214 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20215 SmallVector<SDValue, 16> PSHUFBMask;
20216 int NumBytes = VT.getSizeInBits() / 8;
20217 int Ratio = NumBytes / Mask.size();
20218 for (int i = 0; i < NumBytes; ++i) {
20219 if (Mask[i / Ratio] == SM_SentinelUndef) {
20220 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20223 int M = Mask[i / Ratio] != SM_SentinelZero
20224 ? Ratio * Mask[i / Ratio] + i % Ratio
20226 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20228 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20229 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
20230 DCI.AddToWorklist(Op.getNode());
20231 SDValue PSHUFBMaskOp =
20232 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20233 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20234 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20235 DCI.AddToWorklist(Op.getNode());
20236 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20241 // Failed to find any combines.
20245 /// \brief Fully generic combining of x86 shuffle instructions.
20247 /// This should be the last combine run over the x86 shuffle instructions. Once
20248 /// they have been fully optimized, this will recursively consider all chains
20249 /// of single-use shuffle instructions, build a generic model of the cumulative
20250 /// shuffle operation, and check for simpler instructions which implement this
20251 /// operation. We use this primarily for two purposes:
20253 /// 1) Collapse generic shuffles to specialized single instructions when
20254 /// equivalent. In most cases, this is just an encoding size win, but
20255 /// sometimes we will collapse multiple generic shuffles into a single
20256 /// special-purpose shuffle.
20257 /// 2) Look for sequences of shuffle instructions with 3 or more total
20258 /// instructions, and replace them with the slightly more expensive SSSE3
20259 /// PSHUFB instruction if available. We do this as the last combining step
20260 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20261 /// a suitable short sequence of other instructions. The PHUFB will either
20262 /// use a register or have to read from memory and so is slightly (but only
20263 /// slightly) more expensive than the other shuffle instructions.
20265 /// Because this is inherently a quadratic operation (for each shuffle in
20266 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20267 /// This should never be an issue in practice as the shuffle lowering doesn't
20268 /// produce sequences of more than 8 instructions.
20270 /// FIXME: We will currently miss some cases where the redundant shuffling
20271 /// would simplify under the threshold for PSHUFB formation because of
20272 /// combine-ordering. To fix this, we should do the redundant instruction
20273 /// combining in this recursive walk.
20274 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20275 ArrayRef<int> RootMask,
20276 int Depth, bool HasPSHUFB,
20278 TargetLowering::DAGCombinerInfo &DCI,
20279 const X86Subtarget *Subtarget) {
20280 // Bound the depth of our recursive combine because this is ultimately
20281 // quadratic in nature.
20285 // Directly rip through bitcasts to find the underlying operand.
20286 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20287 Op = Op.getOperand(0);
20289 MVT VT = Op.getSimpleValueType();
20290 if (!VT.isVector())
20291 return false; // Bail if we hit a non-vector.
20293 assert(Root.getSimpleValueType().isVector() &&
20294 "Shuffles operate on vector types!");
20295 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20296 "Can only combine shuffles of the same vector register size.");
20298 if (!isTargetShuffle(Op.getOpcode()))
20300 SmallVector<int, 16> OpMask;
20302 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20303 // We only can combine unary shuffles which we can decode the mask for.
20304 if (!HaveMask || !IsUnary)
20307 assert(VT.getVectorNumElements() == OpMask.size() &&
20308 "Different mask size from vector size!");
20309 assert(((RootMask.size() > OpMask.size() &&
20310 RootMask.size() % OpMask.size() == 0) ||
20311 (OpMask.size() > RootMask.size() &&
20312 OpMask.size() % RootMask.size() == 0) ||
20313 OpMask.size() == RootMask.size()) &&
20314 "The smaller number of elements must divide the larger.");
20315 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20316 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20317 assert(((RootRatio == 1 && OpRatio == 1) ||
20318 (RootRatio == 1) != (OpRatio == 1)) &&
20319 "Must not have a ratio for both incoming and op masks!");
20321 SmallVector<int, 16> Mask;
20322 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20324 // Merge this shuffle operation's mask into our accumulated mask. Note that
20325 // this shuffle's mask will be the first applied to the input, followed by the
20326 // root mask to get us all the way to the root value arrangement. The reason
20327 // for this order is that we are recursing up the operation chain.
20328 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20329 int RootIdx = i / RootRatio;
20330 if (RootMask[RootIdx] < 0) {
20331 // This is a zero or undef lane, we're done.
20332 Mask.push_back(RootMask[RootIdx]);
20336 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20337 int OpIdx = RootMaskedIdx / OpRatio;
20338 if (OpMask[OpIdx] < 0) {
20339 // The incoming lanes are zero or undef, it doesn't matter which ones we
20341 Mask.push_back(OpMask[OpIdx]);
20345 // Ok, we have non-zero lanes, map them through.
20346 Mask.push_back(OpMask[OpIdx] * OpRatio +
20347 RootMaskedIdx % OpRatio);
20350 // See if we can recurse into the operand to combine more things.
20351 switch (Op.getOpcode()) {
20352 case X86ISD::PSHUFB:
20354 case X86ISD::PSHUFD:
20355 case X86ISD::PSHUFHW:
20356 case X86ISD::PSHUFLW:
20357 if (Op.getOperand(0).hasOneUse() &&
20358 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20359 HasPSHUFB, DAG, DCI, Subtarget))
20363 case X86ISD::UNPCKL:
20364 case X86ISD::UNPCKH:
20365 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20366 // We can't check for single use, we have to check that this shuffle is the only user.
20367 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20368 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20369 HasPSHUFB, DAG, DCI, Subtarget))
20374 // Minor canonicalization of the accumulated shuffle mask to make it easier
20375 // to match below. All this does is detect masks with squential pairs of
20376 // elements, and shrink them to the half-width mask. It does this in a loop
20377 // so it will reduce the size of the mask to the minimal width mask which
20378 // performs an equivalent shuffle.
20379 SmallVector<int, 16> WidenedMask;
20380 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20381 Mask = std::move(WidenedMask);
20382 WidenedMask.clear();
20385 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20389 /// \brief Get the PSHUF-style mask from PSHUF node.
20391 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20392 /// PSHUF-style masks that can be reused with such instructions.
20393 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20394 MVT VT = N.getSimpleValueType();
20395 SmallVector<int, 4> Mask;
20397 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20401 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20402 // matter. Check that the upper masks are repeats and remove them.
20403 if (VT.getSizeInBits() > 128) {
20404 int LaneElts = 128 / VT.getScalarSizeInBits();
20406 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20407 for (int j = 0; j < LaneElts; ++j)
20408 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
20409 "Mask doesn't repeat in high 128-bit lanes!");
20411 Mask.resize(LaneElts);
20414 switch (N.getOpcode()) {
20415 case X86ISD::PSHUFD:
20417 case X86ISD::PSHUFLW:
20420 case X86ISD::PSHUFHW:
20421 Mask.erase(Mask.begin(), Mask.begin() + 4);
20422 for (int &M : Mask)
20426 llvm_unreachable("No valid shuffle instruction found!");
20430 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20432 /// We walk up the chain and look for a combinable shuffle, skipping over
20433 /// shuffles that we could hoist this shuffle's transformation past without
20434 /// altering anything.
20436 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20438 TargetLowering::DAGCombinerInfo &DCI) {
20439 assert(N.getOpcode() == X86ISD::PSHUFD &&
20440 "Called with something other than an x86 128-bit half shuffle!");
20443 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20444 // of the shuffles in the chain so that we can form a fresh chain to replace
20446 SmallVector<SDValue, 8> Chain;
20447 SDValue V = N.getOperand(0);
20448 for (; V.hasOneUse(); V = V.getOperand(0)) {
20449 switch (V.getOpcode()) {
20451 return SDValue(); // Nothing combined!
20454 // Skip bitcasts as we always know the type for the target specific
20458 case X86ISD::PSHUFD:
20459 // Found another dword shuffle.
20462 case X86ISD::PSHUFLW:
20463 // Check that the low words (being shuffled) are the identity in the
20464 // dword shuffle, and the high words are self-contained.
20465 if (Mask[0] != 0 || Mask[1] != 1 ||
20466 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20469 Chain.push_back(V);
20472 case X86ISD::PSHUFHW:
20473 // Check that the high words (being shuffled) are the identity in the
20474 // dword shuffle, and the low words are self-contained.
20475 if (Mask[2] != 2 || Mask[3] != 3 ||
20476 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20479 Chain.push_back(V);
20482 case X86ISD::UNPCKL:
20483 case X86ISD::UNPCKH:
20484 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20485 // shuffle into a preceding word shuffle.
20486 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20487 V.getSimpleValueType().getScalarType() != MVT::i16)
20490 // Search for a half-shuffle which we can combine with.
20491 unsigned CombineOp =
20492 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20493 if (V.getOperand(0) != V.getOperand(1) ||
20494 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20496 Chain.push_back(V);
20497 V = V.getOperand(0);
20499 switch (V.getOpcode()) {
20501 return SDValue(); // Nothing to combine.
20503 case X86ISD::PSHUFLW:
20504 case X86ISD::PSHUFHW:
20505 if (V.getOpcode() == CombineOp)
20508 Chain.push_back(V);
20512 V = V.getOperand(0);
20516 } while (V.hasOneUse());
20519 // Break out of the loop if we break out of the switch.
20523 if (!V.hasOneUse())
20524 // We fell out of the loop without finding a viable combining instruction.
20527 // Merge this node's mask and our incoming mask.
20528 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20529 for (int &M : Mask)
20531 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20532 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20534 // Rebuild the chain around this new shuffle.
20535 while (!Chain.empty()) {
20536 SDValue W = Chain.pop_back_val();
20538 if (V.getValueType() != W.getOperand(0).getValueType())
20539 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20541 switch (W.getOpcode()) {
20543 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20545 case X86ISD::UNPCKL:
20546 case X86ISD::UNPCKH:
20547 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20550 case X86ISD::PSHUFD:
20551 case X86ISD::PSHUFLW:
20552 case X86ISD::PSHUFHW:
20553 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20557 if (V.getValueType() != N.getValueType())
20558 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20560 // Return the new chain to replace N.
20564 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20566 /// We walk up the chain, skipping shuffles of the other half and looking
20567 /// through shuffles which switch halves trying to find a shuffle of the same
20568 /// pair of dwords.
20569 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20571 TargetLowering::DAGCombinerInfo &DCI) {
20573 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20574 "Called with something other than an x86 128-bit half shuffle!");
20576 unsigned CombineOpcode = N.getOpcode();
20578 // Walk up a single-use chain looking for a combinable shuffle.
20579 SDValue V = N.getOperand(0);
20580 for (; V.hasOneUse(); V = V.getOperand(0)) {
20581 switch (V.getOpcode()) {
20583 return false; // Nothing combined!
20586 // Skip bitcasts as we always know the type for the target specific
20590 case X86ISD::PSHUFLW:
20591 case X86ISD::PSHUFHW:
20592 if (V.getOpcode() == CombineOpcode)
20595 // Other-half shuffles are no-ops.
20598 // Break out of the loop if we break out of the switch.
20602 if (!V.hasOneUse())
20603 // We fell out of the loop without finding a viable combining instruction.
20606 // Combine away the bottom node as its shuffle will be accumulated into
20607 // a preceding shuffle.
20608 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20610 // Record the old value.
20613 // Merge this node's mask and our incoming mask (adjusted to account for all
20614 // the pshufd instructions encountered).
20615 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20616 for (int &M : Mask)
20618 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20619 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20621 // Check that the shuffles didn't cancel each other out. If not, we need to
20622 // combine to the new one.
20624 // Replace the combinable shuffle with the combined one, updating all users
20625 // so that we re-evaluate the chain here.
20626 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20631 /// \brief Try to combine x86 target specific shuffles.
20632 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20633 TargetLowering::DAGCombinerInfo &DCI,
20634 const X86Subtarget *Subtarget) {
20636 MVT VT = N.getSimpleValueType();
20637 SmallVector<int, 4> Mask;
20639 switch (N.getOpcode()) {
20640 case X86ISD::PSHUFD:
20641 case X86ISD::PSHUFLW:
20642 case X86ISD::PSHUFHW:
20643 Mask = getPSHUFShuffleMask(N);
20644 assert(Mask.size() == 4);
20650 // Nuke no-op shuffles that show up after combining.
20651 if (isNoopShuffleMask(Mask))
20652 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20654 // Look for simplifications involving one or two shuffle instructions.
20655 SDValue V = N.getOperand(0);
20656 switch (N.getOpcode()) {
20659 case X86ISD::PSHUFLW:
20660 case X86ISD::PSHUFHW:
20661 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20663 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20664 return SDValue(); // We combined away this shuffle, so we're done.
20666 // See if this reduces to a PSHUFD which is no more expensive and can
20667 // combine with more operations. Note that it has to at least flip the
20668 // dwords as otherwise it would have been removed as a no-op.
20669 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20670 int DMask[] = {0, 1, 2, 3};
20671 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20672 DMask[DOffset + 0] = DOffset + 1;
20673 DMask[DOffset + 1] = DOffset + 0;
20674 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20675 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20676 DCI.AddToWorklist(V.getNode());
20677 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20678 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20679 DCI.AddToWorklist(V.getNode());
20680 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20683 // Look for shuffle patterns which can be implemented as a single unpack.
20684 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20685 // only works when we have a PSHUFD followed by two half-shuffles.
20686 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20687 (V.getOpcode() == X86ISD::PSHUFLW ||
20688 V.getOpcode() == X86ISD::PSHUFHW) &&
20689 V.getOpcode() != N.getOpcode() &&
20691 SDValue D = V.getOperand(0);
20692 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20693 D = D.getOperand(0);
20694 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20695 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20696 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20697 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20698 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20700 for (int i = 0; i < 4; ++i) {
20701 WordMask[i + NOffset] = Mask[i] + NOffset;
20702 WordMask[i + VOffset] = VMask[i] + VOffset;
20704 // Map the word mask through the DWord mask.
20706 for (int i = 0; i < 8; ++i)
20707 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20708 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20709 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20710 // We can replace all three shuffles with an unpack.
20711 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20712 DCI.AddToWorklist(V.getNode());
20713 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20722 case X86ISD::PSHUFD:
20723 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20732 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20734 /// We combine this directly on the abstract vector shuffle nodes so it is
20735 /// easier to generically match. We also insert dummy vector shuffle nodes for
20736 /// the operands which explicitly discard the lanes which are unused by this
20737 /// operation to try to flow through the rest of the combiner the fact that
20738 /// they're unused.
20739 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20741 EVT VT = N->getValueType(0);
20743 // We only handle target-independent shuffles.
20744 // FIXME: It would be easy and harmless to use the target shuffle mask
20745 // extraction tool to support more.
20746 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20749 auto *SVN = cast<ShuffleVectorSDNode>(N);
20750 ArrayRef<int> Mask = SVN->getMask();
20751 SDValue V1 = N->getOperand(0);
20752 SDValue V2 = N->getOperand(1);
20754 // We require the first shuffle operand to be the SUB node, and the second to
20755 // be the ADD node.
20756 // FIXME: We should support the commuted patterns.
20757 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20760 // If there are other uses of these operations we can't fold them.
20761 if (!V1->hasOneUse() || !V2->hasOneUse())
20764 // Ensure that both operations have the same operands. Note that we can
20765 // commute the FADD operands.
20766 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20767 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20768 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20771 // We're looking for blends between FADD and FSUB nodes. We insist on these
20772 // nodes being lined up in a specific expected pattern.
20773 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20774 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20775 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20778 // Only specific types are legal at this point, assert so we notice if and
20779 // when these change.
20780 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20781 VT == MVT::v4f64) &&
20782 "Unknown vector type encountered!");
20784 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20787 /// PerformShuffleCombine - Performs several different shuffle combines.
20788 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20789 TargetLowering::DAGCombinerInfo &DCI,
20790 const X86Subtarget *Subtarget) {
20792 SDValue N0 = N->getOperand(0);
20793 SDValue N1 = N->getOperand(1);
20794 EVT VT = N->getValueType(0);
20796 // Don't create instructions with illegal types after legalize types has run.
20797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20798 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20801 // If we have legalized the vector types, look for blends of FADD and FSUB
20802 // nodes that we can fuse into an ADDSUB node.
20803 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20804 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20807 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20808 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20809 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20810 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20812 // During Type Legalization, when promoting illegal vector types,
20813 // the backend might introduce new shuffle dag nodes and bitcasts.
20815 // This code performs the following transformation:
20816 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20817 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20819 // We do this only if both the bitcast and the BINOP dag nodes have
20820 // one use. Also, perform this transformation only if the new binary
20821 // operation is legal. This is to avoid introducing dag nodes that
20822 // potentially need to be further expanded (or custom lowered) into a
20823 // less optimal sequence of dag nodes.
20824 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20825 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20826 N0.getOpcode() == ISD::BITCAST) {
20827 SDValue BC0 = N0.getOperand(0);
20828 EVT SVT = BC0.getValueType();
20829 unsigned Opcode = BC0.getOpcode();
20830 unsigned NumElts = VT.getVectorNumElements();
20832 if (BC0.hasOneUse() && SVT.isVector() &&
20833 SVT.getVectorNumElements() * 2 == NumElts &&
20834 TLI.isOperationLegal(Opcode, VT)) {
20835 bool CanFold = false;
20847 unsigned SVTNumElts = SVT.getVectorNumElements();
20848 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20849 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20850 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20851 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20852 CanFold = SVOp->getMaskElt(i) < 0;
20855 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20856 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20857 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20858 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20863 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20864 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20865 // consecutive, non-overlapping, and in the right order.
20866 SmallVector<SDValue, 16> Elts;
20867 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20868 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20870 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20874 if (isTargetShuffle(N->getOpcode())) {
20876 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20877 if (Shuffle.getNode())
20880 // Try recursively combining arbitrary sequences of x86 shuffle
20881 // instructions into higher-order shuffles. We do this after combining
20882 // specific PSHUF instruction sequences into their minimal form so that we
20883 // can evaluate how many specialized shuffle instructions are involved in
20884 // a particular chain.
20885 SmallVector<int, 1> NonceMask; // Just a placeholder.
20886 NonceMask.push_back(0);
20887 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20888 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20890 return SDValue(); // This routine will use CombineTo to replace N.
20896 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20897 /// specific shuffle of a load can be folded into a single element load.
20898 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20899 /// shuffles have been custom lowered so we need to handle those here.
20900 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20901 TargetLowering::DAGCombinerInfo &DCI) {
20902 if (DCI.isBeforeLegalizeOps())
20905 SDValue InVec = N->getOperand(0);
20906 SDValue EltNo = N->getOperand(1);
20908 if (!isa<ConstantSDNode>(EltNo))
20911 EVT OriginalVT = InVec.getValueType();
20913 if (InVec.getOpcode() == ISD::BITCAST) {
20914 // Don't duplicate a load with other uses.
20915 if (!InVec.hasOneUse())
20917 EVT BCVT = InVec.getOperand(0).getValueType();
20918 if (!BCVT.isVector() ||
20919 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20921 InVec = InVec.getOperand(0);
20924 EVT CurrentVT = InVec.getValueType();
20926 if (!isTargetShuffle(InVec.getOpcode()))
20929 // Don't duplicate a load with other uses.
20930 if (!InVec.hasOneUse())
20933 SmallVector<int, 16> ShuffleMask;
20935 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20936 ShuffleMask, UnaryShuffle))
20939 // Select the input vector, guarding against out of range extract vector.
20940 unsigned NumElems = CurrentVT.getVectorNumElements();
20941 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20942 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20943 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20944 : InVec.getOperand(1);
20946 // If inputs to shuffle are the same for both ops, then allow 2 uses
20947 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20948 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20950 if (LdNode.getOpcode() == ISD::BITCAST) {
20951 // Don't duplicate a load with other uses.
20952 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20955 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20956 LdNode = LdNode.getOperand(0);
20959 if (!ISD::isNormalLoad(LdNode.getNode()))
20962 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20964 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20967 EVT EltVT = N->getValueType(0);
20968 // If there's a bitcast before the shuffle, check if the load type and
20969 // alignment is valid.
20970 unsigned Align = LN0->getAlignment();
20971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20972 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20973 EltVT.getTypeForEVT(*DAG.getContext()));
20975 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20978 // All checks match so transform back to vector_shuffle so that DAG combiner
20979 // can finish the job
20982 // Create shuffle node taking into account the case that its a unary shuffle
20983 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20984 : InVec.getOperand(1);
20985 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20986 InVec.getOperand(0), Shuffle,
20988 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20989 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20993 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20994 /// special and don't usually play with other vector types, it's better to
20995 /// handle them early to be sure we emit efficient code by avoiding
20996 /// store-load conversions.
20997 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20998 if (N->getValueType(0) != MVT::x86mmx ||
20999 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21000 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21003 SDValue V = N->getOperand(0);
21004 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21005 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21006 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21007 N->getValueType(0), V.getOperand(0));
21012 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21013 /// generation and convert it from being a bunch of shuffles and extracts
21014 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21015 /// storing the value and loading scalars back, while for x64 we should
21016 /// use 64-bit extracts and shifts.
21017 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21018 TargetLowering::DAGCombinerInfo &DCI) {
21019 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21020 if (NewOp.getNode())
21023 SDValue InputVector = N->getOperand(0);
21024 SDLoc dl(InputVector);
21025 // Detect mmx to i32 conversion through a v2i32 elt extract.
21026 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21027 N->getValueType(0) == MVT::i32 &&
21028 InputVector.getValueType() == MVT::v2i32) {
21030 // The bitcast source is a direct mmx result.
21031 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21032 if (MMXSrc.getValueType() == MVT::x86mmx)
21033 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21034 N->getValueType(0),
21035 InputVector.getNode()->getOperand(0));
21037 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21038 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21039 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21040 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21041 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21042 MMXSrcOp.getValueType() == MVT::v1i64 &&
21043 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21044 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21045 N->getValueType(0),
21046 MMXSrcOp.getOperand(0));
21049 EVT VT = N->getValueType(0);
21051 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21052 InputVector.getOpcode() == ISD::BITCAST &&
21053 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21054 uint64_t ExtractedElt =
21055 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21056 uint64_t InputValue =
21057 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21058 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21059 return DAG.getConstant(Res, dl, MVT::i1);
21061 // Only operate on vectors of 4 elements, where the alternative shuffling
21062 // gets to be more expensive.
21063 if (InputVector.getValueType() != MVT::v4i32)
21066 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21067 // single use which is a sign-extend or zero-extend, and all elements are
21069 SmallVector<SDNode *, 4> Uses;
21070 unsigned ExtractedElements = 0;
21071 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21072 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21073 if (UI.getUse().getResNo() != InputVector.getResNo())
21076 SDNode *Extract = *UI;
21077 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21080 if (Extract->getValueType(0) != MVT::i32)
21082 if (!Extract->hasOneUse())
21084 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21085 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21087 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21090 // Record which element was extracted.
21091 ExtractedElements |=
21092 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21094 Uses.push_back(Extract);
21097 // If not all the elements were used, this may not be worthwhile.
21098 if (ExtractedElements != 15)
21101 // Ok, we've now decided to do the transformation.
21102 // If 64-bit shifts are legal, use the extract-shift sequence,
21103 // otherwise bounce the vector off the cache.
21104 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21107 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21108 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
21109 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21110 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21111 DAG.getConstant(0, dl, VecIdxTy));
21112 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21113 DAG.getConstant(1, dl, VecIdxTy));
21115 SDValue ShAmt = DAG.getConstant(32, dl,
21116 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21117 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21118 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21119 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21120 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21121 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21122 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21124 // Store the value to a temporary stack slot.
21125 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21126 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21127 MachinePointerInfo(), false, false, 0);
21129 EVT ElementType = InputVector.getValueType().getVectorElementType();
21130 unsigned EltSize = ElementType.getSizeInBits() / 8;
21132 // Replace each use (extract) with a load of the appropriate element.
21133 for (unsigned i = 0; i < 4; ++i) {
21134 uint64_t Offset = EltSize * i;
21135 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21137 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21138 StackPtr, OffsetVal);
21140 // Load the scalar.
21141 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21142 ScalarAddr, MachinePointerInfo(),
21143 false, false, false, 0);
21148 // Replace the extracts
21149 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21150 UE = Uses.end(); UI != UE; ++UI) {
21151 SDNode *Extract = *UI;
21153 SDValue Idx = Extract->getOperand(1);
21154 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21155 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21158 // The replacement was made in place; don't return anything.
21162 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21163 static std::pair<unsigned, bool>
21164 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21165 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21166 if (!VT.isVector())
21167 return std::make_pair(0, false);
21169 bool NeedSplit = false;
21170 switch (VT.getSimpleVT().SimpleTy) {
21171 default: return std::make_pair(0, false);
21174 if (!Subtarget->hasVLX())
21175 return std::make_pair(0, false);
21179 if (!Subtarget->hasBWI())
21180 return std::make_pair(0, false);
21184 if (!Subtarget->hasAVX512())
21185 return std::make_pair(0, false);
21190 if (!Subtarget->hasAVX2())
21192 if (!Subtarget->hasAVX())
21193 return std::make_pair(0, false);
21198 if (!Subtarget->hasSSE2())
21199 return std::make_pair(0, false);
21202 // SSE2 has only a small subset of the operations.
21203 bool hasUnsigned = Subtarget->hasSSE41() ||
21204 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21205 bool hasSigned = Subtarget->hasSSE41() ||
21206 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21208 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21211 // Check for x CC y ? x : y.
21212 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21213 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21218 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21221 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21224 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21227 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21229 // Check for x CC y ? y : x -- a min/max with reversed arms.
21230 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21231 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21236 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21239 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21242 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21245 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21249 return std::make_pair(Opc, NeedSplit);
21253 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21254 const X86Subtarget *Subtarget) {
21256 SDValue Cond = N->getOperand(0);
21257 SDValue LHS = N->getOperand(1);
21258 SDValue RHS = N->getOperand(2);
21260 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21261 SDValue CondSrc = Cond->getOperand(0);
21262 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21263 Cond = CondSrc->getOperand(0);
21266 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21269 // A vselect where all conditions and data are constants can be optimized into
21270 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21271 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21272 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21275 unsigned MaskValue = 0;
21276 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21279 MVT VT = N->getSimpleValueType(0);
21280 unsigned NumElems = VT.getVectorNumElements();
21281 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21282 for (unsigned i = 0; i < NumElems; ++i) {
21283 // Be sure we emit undef where we can.
21284 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21285 ShuffleMask[i] = -1;
21287 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21290 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21291 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21293 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21296 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21298 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21299 TargetLowering::DAGCombinerInfo &DCI,
21300 const X86Subtarget *Subtarget) {
21302 SDValue Cond = N->getOperand(0);
21303 // Get the LHS/RHS of the select.
21304 SDValue LHS = N->getOperand(1);
21305 SDValue RHS = N->getOperand(2);
21306 EVT VT = LHS.getValueType();
21307 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21309 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21310 // instructions match the semantics of the common C idiom x<y?x:y but not
21311 // x<=y?x:y, because of how they handle negative zero (which can be
21312 // ignored in unsafe-math mode).
21313 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21314 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21315 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21316 (Subtarget->hasSSE2() ||
21317 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21318 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21320 unsigned Opcode = 0;
21321 // Check for x CC y ? x : y.
21322 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21323 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21327 // Converting this to a min would handle NaNs incorrectly, and swapping
21328 // the operands would cause it to handle comparisons between positive
21329 // and negative zero incorrectly.
21330 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21331 if (!DAG.getTarget().Options.UnsafeFPMath &&
21332 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21334 std::swap(LHS, RHS);
21336 Opcode = X86ISD::FMIN;
21339 // Converting this to a min would handle comparisons between positive
21340 // and negative zero incorrectly.
21341 if (!DAG.getTarget().Options.UnsafeFPMath &&
21342 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21344 Opcode = X86ISD::FMIN;
21347 // Converting this to a min would handle both negative zeros and NaNs
21348 // incorrectly, but we can swap the operands to fix both.
21349 std::swap(LHS, RHS);
21353 Opcode = X86ISD::FMIN;
21357 // Converting this to a max would handle comparisons between positive
21358 // and negative zero incorrectly.
21359 if (!DAG.getTarget().Options.UnsafeFPMath &&
21360 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21362 Opcode = X86ISD::FMAX;
21365 // Converting this to a max would handle NaNs incorrectly, and swapping
21366 // the operands would cause it to handle comparisons between positive
21367 // and negative zero incorrectly.
21368 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21369 if (!DAG.getTarget().Options.UnsafeFPMath &&
21370 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21372 std::swap(LHS, RHS);
21374 Opcode = X86ISD::FMAX;
21377 // Converting this to a max would handle both negative zeros and NaNs
21378 // incorrectly, but we can swap the operands to fix both.
21379 std::swap(LHS, RHS);
21383 Opcode = X86ISD::FMAX;
21386 // Check for x CC y ? y : x -- a min/max with reversed arms.
21387 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21388 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21392 // Converting this to a min would handle comparisons between positive
21393 // and negative zero incorrectly, and swapping the operands would
21394 // cause it to handle NaNs incorrectly.
21395 if (!DAG.getTarget().Options.UnsafeFPMath &&
21396 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21397 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21399 std::swap(LHS, RHS);
21401 Opcode = X86ISD::FMIN;
21404 // Converting this to a min would handle NaNs incorrectly.
21405 if (!DAG.getTarget().Options.UnsafeFPMath &&
21406 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21408 Opcode = X86ISD::FMIN;
21411 // Converting this to a min would handle both negative zeros and NaNs
21412 // incorrectly, but we can swap the operands to fix both.
21413 std::swap(LHS, RHS);
21417 Opcode = X86ISD::FMIN;
21421 // Converting this to a max would handle NaNs incorrectly.
21422 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21424 Opcode = X86ISD::FMAX;
21427 // Converting this to a max would handle comparisons between positive
21428 // and negative zero incorrectly, and swapping the operands would
21429 // cause it to handle NaNs incorrectly.
21430 if (!DAG.getTarget().Options.UnsafeFPMath &&
21431 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21432 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21434 std::swap(LHS, RHS);
21436 Opcode = X86ISD::FMAX;
21439 // Converting this to a max would handle both negative zeros and NaNs
21440 // incorrectly, but we can swap the operands to fix both.
21441 std::swap(LHS, RHS);
21445 Opcode = X86ISD::FMAX;
21451 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21454 EVT CondVT = Cond.getValueType();
21455 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21456 CondVT.getVectorElementType() == MVT::i1) {
21457 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21458 // lowering on KNL. In this case we convert it to
21459 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21460 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21461 // Since SKX these selects have a proper lowering.
21462 EVT OpVT = LHS.getValueType();
21463 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21464 (OpVT.getVectorElementType() == MVT::i8 ||
21465 OpVT.getVectorElementType() == MVT::i16) &&
21466 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21467 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21468 DCI.AddToWorklist(Cond.getNode());
21469 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21472 // If this is a select between two integer constants, try to do some
21474 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21475 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21476 // Don't do this for crazy integer types.
21477 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21478 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21479 // so that TrueC (the true value) is larger than FalseC.
21480 bool NeedsCondInvert = false;
21482 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21483 // Efficiently invertible.
21484 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21485 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21486 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21487 NeedsCondInvert = true;
21488 std::swap(TrueC, FalseC);
21491 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21492 if (FalseC->getAPIntValue() == 0 &&
21493 TrueC->getAPIntValue().isPowerOf2()) {
21494 if (NeedsCondInvert) // Invert the condition if needed.
21495 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21496 DAG.getConstant(1, DL, Cond.getValueType()));
21498 // Zero extend the condition if needed.
21499 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21501 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21502 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21503 DAG.getConstant(ShAmt, DL, MVT::i8));
21506 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21507 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21508 if (NeedsCondInvert) // Invert the condition if needed.
21509 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21510 DAG.getConstant(1, DL, Cond.getValueType()));
21512 // Zero extend the condition if needed.
21513 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21514 FalseC->getValueType(0), Cond);
21515 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21516 SDValue(FalseC, 0));
21519 // Optimize cases that will turn into an LEA instruction. This requires
21520 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21521 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21522 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21523 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21525 bool isFastMultiplier = false;
21527 switch ((unsigned char)Diff) {
21529 case 1: // result = add base, cond
21530 case 2: // result = lea base( , cond*2)
21531 case 3: // result = lea base(cond, cond*2)
21532 case 4: // result = lea base( , cond*4)
21533 case 5: // result = lea base(cond, cond*4)
21534 case 8: // result = lea base( , cond*8)
21535 case 9: // result = lea base(cond, cond*8)
21536 isFastMultiplier = true;
21541 if (isFastMultiplier) {
21542 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21543 if (NeedsCondInvert) // Invert the condition if needed.
21544 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21545 DAG.getConstant(1, DL, Cond.getValueType()));
21547 // Zero extend the condition if needed.
21548 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21550 // Scale the condition by the difference.
21552 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21553 DAG.getConstant(Diff, DL,
21554 Cond.getValueType()));
21556 // Add the base if non-zero.
21557 if (FalseC->getAPIntValue() != 0)
21558 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21559 SDValue(FalseC, 0));
21566 // Canonicalize max and min:
21567 // (x > y) ? x : y -> (x >= y) ? x : y
21568 // (x < y) ? x : y -> (x <= y) ? x : y
21569 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21570 // the need for an extra compare
21571 // against zero. e.g.
21572 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21574 // testl %edi, %edi
21576 // cmovgl %edi, %eax
21580 // cmovsl %eax, %edi
21581 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21582 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21583 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21584 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21589 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21590 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21591 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21592 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21597 // Early exit check
21598 if (!TLI.isTypeLegal(VT))
21601 // Match VSELECTs into subs with unsigned saturation.
21602 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21603 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21604 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21605 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21606 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21608 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21609 // left side invert the predicate to simplify logic below.
21611 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21613 CC = ISD::getSetCCInverse(CC, true);
21614 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21618 if (Other.getNode() && Other->getNumOperands() == 2 &&
21619 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21620 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21621 SDValue CondRHS = Cond->getOperand(1);
21623 // Look for a general sub with unsigned saturation first.
21624 // x >= y ? x-y : 0 --> subus x, y
21625 // x > y ? x-y : 0 --> subus x, y
21626 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21627 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21628 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21630 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21631 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21632 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21633 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21634 // If the RHS is a constant we have to reverse the const
21635 // canonicalization.
21636 // x > C-1 ? x+-C : 0 --> subus x, C
21637 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21638 CondRHSConst->getAPIntValue() ==
21639 (-OpRHSConst->getAPIntValue() - 1))
21640 return DAG.getNode(
21641 X86ISD::SUBUS, DL, VT, OpLHS,
21642 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21644 // Another special case: If C was a sign bit, the sub has been
21645 // canonicalized into a xor.
21646 // FIXME: Would it be better to use computeKnownBits to determine
21647 // whether it's safe to decanonicalize the xor?
21648 // x s< 0 ? x^C : 0 --> subus x, C
21649 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21650 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21651 OpRHSConst->getAPIntValue().isSignBit())
21652 // Note that we have to rebuild the RHS constant here to ensure we
21653 // don't rely on particular values of undef lanes.
21654 return DAG.getNode(
21655 X86ISD::SUBUS, DL, VT, OpLHS,
21656 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21661 // Try to match a min/max vector operation.
21662 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21663 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21664 unsigned Opc = ret.first;
21665 bool NeedSplit = ret.second;
21667 if (Opc && NeedSplit) {
21668 unsigned NumElems = VT.getVectorNumElements();
21669 // Extract the LHS vectors
21670 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21671 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21673 // Extract the RHS vectors
21674 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21675 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21677 // Create min/max for each subvector
21678 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21679 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21681 // Merge the result
21682 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21684 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21687 // Simplify vector selection if condition value type matches vselect
21689 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21690 assert(Cond.getValueType().isVector() &&
21691 "vector select expects a vector selector!");
21693 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21694 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21696 // Try invert the condition if true value is not all 1s and false value
21698 if (!TValIsAllOnes && !FValIsAllZeros &&
21699 // Check if the selector will be produced by CMPP*/PCMP*
21700 Cond.getOpcode() == ISD::SETCC &&
21701 // Check if SETCC has already been promoted
21702 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21703 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21704 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21706 if (TValIsAllZeros || FValIsAllOnes) {
21707 SDValue CC = Cond.getOperand(2);
21708 ISD::CondCode NewCC =
21709 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21710 Cond.getOperand(0).getValueType().isInteger());
21711 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21712 std::swap(LHS, RHS);
21713 TValIsAllOnes = FValIsAllOnes;
21714 FValIsAllZeros = TValIsAllZeros;
21718 if (TValIsAllOnes || FValIsAllZeros) {
21721 if (TValIsAllOnes && FValIsAllZeros)
21723 else if (TValIsAllOnes)
21724 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21725 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21726 else if (FValIsAllZeros)
21727 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21728 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21730 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21734 // We should generate an X86ISD::BLENDI from a vselect if its argument
21735 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21736 // constants. This specific pattern gets generated when we split a
21737 // selector for a 512 bit vector in a machine without AVX512 (but with
21738 // 256-bit vectors), during legalization:
21740 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21742 // Iff we find this pattern and the build_vectors are built from
21743 // constants, we translate the vselect into a shuffle_vector that we
21744 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21745 if ((N->getOpcode() == ISD::VSELECT ||
21746 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21747 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
21748 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21749 if (Shuffle.getNode())
21753 // If this is a *dynamic* select (non-constant condition) and we can match
21754 // this node with one of the variable blend instructions, restructure the
21755 // condition so that the blends can use the high bit of each element and use
21756 // SimplifyDemandedBits to simplify the condition operand.
21757 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21758 !DCI.isBeforeLegalize() &&
21759 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21760 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21762 // Don't optimize vector selects that map to mask-registers.
21766 // We can only handle the cases where VSELECT is directly legal on the
21767 // subtarget. We custom lower VSELECT nodes with constant conditions and
21768 // this makes it hard to see whether a dynamic VSELECT will correctly
21769 // lower, so we both check the operation's status and explicitly handle the
21770 // cases where a *dynamic* blend will fail even though a constant-condition
21771 // blend could be custom lowered.
21772 // FIXME: We should find a better way to handle this class of problems.
21773 // Potentially, we should combine constant-condition vselect nodes
21774 // pre-legalization into shuffles and not mark as many types as custom
21776 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21778 // FIXME: We don't support i16-element blends currently. We could and
21779 // should support them by making *all* the bits in the condition be set
21780 // rather than just the high bit and using an i8-element blend.
21781 if (VT.getScalarType() == MVT::i16)
21783 // Dynamic blending was only available from SSE4.1 onward.
21784 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21786 // Byte blends are only available in AVX2
21787 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21788 !Subtarget->hasAVX2())
21791 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21792 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21794 APInt KnownZero, KnownOne;
21795 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21796 DCI.isBeforeLegalizeOps());
21797 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21798 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21800 // If we changed the computation somewhere in the DAG, this change
21801 // will affect all users of Cond.
21802 // Make sure it is fine and update all the nodes so that we do not
21803 // use the generic VSELECT anymore. Otherwise, we may perform
21804 // wrong optimizations as we messed up with the actual expectation
21805 // for the vector boolean values.
21806 if (Cond != TLO.Old) {
21807 // Check all uses of that condition operand to check whether it will be
21808 // consumed by non-BLEND instructions, which may depend on all bits are
21810 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21812 if (I->getOpcode() != ISD::VSELECT)
21813 // TODO: Add other opcodes eventually lowered into BLEND.
21816 // Update all the users of the condition, before committing the change,
21817 // so that the VSELECT optimizations that expect the correct vector
21818 // boolean value will not be triggered.
21819 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21821 DAG.ReplaceAllUsesOfValueWith(
21823 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21824 Cond, I->getOperand(1), I->getOperand(2)));
21825 DCI.CommitTargetLoweringOpt(TLO);
21828 // At this point, only Cond is changed. Change the condition
21829 // just for N to keep the opportunity to optimize all other
21830 // users their own way.
21831 DAG.ReplaceAllUsesOfValueWith(
21833 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21834 TLO.New, N->getOperand(1), N->getOperand(2)));
21842 // Check whether a boolean test is testing a boolean value generated by
21843 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21846 // Simplify the following patterns:
21847 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21848 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21849 // to (Op EFLAGS Cond)
21851 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21852 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21853 // to (Op EFLAGS !Cond)
21855 // where Op could be BRCOND or CMOV.
21857 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21858 // Quit if not CMP and SUB with its value result used.
21859 if (Cmp.getOpcode() != X86ISD::CMP &&
21860 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21863 // Quit if not used as a boolean value.
21864 if (CC != X86::COND_E && CC != X86::COND_NE)
21867 // Check CMP operands. One of them should be 0 or 1 and the other should be
21868 // an SetCC or extended from it.
21869 SDValue Op1 = Cmp.getOperand(0);
21870 SDValue Op2 = Cmp.getOperand(1);
21873 const ConstantSDNode* C = nullptr;
21874 bool needOppositeCond = (CC == X86::COND_E);
21875 bool checkAgainstTrue = false; // Is it a comparison against 1?
21877 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21879 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21881 else // Quit if all operands are not constants.
21884 if (C->getZExtValue() == 1) {
21885 needOppositeCond = !needOppositeCond;
21886 checkAgainstTrue = true;
21887 } else if (C->getZExtValue() != 0)
21888 // Quit if the constant is neither 0 or 1.
21891 bool truncatedToBoolWithAnd = false;
21892 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21893 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21894 SetCC.getOpcode() == ISD::TRUNCATE ||
21895 SetCC.getOpcode() == ISD::AND) {
21896 if (SetCC.getOpcode() == ISD::AND) {
21898 ConstantSDNode *CS;
21899 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21900 CS->getZExtValue() == 1)
21902 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21903 CS->getZExtValue() == 1)
21907 SetCC = SetCC.getOperand(OpIdx);
21908 truncatedToBoolWithAnd = true;
21910 SetCC = SetCC.getOperand(0);
21913 switch (SetCC.getOpcode()) {
21914 case X86ISD::SETCC_CARRY:
21915 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21916 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21917 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21918 // truncated to i1 using 'and'.
21919 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21921 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21922 "Invalid use of SETCC_CARRY!");
21924 case X86ISD::SETCC:
21925 // Set the condition code or opposite one if necessary.
21926 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21927 if (needOppositeCond)
21928 CC = X86::GetOppositeBranchCondition(CC);
21929 return SetCC.getOperand(1);
21930 case X86ISD::CMOV: {
21931 // Check whether false/true value has canonical one, i.e. 0 or 1.
21932 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21933 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21934 // Quit if true value is not a constant.
21937 // Quit if false value is not a constant.
21939 SDValue Op = SetCC.getOperand(0);
21940 // Skip 'zext' or 'trunc' node.
21941 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21942 Op.getOpcode() == ISD::TRUNCATE)
21943 Op = Op.getOperand(0);
21944 // A special case for rdrand/rdseed, where 0 is set if false cond is
21946 if ((Op.getOpcode() != X86ISD::RDRAND &&
21947 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21950 // Quit if false value is not the constant 0 or 1.
21951 bool FValIsFalse = true;
21952 if (FVal && FVal->getZExtValue() != 0) {
21953 if (FVal->getZExtValue() != 1)
21955 // If FVal is 1, opposite cond is needed.
21956 needOppositeCond = !needOppositeCond;
21957 FValIsFalse = false;
21959 // Quit if TVal is not the constant opposite of FVal.
21960 if (FValIsFalse && TVal->getZExtValue() != 1)
21962 if (!FValIsFalse && TVal->getZExtValue() != 0)
21964 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21965 if (needOppositeCond)
21966 CC = X86::GetOppositeBranchCondition(CC);
21967 return SetCC.getOperand(3);
21974 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21976 /// (X86or (X86setcc) (X86setcc))
21977 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21978 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21979 X86::CondCode &CC1, SDValue &Flags,
21981 if (Cond->getOpcode() == X86ISD::CMP) {
21982 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21983 if (!CondOp1C || !CondOp1C->isNullValue())
21986 Cond = Cond->getOperand(0);
21991 SDValue SetCC0, SetCC1;
21992 switch (Cond->getOpcode()) {
21993 default: return false;
22000 SetCC0 = Cond->getOperand(0);
22001 SetCC1 = Cond->getOperand(1);
22005 // Make sure we have SETCC nodes, using the same flags value.
22006 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22007 SetCC1.getOpcode() != X86ISD::SETCC ||
22008 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22011 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22012 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22013 Flags = SetCC0->getOperand(1);
22017 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22018 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22019 TargetLowering::DAGCombinerInfo &DCI,
22020 const X86Subtarget *Subtarget) {
22023 // If the flag operand isn't dead, don't touch this CMOV.
22024 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22027 SDValue FalseOp = N->getOperand(0);
22028 SDValue TrueOp = N->getOperand(1);
22029 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22030 SDValue Cond = N->getOperand(3);
22032 if (CC == X86::COND_E || CC == X86::COND_NE) {
22033 switch (Cond.getOpcode()) {
22037 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22038 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22039 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22045 Flags = checkBoolTestSetCCCombine(Cond, CC);
22046 if (Flags.getNode() &&
22047 // Extra check as FCMOV only supports a subset of X86 cond.
22048 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22049 SDValue Ops[] = { FalseOp, TrueOp,
22050 DAG.getConstant(CC, DL, MVT::i8), Flags };
22051 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22054 // If this is a select between two integer constants, try to do some
22055 // optimizations. Note that the operands are ordered the opposite of SELECT
22057 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22058 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22059 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22060 // larger than FalseC (the false value).
22061 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22062 CC = X86::GetOppositeBranchCondition(CC);
22063 std::swap(TrueC, FalseC);
22064 std::swap(TrueOp, FalseOp);
22067 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22068 // This is efficient for any integer data type (including i8/i16) and
22070 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22071 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22072 DAG.getConstant(CC, DL, MVT::i8), Cond);
22074 // Zero extend the condition if needed.
22075 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22077 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22078 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22079 DAG.getConstant(ShAmt, DL, MVT::i8));
22080 if (N->getNumValues() == 2) // Dead flag value?
22081 return DCI.CombineTo(N, Cond, SDValue());
22085 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22086 // for any integer data type, including i8/i16.
22087 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22088 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22089 DAG.getConstant(CC, DL, MVT::i8), Cond);
22091 // Zero extend the condition if needed.
22092 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22093 FalseC->getValueType(0), Cond);
22094 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22095 SDValue(FalseC, 0));
22097 if (N->getNumValues() == 2) // Dead flag value?
22098 return DCI.CombineTo(N, Cond, SDValue());
22102 // Optimize cases that will turn into an LEA instruction. This requires
22103 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22104 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22105 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22106 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22108 bool isFastMultiplier = false;
22110 switch ((unsigned char)Diff) {
22112 case 1: // result = add base, cond
22113 case 2: // result = lea base( , cond*2)
22114 case 3: // result = lea base(cond, cond*2)
22115 case 4: // result = lea base( , cond*4)
22116 case 5: // result = lea base(cond, cond*4)
22117 case 8: // result = lea base( , cond*8)
22118 case 9: // result = lea base(cond, cond*8)
22119 isFastMultiplier = true;
22124 if (isFastMultiplier) {
22125 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22126 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22127 DAG.getConstant(CC, DL, MVT::i8), Cond);
22128 // Zero extend the condition if needed.
22129 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22131 // Scale the condition by the difference.
22133 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22134 DAG.getConstant(Diff, DL, Cond.getValueType()));
22136 // Add the base if non-zero.
22137 if (FalseC->getAPIntValue() != 0)
22138 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22139 SDValue(FalseC, 0));
22140 if (N->getNumValues() == 2) // Dead flag value?
22141 return DCI.CombineTo(N, Cond, SDValue());
22148 // Handle these cases:
22149 // (select (x != c), e, c) -> select (x != c), e, x),
22150 // (select (x == c), c, e) -> select (x == c), x, e)
22151 // where the c is an integer constant, and the "select" is the combination
22152 // of CMOV and CMP.
22154 // The rationale for this change is that the conditional-move from a constant
22155 // needs two instructions, however, conditional-move from a register needs
22156 // only one instruction.
22158 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22159 // some instruction-combining opportunities. This opt needs to be
22160 // postponed as late as possible.
22162 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22163 // the DCI.xxxx conditions are provided to postpone the optimization as
22164 // late as possible.
22166 ConstantSDNode *CmpAgainst = nullptr;
22167 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22168 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22169 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22171 if (CC == X86::COND_NE &&
22172 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22173 CC = X86::GetOppositeBranchCondition(CC);
22174 std::swap(TrueOp, FalseOp);
22177 if (CC == X86::COND_E &&
22178 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22179 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22180 DAG.getConstant(CC, DL, MVT::i8), Cond };
22181 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22186 // Fold and/or of setcc's to double CMOV:
22187 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22188 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22190 // This combine lets us generate:
22191 // cmovcc1 (jcc1 if we don't have CMOV)
22197 // cmovne (jne if we don't have CMOV)
22198 // When we can't use the CMOV instruction, it might increase branch
22200 // When we can use CMOV, or when there is no mispredict, this improves
22201 // throughput and reduces register pressure.
22203 if (CC == X86::COND_NE) {
22205 X86::CondCode CC0, CC1;
22207 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22209 std::swap(FalseOp, TrueOp);
22210 CC0 = X86::GetOppositeBranchCondition(CC0);
22211 CC1 = X86::GetOppositeBranchCondition(CC1);
22214 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22216 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22217 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22218 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22219 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22227 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22228 const X86Subtarget *Subtarget) {
22229 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22231 default: return SDValue();
22232 // SSE/AVX/AVX2 blend intrinsics.
22233 case Intrinsic::x86_avx2_pblendvb:
22234 // Don't try to simplify this intrinsic if we don't have AVX2.
22235 if (!Subtarget->hasAVX2())
22238 case Intrinsic::x86_avx_blendv_pd_256:
22239 case Intrinsic::x86_avx_blendv_ps_256:
22240 // Don't try to simplify this intrinsic if we don't have AVX.
22241 if (!Subtarget->hasAVX())
22244 case Intrinsic::x86_sse41_blendvps:
22245 case Intrinsic::x86_sse41_blendvpd:
22246 case Intrinsic::x86_sse41_pblendvb: {
22247 SDValue Op0 = N->getOperand(1);
22248 SDValue Op1 = N->getOperand(2);
22249 SDValue Mask = N->getOperand(3);
22251 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22252 if (!Subtarget->hasSSE41())
22255 // fold (blend A, A, Mask) -> A
22258 // fold (blend A, B, allZeros) -> A
22259 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22261 // fold (blend A, B, allOnes) -> B
22262 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22265 // Simplify the case where the mask is a constant i32 value.
22266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22267 if (C->isNullValue())
22269 if (C->isAllOnesValue())
22276 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22277 case Intrinsic::x86_sse2_psrai_w:
22278 case Intrinsic::x86_sse2_psrai_d:
22279 case Intrinsic::x86_avx2_psrai_w:
22280 case Intrinsic::x86_avx2_psrai_d:
22281 case Intrinsic::x86_sse2_psra_w:
22282 case Intrinsic::x86_sse2_psra_d:
22283 case Intrinsic::x86_avx2_psra_w:
22284 case Intrinsic::x86_avx2_psra_d: {
22285 SDValue Op0 = N->getOperand(1);
22286 SDValue Op1 = N->getOperand(2);
22287 EVT VT = Op0.getValueType();
22288 assert(VT.isVector() && "Expected a vector type!");
22290 if (isa<BuildVectorSDNode>(Op1))
22291 Op1 = Op1.getOperand(0);
22293 if (!isa<ConstantSDNode>(Op1))
22296 EVT SVT = VT.getVectorElementType();
22297 unsigned SVTBits = SVT.getSizeInBits();
22299 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22300 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22301 uint64_t ShAmt = C.getZExtValue();
22303 // Don't try to convert this shift into a ISD::SRA if the shift
22304 // count is bigger than or equal to the element size.
22305 if (ShAmt >= SVTBits)
22308 // Trivial case: if the shift count is zero, then fold this
22309 // into the first operand.
22313 // Replace this packed shift intrinsic with a target independent
22316 SDValue Splat = DAG.getConstant(C, DL, VT);
22317 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22322 /// PerformMulCombine - Optimize a single multiply with constant into two
22323 /// in order to implement it with two cheaper instructions, e.g.
22324 /// LEA + SHL, LEA + LEA.
22325 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22326 TargetLowering::DAGCombinerInfo &DCI) {
22327 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22330 EVT VT = N->getValueType(0);
22331 if (VT != MVT::i64 && VT != MVT::i32)
22334 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22337 uint64_t MulAmt = C->getZExtValue();
22338 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22341 uint64_t MulAmt1 = 0;
22342 uint64_t MulAmt2 = 0;
22343 if ((MulAmt % 9) == 0) {
22345 MulAmt2 = MulAmt / 9;
22346 } else if ((MulAmt % 5) == 0) {
22348 MulAmt2 = MulAmt / 5;
22349 } else if ((MulAmt % 3) == 0) {
22351 MulAmt2 = MulAmt / 3;
22354 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22357 if (isPowerOf2_64(MulAmt2) &&
22358 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22359 // If second multiplifer is pow2, issue it first. We want the multiply by
22360 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22362 std::swap(MulAmt1, MulAmt2);
22365 if (isPowerOf2_64(MulAmt1))
22366 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22367 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22369 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22370 DAG.getConstant(MulAmt1, DL, VT));
22372 if (isPowerOf2_64(MulAmt2))
22373 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22374 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22376 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22377 DAG.getConstant(MulAmt2, DL, VT));
22379 // Do not add new nodes to DAG combiner worklist.
22380 DCI.CombineTo(N, NewMul, false);
22385 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22386 SDValue N0 = N->getOperand(0);
22387 SDValue N1 = N->getOperand(1);
22388 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22389 EVT VT = N0.getValueType();
22391 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22392 // since the result of setcc_c is all zero's or all ones.
22393 if (VT.isInteger() && !VT.isVector() &&
22394 N1C && N0.getOpcode() == ISD::AND &&
22395 N0.getOperand(1).getOpcode() == ISD::Constant) {
22396 SDValue N00 = N0.getOperand(0);
22397 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22398 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22399 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22400 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22401 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22402 APInt ShAmt = N1C->getAPIntValue();
22403 Mask = Mask.shl(ShAmt);
22406 return DAG.getNode(ISD::AND, DL, VT,
22407 N00, DAG.getConstant(Mask, DL, VT));
22412 // Hardware support for vector shifts is sparse which makes us scalarize the
22413 // vector operations in many cases. Also, on sandybridge ADD is faster than
22415 // (shl V, 1) -> add V,V
22416 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22417 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22418 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22419 // We shift all of the values by one. In many cases we do not have
22420 // hardware support for this operation. This is better expressed as an ADD
22422 if (N1SplatC->getZExtValue() == 1)
22423 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22429 /// \brief Returns a vector of 0s if the node in input is a vector logical
22430 /// shift by a constant amount which is known to be bigger than or equal
22431 /// to the vector element size in bits.
22432 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22433 const X86Subtarget *Subtarget) {
22434 EVT VT = N->getValueType(0);
22436 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22437 (!Subtarget->hasInt256() ||
22438 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22441 SDValue Amt = N->getOperand(1);
22443 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22444 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22445 APInt ShiftAmt = AmtSplat->getAPIntValue();
22446 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22448 // SSE2/AVX2 logical shifts always return a vector of 0s
22449 // if the shift amount is bigger than or equal to
22450 // the element size. The constant shift amount will be
22451 // encoded as a 8-bit immediate.
22452 if (ShiftAmt.trunc(8).uge(MaxAmount))
22453 return getZeroVector(VT, Subtarget, DAG, DL);
22459 /// PerformShiftCombine - Combine shifts.
22460 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22461 TargetLowering::DAGCombinerInfo &DCI,
22462 const X86Subtarget *Subtarget) {
22463 if (N->getOpcode() == ISD::SHL) {
22464 SDValue V = PerformSHLCombine(N, DAG);
22465 if (V.getNode()) return V;
22468 if (N->getOpcode() != ISD::SRA) {
22469 // Try to fold this logical shift into a zero vector.
22470 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22471 if (V.getNode()) return V;
22477 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22478 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22479 // and friends. Likewise for OR -> CMPNEQSS.
22480 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22481 TargetLowering::DAGCombinerInfo &DCI,
22482 const X86Subtarget *Subtarget) {
22485 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22486 // we're requiring SSE2 for both.
22487 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22488 SDValue N0 = N->getOperand(0);
22489 SDValue N1 = N->getOperand(1);
22490 SDValue CMP0 = N0->getOperand(1);
22491 SDValue CMP1 = N1->getOperand(1);
22494 // The SETCCs should both refer to the same CMP.
22495 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22498 SDValue CMP00 = CMP0->getOperand(0);
22499 SDValue CMP01 = CMP0->getOperand(1);
22500 EVT VT = CMP00.getValueType();
22502 if (VT == MVT::f32 || VT == MVT::f64) {
22503 bool ExpectingFlags = false;
22504 // Check for any users that want flags:
22505 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22506 !ExpectingFlags && UI != UE; ++UI)
22507 switch (UI->getOpcode()) {
22512 ExpectingFlags = true;
22514 case ISD::CopyToReg:
22515 case ISD::SIGN_EXTEND:
22516 case ISD::ZERO_EXTEND:
22517 case ISD::ANY_EXTEND:
22521 if (!ExpectingFlags) {
22522 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22523 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22525 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22526 X86::CondCode tmp = cc0;
22531 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22532 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22533 // FIXME: need symbolic constants for these magic numbers.
22534 // See X86ATTInstPrinter.cpp:printSSECC().
22535 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22536 if (Subtarget->hasAVX512()) {
22537 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22539 DAG.getConstant(x86cc, DL, MVT::i8));
22540 if (N->getValueType(0) != MVT::i1)
22541 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22545 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22546 CMP00.getValueType(), CMP00, CMP01,
22547 DAG.getConstant(x86cc, DL,
22550 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22551 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22553 if (is64BitFP && !Subtarget->is64Bit()) {
22554 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22555 // 64-bit integer, since that's not a legal type. Since
22556 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22557 // bits, but can do this little dance to extract the lowest 32 bits
22558 // and work with those going forward.
22559 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22561 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22563 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22564 Vector32, DAG.getIntPtrConstant(0, DL));
22568 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
22570 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22571 DAG.getConstant(1, DL, IntVT));
22572 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22574 return OneBitOfTruth;
22582 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22583 /// so it can be folded inside ANDNP.
22584 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22585 EVT VT = N->getValueType(0);
22587 // Match direct AllOnes for 128 and 256-bit vectors
22588 if (ISD::isBuildVectorAllOnes(N))
22591 // Look through a bit convert.
22592 if (N->getOpcode() == ISD::BITCAST)
22593 N = N->getOperand(0).getNode();
22595 // Sometimes the operand may come from a insert_subvector building a 256-bit
22597 if (VT.is256BitVector() &&
22598 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22599 SDValue V1 = N->getOperand(0);
22600 SDValue V2 = N->getOperand(1);
22602 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22603 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22604 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22605 ISD::isBuildVectorAllOnes(V2.getNode()))
22612 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22613 // register. In most cases we actually compare or select YMM-sized registers
22614 // and mixing the two types creates horrible code. This method optimizes
22615 // some of the transition sequences.
22616 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22617 TargetLowering::DAGCombinerInfo &DCI,
22618 const X86Subtarget *Subtarget) {
22619 EVT VT = N->getValueType(0);
22620 if (!VT.is256BitVector())
22623 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22624 N->getOpcode() == ISD::ZERO_EXTEND ||
22625 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22627 SDValue Narrow = N->getOperand(0);
22628 EVT NarrowVT = Narrow->getValueType(0);
22629 if (!NarrowVT.is128BitVector())
22632 if (Narrow->getOpcode() != ISD::XOR &&
22633 Narrow->getOpcode() != ISD::AND &&
22634 Narrow->getOpcode() != ISD::OR)
22637 SDValue N0 = Narrow->getOperand(0);
22638 SDValue N1 = Narrow->getOperand(1);
22641 // The Left side has to be a trunc.
22642 if (N0.getOpcode() != ISD::TRUNCATE)
22645 // The type of the truncated inputs.
22646 EVT WideVT = N0->getOperand(0)->getValueType(0);
22650 // The right side has to be a 'trunc' or a constant vector.
22651 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22652 ConstantSDNode *RHSConstSplat = nullptr;
22653 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22654 RHSConstSplat = RHSBV->getConstantSplatNode();
22655 if (!RHSTrunc && !RHSConstSplat)
22658 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22660 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22663 // Set N0 and N1 to hold the inputs to the new wide operation.
22664 N0 = N0->getOperand(0);
22665 if (RHSConstSplat) {
22666 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22667 SDValue(RHSConstSplat, 0));
22668 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22669 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22670 } else if (RHSTrunc) {
22671 N1 = N1->getOperand(0);
22674 // Generate the wide operation.
22675 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22676 unsigned Opcode = N->getOpcode();
22678 case ISD::ANY_EXTEND:
22680 case ISD::ZERO_EXTEND: {
22681 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22682 APInt Mask = APInt::getAllOnesValue(InBits);
22683 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22684 return DAG.getNode(ISD::AND, DL, VT,
22685 Op, DAG.getConstant(Mask, DL, VT));
22687 case ISD::SIGN_EXTEND:
22688 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22689 Op, DAG.getValueType(NarrowVT));
22691 llvm_unreachable("Unexpected opcode");
22695 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22696 TargetLowering::DAGCombinerInfo &DCI,
22697 const X86Subtarget *Subtarget) {
22698 SDValue N0 = N->getOperand(0);
22699 SDValue N1 = N->getOperand(1);
22702 // A vector zext_in_reg may be represented as a shuffle,
22703 // feeding into a bitcast (this represents anyext) feeding into
22704 // an and with a mask.
22705 // We'd like to try to combine that into a shuffle with zero
22706 // plus a bitcast, removing the and.
22707 if (N0.getOpcode() != ISD::BITCAST ||
22708 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22711 // The other side of the AND should be a splat of 2^C, where C
22712 // is the number of bits in the source type.
22713 if (N1.getOpcode() == ISD::BITCAST)
22714 N1 = N1.getOperand(0);
22715 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22717 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22719 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22720 EVT SrcType = Shuffle->getValueType(0);
22722 // We expect a single-source shuffle
22723 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22726 unsigned SrcSize = SrcType.getScalarSizeInBits();
22728 APInt SplatValue, SplatUndef;
22729 unsigned SplatBitSize;
22731 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22732 SplatBitSize, HasAnyUndefs))
22735 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22736 // Make sure the splat matches the mask we expect
22737 if (SplatBitSize > ResSize ||
22738 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22741 // Make sure the input and output size make sense
22742 if (SrcSize >= ResSize || ResSize % SrcSize)
22745 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22746 // The number of u's between each two values depends on the ratio between
22747 // the source and dest type.
22748 unsigned ZextRatio = ResSize / SrcSize;
22749 bool IsZext = true;
22750 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22751 if (i % ZextRatio) {
22752 if (Shuffle->getMaskElt(i) > 0) {
22758 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22759 // Expected element number
22769 // Ok, perform the transformation - replace the shuffle with
22770 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22771 // (instead of undef) where the k elements come from the zero vector.
22772 SmallVector<int, 8> Mask;
22773 unsigned NumElems = SrcType.getVectorNumElements();
22774 for (unsigned i = 0; i < NumElems; ++i)
22776 Mask.push_back(NumElems);
22778 Mask.push_back(i / ZextRatio);
22780 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22781 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
22782 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22785 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22786 TargetLowering::DAGCombinerInfo &DCI,
22787 const X86Subtarget *Subtarget) {
22788 if (DCI.isBeforeLegalizeOps())
22791 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22794 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22797 EVT VT = N->getValueType(0);
22798 SDValue N0 = N->getOperand(0);
22799 SDValue N1 = N->getOperand(1);
22802 // Create BEXTR instructions
22803 // BEXTR is ((X >> imm) & (2**size-1))
22804 if (VT == MVT::i32 || VT == MVT::i64) {
22805 // Check for BEXTR.
22806 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22807 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22808 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22809 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22810 if (MaskNode && ShiftNode) {
22811 uint64_t Mask = MaskNode->getZExtValue();
22812 uint64_t Shift = ShiftNode->getZExtValue();
22813 if (isMask_64(Mask)) {
22814 uint64_t MaskSize = countPopulation(Mask);
22815 if (Shift + MaskSize <= VT.getSizeInBits())
22816 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22817 DAG.getConstant(Shift | (MaskSize << 8), DL,
22826 // Want to form ANDNP nodes:
22827 // 1) In the hopes of then easily combining them with OR and AND nodes
22828 // to form PBLEND/PSIGN.
22829 // 2) To match ANDN packed intrinsics
22830 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22833 // Check LHS for vnot
22834 if (N0.getOpcode() == ISD::XOR &&
22835 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22836 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22837 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22839 // Check RHS for vnot
22840 if (N1.getOpcode() == ISD::XOR &&
22841 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22842 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22843 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22848 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22849 TargetLowering::DAGCombinerInfo &DCI,
22850 const X86Subtarget *Subtarget) {
22851 if (DCI.isBeforeLegalizeOps())
22854 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22858 SDValue N0 = N->getOperand(0);
22859 SDValue N1 = N->getOperand(1);
22860 EVT VT = N->getValueType(0);
22862 // look for psign/blend
22863 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22864 if (!Subtarget->hasSSSE3() ||
22865 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22868 // Canonicalize pandn to RHS
22869 if (N0.getOpcode() == X86ISD::ANDNP)
22871 // or (and (m, y), (pandn m, x))
22872 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22873 SDValue Mask = N1.getOperand(0);
22874 SDValue X = N1.getOperand(1);
22876 if (N0.getOperand(0) == Mask)
22877 Y = N0.getOperand(1);
22878 if (N0.getOperand(1) == Mask)
22879 Y = N0.getOperand(0);
22881 // Check to see if the mask appeared in both the AND and ANDNP and
22885 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22886 // Look through mask bitcast.
22887 if (Mask.getOpcode() == ISD::BITCAST)
22888 Mask = Mask.getOperand(0);
22889 if (X.getOpcode() == ISD::BITCAST)
22890 X = X.getOperand(0);
22891 if (Y.getOpcode() == ISD::BITCAST)
22892 Y = Y.getOperand(0);
22894 EVT MaskVT = Mask.getValueType();
22896 // Validate that the Mask operand is a vector sra node.
22897 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22898 // there is no psrai.b
22899 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22900 unsigned SraAmt = ~0;
22901 if (Mask.getOpcode() == ISD::SRA) {
22902 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22903 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22904 SraAmt = AmtConst->getZExtValue();
22905 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22906 SDValue SraC = Mask.getOperand(1);
22907 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22909 if ((SraAmt + 1) != EltBits)
22914 // Now we know we at least have a plendvb with the mask val. See if
22915 // we can form a psignb/w/d.
22916 // psign = x.type == y.type == mask.type && y = sub(0, x);
22917 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22918 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22919 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22920 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22921 "Unsupported VT for PSIGN");
22922 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22923 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22925 // PBLENDVB only available on SSE 4.1
22926 if (!Subtarget->hasSSE41())
22929 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22931 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22932 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22933 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22934 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22935 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22939 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22942 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22943 MachineFunction &MF = DAG.getMachineFunction();
22945 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22947 // SHLD/SHRD instructions have lower register pressure, but on some
22948 // platforms they have higher latency than the equivalent
22949 // series of shifts/or that would otherwise be generated.
22950 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22951 // have higher latencies and we are not optimizing for size.
22952 if (!OptForSize && Subtarget->isSHLDSlow())
22955 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22957 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22959 if (!N0.hasOneUse() || !N1.hasOneUse())
22962 SDValue ShAmt0 = N0.getOperand(1);
22963 if (ShAmt0.getValueType() != MVT::i8)
22965 SDValue ShAmt1 = N1.getOperand(1);
22966 if (ShAmt1.getValueType() != MVT::i8)
22968 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22969 ShAmt0 = ShAmt0.getOperand(0);
22970 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22971 ShAmt1 = ShAmt1.getOperand(0);
22974 unsigned Opc = X86ISD::SHLD;
22975 SDValue Op0 = N0.getOperand(0);
22976 SDValue Op1 = N1.getOperand(0);
22977 if (ShAmt0.getOpcode() == ISD::SUB) {
22978 Opc = X86ISD::SHRD;
22979 std::swap(Op0, Op1);
22980 std::swap(ShAmt0, ShAmt1);
22983 unsigned Bits = VT.getSizeInBits();
22984 if (ShAmt1.getOpcode() == ISD::SUB) {
22985 SDValue Sum = ShAmt1.getOperand(0);
22986 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22987 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22988 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22989 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22990 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22991 return DAG.getNode(Opc, DL, VT,
22993 DAG.getNode(ISD::TRUNCATE, DL,
22996 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22997 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22999 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23000 return DAG.getNode(Opc, DL, VT,
23001 N0.getOperand(0), N1.getOperand(0),
23002 DAG.getNode(ISD::TRUNCATE, DL,
23009 // Generate NEG and CMOV for integer abs.
23010 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23011 EVT VT = N->getValueType(0);
23013 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23014 // 8-bit integer abs to NEG and CMOV.
23015 if (VT.isInteger() && VT.getSizeInBits() == 8)
23018 SDValue N0 = N->getOperand(0);
23019 SDValue N1 = N->getOperand(1);
23022 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23023 // and change it to SUB and CMOV.
23024 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23025 N0.getOpcode() == ISD::ADD &&
23026 N0.getOperand(1) == N1 &&
23027 N1.getOpcode() == ISD::SRA &&
23028 N1.getOperand(0) == N0.getOperand(0))
23029 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23030 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23031 // Generate SUB & CMOV.
23032 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23033 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23035 SDValue Ops[] = { N0.getOperand(0), Neg,
23036 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23037 SDValue(Neg.getNode(), 1) };
23038 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23043 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23044 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23045 TargetLowering::DAGCombinerInfo &DCI,
23046 const X86Subtarget *Subtarget) {
23047 if (DCI.isBeforeLegalizeOps())
23050 if (Subtarget->hasCMov()) {
23051 SDValue RV = performIntegerAbsCombine(N, DAG);
23059 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23060 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23061 TargetLowering::DAGCombinerInfo &DCI,
23062 const X86Subtarget *Subtarget) {
23063 LoadSDNode *Ld = cast<LoadSDNode>(N);
23064 EVT RegVT = Ld->getValueType(0);
23065 EVT MemVT = Ld->getMemoryVT();
23067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23069 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23070 // into two 16-byte operations.
23071 ISD::LoadExtType Ext = Ld->getExtensionType();
23072 unsigned Alignment = Ld->getAlignment();
23073 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23074 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23075 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23076 unsigned NumElems = RegVT.getVectorNumElements();
23080 SDValue Ptr = Ld->getBasePtr();
23081 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23083 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23085 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23086 Ld->getPointerInfo(), Ld->isVolatile(),
23087 Ld->isNonTemporal(), Ld->isInvariant(),
23089 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23090 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23091 Ld->getPointerInfo(), Ld->isVolatile(),
23092 Ld->isNonTemporal(), Ld->isInvariant(),
23093 std::min(16U, Alignment));
23094 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23096 Load2.getValue(1));
23098 SDValue NewVec = DAG.getUNDEF(RegVT);
23099 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23100 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23101 return DCI.CombineTo(N, NewVec, TF, true);
23107 /// PerformMLOADCombine - Resolve extending loads
23108 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23109 TargetLowering::DAGCombinerInfo &DCI,
23110 const X86Subtarget *Subtarget) {
23111 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23112 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23115 EVT VT = Mld->getValueType(0);
23116 unsigned NumElems = VT.getVectorNumElements();
23117 EVT LdVT = Mld->getMemoryVT();
23120 assert(LdVT != VT && "Cannot extend to the same type");
23121 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23122 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23123 // From, To sizes and ElemCount must be pow of two
23124 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23125 "Unexpected size for extending masked load");
23127 unsigned SizeRatio = ToSz / FromSz;
23128 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23130 // Create a type on which we perform the shuffle
23131 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23132 LdVT.getScalarType(), NumElems*SizeRatio);
23133 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23135 // Convert Src0 value
23136 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
23137 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23138 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23139 for (unsigned i = 0; i != NumElems; ++i)
23140 ShuffleVec[i] = i * SizeRatio;
23142 // Can't shuffle using an illegal type.
23143 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23144 && "WideVecVT should be legal");
23145 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23146 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23148 // Prepare the new mask
23150 SDValue Mask = Mld->getMask();
23151 if (Mask.getValueType() == VT) {
23152 // Mask and original value have the same type
23153 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23154 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23155 for (unsigned i = 0; i != NumElems; ++i)
23156 ShuffleVec[i] = i * SizeRatio;
23157 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23158 ShuffleVec[i] = NumElems*SizeRatio;
23159 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23160 DAG.getConstant(0, dl, WideVecVT),
23164 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23165 unsigned WidenNumElts = NumElems*SizeRatio;
23166 unsigned MaskNumElts = VT.getVectorNumElements();
23167 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23170 unsigned NumConcat = WidenNumElts / MaskNumElts;
23171 SmallVector<SDValue, 16> Ops(NumConcat);
23172 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23174 for (unsigned i = 1; i != NumConcat; ++i)
23177 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23180 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23181 Mld->getBasePtr(), NewMask, WideSrc0,
23182 Mld->getMemoryVT(), Mld->getMemOperand(),
23184 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23185 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23188 /// PerformMSTORECombine - Resolve truncating stores
23189 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23190 const X86Subtarget *Subtarget) {
23191 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23192 if (!Mst->isTruncatingStore())
23195 EVT VT = Mst->getValue().getValueType();
23196 unsigned NumElems = VT.getVectorNumElements();
23197 EVT StVT = Mst->getMemoryVT();
23200 assert(StVT != VT && "Cannot truncate to the same type");
23201 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23202 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23204 // From, To sizes and ElemCount must be pow of two
23205 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23206 "Unexpected size for truncating masked store");
23207 // We are going to use the original vector elt for storing.
23208 // Accumulated smaller vector elements must be a multiple of the store size.
23209 assert (((NumElems * FromSz) % ToSz) == 0 &&
23210 "Unexpected ratio for truncating masked store");
23212 unsigned SizeRatio = FromSz / ToSz;
23213 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23215 // Create a type on which we perform the shuffle
23216 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23217 StVT.getScalarType(), NumElems*SizeRatio);
23219 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23221 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
23222 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23223 for (unsigned i = 0; i != NumElems; ++i)
23224 ShuffleVec[i] = i * SizeRatio;
23226 // Can't shuffle using an illegal type.
23227 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23228 && "WideVecVT should be legal");
23230 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23231 DAG.getUNDEF(WideVecVT),
23235 SDValue Mask = Mst->getMask();
23236 if (Mask.getValueType() == VT) {
23237 // Mask and original value have the same type
23238 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23239 for (unsigned i = 0; i != NumElems; ++i)
23240 ShuffleVec[i] = i * SizeRatio;
23241 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23242 ShuffleVec[i] = NumElems*SizeRatio;
23243 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23244 DAG.getConstant(0, dl, WideVecVT),
23248 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23249 unsigned WidenNumElts = NumElems*SizeRatio;
23250 unsigned MaskNumElts = VT.getVectorNumElements();
23251 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23254 unsigned NumConcat = WidenNumElts / MaskNumElts;
23255 SmallVector<SDValue, 16> Ops(NumConcat);
23256 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23258 for (unsigned i = 1; i != NumConcat; ++i)
23261 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23264 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23265 NewMask, StVT, Mst->getMemOperand(), false);
23267 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23268 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23269 const X86Subtarget *Subtarget) {
23270 StoreSDNode *St = cast<StoreSDNode>(N);
23271 EVT VT = St->getValue().getValueType();
23272 EVT StVT = St->getMemoryVT();
23274 SDValue StoredVal = St->getOperand(1);
23275 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23277 // If we are saving a concatenation of two XMM registers and 32-byte stores
23278 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23279 unsigned Alignment = St->getAlignment();
23280 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23281 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23282 StVT == VT && !IsAligned) {
23283 unsigned NumElems = VT.getVectorNumElements();
23287 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23288 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23290 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23291 SDValue Ptr0 = St->getBasePtr();
23292 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23294 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23295 St->getPointerInfo(), St->isVolatile(),
23296 St->isNonTemporal(), Alignment);
23297 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23298 St->getPointerInfo(), St->isVolatile(),
23299 St->isNonTemporal(),
23300 std::min(16U, Alignment));
23301 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23304 // Optimize trunc store (of multiple scalars) to shuffle and store.
23305 // First, pack all of the elements in one place. Next, store to memory
23306 // in fewer chunks.
23307 if (St->isTruncatingStore() && VT.isVector()) {
23308 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23309 unsigned NumElems = VT.getVectorNumElements();
23310 assert(StVT != VT && "Cannot truncate to the same type");
23311 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23312 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23314 // From, To sizes and ElemCount must be pow of two
23315 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23316 // We are going to use the original vector elt for storing.
23317 // Accumulated smaller vector elements must be a multiple of the store size.
23318 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23320 unsigned SizeRatio = FromSz / ToSz;
23322 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23324 // Create a type on which we perform the shuffle
23325 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23326 StVT.getScalarType(), NumElems*SizeRatio);
23328 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23330 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23331 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23332 for (unsigned i = 0; i != NumElems; ++i)
23333 ShuffleVec[i] = i * SizeRatio;
23335 // Can't shuffle using an illegal type.
23336 if (!TLI.isTypeLegal(WideVecVT))
23339 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23340 DAG.getUNDEF(WideVecVT),
23342 // At this point all of the data is stored at the bottom of the
23343 // register. We now need to save it to mem.
23345 // Find the largest store unit
23346 MVT StoreType = MVT::i8;
23347 for (MVT Tp : MVT::integer_valuetypes()) {
23348 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23352 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23353 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23354 (64 <= NumElems * ToSz))
23355 StoreType = MVT::f64;
23357 // Bitcast the original vector into a vector of store-size units
23358 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23359 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23360 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23361 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23362 SmallVector<SDValue, 8> Chains;
23363 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23364 TLI.getPointerTy());
23365 SDValue Ptr = St->getBasePtr();
23367 // Perform one or more big stores into memory.
23368 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23369 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23370 StoreType, ShuffWide,
23371 DAG.getIntPtrConstant(i, dl));
23372 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23373 St->getPointerInfo(), St->isVolatile(),
23374 St->isNonTemporal(), St->getAlignment());
23375 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23376 Chains.push_back(Ch);
23379 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23382 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23383 // the FP state in cases where an emms may be missing.
23384 // A preferable solution to the general problem is to figure out the right
23385 // places to insert EMMS. This qualifies as a quick hack.
23387 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23388 if (VT.getSizeInBits() != 64)
23391 const Function *F = DAG.getMachineFunction().getFunction();
23392 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23394 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23395 if ((VT.isVector() ||
23396 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23397 isa<LoadSDNode>(St->getValue()) &&
23398 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23399 St->getChain().hasOneUse() && !St->isVolatile()) {
23400 SDNode* LdVal = St->getValue().getNode();
23401 LoadSDNode *Ld = nullptr;
23402 int TokenFactorIndex = -1;
23403 SmallVector<SDValue, 8> Ops;
23404 SDNode* ChainVal = St->getChain().getNode();
23405 // Must be a store of a load. We currently handle two cases: the load
23406 // is a direct child, and it's under an intervening TokenFactor. It is
23407 // possible to dig deeper under nested TokenFactors.
23408 if (ChainVal == LdVal)
23409 Ld = cast<LoadSDNode>(St->getChain());
23410 else if (St->getValue().hasOneUse() &&
23411 ChainVal->getOpcode() == ISD::TokenFactor) {
23412 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23413 if (ChainVal->getOperand(i).getNode() == LdVal) {
23414 TokenFactorIndex = i;
23415 Ld = cast<LoadSDNode>(St->getValue());
23417 Ops.push_back(ChainVal->getOperand(i));
23421 if (!Ld || !ISD::isNormalLoad(Ld))
23424 // If this is not the MMX case, i.e. we are just turning i64 load/store
23425 // into f64 load/store, avoid the transformation if there are multiple
23426 // uses of the loaded value.
23427 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23432 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23433 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23435 if (Subtarget->is64Bit() || F64IsLegal) {
23436 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23437 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23438 Ld->getPointerInfo(), Ld->isVolatile(),
23439 Ld->isNonTemporal(), Ld->isInvariant(),
23440 Ld->getAlignment());
23441 SDValue NewChain = NewLd.getValue(1);
23442 if (TokenFactorIndex != -1) {
23443 Ops.push_back(NewChain);
23444 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23446 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23447 St->getPointerInfo(),
23448 St->isVolatile(), St->isNonTemporal(),
23449 St->getAlignment());
23452 // Otherwise, lower to two pairs of 32-bit loads / stores.
23453 SDValue LoAddr = Ld->getBasePtr();
23454 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23455 DAG.getConstant(4, LdDL, MVT::i32));
23457 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23458 Ld->getPointerInfo(),
23459 Ld->isVolatile(), Ld->isNonTemporal(),
23460 Ld->isInvariant(), Ld->getAlignment());
23461 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23462 Ld->getPointerInfo().getWithOffset(4),
23463 Ld->isVolatile(), Ld->isNonTemporal(),
23465 MinAlign(Ld->getAlignment(), 4));
23467 SDValue NewChain = LoLd.getValue(1);
23468 if (TokenFactorIndex != -1) {
23469 Ops.push_back(LoLd);
23470 Ops.push_back(HiLd);
23471 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23474 LoAddr = St->getBasePtr();
23475 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23476 DAG.getConstant(4, StDL, MVT::i32));
23478 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23479 St->getPointerInfo(),
23480 St->isVolatile(), St->isNonTemporal(),
23481 St->getAlignment());
23482 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23483 St->getPointerInfo().getWithOffset(4),
23485 St->isNonTemporal(),
23486 MinAlign(St->getAlignment(), 4));
23487 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23490 // This is similar to the above case, but here we handle a scalar 64-bit
23491 // integer store that is extracted from a vector on a 32-bit target.
23492 // If we have SSE2, then we can treat it like a floating-point double
23493 // to get past legalization. The execution dependencies fixup pass will
23494 // choose the optimal machine instruction for the store if this really is
23495 // an integer or v2f32 rather than an f64.
23496 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23497 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23498 SDValue OldExtract = St->getOperand(1);
23499 SDValue ExtOp0 = OldExtract.getOperand(0);
23500 unsigned VecSize = ExtOp0.getValueSizeInBits();
23501 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23502 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
23503 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23504 BitCast, OldExtract.getOperand(1));
23505 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23506 St->getPointerInfo(), St->isVolatile(),
23507 St->isNonTemporal(), St->getAlignment());
23513 /// Return 'true' if this vector operation is "horizontal"
23514 /// and return the operands for the horizontal operation in LHS and RHS. A
23515 /// horizontal operation performs the binary operation on successive elements
23516 /// of its first operand, then on successive elements of its second operand,
23517 /// returning the resulting values in a vector. For example, if
23518 /// A = < float a0, float a1, float a2, float a3 >
23520 /// B = < float b0, float b1, float b2, float b3 >
23521 /// then the result of doing a horizontal operation on A and B is
23522 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23523 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23524 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23525 /// set to A, RHS to B, and the routine returns 'true'.
23526 /// Note that the binary operation should have the property that if one of the
23527 /// operands is UNDEF then the result is UNDEF.
23528 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23529 // Look for the following pattern: if
23530 // A = < float a0, float a1, float a2, float a3 >
23531 // B = < float b0, float b1, float b2, float b3 >
23533 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23534 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23535 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23536 // which is A horizontal-op B.
23538 // At least one of the operands should be a vector shuffle.
23539 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23540 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23543 MVT VT = LHS.getSimpleValueType();
23545 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23546 "Unsupported vector type for horizontal add/sub");
23548 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23549 // operate independently on 128-bit lanes.
23550 unsigned NumElts = VT.getVectorNumElements();
23551 unsigned NumLanes = VT.getSizeInBits()/128;
23552 unsigned NumLaneElts = NumElts / NumLanes;
23553 assert((NumLaneElts % 2 == 0) &&
23554 "Vector type should have an even number of elements in each lane");
23555 unsigned HalfLaneElts = NumLaneElts/2;
23557 // View LHS in the form
23558 // LHS = VECTOR_SHUFFLE A, B, LMask
23559 // If LHS is not a shuffle then pretend it is the shuffle
23560 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23561 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23564 SmallVector<int, 16> LMask(NumElts);
23565 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23566 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23567 A = LHS.getOperand(0);
23568 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23569 B = LHS.getOperand(1);
23570 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23571 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23573 if (LHS.getOpcode() != ISD::UNDEF)
23575 for (unsigned i = 0; i != NumElts; ++i)
23579 // Likewise, view RHS in the form
23580 // RHS = VECTOR_SHUFFLE C, D, RMask
23582 SmallVector<int, 16> RMask(NumElts);
23583 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23584 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23585 C = RHS.getOperand(0);
23586 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23587 D = RHS.getOperand(1);
23588 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23589 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23591 if (RHS.getOpcode() != ISD::UNDEF)
23593 for (unsigned i = 0; i != NumElts; ++i)
23597 // Check that the shuffles are both shuffling the same vectors.
23598 if (!(A == C && B == D) && !(A == D && B == C))
23601 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23602 if (!A.getNode() && !B.getNode())
23605 // If A and B occur in reverse order in RHS, then "swap" them (which means
23606 // rewriting the mask).
23608 ShuffleVectorSDNode::commuteMask(RMask);
23610 // At this point LHS and RHS are equivalent to
23611 // LHS = VECTOR_SHUFFLE A, B, LMask
23612 // RHS = VECTOR_SHUFFLE A, B, RMask
23613 // Check that the masks correspond to performing a horizontal operation.
23614 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23615 for (unsigned i = 0; i != NumLaneElts; ++i) {
23616 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23618 // Ignore any UNDEF components.
23619 if (LIdx < 0 || RIdx < 0 ||
23620 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23621 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23624 // Check that successive elements are being operated on. If not, this is
23625 // not a horizontal operation.
23626 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23627 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23628 if (!(LIdx == Index && RIdx == Index + 1) &&
23629 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23634 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23635 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23639 /// Do target-specific dag combines on floating point adds.
23640 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23641 const X86Subtarget *Subtarget) {
23642 EVT VT = N->getValueType(0);
23643 SDValue LHS = N->getOperand(0);
23644 SDValue RHS = N->getOperand(1);
23646 // Try to synthesize horizontal adds from adds of shuffles.
23647 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23648 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23649 isHorizontalBinOp(LHS, RHS, true))
23650 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23654 /// Do target-specific dag combines on floating point subs.
23655 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23656 const X86Subtarget *Subtarget) {
23657 EVT VT = N->getValueType(0);
23658 SDValue LHS = N->getOperand(0);
23659 SDValue RHS = N->getOperand(1);
23661 // Try to synthesize horizontal subs from subs of shuffles.
23662 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23663 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23664 isHorizontalBinOp(LHS, RHS, false))
23665 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23669 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23670 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23671 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23673 // F[X]OR(0.0, x) -> x
23674 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23675 if (C->getValueAPF().isPosZero())
23676 return N->getOperand(1);
23678 // F[X]OR(x, 0.0) -> x
23679 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23680 if (C->getValueAPF().isPosZero())
23681 return N->getOperand(0);
23685 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23686 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23687 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23689 // Only perform optimizations if UnsafeMath is used.
23690 if (!DAG.getTarget().Options.UnsafeFPMath)
23693 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23694 // into FMINC and FMAXC, which are Commutative operations.
23695 unsigned NewOp = 0;
23696 switch (N->getOpcode()) {
23697 default: llvm_unreachable("unknown opcode");
23698 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23699 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23702 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23703 N->getOperand(0), N->getOperand(1));
23706 /// Do target-specific dag combines on X86ISD::FAND nodes.
23707 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23708 // FAND(0.0, x) -> 0.0
23709 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23710 if (C->getValueAPF().isPosZero())
23711 return N->getOperand(0);
23713 // FAND(x, 0.0) -> 0.0
23714 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23715 if (C->getValueAPF().isPosZero())
23716 return N->getOperand(1);
23721 /// Do target-specific dag combines on X86ISD::FANDN nodes
23722 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23723 // FANDN(0.0, x) -> x
23724 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23725 if (C->getValueAPF().isPosZero())
23726 return N->getOperand(1);
23728 // FANDN(x, 0.0) -> 0.0
23729 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23730 if (C->getValueAPF().isPosZero())
23731 return N->getOperand(1);
23736 static SDValue PerformBTCombine(SDNode *N,
23738 TargetLowering::DAGCombinerInfo &DCI) {
23739 // BT ignores high bits in the bit index operand.
23740 SDValue Op1 = N->getOperand(1);
23741 if (Op1.hasOneUse()) {
23742 unsigned BitWidth = Op1.getValueSizeInBits();
23743 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23744 APInt KnownZero, KnownOne;
23745 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23746 !DCI.isBeforeLegalizeOps());
23747 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23748 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23749 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23750 DCI.CommitTargetLoweringOpt(TLO);
23755 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23756 SDValue Op = N->getOperand(0);
23757 if (Op.getOpcode() == ISD::BITCAST)
23758 Op = Op.getOperand(0);
23759 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23760 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23761 VT.getVectorElementType().getSizeInBits() ==
23762 OpVT.getVectorElementType().getSizeInBits()) {
23763 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23768 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23769 const X86Subtarget *Subtarget) {
23770 EVT VT = N->getValueType(0);
23771 if (!VT.isVector())
23774 SDValue N0 = N->getOperand(0);
23775 SDValue N1 = N->getOperand(1);
23776 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23779 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23780 // both SSE and AVX2 since there is no sign-extended shift right
23781 // operation on a vector with 64-bit elements.
23782 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23783 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23784 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23785 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23786 SDValue N00 = N0.getOperand(0);
23788 // EXTLOAD has a better solution on AVX2,
23789 // it may be replaced with X86ISD::VSEXT node.
23790 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23791 if (!ISD::isNormalLoad(N00.getNode()))
23794 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23795 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23797 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23803 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23804 TargetLowering::DAGCombinerInfo &DCI,
23805 const X86Subtarget *Subtarget) {
23806 SDValue N0 = N->getOperand(0);
23807 EVT VT = N->getValueType(0);
23808 EVT SVT = VT.getScalarType();
23809 EVT InVT = N0->getValueType(0);
23810 EVT InSVT = InVT.getScalarType();
23813 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23814 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23815 // This exposes the sext to the sdivrem lowering, so that it directly extends
23816 // from AH (which we otherwise need to do contortions to access).
23817 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23818 InVT == MVT::i8 && VT == MVT::i32) {
23819 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23820 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
23821 N0.getOperand(0), N0.getOperand(1));
23822 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23823 return R.getValue(1);
23826 if (!DCI.isBeforeLegalizeOps()) {
23827 if (N0.getValueType() == MVT::i1) {
23828 SDValue Zero = DAG.getConstant(0, DL, VT);
23830 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
23831 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
23836 if (VT.isVector()) {
23837 auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
23838 EVT InVT = N->getValueType(0);
23839 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
23840 128 / InVT.getScalarSizeInBits());
23841 SmallVector<SDValue, 8> Opnds(128 / InVT.getSizeInBits(),
23842 DAG.getUNDEF(InVT));
23844 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
23847 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
23848 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
23849 if (VT.getSizeInBits() == 128 &&
23850 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
23851 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
23852 SDValue ExOp = ExtendToVec128(DL, N0);
23853 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
23856 // On pre-AVX2 targets, split into 128-bit nodes of
23857 // ISD::SIGN_EXTEND_VECTOR_INREG.
23858 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
23859 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
23860 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
23861 unsigned NumVecs = VT.getSizeInBits() / 128;
23862 unsigned NumSubElts = 128 / SVT.getSizeInBits();
23863 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
23864 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
23866 SmallVector<SDValue, 8> Opnds;
23867 for (unsigned i = 0, Offset = 0; i != NumVecs;
23868 ++i, Offset += NumSubElts) {
23869 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
23870 DAG.getIntPtrConstant(Offset, DL));
23871 SrcVec = ExtendToVec128(DL, SrcVec);
23872 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
23873 Opnds.push_back(SrcVec);
23875 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
23879 if (!Subtarget->hasFp256())
23882 if (VT.isVector() && VT.getSizeInBits() == 256) {
23883 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23891 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23892 const X86Subtarget* Subtarget) {
23894 EVT VT = N->getValueType(0);
23896 // Let legalize expand this if it isn't a legal type yet.
23897 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23900 EVT ScalarVT = VT.getScalarType();
23901 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23902 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23905 SDValue A = N->getOperand(0);
23906 SDValue B = N->getOperand(1);
23907 SDValue C = N->getOperand(2);
23909 bool NegA = (A.getOpcode() == ISD::FNEG);
23910 bool NegB = (B.getOpcode() == ISD::FNEG);
23911 bool NegC = (C.getOpcode() == ISD::FNEG);
23913 // Negative multiplication when NegA xor NegB
23914 bool NegMul = (NegA != NegB);
23916 A = A.getOperand(0);
23918 B = B.getOperand(0);
23920 C = C.getOperand(0);
23924 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23926 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23928 return DAG.getNode(Opcode, dl, VT, A, B, C);
23931 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23932 TargetLowering::DAGCombinerInfo &DCI,
23933 const X86Subtarget *Subtarget) {
23934 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23935 // (and (i32 x86isd::setcc_carry), 1)
23936 // This eliminates the zext. This transformation is necessary because
23937 // ISD::SETCC is always legalized to i8.
23939 SDValue N0 = N->getOperand(0);
23940 EVT VT = N->getValueType(0);
23942 if (N0.getOpcode() == ISD::AND &&
23944 N0.getOperand(0).hasOneUse()) {
23945 SDValue N00 = N0.getOperand(0);
23946 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23947 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23948 if (!C || C->getZExtValue() != 1)
23950 return DAG.getNode(ISD::AND, dl, VT,
23951 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23952 N00.getOperand(0), N00.getOperand(1)),
23953 DAG.getConstant(1, dl, VT));
23957 if (N0.getOpcode() == ISD::TRUNCATE &&
23959 N0.getOperand(0).hasOneUse()) {
23960 SDValue N00 = N0.getOperand(0);
23961 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23962 return DAG.getNode(ISD::AND, dl, VT,
23963 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23964 N00.getOperand(0), N00.getOperand(1)),
23965 DAG.getConstant(1, dl, VT));
23968 if (VT.is256BitVector()) {
23969 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23974 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23975 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23976 // This exposes the zext to the udivrem lowering, so that it directly extends
23977 // from AH (which we otherwise need to do contortions to access).
23978 if (N0.getOpcode() == ISD::UDIVREM &&
23979 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23980 (VT == MVT::i32 || VT == MVT::i64)) {
23981 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23982 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23983 N0.getOperand(0), N0.getOperand(1));
23984 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23985 return R.getValue(1);
23991 // Optimize x == -y --> x+y == 0
23992 // x != -y --> x+y != 0
23993 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23994 const X86Subtarget* Subtarget) {
23995 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23996 SDValue LHS = N->getOperand(0);
23997 SDValue RHS = N->getOperand(1);
23998 EVT VT = N->getValueType(0);
24001 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24003 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24004 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24005 LHS.getOperand(1));
24006 return DAG.getSetCC(DL, N->getValueType(0), addV,
24007 DAG.getConstant(0, DL, addV.getValueType()), CC);
24009 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24011 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24012 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24013 RHS.getOperand(1));
24014 return DAG.getSetCC(DL, N->getValueType(0), addV,
24015 DAG.getConstant(0, DL, addV.getValueType()), CC);
24018 if (VT.getScalarType() == MVT::i1 &&
24019 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24021 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24022 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24023 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24025 if (!IsSEXT0 || !IsVZero1) {
24026 // Swap the operands and update the condition code.
24027 std::swap(LHS, RHS);
24028 CC = ISD::getSetCCSwappedOperands(CC);
24030 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24031 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24032 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24035 if (IsSEXT0 && IsVZero1) {
24036 assert(VT == LHS.getOperand(0).getValueType() &&
24037 "Uexpected operand type");
24038 if (CC == ISD::SETGT)
24039 return DAG.getConstant(0, DL, VT);
24040 if (CC == ISD::SETLE)
24041 return DAG.getConstant(1, DL, VT);
24042 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24043 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24045 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24046 "Unexpected condition code!");
24047 return LHS.getOperand(0);
24054 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24055 SelectionDAG &DAG) {
24057 MVT VT = Load->getSimpleValueType(0);
24058 MVT EVT = VT.getVectorElementType();
24059 SDValue Addr = Load->getOperand(1);
24060 SDValue NewAddr = DAG.getNode(
24061 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24062 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24063 Addr.getSimpleValueType()));
24066 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24067 DAG.getMachineFunction().getMachineMemOperand(
24068 Load->getMemOperand(), 0, EVT.getStoreSize()));
24072 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24073 const X86Subtarget *Subtarget) {
24075 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24076 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24077 "X86insertps is only defined for v4x32");
24079 SDValue Ld = N->getOperand(1);
24080 if (MayFoldLoad(Ld)) {
24081 // Extract the countS bits from the immediate so we can get the proper
24082 // address when narrowing the vector load to a specific element.
24083 // When the second source op is a memory address, insertps doesn't use
24084 // countS and just gets an f32 from that address.
24085 unsigned DestIndex =
24086 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24088 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24090 // Create this as a scalar to vector to match the instruction pattern.
24091 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24092 // countS bits are ignored when loading from memory on insertps, which
24093 // means we don't need to explicitly set them to 0.
24094 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24095 LoadScalarToVector, N->getOperand(2));
24100 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24101 SDValue V0 = N->getOperand(0);
24102 SDValue V1 = N->getOperand(1);
24104 EVT VT = N->getValueType(0);
24106 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24107 // operands and changing the mask to 1. This saves us a bunch of
24108 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24109 // x86InstrInfo knows how to commute this back after instruction selection
24110 // if it would help register allocation.
24112 // TODO: If optimizing for size or a processor that doesn't suffer from
24113 // partial register update stalls, this should be transformed into a MOVSD
24114 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24116 if (VT == MVT::v2f64)
24117 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24118 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24119 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24120 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24126 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24127 // as "sbb reg,reg", since it can be extended without zext and produces
24128 // an all-ones bit which is more useful than 0/1 in some cases.
24129 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24132 return DAG.getNode(ISD::AND, DL, VT,
24133 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24134 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24136 DAG.getConstant(1, DL, VT));
24137 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24138 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24139 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24140 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24144 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24145 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24146 TargetLowering::DAGCombinerInfo &DCI,
24147 const X86Subtarget *Subtarget) {
24149 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24150 SDValue EFLAGS = N->getOperand(1);
24152 if (CC == X86::COND_A) {
24153 // Try to convert COND_A into COND_B in an attempt to facilitate
24154 // materializing "setb reg".
24156 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24157 // cannot take an immediate as its first operand.
24159 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24160 EFLAGS.getValueType().isInteger() &&
24161 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24162 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24163 EFLAGS.getNode()->getVTList(),
24164 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24165 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24166 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24170 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24171 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24173 if (CC == X86::COND_B)
24174 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24178 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24179 if (Flags.getNode()) {
24180 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24181 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24187 // Optimize branch condition evaluation.
24189 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24190 TargetLowering::DAGCombinerInfo &DCI,
24191 const X86Subtarget *Subtarget) {
24193 SDValue Chain = N->getOperand(0);
24194 SDValue Dest = N->getOperand(1);
24195 SDValue EFLAGS = N->getOperand(3);
24196 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24200 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24201 if (Flags.getNode()) {
24202 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24203 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24210 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24211 SelectionDAG &DAG) {
24212 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24213 // optimize away operation when it's from a constant.
24215 // The general transformation is:
24216 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24217 // AND(VECTOR_CMP(x,y), constant2)
24218 // constant2 = UNARYOP(constant)
24220 // Early exit if this isn't a vector operation, the operand of the
24221 // unary operation isn't a bitwise AND, or if the sizes of the operations
24222 // aren't the same.
24223 EVT VT = N->getValueType(0);
24224 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24225 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24226 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24229 // Now check that the other operand of the AND is a constant. We could
24230 // make the transformation for non-constant splats as well, but it's unclear
24231 // that would be a benefit as it would not eliminate any operations, just
24232 // perform one more step in scalar code before moving to the vector unit.
24233 if (BuildVectorSDNode *BV =
24234 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24235 // Bail out if the vector isn't a constant.
24236 if (!BV->isConstant())
24239 // Everything checks out. Build up the new and improved node.
24241 EVT IntVT = BV->getValueType(0);
24242 // Create a new constant of the appropriate type for the transformed
24244 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24245 // The AND node needs bitcasts to/from an integer vector type around it.
24246 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24247 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24248 N->getOperand(0)->getOperand(0), MaskConst);
24249 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24256 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24257 const X86Subtarget *Subtarget) {
24258 // First try to optimize away the conversion entirely when it's
24259 // conditionally from a constant. Vectors only.
24260 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24261 if (Res != SDValue())
24264 // Now move on to more general possibilities.
24265 SDValue Op0 = N->getOperand(0);
24266 EVT InVT = Op0->getValueType(0);
24268 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24269 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24271 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24272 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24273 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24276 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24277 // a 32-bit target where SSE doesn't support i64->FP operations.
24278 if (Op0.getOpcode() == ISD::LOAD) {
24279 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24280 EVT VT = Ld->getValueType(0);
24282 // This transformation is not supported if the result type is f16
24283 if (N->getValueType(0) == MVT::f16)
24286 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24287 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24288 !Subtarget->is64Bit() && VT == MVT::i64) {
24289 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24290 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24291 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24298 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24299 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24300 X86TargetLowering::DAGCombinerInfo &DCI) {
24301 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24302 // the result is either zero or one (depending on the input carry bit).
24303 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24304 if (X86::isZeroNode(N->getOperand(0)) &&
24305 X86::isZeroNode(N->getOperand(1)) &&
24306 // We don't have a good way to replace an EFLAGS use, so only do this when
24308 SDValue(N, 1).use_empty()) {
24310 EVT VT = N->getValueType(0);
24311 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24312 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24313 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24314 DAG.getConstant(X86::COND_B, DL,
24317 DAG.getConstant(1, DL, VT));
24318 return DCI.CombineTo(N, Res1, CarryOut);
24324 // fold (add Y, (sete X, 0)) -> adc 0, Y
24325 // (add Y, (setne X, 0)) -> sbb -1, Y
24326 // (sub (sete X, 0), Y) -> sbb 0, Y
24327 // (sub (setne X, 0), Y) -> adc -1, Y
24328 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24331 // Look through ZExts.
24332 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24333 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24336 SDValue SetCC = Ext.getOperand(0);
24337 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24340 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24341 if (CC != X86::COND_E && CC != X86::COND_NE)
24344 SDValue Cmp = SetCC.getOperand(1);
24345 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24346 !X86::isZeroNode(Cmp.getOperand(1)) ||
24347 !Cmp.getOperand(0).getValueType().isInteger())
24350 SDValue CmpOp0 = Cmp.getOperand(0);
24351 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24352 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24354 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24355 if (CC == X86::COND_NE)
24356 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24357 DL, OtherVal.getValueType(), OtherVal,
24358 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24360 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24361 DL, OtherVal.getValueType(), OtherVal,
24362 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24365 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24366 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24367 const X86Subtarget *Subtarget) {
24368 EVT VT = N->getValueType(0);
24369 SDValue Op0 = N->getOperand(0);
24370 SDValue Op1 = N->getOperand(1);
24372 // Try to synthesize horizontal adds from adds of shuffles.
24373 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24374 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24375 isHorizontalBinOp(Op0, Op1, true))
24376 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24378 return OptimizeConditionalInDecrement(N, DAG);
24381 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24382 const X86Subtarget *Subtarget) {
24383 SDValue Op0 = N->getOperand(0);
24384 SDValue Op1 = N->getOperand(1);
24386 // X86 can't encode an immediate LHS of a sub. See if we can push the
24387 // negation into a preceding instruction.
24388 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24389 // If the RHS of the sub is a XOR with one use and a constant, invert the
24390 // immediate. Then add one to the LHS of the sub so we can turn
24391 // X-Y -> X+~Y+1, saving one register.
24392 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24393 isa<ConstantSDNode>(Op1.getOperand(1))) {
24394 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24395 EVT VT = Op0.getValueType();
24396 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24398 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24399 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24400 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24404 // Try to synthesize horizontal adds from adds of shuffles.
24405 EVT VT = N->getValueType(0);
24406 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24407 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24408 isHorizontalBinOp(Op0, Op1, true))
24409 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24411 return OptimizeConditionalInDecrement(N, DAG);
24414 /// performVZEXTCombine - Performs build vector combines
24415 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24416 TargetLowering::DAGCombinerInfo &DCI,
24417 const X86Subtarget *Subtarget) {
24419 MVT VT = N->getSimpleValueType(0);
24420 SDValue Op = N->getOperand(0);
24421 MVT OpVT = Op.getSimpleValueType();
24422 MVT OpEltVT = OpVT.getVectorElementType();
24423 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24425 // (vzext (bitcast (vzext (x)) -> (vzext x)
24427 while (V.getOpcode() == ISD::BITCAST)
24428 V = V.getOperand(0);
24430 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24431 MVT InnerVT = V.getSimpleValueType();
24432 MVT InnerEltVT = InnerVT.getVectorElementType();
24434 // If the element sizes match exactly, we can just do one larger vzext. This
24435 // is always an exact type match as vzext operates on integer types.
24436 if (OpEltVT == InnerEltVT) {
24437 assert(OpVT == InnerVT && "Types must match for vzext!");
24438 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24441 // The only other way we can combine them is if only a single element of the
24442 // inner vzext is used in the input to the outer vzext.
24443 if (InnerEltVT.getSizeInBits() < InputBits)
24446 // In this case, the inner vzext is completely dead because we're going to
24447 // only look at bits inside of the low element. Just do the outer vzext on
24448 // a bitcast of the input to the inner.
24449 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24450 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24453 // Check if we can bypass extracting and re-inserting an element of an input
24454 // vector. Essentialy:
24455 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24456 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24457 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24458 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24459 SDValue ExtractedV = V.getOperand(0);
24460 SDValue OrigV = ExtractedV.getOperand(0);
24461 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24462 if (ExtractIdx->getZExtValue() == 0) {
24463 MVT OrigVT = OrigV.getSimpleValueType();
24464 // Extract a subvector if necessary...
24465 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24466 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24467 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24468 OrigVT.getVectorNumElements() / Ratio);
24469 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24470 DAG.getIntPtrConstant(0, DL));
24472 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24473 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24480 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24481 DAGCombinerInfo &DCI) const {
24482 SelectionDAG &DAG = DCI.DAG;
24483 switch (N->getOpcode()) {
24485 case ISD::EXTRACT_VECTOR_ELT:
24486 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24489 case X86ISD::SHRUNKBLEND:
24490 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24491 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24492 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24493 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24494 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24495 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24496 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24499 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24500 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24501 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24502 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24503 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24504 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24505 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24506 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24507 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24508 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24509 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24511 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24513 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24514 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24515 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24516 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24517 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24518 case ISD::ANY_EXTEND:
24519 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24520 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24521 case ISD::SIGN_EXTEND_INREG:
24522 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24523 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24524 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24525 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24526 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24527 case X86ISD::SHUFP: // Handle all target specific shuffles
24528 case X86ISD::PALIGNR:
24529 case X86ISD::UNPCKH:
24530 case X86ISD::UNPCKL:
24531 case X86ISD::MOVHLPS:
24532 case X86ISD::MOVLHPS:
24533 case X86ISD::PSHUFB:
24534 case X86ISD::PSHUFD:
24535 case X86ISD::PSHUFHW:
24536 case X86ISD::PSHUFLW:
24537 case X86ISD::MOVSS:
24538 case X86ISD::MOVSD:
24539 case X86ISD::VPERMILPI:
24540 case X86ISD::VPERM2X128:
24541 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24542 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24543 case ISD::INTRINSIC_WO_CHAIN:
24544 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24545 case X86ISD::INSERTPS: {
24546 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24547 return PerformINSERTPSCombine(N, DAG, Subtarget);
24550 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24556 /// isTypeDesirableForOp - Return true if the target has native support for
24557 /// the specified value type and it is 'desirable' to use the type for the
24558 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24559 /// instruction encodings are longer and some i16 instructions are slow.
24560 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24561 if (!isTypeLegal(VT))
24563 if (VT != MVT::i16)
24570 case ISD::SIGN_EXTEND:
24571 case ISD::ZERO_EXTEND:
24572 case ISD::ANY_EXTEND:
24585 /// IsDesirableToPromoteOp - This method query the target whether it is
24586 /// beneficial for dag combiner to promote the specified node. If true, it
24587 /// should return the desired promotion type by reference.
24588 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24589 EVT VT = Op.getValueType();
24590 if (VT != MVT::i16)
24593 bool Promote = false;
24594 bool Commute = false;
24595 switch (Op.getOpcode()) {
24598 LoadSDNode *LD = cast<LoadSDNode>(Op);
24599 // If the non-extending load has a single use and it's not live out, then it
24600 // might be folded.
24601 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24602 Op.hasOneUse()*/) {
24603 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24604 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24605 // The only case where we'd want to promote LOAD (rather then it being
24606 // promoted as an operand is when it's only use is liveout.
24607 if (UI->getOpcode() != ISD::CopyToReg)
24614 case ISD::SIGN_EXTEND:
24615 case ISD::ZERO_EXTEND:
24616 case ISD::ANY_EXTEND:
24621 SDValue N0 = Op.getOperand(0);
24622 // Look out for (store (shl (load), x)).
24623 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24636 SDValue N0 = Op.getOperand(0);
24637 SDValue N1 = Op.getOperand(1);
24638 if (!Commute && MayFoldLoad(N1))
24640 // Avoid disabling potential load folding opportunities.
24641 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24643 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24653 //===----------------------------------------------------------------------===//
24654 // X86 Inline Assembly Support
24655 //===----------------------------------------------------------------------===//
24657 // Helper to match a string separated by whitespace.
24658 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24659 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24661 for (StringRef Piece : Pieces) {
24662 if (!S.startswith(Piece)) // Check if the piece matches.
24665 S = S.substr(Piece.size());
24666 StringRef::size_type Pos = S.find_first_not_of(" \t");
24667 if (Pos == 0) // We matched a prefix.
24676 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24678 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24679 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24680 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24681 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24683 if (AsmPieces.size() == 3)
24685 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24692 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24693 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24695 std::string AsmStr = IA->getAsmString();
24697 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24698 if (!Ty || Ty->getBitWidth() % 16 != 0)
24701 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24702 SmallVector<StringRef, 4> AsmPieces;
24703 SplitString(AsmStr, AsmPieces, ";\n");
24705 switch (AsmPieces.size()) {
24706 default: return false;
24708 // FIXME: this should verify that we are targeting a 486 or better. If not,
24709 // we will turn this bswap into something that will be lowered to logical
24710 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24711 // lower so don't worry about this.
24713 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24714 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24715 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24716 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24717 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24718 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24719 // No need to check constraints, nothing other than the equivalent of
24720 // "=r,0" would be valid here.
24721 return IntrinsicLowering::LowerToByteSwap(CI);
24724 // rorw $$8, ${0:w} --> llvm.bswap.i16
24725 if (CI->getType()->isIntegerTy(16) &&
24726 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24727 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24728 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24730 const std::string &ConstraintsStr = IA->getConstraintString();
24731 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24732 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24733 if (clobbersFlagRegisters(AsmPieces))
24734 return IntrinsicLowering::LowerToByteSwap(CI);
24738 if (CI->getType()->isIntegerTy(32) &&
24739 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24740 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24741 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24742 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24744 const std::string &ConstraintsStr = IA->getConstraintString();
24745 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24746 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24747 if (clobbersFlagRegisters(AsmPieces))
24748 return IntrinsicLowering::LowerToByteSwap(CI);
24751 if (CI->getType()->isIntegerTy(64)) {
24752 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24753 if (Constraints.size() >= 2 &&
24754 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24755 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24756 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24757 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24758 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24759 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24760 return IntrinsicLowering::LowerToByteSwap(CI);
24768 /// getConstraintType - Given a constraint letter, return the type of
24769 /// constraint it is for this target.
24770 X86TargetLowering::ConstraintType
24771 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24772 if (Constraint.size() == 1) {
24773 switch (Constraint[0]) {
24784 return C_RegisterClass;
24808 return TargetLowering::getConstraintType(Constraint);
24811 /// Examine constraint type and operand type and determine a weight value.
24812 /// This object must already have been set up with the operand type
24813 /// and the current alternative constraint selected.
24814 TargetLowering::ConstraintWeight
24815 X86TargetLowering::getSingleConstraintMatchWeight(
24816 AsmOperandInfo &info, const char *constraint) const {
24817 ConstraintWeight weight = CW_Invalid;
24818 Value *CallOperandVal = info.CallOperandVal;
24819 // If we don't have a value, we can't do a match,
24820 // but allow it at the lowest weight.
24821 if (!CallOperandVal)
24823 Type *type = CallOperandVal->getType();
24824 // Look at the constraint type.
24825 switch (*constraint) {
24827 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24838 if (CallOperandVal->getType()->isIntegerTy())
24839 weight = CW_SpecificReg;
24844 if (type->isFloatingPointTy())
24845 weight = CW_SpecificReg;
24848 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24849 weight = CW_SpecificReg;
24853 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24854 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24855 weight = CW_Register;
24858 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24859 if (C->getZExtValue() <= 31)
24860 weight = CW_Constant;
24864 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24865 if (C->getZExtValue() <= 63)
24866 weight = CW_Constant;
24870 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24871 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24872 weight = CW_Constant;
24876 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24877 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24878 weight = CW_Constant;
24882 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24883 if (C->getZExtValue() <= 3)
24884 weight = CW_Constant;
24888 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24889 if (C->getZExtValue() <= 0xff)
24890 weight = CW_Constant;
24895 if (isa<ConstantFP>(CallOperandVal)) {
24896 weight = CW_Constant;
24900 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24901 if ((C->getSExtValue() >= -0x80000000LL) &&
24902 (C->getSExtValue() <= 0x7fffffffLL))
24903 weight = CW_Constant;
24907 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24908 if (C->getZExtValue() <= 0xffffffff)
24909 weight = CW_Constant;
24916 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24917 /// with another that has more specific requirements based on the type of the
24918 /// corresponding operand.
24919 const char *X86TargetLowering::
24920 LowerXConstraint(EVT ConstraintVT) const {
24921 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24922 // 'f' like normal targets.
24923 if (ConstraintVT.isFloatingPoint()) {
24924 if (Subtarget->hasSSE2())
24926 if (Subtarget->hasSSE1())
24930 return TargetLowering::LowerXConstraint(ConstraintVT);
24933 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24934 /// vector. If it is invalid, don't add anything to Ops.
24935 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24936 std::string &Constraint,
24937 std::vector<SDValue>&Ops,
24938 SelectionDAG &DAG) const {
24941 // Only support length 1 constraints for now.
24942 if (Constraint.length() > 1) return;
24944 char ConstraintLetter = Constraint[0];
24945 switch (ConstraintLetter) {
24948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24949 if (C->getZExtValue() <= 31) {
24950 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24951 Op.getValueType());
24957 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24958 if (C->getZExtValue() <= 63) {
24959 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24960 Op.getValueType());
24966 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24967 if (isInt<8>(C->getSExtValue())) {
24968 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24969 Op.getValueType());
24975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24976 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24977 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24978 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
24979 Op.getValueType());
24985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24986 if (C->getZExtValue() <= 3) {
24987 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24988 Op.getValueType());
24994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24995 if (C->getZExtValue() <= 255) {
24996 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24997 Op.getValueType());
25003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25004 if (C->getZExtValue() <= 127) {
25005 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25006 Op.getValueType());
25012 // 32-bit signed value
25013 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25014 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25015 C->getSExtValue())) {
25016 // Widen to 64 bits here to get it sign extended.
25017 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25020 // FIXME gcc accepts some relocatable values here too, but only in certain
25021 // memory models; it's complicated.
25026 // 32-bit unsigned value
25027 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25028 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25029 C->getZExtValue())) {
25030 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25031 Op.getValueType());
25035 // FIXME gcc accepts some relocatable values here too, but only in certain
25036 // memory models; it's complicated.
25040 // Literal immediates are always ok.
25041 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25042 // Widen to 64 bits here to get it sign extended.
25043 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25047 // In any sort of PIC mode addresses need to be computed at runtime by
25048 // adding in a register or some sort of table lookup. These can't
25049 // be used as immediates.
25050 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25053 // If we are in non-pic codegen mode, we allow the address of a global (with
25054 // an optional displacement) to be used with 'i'.
25055 GlobalAddressSDNode *GA = nullptr;
25056 int64_t Offset = 0;
25058 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25060 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25061 Offset += GA->getOffset();
25063 } else if (Op.getOpcode() == ISD::ADD) {
25064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25065 Offset += C->getZExtValue();
25066 Op = Op.getOperand(0);
25069 } else if (Op.getOpcode() == ISD::SUB) {
25070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25071 Offset += -C->getZExtValue();
25072 Op = Op.getOperand(0);
25077 // Otherwise, this isn't something we can handle, reject it.
25081 const GlobalValue *GV = GA->getGlobal();
25082 // If we require an extra load to get this address, as in PIC mode, we
25083 // can't accept it.
25084 if (isGlobalStubReference(
25085 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25088 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25089 GA->getValueType(0), Offset);
25094 if (Result.getNode()) {
25095 Ops.push_back(Result);
25098 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25101 std::pair<unsigned, const TargetRegisterClass *>
25102 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25103 const std::string &Constraint,
25105 // First, see if this is a constraint that directly corresponds to an LLVM
25107 if (Constraint.size() == 1) {
25108 // GCC Constraint Letters
25109 switch (Constraint[0]) {
25111 // TODO: Slight differences here in allocation order and leaving
25112 // RIP in the class. Do they matter any more here than they do
25113 // in the normal allocation?
25114 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25115 if (Subtarget->is64Bit()) {
25116 if (VT == MVT::i32 || VT == MVT::f32)
25117 return std::make_pair(0U, &X86::GR32RegClass);
25118 if (VT == MVT::i16)
25119 return std::make_pair(0U, &X86::GR16RegClass);
25120 if (VT == MVT::i8 || VT == MVT::i1)
25121 return std::make_pair(0U, &X86::GR8RegClass);
25122 if (VT == MVT::i64 || VT == MVT::f64)
25123 return std::make_pair(0U, &X86::GR64RegClass);
25126 // 32-bit fallthrough
25127 case 'Q': // Q_REGS
25128 if (VT == MVT::i32 || VT == MVT::f32)
25129 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25130 if (VT == MVT::i16)
25131 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25132 if (VT == MVT::i8 || VT == MVT::i1)
25133 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25134 if (VT == MVT::i64)
25135 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25137 case 'r': // GENERAL_REGS
25138 case 'l': // INDEX_REGS
25139 if (VT == MVT::i8 || VT == MVT::i1)
25140 return std::make_pair(0U, &X86::GR8RegClass);
25141 if (VT == MVT::i16)
25142 return std::make_pair(0U, &X86::GR16RegClass);
25143 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25144 return std::make_pair(0U, &X86::GR32RegClass);
25145 return std::make_pair(0U, &X86::GR64RegClass);
25146 case 'R': // LEGACY_REGS
25147 if (VT == MVT::i8 || VT == MVT::i1)
25148 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25149 if (VT == MVT::i16)
25150 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25151 if (VT == MVT::i32 || !Subtarget->is64Bit())
25152 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25153 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25154 case 'f': // FP Stack registers.
25155 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25156 // value to the correct fpstack register class.
25157 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25158 return std::make_pair(0U, &X86::RFP32RegClass);
25159 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25160 return std::make_pair(0U, &X86::RFP64RegClass);
25161 return std::make_pair(0U, &X86::RFP80RegClass);
25162 case 'y': // MMX_REGS if MMX allowed.
25163 if (!Subtarget->hasMMX()) break;
25164 return std::make_pair(0U, &X86::VR64RegClass);
25165 case 'Y': // SSE_REGS if SSE2 allowed
25166 if (!Subtarget->hasSSE2()) break;
25168 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25169 if (!Subtarget->hasSSE1()) break;
25171 switch (VT.SimpleTy) {
25173 // Scalar SSE types.
25176 return std::make_pair(0U, &X86::FR32RegClass);
25179 return std::make_pair(0U, &X86::FR64RegClass);
25187 return std::make_pair(0U, &X86::VR128RegClass);
25195 return std::make_pair(0U, &X86::VR256RegClass);
25200 return std::make_pair(0U, &X86::VR512RegClass);
25206 // Use the default implementation in TargetLowering to convert the register
25207 // constraint into a member of a register class.
25208 std::pair<unsigned, const TargetRegisterClass*> Res;
25209 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25211 // Not found as a standard register?
25213 // Map st(0) -> st(7) -> ST0
25214 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25215 tolower(Constraint[1]) == 's' &&
25216 tolower(Constraint[2]) == 't' &&
25217 Constraint[3] == '(' &&
25218 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25219 Constraint[5] == ')' &&
25220 Constraint[6] == '}') {
25222 Res.first = X86::FP0+Constraint[4]-'0';
25223 Res.second = &X86::RFP80RegClass;
25227 // GCC allows "st(0)" to be called just plain "st".
25228 if (StringRef("{st}").equals_lower(Constraint)) {
25229 Res.first = X86::FP0;
25230 Res.second = &X86::RFP80RegClass;
25235 if (StringRef("{flags}").equals_lower(Constraint)) {
25236 Res.first = X86::EFLAGS;
25237 Res.second = &X86::CCRRegClass;
25241 // 'A' means EAX + EDX.
25242 if (Constraint == "A") {
25243 Res.first = X86::EAX;
25244 Res.second = &X86::GR32_ADRegClass;
25250 // Otherwise, check to see if this is a register class of the wrong value
25251 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25252 // turn into {ax},{dx}.
25253 if (Res.second->hasType(VT))
25254 return Res; // Correct type already, nothing to do.
25256 // All of the single-register GCC register classes map their values onto
25257 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25258 // really want an 8-bit or 32-bit register, map to the appropriate register
25259 // class and return the appropriate register.
25260 if (Res.second == &X86::GR16RegClass) {
25261 if (VT == MVT::i8 || VT == MVT::i1) {
25262 unsigned DestReg = 0;
25263 switch (Res.first) {
25265 case X86::AX: DestReg = X86::AL; break;
25266 case X86::DX: DestReg = X86::DL; break;
25267 case X86::CX: DestReg = X86::CL; break;
25268 case X86::BX: DestReg = X86::BL; break;
25271 Res.first = DestReg;
25272 Res.second = &X86::GR8RegClass;
25274 } else if (VT == MVT::i32 || VT == MVT::f32) {
25275 unsigned DestReg = 0;
25276 switch (Res.first) {
25278 case X86::AX: DestReg = X86::EAX; break;
25279 case X86::DX: DestReg = X86::EDX; break;
25280 case X86::CX: DestReg = X86::ECX; break;
25281 case X86::BX: DestReg = X86::EBX; break;
25282 case X86::SI: DestReg = X86::ESI; break;
25283 case X86::DI: DestReg = X86::EDI; break;
25284 case X86::BP: DestReg = X86::EBP; break;
25285 case X86::SP: DestReg = X86::ESP; break;
25288 Res.first = DestReg;
25289 Res.second = &X86::GR32RegClass;
25291 } else if (VT == MVT::i64 || VT == MVT::f64) {
25292 unsigned DestReg = 0;
25293 switch (Res.first) {
25295 case X86::AX: DestReg = X86::RAX; break;
25296 case X86::DX: DestReg = X86::RDX; break;
25297 case X86::CX: DestReg = X86::RCX; break;
25298 case X86::BX: DestReg = X86::RBX; break;
25299 case X86::SI: DestReg = X86::RSI; break;
25300 case X86::DI: DestReg = X86::RDI; break;
25301 case X86::BP: DestReg = X86::RBP; break;
25302 case X86::SP: DestReg = X86::RSP; break;
25305 Res.first = DestReg;
25306 Res.second = &X86::GR64RegClass;
25309 } else if (Res.second == &X86::FR32RegClass ||
25310 Res.second == &X86::FR64RegClass ||
25311 Res.second == &X86::VR128RegClass ||
25312 Res.second == &X86::VR256RegClass ||
25313 Res.second == &X86::FR32XRegClass ||
25314 Res.second == &X86::FR64XRegClass ||
25315 Res.second == &X86::VR128XRegClass ||
25316 Res.second == &X86::VR256XRegClass ||
25317 Res.second == &X86::VR512RegClass) {
25318 // Handle references to XMM physical registers that got mapped into the
25319 // wrong class. This can happen with constraints like {xmm0} where the
25320 // target independent register mapper will just pick the first match it can
25321 // find, ignoring the required type.
25323 if (VT == MVT::f32 || VT == MVT::i32)
25324 Res.second = &X86::FR32RegClass;
25325 else if (VT == MVT::f64 || VT == MVT::i64)
25326 Res.second = &X86::FR64RegClass;
25327 else if (X86::VR128RegClass.hasType(VT))
25328 Res.second = &X86::VR128RegClass;
25329 else if (X86::VR256RegClass.hasType(VT))
25330 Res.second = &X86::VR256RegClass;
25331 else if (X86::VR512RegClass.hasType(VT))
25332 Res.second = &X86::VR512RegClass;
25338 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25340 // Scaling factors are not free at all.
25341 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25342 // will take 2 allocations in the out of order engine instead of 1
25343 // for plain addressing mode, i.e. inst (reg1).
25345 // vaddps (%rsi,%drx), %ymm0, %ymm1
25346 // Requires two allocations (one for the load, one for the computation)
25348 // vaddps (%rsi), %ymm0, %ymm1
25349 // Requires just 1 allocation, i.e., freeing allocations for other operations
25350 // and having less micro operations to execute.
25352 // For some X86 architectures, this is even worse because for instance for
25353 // stores, the complex addressing mode forces the instruction to use the
25354 // "load" ports instead of the dedicated "store" port.
25355 // E.g., on Haswell:
25356 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25357 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25358 if (isLegalAddressingMode(AM, Ty))
25359 // Scale represents reg2 * scale, thus account for 1
25360 // as soon as we use a second register.
25361 return AM.Scale != 0;
25365 bool X86TargetLowering::isTargetFTOL() const {
25366 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();