1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
184 // For 64-bit since we have so many registers use the ILP scheduler, for
185 // 32-bit code use the register pressure specific scheduling.
186 if (Subtarget->is64Bit())
187 setSchedulingPreference(Sched::ILP);
189 setSchedulingPreference(Sched::RegPressure);
190 setStackPointerRegisterToSaveRestore(X86StackPtr);
192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
193 // Setup Windows compiler runtime calls.
194 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
196 setLibcallName(RTLIB::SREM_I64, "_allrem");
197 setLibcallName(RTLIB::UREM_I64, "_aullrem");
198 setLibcallName(RTLIB::MUL_I64, "_allmul");
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
210 if (Subtarget->isTargetDarwin()) {
211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
212 setUseUnderscoreSetJmp(false);
213 setUseUnderscoreLongJmp(false);
214 } else if (Subtarget->isTargetMingw()) {
215 // MS runtime is weird: it exports _setjmp, but longjmp!
216 setUseUnderscoreSetJmp(true);
217 setUseUnderscoreLongJmp(false);
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(true);
223 // Set up the register classes.
224 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
225 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
226 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
227 if (Subtarget->is64Bit())
228 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232 // We don't accept any truncstore of integer registers.
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
240 // SETOEQ and SETUNE require checking two conditions.
241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
257 } else if (!UseSoftFloat) {
258 // We have an algorithm for SSE2->double, and we turn this into a
259 // 64-bit FILD followed by conditional FADD for other targets.
260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
261 // We have an algorithm for SSE2, and we turn this into a 64-bit
262 // FILD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
272 // SSE has no i16 to fp conversion, only i32
273 if (X86ScalarSSEf32) {
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
275 // f32 and f64 cases are Legal, f80 case is not
276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 // are Legal, f80 is custom lowered.
288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
296 if (X86ScalarSSEf32) {
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
298 // f32 and f64 cases are Legal, f80 case is not
299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
305 // Handle FP_TO_UINT by promoting the destination to a larger signed
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
314 } else if (!UseSoftFloat) {
315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasXMM())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
455 // On X86 and X86-64, atomic operations are lowered to locked instructions.
456 // Locked instructions, in turn, have implicit fence semantics (all memory
457 // operations are flushed before issuing the locked instruction, and they
458 // are not buffered), so we can fold away the common pattern of
459 // fence-atomic-fence.
460 setShouldFoldAtomicFences(true);
462 // Expand certain atomics
463 for (unsigned i = 0, e = 4; i != e; ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
467 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
470 if (!Subtarget->is64Bit()) {
471 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
477 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
478 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
481 if (Subtarget->hasCmpxchg16b()) {
482 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
485 // FIXME - use subtarget debug flags
486 if (!Subtarget->isTargetDarwin() &&
487 !Subtarget->isTargetELF() &&
488 !Subtarget->isTargetCygMing()) {
489 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
492 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
493 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
494 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
495 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
496 if (Subtarget->is64Bit()) {
497 setExceptionPointerRegister(X86::RAX);
498 setExceptionSelectorRegister(X86::RDX);
500 setExceptionPointerRegister(X86::EAX);
501 setExceptionSelectorRegister(X86::EDX);
503 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
504 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
506 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
508 setOperationAction(ISD::TRAP, MVT::Other, Legal);
510 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
511 setOperationAction(ISD::VASTART , MVT::Other, Custom);
512 setOperationAction(ISD::VAEND , MVT::Other, Expand);
513 if (Subtarget->is64Bit()) {
514 setOperationAction(ISD::VAARG , MVT::Other, Custom);
515 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
517 setOperationAction(ISD::VAARG , MVT::Other, Expand);
518 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
521 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
522 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
523 setOperationAction(ISD::DYNAMIC_STACKALLOC,
524 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
525 (Subtarget->isTargetCOFF()
526 && !Subtarget->isTargetEnvMacho()
529 if (!UseSoftFloat && X86ScalarSSEf64) {
530 // f32 and f64 use SSE.
531 // Set up the FP register classes.
532 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
533 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
535 // Use ANDPD to simulate FABS.
536 setOperationAction(ISD::FABS , MVT::f64, Custom);
537 setOperationAction(ISD::FABS , MVT::f32, Custom);
539 // Use XORP to simulate FNEG.
540 setOperationAction(ISD::FNEG , MVT::f64, Custom);
541 setOperationAction(ISD::FNEG , MVT::f32, Custom);
543 // Use ANDPD and ORPD to simulate FCOPYSIGN.
544 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
545 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
547 // Lower this to FGETSIGNx86 plus an AND.
548 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
549 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
551 // We don't support sin/cos/fmod
552 setOperationAction(ISD::FSIN , MVT::f64, Expand);
553 setOperationAction(ISD::FCOS , MVT::f64, Expand);
554 setOperationAction(ISD::FSIN , MVT::f32, Expand);
555 setOperationAction(ISD::FCOS , MVT::f32, Expand);
557 // Expand FP immediates into loads from the stack, except for the special
559 addLegalFPImmediate(APFloat(+0.0)); // xorpd
560 addLegalFPImmediate(APFloat(+0.0f)); // xorps
561 } else if (!UseSoftFloat && X86ScalarSSEf32) {
562 // Use SSE for f32, x87 for f64.
563 // Set up the FP register classes.
564 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
565 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
567 // Use ANDPS to simulate FABS.
568 setOperationAction(ISD::FABS , MVT::f32, Custom);
570 // Use XORP to simulate FNEG.
571 setOperationAction(ISD::FNEG , MVT::f32, Custom);
573 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
575 // Use ANDPS and ORPS to simulate FCOPYSIGN.
576 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
577 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
579 // We don't support sin/cos/fmod
580 setOperationAction(ISD::FSIN , MVT::f32, Expand);
581 setOperationAction(ISD::FCOS , MVT::f32, Expand);
583 // Special cases we handle for FP constants.
584 addLegalFPImmediate(APFloat(+0.0f)); // xorps
585 addLegalFPImmediate(APFloat(+0.0)); // FLD0
586 addLegalFPImmediate(APFloat(+1.0)); // FLD1
587 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
588 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
591 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
592 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
594 } else if (!UseSoftFloat) {
595 // f32 and f64 in x87.
596 // Set up the FP register classes.
597 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
598 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
600 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
601 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
602 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
606 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
607 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
609 addLegalFPImmediate(APFloat(+0.0)); // FLD0
610 addLegalFPImmediate(APFloat(+1.0)); // FLD1
611 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
612 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
613 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
614 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
615 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
616 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
619 // We don't support FMA.
620 setOperationAction(ISD::FMA, MVT::f64, Expand);
621 setOperationAction(ISD::FMA, MVT::f32, Expand);
623 // Long double always uses X87.
625 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
626 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
627 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
629 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
630 addLegalFPImmediate(TmpFlt); // FLD0
632 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
635 APFloat TmpFlt2(+1.0);
636 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
638 addLegalFPImmediate(TmpFlt2); // FLD1
639 TmpFlt2.changeSign();
640 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
644 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
645 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
648 setOperationAction(ISD::FMA, MVT::f80, Expand);
651 // Always use a library call for pow.
652 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
656 setOperationAction(ISD::FLOG, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 // First set operation action for all vector types to either promote
663 // (for widening) or expand (for scalarization). Then we will selectively
664 // turn on ones that can be effectively codegen'd.
665 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
666 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
667 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
668 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
669 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
670 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
671 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
672 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
673 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
676 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
678 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
679 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
685 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
717 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
721 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
722 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
723 setTruncStoreAction((MVT::SimpleValueType)VT,
724 (MVT::SimpleValueType)InnerVT, Expand);
725 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
726 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
727 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
730 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
731 // with -msoft-float, disable use of MMX as well.
732 if (!UseSoftFloat && Subtarget->hasMMX()) {
733 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
734 // No operations on x86mmx supported, everything uses intrinsics.
737 // MMX-sized vectors (other than x86mmx) are expected to be expanded
738 // into smaller operations.
739 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
740 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
741 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
742 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
743 setOperationAction(ISD::AND, MVT::v8i8, Expand);
744 setOperationAction(ISD::AND, MVT::v4i16, Expand);
745 setOperationAction(ISD::AND, MVT::v2i32, Expand);
746 setOperationAction(ISD::AND, MVT::v1i64, Expand);
747 setOperationAction(ISD::OR, MVT::v8i8, Expand);
748 setOperationAction(ISD::OR, MVT::v4i16, Expand);
749 setOperationAction(ISD::OR, MVT::v2i32, Expand);
750 setOperationAction(ISD::OR, MVT::v1i64, Expand);
751 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
752 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
753 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
754 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
756 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
757 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
758 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
759 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
760 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
761 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
762 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
763 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
764 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
765 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
766 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
767 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
769 if (!UseSoftFloat && Subtarget->hasXMM()) {
770 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
772 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
773 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
774 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
775 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
776 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
777 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
778 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
779 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
782 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
783 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
786 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
787 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
789 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
790 // registers cannot be used even for integer operations.
791 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
792 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
793 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
794 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
796 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
797 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
798 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
799 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
800 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
801 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
802 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
803 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
804 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
805 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
806 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
807 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
808 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
809 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
810 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
811 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
813 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
814 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
815 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
816 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
818 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
819 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
820 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
821 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
825 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
826 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
827 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
828 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
830 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
831 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
832 EVT VT = (MVT::SimpleValueType)i;
833 // Do not attempt to custom lower non-power-of-2 vectors
834 if (!isPowerOf2_32(VT.getVectorNumElements()))
836 // Do not attempt to custom lower non-128-bit vectors
837 if (!VT.is128BitVector())
839 setOperationAction(ISD::BUILD_VECTOR,
840 VT.getSimpleVT().SimpleTy, Custom);
841 setOperationAction(ISD::VECTOR_SHUFFLE,
842 VT.getSimpleVT().SimpleTy, Custom);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
844 VT.getSimpleVT().SimpleTy, Custom);
847 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
848 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
849 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
850 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
851 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
854 if (Subtarget->is64Bit()) {
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
859 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
860 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
861 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
864 // Do not attempt to promote non-128-bit vectors
865 if (!VT.is128BitVector())
868 setOperationAction(ISD::AND, SVT, Promote);
869 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
870 setOperationAction(ISD::OR, SVT, Promote);
871 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
872 setOperationAction(ISD::XOR, SVT, Promote);
873 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
874 setOperationAction(ISD::LOAD, SVT, Promote);
875 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
876 setOperationAction(ISD::SELECT, SVT, Promote);
877 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
880 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
882 // Custom lower v2i64 and v2f64 selects.
883 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
884 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
885 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
886 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
888 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
889 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
892 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
893 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
894 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
895 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
896 setOperationAction(ISD::FRINT, MVT::f32, Legal);
897 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
898 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
899 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
900 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
901 setOperationAction(ISD::FRINT, MVT::f64, Legal);
902 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
904 // FIXME: Do we need to handle scalar-to-vector here?
905 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
907 // Can turn SHL into an integer multiply.
908 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
909 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
911 // i8 and i16 vectors are custom , because the source register and source
912 // source memory operand types are not the same width. f32 vectors are
913 // custom since the immediate controlling the insert encodes additional
915 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
916 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
920 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
922 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 if (Subtarget->is64Bit()) {
926 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
927 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
931 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
932 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
933 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
934 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
935 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
937 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
938 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
939 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
941 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
942 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
945 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
946 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
948 if (!UseSoftFloat && Subtarget->hasAVX()) {
949 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
950 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
951 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
952 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
953 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
954 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
956 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
957 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
958 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
960 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
961 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
962 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
963 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
964 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
965 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
967 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
968 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
969 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
970 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
971 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
972 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
974 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
975 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
976 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
978 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
979 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
980 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
981 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
982 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
983 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
985 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
986 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
987 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
988 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
990 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
991 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
992 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
993 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
995 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
996 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
998 setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
999 setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
1000 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
1001 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
1003 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1004 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1005 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1007 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1008 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1009 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1010 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1012 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1013 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1014 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1015 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1017 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1018 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1019 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1020 // Don't lower v32i8 because there is no 128-bit byte mul
1022 // Custom lower several nodes for 256-bit types.
1023 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1024 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1025 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1028 // Extract subvector is special because the value type
1029 // (result) is 128-bit but the source is 256-bit wide.
1030 if (VT.is128BitVector())
1031 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1033 // Do not attempt to custom lower other non-256-bit vectors
1034 if (!VT.is256BitVector())
1037 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1038 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1041 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1042 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1045 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1046 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1047 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1050 // Do not attempt to promote non-256-bit vectors
1051 if (!VT.is256BitVector())
1054 setOperationAction(ISD::AND, SVT, Promote);
1055 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1056 setOperationAction(ISD::OR, SVT, Promote);
1057 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1058 setOperationAction(ISD::XOR, SVT, Promote);
1059 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1060 setOperationAction(ISD::LOAD, SVT, Promote);
1061 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1062 setOperationAction(ISD::SELECT, SVT, Promote);
1063 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1067 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1068 // of this type with custom code.
1069 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1070 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1071 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1074 // We want to custom lower some of our intrinsics.
1075 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1078 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1079 // handle type legalization for these operations here.
1081 // FIXME: We really should do custom legalization for addition and
1082 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1083 // than generic legalization for 64-bit multiplication-with-overflow, though.
1084 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1085 // Add/Sub/Mul with overflow operations are custom lowered.
1087 setOperationAction(ISD::SADDO, VT, Custom);
1088 setOperationAction(ISD::UADDO, VT, Custom);
1089 setOperationAction(ISD::SSUBO, VT, Custom);
1090 setOperationAction(ISD::USUBO, VT, Custom);
1091 setOperationAction(ISD::SMULO, VT, Custom);
1092 setOperationAction(ISD::UMULO, VT, Custom);
1095 // There are no 8-bit 3-address imul/mul instructions
1096 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1097 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1099 if (!Subtarget->is64Bit()) {
1100 // These libcalls are not available in 32-bit.
1101 setLibcallName(RTLIB::SHL_I128, 0);
1102 setLibcallName(RTLIB::SRL_I128, 0);
1103 setLibcallName(RTLIB::SRA_I128, 0);
1106 // We have target-specific dag combine patterns for the following nodes:
1107 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1108 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1109 setTargetDAGCombine(ISD::BUILD_VECTOR);
1110 setTargetDAGCombine(ISD::SELECT);
1111 setTargetDAGCombine(ISD::SHL);
1112 setTargetDAGCombine(ISD::SRA);
1113 setTargetDAGCombine(ISD::SRL);
1114 setTargetDAGCombine(ISD::OR);
1115 setTargetDAGCombine(ISD::AND);
1116 setTargetDAGCombine(ISD::ADD);
1117 setTargetDAGCombine(ISD::SUB);
1118 setTargetDAGCombine(ISD::STORE);
1119 setTargetDAGCombine(ISD::ZERO_EXTEND);
1120 setTargetDAGCombine(ISD::SINT_TO_FP);
1121 if (Subtarget->is64Bit())
1122 setTargetDAGCombine(ISD::MUL);
1124 computeRegisterProperties();
1126 // On Darwin, -Os means optimize for size without hurting performance,
1127 // do not reduce the limit.
1128 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1129 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1130 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1131 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1132 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1133 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1134 setPrefLoopAlignment(16);
1135 benefitFromCodePlacementOpt = true;
1137 setPrefFunctionAlignment(4);
1141 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1146 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1147 /// the desired ByVal argument alignment.
1148 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1151 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1152 if (VTy->getBitWidth() == 128)
1154 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1155 unsigned EltAlign = 0;
1156 getMaxByValAlign(ATy->getElementType(), EltAlign);
1157 if (EltAlign > MaxAlign)
1158 MaxAlign = EltAlign;
1159 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1160 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1161 unsigned EltAlign = 0;
1162 getMaxByValAlign(STy->getElementType(i), EltAlign);
1163 if (EltAlign > MaxAlign)
1164 MaxAlign = EltAlign;
1172 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1173 /// function arguments in the caller parameter area. For X86, aggregates
1174 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1175 /// are at 4-byte boundaries.
1176 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1177 if (Subtarget->is64Bit()) {
1178 // Max of 8 and alignment of type.
1179 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1186 if (Subtarget->hasXMM())
1187 getMaxByValAlign(Ty, Align);
1191 /// getOptimalMemOpType - Returns the target specific optimal type for load
1192 /// and store operations as a result of memset, memcpy, and memmove
1193 /// lowering. If DstAlign is zero that means it's safe to destination
1194 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1195 /// means there isn't a need to check it against alignment requirement,
1196 /// probably because the source does not need to be loaded. If
1197 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1198 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1199 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1200 /// constant so it does not need to be loaded.
1201 /// It returns EVT::Other if the type should be determined using generic
1202 /// target-independent logic.
1204 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1205 unsigned DstAlign, unsigned SrcAlign,
1206 bool NonScalarIntSafe,
1208 MachineFunction &MF) const {
1209 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1210 // linux. This is because the stack realignment code can't handle certain
1211 // cases like PR2962. This should be removed when PR2962 is fixed.
1212 const Function *F = MF.getFunction();
1213 if (NonScalarIntSafe &&
1214 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1216 (Subtarget->isUnalignedMemAccessFast() ||
1217 ((DstAlign == 0 || DstAlign >= 16) &&
1218 (SrcAlign == 0 || SrcAlign >= 16))) &&
1219 Subtarget->getStackAlignment() >= 16) {
1220 if (Subtarget->hasSSE2())
1222 if (Subtarget->hasSSE1())
1224 } else if (!MemcpyStrSrc && Size >= 8 &&
1225 !Subtarget->is64Bit() &&
1226 Subtarget->getStackAlignment() >= 8 &&
1227 Subtarget->hasXMMInt()) {
1228 // Do not use f64 to lower memcpy if source is string constant. It's
1229 // better to use i32 to avoid the loads.
1233 if (Subtarget->is64Bit() && Size >= 8)
1238 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1239 /// current function. The returned value is a member of the
1240 /// MachineJumpTableInfo::JTEntryKind enum.
1241 unsigned X86TargetLowering::getJumpTableEncoding() const {
1242 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1244 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1245 Subtarget->isPICStyleGOT())
1246 return MachineJumpTableInfo::EK_Custom32;
1248 // Otherwise, use the normal jump table encoding heuristics.
1249 return TargetLowering::getJumpTableEncoding();
1253 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1254 const MachineBasicBlock *MBB,
1255 unsigned uid,MCContext &Ctx) const{
1256 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1257 Subtarget->isPICStyleGOT());
1258 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1260 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1261 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1264 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1266 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1267 SelectionDAG &DAG) const {
1268 if (!Subtarget->is64Bit())
1269 // This doesn't have DebugLoc associated with it, but is not really the
1270 // same as a Register.
1271 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1275 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1276 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1278 const MCExpr *X86TargetLowering::
1279 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1280 MCContext &Ctx) const {
1281 // X86-64 uses RIP relative addressing based on the jump table label.
1282 if (Subtarget->isPICStyleRIPRel())
1283 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1285 // Otherwise, the reference is relative to the PIC base.
1286 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1289 // FIXME: Why this routine is here? Move to RegInfo!
1290 std::pair<const TargetRegisterClass*, uint8_t>
1291 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1292 const TargetRegisterClass *RRC = 0;
1294 switch (VT.getSimpleVT().SimpleTy) {
1296 return TargetLowering::findRepresentativeClass(VT);
1297 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1298 RRC = (Subtarget->is64Bit()
1299 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1302 RRC = X86::VR64RegisterClass;
1304 case MVT::f32: case MVT::f64:
1305 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1306 case MVT::v4f32: case MVT::v2f64:
1307 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1309 RRC = X86::VR128RegisterClass;
1312 return std::make_pair(RRC, Cost);
1315 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1316 unsigned &Offset) const {
1317 if (!Subtarget->isTargetLinux())
1320 if (Subtarget->is64Bit()) {
1321 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1323 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1336 //===----------------------------------------------------------------------===//
1337 // Return Value Calling Convention Implementation
1338 //===----------------------------------------------------------------------===//
1340 #include "X86GenCallingConv.inc"
1343 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1344 MachineFunction &MF, bool isVarArg,
1345 const SmallVectorImpl<ISD::OutputArg> &Outs,
1346 LLVMContext &Context) const {
1347 SmallVector<CCValAssign, 16> RVLocs;
1348 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1350 return CCInfo.CheckReturn(Outs, RetCC_X86);
1354 X86TargetLowering::LowerReturn(SDValue Chain,
1355 CallingConv::ID CallConv, bool isVarArg,
1356 const SmallVectorImpl<ISD::OutputArg> &Outs,
1357 const SmallVectorImpl<SDValue> &OutVals,
1358 DebugLoc dl, SelectionDAG &DAG) const {
1359 MachineFunction &MF = DAG.getMachineFunction();
1360 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1362 SmallVector<CCValAssign, 16> RVLocs;
1363 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1364 RVLocs, *DAG.getContext());
1365 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1367 // Add the regs to the liveout set for the function.
1368 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1369 for (unsigned i = 0; i != RVLocs.size(); ++i)
1370 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1371 MRI.addLiveOut(RVLocs[i].getLocReg());
1375 SmallVector<SDValue, 6> RetOps;
1376 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1377 // Operand #1 = Bytes To Pop
1378 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1381 // Copy the result values into the output registers.
1382 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1383 CCValAssign &VA = RVLocs[i];
1384 assert(VA.isRegLoc() && "Can only return in registers!");
1385 SDValue ValToCopy = OutVals[i];
1386 EVT ValVT = ValToCopy.getValueType();
1388 // If this is x86-64, and we disabled SSE, we can't return FP values,
1389 // or SSE or MMX vectors.
1390 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1391 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1392 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1393 report_fatal_error("SSE register return with SSE disabled");
1395 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1396 // llvm-gcc has never done it right and no one has noticed, so this
1397 // should be OK for now.
1398 if (ValVT == MVT::f64 &&
1399 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1400 report_fatal_error("SSE2 register return with SSE2 disabled");
1402 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1403 // the RET instruction and handled by the FP Stackifier.
1404 if (VA.getLocReg() == X86::ST0 ||
1405 VA.getLocReg() == X86::ST1) {
1406 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1407 // change the value to the FP stack register class.
1408 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1409 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1410 RetOps.push_back(ValToCopy);
1411 // Don't emit a copytoreg.
1415 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1416 // which is returned in RAX / RDX.
1417 if (Subtarget->is64Bit()) {
1418 if (ValVT == MVT::x86mmx) {
1419 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1420 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1421 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1423 // If we don't have SSE2 available, convert to v4f32 so the generated
1424 // register is legal.
1425 if (!Subtarget->hasSSE2())
1426 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1431 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1432 Flag = Chain.getValue(1);
1435 // The x86-64 ABI for returning structs by value requires that we copy
1436 // the sret argument into %rax for the return. We saved the argument into
1437 // a virtual register in the entry block, so now we copy the value out
1439 if (Subtarget->is64Bit() &&
1440 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1441 MachineFunction &MF = DAG.getMachineFunction();
1442 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1443 unsigned Reg = FuncInfo->getSRetReturnReg();
1445 "SRetReturnReg should have been set in LowerFormalArguments().");
1446 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1448 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1449 Flag = Chain.getValue(1);
1451 // RAX now acts like a return value.
1452 MRI.addLiveOut(X86::RAX);
1455 RetOps[0] = Chain; // Update chain.
1457 // Add the flag if we have it.
1459 RetOps.push_back(Flag);
1461 return DAG.getNode(X86ISD::RET_FLAG, dl,
1462 MVT::Other, &RetOps[0], RetOps.size());
1465 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1466 if (N->getNumValues() != 1)
1468 if (!N->hasNUsesOfValue(1, 0))
1471 SDNode *Copy = *N->use_begin();
1472 if (Copy->getOpcode() != ISD::CopyToReg &&
1473 Copy->getOpcode() != ISD::FP_EXTEND)
1476 bool HasRet = false;
1477 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1479 if (UI->getOpcode() != X86ISD::RET_FLAG)
1488 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1489 ISD::NodeType ExtendKind) const {
1491 // TODO: Is this also valid on 32-bit?
1492 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1493 ReturnMVT = MVT::i8;
1495 ReturnMVT = MVT::i32;
1497 EVT MinVT = getRegisterType(Context, ReturnMVT);
1498 return VT.bitsLT(MinVT) ? MinVT : VT;
1501 /// LowerCallResult - Lower the result values of a call into the
1502 /// appropriate copies out of appropriate physical registers.
1505 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1506 CallingConv::ID CallConv, bool isVarArg,
1507 const SmallVectorImpl<ISD::InputArg> &Ins,
1508 DebugLoc dl, SelectionDAG &DAG,
1509 SmallVectorImpl<SDValue> &InVals) const {
1511 // Assign locations to each value returned by this call.
1512 SmallVector<CCValAssign, 16> RVLocs;
1513 bool Is64Bit = Subtarget->is64Bit();
1514 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1515 getTargetMachine(), RVLocs, *DAG.getContext());
1516 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1518 // Copy all of the result registers out of their specified physreg.
1519 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1520 CCValAssign &VA = RVLocs[i];
1521 EVT CopyVT = VA.getValVT();
1523 // If this is x86-64, and we disabled SSE, we can't return FP values
1524 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1525 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1526 report_fatal_error("SSE register return with SSE disabled");
1531 // If this is a call to a function that returns an fp value on the floating
1532 // point stack, we must guarantee the the value is popped from the stack, so
1533 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1534 // if the return value is not used. We use the FpPOP_RETVAL instruction
1536 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1537 // If we prefer to use the value in xmm registers, copy it out as f80 and
1538 // use a truncate to move it from fp stack reg to xmm reg.
1539 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1540 SDValue Ops[] = { Chain, InFlag };
1541 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1542 MVT::Other, MVT::Glue, Ops, 2), 1);
1543 Val = Chain.getValue(0);
1545 // Round the f80 to the right size, which also moves it to the appropriate
1547 if (CopyVT != VA.getValVT())
1548 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1549 // This truncation won't change the value.
1550 DAG.getIntPtrConstant(1));
1552 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1553 CopyVT, InFlag).getValue(1);
1554 Val = Chain.getValue(0);
1556 InFlag = Chain.getValue(2);
1557 InVals.push_back(Val);
1564 //===----------------------------------------------------------------------===//
1565 // C & StdCall & Fast Calling Convention implementation
1566 //===----------------------------------------------------------------------===//
1567 // StdCall calling convention seems to be standard for many Windows' API
1568 // routines and around. It differs from C calling convention just a little:
1569 // callee should clean up the stack, not caller. Symbols should be also
1570 // decorated in some fancy way :) It doesn't support any vector arguments.
1571 // For info on fast calling convention see Fast Calling Convention (tail call)
1572 // implementation LowerX86_32FastCCCallTo.
1574 /// CallIsStructReturn - Determines whether a call uses struct return
1576 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1580 return Outs[0].Flags.isSRet();
1583 /// ArgsAreStructReturn - Determines whether a function uses struct
1584 /// return semantics.
1586 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1590 return Ins[0].Flags.isSRet();
1593 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1594 /// by "Src" to address "Dst" with size and alignment information specified by
1595 /// the specific parameter attribute. The copy will be passed as a byval
1596 /// function parameter.
1598 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1599 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1601 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1603 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1604 /*isVolatile*/false, /*AlwaysInline=*/true,
1605 MachinePointerInfo(), MachinePointerInfo());
1608 /// IsTailCallConvention - Return true if the calling convention is one that
1609 /// supports tail call optimization.
1610 static bool IsTailCallConvention(CallingConv::ID CC) {
1611 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1614 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1615 if (!CI->isTailCall())
1619 CallingConv::ID CalleeCC = CS.getCallingConv();
1620 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1626 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1627 /// a tailcall target by changing its ABI.
1628 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1629 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1633 X86TargetLowering::LowerMemArgument(SDValue Chain,
1634 CallingConv::ID CallConv,
1635 const SmallVectorImpl<ISD::InputArg> &Ins,
1636 DebugLoc dl, SelectionDAG &DAG,
1637 const CCValAssign &VA,
1638 MachineFrameInfo *MFI,
1640 // Create the nodes corresponding to a load from this parameter slot.
1641 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1642 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1643 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1646 // If value is passed by pointer we have address passed instead of the value
1648 if (VA.getLocInfo() == CCValAssign::Indirect)
1649 ValVT = VA.getLocVT();
1651 ValVT = VA.getValVT();
1653 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1654 // changed with more analysis.
1655 // In case of tail call optimization mark all arguments mutable. Since they
1656 // could be overwritten by lowering of arguments in case of a tail call.
1657 if (Flags.isByVal()) {
1658 unsigned Bytes = Flags.getByValSize();
1659 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1660 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1661 return DAG.getFrameIndex(FI, getPointerTy());
1663 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1664 VA.getLocMemOffset(), isImmutable);
1665 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1666 return DAG.getLoad(ValVT, dl, Chain, FIN,
1667 MachinePointerInfo::getFixedStack(FI),
1673 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1674 CallingConv::ID CallConv,
1676 const SmallVectorImpl<ISD::InputArg> &Ins,
1679 SmallVectorImpl<SDValue> &InVals)
1681 MachineFunction &MF = DAG.getMachineFunction();
1682 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1684 const Function* Fn = MF.getFunction();
1685 if (Fn->hasExternalLinkage() &&
1686 Subtarget->isTargetCygMing() &&
1687 Fn->getName() == "main")
1688 FuncInfo->setForceFramePointer(true);
1690 MachineFrameInfo *MFI = MF.getFrameInfo();
1691 bool Is64Bit = Subtarget->is64Bit();
1692 bool IsWin64 = Subtarget->isTargetWin64();
1694 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1695 "Var args not supported with calling convention fastcc or ghc");
1697 // Assign locations to all of the incoming arguments.
1698 SmallVector<CCValAssign, 16> ArgLocs;
1699 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1700 ArgLocs, *DAG.getContext());
1702 // Allocate shadow area for Win64
1704 CCInfo.AllocateStack(32, 8);
1707 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1709 unsigned LastVal = ~0U;
1711 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1712 CCValAssign &VA = ArgLocs[i];
1713 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1715 assert(VA.getValNo() != LastVal &&
1716 "Don't support value assigned to multiple locs yet");
1717 LastVal = VA.getValNo();
1719 if (VA.isRegLoc()) {
1720 EVT RegVT = VA.getLocVT();
1721 TargetRegisterClass *RC = NULL;
1722 if (RegVT == MVT::i32)
1723 RC = X86::GR32RegisterClass;
1724 else if (Is64Bit && RegVT == MVT::i64)
1725 RC = X86::GR64RegisterClass;
1726 else if (RegVT == MVT::f32)
1727 RC = X86::FR32RegisterClass;
1728 else if (RegVT == MVT::f64)
1729 RC = X86::FR64RegisterClass;
1730 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1731 RC = X86::VR256RegisterClass;
1732 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1733 RC = X86::VR128RegisterClass;
1734 else if (RegVT == MVT::x86mmx)
1735 RC = X86::VR64RegisterClass;
1737 llvm_unreachable("Unknown argument type!");
1739 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1740 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1742 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1743 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1745 if (VA.getLocInfo() == CCValAssign::SExt)
1746 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1747 DAG.getValueType(VA.getValVT()));
1748 else if (VA.getLocInfo() == CCValAssign::ZExt)
1749 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1750 DAG.getValueType(VA.getValVT()));
1751 else if (VA.getLocInfo() == CCValAssign::BCvt)
1752 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1754 if (VA.isExtInLoc()) {
1755 // Handle MMX values passed in XMM regs.
1756 if (RegVT.isVector()) {
1757 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1760 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1763 assert(VA.isMemLoc());
1764 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1767 // If value is passed via pointer - do a load.
1768 if (VA.getLocInfo() == CCValAssign::Indirect)
1769 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1770 MachinePointerInfo(), false, false, 0);
1772 InVals.push_back(ArgValue);
1775 // The x86-64 ABI for returning structs by value requires that we copy
1776 // the sret argument into %rax for the return. Save the argument into
1777 // a virtual register so that we can access it from the return points.
1778 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1779 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1780 unsigned Reg = FuncInfo->getSRetReturnReg();
1782 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1783 FuncInfo->setSRetReturnReg(Reg);
1785 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1786 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1789 unsigned StackSize = CCInfo.getNextStackOffset();
1790 // Align stack specially for tail calls.
1791 if (FuncIsMadeTailCallSafe(CallConv))
1792 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1794 // If the function takes variable number of arguments, make a frame index for
1795 // the start of the first vararg value... for expansion of llvm.va_start.
1797 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1798 CallConv != CallingConv::X86_ThisCall)) {
1799 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1802 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1804 // FIXME: We should really autogenerate these arrays
1805 static const unsigned GPR64ArgRegsWin64[] = {
1806 X86::RCX, X86::RDX, X86::R8, X86::R9
1808 static const unsigned GPR64ArgRegs64Bit[] = {
1809 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1811 static const unsigned XMMArgRegs64Bit[] = {
1812 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1813 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1815 const unsigned *GPR64ArgRegs;
1816 unsigned NumXMMRegs = 0;
1819 // The XMM registers which might contain var arg parameters are shadowed
1820 // in their paired GPR. So we only need to save the GPR to their home
1822 TotalNumIntRegs = 4;
1823 GPR64ArgRegs = GPR64ArgRegsWin64;
1825 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1826 GPR64ArgRegs = GPR64ArgRegs64Bit;
1828 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1830 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1833 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1834 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1835 "SSE register cannot be used when SSE is disabled!");
1836 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1837 "SSE register cannot be used when SSE is disabled!");
1838 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1839 // Kernel mode asks for SSE to be disabled, so don't push them
1841 TotalNumXMMRegs = 0;
1844 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1845 // Get to the caller-allocated home save location. Add 8 to account
1846 // for the return address.
1847 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1848 FuncInfo->setRegSaveFrameIndex(
1849 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1850 // Fixup to set vararg frame on shadow area (4 x i64).
1852 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1854 // For X86-64, if there are vararg parameters that are passed via
1855 // registers, then we must store them to their spots on the stack so they
1856 // may be loaded by deferencing the result of va_next.
1857 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1858 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1859 FuncInfo->setRegSaveFrameIndex(
1860 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1864 // Store the integer parameter registers.
1865 SmallVector<SDValue, 8> MemOps;
1866 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1868 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1869 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1870 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1871 DAG.getIntPtrConstant(Offset));
1872 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1873 X86::GR64RegisterClass);
1874 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1876 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1877 MachinePointerInfo::getFixedStack(
1878 FuncInfo->getRegSaveFrameIndex(), Offset),
1880 MemOps.push_back(Store);
1884 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1885 // Now store the XMM (fp + vector) parameter registers.
1886 SmallVector<SDValue, 11> SaveXMMOps;
1887 SaveXMMOps.push_back(Chain);
1889 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1890 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1891 SaveXMMOps.push_back(ALVal);
1893 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1894 FuncInfo->getRegSaveFrameIndex()));
1895 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1896 FuncInfo->getVarArgsFPOffset()));
1898 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1899 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1900 X86::VR128RegisterClass);
1901 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1902 SaveXMMOps.push_back(Val);
1904 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1906 &SaveXMMOps[0], SaveXMMOps.size()));
1909 if (!MemOps.empty())
1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1911 &MemOps[0], MemOps.size());
1915 // Some CCs need callee pop.
1916 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1917 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1919 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1920 // If this is an sret function, the return should pop the hidden pointer.
1921 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1922 FuncInfo->setBytesToPopOnReturn(4);
1926 // RegSaveFrameIndex is X86-64 only.
1927 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1928 if (CallConv == CallingConv::X86_FastCall ||
1929 CallConv == CallingConv::X86_ThisCall)
1930 // fastcc functions can't have varargs.
1931 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1938 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1939 SDValue StackPtr, SDValue Arg,
1940 DebugLoc dl, SelectionDAG &DAG,
1941 const CCValAssign &VA,
1942 ISD::ArgFlagsTy Flags) const {
1943 unsigned LocMemOffset = VA.getLocMemOffset();
1944 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1945 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1946 if (Flags.isByVal())
1947 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1949 return DAG.getStore(Chain, dl, Arg, PtrOff,
1950 MachinePointerInfo::getStack(LocMemOffset),
1954 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1955 /// optimization is performed and it is required.
1957 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1958 SDValue &OutRetAddr, SDValue Chain,
1959 bool IsTailCall, bool Is64Bit,
1960 int FPDiff, DebugLoc dl) const {
1961 // Adjust the Return address stack slot.
1962 EVT VT = getPointerTy();
1963 OutRetAddr = getReturnAddressFrameIndex(DAG);
1965 // Load the "old" Return address.
1966 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1968 return SDValue(OutRetAddr.getNode(), 1);
1971 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1972 /// optimization is performed and it is required (FPDiff!=0).
1974 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1975 SDValue Chain, SDValue RetAddrFrIdx,
1976 bool Is64Bit, int FPDiff, DebugLoc dl) {
1977 // Store the return address to the appropriate stack slot.
1978 if (!FPDiff) return Chain;
1979 // Calculate the new stack slot for the return address.
1980 int SlotSize = Is64Bit ? 8 : 4;
1981 int NewReturnAddrFI =
1982 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1983 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1984 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1985 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1986 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1992 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1993 CallingConv::ID CallConv, bool isVarArg,
1995 const SmallVectorImpl<ISD::OutputArg> &Outs,
1996 const SmallVectorImpl<SDValue> &OutVals,
1997 const SmallVectorImpl<ISD::InputArg> &Ins,
1998 DebugLoc dl, SelectionDAG &DAG,
1999 SmallVectorImpl<SDValue> &InVals) const {
2000 MachineFunction &MF = DAG.getMachineFunction();
2001 bool Is64Bit = Subtarget->is64Bit();
2002 bool IsWin64 = Subtarget->isTargetWin64();
2003 bool IsStructRet = CallIsStructReturn(Outs);
2004 bool IsSibcall = false;
2007 // Check if it's really possible to do a tail call.
2008 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2009 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2010 Outs, OutVals, Ins, DAG);
2012 // Sibcalls are automatically detected tailcalls which do not require
2014 if (!GuaranteedTailCallOpt && isTailCall)
2021 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2022 "Var args not supported with calling convention fastcc or ghc");
2024 // Analyze operands of the call, assigning locations to each operand.
2025 SmallVector<CCValAssign, 16> ArgLocs;
2026 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2027 ArgLocs, *DAG.getContext());
2029 // Allocate shadow area for Win64
2031 CCInfo.AllocateStack(32, 8);
2034 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2036 // Get a count of how many bytes are to be pushed on the stack.
2037 unsigned NumBytes = CCInfo.getNextStackOffset();
2039 // This is a sibcall. The memory operands are available in caller's
2040 // own caller's stack.
2042 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2043 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2046 if (isTailCall && !IsSibcall) {
2047 // Lower arguments at fp - stackoffset + fpdiff.
2048 unsigned NumBytesCallerPushed =
2049 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2050 FPDiff = NumBytesCallerPushed - NumBytes;
2052 // Set the delta of movement of the returnaddr stackslot.
2053 // But only set if delta is greater than previous delta.
2054 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2055 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2059 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2061 SDValue RetAddrFrIdx;
2062 // Load return address for tail calls.
2063 if (isTailCall && FPDiff)
2064 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2065 Is64Bit, FPDiff, dl);
2067 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2068 SmallVector<SDValue, 8> MemOpChains;
2071 // Walk the register/memloc assignments, inserting copies/loads. In the case
2072 // of tail call optimization arguments are handle later.
2073 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2074 CCValAssign &VA = ArgLocs[i];
2075 EVT RegVT = VA.getLocVT();
2076 SDValue Arg = OutVals[i];
2077 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2078 bool isByVal = Flags.isByVal();
2080 // Promote the value if needed.
2081 switch (VA.getLocInfo()) {
2082 default: llvm_unreachable("Unknown loc info!");
2083 case CCValAssign::Full: break;
2084 case CCValAssign::SExt:
2085 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2087 case CCValAssign::ZExt:
2088 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2090 case CCValAssign::AExt:
2091 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2092 // Special case: passing MMX values in XMM registers.
2093 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2094 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2095 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2097 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2099 case CCValAssign::BCvt:
2100 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2102 case CCValAssign::Indirect: {
2103 // Store the argument.
2104 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2105 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2106 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2107 MachinePointerInfo::getFixedStack(FI),
2114 if (VA.isRegLoc()) {
2115 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2116 if (isVarArg && IsWin64) {
2117 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2118 // shadow reg if callee is a varargs function.
2119 unsigned ShadowReg = 0;
2120 switch (VA.getLocReg()) {
2121 case X86::XMM0: ShadowReg = X86::RCX; break;
2122 case X86::XMM1: ShadowReg = X86::RDX; break;
2123 case X86::XMM2: ShadowReg = X86::R8; break;
2124 case X86::XMM3: ShadowReg = X86::R9; break;
2127 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2129 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2130 assert(VA.isMemLoc());
2131 if (StackPtr.getNode() == 0)
2132 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2133 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2134 dl, DAG, VA, Flags));
2138 if (!MemOpChains.empty())
2139 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2140 &MemOpChains[0], MemOpChains.size());
2142 // Build a sequence of copy-to-reg nodes chained together with token chain
2143 // and flag operands which copy the outgoing args into registers.
2145 // Tail call byval lowering might overwrite argument registers so in case of
2146 // tail call optimization the copies to registers are lowered later.
2148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2149 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2150 RegsToPass[i].second, InFlag);
2151 InFlag = Chain.getValue(1);
2154 if (Subtarget->isPICStyleGOT()) {
2155 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2158 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2159 DAG.getNode(X86ISD::GlobalBaseReg,
2160 DebugLoc(), getPointerTy()),
2162 InFlag = Chain.getValue(1);
2164 // If we are tail calling and generating PIC/GOT style code load the
2165 // address of the callee into ECX. The value in ecx is used as target of
2166 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2167 // for tail calls on PIC/GOT architectures. Normally we would just put the
2168 // address of GOT into ebx and then call target@PLT. But for tail calls
2169 // ebx would be restored (since ebx is callee saved) before jumping to the
2172 // Note: The actual moving to ECX is done further down.
2173 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2174 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2175 !G->getGlobal()->hasProtectedVisibility())
2176 Callee = LowerGlobalAddress(Callee, DAG);
2177 else if (isa<ExternalSymbolSDNode>(Callee))
2178 Callee = LowerExternalSymbol(Callee, DAG);
2182 if (Is64Bit && isVarArg && !IsWin64) {
2183 // From AMD64 ABI document:
2184 // For calls that may call functions that use varargs or stdargs
2185 // (prototype-less calls or calls to functions containing ellipsis (...) in
2186 // the declaration) %al is used as hidden argument to specify the number
2187 // of SSE registers used. The contents of %al do not need to match exactly
2188 // the number of registers, but must be an ubound on the number of SSE
2189 // registers used and is in the range 0 - 8 inclusive.
2191 // Count the number of XMM registers allocated.
2192 static const unsigned XMMArgRegs[] = {
2193 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2194 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2196 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2197 assert((Subtarget->hasXMM() || !NumXMMRegs)
2198 && "SSE registers cannot be used when SSE is disabled");
2200 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2201 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2202 InFlag = Chain.getValue(1);
2206 // For tail calls lower the arguments to the 'real' stack slot.
2208 // Force all the incoming stack arguments to be loaded from the stack
2209 // before any new outgoing arguments are stored to the stack, because the
2210 // outgoing stack slots may alias the incoming argument stack slots, and
2211 // the alias isn't otherwise explicit. This is slightly more conservative
2212 // than necessary, because it means that each store effectively depends
2213 // on every argument instead of just those arguments it would clobber.
2214 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2216 SmallVector<SDValue, 8> MemOpChains2;
2219 // Do not flag preceding copytoreg stuff together with the following stuff.
2221 if (GuaranteedTailCallOpt) {
2222 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2223 CCValAssign &VA = ArgLocs[i];
2226 assert(VA.isMemLoc());
2227 SDValue Arg = OutVals[i];
2228 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2229 // Create frame index.
2230 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2231 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2232 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2233 FIN = DAG.getFrameIndex(FI, getPointerTy());
2235 if (Flags.isByVal()) {
2236 // Copy relative to framepointer.
2237 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2238 if (StackPtr.getNode() == 0)
2239 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2241 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2243 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2247 // Store relative to framepointer.
2248 MemOpChains2.push_back(
2249 DAG.getStore(ArgChain, dl, Arg, FIN,
2250 MachinePointerInfo::getFixedStack(FI),
2256 if (!MemOpChains2.empty())
2257 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2258 &MemOpChains2[0], MemOpChains2.size());
2260 // Copy arguments to their registers.
2261 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2262 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2263 RegsToPass[i].second, InFlag);
2264 InFlag = Chain.getValue(1);
2268 // Store the return address to the appropriate stack slot.
2269 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2273 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2274 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2275 // In the 64-bit large code model, we have to make all calls
2276 // through a register, since the call instruction's 32-bit
2277 // pc-relative offset may not be large enough to hold the whole
2279 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2280 // If the callee is a GlobalAddress node (quite common, every direct call
2281 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2284 // We should use extra load for direct calls to dllimported functions in
2286 const GlobalValue *GV = G->getGlobal();
2287 if (!GV->hasDLLImportLinkage()) {
2288 unsigned char OpFlags = 0;
2289 bool ExtraLoad = false;
2290 unsigned WrapperKind = ISD::DELETED_NODE;
2292 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2293 // external symbols most go through the PLT in PIC mode. If the symbol
2294 // has hidden or protected visibility, or if it is static or local, then
2295 // we don't need to use the PLT - we can directly call it.
2296 if (Subtarget->isTargetELF() &&
2297 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2298 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2299 OpFlags = X86II::MO_PLT;
2300 } else if (Subtarget->isPICStyleStubAny() &&
2301 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2302 (!Subtarget->getTargetTriple().isMacOSX() ||
2303 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2304 // PC-relative references to external symbols should go through $stub,
2305 // unless we're building with the leopard linker or later, which
2306 // automatically synthesizes these stubs.
2307 OpFlags = X86II::MO_DARWIN_STUB;
2308 } else if (Subtarget->isPICStyleRIPRel() &&
2309 isa<Function>(GV) &&
2310 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2311 // If the function is marked as non-lazy, generate an indirect call
2312 // which loads from the GOT directly. This avoids runtime overhead
2313 // at the cost of eager binding (and one extra byte of encoding).
2314 OpFlags = X86II::MO_GOTPCREL;
2315 WrapperKind = X86ISD::WrapperRIP;
2319 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2320 G->getOffset(), OpFlags);
2322 // Add a wrapper if needed.
2323 if (WrapperKind != ISD::DELETED_NODE)
2324 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2325 // Add extra indirection if needed.
2327 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2328 MachinePointerInfo::getGOT(),
2331 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2332 unsigned char OpFlags = 0;
2334 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2335 // external symbols should go through the PLT.
2336 if (Subtarget->isTargetELF() &&
2337 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2338 OpFlags = X86II::MO_PLT;
2339 } else if (Subtarget->isPICStyleStubAny() &&
2340 (!Subtarget->getTargetTriple().isMacOSX() ||
2341 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2342 // PC-relative references to external symbols should go through $stub,
2343 // unless we're building with the leopard linker or later, which
2344 // automatically synthesizes these stubs.
2345 OpFlags = X86II::MO_DARWIN_STUB;
2348 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2352 // Returns a chain & a flag for retval copy to use.
2353 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2354 SmallVector<SDValue, 8> Ops;
2356 if (!IsSibcall && isTailCall) {
2357 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2358 DAG.getIntPtrConstant(0, true), InFlag);
2359 InFlag = Chain.getValue(1);
2362 Ops.push_back(Chain);
2363 Ops.push_back(Callee);
2366 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2368 // Add argument registers to the end of the list so that they are known live
2370 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2371 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2372 RegsToPass[i].second.getValueType()));
2374 // Add an implicit use GOT pointer in EBX.
2375 if (!isTailCall && Subtarget->isPICStyleGOT())
2376 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2378 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2379 if (Is64Bit && isVarArg && !IsWin64)
2380 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2382 if (InFlag.getNode())
2383 Ops.push_back(InFlag);
2387 //// If this is the first return lowered for this function, add the regs
2388 //// to the liveout set for the function.
2389 // This isn't right, although it's probably harmless on x86; liveouts
2390 // should be computed from returns not tail calls. Consider a void
2391 // function making a tail call to a function returning int.
2392 return DAG.getNode(X86ISD::TC_RETURN, dl,
2393 NodeTys, &Ops[0], Ops.size());
2396 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2397 InFlag = Chain.getValue(1);
2399 // Create the CALLSEQ_END node.
2400 unsigned NumBytesForCalleeToPush;
2401 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2402 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2403 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2404 // If this is a call to a struct-return function, the callee
2405 // pops the hidden struct pointer, so we have to push it back.
2406 // This is common for Darwin/X86, Linux & Mingw32 targets.
2407 NumBytesForCalleeToPush = 4;
2409 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2411 // Returns a flag for retval copy to use.
2413 Chain = DAG.getCALLSEQ_END(Chain,
2414 DAG.getIntPtrConstant(NumBytes, true),
2415 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2418 InFlag = Chain.getValue(1);
2421 // Handle result values, copying them out of physregs into vregs that we
2423 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2424 Ins, dl, DAG, InVals);
2428 //===----------------------------------------------------------------------===//
2429 // Fast Calling Convention (tail call) implementation
2430 //===----------------------------------------------------------------------===//
2432 // Like std call, callee cleans arguments, convention except that ECX is
2433 // reserved for storing the tail called function address. Only 2 registers are
2434 // free for argument passing (inreg). Tail call optimization is performed
2436 // * tailcallopt is enabled
2437 // * caller/callee are fastcc
2438 // On X86_64 architecture with GOT-style position independent code only local
2439 // (within module) calls are supported at the moment.
2440 // To keep the stack aligned according to platform abi the function
2441 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2442 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2443 // If a tail called function callee has more arguments than the caller the
2444 // caller needs to make sure that there is room to move the RETADDR to. This is
2445 // achieved by reserving an area the size of the argument delta right after the
2446 // original REtADDR, but before the saved framepointer or the spilled registers
2447 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2459 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2460 /// for a 16 byte align requirement.
2462 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2463 SelectionDAG& DAG) const {
2464 MachineFunction &MF = DAG.getMachineFunction();
2465 const TargetMachine &TM = MF.getTarget();
2466 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2467 unsigned StackAlignment = TFI.getStackAlignment();
2468 uint64_t AlignMask = StackAlignment - 1;
2469 int64_t Offset = StackSize;
2470 uint64_t SlotSize = TD->getPointerSize();
2471 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2472 // Number smaller than 12 so just add the difference.
2473 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2475 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2476 Offset = ((~AlignMask) & Offset) + StackAlignment +
2477 (StackAlignment-SlotSize);
2482 /// MatchingStackOffset - Return true if the given stack call argument is
2483 /// already available in the same position (relatively) of the caller's
2484 /// incoming argument stack.
2486 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2487 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2488 const X86InstrInfo *TII) {
2489 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2491 if (Arg.getOpcode() == ISD::CopyFromReg) {
2492 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2493 if (!TargetRegisterInfo::isVirtualRegister(VR))
2495 MachineInstr *Def = MRI->getVRegDef(VR);
2498 if (!Flags.isByVal()) {
2499 if (!TII->isLoadFromStackSlot(Def, FI))
2502 unsigned Opcode = Def->getOpcode();
2503 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2504 Def->getOperand(1).isFI()) {
2505 FI = Def->getOperand(1).getIndex();
2506 Bytes = Flags.getByValSize();
2510 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2511 if (Flags.isByVal())
2512 // ByVal argument is passed in as a pointer but it's now being
2513 // dereferenced. e.g.
2514 // define @foo(%struct.X* %A) {
2515 // tail call @bar(%struct.X* byval %A)
2518 SDValue Ptr = Ld->getBasePtr();
2519 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2522 FI = FINode->getIndex();
2523 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2524 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2525 FI = FINode->getIndex();
2526 Bytes = Flags.getByValSize();
2530 assert(FI != INT_MAX);
2531 if (!MFI->isFixedObjectIndex(FI))
2533 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2536 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2537 /// for tail call optimization. Targets which want to do tail call
2538 /// optimization should implement this function.
2540 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2541 CallingConv::ID CalleeCC,
2543 bool isCalleeStructRet,
2544 bool isCallerStructRet,
2545 const SmallVectorImpl<ISD::OutputArg> &Outs,
2546 const SmallVectorImpl<SDValue> &OutVals,
2547 const SmallVectorImpl<ISD::InputArg> &Ins,
2548 SelectionDAG& DAG) const {
2549 if (!IsTailCallConvention(CalleeCC) &&
2550 CalleeCC != CallingConv::C)
2553 // If -tailcallopt is specified, make fastcc functions tail-callable.
2554 const MachineFunction &MF = DAG.getMachineFunction();
2555 const Function *CallerF = DAG.getMachineFunction().getFunction();
2556 CallingConv::ID CallerCC = CallerF->getCallingConv();
2557 bool CCMatch = CallerCC == CalleeCC;
2559 if (GuaranteedTailCallOpt) {
2560 if (IsTailCallConvention(CalleeCC) && CCMatch)
2565 // Look for obvious safe cases to perform tail call optimization that do not
2566 // require ABI changes. This is what gcc calls sibcall.
2568 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2569 // emit a special epilogue.
2570 if (RegInfo->needsStackRealignment(MF))
2573 // Also avoid sibcall optimization if either caller or callee uses struct
2574 // return semantics.
2575 if (isCalleeStructRet || isCallerStructRet)
2578 // An stdcall caller is expected to clean up its arguments; the callee
2579 // isn't going to do that.
2580 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2583 // Do not sibcall optimize vararg calls unless all arguments are passed via
2585 if (isVarArg && !Outs.empty()) {
2587 // Optimizing for varargs on Win64 is unlikely to be safe without
2588 // additional testing.
2589 if (Subtarget->isTargetWin64())
2592 SmallVector<CCValAssign, 16> ArgLocs;
2593 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2594 getTargetMachine(), ArgLocs, *DAG.getContext());
2596 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2597 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2598 if (!ArgLocs[i].isRegLoc())
2602 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2603 // Therefore if it's not used by the call it is not safe to optimize this into
2605 bool Unused = false;
2606 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2613 SmallVector<CCValAssign, 16> RVLocs;
2614 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2615 getTargetMachine(), RVLocs, *DAG.getContext());
2616 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2617 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2618 CCValAssign &VA = RVLocs[i];
2619 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2624 // If the calling conventions do not match, then we'd better make sure the
2625 // results are returned in the same way as what the caller expects.
2627 SmallVector<CCValAssign, 16> RVLocs1;
2628 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2629 getTargetMachine(), RVLocs1, *DAG.getContext());
2630 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2632 SmallVector<CCValAssign, 16> RVLocs2;
2633 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2634 getTargetMachine(), RVLocs2, *DAG.getContext());
2635 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2637 if (RVLocs1.size() != RVLocs2.size())
2639 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2640 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2642 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2644 if (RVLocs1[i].isRegLoc()) {
2645 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2648 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2654 // If the callee takes no arguments then go on to check the results of the
2656 if (!Outs.empty()) {
2657 // Check if stack adjustment is needed. For now, do not do this if any
2658 // argument is passed on the stack.
2659 SmallVector<CCValAssign, 16> ArgLocs;
2660 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2661 getTargetMachine(), ArgLocs, *DAG.getContext());
2663 // Allocate shadow area for Win64
2664 if (Subtarget->isTargetWin64()) {
2665 CCInfo.AllocateStack(32, 8);
2668 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2669 if (CCInfo.getNextStackOffset()) {
2670 MachineFunction &MF = DAG.getMachineFunction();
2671 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2674 // Check if the arguments are already laid out in the right way as
2675 // the caller's fixed stack objects.
2676 MachineFrameInfo *MFI = MF.getFrameInfo();
2677 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2678 const X86InstrInfo *TII =
2679 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2681 CCValAssign &VA = ArgLocs[i];
2682 SDValue Arg = OutVals[i];
2683 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2684 if (VA.getLocInfo() == CCValAssign::Indirect)
2686 if (!VA.isRegLoc()) {
2687 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2694 // If the tailcall address may be in a register, then make sure it's
2695 // possible to register allocate for it. In 32-bit, the call address can
2696 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2697 // callee-saved registers are restored. These happen to be the same
2698 // registers used to pass 'inreg' arguments so watch out for those.
2699 if (!Subtarget->is64Bit() &&
2700 !isa<GlobalAddressSDNode>(Callee) &&
2701 !isa<ExternalSymbolSDNode>(Callee)) {
2702 unsigned NumInRegs = 0;
2703 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2704 CCValAssign &VA = ArgLocs[i];
2707 unsigned Reg = VA.getLocReg();
2710 case X86::EAX: case X86::EDX: case X86::ECX:
2711 if (++NumInRegs == 3)
2723 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2724 return X86::createFastISel(funcInfo);
2728 //===----------------------------------------------------------------------===//
2729 // Other Lowering Hooks
2730 //===----------------------------------------------------------------------===//
2732 static bool MayFoldLoad(SDValue Op) {
2733 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2736 static bool MayFoldIntoStore(SDValue Op) {
2737 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2740 static bool isTargetShuffle(unsigned Opcode) {
2742 default: return false;
2743 case X86ISD::PSHUFD:
2744 case X86ISD::PSHUFHW:
2745 case X86ISD::PSHUFLW:
2746 case X86ISD::SHUFPD:
2747 case X86ISD::PALIGN:
2748 case X86ISD::SHUFPS:
2749 case X86ISD::MOVLHPS:
2750 case X86ISD::MOVLHPD:
2751 case X86ISD::MOVHLPS:
2752 case X86ISD::MOVLPS:
2753 case X86ISD::MOVLPD:
2754 case X86ISD::MOVSHDUP:
2755 case X86ISD::MOVSLDUP:
2756 case X86ISD::MOVDDUP:
2759 case X86ISD::UNPCKLPS:
2760 case X86ISD::UNPCKLPD:
2761 case X86ISD::VUNPCKLPSY:
2762 case X86ISD::VUNPCKLPDY:
2763 case X86ISD::PUNPCKLWD:
2764 case X86ISD::PUNPCKLBW:
2765 case X86ISD::PUNPCKLDQ:
2766 case X86ISD::PUNPCKLQDQ:
2767 case X86ISD::UNPCKHPS:
2768 case X86ISD::UNPCKHPD:
2769 case X86ISD::VUNPCKHPSY:
2770 case X86ISD::VUNPCKHPDY:
2771 case X86ISD::PUNPCKHWD:
2772 case X86ISD::PUNPCKHBW:
2773 case X86ISD::PUNPCKHDQ:
2774 case X86ISD::PUNPCKHQDQ:
2775 case X86ISD::VPERMILPS:
2776 case X86ISD::VPERMILPSY:
2777 case X86ISD::VPERMILPD:
2778 case X86ISD::VPERMILPDY:
2779 case X86ISD::VPERM2F128:
2785 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2786 SDValue V1, SelectionDAG &DAG) {
2788 default: llvm_unreachable("Unknown x86 shuffle node");
2789 case X86ISD::MOVSHDUP:
2790 case X86ISD::MOVSLDUP:
2791 case X86ISD::MOVDDUP:
2792 return DAG.getNode(Opc, dl, VT, V1);
2798 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2799 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2801 default: llvm_unreachable("Unknown x86 shuffle node");
2802 case X86ISD::PSHUFD:
2803 case X86ISD::PSHUFHW:
2804 case X86ISD::PSHUFLW:
2805 case X86ISD::VPERMILPS:
2806 case X86ISD::VPERMILPSY:
2807 case X86ISD::VPERMILPD:
2808 case X86ISD::VPERMILPDY:
2809 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2815 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2816 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2818 default: llvm_unreachable("Unknown x86 shuffle node");
2819 case X86ISD::PALIGN:
2820 case X86ISD::SHUFPD:
2821 case X86ISD::SHUFPS:
2822 case X86ISD::VPERM2F128:
2823 return DAG.getNode(Opc, dl, VT, V1, V2,
2824 DAG.getConstant(TargetMask, MVT::i8));
2829 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2830 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2832 default: llvm_unreachable("Unknown x86 shuffle node");
2833 case X86ISD::MOVLHPS:
2834 case X86ISD::MOVLHPD:
2835 case X86ISD::MOVHLPS:
2836 case X86ISD::MOVLPS:
2837 case X86ISD::MOVLPD:
2840 case X86ISD::UNPCKLPS:
2841 case X86ISD::UNPCKLPD:
2842 case X86ISD::VUNPCKLPSY:
2843 case X86ISD::VUNPCKLPDY:
2844 case X86ISD::PUNPCKLWD:
2845 case X86ISD::PUNPCKLBW:
2846 case X86ISD::PUNPCKLDQ:
2847 case X86ISD::PUNPCKLQDQ:
2848 case X86ISD::UNPCKHPS:
2849 case X86ISD::UNPCKHPD:
2850 case X86ISD::VUNPCKHPSY:
2851 case X86ISD::VUNPCKHPDY:
2852 case X86ISD::PUNPCKHWD:
2853 case X86ISD::PUNPCKHBW:
2854 case X86ISD::PUNPCKHDQ:
2855 case X86ISD::PUNPCKHQDQ:
2856 return DAG.getNode(Opc, dl, VT, V1, V2);
2861 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2862 MachineFunction &MF = DAG.getMachineFunction();
2863 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2864 int ReturnAddrIndex = FuncInfo->getRAIndex();
2866 if (ReturnAddrIndex == 0) {
2867 // Set up a frame object for the return address.
2868 uint64_t SlotSize = TD->getPointerSize();
2869 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2871 FuncInfo->setRAIndex(ReturnAddrIndex);
2874 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2878 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2879 bool hasSymbolicDisplacement) {
2880 // Offset should fit into 32 bit immediate field.
2881 if (!isInt<32>(Offset))
2884 // If we don't have a symbolic displacement - we don't have any extra
2886 if (!hasSymbolicDisplacement)
2889 // FIXME: Some tweaks might be needed for medium code model.
2890 if (M != CodeModel::Small && M != CodeModel::Kernel)
2893 // For small code model we assume that latest object is 16MB before end of 31
2894 // bits boundary. We may also accept pretty large negative constants knowing
2895 // that all objects are in the positive half of address space.
2896 if (M == CodeModel::Small && Offset < 16*1024*1024)
2899 // For kernel code model we know that all object resist in the negative half
2900 // of 32bits address space. We may not accept negative offsets, since they may
2901 // be just off and we may accept pretty large positive ones.
2902 if (M == CodeModel::Kernel && Offset > 0)
2908 /// isCalleePop - Determines whether the callee is required to pop its
2909 /// own arguments. Callee pop is necessary to support tail calls.
2910 bool X86::isCalleePop(CallingConv::ID CallingConv,
2911 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2915 switch (CallingConv) {
2918 case CallingConv::X86_StdCall:
2920 case CallingConv::X86_FastCall:
2922 case CallingConv::X86_ThisCall:
2924 case CallingConv::Fast:
2926 case CallingConv::GHC:
2931 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2932 /// specific condition code, returning the condition code and the LHS/RHS of the
2933 /// comparison to make.
2934 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2935 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2937 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2938 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2939 // X > -1 -> X == 0, jump !sign.
2940 RHS = DAG.getConstant(0, RHS.getValueType());
2941 return X86::COND_NS;
2942 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2943 // X < 0 -> X == 0, jump on sign.
2945 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2947 RHS = DAG.getConstant(0, RHS.getValueType());
2948 return X86::COND_LE;
2952 switch (SetCCOpcode) {
2953 default: llvm_unreachable("Invalid integer condition!");
2954 case ISD::SETEQ: return X86::COND_E;
2955 case ISD::SETGT: return X86::COND_G;
2956 case ISD::SETGE: return X86::COND_GE;
2957 case ISD::SETLT: return X86::COND_L;
2958 case ISD::SETLE: return X86::COND_LE;
2959 case ISD::SETNE: return X86::COND_NE;
2960 case ISD::SETULT: return X86::COND_B;
2961 case ISD::SETUGT: return X86::COND_A;
2962 case ISD::SETULE: return X86::COND_BE;
2963 case ISD::SETUGE: return X86::COND_AE;
2967 // First determine if it is required or is profitable to flip the operands.
2969 // If LHS is a foldable load, but RHS is not, flip the condition.
2970 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2971 !ISD::isNON_EXTLoad(RHS.getNode())) {
2972 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2973 std::swap(LHS, RHS);
2976 switch (SetCCOpcode) {
2982 std::swap(LHS, RHS);
2986 // On a floating point condition, the flags are set as follows:
2988 // 0 | 0 | 0 | X > Y
2989 // 0 | 0 | 1 | X < Y
2990 // 1 | 0 | 0 | X == Y
2991 // 1 | 1 | 1 | unordered
2992 switch (SetCCOpcode) {
2993 default: llvm_unreachable("Condcode should be pre-legalized away");
2995 case ISD::SETEQ: return X86::COND_E;
2996 case ISD::SETOLT: // flipped
2998 case ISD::SETGT: return X86::COND_A;
2999 case ISD::SETOLE: // flipped
3001 case ISD::SETGE: return X86::COND_AE;
3002 case ISD::SETUGT: // flipped
3004 case ISD::SETLT: return X86::COND_B;
3005 case ISD::SETUGE: // flipped
3007 case ISD::SETLE: return X86::COND_BE;
3009 case ISD::SETNE: return X86::COND_NE;
3010 case ISD::SETUO: return X86::COND_P;
3011 case ISD::SETO: return X86::COND_NP;
3013 case ISD::SETUNE: return X86::COND_INVALID;
3017 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3018 /// code. Current x86 isa includes the following FP cmov instructions:
3019 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3020 static bool hasFPCMov(unsigned X86CC) {
3036 /// isFPImmLegal - Returns true if the target can instruction select the
3037 /// specified FP immediate natively. If false, the legalizer will
3038 /// materialize the FP immediate as a load from a constant pool.
3039 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3040 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3041 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3047 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3048 /// the specified range (L, H].
3049 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3050 return (Val < 0) || (Val >= Low && Val < Hi);
3053 /// isUndefOrInRange - Return true if every element in Mask, begining
3054 /// from position Pos and ending in Pos+Size, falls within the specified
3055 /// range (L, L+Pos]. or is undef.
3056 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3057 int Pos, int Size, int Low, int Hi) {
3058 for (int i = Pos, e = Pos+Size; i != e; ++i)
3059 if (!isUndefOrInRange(Mask[i], Low, Hi))
3064 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3065 /// specified value.
3066 static bool isUndefOrEqual(int Val, int CmpVal) {
3067 if (Val < 0 || Val == CmpVal)
3072 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3073 /// from position Pos and ending in Pos+Size, falls within the specified
3074 /// sequential range (L, L+Pos]. or is undef.
3075 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3076 int Pos, int Size, int Low) {
3077 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3078 if (!isUndefOrEqual(Mask[i], Low))
3083 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3084 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3085 /// the second operand.
3086 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3087 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3088 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3089 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3090 return (Mask[0] < 2 && Mask[1] < 2);
3094 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3095 SmallVector<int, 8> M;
3097 return ::isPSHUFDMask(M, N->getValueType(0));
3100 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3101 /// is suitable for input to PSHUFHW.
3102 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3103 if (VT != MVT::v8i16)
3106 // Lower quadword copied in order or undef.
3107 for (int i = 0; i != 4; ++i)
3108 if (Mask[i] >= 0 && Mask[i] != i)
3111 // Upper quadword shuffled.
3112 for (int i = 4; i != 8; ++i)
3113 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3119 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3120 SmallVector<int, 8> M;
3122 return ::isPSHUFHWMask(M, N->getValueType(0));
3125 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3126 /// is suitable for input to PSHUFLW.
3127 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3128 if (VT != MVT::v8i16)
3131 // Upper quadword copied in order.
3132 for (int i = 4; i != 8; ++i)
3133 if (Mask[i] >= 0 && Mask[i] != i)
3136 // Lower quadword shuffled.
3137 for (int i = 0; i != 4; ++i)
3144 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3145 SmallVector<int, 8> M;
3147 return ::isPSHUFLWMask(M, N->getValueType(0));
3150 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3151 /// is suitable for input to PALIGNR.
3152 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3154 int i, e = VT.getVectorNumElements();
3155 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3158 // Do not handle v2i64 / v2f64 shuffles with palignr.
3159 if (e < 4 || !hasSSSE3)
3162 for (i = 0; i != e; ++i)
3166 // All undef, not a palignr.
3170 // Make sure we're shifting in the right direction.
3174 int s = Mask[i] - i;
3176 // Check the rest of the elements to see if they are consecutive.
3177 for (++i; i != e; ++i) {
3179 if (m >= 0 && m != s+i)
3185 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3186 /// specifies a shuffle of elements that is suitable for input to 256-bit
3188 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3189 const X86Subtarget *Subtarget) {
3190 int NumElems = VT.getVectorNumElements();
3192 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3198 // VSHUFPSY divides the resulting vector into 4 chunks.
3199 // The sources are also splitted into 4 chunks, and each destination
3200 // chunk must come from a different source chunk.
3202 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3203 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3205 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3206 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3208 int QuarterSize = NumElems/4;
3209 int HalfSize = QuarterSize*2;
3210 for (int i = 0; i < QuarterSize; ++i)
3211 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3213 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3214 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3217 // The mask of the second half must be the same as the first but with
3218 // the appropriate offsets. This works in the same way as VPERMILPS
3219 // works with masks.
3220 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
3221 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3223 int FstHalfIdx = i-HalfSize;
3224 if (Mask[FstHalfIdx] < 0)
3226 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3229 for (int i = QuarterSize*3; i < NumElems; ++i) {
3230 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3232 int FstHalfIdx = i-HalfSize;
3233 if (Mask[FstHalfIdx] < 0)
3235 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3243 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
3244 /// the specified VECTOR_MASK mask with VSHUFPSY instruction.
3245 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
3246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3247 EVT VT = SVOp->getValueType(0);
3248 int NumElems = VT.getVectorNumElements();
3250 assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
3251 "Only supports v8i32 and v8f32 types");
3253 int HalfSize = NumElems/2;
3255 for (int i = 0; i != NumElems ; ++i) {
3256 if (SVOp->getMaskElt(i) < 0)
3258 // The mask of the first half must be equal to the second one.
3259 unsigned Shamt = (i%HalfSize)*2;
3260 unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
3261 Mask |= Elt << Shamt;
3267 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3268 /// specifies a shuffle of elements that is suitable for input to 256-bit
3269 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
3270 /// version and the mask of the second half isn't binded with the first
3272 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3273 const X86Subtarget *Subtarget) {
3274 int NumElems = VT.getVectorNumElements();
3276 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3282 // VSHUFPSY divides the resulting vector into 4 chunks.
3283 // The sources are also splitted into 4 chunks, and each destination
3284 // chunk must come from a different source chunk.
3286 // SRC1 => X3 X2 X1 X0
3287 // SRC2 => Y3 Y2 Y1 Y0
3289 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
3291 int QuarterSize = NumElems/4;
3292 int HalfSize = QuarterSize*2;
3293 for (int i = 0; i < QuarterSize; ++i)
3294 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3296 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3297 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3299 for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
3300 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3302 for (int i = QuarterSize*3; i < NumElems; ++i)
3303 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3309 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
3310 /// the specified VECTOR_MASK mask with VSHUFPDY instruction.
3311 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
3312 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3313 EVT VT = SVOp->getValueType(0);
3314 int NumElems = VT.getVectorNumElements();
3316 assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
3317 "Only supports v4i64 and v4f64 types");
3319 int HalfSize = NumElems/2;
3321 for (int i = 0; i != NumElems ; ++i) {
3322 if (SVOp->getMaskElt(i) < 0)
3324 int Elt = SVOp->getMaskElt(i) % HalfSize;
3331 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3332 /// specifies a shuffle of elements that is suitable for input to 128-bit
3333 /// SHUFPS and SHUFPD.
3334 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3335 int NumElems = VT.getVectorNumElements();
3337 if (VT.getSizeInBits() != 128)
3340 if (NumElems != 2 && NumElems != 4)
3343 int Half = NumElems / 2;
3344 for (int i = 0; i < Half; ++i)
3345 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3347 for (int i = Half; i < NumElems; ++i)
3348 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3354 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3355 SmallVector<int, 8> M;
3357 return ::isSHUFPMask(M, N->getValueType(0));
3360 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3361 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3362 /// half elements to come from vector 1 (which would equal the dest.) and
3363 /// the upper half to come from vector 2.
3364 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3365 int NumElems = VT.getVectorNumElements();
3367 if (NumElems != 2 && NumElems != 4)
3370 int Half = NumElems / 2;
3371 for (int i = 0; i < Half; ++i)
3372 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3374 for (int i = Half; i < NumElems; ++i)
3375 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3380 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3381 SmallVector<int, 8> M;
3383 return isCommutedSHUFPMask(M, N->getValueType(0));
3386 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3387 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3388 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3389 EVT VT = N->getValueType(0);
3390 unsigned NumElems = VT.getVectorNumElements();
3392 if (VT.getSizeInBits() != 128)
3398 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3399 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3400 isUndefOrEqual(N->getMaskElt(1), 7) &&
3401 isUndefOrEqual(N->getMaskElt(2), 2) &&
3402 isUndefOrEqual(N->getMaskElt(3), 3);
3405 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3406 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3408 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3409 EVT VT = N->getValueType(0);
3410 unsigned NumElems = VT.getVectorNumElements();
3412 if (VT.getSizeInBits() != 128)
3418 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3419 isUndefOrEqual(N->getMaskElt(1), 3) &&
3420 isUndefOrEqual(N->getMaskElt(2), 2) &&
3421 isUndefOrEqual(N->getMaskElt(3), 3);
3424 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3425 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3426 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3427 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3429 if (NumElems != 2 && NumElems != 4)
3432 for (unsigned i = 0; i < NumElems/2; ++i)
3433 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3436 for (unsigned i = NumElems/2; i < NumElems; ++i)
3437 if (!isUndefOrEqual(N->getMaskElt(i), i))
3443 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3444 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3445 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3446 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3448 if ((NumElems != 2 && NumElems != 4)
3449 || N->getValueType(0).getSizeInBits() > 128)
3452 for (unsigned i = 0; i < NumElems/2; ++i)
3453 if (!isUndefOrEqual(N->getMaskElt(i), i))
3456 for (unsigned i = 0; i < NumElems/2; ++i)
3457 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3463 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3464 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3465 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3466 bool V2IsSplat = false) {
3467 int NumElts = VT.getVectorNumElements();
3469 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3470 "Unsupported vector type for unpckh");
3472 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3475 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3476 // independently on 128-bit lanes.
3477 unsigned NumLanes = VT.getSizeInBits()/128;
3478 unsigned NumLaneElts = NumElts/NumLanes;
3481 unsigned End = NumLaneElts;
3482 for (unsigned s = 0; s < NumLanes; ++s) {
3483 for (unsigned i = Start, j = s * NumLaneElts;
3487 int BitI1 = Mask[i+1];
3488 if (!isUndefOrEqual(BitI, j))
3491 if (!isUndefOrEqual(BitI1, NumElts))
3494 if (!isUndefOrEqual(BitI1, j + NumElts))
3498 // Process the next 128 bits.
3499 Start += NumLaneElts;
3506 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3507 SmallVector<int, 8> M;
3509 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3512 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3513 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3514 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3515 bool V2IsSplat = false) {
3516 int NumElts = VT.getVectorNumElements();
3518 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3519 "Unsupported vector type for unpckh");
3521 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3524 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3525 // independently on 128-bit lanes.
3526 unsigned NumLanes = VT.getSizeInBits()/128;
3527 unsigned NumLaneElts = NumElts/NumLanes;
3530 unsigned End = NumLaneElts;
3531 for (unsigned l = 0; l != NumLanes; ++l) {
3532 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3533 i != End; i += 2, ++j) {
3535 int BitI1 = Mask[i+1];
3536 if (!isUndefOrEqual(BitI, j))
3539 if (isUndefOrEqual(BitI1, NumElts))
3542 if (!isUndefOrEqual(BitI1, j+NumElts))
3546 // Process the next 128 bits.
3547 Start += NumLaneElts;
3553 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3554 SmallVector<int, 8> M;
3556 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3559 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3560 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3562 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3563 int NumElems = VT.getVectorNumElements();
3564 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3567 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3568 // FIXME: Need a better way to get rid of this, there's no latency difference
3569 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3570 // the former later. We should also remove the "_undef" special mask.
3571 if (NumElems == 4 && VT.getSizeInBits() == 256)
3574 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3575 // independently on 128-bit lanes.
3576 unsigned NumLanes = VT.getSizeInBits() / 128;
3577 unsigned NumLaneElts = NumElems / NumLanes;
3579 for (unsigned s = 0; s < NumLanes; ++s) {
3580 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3581 i != NumLaneElts * (s + 1);
3584 int BitI1 = Mask[i+1];
3586 if (!isUndefOrEqual(BitI, j))
3588 if (!isUndefOrEqual(BitI1, j))
3596 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3597 SmallVector<int, 8> M;
3599 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3602 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3603 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3605 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3606 int NumElems = VT.getVectorNumElements();
3607 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3610 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3612 int BitI1 = Mask[i+1];
3613 if (!isUndefOrEqual(BitI, j))
3615 if (!isUndefOrEqual(BitI1, j))
3621 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3622 SmallVector<int, 8> M;
3624 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3627 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3628 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3629 /// MOVSD, and MOVD, i.e. setting the lowest element.
3630 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3631 if (VT.getVectorElementType().getSizeInBits() < 32)
3634 int NumElts = VT.getVectorNumElements();
3636 if (!isUndefOrEqual(Mask[0], NumElts))
3639 for (int i = 1; i < NumElts; ++i)
3640 if (!isUndefOrEqual(Mask[i], i))
3646 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3647 SmallVector<int, 8> M;
3649 return ::isMOVLMask(M, N->getValueType(0));
3652 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3653 /// as permutations between 128-bit chunks or halves. As an example: this
3655 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3656 /// The first half comes from the second half of V1 and the second half from the
3657 /// the second half of V2.
3658 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3659 const X86Subtarget *Subtarget) {
3660 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3663 // The shuffle result is divided into half A and half B. In total the two
3664 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3665 // B must come from C, D, E or F.
3666 int HalfSize = VT.getVectorNumElements()/2;
3667 bool MatchA = false, MatchB = false;
3669 // Check if A comes from one of C, D, E, F.
3670 for (int Half = 0; Half < 4; ++Half) {
3671 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3677 // Check if B comes from one of C, D, E, F.
3678 for (int Half = 0; Half < 4; ++Half) {
3679 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3685 return MatchA && MatchB;
3688 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3689 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3690 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3691 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3692 EVT VT = SVOp->getValueType(0);
3694 int HalfSize = VT.getVectorNumElements()/2;
3696 int FstHalf = 0, SndHalf = 0;
3697 for (int i = 0; i < HalfSize; ++i) {
3698 if (SVOp->getMaskElt(i) > 0) {
3699 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3703 for (int i = HalfSize; i < HalfSize*2; ++i) {
3704 if (SVOp->getMaskElt(i) > 0) {
3705 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3710 return (FstHalf | (SndHalf << 4));
3713 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3714 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3715 /// Note that VPERMIL mask matching is different depending whether theunderlying
3716 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3717 /// to the same elements of the low, but to the higher half of the source.
3718 /// In VPERMILPD the two lanes could be shuffled independently of each other
3719 /// with the same restriction that lanes can't be crossed.
3720 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3721 const X86Subtarget *Subtarget) {
3722 int NumElts = VT.getVectorNumElements();
3723 int NumLanes = VT.getSizeInBits()/128;
3725 if (!Subtarget->hasAVX())
3728 // Match any permutation of 128-bit vector with 64-bit types
3729 if (NumLanes == 1 && NumElts != 2)
3732 // Only match 256-bit with 32 types
3733 if (VT.getSizeInBits() == 256 && NumElts != 4)
3736 // The mask on the high lane is independent of the low. Both can match
3737 // any element in inside its own lane, but can't cross.
3738 int LaneSize = NumElts/NumLanes;
3739 for (int l = 0; l < NumLanes; ++l)
3740 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3741 int LaneStart = l*LaneSize;
3742 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3749 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3750 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3751 /// Note that VPERMIL mask matching is different depending whether theunderlying
3752 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3753 /// to the same elements of the low, but to the higher half of the source.
3754 /// In VPERMILPD the two lanes could be shuffled independently of each other
3755 /// with the same restriction that lanes can't be crossed.
3756 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3757 const X86Subtarget *Subtarget) {
3758 unsigned NumElts = VT.getVectorNumElements();
3759 unsigned NumLanes = VT.getSizeInBits()/128;
3761 if (!Subtarget->hasAVX())
3764 // Match any permutation of 128-bit vector with 32-bit types
3765 if (NumLanes == 1 && NumElts != 4)
3768 // Only match 256-bit with 32 types
3769 if (VT.getSizeInBits() == 256 && NumElts != 8)
3772 // The mask on the high lane should be the same as the low. Actually,
3773 // they can differ if any of the corresponding index in a lane is undef
3774 // and the other stays in range.
3775 int LaneSize = NumElts/NumLanes;
3776 for (int i = 0; i < LaneSize; ++i) {
3777 int HighElt = i+LaneSize;
3778 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3779 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3781 if (!HighValid || !LowValid)
3783 if (Mask[i] < 0 || Mask[HighElt] < 0)
3785 if (Mask[HighElt]-Mask[i] != LaneSize)
3792 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3793 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3794 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3795 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3796 EVT VT = SVOp->getValueType(0);
3798 int NumElts = VT.getVectorNumElements();
3799 int NumLanes = VT.getSizeInBits()/128;
3800 int LaneSize = NumElts/NumLanes;
3802 // Although the mask is equal for both lanes do it twice to get the cases
3803 // where a mask will match because the same mask element is undef on the
3804 // first half but valid on the second. This would get pathological cases
3805 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3807 for (int l = 0; l < NumLanes; ++l) {
3808 for (int i = 0; i < LaneSize; ++i) {
3809 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3812 if (MaskElt >= LaneSize)
3813 MaskElt -= LaneSize;
3814 Mask |= MaskElt << (i*2);
3821 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3822 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3823 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3824 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3825 EVT VT = SVOp->getValueType(0);
3827 int NumElts = VT.getVectorNumElements();
3828 int NumLanes = VT.getSizeInBits()/128;
3831 int LaneSize = NumElts/NumLanes;
3832 for (int l = 0; l < NumLanes; ++l)
3833 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3834 int MaskElt = SVOp->getMaskElt(i);
3837 Mask |= (MaskElt-l*LaneSize) << i;
3843 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3844 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3845 /// element of vector 2 and the other elements to come from vector 1 in order.
3846 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3847 bool V2IsSplat = false, bool V2IsUndef = false) {
3848 int NumOps = VT.getVectorNumElements();
3849 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3852 if (!isUndefOrEqual(Mask[0], 0))
3855 for (int i = 1; i < NumOps; ++i)
3856 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3857 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3858 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3864 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3865 bool V2IsUndef = false) {
3866 SmallVector<int, 8> M;
3868 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3871 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3872 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3873 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3874 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3875 const X86Subtarget *Subtarget) {
3876 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3879 // The second vector must be undef
3880 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3883 EVT VT = N->getValueType(0);
3884 unsigned NumElems = VT.getVectorNumElements();
3886 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3887 (VT.getSizeInBits() == 256 && NumElems != 8))
3890 // "i+1" is the value the indexed mask element must have
3891 for (unsigned i = 0; i < NumElems; i += 2)
3892 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3893 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3899 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3900 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3901 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3902 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3903 const X86Subtarget *Subtarget) {
3904 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3907 // The second vector must be undef
3908 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3911 EVT VT = N->getValueType(0);
3912 unsigned NumElems = VT.getVectorNumElements();
3914 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3915 (VT.getSizeInBits() == 256 && NumElems != 8))
3918 // "i" is the value the indexed mask element must have
3919 for (unsigned i = 0; i < NumElems; i += 2)
3920 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3921 !isUndefOrEqual(N->getMaskElt(i+1), i))
3927 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3928 /// specifies a shuffle of elements that is suitable for input to 256-bit
3929 /// version of MOVDDUP.
3930 static bool isMOVDDUPYMask(ShuffleVectorSDNode *N,
3931 const X86Subtarget *Subtarget) {
3932 EVT VT = N->getValueType(0);
3933 int NumElts = VT.getVectorNumElements();
3934 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF;
3936 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 ||
3937 !V2IsUndef || NumElts != 4)
3940 for (int i = 0; i != NumElts/2; ++i)
3941 if (!isUndefOrEqual(N->getMaskElt(i), 0))
3943 for (int i = NumElts/2; i != NumElts; ++i)
3944 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2))
3949 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3950 /// specifies a shuffle of elements that is suitable for input to 128-bit
3951 /// version of MOVDDUP.
3952 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3953 EVT VT = N->getValueType(0);
3955 if (VT.getSizeInBits() != 128)
3958 int e = VT.getVectorNumElements() / 2;
3959 for (int i = 0; i < e; ++i)
3960 if (!isUndefOrEqual(N->getMaskElt(i), i))
3962 for (int i = 0; i < e; ++i)
3963 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3968 /// isVEXTRACTF128Index - Return true if the specified
3969 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3970 /// suitable for input to VEXTRACTF128.
3971 bool X86::isVEXTRACTF128Index(SDNode *N) {
3972 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3975 // The index should be aligned on a 128-bit boundary.
3977 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3979 unsigned VL = N->getValueType(0).getVectorNumElements();
3980 unsigned VBits = N->getValueType(0).getSizeInBits();
3981 unsigned ElSize = VBits / VL;
3982 bool Result = (Index * ElSize) % 128 == 0;
3987 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3988 /// operand specifies a subvector insert that is suitable for input to
3990 bool X86::isVINSERTF128Index(SDNode *N) {
3991 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3994 // The index should be aligned on a 128-bit boundary.
3996 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3998 unsigned VL = N->getValueType(0).getVectorNumElements();
3999 unsigned VBits = N->getValueType(0).getSizeInBits();
4000 unsigned ElSize = VBits / VL;
4001 bool Result = (Index * ElSize) % 128 == 0;
4006 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4007 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4008 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
4009 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4010 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
4012 unsigned Shift = (NumOperands == 4) ? 2 : 1;
4014 for (int i = 0; i < NumOperands; ++i) {
4015 int Val = SVOp->getMaskElt(NumOperands-i-1);
4016 if (Val < 0) Val = 0;
4017 if (Val >= NumOperands) Val -= NumOperands;
4019 if (i != NumOperands - 1)
4025 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4026 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4027 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
4028 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4030 // 8 nodes, but we only care about the last 4.
4031 for (unsigned i = 7; i >= 4; --i) {
4032 int Val = SVOp->getMaskElt(i);
4041 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4042 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4043 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4044 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4046 // 8 nodes, but we only care about the first 4.
4047 for (int i = 3; i >= 0; --i) {
4048 int Val = SVOp->getMaskElt(i);
4057 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4058 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4059 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
4060 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4061 EVT VVT = N->getValueType(0);
4062 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
4066 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
4067 Val = SVOp->getMaskElt(i);
4071 assert(Val - i > 0 && "PALIGNR imm should be positive");
4072 return (Val - i) * EltSize;
4075 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4076 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4078 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4079 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4080 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4083 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4085 EVT VecVT = N->getOperand(0).getValueType();
4086 EVT ElVT = VecVT.getVectorElementType();
4088 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4089 return Index / NumElemsPerChunk;
4092 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4093 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4095 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4096 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4097 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4100 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4102 EVT VecVT = N->getValueType(0);
4103 EVT ElVT = VecVT.getVectorElementType();
4105 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4106 return Index / NumElemsPerChunk;
4109 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4111 bool X86::isZeroNode(SDValue Elt) {
4112 return ((isa<ConstantSDNode>(Elt) &&
4113 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4114 (isa<ConstantFPSDNode>(Elt) &&
4115 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4118 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4119 /// their permute mask.
4120 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4121 SelectionDAG &DAG) {
4122 EVT VT = SVOp->getValueType(0);
4123 unsigned NumElems = VT.getVectorNumElements();
4124 SmallVector<int, 8> MaskVec;
4126 for (unsigned i = 0; i != NumElems; ++i) {
4127 int idx = SVOp->getMaskElt(i);
4129 MaskVec.push_back(idx);
4130 else if (idx < (int)NumElems)
4131 MaskVec.push_back(idx + NumElems);
4133 MaskVec.push_back(idx - NumElems);
4135 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4136 SVOp->getOperand(0), &MaskVec[0]);
4139 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4140 /// the two vector operands have swapped position.
4141 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
4142 unsigned NumElems = VT.getVectorNumElements();
4143 for (unsigned i = 0; i != NumElems; ++i) {
4147 else if (idx < (int)NumElems)
4148 Mask[i] = idx + NumElems;
4150 Mask[i] = idx - NumElems;
4154 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4155 /// match movhlps. The lower half elements should come from upper half of
4156 /// V1 (and in order), and the upper half elements should come from the upper
4157 /// half of V2 (and in order).
4158 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4159 EVT VT = Op->getValueType(0);
4160 if (VT.getSizeInBits() != 128)
4162 if (VT.getVectorNumElements() != 4)
4164 for (unsigned i = 0, e = 2; i != e; ++i)
4165 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4167 for (unsigned i = 2; i != 4; ++i)
4168 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4173 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4174 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4176 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4177 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4179 N = N->getOperand(0).getNode();
4180 if (!ISD::isNON_EXTLoad(N))
4183 *LD = cast<LoadSDNode>(N);
4187 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4188 /// match movlp{s|d}. The lower half elements should come from lower half of
4189 /// V1 (and in order), and the upper half elements should come from the upper
4190 /// half of V2 (and in order). And since V1 will become the source of the
4191 /// MOVLP, it must be either a vector load or a scalar load to vector.
4192 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4193 ShuffleVectorSDNode *Op) {
4194 EVT VT = Op->getValueType(0);
4195 if (VT.getSizeInBits() != 128)
4198 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4200 // Is V2 is a vector load, don't do this transformation. We will try to use
4201 // load folding shufps op.
4202 if (ISD::isNON_EXTLoad(V2))
4205 unsigned NumElems = VT.getVectorNumElements();
4207 if (NumElems != 2 && NumElems != 4)
4209 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4210 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4212 for (unsigned i = NumElems/2; i != NumElems; ++i)
4213 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4218 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4220 static bool isSplatVector(SDNode *N) {
4221 if (N->getOpcode() != ISD::BUILD_VECTOR)
4224 SDValue SplatValue = N->getOperand(0);
4225 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4226 if (N->getOperand(i) != SplatValue)
4231 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4232 /// to an zero vector.
4233 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4234 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4235 SDValue V1 = N->getOperand(0);
4236 SDValue V2 = N->getOperand(1);
4237 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4238 for (unsigned i = 0; i != NumElems; ++i) {
4239 int Idx = N->getMaskElt(i);
4240 if (Idx >= (int)NumElems) {
4241 unsigned Opc = V2.getOpcode();
4242 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4244 if (Opc != ISD::BUILD_VECTOR ||
4245 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4247 } else if (Idx >= 0) {
4248 unsigned Opc = V1.getOpcode();
4249 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4251 if (Opc != ISD::BUILD_VECTOR ||
4252 !X86::isZeroNode(V1.getOperand(Idx)))
4259 /// getZeroVector - Returns a vector of specified type with all zero elements.
4261 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4263 assert(VT.isVector() && "Expected a vector type");
4265 // Always build SSE zero vectors as <4 x i32> bitcasted
4266 // to their dest type. This ensures they get CSE'd.
4268 if (VT.getSizeInBits() == 128) { // SSE
4269 if (HasSSE2) { // SSE2
4270 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4271 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4273 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4274 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4276 } else if (VT.getSizeInBits() == 256) { // AVX
4277 // 256-bit logic and arithmetic instructions in AVX are
4278 // all floating-point, no support for integer ops. Default
4279 // to emitting fp zeroed vectors then.
4280 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4281 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4282 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4284 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4287 /// getOnesVector - Returns a vector of specified type with all bits set.
4288 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4289 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4290 /// original type, ensuring they get CSE'd.
4291 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4292 assert(VT.isVector() && "Expected a vector type");
4293 assert((VT.is128BitVector() || VT.is256BitVector())
4294 && "Expected a 128-bit or 256-bit vector type");
4296 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4297 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4298 Cst, Cst, Cst, Cst);
4300 if (VT.is256BitVector()) {
4301 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4302 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4303 Vec = Insert128BitVector(InsV, Vec,
4304 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4307 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4310 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4311 /// that point to V2 points to its first element.
4312 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4313 EVT VT = SVOp->getValueType(0);
4314 unsigned NumElems = VT.getVectorNumElements();
4316 bool Changed = false;
4317 SmallVector<int, 8> MaskVec;
4318 SVOp->getMask(MaskVec);
4320 for (unsigned i = 0; i != NumElems; ++i) {
4321 if (MaskVec[i] > (int)NumElems) {
4322 MaskVec[i] = NumElems;
4327 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4328 SVOp->getOperand(1), &MaskVec[0]);
4329 return SDValue(SVOp, 0);
4332 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4333 /// operation of specified width.
4334 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4336 unsigned NumElems = VT.getVectorNumElements();
4337 SmallVector<int, 8> Mask;
4338 Mask.push_back(NumElems);
4339 for (unsigned i = 1; i != NumElems; ++i)
4341 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4344 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4345 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4347 unsigned NumElems = VT.getVectorNumElements();
4348 SmallVector<int, 8> Mask;
4349 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4351 Mask.push_back(i + NumElems);
4353 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4356 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4357 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4359 unsigned NumElems = VT.getVectorNumElements();
4360 unsigned Half = NumElems/2;
4361 SmallVector<int, 8> Mask;
4362 for (unsigned i = 0; i != Half; ++i) {
4363 Mask.push_back(i + Half);
4364 Mask.push_back(i + NumElems + Half);
4366 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4369 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4370 // a generic shuffle instruction because the target has no such instructions.
4371 // Generate shuffles which repeat i16 and i8 several times until they can be
4372 // represented by v4f32 and then be manipulated by target suported shuffles.
4373 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4374 EVT VT = V.getValueType();
4375 int NumElems = VT.getVectorNumElements();
4376 DebugLoc dl = V.getDebugLoc();
4378 while (NumElems > 4) {
4379 if (EltNo < NumElems/2) {
4380 V = getUnpackl(DAG, dl, VT, V, V);
4382 V = getUnpackh(DAG, dl, VT, V, V);
4383 EltNo -= NumElems/2;
4390 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4391 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4392 EVT VT = V.getValueType();
4393 DebugLoc dl = V.getDebugLoc();
4394 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4395 && "Vector size not supported");
4397 if (VT.getSizeInBits() == 128) {
4398 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4399 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4400 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4403 // To use VPERMILPS to splat scalars, the second half of indicies must
4404 // refer to the higher part, which is a duplication of the lower one,
4405 // because VPERMILPS can only handle in-lane permutations.
4406 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4407 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4409 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4410 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4414 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4417 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4418 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4419 EVT SrcVT = SV->getValueType(0);
4420 SDValue V1 = SV->getOperand(0);
4421 DebugLoc dl = SV->getDebugLoc();
4423 int EltNo = SV->getSplatIndex();
4424 int NumElems = SrcVT.getVectorNumElements();
4425 unsigned Size = SrcVT.getSizeInBits();
4427 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4428 "Unknown how to promote splat for type");
4430 // Extract the 128-bit part containing the splat element and update
4431 // the splat element index when it refers to the higher register.
4433 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4434 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4436 EltNo -= NumElems/2;
4439 // All i16 and i8 vector types can't be used directly by a generic shuffle
4440 // instruction because the target has no such instruction. Generate shuffles
4441 // which repeat i16 and i8 several times until they fit in i32, and then can
4442 // be manipulated by target suported shuffles.
4443 EVT EltVT = SrcVT.getVectorElementType();
4444 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4445 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4447 // Recreate the 256-bit vector and place the same 128-bit vector
4448 // into the low and high part. This is necessary because we want
4449 // to use VPERM* to shuffle the vectors
4451 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4452 DAG.getConstant(0, MVT::i32), DAG, dl);
4453 V1 = Insert128BitVector(InsV, V1,
4454 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4457 return getLegalSplat(DAG, V1, EltNo);
4460 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4461 /// vector of zero or undef vector. This produces a shuffle where the low
4462 /// element of V2 is swizzled into the zero/undef vector, landing at element
4463 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4464 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4465 bool isZero, bool HasSSE2,
4466 SelectionDAG &DAG) {
4467 EVT VT = V2.getValueType();
4469 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4470 unsigned NumElems = VT.getVectorNumElements();
4471 SmallVector<int, 16> MaskVec;
4472 for (unsigned i = 0; i != NumElems; ++i)
4473 // If this is the insertion idx, put the low elt of V2 here.
4474 MaskVec.push_back(i == Idx ? NumElems : i);
4475 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4478 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4479 /// element of the result of the vector shuffle.
4480 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4483 return SDValue(); // Limit search depth.
4485 SDValue V = SDValue(N, 0);
4486 EVT VT = V.getValueType();
4487 unsigned Opcode = V.getOpcode();
4489 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4490 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4491 Index = SV->getMaskElt(Index);
4494 return DAG.getUNDEF(VT.getVectorElementType());
4496 int NumElems = VT.getVectorNumElements();
4497 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4498 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4501 // Recurse into target specific vector shuffles to find scalars.
4502 if (isTargetShuffle(Opcode)) {
4503 int NumElems = VT.getVectorNumElements();
4504 SmallVector<unsigned, 16> ShuffleMask;
4508 case X86ISD::SHUFPS:
4509 case X86ISD::SHUFPD:
4510 ImmN = N->getOperand(N->getNumOperands()-1);
4511 DecodeSHUFPSMask(NumElems,
4512 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4515 case X86ISD::PUNPCKHBW:
4516 case X86ISD::PUNPCKHWD:
4517 case X86ISD::PUNPCKHDQ:
4518 case X86ISD::PUNPCKHQDQ:
4519 DecodePUNPCKHMask(NumElems, ShuffleMask);
4521 case X86ISD::UNPCKHPS:
4522 case X86ISD::UNPCKHPD:
4523 case X86ISD::VUNPCKHPSY:
4524 case X86ISD::VUNPCKHPDY:
4525 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4527 case X86ISD::PUNPCKLBW:
4528 case X86ISD::PUNPCKLWD:
4529 case X86ISD::PUNPCKLDQ:
4530 case X86ISD::PUNPCKLQDQ:
4531 DecodePUNPCKLMask(VT, ShuffleMask);
4533 case X86ISD::UNPCKLPS:
4534 case X86ISD::UNPCKLPD:
4535 case X86ISD::VUNPCKLPSY:
4536 case X86ISD::VUNPCKLPDY:
4537 DecodeUNPCKLPMask(VT, ShuffleMask);
4539 case X86ISD::MOVHLPS:
4540 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4542 case X86ISD::MOVLHPS:
4543 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4545 case X86ISD::PSHUFD:
4546 ImmN = N->getOperand(N->getNumOperands()-1);
4547 DecodePSHUFMask(NumElems,
4548 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4551 case X86ISD::PSHUFHW:
4552 ImmN = N->getOperand(N->getNumOperands()-1);
4553 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4556 case X86ISD::PSHUFLW:
4557 ImmN = N->getOperand(N->getNumOperands()-1);
4558 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4562 case X86ISD::MOVSD: {
4563 // The index 0 always comes from the first element of the second source,
4564 // this is why MOVSS and MOVSD are used in the first place. The other
4565 // elements come from the other positions of the first source vector.
4566 unsigned OpNum = (Index == 0) ? 1 : 0;
4567 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4570 case X86ISD::VPERMILPS:
4571 ImmN = N->getOperand(N->getNumOperands()-1);
4572 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4575 case X86ISD::VPERMILPSY:
4576 ImmN = N->getOperand(N->getNumOperands()-1);
4577 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4580 case X86ISD::VPERMILPD:
4581 ImmN = N->getOperand(N->getNumOperands()-1);
4582 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4585 case X86ISD::VPERMILPDY:
4586 ImmN = N->getOperand(N->getNumOperands()-1);
4587 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4590 case X86ISD::VPERM2F128:
4591 ImmN = N->getOperand(N->getNumOperands()-1);
4592 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4596 assert("not implemented for target shuffle node");
4600 Index = ShuffleMask[Index];
4602 return DAG.getUNDEF(VT.getVectorElementType());
4604 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4605 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4609 // Actual nodes that may contain scalar elements
4610 if (Opcode == ISD::BITCAST) {
4611 V = V.getOperand(0);
4612 EVT SrcVT = V.getValueType();
4613 unsigned NumElems = VT.getVectorNumElements();
4615 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4619 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4620 return (Index == 0) ? V.getOperand(0)
4621 : DAG.getUNDEF(VT.getVectorElementType());
4623 if (V.getOpcode() == ISD::BUILD_VECTOR)
4624 return V.getOperand(Index);
4629 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4630 /// shuffle operation which come from a consecutively from a zero. The
4631 /// search can start in two different directions, from left or right.
4633 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4634 bool ZerosFromLeft, SelectionDAG &DAG) {
4637 while (i < NumElems) {
4638 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4639 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4640 if (!(Elt.getNode() &&
4641 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4649 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4650 /// MaskE correspond consecutively to elements from one of the vector operands,
4651 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4653 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4654 int OpIdx, int NumElems, unsigned &OpNum) {
4655 bool SeenV1 = false;
4656 bool SeenV2 = false;
4658 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4659 int Idx = SVOp->getMaskElt(i);
4660 // Ignore undef indicies
4669 // Only accept consecutive elements from the same vector
4670 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4674 OpNum = SeenV1 ? 0 : 1;
4678 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4679 /// logical left shift of a vector.
4680 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4681 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4682 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4683 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4684 false /* check zeros from right */, DAG);
4690 // Considering the elements in the mask that are not consecutive zeros,
4691 // check if they consecutively come from only one of the source vectors.
4693 // V1 = {X, A, B, C} 0
4695 // vector_shuffle V1, V2 <1, 2, 3, X>
4697 if (!isShuffleMaskConsecutive(SVOp,
4698 0, // Mask Start Index
4699 NumElems-NumZeros-1, // Mask End Index
4700 NumZeros, // Where to start looking in the src vector
4701 NumElems, // Number of elements in vector
4702 OpSrc)) // Which source operand ?
4707 ShVal = SVOp->getOperand(OpSrc);
4711 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4712 /// logical left shift of a vector.
4713 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4714 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4715 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4716 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4717 true /* check zeros from left */, DAG);
4723 // Considering the elements in the mask that are not consecutive zeros,
4724 // check if they consecutively come from only one of the source vectors.
4726 // 0 { A, B, X, X } = V2
4728 // vector_shuffle V1, V2 <X, X, 4, 5>
4730 if (!isShuffleMaskConsecutive(SVOp,
4731 NumZeros, // Mask Start Index
4732 NumElems-1, // Mask End Index
4733 0, // Where to start looking in the src vector
4734 NumElems, // Number of elements in vector
4735 OpSrc)) // Which source operand ?
4740 ShVal = SVOp->getOperand(OpSrc);
4744 /// isVectorShift - Returns true if the shuffle can be implemented as a
4745 /// logical left or right shift of a vector.
4746 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4747 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4748 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4749 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4755 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4757 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4758 unsigned NumNonZero, unsigned NumZero,
4760 const TargetLowering &TLI) {
4764 DebugLoc dl = Op.getDebugLoc();
4767 for (unsigned i = 0; i < 16; ++i) {
4768 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4769 if (ThisIsNonZero && First) {
4771 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4773 V = DAG.getUNDEF(MVT::v8i16);
4778 SDValue ThisElt(0, 0), LastElt(0, 0);
4779 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4780 if (LastIsNonZero) {
4781 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4782 MVT::i16, Op.getOperand(i-1));
4784 if (ThisIsNonZero) {
4785 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4786 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4787 ThisElt, DAG.getConstant(8, MVT::i8));
4789 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4793 if (ThisElt.getNode())
4794 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4795 DAG.getIntPtrConstant(i/2));
4799 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4802 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4804 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4805 unsigned NumNonZero, unsigned NumZero,
4807 const TargetLowering &TLI) {
4811 DebugLoc dl = Op.getDebugLoc();
4814 for (unsigned i = 0; i < 8; ++i) {
4815 bool isNonZero = (NonZeros & (1 << i)) != 0;
4819 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4821 V = DAG.getUNDEF(MVT::v8i16);
4824 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4825 MVT::v8i16, V, Op.getOperand(i),
4826 DAG.getIntPtrConstant(i));
4833 /// getVShift - Return a vector logical shift node.
4835 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4836 unsigned NumBits, SelectionDAG &DAG,
4837 const TargetLowering &TLI, DebugLoc dl) {
4838 EVT ShVT = MVT::v2i64;
4839 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4840 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4841 return DAG.getNode(ISD::BITCAST, dl, VT,
4842 DAG.getNode(Opc, dl, ShVT, SrcOp,
4843 DAG.getConstant(NumBits,
4844 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4848 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4849 SelectionDAG &DAG) const {
4851 // Check if the scalar load can be widened into a vector load. And if
4852 // the address is "base + cst" see if the cst can be "absorbed" into
4853 // the shuffle mask.
4854 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4855 SDValue Ptr = LD->getBasePtr();
4856 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4858 EVT PVT = LD->getValueType(0);
4859 if (PVT != MVT::i32 && PVT != MVT::f32)
4864 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4865 FI = FINode->getIndex();
4867 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4868 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4869 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4870 Offset = Ptr.getConstantOperandVal(1);
4871 Ptr = Ptr.getOperand(0);
4876 // FIXME: 256-bit vector instructions don't require a strict alignment,
4877 // improve this code to support it better.
4878 unsigned RequiredAlign = VT.getSizeInBits()/8;
4879 SDValue Chain = LD->getChain();
4880 // Make sure the stack object alignment is at least 16 or 32.
4881 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4882 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4883 if (MFI->isFixedObjectIndex(FI)) {
4884 // Can't change the alignment. FIXME: It's possible to compute
4885 // the exact stack offset and reference FI + adjust offset instead.
4886 // If someone *really* cares about this. That's the way to implement it.
4889 MFI->setObjectAlignment(FI, RequiredAlign);
4893 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4894 // Ptr + (Offset & ~15).
4897 if ((Offset % RequiredAlign) & 3)
4899 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4901 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4902 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4904 int EltNo = (Offset - StartOffset) >> 2;
4905 int NumElems = VT.getVectorNumElements();
4907 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4908 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4909 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4910 LD->getPointerInfo().getWithOffset(StartOffset),
4913 // Canonicalize it to a v4i32 or v8i32 shuffle.
4914 SmallVector<int, 8> Mask;
4915 for (int i = 0; i < NumElems; ++i)
4916 Mask.push_back(EltNo);
4918 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4919 return DAG.getNode(ISD::BITCAST, dl, NVT,
4920 DAG.getVectorShuffle(CanonVT, dl, V1,
4921 DAG.getUNDEF(CanonVT),&Mask[0]));
4927 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4928 /// vector of type 'VT', see if the elements can be replaced by a single large
4929 /// load which has the same value as a build_vector whose operands are 'elts'.
4931 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4933 /// FIXME: we'd also like to handle the case where the last elements are zero
4934 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4935 /// There's even a handy isZeroNode for that purpose.
4936 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4937 DebugLoc &DL, SelectionDAG &DAG) {
4938 EVT EltVT = VT.getVectorElementType();
4939 unsigned NumElems = Elts.size();
4941 LoadSDNode *LDBase = NULL;
4942 unsigned LastLoadedElt = -1U;
4944 // For each element in the initializer, see if we've found a load or an undef.
4945 // If we don't find an initial load element, or later load elements are
4946 // non-consecutive, bail out.
4947 for (unsigned i = 0; i < NumElems; ++i) {
4948 SDValue Elt = Elts[i];
4950 if (!Elt.getNode() ||
4951 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4954 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4956 LDBase = cast<LoadSDNode>(Elt.getNode());
4960 if (Elt.getOpcode() == ISD::UNDEF)
4963 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4964 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4969 // If we have found an entire vector of loads and undefs, then return a large
4970 // load of the entire vector width starting at the base pointer. If we found
4971 // consecutive loads for the low half, generate a vzext_load node.
4972 if (LastLoadedElt == NumElems - 1) {
4973 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4974 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4975 LDBase->getPointerInfo(),
4976 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4977 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4978 LDBase->getPointerInfo(),
4979 LDBase->isVolatile(), LDBase->isNonTemporal(),
4980 LDBase->getAlignment());
4981 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4982 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4983 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4984 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4985 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4987 LDBase->getMemOperand());
4988 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4994 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4995 DebugLoc dl = Op.getDebugLoc();
4997 EVT VT = Op.getValueType();
4998 EVT ExtVT = VT.getVectorElementType();
4999 unsigned NumElems = Op.getNumOperands();
5001 // Vectors containing all zeros can be matched by pxor and xorps later
5002 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5003 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5004 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5005 if (Op.getValueType() == MVT::v4i32 ||
5006 Op.getValueType() == MVT::v8i32)
5009 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
5012 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5013 // vectors or broken into v4i32 operations on 256-bit vectors.
5014 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5015 if (Op.getValueType() == MVT::v4i32)
5018 return getOnesVector(Op.getValueType(), DAG, dl);
5021 unsigned EVTBits = ExtVT.getSizeInBits();
5023 unsigned NumZero = 0;
5024 unsigned NumNonZero = 0;
5025 unsigned NonZeros = 0;
5026 bool IsAllConstants = true;
5027 SmallSet<SDValue, 8> Values;
5028 for (unsigned i = 0; i < NumElems; ++i) {
5029 SDValue Elt = Op.getOperand(i);
5030 if (Elt.getOpcode() == ISD::UNDEF)
5033 if (Elt.getOpcode() != ISD::Constant &&
5034 Elt.getOpcode() != ISD::ConstantFP)
5035 IsAllConstants = false;
5036 if (X86::isZeroNode(Elt))
5039 NonZeros |= (1 << i);
5044 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5045 if (NumNonZero == 0)
5046 return DAG.getUNDEF(VT);
5048 // Special case for single non-zero, non-undef, element.
5049 if (NumNonZero == 1) {
5050 unsigned Idx = CountTrailingZeros_32(NonZeros);
5051 SDValue Item = Op.getOperand(Idx);
5053 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5054 // the value are obviously zero, truncate the value to i32 and do the
5055 // insertion that way. Only do this if the value is non-constant or if the
5056 // value is a constant being inserted into element 0. It is cheaper to do
5057 // a constant pool load than it is to do a movd + shuffle.
5058 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5059 (!IsAllConstants || Idx == 0)) {
5060 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5062 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5063 EVT VecVT = MVT::v4i32;
5064 unsigned VecElts = 4;
5066 // Truncate the value (which may itself be a constant) to i32, and
5067 // convert it to a vector with movd (S2V+shuffle to zero extend).
5068 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5069 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5070 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5071 Subtarget->hasSSE2(), DAG);
5073 // Now we have our 32-bit value zero extended in the low element of
5074 // a vector. If Idx != 0, swizzle it into place.
5076 SmallVector<int, 4> Mask;
5077 Mask.push_back(Idx);
5078 for (unsigned i = 1; i != VecElts; ++i)
5080 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5081 DAG.getUNDEF(Item.getValueType()),
5084 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5088 // If we have a constant or non-constant insertion into the low element of
5089 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5090 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5091 // depending on what the source datatype is.
5094 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5095 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5096 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5097 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5098 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5099 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
5101 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5102 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5103 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5104 EVT MiddleVT = MVT::v4i32;
5105 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5106 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5107 Subtarget->hasSSE2(), DAG);
5108 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5112 // Is it a vector logical left shift?
5113 if (NumElems == 2 && Idx == 1 &&
5114 X86::isZeroNode(Op.getOperand(0)) &&
5115 !X86::isZeroNode(Op.getOperand(1))) {
5116 unsigned NumBits = VT.getSizeInBits();
5117 return getVShift(true, VT,
5118 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5119 VT, Op.getOperand(1)),
5120 NumBits/2, DAG, *this, dl);
5123 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5126 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5127 // is a non-constant being inserted into an element other than the low one,
5128 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5129 // movd/movss) to move this into the low element, then shuffle it into
5131 if (EVTBits == 32) {
5132 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5134 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5135 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5136 Subtarget->hasSSE2(), DAG);
5137 SmallVector<int, 8> MaskVec;
5138 for (unsigned i = 0; i < NumElems; i++)
5139 MaskVec.push_back(i == Idx ? 0 : 1);
5140 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5144 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5145 if (Values.size() == 1) {
5146 if (EVTBits == 32) {
5147 // Instead of a shuffle like this:
5148 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5149 // Check if it's possible to issue this instead.
5150 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5151 unsigned Idx = CountTrailingZeros_32(NonZeros);
5152 SDValue Item = Op.getOperand(Idx);
5153 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5154 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5159 // A vector full of immediates; various special cases are already
5160 // handled, so this is best done with a single constant-pool load.
5164 // For AVX-length vectors, build the individual 128-bit pieces and use
5165 // shuffles to put them in place.
5166 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5167 SmallVector<SDValue, 32> V;
5168 for (unsigned i = 0; i < NumElems; ++i)
5169 V.push_back(Op.getOperand(i));
5171 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5173 // Build both the lower and upper subvector.
5174 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5175 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5178 // Recreate the wider vector with the lower and upper part.
5179 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5180 DAG.getConstant(0, MVT::i32), DAG, dl);
5181 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5185 // Let legalizer expand 2-wide build_vectors.
5186 if (EVTBits == 64) {
5187 if (NumNonZero == 1) {
5188 // One half is zero or undef.
5189 unsigned Idx = CountTrailingZeros_32(NonZeros);
5190 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5191 Op.getOperand(Idx));
5192 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5193 Subtarget->hasSSE2(), DAG);
5198 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5199 if (EVTBits == 8 && NumElems == 16) {
5200 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5202 if (V.getNode()) return V;
5205 if (EVTBits == 16 && NumElems == 8) {
5206 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5208 if (V.getNode()) return V;
5211 // If element VT is == 32 bits, turn it into a number of shuffles.
5212 SmallVector<SDValue, 8> V;
5214 if (NumElems == 4 && NumZero > 0) {
5215 for (unsigned i = 0; i < 4; ++i) {
5216 bool isZero = !(NonZeros & (1 << i));
5218 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5220 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5223 for (unsigned i = 0; i < 2; ++i) {
5224 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5227 V[i] = V[i*2]; // Must be a zero vector.
5230 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5233 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5236 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5241 SmallVector<int, 8> MaskVec;
5242 bool Reverse = (NonZeros & 0x3) == 2;
5243 for (unsigned i = 0; i < 2; ++i)
5244 MaskVec.push_back(Reverse ? 1-i : i);
5245 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5246 for (unsigned i = 0; i < 2; ++i)
5247 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5248 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5251 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5252 // Check for a build vector of consecutive loads.
5253 for (unsigned i = 0; i < NumElems; ++i)
5254 V[i] = Op.getOperand(i);
5256 // Check for elements which are consecutive loads.
5257 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5261 // For SSE 4.1, use insertps to put the high elements into the low element.
5262 if (getSubtarget()->hasSSE41()) {
5264 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5265 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5267 Result = DAG.getUNDEF(VT);
5269 for (unsigned i = 1; i < NumElems; ++i) {
5270 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5271 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5272 Op.getOperand(i), DAG.getIntPtrConstant(i));
5277 // Otherwise, expand into a number of unpckl*, start by extending each of
5278 // our (non-undef) elements to the full vector width with the element in the
5279 // bottom slot of the vector (which generates no code for SSE).
5280 for (unsigned i = 0; i < NumElems; ++i) {
5281 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5282 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5284 V[i] = DAG.getUNDEF(VT);
5287 // Next, we iteratively mix elements, e.g. for v4f32:
5288 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5289 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5290 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5291 unsigned EltStride = NumElems >> 1;
5292 while (EltStride != 0) {
5293 for (unsigned i = 0; i < EltStride; ++i) {
5294 // If V[i+EltStride] is undef and this is the first round of mixing,
5295 // then it is safe to just drop this shuffle: V[i] is already in the
5296 // right place, the one element (since it's the first round) being
5297 // inserted as undef can be dropped. This isn't safe for successive
5298 // rounds because they will permute elements within both vectors.
5299 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5300 EltStride == NumElems/2)
5303 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5312 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5313 // them in a MMX register. This is better than doing a stack convert.
5314 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5315 DebugLoc dl = Op.getDebugLoc();
5316 EVT ResVT = Op.getValueType();
5318 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5319 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5321 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5322 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5323 InVec = Op.getOperand(1);
5324 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5325 unsigned NumElts = ResVT.getVectorNumElements();
5326 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5327 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5328 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5330 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5331 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5332 Mask[0] = 0; Mask[1] = 2;
5333 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5335 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5338 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5339 // to create 256-bit vectors from two other 128-bit ones.
5340 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5341 DebugLoc dl = Op.getDebugLoc();
5342 EVT ResVT = Op.getValueType();
5344 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5346 SDValue V1 = Op.getOperand(0);
5347 SDValue V2 = Op.getOperand(1);
5348 unsigned NumElems = ResVT.getVectorNumElements();
5350 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5351 DAG.getConstant(0, MVT::i32), DAG, dl);
5352 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5357 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5358 EVT ResVT = Op.getValueType();
5360 assert(Op.getNumOperands() == 2);
5361 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5362 "Unsupported CONCAT_VECTORS for value type");
5364 // We support concatenate two MMX registers and place them in a MMX register.
5365 // This is better than doing a stack convert.
5366 if (ResVT.is128BitVector())
5367 return LowerMMXCONCAT_VECTORS(Op, DAG);
5369 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5370 // from two other 128-bit ones.
5371 return LowerAVXCONCAT_VECTORS(Op, DAG);
5374 // v8i16 shuffles - Prefer shuffles in the following order:
5375 // 1. [all] pshuflw, pshufhw, optional move
5376 // 2. [ssse3] 1 x pshufb
5377 // 3. [ssse3] 2 x pshufb + 1 x por
5378 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5380 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5381 SelectionDAG &DAG) const {
5382 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5383 SDValue V1 = SVOp->getOperand(0);
5384 SDValue V2 = SVOp->getOperand(1);
5385 DebugLoc dl = SVOp->getDebugLoc();
5386 SmallVector<int, 8> MaskVals;
5388 // Determine if more than 1 of the words in each of the low and high quadwords
5389 // of the result come from the same quadword of one of the two inputs. Undef
5390 // mask values count as coming from any quadword, for better codegen.
5391 SmallVector<unsigned, 4> LoQuad(4);
5392 SmallVector<unsigned, 4> HiQuad(4);
5393 BitVector InputQuads(4);
5394 for (unsigned i = 0; i < 8; ++i) {
5395 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5396 int EltIdx = SVOp->getMaskElt(i);
5397 MaskVals.push_back(EltIdx);
5406 InputQuads.set(EltIdx / 4);
5409 int BestLoQuad = -1;
5410 unsigned MaxQuad = 1;
5411 for (unsigned i = 0; i < 4; ++i) {
5412 if (LoQuad[i] > MaxQuad) {
5414 MaxQuad = LoQuad[i];
5418 int BestHiQuad = -1;
5420 for (unsigned i = 0; i < 4; ++i) {
5421 if (HiQuad[i] > MaxQuad) {
5423 MaxQuad = HiQuad[i];
5427 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5428 // of the two input vectors, shuffle them into one input vector so only a
5429 // single pshufb instruction is necessary. If There are more than 2 input
5430 // quads, disable the next transformation since it does not help SSSE3.
5431 bool V1Used = InputQuads[0] || InputQuads[1];
5432 bool V2Used = InputQuads[2] || InputQuads[3];
5433 if (Subtarget->hasSSSE3()) {
5434 if (InputQuads.count() == 2 && V1Used && V2Used) {
5435 BestLoQuad = InputQuads.find_first();
5436 BestHiQuad = InputQuads.find_next(BestLoQuad);
5438 if (InputQuads.count() > 2) {
5444 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5445 // the shuffle mask. If a quad is scored as -1, that means that it contains
5446 // words from all 4 input quadwords.
5448 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5449 SmallVector<int, 8> MaskV;
5450 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5451 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5452 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5453 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5454 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5455 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5457 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5458 // source words for the shuffle, to aid later transformations.
5459 bool AllWordsInNewV = true;
5460 bool InOrder[2] = { true, true };
5461 for (unsigned i = 0; i != 8; ++i) {
5462 int idx = MaskVals[i];
5464 InOrder[i/4] = false;
5465 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5467 AllWordsInNewV = false;
5471 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5472 if (AllWordsInNewV) {
5473 for (int i = 0; i != 8; ++i) {
5474 int idx = MaskVals[i];
5477 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5478 if ((idx != i) && idx < 4)
5480 if ((idx != i) && idx > 3)
5489 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5490 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5491 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5492 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5493 unsigned TargetMask = 0;
5494 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5495 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5496 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5497 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5498 V1 = NewV.getOperand(0);
5499 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5503 // If we have SSSE3, and all words of the result are from 1 input vector,
5504 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5505 // is present, fall back to case 4.
5506 if (Subtarget->hasSSSE3()) {
5507 SmallVector<SDValue,16> pshufbMask;
5509 // If we have elements from both input vectors, set the high bit of the
5510 // shuffle mask element to zero out elements that come from V2 in the V1
5511 // mask, and elements that come from V1 in the V2 mask, so that the two
5512 // results can be OR'd together.
5513 bool TwoInputs = V1Used && V2Used;
5514 for (unsigned i = 0; i != 8; ++i) {
5515 int EltIdx = MaskVals[i] * 2;
5516 if (TwoInputs && (EltIdx >= 16)) {
5517 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5518 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5521 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5522 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5524 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5525 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5526 DAG.getNode(ISD::BUILD_VECTOR, dl,
5527 MVT::v16i8, &pshufbMask[0], 16));
5529 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5531 // Calculate the shuffle mask for the second input, shuffle it, and
5532 // OR it with the first shuffled input.
5534 for (unsigned i = 0; i != 8; ++i) {
5535 int EltIdx = MaskVals[i] * 2;
5537 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5538 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5541 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5542 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5544 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5545 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5546 DAG.getNode(ISD::BUILD_VECTOR, dl,
5547 MVT::v16i8, &pshufbMask[0], 16));
5548 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5549 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5552 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5553 // and update MaskVals with new element order.
5554 BitVector InOrder(8);
5555 if (BestLoQuad >= 0) {
5556 SmallVector<int, 8> MaskV;
5557 for (int i = 0; i != 4; ++i) {
5558 int idx = MaskVals[i];
5560 MaskV.push_back(-1);
5562 } else if ((idx / 4) == BestLoQuad) {
5563 MaskV.push_back(idx & 3);
5566 MaskV.push_back(-1);
5569 for (unsigned i = 4; i != 8; ++i)
5571 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5574 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5575 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5577 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5581 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5582 // and update MaskVals with the new element order.
5583 if (BestHiQuad >= 0) {
5584 SmallVector<int, 8> MaskV;
5585 for (unsigned i = 0; i != 4; ++i)
5587 for (unsigned i = 4; i != 8; ++i) {
5588 int idx = MaskVals[i];
5590 MaskV.push_back(-1);
5592 } else if ((idx / 4) == BestHiQuad) {
5593 MaskV.push_back((idx & 3) + 4);
5596 MaskV.push_back(-1);
5599 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5602 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5603 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5605 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5609 // In case BestHi & BestLo were both -1, which means each quadword has a word
5610 // from each of the four input quadwords, calculate the InOrder bitvector now
5611 // before falling through to the insert/extract cleanup.
5612 if (BestLoQuad == -1 && BestHiQuad == -1) {
5614 for (int i = 0; i != 8; ++i)
5615 if (MaskVals[i] < 0 || MaskVals[i] == i)
5619 // The other elements are put in the right place using pextrw and pinsrw.
5620 for (unsigned i = 0; i != 8; ++i) {
5623 int EltIdx = MaskVals[i];
5626 SDValue ExtOp = (EltIdx < 8)
5627 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5628 DAG.getIntPtrConstant(EltIdx))
5629 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5630 DAG.getIntPtrConstant(EltIdx - 8));
5631 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5632 DAG.getIntPtrConstant(i));
5637 // v16i8 shuffles - Prefer shuffles in the following order:
5638 // 1. [ssse3] 1 x pshufb
5639 // 2. [ssse3] 2 x pshufb + 1 x por
5640 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5642 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5644 const X86TargetLowering &TLI) {
5645 SDValue V1 = SVOp->getOperand(0);
5646 SDValue V2 = SVOp->getOperand(1);
5647 DebugLoc dl = SVOp->getDebugLoc();
5648 SmallVector<int, 16> MaskVals;
5649 SVOp->getMask(MaskVals);
5651 // If we have SSSE3, case 1 is generated when all result bytes come from
5652 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5653 // present, fall back to case 3.
5654 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5657 for (unsigned i = 0; i < 16; ++i) {
5658 int EltIdx = MaskVals[i];
5667 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5668 if (TLI.getSubtarget()->hasSSSE3()) {
5669 SmallVector<SDValue,16> pshufbMask;
5671 // If all result elements are from one input vector, then only translate
5672 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5674 // Otherwise, we have elements from both input vectors, and must zero out
5675 // elements that come from V2 in the first mask, and V1 in the second mask
5676 // so that we can OR them together.
5677 bool TwoInputs = !(V1Only || V2Only);
5678 for (unsigned i = 0; i != 16; ++i) {
5679 int EltIdx = MaskVals[i];
5680 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5681 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5684 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5686 // If all the elements are from V2, assign it to V1 and return after
5687 // building the first pshufb.
5690 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5691 DAG.getNode(ISD::BUILD_VECTOR, dl,
5692 MVT::v16i8, &pshufbMask[0], 16));
5696 // Calculate the shuffle mask for the second input, shuffle it, and
5697 // OR it with the first shuffled input.
5699 for (unsigned i = 0; i != 16; ++i) {
5700 int EltIdx = MaskVals[i];
5702 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5705 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5707 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5708 DAG.getNode(ISD::BUILD_VECTOR, dl,
5709 MVT::v16i8, &pshufbMask[0], 16));
5710 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5713 // No SSSE3 - Calculate in place words and then fix all out of place words
5714 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5715 // the 16 different words that comprise the two doublequadword input vectors.
5716 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5717 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5718 SDValue NewV = V2Only ? V2 : V1;
5719 for (int i = 0; i != 8; ++i) {
5720 int Elt0 = MaskVals[i*2];
5721 int Elt1 = MaskVals[i*2+1];
5723 // This word of the result is all undef, skip it.
5724 if (Elt0 < 0 && Elt1 < 0)
5727 // This word of the result is already in the correct place, skip it.
5728 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5730 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5733 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5734 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5737 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5738 // using a single extract together, load it and store it.
5739 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5740 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5741 DAG.getIntPtrConstant(Elt1 / 2));
5742 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5743 DAG.getIntPtrConstant(i));
5747 // If Elt1 is defined, extract it from the appropriate source. If the
5748 // source byte is not also odd, shift the extracted word left 8 bits
5749 // otherwise clear the bottom 8 bits if we need to do an or.
5751 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5752 DAG.getIntPtrConstant(Elt1 / 2));
5753 if ((Elt1 & 1) == 0)
5754 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5756 TLI.getShiftAmountTy(InsElt.getValueType())));
5758 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5759 DAG.getConstant(0xFF00, MVT::i16));
5761 // If Elt0 is defined, extract it from the appropriate source. If the
5762 // source byte is not also even, shift the extracted word right 8 bits. If
5763 // Elt1 was also defined, OR the extracted values together before
5764 // inserting them in the result.
5766 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5767 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5768 if ((Elt0 & 1) != 0)
5769 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5771 TLI.getShiftAmountTy(InsElt0.getValueType())));
5773 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5774 DAG.getConstant(0x00FF, MVT::i16));
5775 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5778 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5779 DAG.getIntPtrConstant(i));
5781 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5784 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5785 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5786 /// done when every pair / quad of shuffle mask elements point to elements in
5787 /// the right sequence. e.g.
5788 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5790 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5791 SelectionDAG &DAG, DebugLoc dl) {
5792 EVT VT = SVOp->getValueType(0);
5793 SDValue V1 = SVOp->getOperand(0);
5794 SDValue V2 = SVOp->getOperand(1);
5795 unsigned NumElems = VT.getVectorNumElements();
5796 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5798 switch (VT.getSimpleVT().SimpleTy) {
5799 default: assert(false && "Unexpected!");
5800 case MVT::v4f32: NewVT = MVT::v2f64; break;
5801 case MVT::v4i32: NewVT = MVT::v2i64; break;
5802 case MVT::v8i16: NewVT = MVT::v4i32; break;
5803 case MVT::v16i8: NewVT = MVT::v4i32; break;
5806 int Scale = NumElems / NewWidth;
5807 SmallVector<int, 8> MaskVec;
5808 for (unsigned i = 0; i < NumElems; i += Scale) {
5810 for (int j = 0; j < Scale; ++j) {
5811 int EltIdx = SVOp->getMaskElt(i+j);
5815 StartIdx = EltIdx - (EltIdx % Scale);
5816 if (EltIdx != StartIdx + j)
5820 MaskVec.push_back(-1);
5822 MaskVec.push_back(StartIdx / Scale);
5825 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5826 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5827 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5830 /// getVZextMovL - Return a zero-extending vector move low node.
5832 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5833 SDValue SrcOp, SelectionDAG &DAG,
5834 const X86Subtarget *Subtarget, DebugLoc dl) {
5835 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5836 LoadSDNode *LD = NULL;
5837 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5838 LD = dyn_cast<LoadSDNode>(SrcOp);
5840 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5842 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5843 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5844 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5845 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5846 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5848 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5849 return DAG.getNode(ISD::BITCAST, dl, VT,
5850 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5851 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5859 return DAG.getNode(ISD::BITCAST, dl, VT,
5860 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5861 DAG.getNode(ISD::BITCAST, dl,
5865 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5866 /// shuffle node referes to only one lane in the sources.
5867 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5868 EVT VT = SVOp->getValueType(0);
5869 int NumElems = VT.getVectorNumElements();
5870 int HalfSize = NumElems/2;
5871 SmallVector<int, 16> M;
5873 bool MatchA = false, MatchB = false;
5875 for (int l = 0; l < NumElems*2; l += HalfSize) {
5876 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5882 for (int l = 0; l < NumElems*2; l += HalfSize) {
5883 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5889 return MatchA && MatchB;
5892 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5893 /// which could not be matched by any known target speficic shuffle
5895 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5896 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5897 // If each half of a vector shuffle node referes to only one lane in the
5898 // source vectors, extract each used 128-bit lane and shuffle them using
5899 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5900 // the work to the legalizer.
5901 DebugLoc dl = SVOp->getDebugLoc();
5902 EVT VT = SVOp->getValueType(0);
5903 int NumElems = VT.getVectorNumElements();
5904 int HalfSize = NumElems/2;
5906 // Extract the reference for each half
5907 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5908 int FstVecOpNum = 0, SndVecOpNum = 0;
5909 for (int i = 0; i < HalfSize; ++i) {
5910 int Elt = SVOp->getMaskElt(i);
5911 if (SVOp->getMaskElt(i) < 0)
5913 FstVecOpNum = Elt/NumElems;
5914 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5917 for (int i = HalfSize; i < NumElems; ++i) {
5918 int Elt = SVOp->getMaskElt(i);
5919 if (SVOp->getMaskElt(i) < 0)
5921 SndVecOpNum = Elt/NumElems;
5922 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5926 // Extract the subvectors
5927 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5928 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5929 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5930 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5932 // Generate 128-bit shuffles
5933 SmallVector<int, 16> MaskV1, MaskV2;
5934 for (int i = 0; i < HalfSize; ++i) {
5935 int Elt = SVOp->getMaskElt(i);
5936 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5938 for (int i = HalfSize; i < NumElems; ++i) {
5939 int Elt = SVOp->getMaskElt(i);
5940 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5943 EVT NVT = V1.getValueType();
5944 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5945 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5947 // Concatenate the result back
5948 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5949 DAG.getConstant(0, MVT::i32), DAG, dl);
5950 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5957 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5958 /// 4 elements, and match them with several different shuffle types.
5960 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5961 SDValue V1 = SVOp->getOperand(0);
5962 SDValue V2 = SVOp->getOperand(1);
5963 DebugLoc dl = SVOp->getDebugLoc();
5964 EVT VT = SVOp->getValueType(0);
5966 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5968 SmallVector<std::pair<int, int>, 8> Locs;
5970 SmallVector<int, 8> Mask1(4U, -1);
5971 SmallVector<int, 8> PermMask;
5972 SVOp->getMask(PermMask);
5976 for (unsigned i = 0; i != 4; ++i) {
5977 int Idx = PermMask[i];
5979 Locs[i] = std::make_pair(-1, -1);
5981 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5983 Locs[i] = std::make_pair(0, NumLo);
5987 Locs[i] = std::make_pair(1, NumHi);
5989 Mask1[2+NumHi] = Idx;
5995 if (NumLo <= 2 && NumHi <= 2) {
5996 // If no more than two elements come from either vector. This can be
5997 // implemented with two shuffles. First shuffle gather the elements.
5998 // The second shuffle, which takes the first shuffle as both of its
5999 // vector operands, put the elements into the right order.
6000 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6002 SmallVector<int, 8> Mask2(4U, -1);
6004 for (unsigned i = 0; i != 4; ++i) {
6005 if (Locs[i].first == -1)
6008 unsigned Idx = (i < 2) ? 0 : 4;
6009 Idx += Locs[i].first * 2 + Locs[i].second;
6014 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6015 } else if (NumLo == 3 || NumHi == 3) {
6016 // Otherwise, we must have three elements from one vector, call it X, and
6017 // one element from the other, call it Y. First, use a shufps to build an
6018 // intermediate vector with the one element from Y and the element from X
6019 // that will be in the same half in the final destination (the indexes don't
6020 // matter). Then, use a shufps to build the final vector, taking the half
6021 // containing the element from Y from the intermediate, and the other half
6024 // Normalize it so the 3 elements come from V1.
6025 CommuteVectorShuffleMask(PermMask, VT);
6029 // Find the element from V2.
6031 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6032 int Val = PermMask[HiIndex];
6039 Mask1[0] = PermMask[HiIndex];
6041 Mask1[2] = PermMask[HiIndex^1];
6043 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6046 Mask1[0] = PermMask[0];
6047 Mask1[1] = PermMask[1];
6048 Mask1[2] = HiIndex & 1 ? 6 : 4;
6049 Mask1[3] = HiIndex & 1 ? 4 : 6;
6050 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6052 Mask1[0] = HiIndex & 1 ? 2 : 0;
6053 Mask1[1] = HiIndex & 1 ? 0 : 2;
6054 Mask1[2] = PermMask[2];
6055 Mask1[3] = PermMask[3];
6060 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6064 // Break it into (shuffle shuffle_hi, shuffle_lo).
6067 SmallVector<int,8> LoMask(4U, -1);
6068 SmallVector<int,8> HiMask(4U, -1);
6070 SmallVector<int,8> *MaskPtr = &LoMask;
6071 unsigned MaskIdx = 0;
6074 for (unsigned i = 0; i != 4; ++i) {
6081 int Idx = PermMask[i];
6083 Locs[i] = std::make_pair(-1, -1);
6084 } else if (Idx < 4) {
6085 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6086 (*MaskPtr)[LoIdx] = Idx;
6089 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6090 (*MaskPtr)[HiIdx] = Idx;
6095 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6096 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6097 SmallVector<int, 8> MaskOps;
6098 for (unsigned i = 0; i != 4; ++i) {
6099 if (Locs[i].first == -1) {
6100 MaskOps.push_back(-1);
6102 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6103 MaskOps.push_back(Idx);
6106 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6109 static bool MayFoldVectorLoad(SDValue V) {
6110 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6111 V = V.getOperand(0);
6112 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6113 V = V.getOperand(0);
6119 // FIXME: the version above should always be used. Since there's
6120 // a bug where several vector shuffles can't be folded because the
6121 // DAG is not updated during lowering and a node claims to have two
6122 // uses while it only has one, use this version, and let isel match
6123 // another instruction if the load really happens to have more than
6124 // one use. Remove this version after this bug get fixed.
6125 // rdar://8434668, PR8156
6126 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6127 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6128 V = V.getOperand(0);
6129 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6130 V = V.getOperand(0);
6131 if (ISD::isNormalLoad(V.getNode()))
6136 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6137 /// a vector extract, and if both can be later optimized into a single load.
6138 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6139 /// here because otherwise a target specific shuffle node is going to be
6140 /// emitted for this shuffle, and the optimization not done.
6141 /// FIXME: This is probably not the best approach, but fix the problem
6142 /// until the right path is decided.
6144 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6145 const TargetLowering &TLI) {
6146 EVT VT = V.getValueType();
6147 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6149 // Be sure that the vector shuffle is present in a pattern like this:
6150 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6154 SDNode *N = *V.getNode()->use_begin();
6155 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6158 SDValue EltNo = N->getOperand(1);
6159 if (!isa<ConstantSDNode>(EltNo))
6162 // If the bit convert changed the number of elements, it is unsafe
6163 // to examine the mask.
6164 bool HasShuffleIntoBitcast = false;
6165 if (V.getOpcode() == ISD::BITCAST) {
6166 EVT SrcVT = V.getOperand(0).getValueType();
6167 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6169 V = V.getOperand(0);
6170 HasShuffleIntoBitcast = true;
6173 // Select the input vector, guarding against out of range extract vector.
6174 unsigned NumElems = VT.getVectorNumElements();
6175 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6176 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6177 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6179 // Skip one more bit_convert if necessary
6180 if (V.getOpcode() == ISD::BITCAST)
6181 V = V.getOperand(0);
6183 if (ISD::isNormalLoad(V.getNode())) {
6184 // Is the original load suitable?
6185 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6187 // FIXME: avoid the multi-use bug that is preventing lots of
6188 // of foldings to be detected, this is still wrong of course, but
6189 // give the temporary desired behavior, and if it happens that
6190 // the load has real more uses, during isel it will not fold, and
6191 // will generate poor code.
6192 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6195 if (!HasShuffleIntoBitcast)
6198 // If there's a bitcast before the shuffle, check if the load type and
6199 // alignment is valid.
6200 unsigned Align = LN0->getAlignment();
6202 TLI.getTargetData()->getABITypeAlignment(
6203 VT.getTypeForEVT(*DAG.getContext()));
6205 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6213 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6214 EVT VT = Op.getValueType();
6216 // Canonizalize to v2f64.
6217 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6218 return DAG.getNode(ISD::BITCAST, dl, VT,
6219 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6224 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6226 SDValue V1 = Op.getOperand(0);
6227 SDValue V2 = Op.getOperand(1);
6228 EVT VT = Op.getValueType();
6230 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6232 if (HasSSE2 && VT == MVT::v2f64)
6233 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6236 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
6240 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6241 SDValue V1 = Op.getOperand(0);
6242 SDValue V2 = Op.getOperand(1);
6243 EVT VT = Op.getValueType();
6245 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6246 "unsupported shuffle type");
6248 if (V2.getOpcode() == ISD::UNDEF)
6252 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6255 static inline unsigned getSHUFPOpcode(EVT VT) {
6256 switch(VT.getSimpleVT().SimpleTy) {
6257 case MVT::v8i32: // Use fp unit for int unpack.
6259 case MVT::v4i32: // Use fp unit for int unpack.
6260 case MVT::v4f32: return X86ISD::SHUFPS;
6261 case MVT::v4i64: // Use fp unit for int unpack.
6263 case MVT::v2i64: // Use fp unit for int unpack.
6264 case MVT::v2f64: return X86ISD::SHUFPD;
6266 llvm_unreachable("Unknown type for shufp*");
6272 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6273 SDValue V1 = Op.getOperand(0);
6274 SDValue V2 = Op.getOperand(1);
6275 EVT VT = Op.getValueType();
6276 unsigned NumElems = VT.getVectorNumElements();
6278 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6279 // operand of these instructions is only memory, so check if there's a
6280 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6282 bool CanFoldLoad = false;
6284 // Trivial case, when V2 comes from a load.
6285 if (MayFoldVectorLoad(V2))
6288 // When V1 is a load, it can be folded later into a store in isel, example:
6289 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6291 // (MOVLPSmr addr:$src1, VR128:$src2)
6292 // So, recognize this potential and also use MOVLPS or MOVLPD
6293 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6296 // Both of them can't be memory operations though.
6297 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6298 CanFoldLoad = false;
6301 if (HasSSE2 && NumElems == 2)
6302 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6305 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6308 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6309 // movl and movlp will both match v2i64, but v2i64 is never matched by
6310 // movl earlier because we make it strict to avoid messing with the movlp load
6311 // folding logic (see the code above getMOVLP call). Match it here then,
6312 // this is horrible, but will stay like this until we move all shuffle
6313 // matching to x86 specific nodes. Note that for the 1st condition all
6314 // types are matched with movsd.
6315 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
6316 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6318 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6321 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6323 // Invert the operand order and use SHUFPS to match it.
6324 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6325 X86::getShuffleSHUFImmediate(SVOp), DAG);
6328 static inline unsigned getUNPCKLOpcode(EVT VT) {
6329 switch(VT.getSimpleVT().SimpleTy) {
6330 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6331 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6332 case MVT::v4f32: return X86ISD::UNPCKLPS;
6333 case MVT::v2f64: return X86ISD::UNPCKLPD;
6334 case MVT::v8i32: // Use fp unit for int unpack.
6335 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6336 case MVT::v4i64: // Use fp unit for int unpack.
6337 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6338 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6339 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6341 llvm_unreachable("Unknown type for unpckl");
6346 static inline unsigned getUNPCKHOpcode(EVT VT) {
6347 switch(VT.getSimpleVT().SimpleTy) {
6348 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6349 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6350 case MVT::v4f32: return X86ISD::UNPCKHPS;
6351 case MVT::v2f64: return X86ISD::UNPCKHPD;
6352 case MVT::v8i32: // Use fp unit for int unpack.
6353 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6354 case MVT::v4i64: // Use fp unit for int unpack.
6355 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6356 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6357 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6359 llvm_unreachable("Unknown type for unpckh");
6364 static inline unsigned getVPERMILOpcode(EVT VT) {
6365 switch(VT.getSimpleVT().SimpleTy) {
6367 case MVT::v4f32: return X86ISD::VPERMILPS;
6369 case MVT::v2f64: return X86ISD::VPERMILPD;
6371 case MVT::v8f32: return X86ISD::VPERMILPSY;
6373 case MVT::v4f64: return X86ISD::VPERMILPDY;
6375 llvm_unreachable("Unknown type for vpermil");
6380 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6381 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6382 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6383 static bool isVectorBroadcast(SDValue &Op) {
6384 EVT VT = Op.getValueType();
6385 bool Is256 = VT.getSizeInBits() == 256;
6387 assert((VT.getSizeInBits() == 128 || Is256) &&
6388 "Unsupported type for vbroadcast node");
6391 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6392 V = V.getOperand(0);
6394 if (Is256 && !(V.hasOneUse() &&
6395 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6396 V.getOperand(0).getOpcode() == ISD::UNDEF))
6400 V = V.getOperand(1);
6401 if (V.hasOneUse() && V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6404 // Check the source scalar_to_vector type. 256-bit broadcasts are
6405 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6406 // for 32-bit scalars.
6407 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6408 if (ScalarSize != 32 && ScalarSize != 64)
6410 if (!Is256 && ScalarSize == 64)
6413 V = V.getOperand(0);
6414 if (!MayFoldLoad(V))
6417 // Return the load node
6423 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6424 const TargetLowering &TLI,
6425 const X86Subtarget *Subtarget) {
6426 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6427 EVT VT = Op.getValueType();
6428 DebugLoc dl = Op.getDebugLoc();
6429 SDValue V1 = Op.getOperand(0);
6430 SDValue V2 = Op.getOperand(1);
6432 if (isZeroShuffle(SVOp))
6433 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6435 // Handle splat operations
6436 if (SVOp->isSplat()) {
6437 unsigned NumElem = VT.getVectorNumElements();
6438 int Size = VT.getSizeInBits();
6439 // Special case, this is the only place now where it's allowed to return
6440 // a vector_shuffle operation without using a target specific node, because
6441 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6442 // this be moved to DAGCombine instead?
6443 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6446 // Use vbroadcast whenever the splat comes from a foldable load
6447 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6448 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6450 // Handle splats by matching through known shuffle masks
6451 if ((Size == 128 && NumElem <= 4) ||
6452 (Size == 256 && NumElem < 8))
6455 // All remaning splats are promoted to target supported vector shuffles.
6456 return PromoteSplat(SVOp, DAG);
6459 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6461 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6462 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6463 if (NewOp.getNode())
6464 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6465 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6466 // FIXME: Figure out a cleaner way to do this.
6467 // Try to make use of movq to zero out the top part.
6468 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6469 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6470 if (NewOp.getNode()) {
6471 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6472 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6473 DAG, Subtarget, dl);
6475 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6476 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6477 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6478 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6479 DAG, Subtarget, dl);
6486 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6487 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6488 SDValue V1 = Op.getOperand(0);
6489 SDValue V2 = Op.getOperand(1);
6490 EVT VT = Op.getValueType();
6491 DebugLoc dl = Op.getDebugLoc();
6492 unsigned NumElems = VT.getVectorNumElements();
6493 bool isMMX = VT.getSizeInBits() == 64;
6494 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6495 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6496 bool V1IsSplat = false;
6497 bool V2IsSplat = false;
6498 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6499 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6500 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6501 MachineFunction &MF = DAG.getMachineFunction();
6502 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6504 // Shuffle operations on MMX not supported.
6508 // Vector shuffle lowering takes 3 steps:
6510 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6511 // narrowing and commutation of operands should be handled.
6512 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6514 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6515 // so the shuffle can be broken into other shuffles and the legalizer can
6516 // try the lowering again.
6518 // The general ideia is that no vector_shuffle operation should be left to
6519 // be matched during isel, all of them must be converted to a target specific
6522 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6523 // narrowing and commutation of operands should be handled. The actual code
6524 // doesn't include all of those, work in progress...
6525 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6526 if (NewOp.getNode())
6529 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6530 // unpckh_undef). Only use pshufd if speed is more important than size.
6531 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6532 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6533 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6534 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6536 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6537 RelaxedMayFoldVectorLoad(V1))
6538 return getMOVDDup(Op, dl, V1, DAG);
6540 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6541 return getMOVHighToLow(Op, dl, DAG);
6543 // Use to match splats
6544 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6545 (VT == MVT::v2f64 || VT == MVT::v2i64))
6546 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6548 if (X86::isPSHUFDMask(SVOp)) {
6549 // The actual implementation will match the mask in the if above and then
6550 // during isel it can match several different instructions, not only pshufd
6551 // as its name says, sad but true, emulate the behavior for now...
6552 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6553 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6555 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6557 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6558 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6560 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6564 // Check if this can be converted into a logical shift.
6565 bool isLeft = false;
6568 bool isShift = getSubtarget()->hasSSE2() &&
6569 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6570 if (isShift && ShVal.hasOneUse()) {
6571 // If the shifted value has multiple uses, it may be cheaper to use
6572 // v_set0 + movlhps or movhlps, etc.
6573 EVT EltVT = VT.getVectorElementType();
6574 ShAmt *= EltVT.getSizeInBits();
6575 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6578 if (X86::isMOVLMask(SVOp)) {
6581 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6582 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6583 if (!X86::isMOVLPMask(SVOp)) {
6584 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6585 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6587 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6588 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6592 // FIXME: fold these into legal mask.
6593 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6594 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6596 if (X86::isMOVHLPSMask(SVOp))
6597 return getMOVHighToLow(Op, dl, DAG);
6599 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6600 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6602 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6603 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6605 if (X86::isMOVLPMask(SVOp))
6606 return getMOVLP(Op, dl, DAG, HasSSE2);
6608 if (ShouldXformToMOVHLPS(SVOp) ||
6609 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6610 return CommuteVectorShuffle(SVOp, DAG);
6613 // No better options. Use a vshl / vsrl.
6614 EVT EltVT = VT.getVectorElementType();
6615 ShAmt *= EltVT.getSizeInBits();
6616 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6619 bool Commuted = false;
6620 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6621 // 1,1,1,1 -> v8i16 though.
6622 V1IsSplat = isSplatVector(V1.getNode());
6623 V2IsSplat = isSplatVector(V2.getNode());
6625 // Canonicalize the splat or undef, if present, to be on the RHS.
6626 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6627 Op = CommuteVectorShuffle(SVOp, DAG);
6628 SVOp = cast<ShuffleVectorSDNode>(Op);
6629 V1 = SVOp->getOperand(0);
6630 V2 = SVOp->getOperand(1);
6631 std::swap(V1IsSplat, V2IsSplat);
6632 std::swap(V1IsUndef, V2IsUndef);
6636 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6637 // Shuffling low element of v1 into undef, just return v1.
6640 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6641 // the instruction selector will not match, so get a canonical MOVL with
6642 // swapped operands to undo the commute.
6643 return getMOVL(DAG, dl, VT, V2, V1);
6646 if (X86::isUNPCKLMask(SVOp))
6647 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6649 if (X86::isUNPCKHMask(SVOp))
6650 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6653 // Normalize mask so all entries that point to V2 points to its first
6654 // element then try to match unpck{h|l} again. If match, return a
6655 // new vector_shuffle with the corrected mask.
6656 SDValue NewMask = NormalizeMask(SVOp, DAG);
6657 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6658 if (NSVOp != SVOp) {
6659 if (X86::isUNPCKLMask(NSVOp, true)) {
6661 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6668 // Commute is back and try unpck* again.
6669 // FIXME: this seems wrong.
6670 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6671 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6673 if (X86::isUNPCKLMask(NewSVOp))
6674 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6676 if (X86::isUNPCKHMask(NewSVOp))
6677 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6680 // Normalize the node to match x86 shuffle ops if needed
6681 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6682 return CommuteVectorShuffle(SVOp, DAG);
6684 // The checks below are all present in isShuffleMaskLegal, but they are
6685 // inlined here right now to enable us to directly emit target specific
6686 // nodes, and remove one by one until they don't return Op anymore.
6687 SmallVector<int, 16> M;
6690 if (isPALIGNRMask(M, VT, HasSSSE3))
6691 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6692 X86::getShufflePALIGNRImmediate(SVOp),
6695 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6696 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6697 if (VT == MVT::v2f64)
6698 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6699 if (VT == MVT::v2i64)
6700 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6703 if (isPSHUFHWMask(M, VT))
6704 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6705 X86::getShufflePSHUFHWImmediate(SVOp),
6708 if (isPSHUFLWMask(M, VT))
6709 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6710 X86::getShufflePSHUFLWImmediate(SVOp),
6713 if (isSHUFPMask(M, VT))
6714 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6715 X86::getShuffleSHUFImmediate(SVOp), DAG);
6717 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6718 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6719 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6720 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6722 //===--------------------------------------------------------------------===//
6723 // Generate target specific nodes for 128 or 256-bit shuffles only
6724 // supported in the AVX instruction set.
6727 // Handle VMOVDDUPY permutations
6728 if (isMOVDDUPYMask(SVOp, Subtarget))
6729 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6731 // Handle VPERMILPS* permutations
6732 if (isVPERMILPSMask(M, VT, Subtarget))
6733 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6734 getShuffleVPERMILPSImmediate(SVOp), DAG);
6736 // Handle VPERMILPD* permutations
6737 if (isVPERMILPDMask(M, VT, Subtarget))
6738 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6739 getShuffleVPERMILPDImmediate(SVOp), DAG);
6741 // Handle VPERM2F128 permutations
6742 if (isVPERM2F128Mask(M, VT, Subtarget))
6743 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6744 getShuffleVPERM2F128Immediate(SVOp), DAG);
6746 // Handle VSHUFPSY permutations
6747 if (isVSHUFPSYMask(M, VT, Subtarget))
6748 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6749 getShuffleVSHUFPSYImmediate(SVOp), DAG);
6751 // Handle VSHUFPDY permutations
6752 if (isVSHUFPDYMask(M, VT, Subtarget))
6753 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6754 getShuffleVSHUFPDYImmediate(SVOp), DAG);
6756 //===--------------------------------------------------------------------===//
6757 // Since no target specific shuffle was selected for this generic one,
6758 // lower it into other known shuffles. FIXME: this isn't true yet, but
6759 // this is the plan.
6762 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6763 if (VT == MVT::v8i16) {
6764 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6765 if (NewOp.getNode())
6769 if (VT == MVT::v16i8) {
6770 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6771 if (NewOp.getNode())
6775 // Handle all 128-bit wide vectors with 4 elements, and match them with
6776 // several different shuffle types.
6777 if (NumElems == 4 && VT.getSizeInBits() == 128)
6778 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6780 // Handle general 256-bit shuffles
6781 if (VT.is256BitVector())
6782 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6788 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6789 SelectionDAG &DAG) const {
6790 EVT VT = Op.getValueType();
6791 DebugLoc dl = Op.getDebugLoc();
6793 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6796 if (VT.getSizeInBits() == 8) {
6797 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6798 Op.getOperand(0), Op.getOperand(1));
6799 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6800 DAG.getValueType(VT));
6801 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6802 } else if (VT.getSizeInBits() == 16) {
6803 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6804 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6806 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6807 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6808 DAG.getNode(ISD::BITCAST, dl,
6812 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6813 Op.getOperand(0), Op.getOperand(1));
6814 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6815 DAG.getValueType(VT));
6816 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6817 } else if (VT == MVT::f32) {
6818 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6819 // the result back to FR32 register. It's only worth matching if the
6820 // result has a single use which is a store or a bitcast to i32. And in
6821 // the case of a store, it's not worth it if the index is a constant 0,
6822 // because a MOVSSmr can be used instead, which is smaller and faster.
6823 if (!Op.hasOneUse())
6825 SDNode *User = *Op.getNode()->use_begin();
6826 if ((User->getOpcode() != ISD::STORE ||
6827 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6828 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6829 (User->getOpcode() != ISD::BITCAST ||
6830 User->getValueType(0) != MVT::i32))
6832 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6833 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6836 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6837 } else if (VT == MVT::i32) {
6838 // ExtractPS works with constant index.
6839 if (isa<ConstantSDNode>(Op.getOperand(1)))
6847 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6848 SelectionDAG &DAG) const {
6849 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6852 SDValue Vec = Op.getOperand(0);
6853 EVT VecVT = Vec.getValueType();
6855 // If this is a 256-bit vector result, first extract the 128-bit vector and
6856 // then extract the element from the 128-bit vector.
6857 if (VecVT.getSizeInBits() == 256) {
6858 DebugLoc dl = Op.getNode()->getDebugLoc();
6859 unsigned NumElems = VecVT.getVectorNumElements();
6860 SDValue Idx = Op.getOperand(1);
6861 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6863 // Get the 128-bit vector.
6864 bool Upper = IdxVal >= NumElems/2;
6865 Vec = Extract128BitVector(Vec,
6866 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6868 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6869 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6872 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6874 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6875 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6880 EVT VT = Op.getValueType();
6881 DebugLoc dl = Op.getDebugLoc();
6882 // TODO: handle v16i8.
6883 if (VT.getSizeInBits() == 16) {
6884 SDValue Vec = Op.getOperand(0);
6885 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6887 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6888 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6889 DAG.getNode(ISD::BITCAST, dl,
6892 // Transform it so it match pextrw which produces a 32-bit result.
6893 EVT EltVT = MVT::i32;
6894 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6895 Op.getOperand(0), Op.getOperand(1));
6896 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6897 DAG.getValueType(VT));
6898 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6899 } else if (VT.getSizeInBits() == 32) {
6900 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6904 // SHUFPS the element to the lowest double word, then movss.
6905 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6906 EVT VVT = Op.getOperand(0).getValueType();
6907 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6908 DAG.getUNDEF(VVT), Mask);
6909 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6910 DAG.getIntPtrConstant(0));
6911 } else if (VT.getSizeInBits() == 64) {
6912 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6913 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6914 // to match extract_elt for f64.
6915 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6919 // UNPCKHPD the element to the lowest double word, then movsd.
6920 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6921 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6922 int Mask[2] = { 1, -1 };
6923 EVT VVT = Op.getOperand(0).getValueType();
6924 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6925 DAG.getUNDEF(VVT), Mask);
6926 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6927 DAG.getIntPtrConstant(0));
6934 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6935 SelectionDAG &DAG) const {
6936 EVT VT = Op.getValueType();
6937 EVT EltVT = VT.getVectorElementType();
6938 DebugLoc dl = Op.getDebugLoc();
6940 SDValue N0 = Op.getOperand(0);
6941 SDValue N1 = Op.getOperand(1);
6942 SDValue N2 = Op.getOperand(2);
6944 if (VT.getSizeInBits() == 256)
6947 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6948 isa<ConstantSDNode>(N2)) {
6950 if (VT == MVT::v8i16)
6951 Opc = X86ISD::PINSRW;
6952 else if (VT == MVT::v16i8)
6953 Opc = X86ISD::PINSRB;
6955 Opc = X86ISD::PINSRB;
6957 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6959 if (N1.getValueType() != MVT::i32)
6960 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6961 if (N2.getValueType() != MVT::i32)
6962 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6963 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6964 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6965 // Bits [7:6] of the constant are the source select. This will always be
6966 // zero here. The DAG Combiner may combine an extract_elt index into these
6967 // bits. For example (insert (extract, 3), 2) could be matched by putting
6968 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6969 // Bits [5:4] of the constant are the destination select. This is the
6970 // value of the incoming immediate.
6971 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6972 // combine either bitwise AND or insert of float 0.0 to set these bits.
6973 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6974 // Create this as a scalar to vector..
6975 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6976 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6977 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6978 // PINSR* works with constant index.
6985 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6986 EVT VT = Op.getValueType();
6987 EVT EltVT = VT.getVectorElementType();
6989 DebugLoc dl = Op.getDebugLoc();
6990 SDValue N0 = Op.getOperand(0);
6991 SDValue N1 = Op.getOperand(1);
6992 SDValue N2 = Op.getOperand(2);
6994 // If this is a 256-bit vector result, first extract the 128-bit vector,
6995 // insert the element into the extracted half and then place it back.
6996 if (VT.getSizeInBits() == 256) {
6997 if (!isa<ConstantSDNode>(N2))
7000 // Get the desired 128-bit vector half.
7001 unsigned NumElems = VT.getVectorNumElements();
7002 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7003 bool Upper = IdxVal >= NumElems/2;
7004 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
7005 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
7007 // Insert the element into the desired half.
7008 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
7009 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
7011 // Insert the changed part back to the 256-bit vector
7012 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
7015 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
7016 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7018 if (EltVT == MVT::i8)
7021 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7022 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7023 // as its second argument.
7024 if (N1.getValueType() != MVT::i32)
7025 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7026 if (N2.getValueType() != MVT::i32)
7027 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7028 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7034 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7035 LLVMContext *Context = DAG.getContext();
7036 DebugLoc dl = Op.getDebugLoc();
7037 EVT OpVT = Op.getValueType();
7039 // If this is a 256-bit vector result, first insert into a 128-bit
7040 // vector and then insert into the 256-bit vector.
7041 if (OpVT.getSizeInBits() > 128) {
7042 // Insert into a 128-bit vector.
7043 EVT VT128 = EVT::getVectorVT(*Context,
7044 OpVT.getVectorElementType(),
7045 OpVT.getVectorNumElements() / 2);
7047 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7049 // Insert the 128-bit vector.
7050 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7051 DAG.getConstant(0, MVT::i32),
7055 if (Op.getValueType() == MVT::v1i64 &&
7056 Op.getOperand(0).getValueType() == MVT::i64)
7057 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7059 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7060 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7061 "Expected an SSE type!");
7062 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7063 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7066 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7067 // a simple subregister reference or explicit instructions to grab
7068 // upper bits of a vector.
7070 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7071 if (Subtarget->hasAVX()) {
7072 DebugLoc dl = Op.getNode()->getDebugLoc();
7073 SDValue Vec = Op.getNode()->getOperand(0);
7074 SDValue Idx = Op.getNode()->getOperand(1);
7076 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7077 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7078 return Extract128BitVector(Vec, Idx, DAG, dl);
7084 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7085 // simple superregister reference or explicit instructions to insert
7086 // the upper bits of a vector.
7088 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7089 if (Subtarget->hasAVX()) {
7090 DebugLoc dl = Op.getNode()->getDebugLoc();
7091 SDValue Vec = Op.getNode()->getOperand(0);
7092 SDValue SubVec = Op.getNode()->getOperand(1);
7093 SDValue Idx = Op.getNode()->getOperand(2);
7095 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7096 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7097 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7103 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7104 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7105 // one of the above mentioned nodes. It has to be wrapped because otherwise
7106 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7107 // be used to form addressing mode. These wrapped nodes will be selected
7110 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7111 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7113 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7115 unsigned char OpFlag = 0;
7116 unsigned WrapperKind = X86ISD::Wrapper;
7117 CodeModel::Model M = getTargetMachine().getCodeModel();
7119 if (Subtarget->isPICStyleRIPRel() &&
7120 (M == CodeModel::Small || M == CodeModel::Kernel))
7121 WrapperKind = X86ISD::WrapperRIP;
7122 else if (Subtarget->isPICStyleGOT())
7123 OpFlag = X86II::MO_GOTOFF;
7124 else if (Subtarget->isPICStyleStubPIC())
7125 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7127 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7129 CP->getOffset(), OpFlag);
7130 DebugLoc DL = CP->getDebugLoc();
7131 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7132 // With PIC, the address is actually $g + Offset.
7134 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7135 DAG.getNode(X86ISD::GlobalBaseReg,
7136 DebugLoc(), getPointerTy()),
7143 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7144 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7146 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7148 unsigned char OpFlag = 0;
7149 unsigned WrapperKind = X86ISD::Wrapper;
7150 CodeModel::Model M = getTargetMachine().getCodeModel();
7152 if (Subtarget->isPICStyleRIPRel() &&
7153 (M == CodeModel::Small || M == CodeModel::Kernel))
7154 WrapperKind = X86ISD::WrapperRIP;
7155 else if (Subtarget->isPICStyleGOT())
7156 OpFlag = X86II::MO_GOTOFF;
7157 else if (Subtarget->isPICStyleStubPIC())
7158 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7160 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7162 DebugLoc DL = JT->getDebugLoc();
7163 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7165 // With PIC, the address is actually $g + Offset.
7167 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7168 DAG.getNode(X86ISD::GlobalBaseReg,
7169 DebugLoc(), getPointerTy()),
7176 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7177 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7179 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7181 unsigned char OpFlag = 0;
7182 unsigned WrapperKind = X86ISD::Wrapper;
7183 CodeModel::Model M = getTargetMachine().getCodeModel();
7185 if (Subtarget->isPICStyleRIPRel() &&
7186 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7187 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7188 OpFlag = X86II::MO_GOTPCREL;
7189 WrapperKind = X86ISD::WrapperRIP;
7190 } else if (Subtarget->isPICStyleGOT()) {
7191 OpFlag = X86II::MO_GOT;
7192 } else if (Subtarget->isPICStyleStubPIC()) {
7193 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7194 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7195 OpFlag = X86II::MO_DARWIN_NONLAZY;
7198 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7200 DebugLoc DL = Op.getDebugLoc();
7201 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7204 // With PIC, the address is actually $g + Offset.
7205 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7206 !Subtarget->is64Bit()) {
7207 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7208 DAG.getNode(X86ISD::GlobalBaseReg,
7209 DebugLoc(), getPointerTy()),
7213 // For symbols that require a load from a stub to get the address, emit the
7215 if (isGlobalStubReference(OpFlag))
7216 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7217 MachinePointerInfo::getGOT(), false, false, 0);
7223 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7224 // Create the TargetBlockAddressAddress node.
7225 unsigned char OpFlags =
7226 Subtarget->ClassifyBlockAddressReference();
7227 CodeModel::Model M = getTargetMachine().getCodeModel();
7228 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7229 DebugLoc dl = Op.getDebugLoc();
7230 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7231 /*isTarget=*/true, OpFlags);
7233 if (Subtarget->isPICStyleRIPRel() &&
7234 (M == CodeModel::Small || M == CodeModel::Kernel))
7235 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7237 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7239 // With PIC, the address is actually $g + Offset.
7240 if (isGlobalRelativeToPICBase(OpFlags)) {
7241 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7242 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7250 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7252 SelectionDAG &DAG) const {
7253 // Create the TargetGlobalAddress node, folding in the constant
7254 // offset if it is legal.
7255 unsigned char OpFlags =
7256 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7257 CodeModel::Model M = getTargetMachine().getCodeModel();
7259 if (OpFlags == X86II::MO_NO_FLAG &&
7260 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7261 // A direct static reference to a global.
7262 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7265 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7268 if (Subtarget->isPICStyleRIPRel() &&
7269 (M == CodeModel::Small || M == CodeModel::Kernel))
7270 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7272 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7274 // With PIC, the address is actually $g + Offset.
7275 if (isGlobalRelativeToPICBase(OpFlags)) {
7276 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7277 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7281 // For globals that require a load from a stub to get the address, emit the
7283 if (isGlobalStubReference(OpFlags))
7284 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7285 MachinePointerInfo::getGOT(), false, false, 0);
7287 // If there was a non-zero offset that we didn't fold, create an explicit
7290 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7291 DAG.getConstant(Offset, getPointerTy()));
7297 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7298 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7299 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7300 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7304 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7305 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7306 unsigned char OperandFlags) {
7307 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7308 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7309 DebugLoc dl = GA->getDebugLoc();
7310 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7311 GA->getValueType(0),
7315 SDValue Ops[] = { Chain, TGA, *InFlag };
7316 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7318 SDValue Ops[] = { Chain, TGA };
7319 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7322 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7323 MFI->setAdjustsStack(true);
7325 SDValue Flag = Chain.getValue(1);
7326 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7329 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7331 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7334 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7335 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7336 DAG.getNode(X86ISD::GlobalBaseReg,
7337 DebugLoc(), PtrVT), InFlag);
7338 InFlag = Chain.getValue(1);
7340 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7343 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7345 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7347 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7348 X86::RAX, X86II::MO_TLSGD);
7351 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7352 // "local exec" model.
7353 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7354 const EVT PtrVT, TLSModel::Model model,
7356 DebugLoc dl = GA->getDebugLoc();
7358 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7359 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7360 is64Bit ? 257 : 256));
7362 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7363 DAG.getIntPtrConstant(0),
7364 MachinePointerInfo(Ptr), false, false, 0);
7366 unsigned char OperandFlags = 0;
7367 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7369 unsigned WrapperKind = X86ISD::Wrapper;
7370 if (model == TLSModel::LocalExec) {
7371 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7372 } else if (is64Bit) {
7373 assert(model == TLSModel::InitialExec);
7374 OperandFlags = X86II::MO_GOTTPOFF;
7375 WrapperKind = X86ISD::WrapperRIP;
7377 assert(model == TLSModel::InitialExec);
7378 OperandFlags = X86II::MO_INDNTPOFF;
7381 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7383 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7384 GA->getValueType(0),
7385 GA->getOffset(), OperandFlags);
7386 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7388 if (model == TLSModel::InitialExec)
7389 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7390 MachinePointerInfo::getGOT(), false, false, 0);
7392 // The address of the thread local variable is the add of the thread
7393 // pointer with the offset of the variable.
7394 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7398 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7400 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7401 const GlobalValue *GV = GA->getGlobal();
7403 if (Subtarget->isTargetELF()) {
7404 // TODO: implement the "local dynamic" model
7405 // TODO: implement the "initial exec"model for pic executables
7407 // If GV is an alias then use the aliasee for determining
7408 // thread-localness.
7409 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7410 GV = GA->resolveAliasedGlobal(false);
7412 TLSModel::Model model
7413 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7416 case TLSModel::GeneralDynamic:
7417 case TLSModel::LocalDynamic: // not implemented
7418 if (Subtarget->is64Bit())
7419 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7420 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7422 case TLSModel::InitialExec:
7423 case TLSModel::LocalExec:
7424 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7425 Subtarget->is64Bit());
7427 } else if (Subtarget->isTargetDarwin()) {
7428 // Darwin only has one model of TLS. Lower to that.
7429 unsigned char OpFlag = 0;
7430 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7431 X86ISD::WrapperRIP : X86ISD::Wrapper;
7433 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7435 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7436 !Subtarget->is64Bit();
7438 OpFlag = X86II::MO_TLVP_PIC_BASE;
7440 OpFlag = X86II::MO_TLVP;
7441 DebugLoc DL = Op.getDebugLoc();
7442 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7443 GA->getValueType(0),
7444 GA->getOffset(), OpFlag);
7445 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7447 // With PIC32, the address is actually $g + Offset.
7449 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7450 DAG.getNode(X86ISD::GlobalBaseReg,
7451 DebugLoc(), getPointerTy()),
7454 // Lowering the machine isd will make sure everything is in the right
7456 SDValue Chain = DAG.getEntryNode();
7457 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7458 SDValue Args[] = { Chain, Offset };
7459 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7461 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7462 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7463 MFI->setAdjustsStack(true);
7465 // And our return value (tls address) is in the standard call return value
7467 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7468 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7472 "TLS not implemented for this target.");
7474 llvm_unreachable("Unreachable");
7479 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7480 /// take a 2 x i32 value to shift plus a shift amount.
7481 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7482 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7483 EVT VT = Op.getValueType();
7484 unsigned VTBits = VT.getSizeInBits();
7485 DebugLoc dl = Op.getDebugLoc();
7486 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7487 SDValue ShOpLo = Op.getOperand(0);
7488 SDValue ShOpHi = Op.getOperand(1);
7489 SDValue ShAmt = Op.getOperand(2);
7490 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7491 DAG.getConstant(VTBits - 1, MVT::i8))
7492 : DAG.getConstant(0, VT);
7495 if (Op.getOpcode() == ISD::SHL_PARTS) {
7496 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7497 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7499 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7500 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7503 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7504 DAG.getConstant(VTBits, MVT::i8));
7505 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7506 AndNode, DAG.getConstant(0, MVT::i8));
7509 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7510 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7511 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7513 if (Op.getOpcode() == ISD::SHL_PARTS) {
7514 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7515 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7517 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7518 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7521 SDValue Ops[2] = { Lo, Hi };
7522 return DAG.getMergeValues(Ops, 2, dl);
7525 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7526 SelectionDAG &DAG) const {
7527 EVT SrcVT = Op.getOperand(0).getValueType();
7529 if (SrcVT.isVector())
7532 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7533 "Unknown SINT_TO_FP to lower!");
7535 // These are really Legal; return the operand so the caller accepts it as
7537 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7539 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7540 Subtarget->is64Bit()) {
7544 DebugLoc dl = Op.getDebugLoc();
7545 unsigned Size = SrcVT.getSizeInBits()/8;
7546 MachineFunction &MF = DAG.getMachineFunction();
7547 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7548 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7549 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7551 MachinePointerInfo::getFixedStack(SSFI),
7553 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7556 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7558 SelectionDAG &DAG) const {
7560 DebugLoc DL = Op.getDebugLoc();
7562 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7564 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7566 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7568 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7570 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7571 MachineMemOperand *MMO;
7573 int SSFI = FI->getIndex();
7575 DAG.getMachineFunction()
7576 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7577 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7579 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7580 StackSlot = StackSlot.getOperand(1);
7582 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7583 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7585 Tys, Ops, array_lengthof(Ops),
7589 Chain = Result.getValue(1);
7590 SDValue InFlag = Result.getValue(2);
7592 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7593 // shouldn't be necessary except that RFP cannot be live across
7594 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7595 MachineFunction &MF = DAG.getMachineFunction();
7596 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7597 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7598 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7599 Tys = DAG.getVTList(MVT::Other);
7601 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7603 MachineMemOperand *MMO =
7604 DAG.getMachineFunction()
7605 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7606 MachineMemOperand::MOStore, SSFISize, SSFISize);
7608 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7609 Ops, array_lengthof(Ops),
7610 Op.getValueType(), MMO);
7611 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7612 MachinePointerInfo::getFixedStack(SSFI),
7619 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7620 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7621 SelectionDAG &DAG) const {
7622 // This algorithm is not obvious. Here it is in C code, more or less:
7624 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7625 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7626 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7628 // Copy ints to xmm registers.
7629 __m128i xh = _mm_cvtsi32_si128( hi );
7630 __m128i xl = _mm_cvtsi32_si128( lo );
7632 // Combine into low half of a single xmm register.
7633 __m128i x = _mm_unpacklo_epi32( xh, xl );
7637 // Merge in appropriate exponents to give the integer bits the right
7639 x = _mm_unpacklo_epi32( x, exp );
7641 // Subtract away the biases to deal with the IEEE-754 double precision
7643 d = _mm_sub_pd( (__m128d) x, bias );
7645 // All conversions up to here are exact. The correctly rounded result is
7646 // calculated using the current rounding mode using the following
7648 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7649 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7650 // store doesn't really need to be here (except
7651 // maybe to zero the other double)
7656 DebugLoc dl = Op.getDebugLoc();
7657 LLVMContext *Context = DAG.getContext();
7659 // Build some magic constants.
7660 std::vector<Constant*> CV0;
7661 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7662 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7663 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7664 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7665 Constant *C0 = ConstantVector::get(CV0);
7666 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7668 std::vector<Constant*> CV1;
7670 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7672 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7673 Constant *C1 = ConstantVector::get(CV1);
7674 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7676 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7677 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7679 DAG.getIntPtrConstant(1)));
7680 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7681 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7683 DAG.getIntPtrConstant(0)));
7684 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7685 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7686 MachinePointerInfo::getConstantPool(),
7688 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7689 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7690 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7691 MachinePointerInfo::getConstantPool(),
7693 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7695 // Add the halves; easiest way is to swap them into another reg first.
7696 int ShufMask[2] = { 1, -1 };
7697 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7698 DAG.getUNDEF(MVT::v2f64), ShufMask);
7699 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7700 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7701 DAG.getIntPtrConstant(0));
7704 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7705 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7706 SelectionDAG &DAG) const {
7707 DebugLoc dl = Op.getDebugLoc();
7708 // FP constant to bias correct the final result.
7709 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7712 // Load the 32-bit value into an XMM register.
7713 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7716 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7717 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7718 DAG.getIntPtrConstant(0));
7720 // Or the load with the bias.
7721 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7722 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7723 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7725 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7726 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7727 MVT::v2f64, Bias)));
7728 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7729 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7730 DAG.getIntPtrConstant(0));
7732 // Subtract the bias.
7733 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7735 // Handle final rounding.
7736 EVT DestVT = Op.getValueType();
7738 if (DestVT.bitsLT(MVT::f64)) {
7739 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7740 DAG.getIntPtrConstant(0));
7741 } else if (DestVT.bitsGT(MVT::f64)) {
7742 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7745 // Handle final rounding.
7749 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7750 SelectionDAG &DAG) const {
7751 SDValue N0 = Op.getOperand(0);
7752 DebugLoc dl = Op.getDebugLoc();
7754 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7755 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7756 // the optimization here.
7757 if (DAG.SignBitIsZero(N0))
7758 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7760 EVT SrcVT = N0.getValueType();
7761 EVT DstVT = Op.getValueType();
7762 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7763 return LowerUINT_TO_FP_i64(Op, DAG);
7764 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7765 return LowerUINT_TO_FP_i32(Op, DAG);
7767 // Make a 64-bit buffer, and use it to build an FILD.
7768 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7769 if (SrcVT == MVT::i32) {
7770 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7771 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7772 getPointerTy(), StackSlot, WordOff);
7773 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7774 StackSlot, MachinePointerInfo(),
7776 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7777 OffsetSlot, MachinePointerInfo(),
7779 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7783 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7784 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7785 StackSlot, MachinePointerInfo(),
7787 // For i64 source, we need to add the appropriate power of 2 if the input
7788 // was negative. This is the same as the optimization in
7789 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7790 // we must be careful to do the computation in x87 extended precision, not
7791 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7792 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7793 MachineMemOperand *MMO =
7794 DAG.getMachineFunction()
7795 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7796 MachineMemOperand::MOLoad, 8, 8);
7798 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7799 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7800 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7803 APInt FF(32, 0x5F800000ULL);
7805 // Check whether the sign bit is set.
7806 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7807 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7810 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7811 SDValue FudgePtr = DAG.getConstantPool(
7812 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7815 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7816 SDValue Zero = DAG.getIntPtrConstant(0);
7817 SDValue Four = DAG.getIntPtrConstant(4);
7818 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7820 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7822 // Load the value out, extending it from f32 to f80.
7823 // FIXME: Avoid the extend by constructing the right constant pool?
7824 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7825 FudgePtr, MachinePointerInfo::getConstantPool(),
7826 MVT::f32, false, false, 4);
7827 // Extend everything to 80 bits to force it to be done on x87.
7828 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7829 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7832 std::pair<SDValue,SDValue> X86TargetLowering::
7833 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7834 DebugLoc DL = Op.getDebugLoc();
7836 EVT DstTy = Op.getValueType();
7839 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7843 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7844 DstTy.getSimpleVT() >= MVT::i16 &&
7845 "Unknown FP_TO_SINT to lower!");
7847 // These are really Legal.
7848 if (DstTy == MVT::i32 &&
7849 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7850 return std::make_pair(SDValue(), SDValue());
7851 if (Subtarget->is64Bit() &&
7852 DstTy == MVT::i64 &&
7853 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7854 return std::make_pair(SDValue(), SDValue());
7856 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7858 MachineFunction &MF = DAG.getMachineFunction();
7859 unsigned MemSize = DstTy.getSizeInBits()/8;
7860 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7861 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7866 switch (DstTy.getSimpleVT().SimpleTy) {
7867 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7868 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7869 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7870 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7873 SDValue Chain = DAG.getEntryNode();
7874 SDValue Value = Op.getOperand(0);
7875 EVT TheVT = Op.getOperand(0).getValueType();
7876 if (isScalarFPTypeInSSEReg(TheVT)) {
7877 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7878 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7879 MachinePointerInfo::getFixedStack(SSFI),
7881 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7883 Chain, StackSlot, DAG.getValueType(TheVT)
7886 MachineMemOperand *MMO =
7887 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7888 MachineMemOperand::MOLoad, MemSize, MemSize);
7889 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7891 Chain = Value.getValue(1);
7892 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7893 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7896 MachineMemOperand *MMO =
7897 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7898 MachineMemOperand::MOStore, MemSize, MemSize);
7900 // Build the FP_TO_INT*_IN_MEM
7901 SDValue Ops[] = { Chain, Value, StackSlot };
7902 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7903 Ops, 3, DstTy, MMO);
7905 return std::make_pair(FIST, StackSlot);
7908 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7909 SelectionDAG &DAG) const {
7910 if (Op.getValueType().isVector())
7913 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7914 SDValue FIST = Vals.first, StackSlot = Vals.second;
7915 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7916 if (FIST.getNode() == 0) return Op;
7919 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7920 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7923 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7924 SelectionDAG &DAG) const {
7925 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7926 SDValue FIST = Vals.first, StackSlot = Vals.second;
7927 assert(FIST.getNode() && "Unexpected failure");
7930 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7931 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7934 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7935 SelectionDAG &DAG) const {
7936 LLVMContext *Context = DAG.getContext();
7937 DebugLoc dl = Op.getDebugLoc();
7938 EVT VT = Op.getValueType();
7941 EltVT = VT.getVectorElementType();
7942 std::vector<Constant*> CV;
7943 if (EltVT == MVT::f64) {
7944 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7948 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7954 Constant *C = ConstantVector::get(CV);
7955 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7956 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7957 MachinePointerInfo::getConstantPool(),
7959 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7962 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7963 LLVMContext *Context = DAG.getContext();
7964 DebugLoc dl = Op.getDebugLoc();
7965 EVT VT = Op.getValueType();
7968 EltVT = VT.getVectorElementType();
7969 std::vector<Constant*> CV;
7970 if (EltVT == MVT::f64) {
7971 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7975 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7981 Constant *C = ConstantVector::get(CV);
7982 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7983 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7984 MachinePointerInfo::getConstantPool(),
7986 if (VT.isVector()) {
7987 return DAG.getNode(ISD::BITCAST, dl, VT,
7988 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7989 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7991 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7993 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7997 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7998 LLVMContext *Context = DAG.getContext();
7999 SDValue Op0 = Op.getOperand(0);
8000 SDValue Op1 = Op.getOperand(1);
8001 DebugLoc dl = Op.getDebugLoc();
8002 EVT VT = Op.getValueType();
8003 EVT SrcVT = Op1.getValueType();
8005 // If second operand is smaller, extend it first.
8006 if (SrcVT.bitsLT(VT)) {
8007 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8010 // And if it is bigger, shrink it first.
8011 if (SrcVT.bitsGT(VT)) {
8012 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8016 // At this point the operands and the result should have the same
8017 // type, and that won't be f80 since that is not custom lowered.
8019 // First get the sign bit of second operand.
8020 std::vector<Constant*> CV;
8021 if (SrcVT == MVT::f64) {
8022 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8023 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8025 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8026 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8027 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8028 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8030 Constant *C = ConstantVector::get(CV);
8031 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8032 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8033 MachinePointerInfo::getConstantPool(),
8035 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8037 // Shift sign bit right or left if the two operands have different types.
8038 if (SrcVT.bitsGT(VT)) {
8039 // Op0 is MVT::f32, Op1 is MVT::f64.
8040 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8041 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8042 DAG.getConstant(32, MVT::i32));
8043 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8044 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8045 DAG.getIntPtrConstant(0));
8048 // Clear first operand sign bit.
8050 if (VT == MVT::f64) {
8051 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8052 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8054 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8055 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8056 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8057 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8059 C = ConstantVector::get(CV);
8060 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8061 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8062 MachinePointerInfo::getConstantPool(),
8064 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8066 // Or the value with the sign bit.
8067 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8070 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8071 SDValue N0 = Op.getOperand(0);
8072 DebugLoc dl = Op.getDebugLoc();
8073 EVT VT = Op.getValueType();
8075 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8076 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8077 DAG.getConstant(1, VT));
8078 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8081 /// Emit nodes that will be selected as "test Op0,Op0", or something
8083 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8084 SelectionDAG &DAG) const {
8085 DebugLoc dl = Op.getDebugLoc();
8087 // CF and OF aren't always set the way we want. Determine which
8088 // of these we need.
8089 bool NeedCF = false;
8090 bool NeedOF = false;
8093 case X86::COND_A: case X86::COND_AE:
8094 case X86::COND_B: case X86::COND_BE:
8097 case X86::COND_G: case X86::COND_GE:
8098 case X86::COND_L: case X86::COND_LE:
8099 case X86::COND_O: case X86::COND_NO:
8104 // See if we can use the EFLAGS value from the operand instead of
8105 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8106 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8107 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8108 // Emit a CMP with 0, which is the TEST pattern.
8109 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8110 DAG.getConstant(0, Op.getValueType()));
8112 unsigned Opcode = 0;
8113 unsigned NumOperands = 0;
8114 switch (Op.getNode()->getOpcode()) {
8116 // Due to an isel shortcoming, be conservative if this add is likely to be
8117 // selected as part of a load-modify-store instruction. When the root node
8118 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8119 // uses of other nodes in the match, such as the ADD in this case. This
8120 // leads to the ADD being left around and reselected, with the result being
8121 // two adds in the output. Alas, even if none our users are stores, that
8122 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8123 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8124 // climbing the DAG back to the root, and it doesn't seem to be worth the
8126 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8127 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8128 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8131 if (ConstantSDNode *C =
8132 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8133 // An add of one will be selected as an INC.
8134 if (C->getAPIntValue() == 1) {
8135 Opcode = X86ISD::INC;
8140 // An add of negative one (subtract of one) will be selected as a DEC.
8141 if (C->getAPIntValue().isAllOnesValue()) {
8142 Opcode = X86ISD::DEC;
8148 // Otherwise use a regular EFLAGS-setting add.
8149 Opcode = X86ISD::ADD;
8153 // If the primary and result isn't used, don't bother using X86ISD::AND,
8154 // because a TEST instruction will be better.
8155 bool NonFlagUse = false;
8156 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8157 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8159 unsigned UOpNo = UI.getOperandNo();
8160 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8161 // Look pass truncate.
8162 UOpNo = User->use_begin().getOperandNo();
8163 User = *User->use_begin();
8166 if (User->getOpcode() != ISD::BRCOND &&
8167 User->getOpcode() != ISD::SETCC &&
8168 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8181 // Due to the ISEL shortcoming noted above, be conservative if this op is
8182 // likely to be selected as part of a load-modify-store instruction.
8183 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8184 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8185 if (UI->getOpcode() == ISD::STORE)
8188 // Otherwise use a regular EFLAGS-setting instruction.
8189 switch (Op.getNode()->getOpcode()) {
8190 default: llvm_unreachable("unexpected operator!");
8191 case ISD::SUB: Opcode = X86ISD::SUB; break;
8192 case ISD::OR: Opcode = X86ISD::OR; break;
8193 case ISD::XOR: Opcode = X86ISD::XOR; break;
8194 case ISD::AND: Opcode = X86ISD::AND; break;
8206 return SDValue(Op.getNode(), 1);
8213 // Emit a CMP with 0, which is the TEST pattern.
8214 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8215 DAG.getConstant(0, Op.getValueType()));
8217 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8218 SmallVector<SDValue, 4> Ops;
8219 for (unsigned i = 0; i != NumOperands; ++i)
8220 Ops.push_back(Op.getOperand(i));
8222 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8223 DAG.ReplaceAllUsesWith(Op, New);
8224 return SDValue(New.getNode(), 1);
8227 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8229 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8230 SelectionDAG &DAG) const {
8231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8232 if (C->getAPIntValue() == 0)
8233 return EmitTest(Op0, X86CC, DAG);
8235 DebugLoc dl = Op0.getDebugLoc();
8236 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8239 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8240 /// if it's possible.
8241 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8242 DebugLoc dl, SelectionDAG &DAG) const {
8243 SDValue Op0 = And.getOperand(0);
8244 SDValue Op1 = And.getOperand(1);
8245 if (Op0.getOpcode() == ISD::TRUNCATE)
8246 Op0 = Op0.getOperand(0);
8247 if (Op1.getOpcode() == ISD::TRUNCATE)
8248 Op1 = Op1.getOperand(0);
8251 if (Op1.getOpcode() == ISD::SHL)
8252 std::swap(Op0, Op1);
8253 if (Op0.getOpcode() == ISD::SHL) {
8254 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8255 if (And00C->getZExtValue() == 1) {
8256 // If we looked past a truncate, check that it's only truncating away
8258 unsigned BitWidth = Op0.getValueSizeInBits();
8259 unsigned AndBitWidth = And.getValueSizeInBits();
8260 if (BitWidth > AndBitWidth) {
8261 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8262 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8263 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8267 RHS = Op0.getOperand(1);
8269 } else if (Op1.getOpcode() == ISD::Constant) {
8270 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8271 SDValue AndLHS = Op0;
8272 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8273 LHS = AndLHS.getOperand(0);
8274 RHS = AndLHS.getOperand(1);
8278 if (LHS.getNode()) {
8279 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8280 // instruction. Since the shift amount is in-range-or-undefined, we know
8281 // that doing a bittest on the i32 value is ok. We extend to i32 because
8282 // the encoding for the i16 version is larger than the i32 version.
8283 // Also promote i16 to i32 for performance / code size reason.
8284 if (LHS.getValueType() == MVT::i8 ||
8285 LHS.getValueType() == MVT::i16)
8286 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8288 // If the operand types disagree, extend the shift amount to match. Since
8289 // BT ignores high bits (like shifts) we can use anyextend.
8290 if (LHS.getValueType() != RHS.getValueType())
8291 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8293 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8294 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8295 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8296 DAG.getConstant(Cond, MVT::i8), BT);
8302 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8303 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8304 SDValue Op0 = Op.getOperand(0);
8305 SDValue Op1 = Op.getOperand(1);
8306 DebugLoc dl = Op.getDebugLoc();
8307 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8309 // Optimize to BT if possible.
8310 // Lower (X & (1 << N)) == 0 to BT(X, N).
8311 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8312 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8313 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8314 Op1.getOpcode() == ISD::Constant &&
8315 cast<ConstantSDNode>(Op1)->isNullValue() &&
8316 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8317 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8318 if (NewSetCC.getNode())
8322 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8324 if (Op1.getOpcode() == ISD::Constant &&
8325 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8326 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8327 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8329 // If the input is a setcc, then reuse the input setcc or use a new one with
8330 // the inverted condition.
8331 if (Op0.getOpcode() == X86ISD::SETCC) {
8332 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8333 bool Invert = (CC == ISD::SETNE) ^
8334 cast<ConstantSDNode>(Op1)->isNullValue();
8335 if (!Invert) return Op0;
8337 CCode = X86::GetOppositeBranchCondition(CCode);
8338 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8339 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8343 bool isFP = Op1.getValueType().isFloatingPoint();
8344 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8345 if (X86CC == X86::COND_INVALID)
8348 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8349 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8350 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8353 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8354 // ones, and then concatenate the result back.
8355 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8356 EVT VT = Op.getValueType();
8358 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
8359 "Unsupported value type for operation");
8361 int NumElems = VT.getVectorNumElements();
8362 DebugLoc dl = Op.getDebugLoc();
8363 SDValue CC = Op.getOperand(2);
8364 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8365 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8367 // Extract the LHS vectors
8368 SDValue LHS = Op.getOperand(0);
8369 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8370 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8372 // Extract the RHS vectors
8373 SDValue RHS = Op.getOperand(1);
8374 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8375 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8377 // Issue the operation on the smaller types and concatenate the result back
8378 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8379 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8380 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8381 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8382 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8386 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8388 SDValue Op0 = Op.getOperand(0);
8389 SDValue Op1 = Op.getOperand(1);
8390 SDValue CC = Op.getOperand(2);
8391 EVT VT = Op.getValueType();
8392 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8393 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8394 DebugLoc dl = Op.getDebugLoc();
8398 EVT EltVT = Op0.getValueType().getVectorElementType();
8399 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8401 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8404 switch (SetCCOpcode) {
8407 case ISD::SETEQ: SSECC = 0; break;
8409 case ISD::SETGT: Swap = true; // Fallthrough
8411 case ISD::SETOLT: SSECC = 1; break;
8413 case ISD::SETGE: Swap = true; // Fallthrough
8415 case ISD::SETOLE: SSECC = 2; break;
8416 case ISD::SETUO: SSECC = 3; break;
8418 case ISD::SETNE: SSECC = 4; break;
8419 case ISD::SETULE: Swap = true;
8420 case ISD::SETUGE: SSECC = 5; break;
8421 case ISD::SETULT: Swap = true;
8422 case ISD::SETUGT: SSECC = 6; break;
8423 case ISD::SETO: SSECC = 7; break;
8426 std::swap(Op0, Op1);
8428 // In the two special cases we can't handle, emit two comparisons.
8430 if (SetCCOpcode == ISD::SETUEQ) {
8432 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8433 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8434 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8436 else if (SetCCOpcode == ISD::SETONE) {
8438 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8439 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8440 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8442 llvm_unreachable("Illegal FP comparison");
8444 // Handle all other FP comparisons here.
8445 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8448 // Break 256-bit integer vector compare into smaller ones.
8449 if (!isFP && VT.getSizeInBits() == 256)
8450 return Lower256IntVETCC(Op, DAG);
8452 // We are handling one of the integer comparisons here. Since SSE only has
8453 // GT and EQ comparisons for integer, swapping operands and multiple
8454 // operations may be required for some comparisons.
8455 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8456 bool Swap = false, Invert = false, FlipSigns = false;
8458 switch (VT.getSimpleVT().SimpleTy) {
8460 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8461 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8462 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8463 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8466 switch (SetCCOpcode) {
8468 case ISD::SETNE: Invert = true;
8469 case ISD::SETEQ: Opc = EQOpc; break;
8470 case ISD::SETLT: Swap = true;
8471 case ISD::SETGT: Opc = GTOpc; break;
8472 case ISD::SETGE: Swap = true;
8473 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8474 case ISD::SETULT: Swap = true;
8475 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8476 case ISD::SETUGE: Swap = true;
8477 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8480 std::swap(Op0, Op1);
8482 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8483 // bits of the inputs before performing those operations.
8485 EVT EltVT = VT.getVectorElementType();
8486 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8488 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8489 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8491 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8492 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8495 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8497 // If the logical-not of the result is required, perform that now.
8499 Result = DAG.getNOT(dl, Result, VT);
8504 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8505 static bool isX86LogicalCmp(SDValue Op) {
8506 unsigned Opc = Op.getNode()->getOpcode();
8507 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8509 if (Op.getResNo() == 1 &&
8510 (Opc == X86ISD::ADD ||
8511 Opc == X86ISD::SUB ||
8512 Opc == X86ISD::ADC ||
8513 Opc == X86ISD::SBB ||
8514 Opc == X86ISD::SMUL ||
8515 Opc == X86ISD::UMUL ||
8516 Opc == X86ISD::INC ||
8517 Opc == X86ISD::DEC ||
8518 Opc == X86ISD::OR ||
8519 Opc == X86ISD::XOR ||
8520 Opc == X86ISD::AND))
8523 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8529 static bool isZero(SDValue V) {
8530 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8531 return C && C->isNullValue();
8534 static bool isAllOnes(SDValue V) {
8535 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8536 return C && C->isAllOnesValue();
8539 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8540 bool addTest = true;
8541 SDValue Cond = Op.getOperand(0);
8542 SDValue Op1 = Op.getOperand(1);
8543 SDValue Op2 = Op.getOperand(2);
8544 DebugLoc DL = Op.getDebugLoc();
8547 if (Cond.getOpcode() == ISD::SETCC) {
8548 SDValue NewCond = LowerSETCC(Cond, DAG);
8549 if (NewCond.getNode())
8553 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8554 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8555 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8556 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8557 if (Cond.getOpcode() == X86ISD::SETCC &&
8558 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8559 isZero(Cond.getOperand(1).getOperand(1))) {
8560 SDValue Cmp = Cond.getOperand(1);
8562 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8564 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8565 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8566 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8568 SDValue CmpOp0 = Cmp.getOperand(0);
8569 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8570 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8572 SDValue Res = // Res = 0 or -1.
8573 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8574 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8576 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8577 Res = DAG.getNOT(DL, Res, Res.getValueType());
8579 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8580 if (N2C == 0 || !N2C->isNullValue())
8581 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8586 // Look past (and (setcc_carry (cmp ...)), 1).
8587 if (Cond.getOpcode() == ISD::AND &&
8588 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8589 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8590 if (C && C->getAPIntValue() == 1)
8591 Cond = Cond.getOperand(0);
8594 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8595 // setting operand in place of the X86ISD::SETCC.
8596 if (Cond.getOpcode() == X86ISD::SETCC ||
8597 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8598 CC = Cond.getOperand(0);
8600 SDValue Cmp = Cond.getOperand(1);
8601 unsigned Opc = Cmp.getOpcode();
8602 EVT VT = Op.getValueType();
8604 bool IllegalFPCMov = false;
8605 if (VT.isFloatingPoint() && !VT.isVector() &&
8606 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8607 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8609 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8610 Opc == X86ISD::BT) { // FIXME
8617 // Look pass the truncate.
8618 if (Cond.getOpcode() == ISD::TRUNCATE)
8619 Cond = Cond.getOperand(0);
8621 // We know the result of AND is compared against zero. Try to match
8623 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8624 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8625 if (NewSetCC.getNode()) {
8626 CC = NewSetCC.getOperand(0);
8627 Cond = NewSetCC.getOperand(1);
8634 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8635 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8638 // a < b ? -1 : 0 -> RES = ~setcc_carry
8639 // a < b ? 0 : -1 -> RES = setcc_carry
8640 // a >= b ? -1 : 0 -> RES = setcc_carry
8641 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8642 if (Cond.getOpcode() == X86ISD::CMP) {
8643 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8645 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8646 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8647 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8648 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8649 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8650 return DAG.getNOT(DL, Res, Res.getValueType());
8655 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8656 // condition is true.
8657 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8658 SDValue Ops[] = { Op2, Op1, CC, Cond };
8659 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8662 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8663 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8664 // from the AND / OR.
8665 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8666 Opc = Op.getOpcode();
8667 if (Opc != ISD::OR && Opc != ISD::AND)
8669 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8670 Op.getOperand(0).hasOneUse() &&
8671 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8672 Op.getOperand(1).hasOneUse());
8675 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8676 // 1 and that the SETCC node has a single use.
8677 static bool isXor1OfSetCC(SDValue Op) {
8678 if (Op.getOpcode() != ISD::XOR)
8680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8681 if (N1C && N1C->getAPIntValue() == 1) {
8682 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8683 Op.getOperand(0).hasOneUse();
8688 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8689 bool addTest = true;
8690 SDValue Chain = Op.getOperand(0);
8691 SDValue Cond = Op.getOperand(1);
8692 SDValue Dest = Op.getOperand(2);
8693 DebugLoc dl = Op.getDebugLoc();
8696 if (Cond.getOpcode() == ISD::SETCC) {
8697 SDValue NewCond = LowerSETCC(Cond, DAG);
8698 if (NewCond.getNode())
8702 // FIXME: LowerXALUO doesn't handle these!!
8703 else if (Cond.getOpcode() == X86ISD::ADD ||
8704 Cond.getOpcode() == X86ISD::SUB ||
8705 Cond.getOpcode() == X86ISD::SMUL ||
8706 Cond.getOpcode() == X86ISD::UMUL)
8707 Cond = LowerXALUO(Cond, DAG);
8710 // Look pass (and (setcc_carry (cmp ...)), 1).
8711 if (Cond.getOpcode() == ISD::AND &&
8712 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8713 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8714 if (C && C->getAPIntValue() == 1)
8715 Cond = Cond.getOperand(0);
8718 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8719 // setting operand in place of the X86ISD::SETCC.
8720 if (Cond.getOpcode() == X86ISD::SETCC ||
8721 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8722 CC = Cond.getOperand(0);
8724 SDValue Cmp = Cond.getOperand(1);
8725 unsigned Opc = Cmp.getOpcode();
8726 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8727 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8731 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8735 // These can only come from an arithmetic instruction with overflow,
8736 // e.g. SADDO, UADDO.
8737 Cond = Cond.getNode()->getOperand(1);
8744 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8745 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8746 if (CondOpc == ISD::OR) {
8747 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8748 // two branches instead of an explicit OR instruction with a
8750 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8751 isX86LogicalCmp(Cmp)) {
8752 CC = Cond.getOperand(0).getOperand(0);
8753 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8754 Chain, Dest, CC, Cmp);
8755 CC = Cond.getOperand(1).getOperand(0);
8759 } else { // ISD::AND
8760 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8761 // two branches instead of an explicit AND instruction with a
8762 // separate test. However, we only do this if this block doesn't
8763 // have a fall-through edge, because this requires an explicit
8764 // jmp when the condition is false.
8765 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8766 isX86LogicalCmp(Cmp) &&
8767 Op.getNode()->hasOneUse()) {
8768 X86::CondCode CCode =
8769 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8770 CCode = X86::GetOppositeBranchCondition(CCode);
8771 CC = DAG.getConstant(CCode, MVT::i8);
8772 SDNode *User = *Op.getNode()->use_begin();
8773 // Look for an unconditional branch following this conditional branch.
8774 // We need this because we need to reverse the successors in order
8775 // to implement FCMP_OEQ.
8776 if (User->getOpcode() == ISD::BR) {
8777 SDValue FalseBB = User->getOperand(1);
8779 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8780 assert(NewBR == User);
8784 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8785 Chain, Dest, CC, Cmp);
8786 X86::CondCode CCode =
8787 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8788 CCode = X86::GetOppositeBranchCondition(CCode);
8789 CC = DAG.getConstant(CCode, MVT::i8);
8795 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8796 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8797 // It should be transformed during dag combiner except when the condition
8798 // is set by a arithmetics with overflow node.
8799 X86::CondCode CCode =
8800 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8801 CCode = X86::GetOppositeBranchCondition(CCode);
8802 CC = DAG.getConstant(CCode, MVT::i8);
8803 Cond = Cond.getOperand(0).getOperand(1);
8809 // Look pass the truncate.
8810 if (Cond.getOpcode() == ISD::TRUNCATE)
8811 Cond = Cond.getOperand(0);
8813 // We know the result of AND is compared against zero. Try to match
8815 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8816 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8817 if (NewSetCC.getNode()) {
8818 CC = NewSetCC.getOperand(0);
8819 Cond = NewSetCC.getOperand(1);
8826 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8827 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8829 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8830 Chain, Dest, CC, Cond);
8834 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8835 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8836 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8837 // that the guard pages used by the OS virtual memory manager are allocated in
8838 // correct sequence.
8840 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8841 SelectionDAG &DAG) const {
8842 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
8843 "This should be used only on Windows targets");
8844 assert(!Subtarget->isTargetEnvMacho());
8845 DebugLoc dl = Op.getDebugLoc();
8848 SDValue Chain = Op.getOperand(0);
8849 SDValue Size = Op.getOperand(1);
8850 // FIXME: Ensure alignment here
8854 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
8855 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8857 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8858 Flag = Chain.getValue(1);
8860 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8862 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8863 Flag = Chain.getValue(1);
8865 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8867 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8868 return DAG.getMergeValues(Ops1, 2, dl);
8871 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8872 MachineFunction &MF = DAG.getMachineFunction();
8873 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8875 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8876 DebugLoc DL = Op.getDebugLoc();
8878 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8879 // vastart just stores the address of the VarArgsFrameIndex slot into the
8880 // memory location argument.
8881 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8883 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8884 MachinePointerInfo(SV), false, false, 0);
8888 // gp_offset (0 - 6 * 8)
8889 // fp_offset (48 - 48 + 8 * 16)
8890 // overflow_arg_area (point to parameters coming in memory).
8892 SmallVector<SDValue, 8> MemOps;
8893 SDValue FIN = Op.getOperand(1);
8895 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8896 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8898 FIN, MachinePointerInfo(SV), false, false, 0);
8899 MemOps.push_back(Store);
8902 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8903 FIN, DAG.getIntPtrConstant(4));
8904 Store = DAG.getStore(Op.getOperand(0), DL,
8905 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8907 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8908 MemOps.push_back(Store);
8910 // Store ptr to overflow_arg_area
8911 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8912 FIN, DAG.getIntPtrConstant(4));
8913 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8915 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8916 MachinePointerInfo(SV, 8),
8918 MemOps.push_back(Store);
8920 // Store ptr to reg_save_area.
8921 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8922 FIN, DAG.getIntPtrConstant(8));
8923 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8925 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8926 MachinePointerInfo(SV, 16), false, false, 0);
8927 MemOps.push_back(Store);
8928 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8929 &MemOps[0], MemOps.size());
8932 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8933 assert(Subtarget->is64Bit() &&
8934 "LowerVAARG only handles 64-bit va_arg!");
8935 assert((Subtarget->isTargetLinux() ||
8936 Subtarget->isTargetDarwin()) &&
8937 "Unhandled target in LowerVAARG");
8938 assert(Op.getNode()->getNumOperands() == 4);
8939 SDValue Chain = Op.getOperand(0);
8940 SDValue SrcPtr = Op.getOperand(1);
8941 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8942 unsigned Align = Op.getConstantOperandVal(3);
8943 DebugLoc dl = Op.getDebugLoc();
8945 EVT ArgVT = Op.getNode()->getValueType(0);
8946 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8947 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8950 // Decide which area this value should be read from.
8951 // TODO: Implement the AMD64 ABI in its entirety. This simple
8952 // selection mechanism works only for the basic types.
8953 if (ArgVT == MVT::f80) {
8954 llvm_unreachable("va_arg for f80 not yet implemented");
8955 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8956 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8957 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8958 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8960 llvm_unreachable("Unhandled argument type in LowerVAARG");
8964 // Sanity Check: Make sure using fp_offset makes sense.
8965 assert(!UseSoftFloat &&
8966 !(DAG.getMachineFunction()
8967 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8968 Subtarget->hasXMM());
8971 // Insert VAARG_64 node into the DAG
8972 // VAARG_64 returns two values: Variable Argument Address, Chain
8973 SmallVector<SDValue, 11> InstOps;
8974 InstOps.push_back(Chain);
8975 InstOps.push_back(SrcPtr);
8976 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8977 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8978 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8979 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8980 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8981 VTs, &InstOps[0], InstOps.size(),
8983 MachinePointerInfo(SV),
8988 Chain = VAARG.getValue(1);
8990 // Load the next argument and return it
8991 return DAG.getLoad(ArgVT, dl,
8994 MachinePointerInfo(),
8998 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
8999 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9000 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9001 SDValue Chain = Op.getOperand(0);
9002 SDValue DstPtr = Op.getOperand(1);
9003 SDValue SrcPtr = Op.getOperand(2);
9004 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9005 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9006 DebugLoc DL = Op.getDebugLoc();
9008 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9009 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9011 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9015 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9016 DebugLoc dl = Op.getDebugLoc();
9017 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9019 default: return SDValue(); // Don't custom lower most intrinsics.
9020 // Comparison intrinsics.
9021 case Intrinsic::x86_sse_comieq_ss:
9022 case Intrinsic::x86_sse_comilt_ss:
9023 case Intrinsic::x86_sse_comile_ss:
9024 case Intrinsic::x86_sse_comigt_ss:
9025 case Intrinsic::x86_sse_comige_ss:
9026 case Intrinsic::x86_sse_comineq_ss:
9027 case Intrinsic::x86_sse_ucomieq_ss:
9028 case Intrinsic::x86_sse_ucomilt_ss:
9029 case Intrinsic::x86_sse_ucomile_ss:
9030 case Intrinsic::x86_sse_ucomigt_ss:
9031 case Intrinsic::x86_sse_ucomige_ss:
9032 case Intrinsic::x86_sse_ucomineq_ss:
9033 case Intrinsic::x86_sse2_comieq_sd:
9034 case Intrinsic::x86_sse2_comilt_sd:
9035 case Intrinsic::x86_sse2_comile_sd:
9036 case Intrinsic::x86_sse2_comigt_sd:
9037 case Intrinsic::x86_sse2_comige_sd:
9038 case Intrinsic::x86_sse2_comineq_sd:
9039 case Intrinsic::x86_sse2_ucomieq_sd:
9040 case Intrinsic::x86_sse2_ucomilt_sd:
9041 case Intrinsic::x86_sse2_ucomile_sd:
9042 case Intrinsic::x86_sse2_ucomigt_sd:
9043 case Intrinsic::x86_sse2_ucomige_sd:
9044 case Intrinsic::x86_sse2_ucomineq_sd: {
9046 ISD::CondCode CC = ISD::SETCC_INVALID;
9049 case Intrinsic::x86_sse_comieq_ss:
9050 case Intrinsic::x86_sse2_comieq_sd:
9054 case Intrinsic::x86_sse_comilt_ss:
9055 case Intrinsic::x86_sse2_comilt_sd:
9059 case Intrinsic::x86_sse_comile_ss:
9060 case Intrinsic::x86_sse2_comile_sd:
9064 case Intrinsic::x86_sse_comigt_ss:
9065 case Intrinsic::x86_sse2_comigt_sd:
9069 case Intrinsic::x86_sse_comige_ss:
9070 case Intrinsic::x86_sse2_comige_sd:
9074 case Intrinsic::x86_sse_comineq_ss:
9075 case Intrinsic::x86_sse2_comineq_sd:
9079 case Intrinsic::x86_sse_ucomieq_ss:
9080 case Intrinsic::x86_sse2_ucomieq_sd:
9081 Opc = X86ISD::UCOMI;
9084 case Intrinsic::x86_sse_ucomilt_ss:
9085 case Intrinsic::x86_sse2_ucomilt_sd:
9086 Opc = X86ISD::UCOMI;
9089 case Intrinsic::x86_sse_ucomile_ss:
9090 case Intrinsic::x86_sse2_ucomile_sd:
9091 Opc = X86ISD::UCOMI;
9094 case Intrinsic::x86_sse_ucomigt_ss:
9095 case Intrinsic::x86_sse2_ucomigt_sd:
9096 Opc = X86ISD::UCOMI;
9099 case Intrinsic::x86_sse_ucomige_ss:
9100 case Intrinsic::x86_sse2_ucomige_sd:
9101 Opc = X86ISD::UCOMI;
9104 case Intrinsic::x86_sse_ucomineq_ss:
9105 case Intrinsic::x86_sse2_ucomineq_sd:
9106 Opc = X86ISD::UCOMI;
9111 SDValue LHS = Op.getOperand(1);
9112 SDValue RHS = Op.getOperand(2);
9113 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9114 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9115 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9116 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9117 DAG.getConstant(X86CC, MVT::i8), Cond);
9118 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9120 // ptest and testp intrinsics. The intrinsic these come from are designed to
9121 // return an integer value, not just an instruction so lower it to the ptest
9122 // or testp pattern and a setcc for the result.
9123 case Intrinsic::x86_sse41_ptestz:
9124 case Intrinsic::x86_sse41_ptestc:
9125 case Intrinsic::x86_sse41_ptestnzc:
9126 case Intrinsic::x86_avx_ptestz_256:
9127 case Intrinsic::x86_avx_ptestc_256:
9128 case Intrinsic::x86_avx_ptestnzc_256:
9129 case Intrinsic::x86_avx_vtestz_ps:
9130 case Intrinsic::x86_avx_vtestc_ps:
9131 case Intrinsic::x86_avx_vtestnzc_ps:
9132 case Intrinsic::x86_avx_vtestz_pd:
9133 case Intrinsic::x86_avx_vtestc_pd:
9134 case Intrinsic::x86_avx_vtestnzc_pd:
9135 case Intrinsic::x86_avx_vtestz_ps_256:
9136 case Intrinsic::x86_avx_vtestc_ps_256:
9137 case Intrinsic::x86_avx_vtestnzc_ps_256:
9138 case Intrinsic::x86_avx_vtestz_pd_256:
9139 case Intrinsic::x86_avx_vtestc_pd_256:
9140 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9141 bool IsTestPacked = false;
9144 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9145 case Intrinsic::x86_avx_vtestz_ps:
9146 case Intrinsic::x86_avx_vtestz_pd:
9147 case Intrinsic::x86_avx_vtestz_ps_256:
9148 case Intrinsic::x86_avx_vtestz_pd_256:
9149 IsTestPacked = true; // Fallthrough
9150 case Intrinsic::x86_sse41_ptestz:
9151 case Intrinsic::x86_avx_ptestz_256:
9153 X86CC = X86::COND_E;
9155 case Intrinsic::x86_avx_vtestc_ps:
9156 case Intrinsic::x86_avx_vtestc_pd:
9157 case Intrinsic::x86_avx_vtestc_ps_256:
9158 case Intrinsic::x86_avx_vtestc_pd_256:
9159 IsTestPacked = true; // Fallthrough
9160 case Intrinsic::x86_sse41_ptestc:
9161 case Intrinsic::x86_avx_ptestc_256:
9163 X86CC = X86::COND_B;
9165 case Intrinsic::x86_avx_vtestnzc_ps:
9166 case Intrinsic::x86_avx_vtestnzc_pd:
9167 case Intrinsic::x86_avx_vtestnzc_ps_256:
9168 case Intrinsic::x86_avx_vtestnzc_pd_256:
9169 IsTestPacked = true; // Fallthrough
9170 case Intrinsic::x86_sse41_ptestnzc:
9171 case Intrinsic::x86_avx_ptestnzc_256:
9173 X86CC = X86::COND_A;
9177 SDValue LHS = Op.getOperand(1);
9178 SDValue RHS = Op.getOperand(2);
9179 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9180 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9181 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9182 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9183 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9186 // Fix vector shift instructions where the last operand is a non-immediate
9188 case Intrinsic::x86_sse2_pslli_w:
9189 case Intrinsic::x86_sse2_pslli_d:
9190 case Intrinsic::x86_sse2_pslli_q:
9191 case Intrinsic::x86_sse2_psrli_w:
9192 case Intrinsic::x86_sse2_psrli_d:
9193 case Intrinsic::x86_sse2_psrli_q:
9194 case Intrinsic::x86_sse2_psrai_w:
9195 case Intrinsic::x86_sse2_psrai_d:
9196 case Intrinsic::x86_mmx_pslli_w:
9197 case Intrinsic::x86_mmx_pslli_d:
9198 case Intrinsic::x86_mmx_pslli_q:
9199 case Intrinsic::x86_mmx_psrli_w:
9200 case Intrinsic::x86_mmx_psrli_d:
9201 case Intrinsic::x86_mmx_psrli_q:
9202 case Intrinsic::x86_mmx_psrai_w:
9203 case Intrinsic::x86_mmx_psrai_d: {
9204 SDValue ShAmt = Op.getOperand(2);
9205 if (isa<ConstantSDNode>(ShAmt))
9208 unsigned NewIntNo = 0;
9209 EVT ShAmtVT = MVT::v4i32;
9211 case Intrinsic::x86_sse2_pslli_w:
9212 NewIntNo = Intrinsic::x86_sse2_psll_w;
9214 case Intrinsic::x86_sse2_pslli_d:
9215 NewIntNo = Intrinsic::x86_sse2_psll_d;
9217 case Intrinsic::x86_sse2_pslli_q:
9218 NewIntNo = Intrinsic::x86_sse2_psll_q;
9220 case Intrinsic::x86_sse2_psrli_w:
9221 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9223 case Intrinsic::x86_sse2_psrli_d:
9224 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9226 case Intrinsic::x86_sse2_psrli_q:
9227 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9229 case Intrinsic::x86_sse2_psrai_w:
9230 NewIntNo = Intrinsic::x86_sse2_psra_w;
9232 case Intrinsic::x86_sse2_psrai_d:
9233 NewIntNo = Intrinsic::x86_sse2_psra_d;
9236 ShAmtVT = MVT::v2i32;
9238 case Intrinsic::x86_mmx_pslli_w:
9239 NewIntNo = Intrinsic::x86_mmx_psll_w;
9241 case Intrinsic::x86_mmx_pslli_d:
9242 NewIntNo = Intrinsic::x86_mmx_psll_d;
9244 case Intrinsic::x86_mmx_pslli_q:
9245 NewIntNo = Intrinsic::x86_mmx_psll_q;
9247 case Intrinsic::x86_mmx_psrli_w:
9248 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9250 case Intrinsic::x86_mmx_psrli_d:
9251 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9253 case Intrinsic::x86_mmx_psrli_q:
9254 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9256 case Intrinsic::x86_mmx_psrai_w:
9257 NewIntNo = Intrinsic::x86_mmx_psra_w;
9259 case Intrinsic::x86_mmx_psrai_d:
9260 NewIntNo = Intrinsic::x86_mmx_psra_d;
9262 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9268 // The vector shift intrinsics with scalars uses 32b shift amounts but
9269 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9273 ShOps[1] = DAG.getConstant(0, MVT::i32);
9274 if (ShAmtVT == MVT::v4i32) {
9275 ShOps[2] = DAG.getUNDEF(MVT::i32);
9276 ShOps[3] = DAG.getUNDEF(MVT::i32);
9277 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9279 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9280 // FIXME this must be lowered to get rid of the invalid type.
9283 EVT VT = Op.getValueType();
9284 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9285 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9286 DAG.getConstant(NewIntNo, MVT::i32),
9287 Op.getOperand(1), ShAmt);
9292 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9293 SelectionDAG &DAG) const {
9294 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9295 MFI->setReturnAddressIsTaken(true);
9297 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9298 DebugLoc dl = Op.getDebugLoc();
9301 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9303 DAG.getConstant(TD->getPointerSize(),
9304 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9305 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9306 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9308 MachinePointerInfo(), false, false, 0);
9311 // Just load the return address.
9312 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9313 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9314 RetAddrFI, MachinePointerInfo(), false, false, 0);
9317 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9318 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9319 MFI->setFrameAddressIsTaken(true);
9321 EVT VT = Op.getValueType();
9322 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9323 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9324 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9325 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9327 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9328 MachinePointerInfo(),
9333 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9334 SelectionDAG &DAG) const {
9335 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9338 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9339 MachineFunction &MF = DAG.getMachineFunction();
9340 SDValue Chain = Op.getOperand(0);
9341 SDValue Offset = Op.getOperand(1);
9342 SDValue Handler = Op.getOperand(2);
9343 DebugLoc dl = Op.getDebugLoc();
9345 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9346 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9348 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9350 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9351 DAG.getIntPtrConstant(TD->getPointerSize()));
9352 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9353 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9355 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9356 MF.getRegInfo().addLiveOut(StoreAddrReg);
9358 return DAG.getNode(X86ISD::EH_RETURN, dl,
9360 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9363 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
9364 SelectionDAG &DAG) const {
9365 SDValue Root = Op.getOperand(0);
9366 SDValue Trmp = Op.getOperand(1); // trampoline
9367 SDValue FPtr = Op.getOperand(2); // nested function
9368 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9369 DebugLoc dl = Op.getDebugLoc();
9371 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9373 if (Subtarget->is64Bit()) {
9374 SDValue OutChains[6];
9376 // Large code-model.
9377 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9378 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9380 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9381 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9383 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9385 // Load the pointer to the nested function into R11.
9386 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9387 SDValue Addr = Trmp;
9388 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9389 Addr, MachinePointerInfo(TrmpAddr),
9392 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9393 DAG.getConstant(2, MVT::i64));
9394 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9395 MachinePointerInfo(TrmpAddr, 2),
9398 // Load the 'nest' parameter value into R10.
9399 // R10 is specified in X86CallingConv.td
9400 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9401 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9402 DAG.getConstant(10, MVT::i64));
9403 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9404 Addr, MachinePointerInfo(TrmpAddr, 10),
9407 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9408 DAG.getConstant(12, MVT::i64));
9409 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9410 MachinePointerInfo(TrmpAddr, 12),
9413 // Jump to the nested function.
9414 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9415 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9416 DAG.getConstant(20, MVT::i64));
9417 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9418 Addr, MachinePointerInfo(TrmpAddr, 20),
9421 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9422 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9423 DAG.getConstant(22, MVT::i64));
9424 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9425 MachinePointerInfo(TrmpAddr, 22),
9429 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
9430 return DAG.getMergeValues(Ops, 2, dl);
9432 const Function *Func =
9433 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9434 CallingConv::ID CC = Func->getCallingConv();
9439 llvm_unreachable("Unsupported calling convention");
9440 case CallingConv::C:
9441 case CallingConv::X86_StdCall: {
9442 // Pass 'nest' parameter in ECX.
9443 // Must be kept in sync with X86CallingConv.td
9446 // Check that ECX wasn't needed by an 'inreg' parameter.
9447 FunctionType *FTy = Func->getFunctionType();
9448 const AttrListPtr &Attrs = Func->getAttributes();
9450 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9451 unsigned InRegCount = 0;
9454 for (FunctionType::param_iterator I = FTy->param_begin(),
9455 E = FTy->param_end(); I != E; ++I, ++Idx)
9456 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9457 // FIXME: should only count parameters that are lowered to integers.
9458 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9460 if (InRegCount > 2) {
9461 report_fatal_error("Nest register in use - reduce number of inreg"
9467 case CallingConv::X86_FastCall:
9468 case CallingConv::X86_ThisCall:
9469 case CallingConv::Fast:
9470 // Pass 'nest' parameter in EAX.
9471 // Must be kept in sync with X86CallingConv.td
9476 SDValue OutChains[4];
9479 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9480 DAG.getConstant(10, MVT::i32));
9481 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9483 // This is storing the opcode for MOV32ri.
9484 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9485 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9486 OutChains[0] = DAG.getStore(Root, dl,
9487 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9488 Trmp, MachinePointerInfo(TrmpAddr),
9491 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9492 DAG.getConstant(1, MVT::i32));
9493 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9494 MachinePointerInfo(TrmpAddr, 1),
9497 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9498 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9499 DAG.getConstant(5, MVT::i32));
9500 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9501 MachinePointerInfo(TrmpAddr, 5),
9504 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9505 DAG.getConstant(6, MVT::i32));
9506 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9507 MachinePointerInfo(TrmpAddr, 6),
9511 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
9512 return DAG.getMergeValues(Ops, 2, dl);
9516 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9517 SelectionDAG &DAG) const {
9519 The rounding mode is in bits 11:10 of FPSR, and has the following
9526 FLT_ROUNDS, on the other hand, expects the following:
9533 To perform the conversion, we do:
9534 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9537 MachineFunction &MF = DAG.getMachineFunction();
9538 const TargetMachine &TM = MF.getTarget();
9539 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9540 unsigned StackAlignment = TFI.getStackAlignment();
9541 EVT VT = Op.getValueType();
9542 DebugLoc DL = Op.getDebugLoc();
9544 // Save FP Control Word to stack slot
9545 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9546 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9549 MachineMemOperand *MMO =
9550 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9551 MachineMemOperand::MOStore, 2, 2);
9553 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9554 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9555 DAG.getVTList(MVT::Other),
9556 Ops, 2, MVT::i16, MMO);
9558 // Load FP Control Word from stack slot
9559 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9560 MachinePointerInfo(), false, false, 0);
9562 // Transform as necessary
9564 DAG.getNode(ISD::SRL, DL, MVT::i16,
9565 DAG.getNode(ISD::AND, DL, MVT::i16,
9566 CWD, DAG.getConstant(0x800, MVT::i16)),
9567 DAG.getConstant(11, MVT::i8));
9569 DAG.getNode(ISD::SRL, DL, MVT::i16,
9570 DAG.getNode(ISD::AND, DL, MVT::i16,
9571 CWD, DAG.getConstant(0x400, MVT::i16)),
9572 DAG.getConstant(9, MVT::i8));
9575 DAG.getNode(ISD::AND, DL, MVT::i16,
9576 DAG.getNode(ISD::ADD, DL, MVT::i16,
9577 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9578 DAG.getConstant(1, MVT::i16)),
9579 DAG.getConstant(3, MVT::i16));
9582 return DAG.getNode((VT.getSizeInBits() < 16 ?
9583 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9586 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9587 EVT VT = Op.getValueType();
9589 unsigned NumBits = VT.getSizeInBits();
9590 DebugLoc dl = Op.getDebugLoc();
9592 Op = Op.getOperand(0);
9593 if (VT == MVT::i8) {
9594 // Zero extend to i32 since there is not an i8 bsr.
9596 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9599 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9600 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9601 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9603 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9606 DAG.getConstant(NumBits+NumBits-1, OpVT),
9607 DAG.getConstant(X86::COND_E, MVT::i8),
9610 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9612 // Finally xor with NumBits-1.
9613 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9616 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9620 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9621 EVT VT = Op.getValueType();
9623 unsigned NumBits = VT.getSizeInBits();
9624 DebugLoc dl = Op.getDebugLoc();
9626 Op = Op.getOperand(0);
9627 if (VT == MVT::i8) {
9629 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9632 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9633 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9634 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9636 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9639 DAG.getConstant(NumBits, OpVT),
9640 DAG.getConstant(X86::COND_E, MVT::i8),
9643 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9646 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9650 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9651 // ones, and then concatenate the result back.
9652 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9653 EVT VT = Op.getValueType();
9655 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9656 "Unsupported value type for operation");
9658 int NumElems = VT.getVectorNumElements();
9659 DebugLoc dl = Op.getDebugLoc();
9660 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9661 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9663 // Extract the LHS vectors
9664 SDValue LHS = Op.getOperand(0);
9665 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9666 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9668 // Extract the RHS vectors
9669 SDValue RHS = Op.getOperand(1);
9670 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9671 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9673 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9674 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9676 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9677 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9678 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9681 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9682 assert(Op.getValueType().getSizeInBits() == 256 &&
9683 Op.getValueType().isInteger() &&
9684 "Only handle AVX 256-bit vector integer operation");
9685 return Lower256IntArith(Op, DAG);
9688 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9689 assert(Op.getValueType().getSizeInBits() == 256 &&
9690 Op.getValueType().isInteger() &&
9691 "Only handle AVX 256-bit vector integer operation");
9692 return Lower256IntArith(Op, DAG);
9695 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9696 EVT VT = Op.getValueType();
9698 // Decompose 256-bit ops into smaller 128-bit ops.
9699 if (VT.getSizeInBits() == 256)
9700 return Lower256IntArith(Op, DAG);
9702 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9703 DebugLoc dl = Op.getDebugLoc();
9705 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9706 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9707 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9708 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9709 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9711 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9712 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9713 // return AloBlo + AloBhi + AhiBlo;
9715 SDValue A = Op.getOperand(0);
9716 SDValue B = Op.getOperand(1);
9718 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9719 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9720 A, DAG.getConstant(32, MVT::i32));
9721 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9722 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9723 B, DAG.getConstant(32, MVT::i32));
9724 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9725 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9727 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9728 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9730 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9731 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9733 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9734 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9735 AloBhi, DAG.getConstant(32, MVT::i32));
9736 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9737 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9738 AhiBlo, DAG.getConstant(32, MVT::i32));
9739 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9740 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9744 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9746 EVT VT = Op.getValueType();
9747 DebugLoc dl = Op.getDebugLoc();
9748 SDValue R = Op.getOperand(0);
9749 SDValue Amt = Op.getOperand(1);
9750 LLVMContext *Context = DAG.getContext();
9752 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9755 // Decompose 256-bit shifts into smaller 128-bit shifts.
9756 if (VT.getSizeInBits() == 256) {
9757 int NumElems = VT.getVectorNumElements();
9758 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9759 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9761 // Extract the two vectors
9762 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9763 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9766 // Recreate the shift amount vectors
9768 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9769 // Constant shift amount
9770 SmallVector<SDValue, 4> Amt1Csts;
9771 SmallVector<SDValue, 4> Amt2Csts;
9772 for (int i = 0; i < NumElems/2; ++i)
9773 Amt1Csts.push_back(Amt->getOperand(i));
9774 for (int i = NumElems/2; i < NumElems; ++i)
9775 Amt2Csts.push_back(Amt->getOperand(i));
9777 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9778 &Amt1Csts[0], NumElems/2);
9779 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9780 &Amt2Csts[0], NumElems/2);
9782 // Variable shift amount
9783 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9784 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9788 // Issue new vector shifts for the smaller types
9789 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9790 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9792 // Concatenate the result back
9793 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9796 // Optimize shl/srl/sra with constant shift amount.
9797 if (isSplatVector(Amt.getNode())) {
9798 SDValue SclrAmt = Amt->getOperand(0);
9799 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9800 uint64_t ShiftAmt = C->getZExtValue();
9802 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9803 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9804 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9805 R, DAG.getConstant(ShiftAmt, MVT::i32));
9807 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9808 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9809 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9810 R, DAG.getConstant(ShiftAmt, MVT::i32));
9812 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9813 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9814 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9815 R, DAG.getConstant(ShiftAmt, MVT::i32));
9817 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9818 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9819 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9820 R, DAG.getConstant(ShiftAmt, MVT::i32));
9822 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9823 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9824 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9825 R, DAG.getConstant(ShiftAmt, MVT::i32));
9827 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9828 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9829 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9830 R, DAG.getConstant(ShiftAmt, MVT::i32));
9832 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9833 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9834 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9835 R, DAG.getConstant(ShiftAmt, MVT::i32));
9837 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9838 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9839 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9840 R, DAG.getConstant(ShiftAmt, MVT::i32));
9844 // Lower SHL with variable shift amount.
9845 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9846 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9847 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9848 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9850 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9852 std::vector<Constant*> CV(4, CI);
9853 Constant *C = ConstantVector::get(CV);
9854 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9855 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9856 MachinePointerInfo::getConstantPool(),
9859 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9860 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9861 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9862 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9864 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9866 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9867 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9868 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9870 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9871 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9873 std::vector<Constant*> CVM1(16, CM1);
9874 std::vector<Constant*> CVM2(16, CM2);
9875 Constant *C = ConstantVector::get(CVM1);
9876 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9877 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9878 MachinePointerInfo::getConstantPool(),
9881 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9882 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9883 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9884 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9885 DAG.getConstant(4, MVT::i32));
9886 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9888 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9890 C = ConstantVector::get(CVM2);
9891 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9892 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9893 MachinePointerInfo::getConstantPool(),
9896 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9897 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9898 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9899 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9900 DAG.getConstant(2, MVT::i32));
9901 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9903 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9905 // return pblendv(r, r+r, a);
9906 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9907 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9913 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9914 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9915 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9916 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9917 // has only one use.
9918 SDNode *N = Op.getNode();
9919 SDValue LHS = N->getOperand(0);
9920 SDValue RHS = N->getOperand(1);
9921 unsigned BaseOp = 0;
9923 DebugLoc DL = Op.getDebugLoc();
9924 switch (Op.getOpcode()) {
9925 default: llvm_unreachable("Unknown ovf instruction!");
9927 // A subtract of one will be selected as a INC. Note that INC doesn't
9928 // set CF, so we can't do this for UADDO.
9929 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9931 BaseOp = X86ISD::INC;
9935 BaseOp = X86ISD::ADD;
9939 BaseOp = X86ISD::ADD;
9943 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9944 // set CF, so we can't do this for USUBO.
9945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9947 BaseOp = X86ISD::DEC;
9951 BaseOp = X86ISD::SUB;
9955 BaseOp = X86ISD::SUB;
9959 BaseOp = X86ISD::SMUL;
9962 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
9963 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
9965 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
9968 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9969 DAG.getConstant(X86::COND_O, MVT::i32),
9970 SDValue(Sum.getNode(), 2));
9972 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9976 // Also sets EFLAGS.
9977 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
9978 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
9981 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9982 DAG.getConstant(Cond, MVT::i32),
9983 SDValue(Sum.getNode(), 1));
9985 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9988 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
9989 DebugLoc dl = Op.getDebugLoc();
9990 SDNode* Node = Op.getNode();
9991 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
9992 EVT VT = Node->getValueType(0);
9994 if (Subtarget->hasSSE2() && VT.isVector()) {
9995 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
9996 ExtraVT.getScalarType().getSizeInBits();
9997 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
9999 unsigned SHLIntrinsicsID = 0;
10000 unsigned SRAIntrinsicsID = 0;
10001 switch (VT.getSimpleVT().SimpleTy) {
10005 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
10006 SRAIntrinsicsID = 0;
10010 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10011 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10015 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10016 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10021 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10022 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10023 Node->getOperand(0), ShAmt);
10025 // In case of 1 bit sext, no need to shr
10026 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
10028 if (SRAIntrinsicsID) {
10029 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10030 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10040 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10041 DebugLoc dl = Op.getDebugLoc();
10043 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10044 // There isn't any reason to disable it if the target processor supports it.
10045 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10046 SDValue Chain = Op.getOperand(0);
10047 SDValue Zero = DAG.getConstant(0, MVT::i32);
10049 DAG.getRegister(X86::ESP, MVT::i32), // Base
10050 DAG.getTargetConstant(1, MVT::i8), // Scale
10051 DAG.getRegister(0, MVT::i32), // Index
10052 DAG.getTargetConstant(0, MVT::i32), // Disp
10053 DAG.getRegister(0, MVT::i32), // Segment.
10058 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10059 array_lengthof(Ops));
10060 return SDValue(Res, 0);
10063 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10065 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10067 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10068 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10069 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10070 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10072 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10073 if (!Op1 && !Op2 && !Op3 && Op4)
10074 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10076 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10077 if (Op1 && !Op2 && !Op3 && !Op4)
10078 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10080 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10082 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10085 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10086 SelectionDAG &DAG) const {
10087 DebugLoc dl = Op.getDebugLoc();
10088 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10089 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10090 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10091 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10093 // The only fence that needs an instruction is a sequentially-consistent
10094 // cross-thread fence.
10095 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10096 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10097 // no-sse2). There isn't any reason to disable it if the target processor
10099 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10100 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10102 SDValue Chain = Op.getOperand(0);
10103 SDValue Zero = DAG.getConstant(0, MVT::i32);
10105 DAG.getRegister(X86::ESP, MVT::i32), // Base
10106 DAG.getTargetConstant(1, MVT::i8), // Scale
10107 DAG.getRegister(0, MVT::i32), // Index
10108 DAG.getTargetConstant(0, MVT::i32), // Disp
10109 DAG.getRegister(0, MVT::i32), // Segment.
10114 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10115 array_lengthof(Ops));
10116 return SDValue(Res, 0);
10119 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10120 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10124 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10125 EVT T = Op.getValueType();
10126 DebugLoc DL = Op.getDebugLoc();
10129 switch(T.getSimpleVT().SimpleTy) {
10131 assert(false && "Invalid value type!");
10132 case MVT::i8: Reg = X86::AL; size = 1; break;
10133 case MVT::i16: Reg = X86::AX; size = 2; break;
10134 case MVT::i32: Reg = X86::EAX; size = 4; break;
10136 assert(Subtarget->is64Bit() && "Node not type legal!");
10137 Reg = X86::RAX; size = 8;
10140 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10141 Op.getOperand(2), SDValue());
10142 SDValue Ops[] = { cpIn.getValue(0),
10145 DAG.getTargetConstant(size, MVT::i8),
10146 cpIn.getValue(1) };
10147 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10148 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10149 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10152 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10156 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10157 SelectionDAG &DAG) const {
10158 assert(Subtarget->is64Bit() && "Result not type legalized?");
10159 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10160 SDValue TheChain = Op.getOperand(0);
10161 DebugLoc dl = Op.getDebugLoc();
10162 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10163 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10164 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10166 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10167 DAG.getConstant(32, MVT::i8));
10169 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10172 return DAG.getMergeValues(Ops, 2, dl);
10175 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10176 SelectionDAG &DAG) const {
10177 EVT SrcVT = Op.getOperand(0).getValueType();
10178 EVT DstVT = Op.getValueType();
10179 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10180 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10181 assert((DstVT == MVT::i64 ||
10182 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10183 "Unexpected custom BITCAST");
10184 // i64 <=> MMX conversions are Legal.
10185 if (SrcVT==MVT::i64 && DstVT.isVector())
10187 if (DstVT==MVT::i64 && SrcVT.isVector())
10189 // MMX <=> MMX conversions are Legal.
10190 if (SrcVT.isVector() && DstVT.isVector())
10192 // All other conversions need to be expanded.
10196 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10197 SDNode *Node = Op.getNode();
10198 DebugLoc dl = Node->getDebugLoc();
10199 EVT T = Node->getValueType(0);
10200 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10201 DAG.getConstant(0, T), Node->getOperand(2));
10202 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10203 cast<AtomicSDNode>(Node)->getMemoryVT(),
10204 Node->getOperand(0),
10205 Node->getOperand(1), negOp,
10206 cast<AtomicSDNode>(Node)->getSrcValue(),
10207 cast<AtomicSDNode>(Node)->getAlignment(),
10208 cast<AtomicSDNode>(Node)->getOrdering(),
10209 cast<AtomicSDNode>(Node)->getSynchScope());
10212 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10213 SDNode *Node = Op.getNode();
10214 DebugLoc dl = Node->getDebugLoc();
10215 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10217 // Convert seq_cst store -> xchg
10218 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10219 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10220 // (The only way to get a 16-byte store is cmpxchg16b)
10221 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10222 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10223 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10224 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10225 cast<AtomicSDNode>(Node)->getMemoryVT(),
10226 Node->getOperand(0),
10227 Node->getOperand(1), Node->getOperand(2),
10228 cast<AtomicSDNode>(Node)->getMemOperand(),
10229 cast<AtomicSDNode>(Node)->getOrdering(),
10230 cast<AtomicSDNode>(Node)->getSynchScope());
10231 return Swap.getValue(1);
10233 // Other atomic stores have a simple pattern.
10237 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10238 EVT VT = Op.getNode()->getValueType(0);
10240 // Let legalize expand this if it isn't a legal type yet.
10241 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10244 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10247 bool ExtraOp = false;
10248 switch (Op.getOpcode()) {
10249 default: assert(0 && "Invalid code");
10250 case ISD::ADDC: Opc = X86ISD::ADD; break;
10251 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10252 case ISD::SUBC: Opc = X86ISD::SUB; break;
10253 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10257 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10259 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10260 Op.getOperand(1), Op.getOperand(2));
10263 /// LowerOperation - Provide custom lowering hooks for some operations.
10265 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10266 switch (Op.getOpcode()) {
10267 default: llvm_unreachable("Should not custom lower this!");
10268 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10269 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10270 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10271 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10272 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10273 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10274 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10275 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10276 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10277 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10278 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10279 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10280 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10281 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10282 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10283 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10284 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10285 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10286 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10287 case ISD::SHL_PARTS:
10288 case ISD::SRA_PARTS:
10289 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10290 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10291 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10292 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10293 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10294 case ISD::FABS: return LowerFABS(Op, DAG);
10295 case ISD::FNEG: return LowerFNEG(Op, DAG);
10296 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10297 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10298 case ISD::SETCC: return LowerSETCC(Op, DAG);
10299 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
10300 case ISD::SELECT: return LowerSELECT(Op, DAG);
10301 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10302 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10303 case ISD::VASTART: return LowerVASTART(Op, DAG);
10304 case ISD::VAARG: return LowerVAARG(Op, DAG);
10305 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10306 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10307 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10308 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10309 case ISD::FRAME_TO_ARGS_OFFSET:
10310 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10311 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10312 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10313 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
10314 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10315 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10316 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10317 case ISD::MUL: return LowerMUL(Op, DAG);
10320 case ISD::SHL: return LowerShift(Op, DAG);
10326 case ISD::UMULO: return LowerXALUO(Op, DAG);
10327 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10328 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10332 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10333 case ISD::ADD: return LowerADD(Op, DAG);
10334 case ISD::SUB: return LowerSUB(Op, DAG);
10338 static void ReplaceATOMIC_LOAD(SDNode *Node,
10339 SmallVectorImpl<SDValue> &Results,
10340 SelectionDAG &DAG) {
10341 DebugLoc dl = Node->getDebugLoc();
10342 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10344 // Convert wide load -> cmpxchg8b/cmpxchg16b
10345 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10346 // (The only way to get a 16-byte load is cmpxchg16b)
10347 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10348 SDValue Zero = DAG.getConstant(0, cast<AtomicSDNode>(Node)->getMemoryVT());
10349 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
10350 cast<AtomicSDNode>(Node)->getMemoryVT(),
10351 Node->getOperand(0),
10352 Node->getOperand(1), Zero, Zero,
10353 cast<AtomicSDNode>(Node)->getMemOperand(),
10354 cast<AtomicSDNode>(Node)->getOrdering(),
10355 cast<AtomicSDNode>(Node)->getSynchScope());
10356 Results.push_back(Swap.getValue(0));
10357 Results.push_back(Swap.getValue(1));
10360 void X86TargetLowering::
10361 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10362 SelectionDAG &DAG, unsigned NewOp) const {
10363 EVT T = Node->getValueType(0);
10364 DebugLoc dl = Node->getDebugLoc();
10365 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10367 SDValue Chain = Node->getOperand(0);
10368 SDValue In1 = Node->getOperand(1);
10369 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10370 Node->getOperand(2), DAG.getIntPtrConstant(0));
10371 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10372 Node->getOperand(2), DAG.getIntPtrConstant(1));
10373 SDValue Ops[] = { Chain, In1, In2L, In2H };
10374 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10376 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10377 cast<MemSDNode>(Node)->getMemOperand());
10378 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10379 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10380 Results.push_back(Result.getValue(2));
10383 /// ReplaceNodeResults - Replace a node with an illegal result type
10384 /// with a new node built out of custom code.
10385 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10386 SmallVectorImpl<SDValue>&Results,
10387 SelectionDAG &DAG) const {
10388 DebugLoc dl = N->getDebugLoc();
10389 switch (N->getOpcode()) {
10391 assert(false && "Do not know how to custom type legalize this operation!");
10393 case ISD::SIGN_EXTEND_INREG:
10398 // We don't want to expand or promote these.
10400 case ISD::FP_TO_SINT: {
10401 std::pair<SDValue,SDValue> Vals =
10402 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10403 SDValue FIST = Vals.first, StackSlot = Vals.second;
10404 if (FIST.getNode() != 0) {
10405 EVT VT = N->getValueType(0);
10406 // Return a load from the stack slot.
10407 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10408 MachinePointerInfo(), false, false, 0));
10412 case ISD::READCYCLECOUNTER: {
10413 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10414 SDValue TheChain = N->getOperand(0);
10415 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10416 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10418 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10420 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10421 SDValue Ops[] = { eax, edx };
10422 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10423 Results.push_back(edx.getValue(1));
10426 case ISD::ATOMIC_CMP_SWAP: {
10427 EVT T = N->getValueType(0);
10428 assert (T == MVT::i64 || T == MVT::i128 && "can only expand cmpxchg pair");
10429 bool Regs64bit = T == MVT::i128;
10430 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10431 SDValue cpInL, cpInH;
10432 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10433 DAG.getConstant(0, HalfT));
10434 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10435 DAG.getConstant(1, HalfT));
10436 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10437 Regs64bit ? X86::RAX : X86::EAX,
10439 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10440 Regs64bit ? X86::RDX : X86::EDX,
10441 cpInH, cpInL.getValue(1));
10442 SDValue swapInL, swapInH;
10443 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10444 DAG.getConstant(0, HalfT));
10445 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10446 DAG.getConstant(1, HalfT));
10447 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10448 Regs64bit ? X86::RBX : X86::EBX,
10449 swapInL, cpInH.getValue(1));
10450 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10451 Regs64bit ? X86::RCX : X86::ECX,
10452 swapInH, swapInL.getValue(1));
10453 SDValue Ops[] = { swapInH.getValue(0),
10455 swapInH.getValue(1) };
10456 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10457 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10458 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10459 X86ISD::LCMPXCHG8_DAG;
10460 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10462 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10463 Regs64bit ? X86::RAX : X86::EAX,
10464 HalfT, Result.getValue(1));
10465 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10466 Regs64bit ? X86::RDX : X86::EDX,
10467 HalfT, cpOutL.getValue(2));
10468 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10469 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10470 Results.push_back(cpOutH.getValue(1));
10473 case ISD::ATOMIC_LOAD_ADD:
10474 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10476 case ISD::ATOMIC_LOAD_AND:
10477 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10479 case ISD::ATOMIC_LOAD_NAND:
10480 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10482 case ISD::ATOMIC_LOAD_OR:
10483 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10485 case ISD::ATOMIC_LOAD_SUB:
10486 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10488 case ISD::ATOMIC_LOAD_XOR:
10489 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10491 case ISD::ATOMIC_SWAP:
10492 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10494 case ISD::ATOMIC_LOAD:
10495 ReplaceATOMIC_LOAD(N, Results, DAG);
10499 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10501 default: return NULL;
10502 case X86ISD::BSF: return "X86ISD::BSF";
10503 case X86ISD::BSR: return "X86ISD::BSR";
10504 case X86ISD::SHLD: return "X86ISD::SHLD";
10505 case X86ISD::SHRD: return "X86ISD::SHRD";
10506 case X86ISD::FAND: return "X86ISD::FAND";
10507 case X86ISD::FOR: return "X86ISD::FOR";
10508 case X86ISD::FXOR: return "X86ISD::FXOR";
10509 case X86ISD::FSRL: return "X86ISD::FSRL";
10510 case X86ISD::FILD: return "X86ISD::FILD";
10511 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10512 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10513 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10514 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10515 case X86ISD::FLD: return "X86ISD::FLD";
10516 case X86ISD::FST: return "X86ISD::FST";
10517 case X86ISD::CALL: return "X86ISD::CALL";
10518 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10519 case X86ISD::BT: return "X86ISD::BT";
10520 case X86ISD::CMP: return "X86ISD::CMP";
10521 case X86ISD::COMI: return "X86ISD::COMI";
10522 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10523 case X86ISD::SETCC: return "X86ISD::SETCC";
10524 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10525 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10526 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10527 case X86ISD::CMOV: return "X86ISD::CMOV";
10528 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10529 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10530 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10531 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10532 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10533 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10534 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10535 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10536 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10537 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10538 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10539 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10540 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10541 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10542 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10543 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10544 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10545 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
10546 case X86ISD::FMAX: return "X86ISD::FMAX";
10547 case X86ISD::FMIN: return "X86ISD::FMIN";
10548 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10549 case X86ISD::FRCP: return "X86ISD::FRCP";
10550 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10551 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10552 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10553 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10554 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10555 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10556 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10557 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10558 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10559 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10560 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10561 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10562 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10563 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10564 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10565 case X86ISD::VSHL: return "X86ISD::VSHL";
10566 case X86ISD::VSRL: return "X86ISD::VSRL";
10567 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10568 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10569 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10570 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10571 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10572 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10573 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10574 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10575 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10576 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10577 case X86ISD::ADD: return "X86ISD::ADD";
10578 case X86ISD::SUB: return "X86ISD::SUB";
10579 case X86ISD::ADC: return "X86ISD::ADC";
10580 case X86ISD::SBB: return "X86ISD::SBB";
10581 case X86ISD::SMUL: return "X86ISD::SMUL";
10582 case X86ISD::UMUL: return "X86ISD::UMUL";
10583 case X86ISD::INC: return "X86ISD::INC";
10584 case X86ISD::DEC: return "X86ISD::DEC";
10585 case X86ISD::OR: return "X86ISD::OR";
10586 case X86ISD::XOR: return "X86ISD::XOR";
10587 case X86ISD::AND: return "X86ISD::AND";
10588 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10589 case X86ISD::PTEST: return "X86ISD::PTEST";
10590 case X86ISD::TESTP: return "X86ISD::TESTP";
10591 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10592 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10593 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10594 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10595 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10596 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10597 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10598 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10599 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10600 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10601 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10602 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10603 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10604 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10605 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10606 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10607 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10608 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10609 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10610 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10611 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10612 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10613 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10614 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10615 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10616 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10617 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10618 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10619 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10620 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10621 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10622 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10623 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10624 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10625 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10626 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10627 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10628 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10629 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10630 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10631 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10632 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10633 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10634 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10638 // isLegalAddressingMode - Return true if the addressing mode represented
10639 // by AM is legal for this target, for a load/store of the specified type.
10640 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10642 // X86 supports extremely general addressing modes.
10643 CodeModel::Model M = getTargetMachine().getCodeModel();
10644 Reloc::Model R = getTargetMachine().getRelocationModel();
10646 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10647 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10652 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10654 // If a reference to this global requires an extra load, we can't fold it.
10655 if (isGlobalStubReference(GVFlags))
10658 // If BaseGV requires a register for the PIC base, we cannot also have a
10659 // BaseReg specified.
10660 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10663 // If lower 4G is not available, then we must use rip-relative addressing.
10664 if ((M != CodeModel::Small || R != Reloc::Static) &&
10665 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10669 switch (AM.Scale) {
10675 // These scales always work.
10680 // These scales are formed with basereg+scalereg. Only accept if there is
10685 default: // Other stuff never works.
10693 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10694 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10696 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10697 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10698 if (NumBits1 <= NumBits2)
10703 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10704 if (!VT1.isInteger() || !VT2.isInteger())
10706 unsigned NumBits1 = VT1.getSizeInBits();
10707 unsigned NumBits2 = VT2.getSizeInBits();
10708 if (NumBits1 <= NumBits2)
10713 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10714 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10715 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10718 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10719 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10720 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10723 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10724 // i16 instructions are longer (0x66 prefix) and potentially slower.
10725 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10728 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10729 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10730 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10731 /// are assumed to be legal.
10733 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10735 // Very little shuffling can be done for 64-bit vectors right now.
10736 if (VT.getSizeInBits() == 64)
10737 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10739 // FIXME: pshufb, blends, shifts.
10740 return (VT.getVectorNumElements() == 2 ||
10741 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10742 isMOVLMask(M, VT) ||
10743 isSHUFPMask(M, VT) ||
10744 isPSHUFDMask(M, VT) ||
10745 isPSHUFHWMask(M, VT) ||
10746 isPSHUFLWMask(M, VT) ||
10747 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10748 isUNPCKLMask(M, VT) ||
10749 isUNPCKHMask(M, VT) ||
10750 isUNPCKL_v_undef_Mask(M, VT) ||
10751 isUNPCKH_v_undef_Mask(M, VT));
10755 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10757 unsigned NumElts = VT.getVectorNumElements();
10758 // FIXME: This collection of masks seems suspect.
10761 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10762 return (isMOVLMask(Mask, VT) ||
10763 isCommutedMOVLMask(Mask, VT, true) ||
10764 isSHUFPMask(Mask, VT) ||
10765 isCommutedSHUFPMask(Mask, VT));
10770 //===----------------------------------------------------------------------===//
10771 // X86 Scheduler Hooks
10772 //===----------------------------------------------------------------------===//
10774 // private utility function
10775 MachineBasicBlock *
10776 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10777 MachineBasicBlock *MBB,
10784 TargetRegisterClass *RC,
10785 bool invSrc) const {
10786 // For the atomic bitwise operator, we generate
10789 // ld t1 = [bitinstr.addr]
10790 // op t2 = t1, [bitinstr.val]
10792 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10794 // fallthrough -->nextMBB
10795 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10796 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10797 MachineFunction::iterator MBBIter = MBB;
10800 /// First build the CFG
10801 MachineFunction *F = MBB->getParent();
10802 MachineBasicBlock *thisMBB = MBB;
10803 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10804 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10805 F->insert(MBBIter, newMBB);
10806 F->insert(MBBIter, nextMBB);
10808 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10809 nextMBB->splice(nextMBB->begin(), thisMBB,
10810 llvm::next(MachineBasicBlock::iterator(bInstr)),
10812 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10814 // Update thisMBB to fall through to newMBB
10815 thisMBB->addSuccessor(newMBB);
10817 // newMBB jumps to itself and fall through to nextMBB
10818 newMBB->addSuccessor(nextMBB);
10819 newMBB->addSuccessor(newMBB);
10821 // Insert instructions into newMBB based on incoming instruction
10822 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10823 "unexpected number of operands");
10824 DebugLoc dl = bInstr->getDebugLoc();
10825 MachineOperand& destOper = bInstr->getOperand(0);
10826 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10827 int numArgs = bInstr->getNumOperands() - 1;
10828 for (int i=0; i < numArgs; ++i)
10829 argOpers[i] = &bInstr->getOperand(i+1);
10831 // x86 address has 4 operands: base, index, scale, and displacement
10832 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10833 int valArgIndx = lastAddrIndx + 1;
10835 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10836 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10837 for (int i=0; i <= lastAddrIndx; ++i)
10838 (*MIB).addOperand(*argOpers[i]);
10840 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10842 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10847 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10848 assert((argOpers[valArgIndx]->isReg() ||
10849 argOpers[valArgIndx]->isImm()) &&
10850 "invalid operand");
10851 if (argOpers[valArgIndx]->isReg())
10852 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10854 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10856 (*MIB).addOperand(*argOpers[valArgIndx]);
10858 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10861 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10862 for (int i=0; i <= lastAddrIndx; ++i)
10863 (*MIB).addOperand(*argOpers[i]);
10865 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10866 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10867 bInstr->memoperands_end());
10869 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10870 MIB.addReg(EAXreg);
10873 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10875 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10879 // private utility function: 64 bit atomics on 32 bit host.
10880 MachineBasicBlock *
10881 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10882 MachineBasicBlock *MBB,
10887 bool invSrc) const {
10888 // For the atomic bitwise operator, we generate
10889 // thisMBB (instructions are in pairs, except cmpxchg8b)
10890 // ld t1,t2 = [bitinstr.addr]
10892 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10893 // op t5, t6 <- out1, out2, [bitinstr.val]
10894 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10895 // mov ECX, EBX <- t5, t6
10896 // mov EAX, EDX <- t1, t2
10897 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10898 // mov t3, t4 <- EAX, EDX
10900 // result in out1, out2
10901 // fallthrough -->nextMBB
10903 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10904 const unsigned LoadOpc = X86::MOV32rm;
10905 const unsigned NotOpc = X86::NOT32r;
10906 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10907 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10908 MachineFunction::iterator MBBIter = MBB;
10911 /// First build the CFG
10912 MachineFunction *F = MBB->getParent();
10913 MachineBasicBlock *thisMBB = MBB;
10914 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10915 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10916 F->insert(MBBIter, newMBB);
10917 F->insert(MBBIter, nextMBB);
10919 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10920 nextMBB->splice(nextMBB->begin(), thisMBB,
10921 llvm::next(MachineBasicBlock::iterator(bInstr)),
10923 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10925 // Update thisMBB to fall through to newMBB
10926 thisMBB->addSuccessor(newMBB);
10928 // newMBB jumps to itself and fall through to nextMBB
10929 newMBB->addSuccessor(nextMBB);
10930 newMBB->addSuccessor(newMBB);
10932 DebugLoc dl = bInstr->getDebugLoc();
10933 // Insert instructions into newMBB based on incoming instruction
10934 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10935 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10936 "unexpected number of operands");
10937 MachineOperand& dest1Oper = bInstr->getOperand(0);
10938 MachineOperand& dest2Oper = bInstr->getOperand(1);
10939 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10940 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10941 argOpers[i] = &bInstr->getOperand(i+2);
10943 // We use some of the operands multiple times, so conservatively just
10944 // clear any kill flags that might be present.
10945 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10946 argOpers[i]->setIsKill(false);
10949 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10950 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10952 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10953 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
10954 for (int i=0; i <= lastAddrIndx; ++i)
10955 (*MIB).addOperand(*argOpers[i]);
10956 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10957 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
10958 // add 4 to displacement.
10959 for (int i=0; i <= lastAddrIndx-2; ++i)
10960 (*MIB).addOperand(*argOpers[i]);
10961 MachineOperand newOp3 = *(argOpers[3]);
10962 if (newOp3.isImm())
10963 newOp3.setImm(newOp3.getImm()+4);
10965 newOp3.setOffset(newOp3.getOffset()+4);
10966 (*MIB).addOperand(newOp3);
10967 (*MIB).addOperand(*argOpers[lastAddrIndx]);
10969 // t3/4 are defined later, at the bottom of the loop
10970 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
10971 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
10972 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
10973 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
10974 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
10975 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
10977 // The subsequent operations should be using the destination registers of
10978 //the PHI instructions.
10980 t1 = F->getRegInfo().createVirtualRegister(RC);
10981 t2 = F->getRegInfo().createVirtualRegister(RC);
10982 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
10983 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
10985 t1 = dest1Oper.getReg();
10986 t2 = dest2Oper.getReg();
10989 int valArgIndx = lastAddrIndx + 1;
10990 assert((argOpers[valArgIndx]->isReg() ||
10991 argOpers[valArgIndx]->isImm()) &&
10992 "invalid operand");
10993 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
10994 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
10995 if (argOpers[valArgIndx]->isReg())
10996 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
10998 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
10999 if (regOpcL != X86::MOV32rr)
11001 (*MIB).addOperand(*argOpers[valArgIndx]);
11002 assert(argOpers[valArgIndx + 1]->isReg() ==
11003 argOpers[valArgIndx]->isReg());
11004 assert(argOpers[valArgIndx + 1]->isImm() ==
11005 argOpers[valArgIndx]->isImm());
11006 if (argOpers[valArgIndx + 1]->isReg())
11007 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11009 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11010 if (regOpcH != X86::MOV32rr)
11012 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11014 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11016 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11019 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11021 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11024 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11025 for (int i=0; i <= lastAddrIndx; ++i)
11026 (*MIB).addOperand(*argOpers[i]);
11028 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11029 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11030 bInstr->memoperands_end());
11032 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11033 MIB.addReg(X86::EAX);
11034 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11035 MIB.addReg(X86::EDX);
11038 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11040 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11044 // private utility function
11045 MachineBasicBlock *
11046 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11047 MachineBasicBlock *MBB,
11048 unsigned cmovOpc) const {
11049 // For the atomic min/max operator, we generate
11052 // ld t1 = [min/max.addr]
11053 // mov t2 = [min/max.val]
11055 // cmov[cond] t2 = t1
11057 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11059 // fallthrough -->nextMBB
11061 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11062 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11063 MachineFunction::iterator MBBIter = MBB;
11066 /// First build the CFG
11067 MachineFunction *F = MBB->getParent();
11068 MachineBasicBlock *thisMBB = MBB;
11069 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11070 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11071 F->insert(MBBIter, newMBB);
11072 F->insert(MBBIter, nextMBB);
11074 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11075 nextMBB->splice(nextMBB->begin(), thisMBB,
11076 llvm::next(MachineBasicBlock::iterator(mInstr)),
11078 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11080 // Update thisMBB to fall through to newMBB
11081 thisMBB->addSuccessor(newMBB);
11083 // newMBB jumps to newMBB and fall through to nextMBB
11084 newMBB->addSuccessor(nextMBB);
11085 newMBB->addSuccessor(newMBB);
11087 DebugLoc dl = mInstr->getDebugLoc();
11088 // Insert instructions into newMBB based on incoming instruction
11089 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11090 "unexpected number of operands");
11091 MachineOperand& destOper = mInstr->getOperand(0);
11092 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11093 int numArgs = mInstr->getNumOperands() - 1;
11094 for (int i=0; i < numArgs; ++i)
11095 argOpers[i] = &mInstr->getOperand(i+1);
11097 // x86 address has 4 operands: base, index, scale, and displacement
11098 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11099 int valArgIndx = lastAddrIndx + 1;
11101 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11102 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11103 for (int i=0; i <= lastAddrIndx; ++i)
11104 (*MIB).addOperand(*argOpers[i]);
11106 // We only support register and immediate values
11107 assert((argOpers[valArgIndx]->isReg() ||
11108 argOpers[valArgIndx]->isImm()) &&
11109 "invalid operand");
11111 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11112 if (argOpers[valArgIndx]->isReg())
11113 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11115 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11116 (*MIB).addOperand(*argOpers[valArgIndx]);
11118 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11121 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11126 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11127 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11131 // Cmp and exchange if none has modified the memory location
11132 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11133 for (int i=0; i <= lastAddrIndx; ++i)
11134 (*MIB).addOperand(*argOpers[i]);
11136 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11137 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11138 mInstr->memoperands_end());
11140 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11141 MIB.addReg(X86::EAX);
11144 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11146 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11150 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11151 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11152 // in the .td file.
11153 MachineBasicBlock *
11154 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11155 unsigned numArgs, bool memArg) const {
11156 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
11157 "Target must have SSE4.2 or AVX features enabled");
11159 DebugLoc dl = MI->getDebugLoc();
11160 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11162 if (!Subtarget->hasAVX()) {
11164 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11166 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11169 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11171 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11174 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11175 for (unsigned i = 0; i < numArgs; ++i) {
11176 MachineOperand &Op = MI->getOperand(i+1);
11177 if (!(Op.isReg() && Op.isImplicit()))
11178 MIB.addOperand(Op);
11180 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
11181 .addReg(X86::XMM0);
11183 MI->eraseFromParent();
11187 MachineBasicBlock *
11188 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11189 DebugLoc dl = MI->getDebugLoc();
11190 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11192 // Address into RAX/EAX, other two args into ECX, EDX.
11193 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11194 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11195 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11196 for (int i = 0; i < X86::AddrNumOperands; ++i)
11197 MIB.addOperand(MI->getOperand(i));
11199 unsigned ValOps = X86::AddrNumOperands;
11200 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11201 .addReg(MI->getOperand(ValOps).getReg());
11202 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11203 .addReg(MI->getOperand(ValOps+1).getReg());
11205 // The instruction doesn't actually take any operands though.
11206 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11208 MI->eraseFromParent(); // The pseudo is gone now.
11212 MachineBasicBlock *
11213 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11214 DebugLoc dl = MI->getDebugLoc();
11215 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11217 // First arg in ECX, the second in EAX.
11218 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11219 .addReg(MI->getOperand(0).getReg());
11220 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11221 .addReg(MI->getOperand(1).getReg());
11223 // The instruction doesn't actually take any operands though.
11224 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11226 MI->eraseFromParent(); // The pseudo is gone now.
11230 MachineBasicBlock *
11231 X86TargetLowering::EmitVAARG64WithCustomInserter(
11233 MachineBasicBlock *MBB) const {
11234 // Emit va_arg instruction on X86-64.
11236 // Operands to this pseudo-instruction:
11237 // 0 ) Output : destination address (reg)
11238 // 1-5) Input : va_list address (addr, i64mem)
11239 // 6 ) ArgSize : Size (in bytes) of vararg type
11240 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11241 // 8 ) Align : Alignment of type
11242 // 9 ) EFLAGS (implicit-def)
11244 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11245 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11247 unsigned DestReg = MI->getOperand(0).getReg();
11248 MachineOperand &Base = MI->getOperand(1);
11249 MachineOperand &Scale = MI->getOperand(2);
11250 MachineOperand &Index = MI->getOperand(3);
11251 MachineOperand &Disp = MI->getOperand(4);
11252 MachineOperand &Segment = MI->getOperand(5);
11253 unsigned ArgSize = MI->getOperand(6).getImm();
11254 unsigned ArgMode = MI->getOperand(7).getImm();
11255 unsigned Align = MI->getOperand(8).getImm();
11257 // Memory Reference
11258 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11259 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11260 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11262 // Machine Information
11263 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11264 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11265 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11266 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11267 DebugLoc DL = MI->getDebugLoc();
11269 // struct va_list {
11272 // i64 overflow_area (address)
11273 // i64 reg_save_area (address)
11275 // sizeof(va_list) = 24
11276 // alignment(va_list) = 8
11278 unsigned TotalNumIntRegs = 6;
11279 unsigned TotalNumXMMRegs = 8;
11280 bool UseGPOffset = (ArgMode == 1);
11281 bool UseFPOffset = (ArgMode == 2);
11282 unsigned MaxOffset = TotalNumIntRegs * 8 +
11283 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11285 /* Align ArgSize to a multiple of 8 */
11286 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11287 bool NeedsAlign = (Align > 8);
11289 MachineBasicBlock *thisMBB = MBB;
11290 MachineBasicBlock *overflowMBB;
11291 MachineBasicBlock *offsetMBB;
11292 MachineBasicBlock *endMBB;
11294 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11295 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11296 unsigned OffsetReg = 0;
11298 if (!UseGPOffset && !UseFPOffset) {
11299 // If we only pull from the overflow region, we don't create a branch.
11300 // We don't need to alter control flow.
11301 OffsetDestReg = 0; // unused
11302 OverflowDestReg = DestReg;
11305 overflowMBB = thisMBB;
11308 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11309 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11310 // If not, pull from overflow_area. (branch to overflowMBB)
11315 // offsetMBB overflowMBB
11320 // Registers for the PHI in endMBB
11321 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11322 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11324 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11325 MachineFunction *MF = MBB->getParent();
11326 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11327 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11328 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11330 MachineFunction::iterator MBBIter = MBB;
11333 // Insert the new basic blocks
11334 MF->insert(MBBIter, offsetMBB);
11335 MF->insert(MBBIter, overflowMBB);
11336 MF->insert(MBBIter, endMBB);
11338 // Transfer the remainder of MBB and its successor edges to endMBB.
11339 endMBB->splice(endMBB->begin(), thisMBB,
11340 llvm::next(MachineBasicBlock::iterator(MI)),
11342 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11344 // Make offsetMBB and overflowMBB successors of thisMBB
11345 thisMBB->addSuccessor(offsetMBB);
11346 thisMBB->addSuccessor(overflowMBB);
11348 // endMBB is a successor of both offsetMBB and overflowMBB
11349 offsetMBB->addSuccessor(endMBB);
11350 overflowMBB->addSuccessor(endMBB);
11352 // Load the offset value into a register
11353 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11354 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11358 .addDisp(Disp, UseFPOffset ? 4 : 0)
11359 .addOperand(Segment)
11360 .setMemRefs(MMOBegin, MMOEnd);
11362 // Check if there is enough room left to pull this argument.
11363 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11365 .addImm(MaxOffset + 8 - ArgSizeA8);
11367 // Branch to "overflowMBB" if offset >= max
11368 // Fall through to "offsetMBB" otherwise
11369 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11370 .addMBB(overflowMBB);
11373 // In offsetMBB, emit code to use the reg_save_area.
11375 assert(OffsetReg != 0);
11377 // Read the reg_save_area address.
11378 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11379 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11384 .addOperand(Segment)
11385 .setMemRefs(MMOBegin, MMOEnd);
11387 // Zero-extend the offset
11388 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11389 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11392 .addImm(X86::sub_32bit);
11394 // Add the offset to the reg_save_area to get the final address.
11395 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11396 .addReg(OffsetReg64)
11397 .addReg(RegSaveReg);
11399 // Compute the offset for the next argument
11400 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11401 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11403 .addImm(UseFPOffset ? 16 : 8);
11405 // Store it back into the va_list.
11406 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11410 .addDisp(Disp, UseFPOffset ? 4 : 0)
11411 .addOperand(Segment)
11412 .addReg(NextOffsetReg)
11413 .setMemRefs(MMOBegin, MMOEnd);
11416 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11421 // Emit code to use overflow area
11424 // Load the overflow_area address into a register.
11425 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11426 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11431 .addOperand(Segment)
11432 .setMemRefs(MMOBegin, MMOEnd);
11434 // If we need to align it, do so. Otherwise, just copy the address
11435 // to OverflowDestReg.
11437 // Align the overflow address
11438 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11439 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11441 // aligned_addr = (addr + (align-1)) & ~(align-1)
11442 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11443 .addReg(OverflowAddrReg)
11446 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11448 .addImm(~(uint64_t)(Align-1));
11450 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11451 .addReg(OverflowAddrReg);
11454 // Compute the next overflow address after this argument.
11455 // (the overflow address should be kept 8-byte aligned)
11456 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11457 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11458 .addReg(OverflowDestReg)
11459 .addImm(ArgSizeA8);
11461 // Store the new overflow address.
11462 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11467 .addOperand(Segment)
11468 .addReg(NextAddrReg)
11469 .setMemRefs(MMOBegin, MMOEnd);
11471 // If we branched, emit the PHI to the front of endMBB.
11473 BuildMI(*endMBB, endMBB->begin(), DL,
11474 TII->get(X86::PHI), DestReg)
11475 .addReg(OffsetDestReg).addMBB(offsetMBB)
11476 .addReg(OverflowDestReg).addMBB(overflowMBB);
11479 // Erase the pseudo instruction
11480 MI->eraseFromParent();
11485 MachineBasicBlock *
11486 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11488 MachineBasicBlock *MBB) const {
11489 // Emit code to save XMM registers to the stack. The ABI says that the
11490 // number of registers to save is given in %al, so it's theoretically
11491 // possible to do an indirect jump trick to avoid saving all of them,
11492 // however this code takes a simpler approach and just executes all
11493 // of the stores if %al is non-zero. It's less code, and it's probably
11494 // easier on the hardware branch predictor, and stores aren't all that
11495 // expensive anyway.
11497 // Create the new basic blocks. One block contains all the XMM stores,
11498 // and one block is the final destination regardless of whether any
11499 // stores were performed.
11500 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11501 MachineFunction *F = MBB->getParent();
11502 MachineFunction::iterator MBBIter = MBB;
11504 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11505 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11506 F->insert(MBBIter, XMMSaveMBB);
11507 F->insert(MBBIter, EndMBB);
11509 // Transfer the remainder of MBB and its successor edges to EndMBB.
11510 EndMBB->splice(EndMBB->begin(), MBB,
11511 llvm::next(MachineBasicBlock::iterator(MI)),
11513 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11515 // The original block will now fall through to the XMM save block.
11516 MBB->addSuccessor(XMMSaveMBB);
11517 // The XMMSaveMBB will fall through to the end block.
11518 XMMSaveMBB->addSuccessor(EndMBB);
11520 // Now add the instructions.
11521 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11522 DebugLoc DL = MI->getDebugLoc();
11524 unsigned CountReg = MI->getOperand(0).getReg();
11525 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11526 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11528 if (!Subtarget->isTargetWin64()) {
11529 // If %al is 0, branch around the XMM save block.
11530 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11531 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11532 MBB->addSuccessor(EndMBB);
11535 // In the XMM save block, save all the XMM argument registers.
11536 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11537 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11538 MachineMemOperand *MMO =
11539 F->getMachineMemOperand(
11540 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11541 MachineMemOperand::MOStore,
11542 /*Size=*/16, /*Align=*/16);
11543 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
11544 .addFrameIndex(RegSaveFrameIndex)
11545 .addImm(/*Scale=*/1)
11546 .addReg(/*IndexReg=*/0)
11547 .addImm(/*Disp=*/Offset)
11548 .addReg(/*Segment=*/0)
11549 .addReg(MI->getOperand(i).getReg())
11550 .addMemOperand(MMO);
11553 MI->eraseFromParent(); // The pseudo instruction is gone now.
11558 MachineBasicBlock *
11559 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11560 MachineBasicBlock *BB) const {
11561 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11562 DebugLoc DL = MI->getDebugLoc();
11564 // To "insert" a SELECT_CC instruction, we actually have to insert the
11565 // diamond control-flow pattern. The incoming instruction knows the
11566 // destination vreg to set, the condition code register to branch on, the
11567 // true/false values to select between, and a branch opcode to use.
11568 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11569 MachineFunction::iterator It = BB;
11575 // cmpTY ccX, r1, r2
11577 // fallthrough --> copy0MBB
11578 MachineBasicBlock *thisMBB = BB;
11579 MachineFunction *F = BB->getParent();
11580 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11581 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11582 F->insert(It, copy0MBB);
11583 F->insert(It, sinkMBB);
11585 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11586 // live into the sink and copy blocks.
11587 const MachineFunction *MF = BB->getParent();
11588 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
11589 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
11591 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
11592 const MachineOperand &MO = MI->getOperand(I);
11593 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
11594 unsigned Reg = MO.getReg();
11595 if (Reg != X86::EFLAGS) continue;
11596 copy0MBB->addLiveIn(Reg);
11597 sinkMBB->addLiveIn(Reg);
11600 // Transfer the remainder of BB and its successor edges to sinkMBB.
11601 sinkMBB->splice(sinkMBB->begin(), BB,
11602 llvm::next(MachineBasicBlock::iterator(MI)),
11604 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11606 // Add the true and fallthrough blocks as its successors.
11607 BB->addSuccessor(copy0MBB);
11608 BB->addSuccessor(sinkMBB);
11610 // Create the conditional branch instruction.
11612 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11613 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11616 // %FalseValue = ...
11617 // # fallthrough to sinkMBB
11618 copy0MBB->addSuccessor(sinkMBB);
11621 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11623 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11624 TII->get(X86::PHI), MI->getOperand(0).getReg())
11625 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11626 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11628 MI->eraseFromParent(); // The pseudo instruction is gone now.
11632 MachineBasicBlock *
11633 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11634 MachineBasicBlock *BB) const {
11635 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11636 DebugLoc DL = MI->getDebugLoc();
11638 assert(!Subtarget->isTargetEnvMacho());
11640 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11641 // non-trivial part is impdef of ESP.
11643 if (Subtarget->isTargetWin64()) {
11644 if (Subtarget->isTargetCygMing()) {
11645 // ___chkstk(Mingw64):
11646 // Clobbers R10, R11, RAX and EFLAGS.
11648 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11649 .addExternalSymbol("___chkstk")
11650 .addReg(X86::RAX, RegState::Implicit)
11651 .addReg(X86::RSP, RegState::Implicit)
11652 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11653 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11654 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11656 // __chkstk(MSVCRT): does not update stack pointer.
11657 // Clobbers R10, R11 and EFLAGS.
11658 // FIXME: RAX(allocated size) might be reused and not killed.
11659 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11660 .addExternalSymbol("__chkstk")
11661 .addReg(X86::RAX, RegState::Implicit)
11662 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11663 // RAX has the offset to subtracted from RSP.
11664 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11669 const char *StackProbeSymbol =
11670 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11672 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11673 .addExternalSymbol(StackProbeSymbol)
11674 .addReg(X86::EAX, RegState::Implicit)
11675 .addReg(X86::ESP, RegState::Implicit)
11676 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11677 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11678 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11681 MI->eraseFromParent(); // The pseudo instruction is gone now.
11685 MachineBasicBlock *
11686 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11687 MachineBasicBlock *BB) const {
11688 // This is pretty easy. We're taking the value that we received from
11689 // our load from the relocation, sticking it in either RDI (x86-64)
11690 // or EAX and doing an indirect call. The return value will then
11691 // be in the normal return register.
11692 const X86InstrInfo *TII
11693 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11694 DebugLoc DL = MI->getDebugLoc();
11695 MachineFunction *F = BB->getParent();
11697 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11698 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11700 if (Subtarget->is64Bit()) {
11701 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11702 TII->get(X86::MOV64rm), X86::RDI)
11704 .addImm(0).addReg(0)
11705 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11706 MI->getOperand(3).getTargetFlags())
11708 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11709 addDirectMem(MIB, X86::RDI);
11710 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11711 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11712 TII->get(X86::MOV32rm), X86::EAX)
11714 .addImm(0).addReg(0)
11715 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11716 MI->getOperand(3).getTargetFlags())
11718 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11719 addDirectMem(MIB, X86::EAX);
11721 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11722 TII->get(X86::MOV32rm), X86::EAX)
11723 .addReg(TII->getGlobalBaseReg(F))
11724 .addImm(0).addReg(0)
11725 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11726 MI->getOperand(3).getTargetFlags())
11728 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11729 addDirectMem(MIB, X86::EAX);
11732 MI->eraseFromParent(); // The pseudo instruction is gone now.
11736 MachineBasicBlock *
11737 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11738 MachineBasicBlock *BB) const {
11739 switch (MI->getOpcode()) {
11740 default: assert(false && "Unexpected instr type to insert");
11741 case X86::TAILJMPd64:
11742 case X86::TAILJMPr64:
11743 case X86::TAILJMPm64:
11744 assert(!"TAILJMP64 would not be touched here.");
11745 case X86::TCRETURNdi64:
11746 case X86::TCRETURNri64:
11747 case X86::TCRETURNmi64:
11748 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11749 // On AMD64, additional defs should be added before register allocation.
11750 if (!Subtarget->isTargetWin64()) {
11751 MI->addRegisterDefined(X86::RSI);
11752 MI->addRegisterDefined(X86::RDI);
11753 MI->addRegisterDefined(X86::XMM6);
11754 MI->addRegisterDefined(X86::XMM7);
11755 MI->addRegisterDefined(X86::XMM8);
11756 MI->addRegisterDefined(X86::XMM9);
11757 MI->addRegisterDefined(X86::XMM10);
11758 MI->addRegisterDefined(X86::XMM11);
11759 MI->addRegisterDefined(X86::XMM12);
11760 MI->addRegisterDefined(X86::XMM13);
11761 MI->addRegisterDefined(X86::XMM14);
11762 MI->addRegisterDefined(X86::XMM15);
11765 case X86::WIN_ALLOCA:
11766 return EmitLoweredWinAlloca(MI, BB);
11767 case X86::TLSCall_32:
11768 case X86::TLSCall_64:
11769 return EmitLoweredTLSCall(MI, BB);
11770 case X86::CMOV_GR8:
11771 case X86::CMOV_FR32:
11772 case X86::CMOV_FR64:
11773 case X86::CMOV_V4F32:
11774 case X86::CMOV_V2F64:
11775 case X86::CMOV_V2I64:
11776 case X86::CMOV_V8F32:
11777 case X86::CMOV_V4F64:
11778 case X86::CMOV_V4I64:
11779 case X86::CMOV_GR16:
11780 case X86::CMOV_GR32:
11781 case X86::CMOV_RFP32:
11782 case X86::CMOV_RFP64:
11783 case X86::CMOV_RFP80:
11784 return EmitLoweredSelect(MI, BB);
11786 case X86::FP32_TO_INT16_IN_MEM:
11787 case X86::FP32_TO_INT32_IN_MEM:
11788 case X86::FP32_TO_INT64_IN_MEM:
11789 case X86::FP64_TO_INT16_IN_MEM:
11790 case X86::FP64_TO_INT32_IN_MEM:
11791 case X86::FP64_TO_INT64_IN_MEM:
11792 case X86::FP80_TO_INT16_IN_MEM:
11793 case X86::FP80_TO_INT32_IN_MEM:
11794 case X86::FP80_TO_INT64_IN_MEM: {
11795 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11796 DebugLoc DL = MI->getDebugLoc();
11798 // Change the floating point control register to use "round towards zero"
11799 // mode when truncating to an integer value.
11800 MachineFunction *F = BB->getParent();
11801 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11802 addFrameReference(BuildMI(*BB, MI, DL,
11803 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11805 // Load the old value of the high byte of the control word...
11807 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11808 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11811 // Set the high part to be round to zero...
11812 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11815 // Reload the modified control word now...
11816 addFrameReference(BuildMI(*BB, MI, DL,
11817 TII->get(X86::FLDCW16m)), CWFrameIdx);
11819 // Restore the memory image of control word to original value
11820 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11823 // Get the X86 opcode to use.
11825 switch (MI->getOpcode()) {
11826 default: llvm_unreachable("illegal opcode!");
11827 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11828 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11829 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11830 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11831 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11832 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11833 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
11834 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
11835 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
11839 MachineOperand &Op = MI->getOperand(0);
11841 AM.BaseType = X86AddressMode::RegBase;
11842 AM.Base.Reg = Op.getReg();
11844 AM.BaseType = X86AddressMode::FrameIndexBase;
11845 AM.Base.FrameIndex = Op.getIndex();
11847 Op = MI->getOperand(1);
11849 AM.Scale = Op.getImm();
11850 Op = MI->getOperand(2);
11852 AM.IndexReg = Op.getImm();
11853 Op = MI->getOperand(3);
11854 if (Op.isGlobal()) {
11855 AM.GV = Op.getGlobal();
11857 AM.Disp = Op.getImm();
11859 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
11860 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
11862 // Reload the original control word now.
11863 addFrameReference(BuildMI(*BB, MI, DL,
11864 TII->get(X86::FLDCW16m)), CWFrameIdx);
11866 MI->eraseFromParent(); // The pseudo instruction is gone now.
11869 // String/text processing lowering.
11870 case X86::PCMPISTRM128REG:
11871 case X86::VPCMPISTRM128REG:
11872 return EmitPCMP(MI, BB, 3, false /* in-mem */);
11873 case X86::PCMPISTRM128MEM:
11874 case X86::VPCMPISTRM128MEM:
11875 return EmitPCMP(MI, BB, 3, true /* in-mem */);
11876 case X86::PCMPESTRM128REG:
11877 case X86::VPCMPESTRM128REG:
11878 return EmitPCMP(MI, BB, 5, false /* in mem */);
11879 case X86::PCMPESTRM128MEM:
11880 case X86::VPCMPESTRM128MEM:
11881 return EmitPCMP(MI, BB, 5, true /* in mem */);
11883 // Thread synchronization.
11885 return EmitMonitor(MI, BB);
11887 return EmitMwait(MI, BB);
11889 // Atomic Lowering.
11890 case X86::ATOMAND32:
11891 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11892 X86::AND32ri, X86::MOV32rm,
11894 X86::NOT32r, X86::EAX,
11895 X86::GR32RegisterClass);
11896 case X86::ATOMOR32:
11897 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
11898 X86::OR32ri, X86::MOV32rm,
11900 X86::NOT32r, X86::EAX,
11901 X86::GR32RegisterClass);
11902 case X86::ATOMXOR32:
11903 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
11904 X86::XOR32ri, X86::MOV32rm,
11906 X86::NOT32r, X86::EAX,
11907 X86::GR32RegisterClass);
11908 case X86::ATOMNAND32:
11909 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11910 X86::AND32ri, X86::MOV32rm,
11912 X86::NOT32r, X86::EAX,
11913 X86::GR32RegisterClass, true);
11914 case X86::ATOMMIN32:
11915 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
11916 case X86::ATOMMAX32:
11917 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
11918 case X86::ATOMUMIN32:
11919 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
11920 case X86::ATOMUMAX32:
11921 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
11923 case X86::ATOMAND16:
11924 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11925 X86::AND16ri, X86::MOV16rm,
11927 X86::NOT16r, X86::AX,
11928 X86::GR16RegisterClass);
11929 case X86::ATOMOR16:
11930 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
11931 X86::OR16ri, X86::MOV16rm,
11933 X86::NOT16r, X86::AX,
11934 X86::GR16RegisterClass);
11935 case X86::ATOMXOR16:
11936 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
11937 X86::XOR16ri, X86::MOV16rm,
11939 X86::NOT16r, X86::AX,
11940 X86::GR16RegisterClass);
11941 case X86::ATOMNAND16:
11942 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11943 X86::AND16ri, X86::MOV16rm,
11945 X86::NOT16r, X86::AX,
11946 X86::GR16RegisterClass, true);
11947 case X86::ATOMMIN16:
11948 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
11949 case X86::ATOMMAX16:
11950 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
11951 case X86::ATOMUMIN16:
11952 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
11953 case X86::ATOMUMAX16:
11954 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
11956 case X86::ATOMAND8:
11957 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11958 X86::AND8ri, X86::MOV8rm,
11960 X86::NOT8r, X86::AL,
11961 X86::GR8RegisterClass);
11963 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
11964 X86::OR8ri, X86::MOV8rm,
11966 X86::NOT8r, X86::AL,
11967 X86::GR8RegisterClass);
11968 case X86::ATOMXOR8:
11969 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
11970 X86::XOR8ri, X86::MOV8rm,
11972 X86::NOT8r, X86::AL,
11973 X86::GR8RegisterClass);
11974 case X86::ATOMNAND8:
11975 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11976 X86::AND8ri, X86::MOV8rm,
11978 X86::NOT8r, X86::AL,
11979 X86::GR8RegisterClass, true);
11980 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
11981 // This group is for 64-bit host.
11982 case X86::ATOMAND64:
11983 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11984 X86::AND64ri32, X86::MOV64rm,
11986 X86::NOT64r, X86::RAX,
11987 X86::GR64RegisterClass);
11988 case X86::ATOMOR64:
11989 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
11990 X86::OR64ri32, X86::MOV64rm,
11992 X86::NOT64r, X86::RAX,
11993 X86::GR64RegisterClass);
11994 case X86::ATOMXOR64:
11995 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
11996 X86::XOR64ri32, X86::MOV64rm,
11998 X86::NOT64r, X86::RAX,
11999 X86::GR64RegisterClass);
12000 case X86::ATOMNAND64:
12001 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12002 X86::AND64ri32, X86::MOV64rm,
12004 X86::NOT64r, X86::RAX,
12005 X86::GR64RegisterClass, true);
12006 case X86::ATOMMIN64:
12007 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12008 case X86::ATOMMAX64:
12009 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12010 case X86::ATOMUMIN64:
12011 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12012 case X86::ATOMUMAX64:
12013 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12015 // This group does 64-bit operations on a 32-bit host.
12016 case X86::ATOMAND6432:
12017 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12018 X86::AND32rr, X86::AND32rr,
12019 X86::AND32ri, X86::AND32ri,
12021 case X86::ATOMOR6432:
12022 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12023 X86::OR32rr, X86::OR32rr,
12024 X86::OR32ri, X86::OR32ri,
12026 case X86::ATOMXOR6432:
12027 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12028 X86::XOR32rr, X86::XOR32rr,
12029 X86::XOR32ri, X86::XOR32ri,
12031 case X86::ATOMNAND6432:
12032 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12033 X86::AND32rr, X86::AND32rr,
12034 X86::AND32ri, X86::AND32ri,
12036 case X86::ATOMADD6432:
12037 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12038 X86::ADD32rr, X86::ADC32rr,
12039 X86::ADD32ri, X86::ADC32ri,
12041 case X86::ATOMSUB6432:
12042 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12043 X86::SUB32rr, X86::SBB32rr,
12044 X86::SUB32ri, X86::SBB32ri,
12046 case X86::ATOMSWAP6432:
12047 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12048 X86::MOV32rr, X86::MOV32rr,
12049 X86::MOV32ri, X86::MOV32ri,
12051 case X86::VASTART_SAVE_XMM_REGS:
12052 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12054 case X86::VAARG_64:
12055 return EmitVAARG64WithCustomInserter(MI, BB);
12059 //===----------------------------------------------------------------------===//
12060 // X86 Optimization Hooks
12061 //===----------------------------------------------------------------------===//
12063 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12067 const SelectionDAG &DAG,
12068 unsigned Depth) const {
12069 unsigned Opc = Op.getOpcode();
12070 assert((Opc >= ISD::BUILTIN_OP_END ||
12071 Opc == ISD::INTRINSIC_WO_CHAIN ||
12072 Opc == ISD::INTRINSIC_W_CHAIN ||
12073 Opc == ISD::INTRINSIC_VOID) &&
12074 "Should use MaskedValueIsZero if you don't know whether Op"
12075 " is a target node!");
12077 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12091 // These nodes' second result is a boolean.
12092 if (Op.getResNo() == 0)
12095 case X86ISD::SETCC:
12096 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12097 Mask.getBitWidth() - 1);
12102 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12103 unsigned Depth) const {
12104 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12105 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12106 return Op.getValueType().getScalarType().getSizeInBits();
12112 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12113 /// node is a GlobalAddress + offset.
12114 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12115 const GlobalValue* &GA,
12116 int64_t &Offset) const {
12117 if (N->getOpcode() == X86ISD::Wrapper) {
12118 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12119 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12120 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12124 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12127 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12128 /// same as extracting the high 128-bit part of 256-bit vector and then
12129 /// inserting the result into the low part of a new 256-bit vector
12130 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12131 EVT VT = SVOp->getValueType(0);
12132 int NumElems = VT.getVectorNumElements();
12134 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12135 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12136 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12137 SVOp->getMaskElt(j) >= 0)
12143 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12144 /// same as extracting the low 128-bit part of 256-bit vector and then
12145 /// inserting the result into the high part of a new 256-bit vector
12146 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12147 EVT VT = SVOp->getValueType(0);
12148 int NumElems = VT.getVectorNumElements();
12150 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12151 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12152 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12153 SVOp->getMaskElt(j) >= 0)
12159 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12160 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12161 TargetLowering::DAGCombinerInfo &DCI) {
12162 DebugLoc dl = N->getDebugLoc();
12163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12164 SDValue V1 = SVOp->getOperand(0);
12165 SDValue V2 = SVOp->getOperand(1);
12166 EVT VT = SVOp->getValueType(0);
12167 int NumElems = VT.getVectorNumElements();
12169 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12170 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12174 // V UNDEF BUILD_VECTOR UNDEF
12176 // CONCAT_VECTOR CONCAT_VECTOR
12179 // RESULT: V + zero extended
12181 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12182 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12183 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12186 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12189 // To match the shuffle mask, the first half of the mask should
12190 // be exactly the first vector, and all the rest a splat with the
12191 // first element of the second one.
12192 for (int i = 0; i < NumElems/2; ++i)
12193 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12194 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12197 // Emit a zeroed vector and insert the desired subvector on its
12199 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
12200 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12201 DAG.getConstant(0, MVT::i32), DAG, dl);
12202 return DCI.CombineTo(N, InsV);
12205 //===--------------------------------------------------------------------===//
12206 // Combine some shuffles into subvector extracts and inserts:
12209 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12210 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12211 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12213 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12214 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12215 return DCI.CombineTo(N, InsV);
12218 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12219 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12220 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12221 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12222 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12223 return DCI.CombineTo(N, InsV);
12229 /// PerformShuffleCombine - Performs several different shuffle combines.
12230 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12231 TargetLowering::DAGCombinerInfo &DCI,
12232 const X86Subtarget *Subtarget) {
12233 DebugLoc dl = N->getDebugLoc();
12234 EVT VT = N->getValueType(0);
12236 // Don't create instructions with illegal types after legalize types has run.
12237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12238 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12241 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12242 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12243 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12244 return PerformShuffleCombine256(N, DAG, DCI);
12246 // Only handle 128 wide vector from here on.
12247 if (VT.getSizeInBits() != 128)
12250 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12251 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12252 // consecutive, non-overlapping, and in the right order.
12253 SmallVector<SDValue, 16> Elts;
12254 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12255 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12257 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12260 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12261 /// generation and convert it from being a bunch of shuffles and extracts
12262 /// to a simple store and scalar loads to extract the elements.
12263 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12264 const TargetLowering &TLI) {
12265 SDValue InputVector = N->getOperand(0);
12267 // Only operate on vectors of 4 elements, where the alternative shuffling
12268 // gets to be more expensive.
12269 if (InputVector.getValueType() != MVT::v4i32)
12272 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12273 // single use which is a sign-extend or zero-extend, and all elements are
12275 SmallVector<SDNode *, 4> Uses;
12276 unsigned ExtractedElements = 0;
12277 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12278 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12279 if (UI.getUse().getResNo() != InputVector.getResNo())
12282 SDNode *Extract = *UI;
12283 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12286 if (Extract->getValueType(0) != MVT::i32)
12288 if (!Extract->hasOneUse())
12290 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12291 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12293 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12296 // Record which element was extracted.
12297 ExtractedElements |=
12298 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12300 Uses.push_back(Extract);
12303 // If not all the elements were used, this may not be worthwhile.
12304 if (ExtractedElements != 15)
12307 // Ok, we've now decided to do the transformation.
12308 DebugLoc dl = InputVector.getDebugLoc();
12310 // Store the value to a temporary stack slot.
12311 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12312 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12313 MachinePointerInfo(), false, false, 0);
12315 // Replace each use (extract) with a load of the appropriate element.
12316 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12317 UE = Uses.end(); UI != UE; ++UI) {
12318 SDNode *Extract = *UI;
12320 // cOMpute the element's address.
12321 SDValue Idx = Extract->getOperand(1);
12323 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12324 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12325 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12327 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12328 StackPtr, OffsetVal);
12330 // Load the scalar.
12331 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12332 ScalarAddr, MachinePointerInfo(),
12335 // Replace the exact with the load.
12336 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12339 // The replacement was made in place; don't return anything.
12343 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12344 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12345 const X86Subtarget *Subtarget) {
12346 DebugLoc DL = N->getDebugLoc();
12347 SDValue Cond = N->getOperand(0);
12348 // Get the LHS/RHS of the select.
12349 SDValue LHS = N->getOperand(1);
12350 SDValue RHS = N->getOperand(2);
12352 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12353 // instructions match the semantics of the common C idiom x<y?x:y but not
12354 // x<=y?x:y, because of how they handle negative zero (which can be
12355 // ignored in unsafe-math mode).
12356 if (Subtarget->hasSSE2() &&
12357 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12358 Cond.getOpcode() == ISD::SETCC) {
12359 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12361 unsigned Opcode = 0;
12362 // Check for x CC y ? x : y.
12363 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12364 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12368 // Converting this to a min would handle NaNs incorrectly, and swapping
12369 // the operands would cause it to handle comparisons between positive
12370 // and negative zero incorrectly.
12371 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12372 if (!UnsafeFPMath &&
12373 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12375 std::swap(LHS, RHS);
12377 Opcode = X86ISD::FMIN;
12380 // Converting this to a min would handle comparisons between positive
12381 // and negative zero incorrectly.
12382 if (!UnsafeFPMath &&
12383 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12385 Opcode = X86ISD::FMIN;
12388 // Converting this to a min would handle both negative zeros and NaNs
12389 // incorrectly, but we can swap the operands to fix both.
12390 std::swap(LHS, RHS);
12394 Opcode = X86ISD::FMIN;
12398 // Converting this to a max would handle comparisons between positive
12399 // and negative zero incorrectly.
12400 if (!UnsafeFPMath &&
12401 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12403 Opcode = X86ISD::FMAX;
12406 // Converting this to a max would handle NaNs incorrectly, and swapping
12407 // the operands would cause it to handle comparisons between positive
12408 // and negative zero incorrectly.
12409 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12410 if (!UnsafeFPMath &&
12411 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12413 std::swap(LHS, RHS);
12415 Opcode = X86ISD::FMAX;
12418 // Converting this to a max would handle both negative zeros and NaNs
12419 // incorrectly, but we can swap the operands to fix both.
12420 std::swap(LHS, RHS);
12424 Opcode = X86ISD::FMAX;
12427 // Check for x CC y ? y : x -- a min/max with reversed arms.
12428 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12429 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12433 // Converting this to a min would handle comparisons between positive
12434 // and negative zero incorrectly, and swapping the operands would
12435 // cause it to handle NaNs incorrectly.
12436 if (!UnsafeFPMath &&
12437 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12438 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12440 std::swap(LHS, RHS);
12442 Opcode = X86ISD::FMIN;
12445 // Converting this to a min would handle NaNs incorrectly.
12446 if (!UnsafeFPMath &&
12447 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12449 Opcode = X86ISD::FMIN;
12452 // Converting this to a min would handle both negative zeros and NaNs
12453 // incorrectly, but we can swap the operands to fix both.
12454 std::swap(LHS, RHS);
12458 Opcode = X86ISD::FMIN;
12462 // Converting this to a max would handle NaNs incorrectly.
12463 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12465 Opcode = X86ISD::FMAX;
12468 // Converting this to a max would handle comparisons between positive
12469 // and negative zero incorrectly, and swapping the operands would
12470 // cause it to handle NaNs incorrectly.
12471 if (!UnsafeFPMath &&
12472 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12473 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12475 std::swap(LHS, RHS);
12477 Opcode = X86ISD::FMAX;
12480 // Converting this to a max would handle both negative zeros and NaNs
12481 // incorrectly, but we can swap the operands to fix both.
12482 std::swap(LHS, RHS);
12486 Opcode = X86ISD::FMAX;
12492 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12495 // If this is a select between two integer constants, try to do some
12497 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12498 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12499 // Don't do this for crazy integer types.
12500 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12501 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12502 // so that TrueC (the true value) is larger than FalseC.
12503 bool NeedsCondInvert = false;
12505 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12506 // Efficiently invertible.
12507 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12508 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12509 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12510 NeedsCondInvert = true;
12511 std::swap(TrueC, FalseC);
12514 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12515 if (FalseC->getAPIntValue() == 0 &&
12516 TrueC->getAPIntValue().isPowerOf2()) {
12517 if (NeedsCondInvert) // Invert the condition if needed.
12518 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12519 DAG.getConstant(1, Cond.getValueType()));
12521 // Zero extend the condition if needed.
12522 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12524 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12525 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12526 DAG.getConstant(ShAmt, MVT::i8));
12529 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12530 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12531 if (NeedsCondInvert) // Invert the condition if needed.
12532 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12533 DAG.getConstant(1, Cond.getValueType()));
12535 // Zero extend the condition if needed.
12536 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12537 FalseC->getValueType(0), Cond);
12538 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12539 SDValue(FalseC, 0));
12542 // Optimize cases that will turn into an LEA instruction. This requires
12543 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12544 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12545 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12546 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12548 bool isFastMultiplier = false;
12550 switch ((unsigned char)Diff) {
12552 case 1: // result = add base, cond
12553 case 2: // result = lea base( , cond*2)
12554 case 3: // result = lea base(cond, cond*2)
12555 case 4: // result = lea base( , cond*4)
12556 case 5: // result = lea base(cond, cond*4)
12557 case 8: // result = lea base( , cond*8)
12558 case 9: // result = lea base(cond, cond*8)
12559 isFastMultiplier = true;
12564 if (isFastMultiplier) {
12565 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12566 if (NeedsCondInvert) // Invert the condition if needed.
12567 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12568 DAG.getConstant(1, Cond.getValueType()));
12570 // Zero extend the condition if needed.
12571 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12573 // Scale the condition by the difference.
12575 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12576 DAG.getConstant(Diff, Cond.getValueType()));
12578 // Add the base if non-zero.
12579 if (FalseC->getAPIntValue() != 0)
12580 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12581 SDValue(FalseC, 0));
12591 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12592 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12593 TargetLowering::DAGCombinerInfo &DCI) {
12594 DebugLoc DL = N->getDebugLoc();
12596 // If the flag operand isn't dead, don't touch this CMOV.
12597 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12600 SDValue FalseOp = N->getOperand(0);
12601 SDValue TrueOp = N->getOperand(1);
12602 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12603 SDValue Cond = N->getOperand(3);
12604 if (CC == X86::COND_E || CC == X86::COND_NE) {
12605 switch (Cond.getOpcode()) {
12609 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12610 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12611 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12615 // If this is a select between two integer constants, try to do some
12616 // optimizations. Note that the operands are ordered the opposite of SELECT
12618 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12619 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12620 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12621 // larger than FalseC (the false value).
12622 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12623 CC = X86::GetOppositeBranchCondition(CC);
12624 std::swap(TrueC, FalseC);
12627 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12628 // This is efficient for any integer data type (including i8/i16) and
12630 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12631 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12632 DAG.getConstant(CC, MVT::i8), Cond);
12634 // Zero extend the condition if needed.
12635 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12637 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12638 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12639 DAG.getConstant(ShAmt, MVT::i8));
12640 if (N->getNumValues() == 2) // Dead flag value?
12641 return DCI.CombineTo(N, Cond, SDValue());
12645 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12646 // for any integer data type, including i8/i16.
12647 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12648 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12649 DAG.getConstant(CC, MVT::i8), Cond);
12651 // Zero extend the condition if needed.
12652 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12653 FalseC->getValueType(0), Cond);
12654 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12655 SDValue(FalseC, 0));
12657 if (N->getNumValues() == 2) // Dead flag value?
12658 return DCI.CombineTo(N, Cond, SDValue());
12662 // Optimize cases that will turn into an LEA instruction. This requires
12663 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12664 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12665 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12666 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12668 bool isFastMultiplier = false;
12670 switch ((unsigned char)Diff) {
12672 case 1: // result = add base, cond
12673 case 2: // result = lea base( , cond*2)
12674 case 3: // result = lea base(cond, cond*2)
12675 case 4: // result = lea base( , cond*4)
12676 case 5: // result = lea base(cond, cond*4)
12677 case 8: // result = lea base( , cond*8)
12678 case 9: // result = lea base(cond, cond*8)
12679 isFastMultiplier = true;
12684 if (isFastMultiplier) {
12685 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12686 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12687 DAG.getConstant(CC, MVT::i8), Cond);
12688 // Zero extend the condition if needed.
12689 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12691 // Scale the condition by the difference.
12693 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12694 DAG.getConstant(Diff, Cond.getValueType()));
12696 // Add the base if non-zero.
12697 if (FalseC->getAPIntValue() != 0)
12698 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12699 SDValue(FalseC, 0));
12700 if (N->getNumValues() == 2) // Dead flag value?
12701 return DCI.CombineTo(N, Cond, SDValue());
12711 /// PerformMulCombine - Optimize a single multiply with constant into two
12712 /// in order to implement it with two cheaper instructions, e.g.
12713 /// LEA + SHL, LEA + LEA.
12714 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12715 TargetLowering::DAGCombinerInfo &DCI) {
12716 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12719 EVT VT = N->getValueType(0);
12720 if (VT != MVT::i64)
12723 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12726 uint64_t MulAmt = C->getZExtValue();
12727 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12730 uint64_t MulAmt1 = 0;
12731 uint64_t MulAmt2 = 0;
12732 if ((MulAmt % 9) == 0) {
12734 MulAmt2 = MulAmt / 9;
12735 } else if ((MulAmt % 5) == 0) {
12737 MulAmt2 = MulAmt / 5;
12738 } else if ((MulAmt % 3) == 0) {
12740 MulAmt2 = MulAmt / 3;
12743 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12744 DebugLoc DL = N->getDebugLoc();
12746 if (isPowerOf2_64(MulAmt2) &&
12747 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12748 // If second multiplifer is pow2, issue it first. We want the multiply by
12749 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12751 std::swap(MulAmt1, MulAmt2);
12754 if (isPowerOf2_64(MulAmt1))
12755 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12756 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12758 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12759 DAG.getConstant(MulAmt1, VT));
12761 if (isPowerOf2_64(MulAmt2))
12762 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12763 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12765 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12766 DAG.getConstant(MulAmt2, VT));
12768 // Do not add new nodes to DAG combiner worklist.
12769 DCI.CombineTo(N, NewMul, false);
12774 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12775 SDValue N0 = N->getOperand(0);
12776 SDValue N1 = N->getOperand(1);
12777 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12778 EVT VT = N0.getValueType();
12780 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12781 // since the result of setcc_c is all zero's or all ones.
12782 if (N1C && N0.getOpcode() == ISD::AND &&
12783 N0.getOperand(1).getOpcode() == ISD::Constant) {
12784 SDValue N00 = N0.getOperand(0);
12785 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12786 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12787 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12788 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12789 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12790 APInt ShAmt = N1C->getAPIntValue();
12791 Mask = Mask.shl(ShAmt);
12793 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12794 N00, DAG.getConstant(Mask, VT));
12801 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12803 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12804 const X86Subtarget *Subtarget) {
12805 EVT VT = N->getValueType(0);
12806 if (!VT.isVector() && VT.isInteger() &&
12807 N->getOpcode() == ISD::SHL)
12808 return PerformSHLCombine(N, DAG);
12810 // On X86 with SSE2 support, we can transform this to a vector shift if
12811 // all elements are shifted by the same amount. We can't do this in legalize
12812 // because the a constant vector is typically transformed to a constant pool
12813 // so we have no knowledge of the shift amount.
12814 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
12817 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
12820 SDValue ShAmtOp = N->getOperand(1);
12821 EVT EltVT = VT.getVectorElementType();
12822 DebugLoc DL = N->getDebugLoc();
12823 SDValue BaseShAmt = SDValue();
12824 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
12825 unsigned NumElts = VT.getVectorNumElements();
12827 for (; i != NumElts; ++i) {
12828 SDValue Arg = ShAmtOp.getOperand(i);
12829 if (Arg.getOpcode() == ISD::UNDEF) continue;
12833 for (; i != NumElts; ++i) {
12834 SDValue Arg = ShAmtOp.getOperand(i);
12835 if (Arg.getOpcode() == ISD::UNDEF) continue;
12836 if (Arg != BaseShAmt) {
12840 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
12841 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
12842 SDValue InVec = ShAmtOp.getOperand(0);
12843 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12844 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12846 for (; i != NumElts; ++i) {
12847 SDValue Arg = InVec.getOperand(i);
12848 if (Arg.getOpcode() == ISD::UNDEF) continue;
12852 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12853 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12854 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
12855 if (C->getZExtValue() == SplatIdx)
12856 BaseShAmt = InVec.getOperand(1);
12859 if (BaseShAmt.getNode() == 0)
12860 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
12861 DAG.getIntPtrConstant(0));
12865 // The shift amount is an i32.
12866 if (EltVT.bitsGT(MVT::i32))
12867 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
12868 else if (EltVT.bitsLT(MVT::i32))
12869 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
12871 // The shift amount is identical so we can do a vector shift.
12872 SDValue ValOp = N->getOperand(0);
12873 switch (N->getOpcode()) {
12875 llvm_unreachable("Unknown shift opcode!");
12878 if (VT == MVT::v2i64)
12879 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12880 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
12882 if (VT == MVT::v4i32)
12883 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12884 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
12886 if (VT == MVT::v8i16)
12887 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12888 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
12892 if (VT == MVT::v4i32)
12893 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12894 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
12896 if (VT == MVT::v8i16)
12897 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12898 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
12902 if (VT == MVT::v2i64)
12903 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12904 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
12906 if (VT == MVT::v4i32)
12907 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12908 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
12910 if (VT == MVT::v8i16)
12911 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12912 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
12920 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12921 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
12922 // and friends. Likewise for OR -> CMPNEQSS.
12923 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
12924 TargetLowering::DAGCombinerInfo &DCI,
12925 const X86Subtarget *Subtarget) {
12928 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
12929 // we're requiring SSE2 for both.
12930 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
12931 SDValue N0 = N->getOperand(0);
12932 SDValue N1 = N->getOperand(1);
12933 SDValue CMP0 = N0->getOperand(1);
12934 SDValue CMP1 = N1->getOperand(1);
12935 DebugLoc DL = N->getDebugLoc();
12937 // The SETCCs should both refer to the same CMP.
12938 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
12941 SDValue CMP00 = CMP0->getOperand(0);
12942 SDValue CMP01 = CMP0->getOperand(1);
12943 EVT VT = CMP00.getValueType();
12945 if (VT == MVT::f32 || VT == MVT::f64) {
12946 bool ExpectingFlags = false;
12947 // Check for any users that want flags:
12948 for (SDNode::use_iterator UI = N->use_begin(),
12950 !ExpectingFlags && UI != UE; ++UI)
12951 switch (UI->getOpcode()) {
12956 ExpectingFlags = true;
12958 case ISD::CopyToReg:
12959 case ISD::SIGN_EXTEND:
12960 case ISD::ZERO_EXTEND:
12961 case ISD::ANY_EXTEND:
12965 if (!ExpectingFlags) {
12966 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
12967 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
12969 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
12970 X86::CondCode tmp = cc0;
12975 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
12976 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
12977 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
12978 X86ISD::NodeType NTOperator = is64BitFP ?
12979 X86ISD::FSETCCsd : X86ISD::FSETCCss;
12980 // FIXME: need symbolic constants for these magic numbers.
12981 // See X86ATTInstPrinter.cpp:printSSECC().
12982 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
12983 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
12984 DAG.getConstant(x86cc, MVT::i8));
12985 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
12987 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
12988 DAG.getConstant(1, MVT::i32));
12989 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
12990 return OneBitOfTruth;
12998 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
12999 /// so it can be folded inside ANDNP.
13000 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13001 EVT VT = N->getValueType(0);
13003 // Match direct AllOnes for 128 and 256-bit vectors
13004 if (ISD::isBuildVectorAllOnes(N))
13007 // Look through a bit convert.
13008 if (N->getOpcode() == ISD::BITCAST)
13009 N = N->getOperand(0).getNode();
13011 // Sometimes the operand may come from a insert_subvector building a 256-bit
13013 if (VT.getSizeInBits() == 256 &&
13014 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13015 SDValue V1 = N->getOperand(0);
13016 SDValue V2 = N->getOperand(1);
13018 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13019 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13020 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13021 ISD::isBuildVectorAllOnes(V2.getNode()))
13028 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13029 TargetLowering::DAGCombinerInfo &DCI,
13030 const X86Subtarget *Subtarget) {
13031 if (DCI.isBeforeLegalizeOps())
13034 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13038 // Want to form ANDNP nodes:
13039 // 1) In the hopes of then easily combining them with OR and AND nodes
13040 // to form PBLEND/PSIGN.
13041 // 2) To match ANDN packed intrinsics
13042 EVT VT = N->getValueType(0);
13043 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13046 SDValue N0 = N->getOperand(0);
13047 SDValue N1 = N->getOperand(1);
13048 DebugLoc DL = N->getDebugLoc();
13050 // Check LHS for vnot
13051 if (N0.getOpcode() == ISD::XOR &&
13052 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13053 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13054 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13056 // Check RHS for vnot
13057 if (N1.getOpcode() == ISD::XOR &&
13058 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13059 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13060 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13065 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13066 TargetLowering::DAGCombinerInfo &DCI,
13067 const X86Subtarget *Subtarget) {
13068 if (DCI.isBeforeLegalizeOps())
13071 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13075 EVT VT = N->getValueType(0);
13076 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13079 SDValue N0 = N->getOperand(0);
13080 SDValue N1 = N->getOperand(1);
13082 // look for psign/blend
13083 if (Subtarget->hasSSSE3()) {
13084 if (VT == MVT::v2i64) {
13085 // Canonicalize pandn to RHS
13086 if (N0.getOpcode() == X86ISD::ANDNP)
13088 // or (and (m, x), (pandn m, y))
13089 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13090 SDValue Mask = N1.getOperand(0);
13091 SDValue X = N1.getOperand(1);
13093 if (N0.getOperand(0) == Mask)
13094 Y = N0.getOperand(1);
13095 if (N0.getOperand(1) == Mask)
13096 Y = N0.getOperand(0);
13098 // Check to see if the mask appeared in both the AND and ANDNP and
13102 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13103 if (Mask.getOpcode() != ISD::BITCAST ||
13104 X.getOpcode() != ISD::BITCAST ||
13105 Y.getOpcode() != ISD::BITCAST)
13108 // Look through mask bitcast.
13109 Mask = Mask.getOperand(0);
13110 EVT MaskVT = Mask.getValueType();
13112 // Validate that the Mask operand is a vector sra node. The sra node
13113 // will be an intrinsic.
13114 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13117 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13118 // there is no psrai.b
13119 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13120 case Intrinsic::x86_sse2_psrai_w:
13121 case Intrinsic::x86_sse2_psrai_d:
13123 default: return SDValue();
13126 // Check that the SRA is all signbits.
13127 SDValue SraC = Mask.getOperand(2);
13128 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13129 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13130 if ((SraAmt + 1) != EltBits)
13133 DebugLoc DL = N->getDebugLoc();
13135 // Now we know we at least have a plendvb with the mask val. See if
13136 // we can form a psignb/w/d.
13137 // psign = x.type == y.type == mask.type && y = sub(0, x);
13138 X = X.getOperand(0);
13139 Y = Y.getOperand(0);
13140 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13141 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13142 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
13145 case 8: Opc = X86ISD::PSIGNB; break;
13146 case 16: Opc = X86ISD::PSIGNW; break;
13147 case 32: Opc = X86ISD::PSIGND; break;
13151 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
13152 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
13155 // PBLENDVB only available on SSE 4.1
13156 if (!Subtarget->hasSSE41())
13159 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
13160 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
13161 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13162 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
13163 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
13168 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13169 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13171 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13173 if (!N0.hasOneUse() || !N1.hasOneUse())
13176 SDValue ShAmt0 = N0.getOperand(1);
13177 if (ShAmt0.getValueType() != MVT::i8)
13179 SDValue ShAmt1 = N1.getOperand(1);
13180 if (ShAmt1.getValueType() != MVT::i8)
13182 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13183 ShAmt0 = ShAmt0.getOperand(0);
13184 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13185 ShAmt1 = ShAmt1.getOperand(0);
13187 DebugLoc DL = N->getDebugLoc();
13188 unsigned Opc = X86ISD::SHLD;
13189 SDValue Op0 = N0.getOperand(0);
13190 SDValue Op1 = N1.getOperand(0);
13191 if (ShAmt0.getOpcode() == ISD::SUB) {
13192 Opc = X86ISD::SHRD;
13193 std::swap(Op0, Op1);
13194 std::swap(ShAmt0, ShAmt1);
13197 unsigned Bits = VT.getSizeInBits();
13198 if (ShAmt1.getOpcode() == ISD::SUB) {
13199 SDValue Sum = ShAmt1.getOperand(0);
13200 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13201 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13202 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13203 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13204 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13205 return DAG.getNode(Opc, DL, VT,
13207 DAG.getNode(ISD::TRUNCATE, DL,
13210 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13211 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13213 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13214 return DAG.getNode(Opc, DL, VT,
13215 N0.getOperand(0), N1.getOperand(0),
13216 DAG.getNode(ISD::TRUNCATE, DL,
13223 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13224 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13225 const X86Subtarget *Subtarget) {
13226 StoreSDNode *St = cast<StoreSDNode>(N);
13227 EVT VT = St->getValue().getValueType();
13228 EVT StVT = St->getMemoryVT();
13229 DebugLoc dl = St->getDebugLoc();
13230 SDValue StoredVal = St->getOperand(1);
13231 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13233 // If we are saving a concatination of two XMM registers, perform two stores.
13234 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13235 // 128-bit ones. If in the future the cost becomes only one memory access the
13236 // first version would be better.
13237 if (VT.getSizeInBits() == 256 &&
13238 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13239 StoredVal.getNumOperands() == 2) {
13241 SDValue Value0 = StoredVal.getOperand(0);
13242 SDValue Value1 = StoredVal.getOperand(1);
13244 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13245 SDValue Ptr0 = St->getBasePtr();
13246 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13248 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13249 St->getPointerInfo(), St->isVolatile(),
13250 St->isNonTemporal(), St->getAlignment());
13251 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13252 St->getPointerInfo(), St->isVolatile(),
13253 St->isNonTemporal(), St->getAlignment());
13254 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13257 // Optimize trunc store (of multiple scalars) to shuffle and store.
13258 // First, pack all of the elements in one place. Next, store to memory
13259 // in fewer chunks.
13260 if (St->isTruncatingStore() && VT.isVector()) {
13261 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13262 unsigned NumElems = VT.getVectorNumElements();
13263 assert(StVT != VT && "Cannot truncate to the same type");
13264 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13265 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13267 // From, To sizes and ElemCount must be pow of two
13268 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13269 // We are going to use the original vector elt for storing.
13270 // accumulated smaller vector elements must be a multiple of bigger size.
13271 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
13272 unsigned SizeRatio = FromSz / ToSz;
13274 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13276 // Create a type on which we perform the shuffle
13277 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13278 StVT.getScalarType(), NumElems*SizeRatio);
13280 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13282 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13283 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13284 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13286 // Can't shuffle using an illegal type
13287 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13289 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13290 DAG.getUNDEF(WideVec.getValueType()),
13291 ShuffleVec.data());
13292 // At this point all of the data is stored at the bottom of the
13293 // register. We now need to save it to mem.
13295 // Find the largest store unit
13296 MVT StoreType = MVT::i8;
13297 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13298 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13299 MVT Tp = (MVT::SimpleValueType)tp;
13300 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13304 // Bitcast the original vector into a vector of store-size units
13305 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13306 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13307 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13308 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13309 SmallVector<SDValue, 8> Chains;
13310 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13311 TLI.getPointerTy());
13312 SDValue Ptr = St->getBasePtr();
13314 // Perform one or more big stores into memory.
13315 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13316 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13317 StoreType, ShuffWide,
13318 DAG.getIntPtrConstant(i));
13319 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13320 St->getPointerInfo(), St->isVolatile(),
13321 St->isNonTemporal(), St->getAlignment());
13322 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13323 Chains.push_back(Ch);
13326 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13331 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13332 // the FP state in cases where an emms may be missing.
13333 // A preferable solution to the general problem is to figure out the right
13334 // places to insert EMMS. This qualifies as a quick hack.
13336 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13337 if (VT.getSizeInBits() != 64)
13340 const Function *F = DAG.getMachineFunction().getFunction();
13341 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13342 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13343 && Subtarget->hasSSE2();
13344 if ((VT.isVector() ||
13345 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13346 isa<LoadSDNode>(St->getValue()) &&
13347 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13348 St->getChain().hasOneUse() && !St->isVolatile()) {
13349 SDNode* LdVal = St->getValue().getNode();
13350 LoadSDNode *Ld = 0;
13351 int TokenFactorIndex = -1;
13352 SmallVector<SDValue, 8> Ops;
13353 SDNode* ChainVal = St->getChain().getNode();
13354 // Must be a store of a load. We currently handle two cases: the load
13355 // is a direct child, and it's under an intervening TokenFactor. It is
13356 // possible to dig deeper under nested TokenFactors.
13357 if (ChainVal == LdVal)
13358 Ld = cast<LoadSDNode>(St->getChain());
13359 else if (St->getValue().hasOneUse() &&
13360 ChainVal->getOpcode() == ISD::TokenFactor) {
13361 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13362 if (ChainVal->getOperand(i).getNode() == LdVal) {
13363 TokenFactorIndex = i;
13364 Ld = cast<LoadSDNode>(St->getValue());
13366 Ops.push_back(ChainVal->getOperand(i));
13370 if (!Ld || !ISD::isNormalLoad(Ld))
13373 // If this is not the MMX case, i.e. we are just turning i64 load/store
13374 // into f64 load/store, avoid the transformation if there are multiple
13375 // uses of the loaded value.
13376 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13379 DebugLoc LdDL = Ld->getDebugLoc();
13380 DebugLoc StDL = N->getDebugLoc();
13381 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13382 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13384 if (Subtarget->is64Bit() || F64IsLegal) {
13385 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13386 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13387 Ld->getPointerInfo(), Ld->isVolatile(),
13388 Ld->isNonTemporal(), Ld->getAlignment());
13389 SDValue NewChain = NewLd.getValue(1);
13390 if (TokenFactorIndex != -1) {
13391 Ops.push_back(NewChain);
13392 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13395 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13396 St->getPointerInfo(),
13397 St->isVolatile(), St->isNonTemporal(),
13398 St->getAlignment());
13401 // Otherwise, lower to two pairs of 32-bit loads / stores.
13402 SDValue LoAddr = Ld->getBasePtr();
13403 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13404 DAG.getConstant(4, MVT::i32));
13406 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13407 Ld->getPointerInfo(),
13408 Ld->isVolatile(), Ld->isNonTemporal(),
13409 Ld->getAlignment());
13410 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13411 Ld->getPointerInfo().getWithOffset(4),
13412 Ld->isVolatile(), Ld->isNonTemporal(),
13413 MinAlign(Ld->getAlignment(), 4));
13415 SDValue NewChain = LoLd.getValue(1);
13416 if (TokenFactorIndex != -1) {
13417 Ops.push_back(LoLd);
13418 Ops.push_back(HiLd);
13419 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13423 LoAddr = St->getBasePtr();
13424 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13425 DAG.getConstant(4, MVT::i32));
13427 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13428 St->getPointerInfo(),
13429 St->isVolatile(), St->isNonTemporal(),
13430 St->getAlignment());
13431 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13432 St->getPointerInfo().getWithOffset(4),
13434 St->isNonTemporal(),
13435 MinAlign(St->getAlignment(), 4));
13436 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13441 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13442 /// X86ISD::FXOR nodes.
13443 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13444 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13445 // F[X]OR(0.0, x) -> x
13446 // F[X]OR(x, 0.0) -> x
13447 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13448 if (C->getValueAPF().isPosZero())
13449 return N->getOperand(1);
13450 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13451 if (C->getValueAPF().isPosZero())
13452 return N->getOperand(0);
13456 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13457 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13458 // FAND(0.0, x) -> 0.0
13459 // FAND(x, 0.0) -> 0.0
13460 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13461 if (C->getValueAPF().isPosZero())
13462 return N->getOperand(0);
13463 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13464 if (C->getValueAPF().isPosZero())
13465 return N->getOperand(1);
13469 static SDValue PerformBTCombine(SDNode *N,
13471 TargetLowering::DAGCombinerInfo &DCI) {
13472 // BT ignores high bits in the bit index operand.
13473 SDValue Op1 = N->getOperand(1);
13474 if (Op1.hasOneUse()) {
13475 unsigned BitWidth = Op1.getValueSizeInBits();
13476 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13477 APInt KnownZero, KnownOne;
13478 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13479 !DCI.isBeforeLegalizeOps());
13480 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13481 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13482 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13483 DCI.CommitTargetLoweringOpt(TLO);
13488 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13489 SDValue Op = N->getOperand(0);
13490 if (Op.getOpcode() == ISD::BITCAST)
13491 Op = Op.getOperand(0);
13492 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13493 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13494 VT.getVectorElementType().getSizeInBits() ==
13495 OpVT.getVectorElementType().getSizeInBits()) {
13496 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13501 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13502 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13503 // (and (i32 x86isd::setcc_carry), 1)
13504 // This eliminates the zext. This transformation is necessary because
13505 // ISD::SETCC is always legalized to i8.
13506 DebugLoc dl = N->getDebugLoc();
13507 SDValue N0 = N->getOperand(0);
13508 EVT VT = N->getValueType(0);
13509 if (N0.getOpcode() == ISD::AND &&
13511 N0.getOperand(0).hasOneUse()) {
13512 SDValue N00 = N0.getOperand(0);
13513 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13515 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13516 if (!C || C->getZExtValue() != 1)
13518 return DAG.getNode(ISD::AND, dl, VT,
13519 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13520 N00.getOperand(0), N00.getOperand(1)),
13521 DAG.getConstant(1, VT));
13527 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13528 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13529 unsigned X86CC = N->getConstantOperandVal(0);
13530 SDValue EFLAG = N->getOperand(1);
13531 DebugLoc DL = N->getDebugLoc();
13533 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13534 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13536 if (X86CC == X86::COND_B)
13537 return DAG.getNode(ISD::AND, DL, MVT::i8,
13538 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13539 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13540 DAG.getConstant(1, MVT::i8));
13545 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13546 const X86TargetLowering *XTLI) {
13547 SDValue Op0 = N->getOperand(0);
13548 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13549 // a 32-bit target where SSE doesn't support i64->FP operations.
13550 if (Op0.getOpcode() == ISD::LOAD) {
13551 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13552 EVT VT = Ld->getValueType(0);
13553 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13554 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13555 !XTLI->getSubtarget()->is64Bit() &&
13556 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13557 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13558 Ld->getChain(), Op0, DAG);
13559 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13566 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13567 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13568 X86TargetLowering::DAGCombinerInfo &DCI) {
13569 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13570 // the result is either zero or one (depending on the input carry bit).
13571 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13572 if (X86::isZeroNode(N->getOperand(0)) &&
13573 X86::isZeroNode(N->getOperand(1)) &&
13574 // We don't have a good way to replace an EFLAGS use, so only do this when
13576 SDValue(N, 1).use_empty()) {
13577 DebugLoc DL = N->getDebugLoc();
13578 EVT VT = N->getValueType(0);
13579 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13580 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13581 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13582 DAG.getConstant(X86::COND_B,MVT::i8),
13584 DAG.getConstant(1, VT));
13585 return DCI.CombineTo(N, Res1, CarryOut);
13591 // fold (add Y, (sete X, 0)) -> adc 0, Y
13592 // (add Y, (setne X, 0)) -> sbb -1, Y
13593 // (sub (sete X, 0), Y) -> sbb 0, Y
13594 // (sub (setne X, 0), Y) -> adc -1, Y
13595 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13596 DebugLoc DL = N->getDebugLoc();
13598 // Look through ZExts.
13599 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13600 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13603 SDValue SetCC = Ext.getOperand(0);
13604 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13607 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13608 if (CC != X86::COND_E && CC != X86::COND_NE)
13611 SDValue Cmp = SetCC.getOperand(1);
13612 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13613 !X86::isZeroNode(Cmp.getOperand(1)) ||
13614 !Cmp.getOperand(0).getValueType().isInteger())
13617 SDValue CmpOp0 = Cmp.getOperand(0);
13618 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13619 DAG.getConstant(1, CmpOp0.getValueType()));
13621 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13622 if (CC == X86::COND_NE)
13623 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13624 DL, OtherVal.getValueType(), OtherVal,
13625 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13626 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13627 DL, OtherVal.getValueType(), OtherVal,
13628 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13631 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13632 SDValue Op0 = N->getOperand(0);
13633 SDValue Op1 = N->getOperand(1);
13635 // X86 can't encode an immediate LHS of a sub. See if we can push the
13636 // negation into a preceding instruction.
13637 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13638 // If the RHS of the sub is a XOR with one use and a constant, invert the
13639 // immediate. Then add one to the LHS of the sub so we can turn
13640 // X-Y -> X+~Y+1, saving one register.
13641 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13642 isa<ConstantSDNode>(Op1.getOperand(1))) {
13643 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13644 EVT VT = Op0.getValueType();
13645 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13647 DAG.getConstant(~XorC, VT));
13648 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13649 DAG.getConstant(C->getAPIntValue()+1, VT));
13653 return OptimizeConditionalInDecrement(N, DAG);
13656 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13657 DAGCombinerInfo &DCI) const {
13658 SelectionDAG &DAG = DCI.DAG;
13659 switch (N->getOpcode()) {
13661 case ISD::EXTRACT_VECTOR_ELT:
13662 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13663 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13664 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13665 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13666 case ISD::SUB: return PerformSubCombine(N, DAG);
13667 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13668 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13671 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13672 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13673 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13674 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13675 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13677 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13678 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13679 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13680 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13681 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13682 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13683 case X86ISD::SHUFPS: // Handle all target specific shuffles
13684 case X86ISD::SHUFPD:
13685 case X86ISD::PALIGN:
13686 case X86ISD::PUNPCKHBW:
13687 case X86ISD::PUNPCKHWD:
13688 case X86ISD::PUNPCKHDQ:
13689 case X86ISD::PUNPCKHQDQ:
13690 case X86ISD::UNPCKHPS:
13691 case X86ISD::UNPCKHPD:
13692 case X86ISD::VUNPCKHPSY:
13693 case X86ISD::VUNPCKHPDY:
13694 case X86ISD::PUNPCKLBW:
13695 case X86ISD::PUNPCKLWD:
13696 case X86ISD::PUNPCKLDQ:
13697 case X86ISD::PUNPCKLQDQ:
13698 case X86ISD::UNPCKLPS:
13699 case X86ISD::UNPCKLPD:
13700 case X86ISD::VUNPCKLPSY:
13701 case X86ISD::VUNPCKLPDY:
13702 case X86ISD::MOVHLPS:
13703 case X86ISD::MOVLHPS:
13704 case X86ISD::PSHUFD:
13705 case X86ISD::PSHUFHW:
13706 case X86ISD::PSHUFLW:
13707 case X86ISD::MOVSS:
13708 case X86ISD::MOVSD:
13709 case X86ISD::VPERMILPS:
13710 case X86ISD::VPERMILPSY:
13711 case X86ISD::VPERMILPD:
13712 case X86ISD::VPERMILPDY:
13713 case X86ISD::VPERM2F128:
13714 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13720 /// isTypeDesirableForOp - Return true if the target has native support for
13721 /// the specified value type and it is 'desirable' to use the type for the
13722 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13723 /// instruction encodings are longer and some i16 instructions are slow.
13724 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13725 if (!isTypeLegal(VT))
13727 if (VT != MVT::i16)
13734 case ISD::SIGN_EXTEND:
13735 case ISD::ZERO_EXTEND:
13736 case ISD::ANY_EXTEND:
13749 /// IsDesirableToPromoteOp - This method query the target whether it is
13750 /// beneficial for dag combiner to promote the specified node. If true, it
13751 /// should return the desired promotion type by reference.
13752 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13753 EVT VT = Op.getValueType();
13754 if (VT != MVT::i16)
13757 bool Promote = false;
13758 bool Commute = false;
13759 switch (Op.getOpcode()) {
13762 LoadSDNode *LD = cast<LoadSDNode>(Op);
13763 // If the non-extending load has a single use and it's not live out, then it
13764 // might be folded.
13765 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13766 Op.hasOneUse()*/) {
13767 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13768 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13769 // The only case where we'd want to promote LOAD (rather then it being
13770 // promoted as an operand is when it's only use is liveout.
13771 if (UI->getOpcode() != ISD::CopyToReg)
13778 case ISD::SIGN_EXTEND:
13779 case ISD::ZERO_EXTEND:
13780 case ISD::ANY_EXTEND:
13785 SDValue N0 = Op.getOperand(0);
13786 // Look out for (store (shl (load), x)).
13787 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13800 SDValue N0 = Op.getOperand(0);
13801 SDValue N1 = Op.getOperand(1);
13802 if (!Commute && MayFoldLoad(N1))
13804 // Avoid disabling potential load folding opportunities.
13805 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
13807 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
13817 //===----------------------------------------------------------------------===//
13818 // X86 Inline Assembly Support
13819 //===----------------------------------------------------------------------===//
13821 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
13822 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13824 std::string AsmStr = IA->getAsmString();
13826 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
13827 SmallVector<StringRef, 4> AsmPieces;
13828 SplitString(AsmStr, AsmPieces, ";\n");
13830 switch (AsmPieces.size()) {
13831 default: return false;
13833 AsmStr = AsmPieces[0];
13835 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
13837 // FIXME: this should verify that we are targeting a 486 or better. If not,
13838 // we will turn this bswap into something that will be lowered to logical ops
13839 // instead of emitting the bswap asm. For now, we don't support 486 or lower
13840 // so don't worry about this.
13842 if (AsmPieces.size() == 2 &&
13843 (AsmPieces[0] == "bswap" ||
13844 AsmPieces[0] == "bswapq" ||
13845 AsmPieces[0] == "bswapl") &&
13846 (AsmPieces[1] == "$0" ||
13847 AsmPieces[1] == "${0:q}")) {
13848 // No need to check constraints, nothing other than the equivalent of
13849 // "=r,0" would be valid here.
13850 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13851 if (!Ty || Ty->getBitWidth() % 16 != 0)
13853 return IntrinsicLowering::LowerToByteSwap(CI);
13855 // rorw $$8, ${0:w} --> llvm.bswap.i16
13856 if (CI->getType()->isIntegerTy(16) &&
13857 AsmPieces.size() == 3 &&
13858 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
13859 AsmPieces[1] == "$$8," &&
13860 AsmPieces[2] == "${0:w}" &&
13861 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13863 const std::string &ConstraintsStr = IA->getConstraintString();
13864 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13865 std::sort(AsmPieces.begin(), AsmPieces.end());
13866 if (AsmPieces.size() == 4 &&
13867 AsmPieces[0] == "~{cc}" &&
13868 AsmPieces[1] == "~{dirflag}" &&
13869 AsmPieces[2] == "~{flags}" &&
13870 AsmPieces[3] == "~{fpsr}") {
13871 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13872 if (!Ty || Ty->getBitWidth() % 16 != 0)
13874 return IntrinsicLowering::LowerToByteSwap(CI);
13879 if (CI->getType()->isIntegerTy(32) &&
13880 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13881 SmallVector<StringRef, 4> Words;
13882 SplitString(AsmPieces[0], Words, " \t,");
13883 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13884 Words[2] == "${0:w}") {
13886 SplitString(AsmPieces[1], Words, " \t,");
13887 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
13888 Words[2] == "$0") {
13890 SplitString(AsmPieces[2], Words, " \t,");
13891 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13892 Words[2] == "${0:w}") {
13894 const std::string &ConstraintsStr = IA->getConstraintString();
13895 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13896 std::sort(AsmPieces.begin(), AsmPieces.end());
13897 if (AsmPieces.size() == 4 &&
13898 AsmPieces[0] == "~{cc}" &&
13899 AsmPieces[1] == "~{dirflag}" &&
13900 AsmPieces[2] == "~{flags}" &&
13901 AsmPieces[3] == "~{fpsr}") {
13902 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13903 if (!Ty || Ty->getBitWidth() % 16 != 0)
13905 return IntrinsicLowering::LowerToByteSwap(CI);
13912 if (CI->getType()->isIntegerTy(64)) {
13913 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
13914 if (Constraints.size() >= 2 &&
13915 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
13916 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
13917 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
13918 SmallVector<StringRef, 4> Words;
13919 SplitString(AsmPieces[0], Words, " \t");
13920 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
13922 SplitString(AsmPieces[1], Words, " \t");
13923 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
13925 SplitString(AsmPieces[2], Words, " \t,");
13926 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
13927 Words[2] == "%edx") {
13928 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13929 if (!Ty || Ty->getBitWidth() % 16 != 0)
13931 return IntrinsicLowering::LowerToByteSwap(CI);
13944 /// getConstraintType - Given a constraint letter, return the type of
13945 /// constraint it is for this target.
13946 X86TargetLowering::ConstraintType
13947 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
13948 if (Constraint.size() == 1) {
13949 switch (Constraint[0]) {
13960 return C_RegisterClass;
13984 return TargetLowering::getConstraintType(Constraint);
13987 /// Examine constraint type and operand type and determine a weight value.
13988 /// This object must already have been set up with the operand type
13989 /// and the current alternative constraint selected.
13990 TargetLowering::ConstraintWeight
13991 X86TargetLowering::getSingleConstraintMatchWeight(
13992 AsmOperandInfo &info, const char *constraint) const {
13993 ConstraintWeight weight = CW_Invalid;
13994 Value *CallOperandVal = info.CallOperandVal;
13995 // If we don't have a value, we can't do a match,
13996 // but allow it at the lowest weight.
13997 if (CallOperandVal == NULL)
13999 Type *type = CallOperandVal->getType();
14000 // Look at the constraint type.
14001 switch (*constraint) {
14003 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14014 if (CallOperandVal->getType()->isIntegerTy())
14015 weight = CW_SpecificReg;
14020 if (type->isFloatingPointTy())
14021 weight = CW_SpecificReg;
14024 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14025 weight = CW_SpecificReg;
14029 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14030 weight = CW_Register;
14033 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14034 if (C->getZExtValue() <= 31)
14035 weight = CW_Constant;
14039 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14040 if (C->getZExtValue() <= 63)
14041 weight = CW_Constant;
14045 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14046 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14047 weight = CW_Constant;
14051 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14052 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14053 weight = CW_Constant;
14057 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14058 if (C->getZExtValue() <= 3)
14059 weight = CW_Constant;
14063 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14064 if (C->getZExtValue() <= 0xff)
14065 weight = CW_Constant;
14070 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14071 weight = CW_Constant;
14075 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14076 if ((C->getSExtValue() >= -0x80000000LL) &&
14077 (C->getSExtValue() <= 0x7fffffffLL))
14078 weight = CW_Constant;
14082 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14083 if (C->getZExtValue() <= 0xffffffff)
14084 weight = CW_Constant;
14091 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14092 /// with another that has more specific requirements based on the type of the
14093 /// corresponding operand.
14094 const char *X86TargetLowering::
14095 LowerXConstraint(EVT ConstraintVT) const {
14096 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14097 // 'f' like normal targets.
14098 if (ConstraintVT.isFloatingPoint()) {
14099 if (Subtarget->hasXMMInt())
14101 if (Subtarget->hasXMM())
14105 return TargetLowering::LowerXConstraint(ConstraintVT);
14108 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14109 /// vector. If it is invalid, don't add anything to Ops.
14110 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14111 std::string &Constraint,
14112 std::vector<SDValue>&Ops,
14113 SelectionDAG &DAG) const {
14114 SDValue Result(0, 0);
14116 // Only support length 1 constraints for now.
14117 if (Constraint.length() > 1) return;
14119 char ConstraintLetter = Constraint[0];
14120 switch (ConstraintLetter) {
14123 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14124 if (C->getZExtValue() <= 31) {
14125 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14131 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14132 if (C->getZExtValue() <= 63) {
14133 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14139 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14140 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
14141 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14147 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14148 if (C->getZExtValue() <= 255) {
14149 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14155 // 32-bit signed value
14156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14157 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14158 C->getSExtValue())) {
14159 // Widen to 64 bits here to get it sign extended.
14160 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14163 // FIXME gcc accepts some relocatable values here too, but only in certain
14164 // memory models; it's complicated.
14169 // 32-bit unsigned value
14170 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14171 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14172 C->getZExtValue())) {
14173 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14177 // FIXME gcc accepts some relocatable values here too, but only in certain
14178 // memory models; it's complicated.
14182 // Literal immediates are always ok.
14183 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
14184 // Widen to 64 bits here to get it sign extended.
14185 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14189 // In any sort of PIC mode addresses need to be computed at runtime by
14190 // adding in a register or some sort of table lookup. These can't
14191 // be used as immediates.
14192 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
14195 // If we are in non-pic codegen mode, we allow the address of a global (with
14196 // an optional displacement) to be used with 'i'.
14197 GlobalAddressSDNode *GA = 0;
14198 int64_t Offset = 0;
14200 // Match either (GA), (GA+C), (GA+C1+C2), etc.
14202 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
14203 Offset += GA->getOffset();
14205 } else if (Op.getOpcode() == ISD::ADD) {
14206 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14207 Offset += C->getZExtValue();
14208 Op = Op.getOperand(0);
14211 } else if (Op.getOpcode() == ISD::SUB) {
14212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14213 Offset += -C->getZExtValue();
14214 Op = Op.getOperand(0);
14219 // Otherwise, this isn't something we can handle, reject it.
14223 const GlobalValue *GV = GA->getGlobal();
14224 // If we require an extra load to get this address, as in PIC mode, we
14225 // can't accept it.
14226 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14227 getTargetMachine())))
14230 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14231 GA->getValueType(0), Offset);
14236 if (Result.getNode()) {
14237 Ops.push_back(Result);
14240 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14243 std::pair<unsigned, const TargetRegisterClass*>
14244 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14246 // First, see if this is a constraint that directly corresponds to an LLVM
14248 if (Constraint.size() == 1) {
14249 // GCC Constraint Letters
14250 switch (Constraint[0]) {
14252 // TODO: Slight differences here in allocation order and leaving
14253 // RIP in the class. Do they matter any more here than they do
14254 // in the normal allocation?
14255 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14256 if (Subtarget->is64Bit()) {
14257 if (VT == MVT::i32 || VT == MVT::f32)
14258 return std::make_pair(0U, X86::GR32RegisterClass);
14259 else if (VT == MVT::i16)
14260 return std::make_pair(0U, X86::GR16RegisterClass);
14261 else if (VT == MVT::i8 || VT == MVT::i1)
14262 return std::make_pair(0U, X86::GR8RegisterClass);
14263 else if (VT == MVT::i64 || VT == MVT::f64)
14264 return std::make_pair(0U, X86::GR64RegisterClass);
14267 // 32-bit fallthrough
14268 case 'Q': // Q_REGS
14269 if (VT == MVT::i32 || VT == MVT::f32)
14270 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14271 else if (VT == MVT::i16)
14272 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14273 else if (VT == MVT::i8 || VT == MVT::i1)
14274 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14275 else if (VT == MVT::i64)
14276 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14278 case 'r': // GENERAL_REGS
14279 case 'l': // INDEX_REGS
14280 if (VT == MVT::i8 || VT == MVT::i1)
14281 return std::make_pair(0U, X86::GR8RegisterClass);
14282 if (VT == MVT::i16)
14283 return std::make_pair(0U, X86::GR16RegisterClass);
14284 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14285 return std::make_pair(0U, X86::GR32RegisterClass);
14286 return std::make_pair(0U, X86::GR64RegisterClass);
14287 case 'R': // LEGACY_REGS
14288 if (VT == MVT::i8 || VT == MVT::i1)
14289 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14290 if (VT == MVT::i16)
14291 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14292 if (VT == MVT::i32 || !Subtarget->is64Bit())
14293 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14294 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14295 case 'f': // FP Stack registers.
14296 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14297 // value to the correct fpstack register class.
14298 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14299 return std::make_pair(0U, X86::RFP32RegisterClass);
14300 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14301 return std::make_pair(0U, X86::RFP64RegisterClass);
14302 return std::make_pair(0U, X86::RFP80RegisterClass);
14303 case 'y': // MMX_REGS if MMX allowed.
14304 if (!Subtarget->hasMMX()) break;
14305 return std::make_pair(0U, X86::VR64RegisterClass);
14306 case 'Y': // SSE_REGS if SSE2 allowed
14307 if (!Subtarget->hasXMMInt()) break;
14309 case 'x': // SSE_REGS if SSE1 allowed
14310 if (!Subtarget->hasXMM()) break;
14312 switch (VT.getSimpleVT().SimpleTy) {
14314 // Scalar SSE types.
14317 return std::make_pair(0U, X86::FR32RegisterClass);
14320 return std::make_pair(0U, X86::FR64RegisterClass);
14328 return std::make_pair(0U, X86::VR128RegisterClass);
14334 // Use the default implementation in TargetLowering to convert the register
14335 // constraint into a member of a register class.
14336 std::pair<unsigned, const TargetRegisterClass*> Res;
14337 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14339 // Not found as a standard register?
14340 if (Res.second == 0) {
14341 // Map st(0) -> st(7) -> ST0
14342 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14343 tolower(Constraint[1]) == 's' &&
14344 tolower(Constraint[2]) == 't' &&
14345 Constraint[3] == '(' &&
14346 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14347 Constraint[5] == ')' &&
14348 Constraint[6] == '}') {
14350 Res.first = X86::ST0+Constraint[4]-'0';
14351 Res.second = X86::RFP80RegisterClass;
14355 // GCC allows "st(0)" to be called just plain "st".
14356 if (StringRef("{st}").equals_lower(Constraint)) {
14357 Res.first = X86::ST0;
14358 Res.second = X86::RFP80RegisterClass;
14363 if (StringRef("{flags}").equals_lower(Constraint)) {
14364 Res.first = X86::EFLAGS;
14365 Res.second = X86::CCRRegisterClass;
14369 // 'A' means EAX + EDX.
14370 if (Constraint == "A") {
14371 Res.first = X86::EAX;
14372 Res.second = X86::GR32_ADRegisterClass;
14378 // Otherwise, check to see if this is a register class of the wrong value
14379 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14380 // turn into {ax},{dx}.
14381 if (Res.second->hasType(VT))
14382 return Res; // Correct type already, nothing to do.
14384 // All of the single-register GCC register classes map their values onto
14385 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14386 // really want an 8-bit or 32-bit register, map to the appropriate register
14387 // class and return the appropriate register.
14388 if (Res.second == X86::GR16RegisterClass) {
14389 if (VT == MVT::i8) {
14390 unsigned DestReg = 0;
14391 switch (Res.first) {
14393 case X86::AX: DestReg = X86::AL; break;
14394 case X86::DX: DestReg = X86::DL; break;
14395 case X86::CX: DestReg = X86::CL; break;
14396 case X86::BX: DestReg = X86::BL; break;
14399 Res.first = DestReg;
14400 Res.second = X86::GR8RegisterClass;
14402 } else if (VT == MVT::i32) {
14403 unsigned DestReg = 0;
14404 switch (Res.first) {
14406 case X86::AX: DestReg = X86::EAX; break;
14407 case X86::DX: DestReg = X86::EDX; break;
14408 case X86::CX: DestReg = X86::ECX; break;
14409 case X86::BX: DestReg = X86::EBX; break;
14410 case X86::SI: DestReg = X86::ESI; break;
14411 case X86::DI: DestReg = X86::EDI; break;
14412 case X86::BP: DestReg = X86::EBP; break;
14413 case X86::SP: DestReg = X86::ESP; break;
14416 Res.first = DestReg;
14417 Res.second = X86::GR32RegisterClass;
14419 } else if (VT == MVT::i64) {
14420 unsigned DestReg = 0;
14421 switch (Res.first) {
14423 case X86::AX: DestReg = X86::RAX; break;
14424 case X86::DX: DestReg = X86::RDX; break;
14425 case X86::CX: DestReg = X86::RCX; break;
14426 case X86::BX: DestReg = X86::RBX; break;
14427 case X86::SI: DestReg = X86::RSI; break;
14428 case X86::DI: DestReg = X86::RDI; break;
14429 case X86::BP: DestReg = X86::RBP; break;
14430 case X86::SP: DestReg = X86::RSP; break;
14433 Res.first = DestReg;
14434 Res.second = X86::GR64RegisterClass;
14437 } else if (Res.second == X86::FR32RegisterClass ||
14438 Res.second == X86::FR64RegisterClass ||
14439 Res.second == X86::VR128RegisterClass) {
14440 // Handle references to XMM physical registers that got mapped into the
14441 // wrong class. This can happen with constraints like {xmm0} where the
14442 // target independent register mapper will just pick the first match it can
14443 // find, ignoring the required type.
14444 if (VT == MVT::f32)
14445 Res.second = X86::FR32RegisterClass;
14446 else if (VT == MVT::f64)
14447 Res.second = X86::FR64RegisterClass;
14448 else if (X86::VR128RegisterClass->hasType(VT))
14449 Res.second = X86::VR128RegisterClass;