1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/VectorExtras.h"
27 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/StringExtras.h"
39 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
40 : TargetLowering(TM) {
41 Subtarget = &TM.getSubtarget<X86Subtarget>();
42 X86ScalarSSE = Subtarget->hasSSE2();
43 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
45 // Set up the TargetLowering object.
47 // X86 is weird, it always uses i8 for shift amounts and setcc results.
48 setShiftAmountType(MVT::i8);
49 setSetCCResultType(MVT::i8);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
51 setSchedulingPreference(SchedulingForRegPressure);
52 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
53 setStackPointerRegisterToSaveRestore(X86StackPtr);
55 if (Subtarget->isTargetDarwin()) {
56 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
57 setUseUnderscoreSetJmp(false);
58 setUseUnderscoreLongJmp(false);
59 } else if (Subtarget->isTargetMingw()) {
60 // MS runtime is weird: it exports _setjmp, but longjmp!
61 setUseUnderscoreSetJmp(true);
62 setUseUnderscoreLongJmp(false);
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
68 // Set up the register classes.
69 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
70 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
71 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
72 if (Subtarget->is64Bit())
73 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
75 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
77 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
79 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
80 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
81 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
83 if (Subtarget->is64Bit()) {
84 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
85 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
88 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
89 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
91 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
94 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
96 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
97 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
98 // SSE has no i16 to fp conversion, only i32
100 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
102 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
103 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
106 if (!Subtarget->is64Bit()) {
107 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
108 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
109 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
112 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
114 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
115 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
118 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
120 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
124 // Handle FP_TO_UINT by promoting the destination to a larger signed
126 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
127 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
128 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
130 if (Subtarget->is64Bit()) {
131 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
132 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
134 if (X86ScalarSSE && !Subtarget->hasSSE3())
135 // Expand FP_TO_UINT into a select.
136 // FIXME: We would like to use a Custom expander here eventually to do
137 // the optimal thing for SSE vs. the default expansion in the legalizer.
138 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
140 // With SSE3 we can use fisttpll to convert to a signed i64.
141 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
144 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
146 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
147 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
150 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
151 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
152 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
153 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
154 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
155 if (Subtarget->is64Bit())
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
160 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
161 setOperationAction(ISD::FREM , MVT::f64 , Expand);
163 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
164 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
165 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
166 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
167 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
168 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
169 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
170 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
171 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
172 if (Subtarget->is64Bit()) {
173 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
175 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
178 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
179 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
181 // These should be promoted to a larger select which is supported.
182 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
183 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
184 // X86 wants to expand cmov itself.
185 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
186 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
187 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
188 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
189 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
190 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
191 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
192 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
193 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
194 if (Subtarget->is64Bit()) {
195 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
196 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
198 // X86 ret instruction may pop stack.
199 setOperationAction(ISD::RET , MVT::Other, Custom);
201 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
202 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
203 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
204 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
205 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
206 if (Subtarget->is64Bit()) {
207 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
208 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
209 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
210 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
212 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
213 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
214 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
215 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
216 // X86 wants to expand memset / memcpy itself.
217 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
218 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
220 // We don't have line number support yet.
221 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
222 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
223 // FIXME - use subtarget debug flags
224 if (!Subtarget->isTargetDarwin() &&
225 !Subtarget->isTargetELF() &&
226 !Subtarget->isTargetCygMing())
227 setOperationAction(ISD::LABEL, MVT::Other, Expand);
229 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
230 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
231 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
232 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
233 if (Subtarget->is64Bit()) {
235 setExceptionPointerRegister(X86::RAX);
236 setExceptionSelectorRegister(X86::RDX);
238 setExceptionPointerRegister(X86::EAX);
239 setExceptionSelectorRegister(X86::EDX);
242 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
243 setOperationAction(ISD::VASTART , MVT::Other, Custom);
244 setOperationAction(ISD::VAARG , MVT::Other, Expand);
245 setOperationAction(ISD::VAEND , MVT::Other, Expand);
246 if (Subtarget->is64Bit())
247 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
249 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
251 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
252 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
253 if (Subtarget->is64Bit())
254 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
255 if (Subtarget->isTargetCygMing())
256 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
258 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
261 // Set up the FP register classes.
262 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
263 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
265 // Use ANDPD to simulate FABS.
266 setOperationAction(ISD::FABS , MVT::f64, Custom);
267 setOperationAction(ISD::FABS , MVT::f32, Custom);
269 // Use XORP to simulate FNEG.
270 setOperationAction(ISD::FNEG , MVT::f64, Custom);
271 setOperationAction(ISD::FNEG , MVT::f32, Custom);
273 // Use ANDPD and ORPD to simulate FCOPYSIGN.
274 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
275 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
277 // We don't support sin/cos/fmod
278 setOperationAction(ISD::FSIN , MVT::f64, Expand);
279 setOperationAction(ISD::FCOS , MVT::f64, Expand);
280 setOperationAction(ISD::FREM , MVT::f64, Expand);
281 setOperationAction(ISD::FSIN , MVT::f32, Expand);
282 setOperationAction(ISD::FCOS , MVT::f32, Expand);
283 setOperationAction(ISD::FREM , MVT::f32, Expand);
285 // Expand FP immediates into loads from the stack, except for the special
287 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
288 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
289 addLegalFPImmediate(+0.0); // xorps / xorpd
291 // Set up the FP register classes.
292 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
294 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
295 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
296 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
299 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
300 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
303 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
304 addLegalFPImmediate(+0.0); // FLD0
305 addLegalFPImmediate(+1.0); // FLD1
306 addLegalFPImmediate(-0.0); // FLD0/FCHS
307 addLegalFPImmediate(-1.0); // FLD1/FCHS
310 // First set operation action for all vector types to expand. Then we
311 // will selectively turn on ones that can be effectively codegen'd.
312 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
313 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
314 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
315 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
316 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
317 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
318 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
319 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
320 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
321 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
322 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
323 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
324 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
325 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
326 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
327 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
328 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
331 if (Subtarget->hasMMX()) {
332 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
333 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
334 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
335 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
337 // FIXME: add MMX packed arithmetics
339 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
340 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
341 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
342 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
344 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
345 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
346 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
348 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
349 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
351 setOperationAction(ISD::AND, MVT::v8i8, Promote);
352 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
353 setOperationAction(ISD::AND, MVT::v4i16, Promote);
354 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
355 setOperationAction(ISD::AND, MVT::v2i32, Promote);
356 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
357 setOperationAction(ISD::AND, MVT::v1i64, Legal);
359 setOperationAction(ISD::OR, MVT::v8i8, Promote);
360 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
361 setOperationAction(ISD::OR, MVT::v4i16, Promote);
362 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
363 setOperationAction(ISD::OR, MVT::v2i32, Promote);
364 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
365 setOperationAction(ISD::OR, MVT::v1i64, Legal);
367 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
368 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
369 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
370 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
371 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
372 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
373 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
375 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
376 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
377 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
378 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
379 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
380 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
381 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
383 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
384 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
385 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
386 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
388 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
389 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
390 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
393 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
394 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
395 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
396 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
399 if (Subtarget->hasSSE1()) {
400 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
402 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
403 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
404 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
405 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
406 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
407 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
408 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
409 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
410 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
413 if (Subtarget->hasSSE2()) {
414 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
415 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
416 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
417 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
418 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
420 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
421 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
422 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
423 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
424 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
425 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
426 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
427 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
428 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
429 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
430 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
431 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
432 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
434 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
435 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
436 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
437 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
438 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
439 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
441 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
442 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
443 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
444 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
445 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
447 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
448 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
449 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
450 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
454 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
455 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
456 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
457 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
458 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
459 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
460 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
461 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
462 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
463 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
464 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
465 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
468 // Custom lower v2i64 and v2f64 selects.
469 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
470 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
471 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
472 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
475 // We want to custom lower some of our intrinsics.
476 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
478 // We have target-specific dag combine patterns for the following nodes:
479 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
480 setTargetDAGCombine(ISD::SELECT);
482 computeRegisterProperties();
484 // FIXME: These should be based on subtarget info. Plus, the values should
485 // be smaller when we are in optimizing for size mode.
486 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
487 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
488 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
489 allowUnalignedMemoryAccesses = true; // x86 supports it!
493 //===----------------------------------------------------------------------===//
494 // Return Value Calling Convention Implementation
495 //===----------------------------------------------------------------------===//
497 #include "X86GenCallingConv.inc"
499 /// LowerRET - Lower an ISD::RET node.
500 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
501 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
503 SmallVector<CCValAssign, 16> RVLocs;
504 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
505 CCState CCInfo(CC, getTargetMachine(), RVLocs);
506 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
509 // If this is the first return lowered for this function, add the regs to the
510 // liveout set for the function.
511 if (DAG.getMachineFunction().liveout_empty()) {
512 for (unsigned i = 0; i != RVLocs.size(); ++i)
513 if (RVLocs[i].isRegLoc())
514 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
517 SDOperand Chain = Op.getOperand(0);
520 // Copy the result values into the output registers.
521 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
522 RVLocs[0].getLocReg() != X86::ST0) {
523 for (unsigned i = 0; i != RVLocs.size(); ++i) {
524 CCValAssign &VA = RVLocs[i];
525 assert(VA.isRegLoc() && "Can only return in registers!");
526 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
528 Flag = Chain.getValue(1);
531 // We need to handle a destination of ST0 specially, because it isn't really
533 SDOperand Value = Op.getOperand(1);
535 // If this is an FP return with ScalarSSE, we need to move the value from
536 // an XMM register onto the fp-stack.
540 // If this is a load into a scalarsse value, don't store the loaded value
541 // back to the stack, only to reload it: just replace the scalar-sse load.
542 if (ISD::isNON_EXTLoad(Value.Val) &&
543 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
544 Chain = Value.getOperand(0);
545 MemLoc = Value.getOperand(1);
547 // Spill the value to memory and reload it into top of stack.
548 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
549 MachineFunction &MF = DAG.getMachineFunction();
550 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
551 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
552 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
554 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
555 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
556 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
557 Chain = Value.getValue(1);
560 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
561 SDOperand Ops[] = { Chain, Value };
562 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
563 Flag = Chain.getValue(1);
566 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
568 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
570 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
574 /// LowerCallResult - Lower the result values of an ISD::CALL into the
575 /// appropriate copies out of appropriate physical registers. This assumes that
576 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
577 /// being lowered. The returns a SDNode with the same number of values as the
579 SDNode *X86TargetLowering::
580 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
581 unsigned CallingConv, SelectionDAG &DAG) {
583 // Assign locations to each value returned by this call.
584 SmallVector<CCValAssign, 16> RVLocs;
585 CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
586 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
589 SmallVector<SDOperand, 8> ResultVals;
591 // Copy all of the result registers out of their specified physreg.
592 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
593 for (unsigned i = 0; i != RVLocs.size(); ++i) {
594 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
595 RVLocs[i].getValVT(), InFlag).getValue(1);
596 InFlag = Chain.getValue(2);
597 ResultVals.push_back(Chain.getValue(0));
600 // Copies from the FP stack are special, as ST0 isn't a valid register
601 // before the fp stackifier runs.
603 // Copy ST0 into an RFP register with FP_GET_RESULT.
604 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
605 SDOperand GROps[] = { Chain, InFlag };
606 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
607 Chain = RetVal.getValue(1);
608 InFlag = RetVal.getValue(2);
610 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
613 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
614 // shouldn't be necessary except that RFP cannot be live across
615 // multiple blocks. When stackifier is fixed, they can be uncoupled.
616 MachineFunction &MF = DAG.getMachineFunction();
617 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
618 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
620 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag
622 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
623 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0);
624 Chain = RetVal.getValue(1);
627 if (RVLocs[0].getValVT() == MVT::f32 && !X86ScalarSSE)
628 // FIXME: we would really like to remember that this FP_ROUND
629 // operation is okay to eliminate if we allow excess FP precision.
630 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
631 ResultVals.push_back(RetVal);
634 // Merge everything together with a MERGE_VALUES node.
635 ResultVals.push_back(Chain);
636 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
637 &ResultVals[0], ResultVals.size()).Val;
641 //===----------------------------------------------------------------------===//
642 // C & StdCall Calling Convention implementation
643 //===----------------------------------------------------------------------===//
644 // StdCall calling convention seems to be standard for many Windows' API
645 // routines and around. It differs from C calling convention just a little:
646 // callee should clean up the stack, not caller. Symbols should be also
647 // decorated in some fancy way :) It doesn't support any vector arguments.
649 /// AddLiveIn - This helper function adds the specified physical register to the
650 /// MachineFunction as a live in value. It also creates a corresponding virtual
652 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
653 const TargetRegisterClass *RC) {
654 assert(RC->contains(PReg) && "Not the correct regclass!");
655 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
656 MF.addLiveIn(PReg, VReg);
660 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
662 unsigned NumArgs = Op.Val->getNumValues() - 1;
663 MachineFunction &MF = DAG.getMachineFunction();
664 MachineFrameInfo *MFI = MF.getFrameInfo();
665 SDOperand Root = Op.getOperand(0);
666 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
668 // Assign locations to all of the incoming arguments.
669 SmallVector<CCValAssign, 16> ArgLocs;
670 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
672 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
674 SmallVector<SDOperand, 8> ArgValues;
675 unsigned LastVal = ~0U;
676 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
677 CCValAssign &VA = ArgLocs[i];
678 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
680 assert(VA.getValNo() != LastVal &&
681 "Don't support value assigned to multiple locs yet");
682 LastVal = VA.getValNo();
685 MVT::ValueType RegVT = VA.getLocVT();
686 TargetRegisterClass *RC;
687 if (RegVT == MVT::i32)
688 RC = X86::GR32RegisterClass;
690 assert(MVT::isVector(RegVT));
691 RC = X86::VR128RegisterClass;
694 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
695 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
697 // If this is an 8 or 16-bit value, it is really passed promoted to 32
698 // bits. Insert an assert[sz]ext to capture this, then truncate to the
700 if (VA.getLocInfo() == CCValAssign::SExt)
701 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
702 DAG.getValueType(VA.getValVT()));
703 else if (VA.getLocInfo() == CCValAssign::ZExt)
704 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
705 DAG.getValueType(VA.getValVT()));
707 if (VA.getLocInfo() != CCValAssign::Full)
708 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
710 ArgValues.push_back(ArgValue);
712 assert(VA.isMemLoc());
714 // Create the nodes corresponding to a load from this parameter slot.
715 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
716 VA.getLocMemOffset());
717 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
718 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
722 unsigned StackSize = CCInfo.getNextStackOffset();
724 ArgValues.push_back(Root);
726 // If the function takes variable number of arguments, make a frame index for
727 // the start of the first vararg value... for expansion of llvm.va_start.
729 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
731 if (isStdCall && !isVarArg) {
732 BytesToPopOnReturn = StackSize; // Callee pops everything..
733 BytesCallerReserves = 0;
735 BytesToPopOnReturn = 0; // Callee pops nothing.
737 // If this is an sret function, the return should pop the hidden pointer.
739 (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
740 ISD::ParamFlags::StructReturn))
741 BytesToPopOnReturn = 4;
743 BytesCallerReserves = StackSize;
746 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
747 ReturnAddrIndex = 0; // No return address slot generated yet.
749 MF.getInfo<X86MachineFunctionInfo>()
750 ->setBytesToPopOnReturn(BytesToPopOnReturn);
752 // Return the new list of results.
753 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
754 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
757 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
759 SDOperand Chain = Op.getOperand(0);
760 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
761 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
762 SDOperand Callee = Op.getOperand(4);
763 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
765 // Analyze operands of the call, assigning locations to each operand.
766 SmallVector<CCValAssign, 16> ArgLocs;
767 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
768 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
770 // Get a count of how many bytes are to be pushed on the stack.
771 unsigned NumBytes = CCInfo.getNextStackOffset();
773 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
775 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
776 SmallVector<SDOperand, 8> MemOpChains;
780 // Walk the register/memloc assignments, inserting copies/loads.
781 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
782 CCValAssign &VA = ArgLocs[i];
783 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
785 // Promote the value if needed.
786 switch (VA.getLocInfo()) {
787 default: assert(0 && "Unknown loc info!");
788 case CCValAssign::Full: break;
789 case CCValAssign::SExt:
790 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
792 case CCValAssign::ZExt:
793 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
795 case CCValAssign::AExt:
796 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
801 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
803 assert(VA.isMemLoc());
804 if (StackPtr.Val == 0)
805 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
806 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
807 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
808 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
812 // If the first argument is an sret pointer, remember it.
813 bool isSRet = NumOps &&
814 (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
815 ISD::ParamFlags::StructReturn);
817 if (!MemOpChains.empty())
818 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
819 &MemOpChains[0], MemOpChains.size());
821 // Build a sequence of copy-to-reg nodes chained together with token chain
822 // and flag operands which copy the outgoing args into registers.
824 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
825 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
827 InFlag = Chain.getValue(1);
830 // ELF / PIC requires GOT in the EBX register before function calls via PLT
832 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
833 Subtarget->isPICStyleGOT()) {
834 Chain = DAG.getCopyToReg(Chain, X86::EBX,
835 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
837 InFlag = Chain.getValue(1);
840 // If the callee is a GlobalAddress node (quite common, every direct call is)
841 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
842 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
843 // We should use extra load for direct calls to dllimported functions in
845 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
846 getTargetMachine(), true))
847 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
848 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
849 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
851 // Returns a chain & a flag for retval copy to use.
852 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
853 SmallVector<SDOperand, 8> Ops;
854 Ops.push_back(Chain);
855 Ops.push_back(Callee);
857 // Add argument registers to the end of the list so that they are known live
859 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
860 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
861 RegsToPass[i].second.getValueType()));
863 // Add an implicit use GOT pointer in EBX.
864 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
865 Subtarget->isPICStyleGOT())
866 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
869 Ops.push_back(InFlag);
871 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
872 NodeTys, &Ops[0], Ops.size());
873 InFlag = Chain.getValue(1);
875 // Create the CALLSEQ_END node.
876 unsigned NumBytesForCalleeToPush = 0;
878 if (CC == CallingConv::X86_StdCall) {
880 NumBytesForCalleeToPush = isSRet ? 4 : 0;
882 NumBytesForCalleeToPush = NumBytes;
884 // If this is is a call to a struct-return function, the callee
885 // pops the hidden struct pointer, so we have to push it back.
886 // This is common for Darwin/X86, Linux & Mingw32 targets.
887 NumBytesForCalleeToPush = isSRet ? 4 : 0;
890 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
892 Ops.push_back(Chain);
893 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
894 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
895 Ops.push_back(InFlag);
896 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
897 InFlag = Chain.getValue(1);
899 // Handle result values, copying them out of physregs into vregs that we
901 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
905 //===----------------------------------------------------------------------===//
906 // FastCall Calling Convention implementation
907 //===----------------------------------------------------------------------===//
909 // The X86 'fastcall' calling convention passes up to two integer arguments in
910 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
911 // and requires that the callee pop its arguments off the stack (allowing proper
912 // tail calls), and has the same return value conventions as C calling convs.
914 // This calling convention always arranges for the callee pop value to be 8n+4
915 // bytes, which is needed for tail recursion elimination and stack alignment
918 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
919 MachineFunction &MF = DAG.getMachineFunction();
920 MachineFrameInfo *MFI = MF.getFrameInfo();
921 SDOperand Root = Op.getOperand(0);
923 // Assign locations to all of the incoming arguments.
924 SmallVector<CCValAssign, 16> ArgLocs;
925 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
927 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
929 SmallVector<SDOperand, 8> ArgValues;
930 unsigned LastVal = ~0U;
931 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
932 CCValAssign &VA = ArgLocs[i];
933 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
935 assert(VA.getValNo() != LastVal &&
936 "Don't support value assigned to multiple locs yet");
937 LastVal = VA.getValNo();
940 MVT::ValueType RegVT = VA.getLocVT();
941 TargetRegisterClass *RC;
942 if (RegVT == MVT::i32)
943 RC = X86::GR32RegisterClass;
945 assert(MVT::isVector(RegVT));
946 RC = X86::VR128RegisterClass;
949 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
950 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
952 // If this is an 8 or 16-bit value, it is really passed promoted to 32
953 // bits. Insert an assert[sz]ext to capture this, then truncate to the
955 if (VA.getLocInfo() == CCValAssign::SExt)
956 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
957 DAG.getValueType(VA.getValVT()));
958 else if (VA.getLocInfo() == CCValAssign::ZExt)
959 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
960 DAG.getValueType(VA.getValVT()));
962 if (VA.getLocInfo() != CCValAssign::Full)
963 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
965 ArgValues.push_back(ArgValue);
967 assert(VA.isMemLoc());
969 // Create the nodes corresponding to a load from this parameter slot.
970 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
971 VA.getLocMemOffset());
972 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
973 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
977 ArgValues.push_back(Root);
979 unsigned StackSize = CCInfo.getNextStackOffset();
981 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
982 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
983 // arguments and the arguments after the retaddr has been pushed are aligned.
984 if ((StackSize & 7) == 0)
988 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
989 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
990 ReturnAddrIndex = 0; // No return address slot generated yet.
991 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
992 BytesCallerReserves = 0;
994 MF.getInfo<X86MachineFunctionInfo>()
995 ->setBytesToPopOnReturn(BytesToPopOnReturn);
997 // Return the new list of results.
998 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
999 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1002 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1004 SDOperand Chain = Op.getOperand(0);
1005 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1006 SDOperand Callee = Op.getOperand(4);
1008 // Analyze operands of the call, assigning locations to each operand.
1009 SmallVector<CCValAssign, 16> ArgLocs;
1010 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
1011 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
1013 // Get a count of how many bytes are to be pushed on the stack.
1014 unsigned NumBytes = CCInfo.getNextStackOffset();
1016 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1017 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1018 // arguments and the arguments after the retaddr has been pushed are aligned.
1019 if ((NumBytes & 7) == 0)
1023 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1025 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1026 SmallVector<SDOperand, 8> MemOpChains;
1030 // Walk the register/memloc assignments, inserting copies/loads.
1031 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1032 CCValAssign &VA = ArgLocs[i];
1033 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1035 // Promote the value if needed.
1036 switch (VA.getLocInfo()) {
1037 default: assert(0 && "Unknown loc info!");
1038 case CCValAssign::Full: break;
1039 case CCValAssign::SExt:
1040 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1042 case CCValAssign::ZExt:
1043 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1045 case CCValAssign::AExt:
1046 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1050 if (VA.isRegLoc()) {
1051 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1053 assert(VA.isMemLoc());
1054 if (StackPtr.Val == 0)
1055 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1056 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1057 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1058 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1062 if (!MemOpChains.empty())
1063 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1064 &MemOpChains[0], MemOpChains.size());
1066 // Build a sequence of copy-to-reg nodes chained together with token chain
1067 // and flag operands which copy the outgoing args into registers.
1069 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1070 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1072 InFlag = Chain.getValue(1);
1075 // If the callee is a GlobalAddress node (quite common, every direct call is)
1076 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1077 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1078 // We should use extra load for direct calls to dllimported functions in
1080 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1081 getTargetMachine(), true))
1082 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1083 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1084 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1086 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1088 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1089 Subtarget->isPICStyleGOT()) {
1090 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1091 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1093 InFlag = Chain.getValue(1);
1096 // Returns a chain & a flag for retval copy to use.
1097 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1098 SmallVector<SDOperand, 8> Ops;
1099 Ops.push_back(Chain);
1100 Ops.push_back(Callee);
1102 // Add argument registers to the end of the list so that they are known live
1104 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1105 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1106 RegsToPass[i].second.getValueType()));
1108 // Add an implicit use GOT pointer in EBX.
1109 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1110 Subtarget->isPICStyleGOT())
1111 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1114 Ops.push_back(InFlag);
1116 // FIXME: Do not generate X86ISD::TAILCALL for now.
1117 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1118 NodeTys, &Ops[0], Ops.size());
1119 InFlag = Chain.getValue(1);
1121 // Returns a flag for retval copy to use.
1122 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1124 Ops.push_back(Chain);
1125 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1126 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1127 Ops.push_back(InFlag);
1128 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1129 InFlag = Chain.getValue(1);
1131 // Handle result values, copying them out of physregs into vregs that we
1133 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1137 //===----------------------------------------------------------------------===//
1138 // X86-64 C Calling Convention implementation
1139 //===----------------------------------------------------------------------===//
1142 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1143 MachineFunction &MF = DAG.getMachineFunction();
1144 MachineFrameInfo *MFI = MF.getFrameInfo();
1145 SDOperand Root = Op.getOperand(0);
1146 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1148 static const unsigned GPR64ArgRegs[] = {
1149 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1151 static const unsigned XMMArgRegs[] = {
1152 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1153 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1157 // Assign locations to all of the incoming arguments.
1158 SmallVector<CCValAssign, 16> ArgLocs;
1159 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
1161 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
1163 SmallVector<SDOperand, 8> ArgValues;
1164 unsigned LastVal = ~0U;
1165 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1166 CCValAssign &VA = ArgLocs[i];
1167 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1169 assert(VA.getValNo() != LastVal &&
1170 "Don't support value assigned to multiple locs yet");
1171 LastVal = VA.getValNo();
1173 if (VA.isRegLoc()) {
1174 MVT::ValueType RegVT = VA.getLocVT();
1175 TargetRegisterClass *RC;
1176 if (RegVT == MVT::i32)
1177 RC = X86::GR32RegisterClass;
1178 else if (RegVT == MVT::i64)
1179 RC = X86::GR64RegisterClass;
1180 else if (RegVT == MVT::f32)
1181 RC = X86::FR32RegisterClass;
1182 else if (RegVT == MVT::f64)
1183 RC = X86::FR64RegisterClass;
1185 assert(MVT::isVector(RegVT));
1186 if (MVT::getSizeInBits(RegVT) == 64) {
1187 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1190 RC = X86::VR128RegisterClass;
1193 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1194 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1196 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1197 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1199 if (VA.getLocInfo() == CCValAssign::SExt)
1200 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1201 DAG.getValueType(VA.getValVT()));
1202 else if (VA.getLocInfo() == CCValAssign::ZExt)
1203 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1204 DAG.getValueType(VA.getValVT()));
1206 if (VA.getLocInfo() != CCValAssign::Full)
1207 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1209 // Handle MMX values passed in GPRs.
1210 if (RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1211 MVT::getSizeInBits(RegVT) == 64)
1212 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1214 ArgValues.push_back(ArgValue);
1216 assert(VA.isMemLoc());
1218 // Create the nodes corresponding to a load from this parameter slot.
1219 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1220 VA.getLocMemOffset());
1221 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1222 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1226 unsigned StackSize = CCInfo.getNextStackOffset();
1228 // If the function takes variable number of arguments, make a frame index for
1229 // the start of the first vararg value... for expansion of llvm.va_start.
1231 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1232 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1234 // For X86-64, if there are vararg parameters that are passed via
1235 // registers, then we must store them to their spots on the stack so they
1236 // may be loaded by deferencing the result of va_next.
1237 VarArgsGPOffset = NumIntRegs * 8;
1238 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1239 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1240 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1242 // Store the integer parameter registers.
1243 SmallVector<SDOperand, 8> MemOps;
1244 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1245 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1246 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1247 for (; NumIntRegs != 6; ++NumIntRegs) {
1248 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1249 X86::GR64RegisterClass);
1250 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1251 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1252 MemOps.push_back(Store);
1253 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1254 DAG.getConstant(8, getPointerTy()));
1257 // Now store the XMM (fp + vector) parameter registers.
1258 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1259 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1260 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1261 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1262 X86::VR128RegisterClass);
1263 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1264 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1265 MemOps.push_back(Store);
1266 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1267 DAG.getConstant(16, getPointerTy()));
1269 if (!MemOps.empty())
1270 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1271 &MemOps[0], MemOps.size());
1274 ArgValues.push_back(Root);
1276 ReturnAddrIndex = 0; // No return address slot generated yet.
1277 BytesToPopOnReturn = 0; // Callee pops nothing.
1278 BytesCallerReserves = StackSize;
1280 // Return the new list of results.
1281 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1282 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1286 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1288 SDOperand Chain = Op.getOperand(0);
1289 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1290 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1291 SDOperand Callee = Op.getOperand(4);
1293 // Analyze operands of the call, assigning locations to each operand.
1294 SmallVector<CCValAssign, 16> ArgLocs;
1295 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
1296 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_64_C);
1298 // Get a count of how many bytes are to be pushed on the stack.
1299 unsigned NumBytes = CCInfo.getNextStackOffset();
1300 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1302 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1303 SmallVector<SDOperand, 8> MemOpChains;
1307 // Walk the register/memloc assignments, inserting copies/loads.
1308 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1309 CCValAssign &VA = ArgLocs[i];
1310 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1312 // Promote the value if needed.
1313 switch (VA.getLocInfo()) {
1314 default: assert(0 && "Unknown loc info!");
1315 case CCValAssign::Full: break;
1316 case CCValAssign::SExt:
1317 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1319 case CCValAssign::ZExt:
1320 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1322 case CCValAssign::AExt:
1323 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1327 if (VA.isRegLoc()) {
1328 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1330 assert(VA.isMemLoc());
1331 if (StackPtr.Val == 0)
1332 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1333 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1334 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1335 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1339 if (!MemOpChains.empty())
1340 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1341 &MemOpChains[0], MemOpChains.size());
1343 // Build a sequence of copy-to-reg nodes chained together with token chain
1344 // and flag operands which copy the outgoing args into registers.
1346 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1347 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1349 InFlag = Chain.getValue(1);
1353 // From AMD64 ABI document:
1354 // For calls that may call functions that use varargs or stdargs
1355 // (prototype-less calls or calls to functions containing ellipsis (...) in
1356 // the declaration) %al is used as hidden argument to specify the number
1357 // of SSE registers used. The contents of %al do not need to match exactly
1358 // the number of registers, but must be an ubound on the number of SSE
1359 // registers used and is in the range 0 - 8 inclusive.
1361 // Count the number of XMM registers allocated.
1362 static const unsigned XMMArgRegs[] = {
1363 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1364 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1366 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1368 Chain = DAG.getCopyToReg(Chain, X86::AL,
1369 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1370 InFlag = Chain.getValue(1);
1373 // If the callee is a GlobalAddress node (quite common, every direct call is)
1374 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1375 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1376 // We should use extra load for direct calls to dllimported functions in
1378 if (getTargetMachine().getCodeModel() != CodeModel::Large
1379 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1380 getTargetMachine(), true))
1381 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1382 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1383 if (getTargetMachine().getCodeModel() != CodeModel::Large)
1384 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1386 // Returns a chain & a flag for retval copy to use.
1387 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1388 SmallVector<SDOperand, 8> Ops;
1389 Ops.push_back(Chain);
1390 Ops.push_back(Callee);
1392 // Add argument registers to the end of the list so that they are known live
1394 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1395 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1396 RegsToPass[i].second.getValueType()));
1399 Ops.push_back(InFlag);
1401 // FIXME: Do not generate X86ISD::TAILCALL for now.
1402 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1403 NodeTys, &Ops[0], Ops.size());
1404 InFlag = Chain.getValue(1);
1406 // Returns a flag for retval copy to use.
1407 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1409 Ops.push_back(Chain);
1410 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1411 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1412 Ops.push_back(InFlag);
1413 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1414 InFlag = Chain.getValue(1);
1416 // Handle result values, copying them out of physregs into vregs that we
1418 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1422 //===----------------------------------------------------------------------===//
1423 // Other Lowering Hooks
1424 //===----------------------------------------------------------------------===//
1427 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1428 if (ReturnAddrIndex == 0) {
1429 // Set up a frame object for the return address.
1430 MachineFunction &MF = DAG.getMachineFunction();
1431 if (Subtarget->is64Bit())
1432 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1434 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1437 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1442 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1443 /// specific condition code. It returns a false if it cannot do a direct
1444 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1446 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1447 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1448 SelectionDAG &DAG) {
1449 X86CC = X86::COND_INVALID;
1451 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1452 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1453 // X > -1 -> X == 0, jump !sign.
1454 RHS = DAG.getConstant(0, RHS.getValueType());
1455 X86CC = X86::COND_NS;
1457 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1458 // X < 0 -> X == 0, jump on sign.
1459 X86CC = X86::COND_S;
1464 switch (SetCCOpcode) {
1466 case ISD::SETEQ: X86CC = X86::COND_E; break;
1467 case ISD::SETGT: X86CC = X86::COND_G; break;
1468 case ISD::SETGE: X86CC = X86::COND_GE; break;
1469 case ISD::SETLT: X86CC = X86::COND_L; break;
1470 case ISD::SETLE: X86CC = X86::COND_LE; break;
1471 case ISD::SETNE: X86CC = X86::COND_NE; break;
1472 case ISD::SETULT: X86CC = X86::COND_B; break;
1473 case ISD::SETUGT: X86CC = X86::COND_A; break;
1474 case ISD::SETULE: X86CC = X86::COND_BE; break;
1475 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1478 // On a floating point condition, the flags are set as follows:
1480 // 0 | 0 | 0 | X > Y
1481 // 0 | 0 | 1 | X < Y
1482 // 1 | 0 | 0 | X == Y
1483 // 1 | 1 | 1 | unordered
1485 switch (SetCCOpcode) {
1488 case ISD::SETEQ: X86CC = X86::COND_E; break;
1489 case ISD::SETOLT: Flip = true; // Fallthrough
1491 case ISD::SETGT: X86CC = X86::COND_A; break;
1492 case ISD::SETOLE: Flip = true; // Fallthrough
1494 case ISD::SETGE: X86CC = X86::COND_AE; break;
1495 case ISD::SETUGT: Flip = true; // Fallthrough
1497 case ISD::SETLT: X86CC = X86::COND_B; break;
1498 case ISD::SETUGE: Flip = true; // Fallthrough
1500 case ISD::SETLE: X86CC = X86::COND_BE; break;
1502 case ISD::SETNE: X86CC = X86::COND_NE; break;
1503 case ISD::SETUO: X86CC = X86::COND_P; break;
1504 case ISD::SETO: X86CC = X86::COND_NP; break;
1507 std::swap(LHS, RHS);
1510 return X86CC != X86::COND_INVALID;
1513 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1514 /// code. Current x86 isa includes the following FP cmov instructions:
1515 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1516 static bool hasFPCMov(unsigned X86CC) {
1532 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1533 /// true if Op is undef or if its value falls within the specified range (L, H].
1534 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1535 if (Op.getOpcode() == ISD::UNDEF)
1538 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1539 return (Val >= Low && Val < Hi);
1542 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1543 /// true if Op is undef or if its value equal to the specified value.
1544 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1545 if (Op.getOpcode() == ISD::UNDEF)
1547 return cast<ConstantSDNode>(Op)->getValue() == Val;
1550 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1551 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1552 bool X86::isPSHUFDMask(SDNode *N) {
1553 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1555 if (N->getNumOperands() != 4)
1558 // Check if the value doesn't reference the second vector.
1559 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1560 SDOperand Arg = N->getOperand(i);
1561 if (Arg.getOpcode() == ISD::UNDEF) continue;
1562 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1563 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
1570 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1571 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1572 bool X86::isPSHUFHWMask(SDNode *N) {
1573 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1575 if (N->getNumOperands() != 8)
1578 // Lower quadword copied in order.
1579 for (unsigned i = 0; i != 4; ++i) {
1580 SDOperand Arg = N->getOperand(i);
1581 if (Arg.getOpcode() == ISD::UNDEF) continue;
1582 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1583 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1587 // Upper quadword shuffled.
1588 for (unsigned i = 4; i != 8; ++i) {
1589 SDOperand Arg = N->getOperand(i);
1590 if (Arg.getOpcode() == ISD::UNDEF) continue;
1591 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1592 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1593 if (Val < 4 || Val > 7)
1600 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1601 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1602 bool X86::isPSHUFLWMask(SDNode *N) {
1603 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1605 if (N->getNumOperands() != 8)
1608 // Upper quadword copied in order.
1609 for (unsigned i = 4; i != 8; ++i)
1610 if (!isUndefOrEqual(N->getOperand(i), i))
1613 // Lower quadword shuffled.
1614 for (unsigned i = 0; i != 4; ++i)
1615 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1621 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1622 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1623 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1624 if (NumElems != 2 && NumElems != 4) return false;
1626 unsigned Half = NumElems / 2;
1627 for (unsigned i = 0; i < Half; ++i)
1628 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1630 for (unsigned i = Half; i < NumElems; ++i)
1631 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1637 bool X86::isSHUFPMask(SDNode *N) {
1638 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1639 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1642 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
1643 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1644 /// half elements to come from vector 1 (which would equal the dest.) and
1645 /// the upper half to come from vector 2.
1646 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1647 if (NumOps != 2 && NumOps != 4) return false;
1649 unsigned Half = NumOps / 2;
1650 for (unsigned i = 0; i < Half; ++i)
1651 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1653 for (unsigned i = Half; i < NumOps; ++i)
1654 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1659 static bool isCommutedSHUFP(SDNode *N) {
1660 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1661 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1664 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1665 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1666 bool X86::isMOVHLPSMask(SDNode *N) {
1667 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1669 if (N->getNumOperands() != 4)
1672 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1673 return isUndefOrEqual(N->getOperand(0), 6) &&
1674 isUndefOrEqual(N->getOperand(1), 7) &&
1675 isUndefOrEqual(N->getOperand(2), 2) &&
1676 isUndefOrEqual(N->getOperand(3), 3);
1679 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1680 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1682 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1683 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1685 if (N->getNumOperands() != 4)
1688 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1689 return isUndefOrEqual(N->getOperand(0), 2) &&
1690 isUndefOrEqual(N->getOperand(1), 3) &&
1691 isUndefOrEqual(N->getOperand(2), 2) &&
1692 isUndefOrEqual(N->getOperand(3), 3);
1695 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1696 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1697 bool X86::isMOVLPMask(SDNode *N) {
1698 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1700 unsigned NumElems = N->getNumOperands();
1701 if (NumElems != 2 && NumElems != 4)
1704 for (unsigned i = 0; i < NumElems/2; ++i)
1705 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1708 for (unsigned i = NumElems/2; i < NumElems; ++i)
1709 if (!isUndefOrEqual(N->getOperand(i), i))
1715 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1716 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1718 bool X86::isMOVHPMask(SDNode *N) {
1719 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1721 unsigned NumElems = N->getNumOperands();
1722 if (NumElems != 2 && NumElems != 4)
1725 for (unsigned i = 0; i < NumElems/2; ++i)
1726 if (!isUndefOrEqual(N->getOperand(i), i))
1729 for (unsigned i = 0; i < NumElems/2; ++i) {
1730 SDOperand Arg = N->getOperand(i + NumElems/2);
1731 if (!isUndefOrEqual(Arg, i + NumElems))
1738 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1739 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1740 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1741 bool V2IsSplat = false) {
1742 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1745 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1746 SDOperand BitI = Elts[i];
1747 SDOperand BitI1 = Elts[i+1];
1748 if (!isUndefOrEqual(BitI, j))
1751 if (isUndefOrEqual(BitI1, NumElts))
1754 if (!isUndefOrEqual(BitI1, j + NumElts))
1762 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1763 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1764 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1767 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1768 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1769 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
1770 bool V2IsSplat = false) {
1771 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1774 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1775 SDOperand BitI = Elts[i];
1776 SDOperand BitI1 = Elts[i+1];
1777 if (!isUndefOrEqual(BitI, j + NumElts/2))
1780 if (isUndefOrEqual(BitI1, NumElts))
1783 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
1791 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1792 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1793 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1796 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1797 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1799 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1800 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1802 unsigned NumElems = N->getNumOperands();
1803 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1806 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1807 SDOperand BitI = N->getOperand(i);
1808 SDOperand BitI1 = N->getOperand(i+1);
1810 if (!isUndefOrEqual(BitI, j))
1812 if (!isUndefOrEqual(BitI1, j))
1819 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
1820 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
1822 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
1823 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1825 unsigned NumElems = N->getNumOperands();
1826 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1829 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
1830 SDOperand BitI = N->getOperand(i);
1831 SDOperand BitI1 = N->getOperand(i + 1);
1833 if (!isUndefOrEqual(BitI, j))
1835 if (!isUndefOrEqual(BitI1, j))
1842 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
1843 /// specifies a shuffle of elements that is suitable for input to MOVSS,
1844 /// MOVSD, and MOVD, i.e. setting the lowest element.
1845 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
1846 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1849 if (!isUndefOrEqual(Elts[0], NumElts))
1852 for (unsigned i = 1; i < NumElts; ++i) {
1853 if (!isUndefOrEqual(Elts[i], i))
1860 bool X86::isMOVLMask(SDNode *N) {
1861 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1862 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
1865 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
1866 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
1867 /// element of vector 2 and the other elements to come from vector 1 in order.
1868 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
1869 bool V2IsSplat = false,
1870 bool V2IsUndef = false) {
1871 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
1874 if (!isUndefOrEqual(Ops[0], 0))
1877 for (unsigned i = 1; i < NumOps; ++i) {
1878 SDOperand Arg = Ops[i];
1879 if (!(isUndefOrEqual(Arg, i+NumOps) ||
1880 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
1881 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
1888 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
1889 bool V2IsUndef = false) {
1890 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1891 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
1892 V2IsSplat, V2IsUndef);
1895 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1896 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
1897 bool X86::isMOVSHDUPMask(SDNode *N) {
1898 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1900 if (N->getNumOperands() != 4)
1903 // Expect 1, 1, 3, 3
1904 for (unsigned i = 0; i < 2; ++i) {
1905 SDOperand Arg = N->getOperand(i);
1906 if (Arg.getOpcode() == ISD::UNDEF) continue;
1907 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1908 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1909 if (Val != 1) return false;
1913 for (unsigned i = 2; i < 4; ++i) {
1914 SDOperand Arg = N->getOperand(i);
1915 if (Arg.getOpcode() == ISD::UNDEF) continue;
1916 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1917 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1918 if (Val != 3) return false;
1922 // Don't use movshdup if it can be done with a shufps.
1926 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1927 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
1928 bool X86::isMOVSLDUPMask(SDNode *N) {
1929 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1931 if (N->getNumOperands() != 4)
1934 // Expect 0, 0, 2, 2
1935 for (unsigned i = 0; i < 2; ++i) {
1936 SDOperand Arg = N->getOperand(i);
1937 if (Arg.getOpcode() == ISD::UNDEF) continue;
1938 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1939 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1940 if (Val != 0) return false;
1944 for (unsigned i = 2; i < 4; ++i) {
1945 SDOperand Arg = N->getOperand(i);
1946 if (Arg.getOpcode() == ISD::UNDEF) continue;
1947 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1948 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1949 if (Val != 2) return false;
1953 // Don't use movshdup if it can be done with a shufps.
1957 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
1958 /// specifies a identity operation on the LHS or RHS.
1959 static bool isIdentityMask(SDNode *N, bool RHS = false) {
1960 unsigned NumElems = N->getNumOperands();
1961 for (unsigned i = 0; i < NumElems; ++i)
1962 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
1967 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
1968 /// a splat of a single element.
1969 static bool isSplatMask(SDNode *N) {
1970 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1972 // This is a splat operation if each element of the permute is the same, and
1973 // if the value doesn't reference the second vector.
1974 unsigned NumElems = N->getNumOperands();
1975 SDOperand ElementBase;
1977 for (; i != NumElems; ++i) {
1978 SDOperand Elt = N->getOperand(i);
1979 if (isa<ConstantSDNode>(Elt)) {
1985 if (!ElementBase.Val)
1988 for (; i != NumElems; ++i) {
1989 SDOperand Arg = N->getOperand(i);
1990 if (Arg.getOpcode() == ISD::UNDEF) continue;
1991 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1992 if (Arg != ElementBase) return false;
1995 // Make sure it is a splat of the first vector operand.
1996 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
1999 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2000 /// a splat of a single element and it's a 2 or 4 element mask.
2001 bool X86::isSplatMask(SDNode *N) {
2002 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2004 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2005 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2007 return ::isSplatMask(N);
2010 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2011 /// specifies a splat of zero element.
2012 bool X86::isSplatLoMask(SDNode *N) {
2013 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2015 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2016 if (!isUndefOrEqual(N->getOperand(i), 0))
2021 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2022 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2024 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2025 unsigned NumOperands = N->getNumOperands();
2026 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2028 for (unsigned i = 0; i < NumOperands; ++i) {
2030 SDOperand Arg = N->getOperand(NumOperands-i-1);
2031 if (Arg.getOpcode() != ISD::UNDEF)
2032 Val = cast<ConstantSDNode>(Arg)->getValue();
2033 if (Val >= NumOperands) Val -= NumOperands;
2035 if (i != NumOperands - 1)
2042 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2043 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2045 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2047 // 8 nodes, but we only care about the last 4.
2048 for (unsigned i = 7; i >= 4; --i) {
2050 SDOperand Arg = N->getOperand(i);
2051 if (Arg.getOpcode() != ISD::UNDEF)
2052 Val = cast<ConstantSDNode>(Arg)->getValue();
2061 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2062 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2064 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2066 // 8 nodes, but we only care about the first 4.
2067 for (int i = 3; i >= 0; --i) {
2069 SDOperand Arg = N->getOperand(i);
2070 if (Arg.getOpcode() != ISD::UNDEF)
2071 Val = cast<ConstantSDNode>(Arg)->getValue();
2080 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2081 /// specifies a 8 element shuffle that can be broken into a pair of
2082 /// PSHUFHW and PSHUFLW.
2083 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2084 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2086 if (N->getNumOperands() != 8)
2089 // Lower quadword shuffled.
2090 for (unsigned i = 0; i != 4; ++i) {
2091 SDOperand Arg = N->getOperand(i);
2092 if (Arg.getOpcode() == ISD::UNDEF) continue;
2093 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2094 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2099 // Upper quadword shuffled.
2100 for (unsigned i = 4; i != 8; ++i) {
2101 SDOperand Arg = N->getOperand(i);
2102 if (Arg.getOpcode() == ISD::UNDEF) continue;
2103 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2104 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2105 if (Val < 4 || Val > 7)
2112 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2113 /// values in ther permute mask.
2114 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2115 SDOperand &V2, SDOperand &Mask,
2116 SelectionDAG &DAG) {
2117 MVT::ValueType VT = Op.getValueType();
2118 MVT::ValueType MaskVT = Mask.getValueType();
2119 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2120 unsigned NumElems = Mask.getNumOperands();
2121 SmallVector<SDOperand, 8> MaskVec;
2123 for (unsigned i = 0; i != NumElems; ++i) {
2124 SDOperand Arg = Mask.getOperand(i);
2125 if (Arg.getOpcode() == ISD::UNDEF) {
2126 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2129 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2130 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2132 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2134 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2138 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2139 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2142 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2143 /// match movhlps. The lower half elements should come from upper half of
2144 /// V1 (and in order), and the upper half elements should come from the upper
2145 /// half of V2 (and in order).
2146 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2147 unsigned NumElems = Mask->getNumOperands();
2150 for (unsigned i = 0, e = 2; i != e; ++i)
2151 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2153 for (unsigned i = 2; i != 4; ++i)
2154 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2159 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2160 /// is promoted to a vector.
2161 static inline bool isScalarLoadToVector(SDNode *N) {
2162 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2163 N = N->getOperand(0).Val;
2164 return ISD::isNON_EXTLoad(N);
2169 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2170 /// match movlp{s|d}. The lower half elements should come from lower half of
2171 /// V1 (and in order), and the upper half elements should come from the upper
2172 /// half of V2 (and in order). And since V1 will become the source of the
2173 /// MOVLP, it must be either a vector load or a scalar load to vector.
2174 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2175 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2177 // Is V2 is a vector load, don't do this transformation. We will try to use
2178 // load folding shufps op.
2179 if (ISD::isNON_EXTLoad(V2))
2182 unsigned NumElems = Mask->getNumOperands();
2183 if (NumElems != 2 && NumElems != 4)
2185 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2186 if (!isUndefOrEqual(Mask->getOperand(i), i))
2188 for (unsigned i = NumElems/2; i != NumElems; ++i)
2189 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2194 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2196 static bool isSplatVector(SDNode *N) {
2197 if (N->getOpcode() != ISD::BUILD_VECTOR)
2200 SDOperand SplatValue = N->getOperand(0);
2201 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2202 if (N->getOperand(i) != SplatValue)
2207 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2209 static bool isUndefShuffle(SDNode *N) {
2210 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2213 SDOperand V1 = N->getOperand(0);
2214 SDOperand V2 = N->getOperand(1);
2215 SDOperand Mask = N->getOperand(2);
2216 unsigned NumElems = Mask.getNumOperands();
2217 for (unsigned i = 0; i != NumElems; ++i) {
2218 SDOperand Arg = Mask.getOperand(i);
2219 if (Arg.getOpcode() != ISD::UNDEF) {
2220 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2221 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2223 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2230 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2232 static inline bool isZeroNode(SDOperand Elt) {
2233 return ((isa<ConstantSDNode>(Elt) &&
2234 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2235 (isa<ConstantFPSDNode>(Elt) &&
2236 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2239 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2240 /// to an zero vector.
2241 static bool isZeroShuffle(SDNode *N) {
2242 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2245 SDOperand V1 = N->getOperand(0);
2246 SDOperand V2 = N->getOperand(1);
2247 SDOperand Mask = N->getOperand(2);
2248 unsigned NumElems = Mask.getNumOperands();
2249 for (unsigned i = 0; i != NumElems; ++i) {
2250 SDOperand Arg = Mask.getOperand(i);
2251 if (Arg.getOpcode() != ISD::UNDEF) {
2252 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2253 if (Idx < NumElems) {
2254 unsigned Opc = V1.Val->getOpcode();
2255 if (Opc == ISD::UNDEF)
2257 if (Opc != ISD::BUILD_VECTOR ||
2258 !isZeroNode(V1.Val->getOperand(Idx)))
2260 } else if (Idx >= NumElems) {
2261 unsigned Opc = V2.Val->getOpcode();
2262 if (Opc == ISD::UNDEF)
2264 if (Opc != ISD::BUILD_VECTOR ||
2265 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2273 /// getZeroVector - Returns a vector of specified type with all zero elements.
2275 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2276 assert(MVT::isVector(VT) && "Expected a vector type");
2277 unsigned NumElems = MVT::getVectorNumElements(VT);
2278 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2279 bool isFP = MVT::isFloatingPoint(EVT);
2280 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2281 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2282 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2285 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2286 /// that point to V2 points to its first element.
2287 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2288 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2290 bool Changed = false;
2291 SmallVector<SDOperand, 8> MaskVec;
2292 unsigned NumElems = Mask.getNumOperands();
2293 for (unsigned i = 0; i != NumElems; ++i) {
2294 SDOperand Arg = Mask.getOperand(i);
2295 if (Arg.getOpcode() != ISD::UNDEF) {
2296 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2297 if (Val > NumElems) {
2298 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2302 MaskVec.push_back(Arg);
2306 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2307 &MaskVec[0], MaskVec.size());
2311 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2312 /// operation of specified width.
2313 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2314 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2315 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2317 SmallVector<SDOperand, 8> MaskVec;
2318 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2319 for (unsigned i = 1; i != NumElems; ++i)
2320 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2321 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2324 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2325 /// of specified width.
2326 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2327 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2328 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2329 SmallVector<SDOperand, 8> MaskVec;
2330 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2331 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2332 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2334 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2337 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2338 /// of specified width.
2339 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2340 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2341 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2342 unsigned Half = NumElems/2;
2343 SmallVector<SDOperand, 8> MaskVec;
2344 for (unsigned i = 0; i != Half; ++i) {
2345 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2346 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2348 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2351 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2353 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2354 SDOperand V1 = Op.getOperand(0);
2355 SDOperand Mask = Op.getOperand(2);
2356 MVT::ValueType VT = Op.getValueType();
2357 unsigned NumElems = Mask.getNumOperands();
2358 Mask = getUnpacklMask(NumElems, DAG);
2359 while (NumElems != 4) {
2360 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2363 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2365 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2366 Mask = getZeroVector(MaskVT, DAG);
2367 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2368 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2369 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2372 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2373 /// vector of zero or undef vector.
2374 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2375 unsigned NumElems, unsigned Idx,
2376 bool isZero, SelectionDAG &DAG) {
2377 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2378 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2379 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2380 SDOperand Zero = DAG.getConstant(0, EVT);
2381 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2382 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2383 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2384 &MaskVec[0], MaskVec.size());
2385 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2388 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2390 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2391 unsigned NumNonZero, unsigned NumZero,
2392 SelectionDAG &DAG, TargetLowering &TLI) {
2398 for (unsigned i = 0; i < 16; ++i) {
2399 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2400 if (ThisIsNonZero && First) {
2402 V = getZeroVector(MVT::v8i16, DAG);
2404 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2409 SDOperand ThisElt(0, 0), LastElt(0, 0);
2410 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2411 if (LastIsNonZero) {
2412 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2414 if (ThisIsNonZero) {
2415 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2416 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2417 ThisElt, DAG.getConstant(8, MVT::i8));
2419 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2424 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2425 DAG.getConstant(i/2, TLI.getPointerTy()));
2429 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2432 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2434 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2435 unsigned NumNonZero, unsigned NumZero,
2436 SelectionDAG &DAG, TargetLowering &TLI) {
2442 for (unsigned i = 0; i < 8; ++i) {
2443 bool isNonZero = (NonZeros & (1 << i)) != 0;
2447 V = getZeroVector(MVT::v8i16, DAG);
2449 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2452 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2453 DAG.getConstant(i, TLI.getPointerTy()));
2461 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2462 // All zero's are handled with pxor.
2463 if (ISD::isBuildVectorAllZeros(Op.Val))
2466 // All one's are handled with pcmpeqd.
2467 if (ISD::isBuildVectorAllOnes(Op.Val))
2470 MVT::ValueType VT = Op.getValueType();
2471 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2472 unsigned EVTBits = MVT::getSizeInBits(EVT);
2474 unsigned NumElems = Op.getNumOperands();
2475 unsigned NumZero = 0;
2476 unsigned NumNonZero = 0;
2477 unsigned NonZeros = 0;
2478 std::set<SDOperand> Values;
2479 for (unsigned i = 0; i < NumElems; ++i) {
2480 SDOperand Elt = Op.getOperand(i);
2481 if (Elt.getOpcode() != ISD::UNDEF) {
2483 if (isZeroNode(Elt))
2486 NonZeros |= (1 << i);
2492 if (NumNonZero == 0)
2493 // Must be a mix of zero and undef. Return a zero vector.
2494 return getZeroVector(VT, DAG);
2496 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2497 if (Values.size() == 1)
2500 // Special case for single non-zero element.
2501 if (NumNonZero == 1) {
2502 unsigned Idx = CountTrailingZeros_32(NonZeros);
2503 SDOperand Item = Op.getOperand(Idx);
2504 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2506 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2507 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2510 if (EVTBits == 32) {
2511 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2512 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2514 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2515 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2516 SmallVector<SDOperand, 8> MaskVec;
2517 for (unsigned i = 0; i < NumElems; i++)
2518 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2519 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2520 &MaskVec[0], MaskVec.size());
2521 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2522 DAG.getNode(ISD::UNDEF, VT), Mask);
2526 // Let legalizer expand 2-wide build_vectors.
2530 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2531 if (EVTBits == 8 && NumElems == 16) {
2532 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2534 if (V.Val) return V;
2537 if (EVTBits == 16 && NumElems == 8) {
2538 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2540 if (V.Val) return V;
2543 // If element VT is == 32 bits, turn it into a number of shuffles.
2544 SmallVector<SDOperand, 8> V;
2546 if (NumElems == 4 && NumZero > 0) {
2547 for (unsigned i = 0; i < 4; ++i) {
2548 bool isZero = !(NonZeros & (1 << i));
2550 V[i] = getZeroVector(VT, DAG);
2552 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2555 for (unsigned i = 0; i < 2; ++i) {
2556 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2559 V[i] = V[i*2]; // Must be a zero vector.
2562 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2563 getMOVLMask(NumElems, DAG));
2566 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2567 getMOVLMask(NumElems, DAG));
2570 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2571 getUnpacklMask(NumElems, DAG));
2576 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2577 // clears the upper bits.
2578 // FIXME: we can do the same for v4f32 case when we know both parts of
2579 // the lower half come from scalar_to_vector (loadf32). We should do
2580 // that in post legalizer dag combiner with target specific hooks.
2581 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2583 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2584 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2585 SmallVector<SDOperand, 8> MaskVec;
2586 bool Reverse = (NonZeros & 0x3) == 2;
2587 for (unsigned i = 0; i < 2; ++i)
2589 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2591 MaskVec.push_back(DAG.getConstant(i, EVT));
2592 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2593 for (unsigned i = 0; i < 2; ++i)
2595 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2597 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2598 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2599 &MaskVec[0], MaskVec.size());
2600 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2603 if (Values.size() > 2) {
2604 // Expand into a number of unpckl*.
2606 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2607 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2608 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2609 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2610 for (unsigned i = 0; i < NumElems; ++i)
2611 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2613 while (NumElems != 0) {
2614 for (unsigned i = 0; i < NumElems; ++i)
2615 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2626 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2627 SDOperand V1 = Op.getOperand(0);
2628 SDOperand V2 = Op.getOperand(1);
2629 SDOperand PermMask = Op.getOperand(2);
2630 MVT::ValueType VT = Op.getValueType();
2631 unsigned NumElems = PermMask.getNumOperands();
2632 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2633 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2634 bool V1IsSplat = false;
2635 bool V2IsSplat = false;
2637 if (isUndefShuffle(Op.Val))
2638 return DAG.getNode(ISD::UNDEF, VT);
2640 if (isZeroShuffle(Op.Val))
2641 return getZeroVector(VT, DAG);
2643 if (isIdentityMask(PermMask.Val))
2645 else if (isIdentityMask(PermMask.Val, true))
2648 if (isSplatMask(PermMask.Val)) {
2649 if (NumElems <= 4) return Op;
2650 // Promote it to a v4i32 splat.
2651 return PromoteSplat(Op, DAG);
2654 if (X86::isMOVLMask(PermMask.Val))
2655 return (V1IsUndef) ? V2 : Op;
2657 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2658 X86::isMOVSLDUPMask(PermMask.Val) ||
2659 X86::isMOVHLPSMask(PermMask.Val) ||
2660 X86::isMOVHPMask(PermMask.Val) ||
2661 X86::isMOVLPMask(PermMask.Val))
2664 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2665 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
2666 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2668 bool Commuted = false;
2669 V1IsSplat = isSplatVector(V1.Val);
2670 V2IsSplat = isSplatVector(V2.Val);
2671 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
2672 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2673 std::swap(V1IsSplat, V2IsSplat);
2674 std::swap(V1IsUndef, V2IsUndef);
2678 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
2679 if (V2IsUndef) return V1;
2680 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2682 // V2 is a splat, so the mask may be malformed. That is, it may point
2683 // to any V2 element. The instruction selectior won't like this. Get
2684 // a corrected mask and commute to form a proper MOVS{S|D}.
2685 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2686 if (NewMask.Val != PermMask.Val)
2687 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2692 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2693 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2694 X86::isUNPCKLMask(PermMask.Val) ||
2695 X86::isUNPCKHMask(PermMask.Val))
2699 // Normalize mask so all entries that point to V2 points to its first
2700 // element then try to match unpck{h|l} again. If match, return a
2701 // new vector_shuffle with the corrected mask.
2702 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2703 if (NewMask.Val != PermMask.Val) {
2704 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2705 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2706 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2707 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2708 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2709 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2714 // Normalize the node to match x86 shuffle ops if needed
2715 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
2716 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2719 // Commute is back and try unpck* again.
2720 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2721 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2722 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2723 X86::isUNPCKLMask(PermMask.Val) ||
2724 X86::isUNPCKHMask(PermMask.Val))
2728 // If VT is integer, try PSHUF* first, then SHUFP*.
2729 if (MVT::isInteger(VT)) {
2730 if (X86::isPSHUFDMask(PermMask.Val) ||
2731 X86::isPSHUFHWMask(PermMask.Val) ||
2732 X86::isPSHUFLWMask(PermMask.Val)) {
2733 if (V2.getOpcode() != ISD::UNDEF)
2734 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2735 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2739 if (X86::isSHUFPMask(PermMask.Val) &&
2740 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
2743 // Handle v8i16 shuffle high / low shuffle node pair.
2744 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2745 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2746 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2747 SmallVector<SDOperand, 8> MaskVec;
2748 for (unsigned i = 0; i != 4; ++i)
2749 MaskVec.push_back(PermMask.getOperand(i));
2750 for (unsigned i = 4; i != 8; ++i)
2751 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2752 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2753 &MaskVec[0], MaskVec.size());
2754 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2756 for (unsigned i = 0; i != 4; ++i)
2757 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2758 for (unsigned i = 4; i != 8; ++i)
2759 MaskVec.push_back(PermMask.getOperand(i));
2760 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
2761 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2764 // Floating point cases in the other order.
2765 if (X86::isSHUFPMask(PermMask.Val))
2767 if (X86::isPSHUFDMask(PermMask.Val) ||
2768 X86::isPSHUFHWMask(PermMask.Val) ||
2769 X86::isPSHUFLWMask(PermMask.Val)) {
2770 if (V2.getOpcode() != ISD::UNDEF)
2771 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2772 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2777 if (NumElems == 4 &&
2778 // Don't do this for MMX.
2779 MVT::getSizeInBits(VT) != 64) {
2780 MVT::ValueType MaskVT = PermMask.getValueType();
2781 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2782 SmallVector<std::pair<int, int>, 8> Locs;
2783 Locs.reserve(NumElems);
2784 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2785 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2788 // If no more than two elements come from either vector. This can be
2789 // implemented with two shuffles. First shuffle gather the elements.
2790 // The second shuffle, which takes the first shuffle as both of its
2791 // vector operands, put the elements into the right order.
2792 for (unsigned i = 0; i != NumElems; ++i) {
2793 SDOperand Elt = PermMask.getOperand(i);
2794 if (Elt.getOpcode() == ISD::UNDEF) {
2795 Locs[i] = std::make_pair(-1, -1);
2797 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2798 if (Val < NumElems) {
2799 Locs[i] = std::make_pair(0, NumLo);
2803 Locs[i] = std::make_pair(1, NumHi);
2804 if (2+NumHi < NumElems)
2805 Mask1[2+NumHi] = Elt;
2810 if (NumLo <= 2 && NumHi <= 2) {
2811 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2812 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2813 &Mask1[0], Mask1.size()));
2814 for (unsigned i = 0; i != NumElems; ++i) {
2815 if (Locs[i].first == -1)
2818 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
2819 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
2820 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
2824 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
2825 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2826 &Mask2[0], Mask2.size()));
2829 // Break it into (shuffle shuffle_hi, shuffle_lo).
2831 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2832 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2833 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
2834 unsigned MaskIdx = 0;
2836 unsigned HiIdx = NumElems/2;
2837 for (unsigned i = 0; i != NumElems; ++i) {
2838 if (i == NumElems/2) {
2844 SDOperand Elt = PermMask.getOperand(i);
2845 if (Elt.getOpcode() == ISD::UNDEF) {
2846 Locs[i] = std::make_pair(-1, -1);
2847 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
2848 Locs[i] = std::make_pair(MaskIdx, LoIdx);
2849 (*MaskPtr)[LoIdx] = Elt;
2852 Locs[i] = std::make_pair(MaskIdx, HiIdx);
2853 (*MaskPtr)[HiIdx] = Elt;
2858 SDOperand LoShuffle =
2859 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2860 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2861 &LoMask[0], LoMask.size()));
2862 SDOperand HiShuffle =
2863 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2864 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2865 &HiMask[0], HiMask.size()));
2866 SmallVector<SDOperand, 8> MaskOps;
2867 for (unsigned i = 0; i != NumElems; ++i) {
2868 if (Locs[i].first == -1) {
2869 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
2871 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
2872 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
2875 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
2876 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2877 &MaskOps[0], MaskOps.size()));
2884 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2885 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2888 MVT::ValueType VT = Op.getValueType();
2889 // TODO: handle v16i8.
2890 if (MVT::getSizeInBits(VT) == 16) {
2891 // Transform it so it match pextrw which produces a 32-bit result.
2892 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
2893 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
2894 Op.getOperand(0), Op.getOperand(1));
2895 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
2896 DAG.getValueType(VT));
2897 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
2898 } else if (MVT::getSizeInBits(VT) == 32) {
2899 SDOperand Vec = Op.getOperand(0);
2900 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2903 // SHUFPS the element to the lowest double word, then movss.
2904 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2905 SmallVector<SDOperand, 8> IdxVec;
2906 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
2907 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
2908 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
2909 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
2910 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2911 &IdxVec[0], IdxVec.size());
2912 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2913 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2914 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2915 DAG.getConstant(0, getPointerTy()));
2916 } else if (MVT::getSizeInBits(VT) == 64) {
2917 SDOperand Vec = Op.getOperand(0);
2918 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2922 // UNPCKHPD the element to the lowest double word, then movsd.
2923 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
2924 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
2925 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2926 SmallVector<SDOperand, 8> IdxVec;
2927 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
2928 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
2929 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2930 &IdxVec[0], IdxVec.size());
2931 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2932 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2933 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2934 DAG.getConstant(0, getPointerTy()));
2941 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2942 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
2943 // as its second argument.
2944 MVT::ValueType VT = Op.getValueType();
2945 MVT::ValueType BaseVT = MVT::getVectorElementType(VT);
2946 SDOperand N0 = Op.getOperand(0);
2947 SDOperand N1 = Op.getOperand(1);
2948 SDOperand N2 = Op.getOperand(2);
2949 if (MVT::getSizeInBits(BaseVT) == 16) {
2950 if (N1.getValueType() != MVT::i32)
2951 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
2952 if (N2.getValueType() != MVT::i32)
2953 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
2954 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
2955 } else if (MVT::getSizeInBits(BaseVT) == 32) {
2956 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
2959 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
2960 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2961 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2962 SmallVector<SDOperand, 8> MaskVec;
2963 MaskVec.push_back(DAG.getConstant(4, BaseVT));
2964 for (unsigned i = 1; i <= 3; ++i)
2965 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2966 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
2967 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2968 &MaskVec[0], MaskVec.size()));
2970 // Use two pinsrw instructions to insert a 32 bit value.
2972 if (MVT::isFloatingPoint(N1.getValueType())) {
2973 if (ISD::isNON_EXTLoad(N1.Val)) {
2974 // Just load directly from f32mem to GR32.
2975 LoadSDNode *LD = cast<LoadSDNode>(N1);
2976 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
2977 LD->getSrcValue(), LD->getSrcValueOffset());
2979 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
2980 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
2981 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
2982 DAG.getConstant(0, getPointerTy()));
2985 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
2986 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2987 DAG.getConstant(Idx, getPointerTy()));
2988 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
2989 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2990 DAG.getConstant(Idx+1, getPointerTy()));
2991 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2999 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3000 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3001 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3004 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3005 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3006 // one of the above mentioned nodes. It has to be wrapped because otherwise
3007 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3008 // be used to form addressing mode. These wrapped nodes will be selected
3011 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3012 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3013 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3015 CP->getAlignment());
3016 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3017 // With PIC, the address is actually $g + Offset.
3018 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3019 !Subtarget->isPICStyleRIPRel()) {
3020 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3021 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3029 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3030 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3031 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3032 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3033 // With PIC, the address is actually $g + Offset.
3034 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3035 !Subtarget->isPICStyleRIPRel()) {
3036 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3037 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3041 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3042 // load the value at address GV, not the value of GV itself. This means that
3043 // the GlobalAddress must be in the base or index register of the address, not
3044 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3045 // The same applies for external symbols during PIC codegen
3046 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3047 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3052 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3054 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3055 const MVT::ValueType PtrVT) {
3057 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3058 DAG.getNode(X86ISD::GlobalBaseReg,
3060 InFlag = Chain.getValue(1);
3062 // emit leal symbol@TLSGD(,%ebx,1), %eax
3063 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3064 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3065 GA->getValueType(0),
3067 SDOperand Ops[] = { Chain, TGA, InFlag };
3068 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3069 InFlag = Result.getValue(2);
3070 Chain = Result.getValue(1);
3072 // call ___tls_get_addr. This function receives its argument in
3073 // the register EAX.
3074 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3075 InFlag = Chain.getValue(1);
3077 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3078 SDOperand Ops1[] = { Chain,
3079 DAG.getTargetExternalSymbol("___tls_get_addr",
3081 DAG.getRegister(X86::EAX, PtrVT),
3082 DAG.getRegister(X86::EBX, PtrVT),
3084 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3085 InFlag = Chain.getValue(1);
3087 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3090 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3091 // "local exec" model.
3093 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3094 const MVT::ValueType PtrVT) {
3095 // Get the Thread Pointer
3096 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3097 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3099 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3100 GA->getValueType(0),
3102 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3104 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3105 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3107 // The address of the thread local variable is the add of the thread
3108 // pointer with the offset of the variable.
3109 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3113 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3114 // TODO: implement the "local dynamic" model
3115 // TODO: implement the "initial exec"model for pic executables
3116 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3117 "TLS not implemented for non-ELF and 64-bit targets");
3118 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3119 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3120 // otherwise use the "Local Exec"TLS Model
3121 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3122 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3124 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3128 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3129 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3130 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3131 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3132 // With PIC, the address is actually $g + Offset.
3133 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3134 !Subtarget->isPICStyleRIPRel()) {
3135 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3136 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3143 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3144 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3145 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3146 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3147 // With PIC, the address is actually $g + Offset.
3148 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3149 !Subtarget->isPICStyleRIPRel()) {
3150 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3151 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3158 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3159 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3160 "Not an i64 shift!");
3161 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3162 SDOperand ShOpLo = Op.getOperand(0);
3163 SDOperand ShOpHi = Op.getOperand(1);
3164 SDOperand ShAmt = Op.getOperand(2);
3165 SDOperand Tmp1 = isSRA ?
3166 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3167 DAG.getConstant(0, MVT::i32);
3169 SDOperand Tmp2, Tmp3;
3170 if (Op.getOpcode() == ISD::SHL_PARTS) {
3171 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3172 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3174 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3175 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3178 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3179 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3180 DAG.getConstant(32, MVT::i8));
3181 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3182 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3185 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3187 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3188 SmallVector<SDOperand, 4> Ops;
3189 if (Op.getOpcode() == ISD::SHL_PARTS) {
3190 Ops.push_back(Tmp2);
3191 Ops.push_back(Tmp3);
3193 Ops.push_back(InFlag);
3194 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3195 InFlag = Hi.getValue(1);
3198 Ops.push_back(Tmp3);
3199 Ops.push_back(Tmp1);
3201 Ops.push_back(InFlag);
3202 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3204 Ops.push_back(Tmp2);
3205 Ops.push_back(Tmp3);
3207 Ops.push_back(InFlag);
3208 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3209 InFlag = Lo.getValue(1);
3212 Ops.push_back(Tmp3);
3213 Ops.push_back(Tmp1);
3215 Ops.push_back(InFlag);
3216 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3219 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3223 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3226 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3227 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3228 Op.getOperand(0).getValueType() >= MVT::i16 &&
3229 "Unknown SINT_TO_FP to lower!");
3232 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3233 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3234 MachineFunction &MF = DAG.getMachineFunction();
3235 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3236 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3237 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3238 StackSlot, NULL, 0);
3243 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3245 Tys = DAG.getVTList(MVT::f64, MVT::Other);
3246 SmallVector<SDOperand, 8> Ops;
3247 Ops.push_back(Chain);
3248 Ops.push_back(StackSlot);
3249 Ops.push_back(DAG.getValueType(SrcVT));
3250 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3251 Tys, &Ops[0], Ops.size());
3254 Chain = Result.getValue(1);
3255 SDOperand InFlag = Result.getValue(2);
3257 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3258 // shouldn't be necessary except that RFP cannot be live across
3259 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3260 MachineFunction &MF = DAG.getMachineFunction();
3261 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3262 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3263 Tys = DAG.getVTList(MVT::Other);
3264 SmallVector<SDOperand, 8> Ops;
3265 Ops.push_back(Chain);
3266 Ops.push_back(Result);
3267 Ops.push_back(StackSlot);
3268 Ops.push_back(DAG.getValueType(Op.getValueType()));
3269 Ops.push_back(InFlag);
3270 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3271 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3277 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3278 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3279 "Unknown FP_TO_SINT to lower!");
3280 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3282 MachineFunction &MF = DAG.getMachineFunction();
3283 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3284 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3285 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3288 switch (Op.getValueType()) {
3289 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3290 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3291 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3292 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3295 SDOperand Chain = DAG.getEntryNode();
3296 SDOperand Value = Op.getOperand(0);
3298 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3299 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3300 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
3302 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3304 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3305 Chain = Value.getValue(1);
3306 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3307 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3310 // Build the FP_TO_INT*_IN_MEM
3311 SDOperand Ops[] = { Chain, Value, StackSlot };
3312 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3315 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3318 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3319 MVT::ValueType VT = Op.getValueType();
3320 const Type *OpNTy = MVT::getTypeForValueType(VT);
3321 std::vector<Constant*> CV;
3322 if (VT == MVT::f64) {
3323 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3324 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3326 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3327 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3328 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3329 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3331 Constant *CS = ConstantStruct::get(CV);
3332 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3333 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3334 SmallVector<SDOperand, 3> Ops;
3335 Ops.push_back(DAG.getEntryNode());
3336 Ops.push_back(CPIdx);
3337 Ops.push_back(DAG.getSrcValue(NULL));
3338 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3339 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3342 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3343 MVT::ValueType VT = Op.getValueType();
3344 const Type *OpNTy = MVT::getTypeForValueType(VT);
3345 std::vector<Constant*> CV;
3346 if (VT == MVT::f64) {
3347 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3348 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3350 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3351 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3352 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3353 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3355 Constant *CS = ConstantStruct::get(CV);
3356 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3357 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3358 SmallVector<SDOperand, 3> Ops;
3359 Ops.push_back(DAG.getEntryNode());
3360 Ops.push_back(CPIdx);
3361 Ops.push_back(DAG.getSrcValue(NULL));
3362 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3363 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3366 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3367 SDOperand Op0 = Op.getOperand(0);
3368 SDOperand Op1 = Op.getOperand(1);
3369 MVT::ValueType VT = Op.getValueType();
3370 MVT::ValueType SrcVT = Op1.getValueType();
3371 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3373 // If second operand is smaller, extend it first.
3374 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3375 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3379 // First get the sign bit of second operand.
3380 std::vector<Constant*> CV;
3381 if (SrcVT == MVT::f64) {
3382 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63)));
3383 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3385 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31)));
3386 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3387 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3388 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3390 Constant *CS = ConstantStruct::get(CV);
3391 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3392 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
3393 SmallVector<SDOperand, 3> Ops;
3394 Ops.push_back(DAG.getEntryNode());
3395 Ops.push_back(CPIdx);
3396 Ops.push_back(DAG.getSrcValue(NULL));
3397 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3398 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3400 // Shift sign bit right or left if the two operands have different types.
3401 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3402 // Op0 is MVT::f32, Op1 is MVT::f64.
3403 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3404 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3405 DAG.getConstant(32, MVT::i32));
3406 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3407 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3408 DAG.getConstant(0, getPointerTy()));
3411 // Clear first operand sign bit.
3413 if (VT == MVT::f64) {
3414 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63))));
3415 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3417 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31))));
3418 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3419 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3420 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3422 CS = ConstantStruct::get(CV);
3423 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3424 Tys = DAG.getVTList(VT, MVT::Other);
3426 Ops.push_back(DAG.getEntryNode());
3427 Ops.push_back(CPIdx);
3428 Ops.push_back(DAG.getSrcValue(NULL));
3429 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3430 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3432 // Or the value with the sign bit.
3433 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3436 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3438 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3440 SDOperand Op0 = Op.getOperand(0);
3441 SDOperand Op1 = Op.getOperand(1);
3442 SDOperand CC = Op.getOperand(2);
3443 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3444 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3445 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3446 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3449 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3451 SDOperand Ops1[] = { Chain, Op0, Op1 };
3452 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3453 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3454 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3457 assert(isFP && "Illegal integer SetCC!");
3459 SDOperand COps[] = { Chain, Op0, Op1 };
3460 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3462 switch (SetCCOpcode) {
3463 default: assert(false && "Illegal floating point SetCC!");
3464 case ISD::SETOEQ: { // !PF & ZF
3465 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3466 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3467 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3469 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3470 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3472 case ISD::SETUNE: { // PF | !ZF
3473 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3474 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3475 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3477 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3478 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3483 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3484 bool addTest = true;
3485 SDOperand Chain = DAG.getEntryNode();
3486 SDOperand Cond = Op.getOperand(0);
3488 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3490 if (Cond.getOpcode() == ISD::SETCC)
3491 Cond = LowerSETCC(Cond, DAG, Chain);
3493 if (Cond.getOpcode() == X86ISD::SETCC) {
3494 CC = Cond.getOperand(0);
3496 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3497 // (since flag operand cannot be shared). Use it as the condition setting
3498 // operand in place of the X86ISD::SETCC.
3499 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3500 // to use a test instead of duplicating the X86ISD::CMP (for register
3501 // pressure reason)?
3502 SDOperand Cmp = Cond.getOperand(1);
3503 unsigned Opc = Cmp.getOpcode();
3504 bool IllegalFPCMov = !X86ScalarSSE &&
3505 MVT::isFloatingPoint(Op.getValueType()) &&
3506 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3507 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3509 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3510 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3516 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3517 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3518 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3521 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3522 SmallVector<SDOperand, 4> Ops;
3523 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3524 // condition is true.
3525 Ops.push_back(Op.getOperand(2));
3526 Ops.push_back(Op.getOperand(1));
3528 Ops.push_back(Cond.getValue(1));
3529 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3532 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3533 bool addTest = true;
3534 SDOperand Chain = Op.getOperand(0);
3535 SDOperand Cond = Op.getOperand(1);
3536 SDOperand Dest = Op.getOperand(2);
3538 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3540 if (Cond.getOpcode() == ISD::SETCC)
3541 Cond = LowerSETCC(Cond, DAG, Chain);
3543 if (Cond.getOpcode() == X86ISD::SETCC) {
3544 CC = Cond.getOperand(0);
3546 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3547 // (since flag operand cannot be shared). Use it as the condition setting
3548 // operand in place of the X86ISD::SETCC.
3549 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3550 // to use a test instead of duplicating the X86ISD::CMP (for register
3551 // pressure reason)?
3552 SDOperand Cmp = Cond.getOperand(1);
3553 unsigned Opc = Cmp.getOpcode();
3554 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3555 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3556 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3562 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3563 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3564 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3566 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3567 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3570 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3571 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3573 if (Subtarget->is64Bit())
3574 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3576 switch (CallingConv) {
3578 assert(0 && "Unsupported calling convention");
3579 case CallingConv::Fast:
3580 // TODO: Implement fastcc
3582 case CallingConv::C:
3583 case CallingConv::X86_StdCall:
3584 return LowerCCCCallTo(Op, DAG, CallingConv);
3585 case CallingConv::X86_FastCall:
3586 return LowerFastCCCallTo(Op, DAG, CallingConv);
3591 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3592 // Calls to _alloca is needed to probe the stack when allocating more than 4k
3593 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3594 // that the guard pages used by the OS virtual memory manager are allocated in
3595 // correct sequence.
3596 SDOperand X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
3597 SelectionDAG &DAG) {
3598 assert(Subtarget->isTargetCygMing() &&
3599 "This should be used only on Cygwin/Mingw targets");
3602 SDOperand Chain = Op.getOperand(0);
3603 SDOperand Size = Op.getOperand(1);
3604 // FIXME: Ensure alignment here
3606 TargetLowering::ArgListTy Args;
3607 TargetLowering::ArgListEntry Entry;
3608 MVT::ValueType IntPtr = getPointerTy();
3609 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
3610 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3613 Entry.Ty = IntPtrTy;
3614 Entry.isInReg = true; // Should pass in EAX
3615 Args.push_back(Entry);
3616 std::pair<SDOperand, SDOperand> CallResult =
3617 LowerCallTo(Chain, IntPtrTy, false, false, CallingConv::C, false,
3618 DAG.getExternalSymbol("_alloca", IntPtr), Args, DAG);
3620 SDOperand SP = DAG.getCopyFromReg(CallResult.second, X86StackPtr, SPTy);
3622 std::vector<MVT::ValueType> Tys;
3623 Tys.push_back(SPTy);
3624 Tys.push_back(MVT::Other);
3625 SDOperand Ops[2] = { SP, CallResult.second };
3626 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
3630 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3631 MachineFunction &MF = DAG.getMachineFunction();
3632 const Function* Fn = MF.getFunction();
3633 if (Fn->hasExternalLinkage() &&
3634 Subtarget->isTargetCygMing() &&
3635 Fn->getName() == "main")
3636 MF.getInfo<X86MachineFunctionInfo>()->setForceFramePointer(true);
3638 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3639 if (Subtarget->is64Bit())
3640 return LowerX86_64CCCArguments(Op, DAG);
3644 assert(0 && "Unsupported calling convention");
3645 case CallingConv::Fast:
3646 // TODO: implement fastcc.
3649 case CallingConv::C:
3650 return LowerCCCArguments(Op, DAG);
3651 case CallingConv::X86_StdCall:
3652 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(StdCall);
3653 return LowerCCCArguments(Op, DAG, true);
3654 case CallingConv::X86_FastCall:
3655 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(FastCall);
3656 return LowerFastCCArguments(Op, DAG);
3660 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3661 SDOperand InFlag(0, 0);
3662 SDOperand Chain = Op.getOperand(0);
3664 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3665 if (Align == 0) Align = 1;
3667 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3668 // If not DWORD aligned, call memset if size is less than the threshold.
3669 // It knows how to align to the right boundary first.
3670 if ((Align & 3) != 0 ||
3671 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3672 MVT::ValueType IntPtr = getPointerTy();
3673 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3674 TargetLowering::ArgListTy Args;
3675 TargetLowering::ArgListEntry Entry;
3676 Entry.Node = Op.getOperand(1);
3677 Entry.Ty = IntPtrTy;
3678 Args.push_back(Entry);
3679 // Extend the unsigned i8 argument to be an int value for the call.
3680 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3681 Entry.Ty = IntPtrTy;
3682 Args.push_back(Entry);
3683 Entry.Node = Op.getOperand(3);
3684 Args.push_back(Entry);
3685 std::pair<SDOperand,SDOperand> CallResult =
3686 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3687 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3688 return CallResult.second;
3693 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3694 unsigned BytesLeft = 0;
3695 bool TwoRepStos = false;
3698 uint64_t Val = ValC->getValue() & 255;
3700 // If the value is a constant, then we can potentially use larger sets.
3701 switch (Align & 3) {
3702 case 2: // WORD aligned
3705 Val = (Val << 8) | Val;
3707 case 0: // DWORD aligned
3710 Val = (Val << 8) | Val;
3711 Val = (Val << 16) | Val;
3712 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3715 Val = (Val << 32) | Val;
3718 default: // Byte aligned
3721 Count = Op.getOperand(3);
3725 if (AVT > MVT::i8) {
3727 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3728 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3729 BytesLeft = I->getValue() % UBytes;
3731 assert(AVT >= MVT::i32 &&
3732 "Do not use rep;stos if not at least DWORD aligned");
3733 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3734 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3739 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3741 InFlag = Chain.getValue(1);
3744 Count = Op.getOperand(3);
3745 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
3746 InFlag = Chain.getValue(1);
3749 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3751 InFlag = Chain.getValue(1);
3752 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3753 Op.getOperand(1), InFlag);
3754 InFlag = Chain.getValue(1);
3756 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3757 SmallVector<SDOperand, 8> Ops;
3758 Ops.push_back(Chain);
3759 Ops.push_back(DAG.getValueType(AVT));
3760 Ops.push_back(InFlag);
3761 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3764 InFlag = Chain.getValue(1);
3765 Count = Op.getOperand(3);
3766 MVT::ValueType CVT = Count.getValueType();
3767 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3768 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3769 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3771 InFlag = Chain.getValue(1);
3772 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3774 Ops.push_back(Chain);
3775 Ops.push_back(DAG.getValueType(MVT::i8));
3776 Ops.push_back(InFlag);
3777 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3778 } else if (BytesLeft) {
3779 // Issue stores for the last 1 - 7 bytes.
3781 unsigned Val = ValC->getValue() & 255;
3782 unsigned Offset = I->getValue() - BytesLeft;
3783 SDOperand DstAddr = Op.getOperand(1);
3784 MVT::ValueType AddrVT = DstAddr.getValueType();
3785 if (BytesLeft >= 4) {
3786 Val = (Val << 8) | Val;
3787 Val = (Val << 16) | Val;
3788 Value = DAG.getConstant(Val, MVT::i32);
3789 Chain = DAG.getStore(Chain, Value,
3790 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3791 DAG.getConstant(Offset, AddrVT)),
3796 if (BytesLeft >= 2) {
3797 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
3798 Chain = DAG.getStore(Chain, Value,
3799 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3800 DAG.getConstant(Offset, AddrVT)),
3805 if (BytesLeft == 1) {
3806 Value = DAG.getConstant(Val, MVT::i8);
3807 Chain = DAG.getStore(Chain, Value,
3808 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3809 DAG.getConstant(Offset, AddrVT)),
3817 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
3818 SDOperand Chain = Op.getOperand(0);
3820 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3821 if (Align == 0) Align = 1;
3823 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3824 // If not DWORD aligned, call memcpy if size is less than the threshold.
3825 // It knows how to align to the right boundary first.
3826 if ((Align & 3) != 0 ||
3827 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3828 MVT::ValueType IntPtr = getPointerTy();
3829 TargetLowering::ArgListTy Args;
3830 TargetLowering::ArgListEntry Entry;
3831 Entry.Ty = getTargetData()->getIntPtrType();
3832 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
3833 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
3834 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
3835 std::pair<SDOperand,SDOperand> CallResult =
3836 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3837 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
3838 return CallResult.second;
3843 unsigned BytesLeft = 0;
3844 bool TwoRepMovs = false;
3845 switch (Align & 3) {
3846 case 2: // WORD aligned
3849 case 0: // DWORD aligned
3851 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
3854 default: // Byte aligned
3856 Count = Op.getOperand(3);
3860 if (AVT > MVT::i8) {
3862 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3863 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3864 BytesLeft = I->getValue() % UBytes;
3866 assert(AVT >= MVT::i32 &&
3867 "Do not use rep;movs if not at least DWORD aligned");
3868 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3869 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3874 SDOperand InFlag(0, 0);
3875 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3877 InFlag = Chain.getValue(1);
3878 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3879 Op.getOperand(1), InFlag);
3880 InFlag = Chain.getValue(1);
3881 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
3882 Op.getOperand(2), InFlag);
3883 InFlag = Chain.getValue(1);
3885 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3886 SmallVector<SDOperand, 8> Ops;
3887 Ops.push_back(Chain);
3888 Ops.push_back(DAG.getValueType(AVT));
3889 Ops.push_back(InFlag);
3890 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3893 InFlag = Chain.getValue(1);
3894 Count = Op.getOperand(3);
3895 MVT::ValueType CVT = Count.getValueType();
3896 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3897 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3898 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3900 InFlag = Chain.getValue(1);
3901 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3903 Ops.push_back(Chain);
3904 Ops.push_back(DAG.getValueType(MVT::i8));
3905 Ops.push_back(InFlag);
3906 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3907 } else if (BytesLeft) {
3908 // Issue loads and stores for the last 1 - 7 bytes.
3909 unsigned Offset = I->getValue() - BytesLeft;
3910 SDOperand DstAddr = Op.getOperand(1);
3911 MVT::ValueType DstVT = DstAddr.getValueType();
3912 SDOperand SrcAddr = Op.getOperand(2);
3913 MVT::ValueType SrcVT = SrcAddr.getValueType();
3915 if (BytesLeft >= 4) {
3916 Value = DAG.getLoad(MVT::i32, Chain,
3917 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3918 DAG.getConstant(Offset, SrcVT)),
3920 Chain = Value.getValue(1);
3921 Chain = DAG.getStore(Chain, Value,
3922 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3923 DAG.getConstant(Offset, DstVT)),
3928 if (BytesLeft >= 2) {
3929 Value = DAG.getLoad(MVT::i16, Chain,
3930 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3931 DAG.getConstant(Offset, SrcVT)),
3933 Chain = Value.getValue(1);
3934 Chain = DAG.getStore(Chain, Value,
3935 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3936 DAG.getConstant(Offset, DstVT)),
3942 if (BytesLeft == 1) {
3943 Value = DAG.getLoad(MVT::i8, Chain,
3944 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3945 DAG.getConstant(Offset, SrcVT)),
3947 Chain = Value.getValue(1);
3948 Chain = DAG.getStore(Chain, Value,
3949 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3950 DAG.getConstant(Offset, DstVT)),
3959 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
3960 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3961 SDOperand TheOp = Op.getOperand(0);
3962 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
3963 if (Subtarget->is64Bit()) {
3964 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
3965 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
3966 MVT::i64, Copy1.getValue(2));
3967 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
3968 DAG.getConstant(32, MVT::i8));
3970 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
3973 Tys = DAG.getVTList(MVT::i64, MVT::Other);
3974 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
3977 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
3978 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
3979 MVT::i32, Copy1.getValue(2));
3980 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
3981 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
3982 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
3985 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
3986 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
3988 if (!Subtarget->is64Bit()) {
3989 // vastart just stores the address of the VarArgsFrameIndex slot into the
3990 // memory location argument.
3991 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
3992 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
3997 // gp_offset (0 - 6 * 8)
3998 // fp_offset (48 - 48 + 8 * 16)
3999 // overflow_arg_area (point to parameters coming in memory).
4001 SmallVector<SDOperand, 8> MemOps;
4002 SDOperand FIN = Op.getOperand(1);
4004 SDOperand Store = DAG.getStore(Op.getOperand(0),
4005 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4006 FIN, SV->getValue(), SV->getOffset());
4007 MemOps.push_back(Store);
4010 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4011 DAG.getConstant(4, getPointerTy()));
4012 Store = DAG.getStore(Op.getOperand(0),
4013 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4014 FIN, SV->getValue(), SV->getOffset());
4015 MemOps.push_back(Store);
4017 // Store ptr to overflow_arg_area
4018 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4019 DAG.getConstant(4, getPointerTy()));
4020 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4021 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4023 MemOps.push_back(Store);
4025 // Store ptr to reg_save_area.
4026 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4027 DAG.getConstant(8, getPointerTy()));
4028 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4029 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4031 MemOps.push_back(Store);
4032 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4035 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4036 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4037 SDOperand Chain = Op.getOperand(0);
4038 SDOperand DstPtr = Op.getOperand(1);
4039 SDOperand SrcPtr = Op.getOperand(2);
4040 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4041 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4043 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4044 SrcSV->getValue(), SrcSV->getOffset());
4045 Chain = SrcPtr.getValue(1);
4046 for (unsigned i = 0; i < 3; ++i) {
4047 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4048 SrcSV->getValue(), SrcSV->getOffset());
4049 Chain = Val.getValue(1);
4050 Chain = DAG.getStore(Chain, Val, DstPtr,
4051 DstSV->getValue(), DstSV->getOffset());
4054 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4055 DAG.getConstant(8, getPointerTy()));
4056 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4057 DAG.getConstant(8, getPointerTy()));
4063 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4064 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4066 default: return SDOperand(); // Don't custom lower most intrinsics.
4067 // Comparison intrinsics.
4068 case Intrinsic::x86_sse_comieq_ss:
4069 case Intrinsic::x86_sse_comilt_ss:
4070 case Intrinsic::x86_sse_comile_ss:
4071 case Intrinsic::x86_sse_comigt_ss:
4072 case Intrinsic::x86_sse_comige_ss:
4073 case Intrinsic::x86_sse_comineq_ss:
4074 case Intrinsic::x86_sse_ucomieq_ss:
4075 case Intrinsic::x86_sse_ucomilt_ss:
4076 case Intrinsic::x86_sse_ucomile_ss:
4077 case Intrinsic::x86_sse_ucomigt_ss:
4078 case Intrinsic::x86_sse_ucomige_ss:
4079 case Intrinsic::x86_sse_ucomineq_ss:
4080 case Intrinsic::x86_sse2_comieq_sd:
4081 case Intrinsic::x86_sse2_comilt_sd:
4082 case Intrinsic::x86_sse2_comile_sd:
4083 case Intrinsic::x86_sse2_comigt_sd:
4084 case Intrinsic::x86_sse2_comige_sd:
4085 case Intrinsic::x86_sse2_comineq_sd:
4086 case Intrinsic::x86_sse2_ucomieq_sd:
4087 case Intrinsic::x86_sse2_ucomilt_sd:
4088 case Intrinsic::x86_sse2_ucomile_sd:
4089 case Intrinsic::x86_sse2_ucomigt_sd:
4090 case Intrinsic::x86_sse2_ucomige_sd:
4091 case Intrinsic::x86_sse2_ucomineq_sd: {
4093 ISD::CondCode CC = ISD::SETCC_INVALID;
4096 case Intrinsic::x86_sse_comieq_ss:
4097 case Intrinsic::x86_sse2_comieq_sd:
4101 case Intrinsic::x86_sse_comilt_ss:
4102 case Intrinsic::x86_sse2_comilt_sd:
4106 case Intrinsic::x86_sse_comile_ss:
4107 case Intrinsic::x86_sse2_comile_sd:
4111 case Intrinsic::x86_sse_comigt_ss:
4112 case Intrinsic::x86_sse2_comigt_sd:
4116 case Intrinsic::x86_sse_comige_ss:
4117 case Intrinsic::x86_sse2_comige_sd:
4121 case Intrinsic::x86_sse_comineq_ss:
4122 case Intrinsic::x86_sse2_comineq_sd:
4126 case Intrinsic::x86_sse_ucomieq_ss:
4127 case Intrinsic::x86_sse2_ucomieq_sd:
4128 Opc = X86ISD::UCOMI;
4131 case Intrinsic::x86_sse_ucomilt_ss:
4132 case Intrinsic::x86_sse2_ucomilt_sd:
4133 Opc = X86ISD::UCOMI;
4136 case Intrinsic::x86_sse_ucomile_ss:
4137 case Intrinsic::x86_sse2_ucomile_sd:
4138 Opc = X86ISD::UCOMI;
4141 case Intrinsic::x86_sse_ucomigt_ss:
4142 case Intrinsic::x86_sse2_ucomigt_sd:
4143 Opc = X86ISD::UCOMI;
4146 case Intrinsic::x86_sse_ucomige_ss:
4147 case Intrinsic::x86_sse2_ucomige_sd:
4148 Opc = X86ISD::UCOMI;
4151 case Intrinsic::x86_sse_ucomineq_ss:
4152 case Intrinsic::x86_sse2_ucomineq_sd:
4153 Opc = X86ISD::UCOMI;
4159 SDOperand LHS = Op.getOperand(1);
4160 SDOperand RHS = Op.getOperand(2);
4161 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4163 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4164 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4165 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4166 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4167 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4168 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4169 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4174 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4175 // Depths > 0 not supported yet!
4176 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4179 // Just load the return address
4180 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4181 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4184 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4185 // Depths > 0 not supported yet!
4186 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4189 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4190 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4191 DAG.getConstant(4, getPointerTy()));
4194 /// LowerOperation - Provide custom lowering hooks for some operations.
4196 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4197 switch (Op.getOpcode()) {
4198 default: assert(0 && "Should not custom lower this!");
4199 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4200 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4201 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4202 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4203 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4204 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4205 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4206 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4207 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4208 case ISD::SHL_PARTS:
4209 case ISD::SRA_PARTS:
4210 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4211 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4212 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4213 case ISD::FABS: return LowerFABS(Op, DAG);
4214 case ISD::FNEG: return LowerFNEG(Op, DAG);
4215 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4216 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4217 case ISD::SELECT: return LowerSELECT(Op, DAG);
4218 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4219 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4220 case ISD::CALL: return LowerCALL(Op, DAG);
4221 case ISD::RET: return LowerRET(Op, DAG);
4222 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4223 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4224 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4225 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4226 case ISD::VASTART: return LowerVASTART(Op, DAG);
4227 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
4228 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4229 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4230 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4231 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
4236 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4238 default: return NULL;
4239 case X86ISD::SHLD: return "X86ISD::SHLD";
4240 case X86ISD::SHRD: return "X86ISD::SHRD";
4241 case X86ISD::FAND: return "X86ISD::FAND";
4242 case X86ISD::FOR: return "X86ISD::FOR";
4243 case X86ISD::FXOR: return "X86ISD::FXOR";
4244 case X86ISD::FSRL: return "X86ISD::FSRL";
4245 case X86ISD::FILD: return "X86ISD::FILD";
4246 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4247 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4248 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4249 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4250 case X86ISD::FLD: return "X86ISD::FLD";
4251 case X86ISD::FST: return "X86ISD::FST";
4252 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4253 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4254 case X86ISD::CALL: return "X86ISD::CALL";
4255 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4256 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4257 case X86ISD::CMP: return "X86ISD::CMP";
4258 case X86ISD::COMI: return "X86ISD::COMI";
4259 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4260 case X86ISD::SETCC: return "X86ISD::SETCC";
4261 case X86ISD::CMOV: return "X86ISD::CMOV";
4262 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4263 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4264 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4265 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4266 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4267 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4268 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4269 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4270 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4271 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4272 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4273 case X86ISD::FMAX: return "X86ISD::FMAX";
4274 case X86ISD::FMIN: return "X86ISD::FMIN";
4275 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
4276 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
4280 // isLegalAddressingMode - Return true if the addressing mode represented
4281 // by AM is legal for this target, for a load/store of the specified type.
4282 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
4283 const Type *Ty) const {
4284 // X86 supports extremely general addressing modes.
4286 // X86 allows a sign-extended 32-bit immediate field as a displacement.
4287 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
4291 // X86-64 only supports addr of globals in small code model.
4292 if (Subtarget->is64Bit() &&
4293 getTargetMachine().getCodeModel() != CodeModel::Small)
4296 // We can only fold this if we don't need a load either.
4297 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
4307 // These scales always work.
4312 // These scales are formed with basereg+scalereg. Only accept if there is
4317 default: // Other stuff never works.
4325 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4326 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4327 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4328 /// are assumed to be legal.
4330 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4331 // Only do shuffles on 128-bit vector types for now.
4332 if (MVT::getSizeInBits(VT) == 64) return false;
4333 return (Mask.Val->getNumOperands() <= 4 ||
4334 isIdentityMask(Mask.Val) ||
4335 isIdentityMask(Mask.Val, true) ||
4336 isSplatMask(Mask.Val) ||
4337 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4338 X86::isUNPCKLMask(Mask.Val) ||
4339 X86::isUNPCKHMask(Mask.Val) ||
4340 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4341 X86::isUNPCKH_v_undef_Mask(Mask.Val));
4344 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4346 SelectionDAG &DAG) const {
4347 unsigned NumElts = BVOps.size();
4348 // Only do shuffles on 128-bit vector types for now.
4349 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4350 if (NumElts == 2) return true;
4352 return (isMOVLMask(&BVOps[0], 4) ||
4353 isCommutedMOVL(&BVOps[0], 4, true) ||
4354 isSHUFPMask(&BVOps[0], 4) ||
4355 isCommutedSHUFP(&BVOps[0], 4));
4360 //===----------------------------------------------------------------------===//
4361 // X86 Scheduler Hooks
4362 //===----------------------------------------------------------------------===//
4365 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4366 MachineBasicBlock *BB) {
4367 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4368 switch (MI->getOpcode()) {
4369 default: assert(false && "Unexpected instr type to insert");
4370 case X86::CMOV_FR32:
4371 case X86::CMOV_FR64:
4372 case X86::CMOV_V4F32:
4373 case X86::CMOV_V2F64:
4374 case X86::CMOV_V2I64: {
4375 // To "insert" a SELECT_CC instruction, we actually have to insert the
4376 // diamond control-flow pattern. The incoming instruction knows the
4377 // destination vreg to set, the condition code register to branch on, the
4378 // true/false values to select between, and a branch opcode to use.
4379 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4380 ilist<MachineBasicBlock>::iterator It = BB;
4386 // cmpTY ccX, r1, r2
4388 // fallthrough --> copy0MBB
4389 MachineBasicBlock *thisMBB = BB;
4390 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4391 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4393 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4394 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4395 MachineFunction *F = BB->getParent();
4396 F->getBasicBlockList().insert(It, copy0MBB);
4397 F->getBasicBlockList().insert(It, sinkMBB);
4398 // Update machine-CFG edges by first adding all successors of the current
4399 // block to the new block which will contain the Phi node for the select.
4400 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4401 e = BB->succ_end(); i != e; ++i)
4402 sinkMBB->addSuccessor(*i);
4403 // Next, remove all successors of the current block, and add the true
4404 // and fallthrough blocks as its successors.
4405 while(!BB->succ_empty())
4406 BB->removeSuccessor(BB->succ_begin());
4407 BB->addSuccessor(copy0MBB);
4408 BB->addSuccessor(sinkMBB);
4411 // %FalseValue = ...
4412 // # fallthrough to sinkMBB
4415 // Update machine-CFG edges
4416 BB->addSuccessor(sinkMBB);
4419 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4422 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4423 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4424 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4426 delete MI; // The pseudo instruction is gone now.
4430 case X86::FP_TO_INT16_IN_MEM:
4431 case X86::FP_TO_INT32_IN_MEM:
4432 case X86::FP_TO_INT64_IN_MEM: {
4433 // Change the floating point control register to use "round towards zero"
4434 // mode when truncating to an integer value.
4435 MachineFunction *F = BB->getParent();
4436 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4437 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4439 // Load the old value of the high byte of the control word...
4441 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4442 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4444 // Set the high part to be round to zero...
4445 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4448 // Reload the modified control word now...
4449 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4451 // Restore the memory image of control word to original value
4452 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4455 // Get the X86 opcode to use.
4457 switch (MI->getOpcode()) {
4458 default: assert(0 && "illegal opcode!");
4459 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
4460 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
4461 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
4465 MachineOperand &Op = MI->getOperand(0);
4466 if (Op.isRegister()) {
4467 AM.BaseType = X86AddressMode::RegBase;
4468 AM.Base.Reg = Op.getReg();
4470 AM.BaseType = X86AddressMode::FrameIndexBase;
4471 AM.Base.FrameIndex = Op.getFrameIndex();
4473 Op = MI->getOperand(1);
4474 if (Op.isImmediate())
4475 AM.Scale = Op.getImm();
4476 Op = MI->getOperand(2);
4477 if (Op.isImmediate())
4478 AM.IndexReg = Op.getImm();
4479 Op = MI->getOperand(3);
4480 if (Op.isGlobalAddress()) {
4481 AM.GV = Op.getGlobal();
4483 AM.Disp = Op.getImm();
4485 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4486 .addReg(MI->getOperand(4).getReg());
4488 // Reload the original control word now.
4489 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4491 delete MI; // The pseudo instruction is gone now.
4497 //===----------------------------------------------------------------------===//
4498 // X86 Optimization Hooks
4499 //===----------------------------------------------------------------------===//
4501 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4503 uint64_t &KnownZero,
4505 unsigned Depth) const {
4506 unsigned Opc = Op.getOpcode();
4507 assert((Opc >= ISD::BUILTIN_OP_END ||
4508 Opc == ISD::INTRINSIC_WO_CHAIN ||
4509 Opc == ISD::INTRINSIC_W_CHAIN ||
4510 Opc == ISD::INTRINSIC_VOID) &&
4511 "Should use MaskedValueIsZero if you don't know whether Op"
4512 " is a target node!");
4514 KnownZero = KnownOne = 0; // Don't know anything.
4518 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4523 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4524 /// element of the result of the vector shuffle.
4525 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4526 MVT::ValueType VT = N->getValueType(0);
4527 SDOperand PermMask = N->getOperand(2);
4528 unsigned NumElems = PermMask.getNumOperands();
4529 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4531 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4533 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
4534 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4535 SDOperand Idx = PermMask.getOperand(i);
4536 if (Idx.getOpcode() == ISD::UNDEF)
4537 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
4538 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4543 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4544 /// node is a GlobalAddress + an offset.
4545 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4546 unsigned Opc = N->getOpcode();
4547 if (Opc == X86ISD::Wrapper) {
4548 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4549 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4552 } else if (Opc == ISD::ADD) {
4553 SDOperand N1 = N->getOperand(0);
4554 SDOperand N2 = N->getOperand(1);
4555 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4556 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4558 Offset += V->getSignExtended();
4561 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4562 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4564 Offset += V->getSignExtended();
4572 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4574 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4575 MachineFrameInfo *MFI) {
4576 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4579 SDOperand Loc = N->getOperand(1);
4580 SDOperand BaseLoc = Base->getOperand(1);
4581 if (Loc.getOpcode() == ISD::FrameIndex) {
4582 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4584 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
4585 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4586 int FS = MFI->getObjectSize(FI);
4587 int BFS = MFI->getObjectSize(BFI);
4588 if (FS != BFS || FS != Size) return false;
4589 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4591 GlobalValue *GV1 = NULL;
4592 GlobalValue *GV2 = NULL;
4593 int64_t Offset1 = 0;
4594 int64_t Offset2 = 0;
4595 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4596 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4597 if (isGA1 && isGA2 && GV1 == GV2)
4598 return Offset1 == (Offset2 + Dist*Size);
4604 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4605 const X86Subtarget *Subtarget) {
4608 if (isGAPlusOffset(Base, GV, Offset))
4609 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4611 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4612 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
4614 // Fixed objects do not specify alignment, however the offsets are known.
4615 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4616 (MFI->getObjectOffset(BFI) % 16) == 0);
4618 return MFI->getObjectAlignment(BFI) >= 16;
4624 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4625 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4626 /// if the load addresses are consecutive, non-overlapping, and in the right
4628 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4629 const X86Subtarget *Subtarget) {
4630 MachineFunction &MF = DAG.getMachineFunction();
4631 MachineFrameInfo *MFI = MF.getFrameInfo();
4632 MVT::ValueType VT = N->getValueType(0);
4633 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4634 SDOperand PermMask = N->getOperand(2);
4635 int NumElems = (int)PermMask.getNumOperands();
4636 SDNode *Base = NULL;
4637 for (int i = 0; i < NumElems; ++i) {
4638 SDOperand Idx = PermMask.getOperand(i);
4639 if (Idx.getOpcode() == ISD::UNDEF) {
4640 if (!Base) return SDOperand();
4643 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4644 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4648 else if (!isConsecutiveLoad(Arg.Val, Base,
4649 i, MVT::getSizeInBits(EVT)/8,MFI))
4654 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4656 LoadSDNode *LD = cast<LoadSDNode>(Base);
4657 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4658 LD->getSrcValueOffset());
4660 // Just use movups, it's shorter.
4661 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
4662 SmallVector<SDOperand, 3> Ops;
4663 Ops.push_back(Base->getOperand(0));
4664 Ops.push_back(Base->getOperand(1));
4665 Ops.push_back(Base->getOperand(2));
4666 return DAG.getNode(ISD::BIT_CONVERT, VT,
4667 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
4671 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4672 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4673 const X86Subtarget *Subtarget) {
4674 SDOperand Cond = N->getOperand(0);
4676 // If we have SSE[12] support, try to form min/max nodes.
4677 if (Subtarget->hasSSE2() &&
4678 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4679 if (Cond.getOpcode() == ISD::SETCC) {
4680 // Get the LHS/RHS of the select.
4681 SDOperand LHS = N->getOperand(1);
4682 SDOperand RHS = N->getOperand(2);
4683 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4685 unsigned Opcode = 0;
4686 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4689 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4692 if (!UnsafeFPMath) break;
4694 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4696 Opcode = X86ISD::FMIN;
4699 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4702 if (!UnsafeFPMath) break;
4704 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4706 Opcode = X86ISD::FMAX;
4709 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4712 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4715 if (!UnsafeFPMath) break;
4717 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4719 Opcode = X86ISD::FMIN;
4722 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4725 if (!UnsafeFPMath) break;
4727 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4729 Opcode = X86ISD::FMAX;
4735 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4744 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4745 DAGCombinerInfo &DCI) const {
4746 SelectionDAG &DAG = DCI.DAG;
4747 switch (N->getOpcode()) {
4749 case ISD::VECTOR_SHUFFLE:
4750 return PerformShuffleCombine(N, DAG, Subtarget);
4752 return PerformSELECTCombine(N, DAG, Subtarget);
4758 //===----------------------------------------------------------------------===//
4759 // X86 Inline Assembly Support
4760 //===----------------------------------------------------------------------===//
4762 /// getConstraintType - Given a constraint letter, return the type of
4763 /// constraint it is for this target.
4764 X86TargetLowering::ConstraintType
4765 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
4766 if (Constraint.size() == 1) {
4767 switch (Constraint[0]) {
4776 return C_RegisterClass;
4781 return TargetLowering::getConstraintType(Constraint);
4784 /// isOperandValidForConstraint - Return the specified operand (possibly
4785 /// modified) if the specified SDOperand is valid for the specified target
4786 /// constraint letter, otherwise return null.
4787 SDOperand X86TargetLowering::
4788 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
4789 switch (Constraint) {
4792 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4793 if (C->getValue() <= 31)
4794 return DAG.getTargetConstant(C->getValue(), Op.getValueType());
4796 return SDOperand(0,0);
4798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4799 if (C->getValue() <= 255)
4800 return DAG.getTargetConstant(C->getValue(), Op.getValueType());
4802 return SDOperand(0,0);
4804 // Literal immediates are always ok.
4805 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op))
4806 return DAG.getTargetConstant(CST->getValue(), Op.getValueType());
4808 // If we are in non-pic codegen mode, we allow the address of a global (with
4809 // an optional displacement) to be used with 'i'.
4810 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
4813 // Match either (GA) or (GA+C)
4815 Offset = GA->getOffset();
4816 } else if (Op.getOpcode() == ISD::ADD) {
4817 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
4818 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
4820 Offset = GA->getOffset()+C->getValue();
4822 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
4823 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
4825 Offset = GA->getOffset()+C->getValue();
4832 // If addressing this global requires a load (e.g. in PIC mode), we can't
4834 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
4836 return SDOperand(0, 0);
4838 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4843 // Otherwise, not valid for this mode.
4844 return SDOperand(0, 0);
4847 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
4850 std::vector<unsigned> X86TargetLowering::
4851 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4852 MVT::ValueType VT) const {
4853 if (Constraint.size() == 1) {
4854 // FIXME: not handling fp-stack yet!
4855 switch (Constraint[0]) { // GCC X86 Constraint Letters
4856 default: break; // Unknown constraint letter
4857 case 'A': // EAX/EDX
4858 if (VT == MVT::i32 || VT == MVT::i64)
4859 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
4861 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
4864 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
4865 else if (VT == MVT::i16)
4866 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
4867 else if (VT == MVT::i8)
4868 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4873 return std::vector<unsigned>();
4876 std::pair<unsigned, const TargetRegisterClass*>
4877 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4878 MVT::ValueType VT) const {
4879 // First, see if this is a constraint that directly corresponds to an LLVM
4881 if (Constraint.size() == 1) {
4882 // GCC Constraint Letters
4883 switch (Constraint[0]) {
4885 case 'r': // GENERAL_REGS
4886 case 'R': // LEGACY_REGS
4887 case 'l': // INDEX_REGS
4888 if (VT == MVT::i64 && Subtarget->is64Bit())
4889 return std::make_pair(0U, X86::GR64RegisterClass);
4891 return std::make_pair(0U, X86::GR32RegisterClass);
4892 else if (VT == MVT::i16)
4893 return std::make_pair(0U, X86::GR16RegisterClass);
4894 else if (VT == MVT::i8)
4895 return std::make_pair(0U, X86::GR8RegisterClass);
4897 case 'y': // MMX_REGS if MMX allowed.
4898 if (!Subtarget->hasMMX()) break;
4899 return std::make_pair(0U, X86::VR64RegisterClass);
4901 case 'Y': // SSE_REGS if SSE2 allowed
4902 if (!Subtarget->hasSSE2()) break;
4904 case 'x': // SSE_REGS if SSE1 allowed
4905 if (!Subtarget->hasSSE1()) break;
4909 // Scalar SSE types.
4912 return std::make_pair(0U, X86::FR32RegisterClass);
4915 return std::make_pair(0U, X86::FR64RegisterClass);
4924 return std::make_pair(0U, X86::VR128RegisterClass);
4930 // Use the default implementation in TargetLowering to convert the register
4931 // constraint into a member of a register class.
4932 std::pair<unsigned, const TargetRegisterClass*> Res;
4933 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4935 // Not found as a standard register?
4936 if (Res.second == 0) {
4937 // GCC calls "st(0)" just plain "st".
4938 if (StringsEqualNoCase("{st}", Constraint)) {
4939 Res.first = X86::ST0;
4940 Res.second = X86::RSTRegisterClass;
4946 // Otherwise, check to see if this is a register class of the wrong value
4947 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
4948 // turn into {ax},{dx}.
4949 if (Res.second->hasType(VT))
4950 return Res; // Correct type already, nothing to do.
4952 // All of the single-register GCC register classes map their values onto
4953 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
4954 // really want an 8-bit or 32-bit register, map to the appropriate register
4955 // class and return the appropriate register.
4956 if (Res.second != X86::GR16RegisterClass)
4959 if (VT == MVT::i8) {
4960 unsigned DestReg = 0;
4961 switch (Res.first) {
4963 case X86::AX: DestReg = X86::AL; break;
4964 case X86::DX: DestReg = X86::DL; break;
4965 case X86::CX: DestReg = X86::CL; break;
4966 case X86::BX: DestReg = X86::BL; break;
4969 Res.first = DestReg;
4970 Res.second = Res.second = X86::GR8RegisterClass;
4972 } else if (VT == MVT::i32) {
4973 unsigned DestReg = 0;
4974 switch (Res.first) {
4976 case X86::AX: DestReg = X86::EAX; break;
4977 case X86::DX: DestReg = X86::EDX; break;
4978 case X86::CX: DestReg = X86::ECX; break;
4979 case X86::BX: DestReg = X86::EBX; break;
4980 case X86::SI: DestReg = X86::ESI; break;
4981 case X86::DI: DestReg = X86::EDI; break;
4982 case X86::BP: DestReg = X86::EBP; break;
4983 case X86::SP: DestReg = X86::ESP; break;
4986 Res.first = DestReg;
4987 Res.second = Res.second = X86::GR32RegisterClass;
4989 } else if (VT == MVT::i64) {
4990 unsigned DestReg = 0;
4991 switch (Res.first) {
4993 case X86::AX: DestReg = X86::RAX; break;
4994 case X86::DX: DestReg = X86::RDX; break;
4995 case X86::CX: DestReg = X86::RCX; break;
4996 case X86::BX: DestReg = X86::RBX; break;
4997 case X86::SI: DestReg = X86::RSI; break;
4998 case X86::DI: DestReg = X86::RDI; break;
4999 case X86::BP: DestReg = X86::RBP; break;
5000 case X86::SP: DestReg = X86::RSP; break;
5003 Res.first = DestReg;
5004 Res.second = Res.second = X86::GR64RegisterClass;