1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1201 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::f64, Legal);
1210 if (Subtarget->hasInt256()) {
1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1224 // Don't lower v32i8 because there is no 128-bit byte mul
1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1243 // Don't lower v32i8 because there is no 128-bit byte mul
1246 // In the customized shift lowering, the legal cases in AVX2 will be
1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1256 // Custom lower several nodes for 256-bit types.
1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType)i;
1261 // Extract subvector is special because the value type
1262 // (result) is 128-bit but the source is 256-bit wide.
1263 if (VT.is128BitVector())
1264 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1266 // Do not attempt to custom lower other non-256-bit vectors
1267 if (!VT.is256BitVector())
1270 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1281 MVT VT = (MVT::SimpleValueType)i;
1283 // Do not attempt to promote non-256-bit vectors
1284 if (!VT.is256BitVector())
1287 setOperationAction(ISD::AND, VT, Promote);
1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1289 setOperationAction(ISD::OR, VT, Promote);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1291 setOperationAction(ISD::XOR, VT, Promote);
1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1293 setOperationAction(ISD::LOAD, VT, Promote);
1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1295 setOperationAction(ISD::SELECT, VT, Promote);
1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1300 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1333 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1334 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1335 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1336 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1337 if (Subtarget->is64Bit()) {
1338 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1339 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1340 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1341 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1343 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1344 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1345 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1346 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1347 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1348 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1349 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1350 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1352 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1353 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1354 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1355 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1356 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1357 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1358 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1359 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1360 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1361 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1362 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1365 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1366 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1367 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1371 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1372 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1374 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1376 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1377 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1378 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1379 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1380 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1382 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1383 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1386 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1388 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1390 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1391 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1393 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1399 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1400 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1401 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1402 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1403 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1404 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1406 // Custom lower several nodes.
1407 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1408 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1409 MVT VT = (MVT::SimpleValueType)i;
1411 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1412 // Extract subvector is special because the value type
1413 // (result) is 256/128-bit but the source is 512-bit wide.
1414 if (VT.is128BitVector() || VT.is256BitVector())
1415 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1417 if (VT.getVectorElementType() == MVT::i1)
1418 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1420 // Do not attempt to custom lower other non-512-bit vectors
1421 if (!VT.is512BitVector())
1424 if ( EltSize >= 32) {
1425 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1426 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1427 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1428 setOperationAction(ISD::VSELECT, VT, Legal);
1429 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1430 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1431 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1434 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1435 MVT VT = (MVT::SimpleValueType)i;
1437 // Do not attempt to promote non-256-bit vectors
1438 if (!VT.is512BitVector())
1441 setOperationAction(ISD::SELECT, VT, Promote);
1442 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1446 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1447 // of this type with custom code.
1448 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1449 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1450 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1454 // We want to custom lower some of our intrinsics.
1455 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1456 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1457 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1459 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1460 // handle type legalization for these operations here.
1462 // FIXME: We really should do custom legalization for addition and
1463 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1464 // than generic legalization for 64-bit multiplication-with-overflow, though.
1465 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1466 // Add/Sub/Mul with overflow operations are custom lowered.
1468 setOperationAction(ISD::SADDO, VT, Custom);
1469 setOperationAction(ISD::UADDO, VT, Custom);
1470 setOperationAction(ISD::SSUBO, VT, Custom);
1471 setOperationAction(ISD::USUBO, VT, Custom);
1472 setOperationAction(ISD::SMULO, VT, Custom);
1473 setOperationAction(ISD::UMULO, VT, Custom);
1476 // There are no 8-bit 3-address imul/mul instructions
1477 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1478 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1480 if (!Subtarget->is64Bit()) {
1481 // These libcalls are not available in 32-bit.
1482 setLibcallName(RTLIB::SHL_I128, 0);
1483 setLibcallName(RTLIB::SRL_I128, 0);
1484 setLibcallName(RTLIB::SRA_I128, 0);
1487 // Combine sin / cos into one node or libcall if possible.
1488 if (Subtarget->hasSinCos()) {
1489 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1490 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1491 if (Subtarget->isTargetDarwin()) {
1492 // For MacOSX, we don't want to the normal expansion of a libcall to
1493 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1495 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1496 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1500 // We have target-specific dag combine patterns for the following nodes:
1501 setTargetDAGCombine(ISD::CONCAT_VECTORS);
1502 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1503 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1504 setTargetDAGCombine(ISD::VSELECT);
1505 setTargetDAGCombine(ISD::SELECT);
1506 setTargetDAGCombine(ISD::SHL);
1507 setTargetDAGCombine(ISD::SRA);
1508 setTargetDAGCombine(ISD::SRL);
1509 setTargetDAGCombine(ISD::OR);
1510 setTargetDAGCombine(ISD::AND);
1511 setTargetDAGCombine(ISD::ADD);
1512 setTargetDAGCombine(ISD::FADD);
1513 setTargetDAGCombine(ISD::FSUB);
1514 setTargetDAGCombine(ISD::FMA);
1515 setTargetDAGCombine(ISD::SUB);
1516 setTargetDAGCombine(ISD::LOAD);
1517 setTargetDAGCombine(ISD::STORE);
1518 setTargetDAGCombine(ISD::ZERO_EXTEND);
1519 setTargetDAGCombine(ISD::ANY_EXTEND);
1520 setTargetDAGCombine(ISD::SIGN_EXTEND);
1521 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1522 setTargetDAGCombine(ISD::TRUNCATE);
1523 setTargetDAGCombine(ISD::SINT_TO_FP);
1524 setTargetDAGCombine(ISD::SETCC);
1525 if (Subtarget->is64Bit())
1526 setTargetDAGCombine(ISD::MUL);
1527 setTargetDAGCombine(ISD::XOR);
1529 computeRegisterProperties();
1531 // On Darwin, -Os means optimize for size without hurting performance,
1532 // do not reduce the limit.
1533 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1534 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1535 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1536 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1537 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1538 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1539 setPrefLoopAlignment(4); // 2^4 bytes.
1541 // Predictable cmov don't hurt on atom because it's in-order.
1542 PredictableSelectIsExpensive = !Subtarget->isAtom();
1544 setPrefFunctionAlignment(4); // 2^4 bytes.
1547 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1548 if (!VT.isVector()) return MVT::i8;
1549 return VT.changeVectorElementTypeToInteger();
1552 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1553 /// the desired ByVal argument alignment.
1554 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1557 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1558 if (VTy->getBitWidth() == 128)
1560 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1561 unsigned EltAlign = 0;
1562 getMaxByValAlign(ATy->getElementType(), EltAlign);
1563 if (EltAlign > MaxAlign)
1564 MaxAlign = EltAlign;
1565 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1566 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1567 unsigned EltAlign = 0;
1568 getMaxByValAlign(STy->getElementType(i), EltAlign);
1569 if (EltAlign > MaxAlign)
1570 MaxAlign = EltAlign;
1577 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1578 /// function arguments in the caller parameter area. For X86, aggregates
1579 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1580 /// are at 4-byte boundaries.
1581 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1582 if (Subtarget->is64Bit()) {
1583 // Max of 8 and alignment of type.
1584 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1591 if (Subtarget->hasSSE1())
1592 getMaxByValAlign(Ty, Align);
1596 /// getOptimalMemOpType - Returns the target specific optimal type for load
1597 /// and store operations as a result of memset, memcpy, and memmove
1598 /// lowering. If DstAlign is zero that means it's safe to destination
1599 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1600 /// means there isn't a need to check it against alignment requirement,
1601 /// probably because the source does not need to be loaded. If 'IsMemset' is
1602 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1603 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1604 /// source is constant so it does not need to be loaded.
1605 /// It returns EVT::Other if the type should be determined using generic
1606 /// target-independent logic.
1608 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1609 unsigned DstAlign, unsigned SrcAlign,
1610 bool IsMemset, bool ZeroMemset,
1612 MachineFunction &MF) const {
1613 const Function *F = MF.getFunction();
1614 if ((!IsMemset || ZeroMemset) &&
1615 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1616 Attribute::NoImplicitFloat)) {
1618 (Subtarget->isUnalignedMemAccessFast() ||
1619 ((DstAlign == 0 || DstAlign >= 16) &&
1620 (SrcAlign == 0 || SrcAlign >= 16)))) {
1622 if (Subtarget->hasInt256())
1624 if (Subtarget->hasFp256())
1627 if (Subtarget->hasSSE2())
1629 if (Subtarget->hasSSE1())
1631 } else if (!MemcpyStrSrc && Size >= 8 &&
1632 !Subtarget->is64Bit() &&
1633 Subtarget->hasSSE2()) {
1634 // Do not use f64 to lower memcpy if source is string constant. It's
1635 // better to use i32 to avoid the loads.
1639 if (Subtarget->is64Bit() && Size >= 8)
1644 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1646 return X86ScalarSSEf32;
1647 else if (VT == MVT::f64)
1648 return X86ScalarSSEf64;
1653 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1655 *Fast = Subtarget->isUnalignedMemAccessFast();
1659 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1660 /// current function. The returned value is a member of the
1661 /// MachineJumpTableInfo::JTEntryKind enum.
1662 unsigned X86TargetLowering::getJumpTableEncoding() const {
1663 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1665 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1666 Subtarget->isPICStyleGOT())
1667 return MachineJumpTableInfo::EK_Custom32;
1669 // Otherwise, use the normal jump table encoding heuristics.
1670 return TargetLowering::getJumpTableEncoding();
1674 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1675 const MachineBasicBlock *MBB,
1676 unsigned uid,MCContext &Ctx) const{
1677 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1678 Subtarget->isPICStyleGOT());
1679 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1681 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1682 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1685 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1687 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1688 SelectionDAG &DAG) const {
1689 if (!Subtarget->is64Bit())
1690 // This doesn't have SDLoc associated with it, but is not really the
1691 // same as a Register.
1692 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1696 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1697 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1699 const MCExpr *X86TargetLowering::
1700 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1701 MCContext &Ctx) const {
1702 // X86-64 uses RIP relative addressing based on the jump table label.
1703 if (Subtarget->isPICStyleRIPRel())
1704 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1706 // Otherwise, the reference is relative to the PIC base.
1707 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1710 // FIXME: Why this routine is here? Move to RegInfo!
1711 std::pair<const TargetRegisterClass*, uint8_t>
1712 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1713 const TargetRegisterClass *RRC = 0;
1715 switch (VT.SimpleTy) {
1717 return TargetLowering::findRepresentativeClass(VT);
1718 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1719 RRC = Subtarget->is64Bit() ?
1720 (const TargetRegisterClass*)&X86::GR64RegClass :
1721 (const TargetRegisterClass*)&X86::GR32RegClass;
1724 RRC = &X86::VR64RegClass;
1726 case MVT::f32: case MVT::f64:
1727 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1728 case MVT::v4f32: case MVT::v2f64:
1729 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1731 RRC = &X86::VR128RegClass;
1734 return std::make_pair(RRC, Cost);
1737 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1738 unsigned &Offset) const {
1739 if (!Subtarget->isTargetLinux())
1742 if (Subtarget->is64Bit()) {
1743 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1745 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1757 //===----------------------------------------------------------------------===//
1758 // Return Value Calling Convention Implementation
1759 //===----------------------------------------------------------------------===//
1761 #include "X86GenCallingConv.inc"
1764 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1765 MachineFunction &MF, bool isVarArg,
1766 const SmallVectorImpl<ISD::OutputArg> &Outs,
1767 LLVMContext &Context) const {
1768 SmallVector<CCValAssign, 16> RVLocs;
1769 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1771 return CCInfo.CheckReturn(Outs, RetCC_X86);
1775 X86TargetLowering::LowerReturn(SDValue Chain,
1776 CallingConv::ID CallConv, bool isVarArg,
1777 const SmallVectorImpl<ISD::OutputArg> &Outs,
1778 const SmallVectorImpl<SDValue> &OutVals,
1779 SDLoc dl, SelectionDAG &DAG) const {
1780 MachineFunction &MF = DAG.getMachineFunction();
1781 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1783 SmallVector<CCValAssign, 16> RVLocs;
1784 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1785 RVLocs, *DAG.getContext());
1786 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1789 SmallVector<SDValue, 6> RetOps;
1790 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1791 // Operand #1 = Bytes To Pop
1792 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1795 // Copy the result values into the output registers.
1796 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1797 CCValAssign &VA = RVLocs[i];
1798 assert(VA.isRegLoc() && "Can only return in registers!");
1799 SDValue ValToCopy = OutVals[i];
1800 EVT ValVT = ValToCopy.getValueType();
1802 // Promote values to the appropriate types
1803 if (VA.getLocInfo() == CCValAssign::SExt)
1804 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1805 else if (VA.getLocInfo() == CCValAssign::ZExt)
1806 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1807 else if (VA.getLocInfo() == CCValAssign::AExt)
1808 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1809 else if (VA.getLocInfo() == CCValAssign::BCvt)
1810 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1812 // If this is x86-64, and we disabled SSE, we can't return FP values,
1813 // or SSE or MMX vectors.
1814 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1815 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1816 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1817 report_fatal_error("SSE register return with SSE disabled");
1819 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1820 // llvm-gcc has never done it right and no one has noticed, so this
1821 // should be OK for now.
1822 if (ValVT == MVT::f64 &&
1823 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1824 report_fatal_error("SSE2 register return with SSE2 disabled");
1826 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1827 // the RET instruction and handled by the FP Stackifier.
1828 if (VA.getLocReg() == X86::ST0 ||
1829 VA.getLocReg() == X86::ST1) {
1830 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1831 // change the value to the FP stack register class.
1832 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1833 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1834 RetOps.push_back(ValToCopy);
1835 // Don't emit a copytoreg.
1839 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1840 // which is returned in RAX / RDX.
1841 if (Subtarget->is64Bit()) {
1842 if (ValVT == MVT::x86mmx) {
1843 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1844 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1845 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1847 // If we don't have SSE2 available, convert to v4f32 so the generated
1848 // register is legal.
1849 if (!Subtarget->hasSSE2())
1850 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1855 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1856 Flag = Chain.getValue(1);
1857 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1860 // The x86-64 ABIs require that for returning structs by value we copy
1861 // the sret argument into %rax/%eax (depending on ABI) for the return.
1862 // Win32 requires us to put the sret argument to %eax as well.
1863 // We saved the argument into a virtual register in the entry block,
1864 // so now we copy the value out and into %rax/%eax.
1865 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1866 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1867 MachineFunction &MF = DAG.getMachineFunction();
1868 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1869 unsigned Reg = FuncInfo->getSRetReturnReg();
1871 "SRetReturnReg should have been set in LowerFormalArguments().");
1872 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1875 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1876 X86::RAX : X86::EAX;
1877 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1878 Flag = Chain.getValue(1);
1880 // RAX/EAX now acts like a return value.
1881 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1884 RetOps[0] = Chain; // Update chain.
1886 // Add the flag if we have it.
1888 RetOps.push_back(Flag);
1890 return DAG.getNode(X86ISD::RET_FLAG, dl,
1891 MVT::Other, &RetOps[0], RetOps.size());
1894 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1895 if (N->getNumValues() != 1)
1897 if (!N->hasNUsesOfValue(1, 0))
1900 SDValue TCChain = Chain;
1901 SDNode *Copy = *N->use_begin();
1902 if (Copy->getOpcode() == ISD::CopyToReg) {
1903 // If the copy has a glue operand, we conservatively assume it isn't safe to
1904 // perform a tail call.
1905 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1907 TCChain = Copy->getOperand(0);
1908 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1911 bool HasRet = false;
1912 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1914 if (UI->getOpcode() != X86ISD::RET_FLAG)
1927 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1928 ISD::NodeType ExtendKind) const {
1930 // TODO: Is this also valid on 32-bit?
1931 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1932 ReturnMVT = MVT::i8;
1934 ReturnMVT = MVT::i32;
1936 MVT MinVT = getRegisterType(ReturnMVT);
1937 return VT.bitsLT(MinVT) ? MinVT : VT;
1940 /// LowerCallResult - Lower the result values of a call into the
1941 /// appropriate copies out of appropriate physical registers.
1944 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1945 CallingConv::ID CallConv, bool isVarArg,
1946 const SmallVectorImpl<ISD::InputArg> &Ins,
1947 SDLoc dl, SelectionDAG &DAG,
1948 SmallVectorImpl<SDValue> &InVals) const {
1950 // Assign locations to each value returned by this call.
1951 SmallVector<CCValAssign, 16> RVLocs;
1952 bool Is64Bit = Subtarget->is64Bit();
1953 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1954 getTargetMachine(), RVLocs, *DAG.getContext());
1955 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1957 // Copy all of the result registers out of their specified physreg.
1958 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1959 CCValAssign &VA = RVLocs[i];
1960 EVT CopyVT = VA.getValVT();
1962 // If this is x86-64, and we disabled SSE, we can't return FP values
1963 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1964 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1965 report_fatal_error("SSE register return with SSE disabled");
1970 // If this is a call to a function that returns an fp value on the floating
1971 // point stack, we must guarantee the value is popped from the stack, so
1972 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1973 // if the return value is not used. We use the FpPOP_RETVAL instruction
1975 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1976 // If we prefer to use the value in xmm registers, copy it out as f80 and
1977 // use a truncate to move it from fp stack reg to xmm reg.
1978 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1979 SDValue Ops[] = { Chain, InFlag };
1980 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1981 MVT::Other, MVT::Glue, Ops), 1);
1982 Val = Chain.getValue(0);
1984 // Round the f80 to the right size, which also moves it to the appropriate
1986 if (CopyVT != VA.getValVT())
1987 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1988 // This truncation won't change the value.
1989 DAG.getIntPtrConstant(1));
1991 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1992 CopyVT, InFlag).getValue(1);
1993 Val = Chain.getValue(0);
1995 InFlag = Chain.getValue(2);
1996 InVals.push_back(Val);
2002 //===----------------------------------------------------------------------===//
2003 // C & StdCall & Fast Calling Convention implementation
2004 //===----------------------------------------------------------------------===//
2005 // StdCall calling convention seems to be standard for many Windows' API
2006 // routines and around. It differs from C calling convention just a little:
2007 // callee should clean up the stack, not caller. Symbols should be also
2008 // decorated in some fancy way :) It doesn't support any vector arguments.
2009 // For info on fast calling convention see Fast Calling Convention (tail call)
2010 // implementation LowerX86_32FastCCCallTo.
2012 /// CallIsStructReturn - Determines whether a call uses struct return
2014 enum StructReturnType {
2019 static StructReturnType
2020 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2022 return NotStructReturn;
2024 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2025 if (!Flags.isSRet())
2026 return NotStructReturn;
2027 if (Flags.isInReg())
2028 return RegStructReturn;
2029 return StackStructReturn;
2032 /// ArgsAreStructReturn - Determines whether a function uses struct
2033 /// return semantics.
2034 static StructReturnType
2035 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2037 return NotStructReturn;
2039 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2040 if (!Flags.isSRet())
2041 return NotStructReturn;
2042 if (Flags.isInReg())
2043 return RegStructReturn;
2044 return StackStructReturn;
2047 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2048 /// by "Src" to address "Dst" with size and alignment information specified by
2049 /// the specific parameter attribute. The copy will be passed as a byval
2050 /// function parameter.
2052 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2053 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2055 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2057 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2058 /*isVolatile*/false, /*AlwaysInline=*/true,
2059 MachinePointerInfo(), MachinePointerInfo());
2062 /// IsTailCallConvention - Return true if the calling convention is one that
2063 /// supports tail call optimization.
2064 static bool IsTailCallConvention(CallingConv::ID CC) {
2065 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2066 CC == CallingConv::HiPE);
2069 /// \brief Return true if the calling convention is a C calling convention.
2070 static bool IsCCallConvention(CallingConv::ID CC) {
2071 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2072 CC == CallingConv::X86_64_SysV);
2075 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2076 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2080 CallingConv::ID CalleeCC = CS.getCallingConv();
2081 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2087 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2088 /// a tailcall target by changing its ABI.
2089 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2090 bool GuaranteedTailCallOpt) {
2091 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2095 X86TargetLowering::LowerMemArgument(SDValue Chain,
2096 CallingConv::ID CallConv,
2097 const SmallVectorImpl<ISD::InputArg> &Ins,
2098 SDLoc dl, SelectionDAG &DAG,
2099 const CCValAssign &VA,
2100 MachineFrameInfo *MFI,
2102 // Create the nodes corresponding to a load from this parameter slot.
2103 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2104 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2105 getTargetMachine().Options.GuaranteedTailCallOpt);
2106 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2109 // If value is passed by pointer we have address passed instead of the value
2111 if (VA.getLocInfo() == CCValAssign::Indirect)
2112 ValVT = VA.getLocVT();
2114 ValVT = VA.getValVT();
2116 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2117 // changed with more analysis.
2118 // In case of tail call optimization mark all arguments mutable. Since they
2119 // could be overwritten by lowering of arguments in case of a tail call.
2120 if (Flags.isByVal()) {
2121 unsigned Bytes = Flags.getByValSize();
2122 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2123 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2124 return DAG.getFrameIndex(FI, getPointerTy());
2126 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2127 VA.getLocMemOffset(), isImmutable);
2128 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2129 return DAG.getLoad(ValVT, dl, Chain, FIN,
2130 MachinePointerInfo::getFixedStack(FI),
2131 false, false, false, 0);
2136 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2137 CallingConv::ID CallConv,
2139 const SmallVectorImpl<ISD::InputArg> &Ins,
2142 SmallVectorImpl<SDValue> &InVals)
2144 MachineFunction &MF = DAG.getMachineFunction();
2145 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2147 const Function* Fn = MF.getFunction();
2148 if (Fn->hasExternalLinkage() &&
2149 Subtarget->isTargetCygMing() &&
2150 Fn->getName() == "main")
2151 FuncInfo->setForceFramePointer(true);
2153 MachineFrameInfo *MFI = MF.getFrameInfo();
2154 bool Is64Bit = Subtarget->is64Bit();
2155 bool IsWindows = Subtarget->isTargetWindows();
2156 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2158 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2159 "Var args not supported with calling convention fastcc, ghc or hipe");
2161 // Assign locations to all of the incoming arguments.
2162 SmallVector<CCValAssign, 16> ArgLocs;
2163 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2164 ArgLocs, *DAG.getContext());
2166 // Allocate shadow area for Win64
2168 CCInfo.AllocateStack(32, 8);
2170 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2172 unsigned LastVal = ~0U;
2174 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2175 CCValAssign &VA = ArgLocs[i];
2176 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2178 assert(VA.getValNo() != LastVal &&
2179 "Don't support value assigned to multiple locs yet");
2181 LastVal = VA.getValNo();
2183 if (VA.isRegLoc()) {
2184 EVT RegVT = VA.getLocVT();
2185 const TargetRegisterClass *RC;
2186 if (RegVT == MVT::i32)
2187 RC = &X86::GR32RegClass;
2188 else if (Is64Bit && RegVT == MVT::i64)
2189 RC = &X86::GR64RegClass;
2190 else if (RegVT == MVT::f32)
2191 RC = &X86::FR32RegClass;
2192 else if (RegVT == MVT::f64)
2193 RC = &X86::FR64RegClass;
2194 else if (RegVT.is512BitVector())
2195 RC = &X86::VR512RegClass;
2196 else if (RegVT.is256BitVector())
2197 RC = &X86::VR256RegClass;
2198 else if (RegVT.is128BitVector())
2199 RC = &X86::VR128RegClass;
2200 else if (RegVT == MVT::x86mmx)
2201 RC = &X86::VR64RegClass;
2202 else if (RegVT == MVT::v8i1)
2203 RC = &X86::VK8RegClass;
2204 else if (RegVT == MVT::v16i1)
2205 RC = &X86::VK16RegClass;
2207 llvm_unreachable("Unknown argument type!");
2209 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2210 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2212 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2213 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2215 if (VA.getLocInfo() == CCValAssign::SExt)
2216 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2217 DAG.getValueType(VA.getValVT()));
2218 else if (VA.getLocInfo() == CCValAssign::ZExt)
2219 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2220 DAG.getValueType(VA.getValVT()));
2221 else if (VA.getLocInfo() == CCValAssign::BCvt)
2222 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2224 if (VA.isExtInLoc()) {
2225 // Handle MMX values passed in XMM regs.
2226 if (RegVT.isVector())
2227 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2229 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2232 assert(VA.isMemLoc());
2233 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2236 // If value is passed via pointer - do a load.
2237 if (VA.getLocInfo() == CCValAssign::Indirect)
2238 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2239 MachinePointerInfo(), false, false, false, 0);
2241 InVals.push_back(ArgValue);
2244 // The x86-64 ABIs require that for returning structs by value we copy
2245 // the sret argument into %rax/%eax (depending on ABI) for the return.
2246 // Win32 requires us to put the sret argument to %eax as well.
2247 // Save the argument into a virtual register so that we can access it
2248 // from the return points.
2249 if (MF.getFunction()->hasStructRetAttr() &&
2250 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2251 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2252 unsigned Reg = FuncInfo->getSRetReturnReg();
2254 MVT PtrTy = getPointerTy();
2255 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2256 FuncInfo->setSRetReturnReg(Reg);
2258 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2259 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2262 unsigned StackSize = CCInfo.getNextStackOffset();
2263 // Align stack specially for tail calls.
2264 if (FuncIsMadeTailCallSafe(CallConv,
2265 MF.getTarget().Options.GuaranteedTailCallOpt))
2266 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2268 // If the function takes variable number of arguments, make a frame index for
2269 // the start of the first vararg value... for expansion of llvm.va_start.
2271 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2272 CallConv != CallingConv::X86_ThisCall)) {
2273 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2276 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2278 // FIXME: We should really autogenerate these arrays
2279 static const uint16_t GPR64ArgRegsWin64[] = {
2280 X86::RCX, X86::RDX, X86::R8, X86::R9
2282 static const uint16_t GPR64ArgRegs64Bit[] = {
2283 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2285 static const uint16_t XMMArgRegs64Bit[] = {
2286 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2287 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2289 const uint16_t *GPR64ArgRegs;
2290 unsigned NumXMMRegs = 0;
2293 // The XMM registers which might contain var arg parameters are shadowed
2294 // in their paired GPR. So we only need to save the GPR to their home
2296 TotalNumIntRegs = 4;
2297 GPR64ArgRegs = GPR64ArgRegsWin64;
2299 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2300 GPR64ArgRegs = GPR64ArgRegs64Bit;
2302 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2305 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2308 bool NoImplicitFloatOps = Fn->getAttributes().
2309 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2310 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2311 "SSE register cannot be used when SSE is disabled!");
2312 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2313 NoImplicitFloatOps) &&
2314 "SSE register cannot be used when SSE is disabled!");
2315 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2316 !Subtarget->hasSSE1())
2317 // Kernel mode asks for SSE to be disabled, so don't push them
2319 TotalNumXMMRegs = 0;
2322 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2323 // Get to the caller-allocated home save location. Add 8 to account
2324 // for the return address.
2325 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2326 FuncInfo->setRegSaveFrameIndex(
2327 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2328 // Fixup to set vararg frame on shadow area (4 x i64).
2330 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2332 // For X86-64, if there are vararg parameters that are passed via
2333 // registers, then we must store them to their spots on the stack so
2334 // they may be loaded by deferencing the result of va_next.
2335 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2336 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2337 FuncInfo->setRegSaveFrameIndex(
2338 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2342 // Store the integer parameter registers.
2343 SmallVector<SDValue, 8> MemOps;
2344 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2346 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2347 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2348 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2349 DAG.getIntPtrConstant(Offset));
2350 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2351 &X86::GR64RegClass);
2352 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2354 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2355 MachinePointerInfo::getFixedStack(
2356 FuncInfo->getRegSaveFrameIndex(), Offset),
2358 MemOps.push_back(Store);
2362 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2363 // Now store the XMM (fp + vector) parameter registers.
2364 SmallVector<SDValue, 11> SaveXMMOps;
2365 SaveXMMOps.push_back(Chain);
2367 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2368 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2369 SaveXMMOps.push_back(ALVal);
2371 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2372 FuncInfo->getRegSaveFrameIndex()));
2373 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2374 FuncInfo->getVarArgsFPOffset()));
2376 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2377 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2378 &X86::VR128RegClass);
2379 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2380 SaveXMMOps.push_back(Val);
2382 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2384 &SaveXMMOps[0], SaveXMMOps.size()));
2387 if (!MemOps.empty())
2388 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2389 &MemOps[0], MemOps.size());
2393 // Some CCs need callee pop.
2394 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2395 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2396 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2398 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2399 // If this is an sret function, the return should pop the hidden pointer.
2400 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2401 argsAreStructReturn(Ins) == StackStructReturn)
2402 FuncInfo->setBytesToPopOnReturn(4);
2406 // RegSaveFrameIndex is X86-64 only.
2407 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2408 if (CallConv == CallingConv::X86_FastCall ||
2409 CallConv == CallingConv::X86_ThisCall)
2410 // fastcc functions can't have varargs.
2411 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2414 FuncInfo->setArgumentStackSize(StackSize);
2420 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2421 SDValue StackPtr, SDValue Arg,
2422 SDLoc dl, SelectionDAG &DAG,
2423 const CCValAssign &VA,
2424 ISD::ArgFlagsTy Flags) const {
2425 unsigned LocMemOffset = VA.getLocMemOffset();
2426 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2427 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2428 if (Flags.isByVal())
2429 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2431 return DAG.getStore(Chain, dl, Arg, PtrOff,
2432 MachinePointerInfo::getStack(LocMemOffset),
2436 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2437 /// optimization is performed and it is required.
2439 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2440 SDValue &OutRetAddr, SDValue Chain,
2441 bool IsTailCall, bool Is64Bit,
2442 int FPDiff, SDLoc dl) const {
2443 // Adjust the Return address stack slot.
2444 EVT VT = getPointerTy();
2445 OutRetAddr = getReturnAddressFrameIndex(DAG);
2447 // Load the "old" Return address.
2448 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2449 false, false, false, 0);
2450 return SDValue(OutRetAddr.getNode(), 1);
2453 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2454 /// optimization is performed and it is required (FPDiff!=0).
2456 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2457 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2458 unsigned SlotSize, int FPDiff, SDLoc dl) {
2459 // Store the return address to the appropriate stack slot.
2460 if (!FPDiff) return Chain;
2461 // Calculate the new stack slot for the return address.
2462 int NewReturnAddrFI =
2463 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2465 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2466 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2467 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2473 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2474 SmallVectorImpl<SDValue> &InVals) const {
2475 SelectionDAG &DAG = CLI.DAG;
2477 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2478 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2479 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2480 SDValue Chain = CLI.Chain;
2481 SDValue Callee = CLI.Callee;
2482 CallingConv::ID CallConv = CLI.CallConv;
2483 bool &isTailCall = CLI.IsTailCall;
2484 bool isVarArg = CLI.IsVarArg;
2486 MachineFunction &MF = DAG.getMachineFunction();
2487 bool Is64Bit = Subtarget->is64Bit();
2488 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2489 bool IsWindows = Subtarget->isTargetWindows();
2490 StructReturnType SR = callIsStructReturn(Outs);
2491 bool IsSibcall = false;
2493 if (MF.getTarget().Options.DisableTailCalls)
2497 // Check if it's really possible to do a tail call.
2498 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2499 isVarArg, SR != NotStructReturn,
2500 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2501 Outs, OutVals, Ins, DAG);
2503 // Sibcalls are automatically detected tailcalls which do not require
2505 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2512 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2513 "Var args not supported with calling convention fastcc, ghc or hipe");
2515 // Analyze operands of the call, assigning locations to each operand.
2516 SmallVector<CCValAssign, 16> ArgLocs;
2517 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2518 ArgLocs, *DAG.getContext());
2520 // Allocate shadow area for Win64
2522 CCInfo.AllocateStack(32, 8);
2524 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2526 // Get a count of how many bytes are to be pushed on the stack.
2527 unsigned NumBytes = CCInfo.getNextStackOffset();
2529 // This is a sibcall. The memory operands are available in caller's
2530 // own caller's stack.
2532 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2533 IsTailCallConvention(CallConv))
2534 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2537 if (isTailCall && !IsSibcall) {
2538 // Lower arguments at fp - stackoffset + fpdiff.
2539 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2540 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2542 FPDiff = NumBytesCallerPushed - NumBytes;
2544 // Set the delta of movement of the returnaddr stackslot.
2545 // But only set if delta is greater than previous delta.
2546 if (FPDiff < X86Info->getTCReturnAddrDelta())
2547 X86Info->setTCReturnAddrDelta(FPDiff);
2551 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2554 SDValue RetAddrFrIdx;
2555 // Load return address for tail calls.
2556 if (isTailCall && FPDiff)
2557 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2558 Is64Bit, FPDiff, dl);
2560 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2561 SmallVector<SDValue, 8> MemOpChains;
2564 // Walk the register/memloc assignments, inserting copies/loads. In the case
2565 // of tail call optimization arguments are handle later.
2566 const X86RegisterInfo *RegInfo =
2567 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2568 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2569 CCValAssign &VA = ArgLocs[i];
2570 EVT RegVT = VA.getLocVT();
2571 SDValue Arg = OutVals[i];
2572 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2573 bool isByVal = Flags.isByVal();
2575 // Promote the value if needed.
2576 switch (VA.getLocInfo()) {
2577 default: llvm_unreachable("Unknown loc info!");
2578 case CCValAssign::Full: break;
2579 case CCValAssign::SExt:
2580 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2582 case CCValAssign::ZExt:
2583 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2585 case CCValAssign::AExt:
2586 if (RegVT.is128BitVector()) {
2587 // Special case: passing MMX values in XMM registers.
2588 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2589 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2590 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2592 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2594 case CCValAssign::BCvt:
2595 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2597 case CCValAssign::Indirect: {
2598 // Store the argument.
2599 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2600 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2601 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2602 MachinePointerInfo::getFixedStack(FI),
2609 if (VA.isRegLoc()) {
2610 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2611 if (isVarArg && IsWin64) {
2612 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2613 // shadow reg if callee is a varargs function.
2614 unsigned ShadowReg = 0;
2615 switch (VA.getLocReg()) {
2616 case X86::XMM0: ShadowReg = X86::RCX; break;
2617 case X86::XMM1: ShadowReg = X86::RDX; break;
2618 case X86::XMM2: ShadowReg = X86::R8; break;
2619 case X86::XMM3: ShadowReg = X86::R9; break;
2622 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2624 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2625 assert(VA.isMemLoc());
2626 if (StackPtr.getNode() == 0)
2627 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2629 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2630 dl, DAG, VA, Flags));
2634 if (!MemOpChains.empty())
2635 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2636 &MemOpChains[0], MemOpChains.size());
2638 if (Subtarget->isPICStyleGOT()) {
2639 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2642 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2643 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2645 // If we are tail calling and generating PIC/GOT style code load the
2646 // address of the callee into ECX. The value in ecx is used as target of
2647 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2648 // for tail calls on PIC/GOT architectures. Normally we would just put the
2649 // address of GOT into ebx and then call target@PLT. But for tail calls
2650 // ebx would be restored (since ebx is callee saved) before jumping to the
2653 // Note: The actual moving to ECX is done further down.
2654 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2655 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2656 !G->getGlobal()->hasProtectedVisibility())
2657 Callee = LowerGlobalAddress(Callee, DAG);
2658 else if (isa<ExternalSymbolSDNode>(Callee))
2659 Callee = LowerExternalSymbol(Callee, DAG);
2663 if (Is64Bit && isVarArg && !IsWin64) {
2664 // From AMD64 ABI document:
2665 // For calls that may call functions that use varargs or stdargs
2666 // (prototype-less calls or calls to functions containing ellipsis (...) in
2667 // the declaration) %al is used as hidden argument to specify the number
2668 // of SSE registers used. The contents of %al do not need to match exactly
2669 // the number of registers, but must be an ubound on the number of SSE
2670 // registers used and is in the range 0 - 8 inclusive.
2672 // Count the number of XMM registers allocated.
2673 static const uint16_t XMMArgRegs[] = {
2674 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2675 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2677 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2678 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2679 && "SSE registers cannot be used when SSE is disabled");
2681 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2682 DAG.getConstant(NumXMMRegs, MVT::i8)));
2685 // For tail calls lower the arguments to the 'real' stack slot.
2687 // Force all the incoming stack arguments to be loaded from the stack
2688 // before any new outgoing arguments are stored to the stack, because the
2689 // outgoing stack slots may alias the incoming argument stack slots, and
2690 // the alias isn't otherwise explicit. This is slightly more conservative
2691 // than necessary, because it means that each store effectively depends
2692 // on every argument instead of just those arguments it would clobber.
2693 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2695 SmallVector<SDValue, 8> MemOpChains2;
2698 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2699 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2700 CCValAssign &VA = ArgLocs[i];
2703 assert(VA.isMemLoc());
2704 SDValue Arg = OutVals[i];
2705 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2706 // Create frame index.
2707 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2708 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2709 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2710 FIN = DAG.getFrameIndex(FI, getPointerTy());
2712 if (Flags.isByVal()) {
2713 // Copy relative to framepointer.
2714 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2715 if (StackPtr.getNode() == 0)
2716 StackPtr = DAG.getCopyFromReg(Chain, dl,
2717 RegInfo->getStackRegister(),
2719 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2721 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2725 // Store relative to framepointer.
2726 MemOpChains2.push_back(
2727 DAG.getStore(ArgChain, dl, Arg, FIN,
2728 MachinePointerInfo::getFixedStack(FI),
2734 if (!MemOpChains2.empty())
2735 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2736 &MemOpChains2[0], MemOpChains2.size());
2738 // Store the return address to the appropriate stack slot.
2739 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2740 getPointerTy(), RegInfo->getSlotSize(),
2744 // Build a sequence of copy-to-reg nodes chained together with token chain
2745 // and flag operands which copy the outgoing args into registers.
2747 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2748 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2749 RegsToPass[i].second, InFlag);
2750 InFlag = Chain.getValue(1);
2753 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2754 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2755 // In the 64-bit large code model, we have to make all calls
2756 // through a register, since the call instruction's 32-bit
2757 // pc-relative offset may not be large enough to hold the whole
2759 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2760 // If the callee is a GlobalAddress node (quite common, every direct call
2761 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2764 // We should use extra load for direct calls to dllimported functions in
2766 const GlobalValue *GV = G->getGlobal();
2767 if (!GV->hasDLLImportLinkage()) {
2768 unsigned char OpFlags = 0;
2769 bool ExtraLoad = false;
2770 unsigned WrapperKind = ISD::DELETED_NODE;
2772 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2773 // external symbols most go through the PLT in PIC mode. If the symbol
2774 // has hidden or protected visibility, or if it is static or local, then
2775 // we don't need to use the PLT - we can directly call it.
2776 if (Subtarget->isTargetELF() &&
2777 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2778 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2779 OpFlags = X86II::MO_PLT;
2780 } else if (Subtarget->isPICStyleStubAny() &&
2781 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2782 (!Subtarget->getTargetTriple().isMacOSX() ||
2783 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2784 // PC-relative references to external symbols should go through $stub,
2785 // unless we're building with the leopard linker or later, which
2786 // automatically synthesizes these stubs.
2787 OpFlags = X86II::MO_DARWIN_STUB;
2788 } else if (Subtarget->isPICStyleRIPRel() &&
2789 isa<Function>(GV) &&
2790 cast<Function>(GV)->getAttributes().
2791 hasAttribute(AttributeSet::FunctionIndex,
2792 Attribute::NonLazyBind)) {
2793 // If the function is marked as non-lazy, generate an indirect call
2794 // which loads from the GOT directly. This avoids runtime overhead
2795 // at the cost of eager binding (and one extra byte of encoding).
2796 OpFlags = X86II::MO_GOTPCREL;
2797 WrapperKind = X86ISD::WrapperRIP;
2801 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2802 G->getOffset(), OpFlags);
2804 // Add a wrapper if needed.
2805 if (WrapperKind != ISD::DELETED_NODE)
2806 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2807 // Add extra indirection if needed.
2809 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2810 MachinePointerInfo::getGOT(),
2811 false, false, false, 0);
2813 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2814 unsigned char OpFlags = 0;
2816 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2817 // external symbols should go through the PLT.
2818 if (Subtarget->isTargetELF() &&
2819 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2820 OpFlags = X86II::MO_PLT;
2821 } else if (Subtarget->isPICStyleStubAny() &&
2822 (!Subtarget->getTargetTriple().isMacOSX() ||
2823 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2824 // PC-relative references to external symbols should go through $stub,
2825 // unless we're building with the leopard linker or later, which
2826 // automatically synthesizes these stubs.
2827 OpFlags = X86II::MO_DARWIN_STUB;
2830 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2834 // Returns a chain & a flag for retval copy to use.
2835 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2836 SmallVector<SDValue, 8> Ops;
2838 if (!IsSibcall && isTailCall) {
2839 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2840 DAG.getIntPtrConstant(0, true), InFlag, dl);
2841 InFlag = Chain.getValue(1);
2844 Ops.push_back(Chain);
2845 Ops.push_back(Callee);
2848 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2850 // Add argument registers to the end of the list so that they are known live
2852 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2853 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2854 RegsToPass[i].second.getValueType()));
2856 // Add a register mask operand representing the call-preserved registers.
2857 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2858 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2859 assert(Mask && "Missing call preserved mask for calling convention");
2860 Ops.push_back(DAG.getRegisterMask(Mask));
2862 if (InFlag.getNode())
2863 Ops.push_back(InFlag);
2867 //// If this is the first return lowered for this function, add the regs
2868 //// to the liveout set for the function.
2869 // This isn't right, although it's probably harmless on x86; liveouts
2870 // should be computed from returns not tail calls. Consider a void
2871 // function making a tail call to a function returning int.
2872 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2875 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2876 InFlag = Chain.getValue(1);
2878 // Create the CALLSEQ_END node.
2879 unsigned NumBytesForCalleeToPush;
2880 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2881 getTargetMachine().Options.GuaranteedTailCallOpt))
2882 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2883 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2884 SR == StackStructReturn)
2885 // If this is a call to a struct-return function, the callee
2886 // pops the hidden struct pointer, so we have to push it back.
2887 // This is common for Darwin/X86, Linux & Mingw32 targets.
2888 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2889 NumBytesForCalleeToPush = 4;
2891 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2893 // Returns a flag for retval copy to use.
2895 Chain = DAG.getCALLSEQ_END(Chain,
2896 DAG.getIntPtrConstant(NumBytes, true),
2897 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2900 InFlag = Chain.getValue(1);
2903 // Handle result values, copying them out of physregs into vregs that we
2905 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2906 Ins, dl, DAG, InVals);
2909 //===----------------------------------------------------------------------===//
2910 // Fast Calling Convention (tail call) implementation
2911 //===----------------------------------------------------------------------===//
2913 // Like std call, callee cleans arguments, convention except that ECX is
2914 // reserved for storing the tail called function address. Only 2 registers are
2915 // free for argument passing (inreg). Tail call optimization is performed
2917 // * tailcallopt is enabled
2918 // * caller/callee are fastcc
2919 // On X86_64 architecture with GOT-style position independent code only local
2920 // (within module) calls are supported at the moment.
2921 // To keep the stack aligned according to platform abi the function
2922 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2923 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2924 // If a tail called function callee has more arguments than the caller the
2925 // caller needs to make sure that there is room to move the RETADDR to. This is
2926 // achieved by reserving an area the size of the argument delta right after the
2927 // original REtADDR, but before the saved framepointer or the spilled registers
2928 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2940 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2941 /// for a 16 byte align requirement.
2943 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2944 SelectionDAG& DAG) const {
2945 MachineFunction &MF = DAG.getMachineFunction();
2946 const TargetMachine &TM = MF.getTarget();
2947 const X86RegisterInfo *RegInfo =
2948 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2949 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2950 unsigned StackAlignment = TFI.getStackAlignment();
2951 uint64_t AlignMask = StackAlignment - 1;
2952 int64_t Offset = StackSize;
2953 unsigned SlotSize = RegInfo->getSlotSize();
2954 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2955 // Number smaller than 12 so just add the difference.
2956 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2958 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2959 Offset = ((~AlignMask) & Offset) + StackAlignment +
2960 (StackAlignment-SlotSize);
2965 /// MatchingStackOffset - Return true if the given stack call argument is
2966 /// already available in the same position (relatively) of the caller's
2967 /// incoming argument stack.
2969 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2970 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2971 const X86InstrInfo *TII) {
2972 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2974 if (Arg.getOpcode() == ISD::CopyFromReg) {
2975 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2976 if (!TargetRegisterInfo::isVirtualRegister(VR))
2978 MachineInstr *Def = MRI->getVRegDef(VR);
2981 if (!Flags.isByVal()) {
2982 if (!TII->isLoadFromStackSlot(Def, FI))
2985 unsigned Opcode = Def->getOpcode();
2986 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2987 Def->getOperand(1).isFI()) {
2988 FI = Def->getOperand(1).getIndex();
2989 Bytes = Flags.getByValSize();
2993 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2994 if (Flags.isByVal())
2995 // ByVal argument is passed in as a pointer but it's now being
2996 // dereferenced. e.g.
2997 // define @foo(%struct.X* %A) {
2998 // tail call @bar(%struct.X* byval %A)
3001 SDValue Ptr = Ld->getBasePtr();
3002 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3005 FI = FINode->getIndex();
3006 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3007 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3008 FI = FINode->getIndex();
3009 Bytes = Flags.getByValSize();
3013 assert(FI != INT_MAX);
3014 if (!MFI->isFixedObjectIndex(FI))
3016 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3019 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3020 /// for tail call optimization. Targets which want to do tail call
3021 /// optimization should implement this function.
3023 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3024 CallingConv::ID CalleeCC,
3026 bool isCalleeStructRet,
3027 bool isCallerStructRet,
3029 const SmallVectorImpl<ISD::OutputArg> &Outs,
3030 const SmallVectorImpl<SDValue> &OutVals,
3031 const SmallVectorImpl<ISD::InputArg> &Ins,
3032 SelectionDAG &DAG) const {
3033 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3036 // If -tailcallopt is specified, make fastcc functions tail-callable.
3037 const MachineFunction &MF = DAG.getMachineFunction();
3038 const Function *CallerF = MF.getFunction();
3040 // If the function return type is x86_fp80 and the callee return type is not,
3041 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3042 // perform a tailcall optimization here.
3043 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3046 CallingConv::ID CallerCC = CallerF->getCallingConv();
3047 bool CCMatch = CallerCC == CalleeCC;
3048 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3049 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3051 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3052 if (IsTailCallConvention(CalleeCC) && CCMatch)
3057 // Look for obvious safe cases to perform tail call optimization that do not
3058 // require ABI changes. This is what gcc calls sibcall.
3060 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3061 // emit a special epilogue.
3062 const X86RegisterInfo *RegInfo =
3063 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3064 if (RegInfo->needsStackRealignment(MF))
3067 // Also avoid sibcall optimization if either caller or callee uses struct
3068 // return semantics.
3069 if (isCalleeStructRet || isCallerStructRet)
3072 // An stdcall caller is expected to clean up its arguments; the callee
3073 // isn't going to do that.
3074 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3077 // Do not sibcall optimize vararg calls unless all arguments are passed via
3079 if (isVarArg && !Outs.empty()) {
3081 // Optimizing for varargs on Win64 is unlikely to be safe without
3082 // additional testing.
3083 if (IsCalleeWin64 || IsCallerWin64)
3086 SmallVector<CCValAssign, 16> ArgLocs;
3087 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3088 getTargetMachine(), ArgLocs, *DAG.getContext());
3090 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3091 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3092 if (!ArgLocs[i].isRegLoc())
3096 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3097 // stack. Therefore, if it's not used by the call it is not safe to optimize
3098 // this into a sibcall.
3099 bool Unused = false;
3100 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3107 SmallVector<CCValAssign, 16> RVLocs;
3108 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3109 getTargetMachine(), RVLocs, *DAG.getContext());
3110 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3111 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3112 CCValAssign &VA = RVLocs[i];
3113 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3118 // If the calling conventions do not match, then we'd better make sure the
3119 // results are returned in the same way as what the caller expects.
3121 SmallVector<CCValAssign, 16> RVLocs1;
3122 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3123 getTargetMachine(), RVLocs1, *DAG.getContext());
3124 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3126 SmallVector<CCValAssign, 16> RVLocs2;
3127 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3128 getTargetMachine(), RVLocs2, *DAG.getContext());
3129 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3131 if (RVLocs1.size() != RVLocs2.size())
3133 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3134 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3136 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3138 if (RVLocs1[i].isRegLoc()) {
3139 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3142 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3148 // If the callee takes no arguments then go on to check the results of the
3150 if (!Outs.empty()) {
3151 // Check if stack adjustment is needed. For now, do not do this if any
3152 // argument is passed on the stack.
3153 SmallVector<CCValAssign, 16> ArgLocs;
3154 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3155 getTargetMachine(), ArgLocs, *DAG.getContext());
3157 // Allocate shadow area for Win64
3159 CCInfo.AllocateStack(32, 8);
3161 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3162 if (CCInfo.getNextStackOffset()) {
3163 MachineFunction &MF = DAG.getMachineFunction();
3164 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3167 // Check if the arguments are already laid out in the right way as
3168 // the caller's fixed stack objects.
3169 MachineFrameInfo *MFI = MF.getFrameInfo();
3170 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3171 const X86InstrInfo *TII =
3172 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3173 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3174 CCValAssign &VA = ArgLocs[i];
3175 SDValue Arg = OutVals[i];
3176 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3177 if (VA.getLocInfo() == CCValAssign::Indirect)
3179 if (!VA.isRegLoc()) {
3180 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3187 // If the tailcall address may be in a register, then make sure it's
3188 // possible to register allocate for it. In 32-bit, the call address can
3189 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3190 // callee-saved registers are restored. These happen to be the same
3191 // registers used to pass 'inreg' arguments so watch out for those.
3192 if (!Subtarget->is64Bit() &&
3193 ((!isa<GlobalAddressSDNode>(Callee) &&
3194 !isa<ExternalSymbolSDNode>(Callee)) ||
3195 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3196 unsigned NumInRegs = 0;
3197 // In PIC we need an extra register to formulate the address computation
3199 unsigned MaxInRegs =
3200 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3202 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3203 CCValAssign &VA = ArgLocs[i];
3206 unsigned Reg = VA.getLocReg();
3209 case X86::EAX: case X86::EDX: case X86::ECX:
3210 if (++NumInRegs == MaxInRegs)
3222 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3223 const TargetLibraryInfo *libInfo) const {
3224 return X86::createFastISel(funcInfo, libInfo);
3227 //===----------------------------------------------------------------------===//
3228 // Other Lowering Hooks
3229 //===----------------------------------------------------------------------===//
3231 static bool MayFoldLoad(SDValue Op) {
3232 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3235 static bool MayFoldIntoStore(SDValue Op) {
3236 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3239 static bool isTargetShuffle(unsigned Opcode) {
3241 default: return false;
3242 case X86ISD::PSHUFD:
3243 case X86ISD::PSHUFHW:
3244 case X86ISD::PSHUFLW:
3246 case X86ISD::PALIGNR:
3247 case X86ISD::MOVLHPS:
3248 case X86ISD::MOVLHPD:
3249 case X86ISD::MOVHLPS:
3250 case X86ISD::MOVLPS:
3251 case X86ISD::MOVLPD:
3252 case X86ISD::MOVSHDUP:
3253 case X86ISD::MOVSLDUP:
3254 case X86ISD::MOVDDUP:
3257 case X86ISD::UNPCKL:
3258 case X86ISD::UNPCKH:
3259 case X86ISD::VPERMILP:
3260 case X86ISD::VPERM2X128:
3261 case X86ISD::VPERMI:
3266 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3267 SDValue V1, SelectionDAG &DAG) {
3269 default: llvm_unreachable("Unknown x86 shuffle node");
3270 case X86ISD::MOVSHDUP:
3271 case X86ISD::MOVSLDUP:
3272 case X86ISD::MOVDDUP:
3273 return DAG.getNode(Opc, dl, VT, V1);
3277 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3278 SDValue V1, unsigned TargetMask,
3279 SelectionDAG &DAG) {
3281 default: llvm_unreachable("Unknown x86 shuffle node");
3282 case X86ISD::PSHUFD:
3283 case X86ISD::PSHUFHW:
3284 case X86ISD::PSHUFLW:
3285 case X86ISD::VPERMILP:
3286 case X86ISD::VPERMI:
3287 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3291 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3292 SDValue V1, SDValue V2, unsigned TargetMask,
3293 SelectionDAG &DAG) {
3295 default: llvm_unreachable("Unknown x86 shuffle node");
3296 case X86ISD::PALIGNR:
3298 case X86ISD::VPERM2X128:
3299 return DAG.getNode(Opc, dl, VT, V1, V2,
3300 DAG.getConstant(TargetMask, MVT::i8));
3304 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3305 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3307 default: llvm_unreachable("Unknown x86 shuffle node");
3308 case X86ISD::MOVLHPS:
3309 case X86ISD::MOVLHPD:
3310 case X86ISD::MOVHLPS:
3311 case X86ISD::MOVLPS:
3312 case X86ISD::MOVLPD:
3315 case X86ISD::UNPCKL:
3316 case X86ISD::UNPCKH:
3317 return DAG.getNode(Opc, dl, VT, V1, V2);
3321 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3322 MachineFunction &MF = DAG.getMachineFunction();
3323 const X86RegisterInfo *RegInfo =
3324 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3325 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3326 int ReturnAddrIndex = FuncInfo->getRAIndex();
3328 if (ReturnAddrIndex == 0) {
3329 // Set up a frame object for the return address.
3330 unsigned SlotSize = RegInfo->getSlotSize();
3331 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3334 FuncInfo->setRAIndex(ReturnAddrIndex);
3337 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3340 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3341 bool hasSymbolicDisplacement) {
3342 // Offset should fit into 32 bit immediate field.
3343 if (!isInt<32>(Offset))
3346 // If we don't have a symbolic displacement - we don't have any extra
3348 if (!hasSymbolicDisplacement)
3351 // FIXME: Some tweaks might be needed for medium code model.
3352 if (M != CodeModel::Small && M != CodeModel::Kernel)
3355 // For small code model we assume that latest object is 16MB before end of 31
3356 // bits boundary. We may also accept pretty large negative constants knowing
3357 // that all objects are in the positive half of address space.
3358 if (M == CodeModel::Small && Offset < 16*1024*1024)
3361 // For kernel code model we know that all object resist in the negative half
3362 // of 32bits address space. We may not accept negative offsets, since they may
3363 // be just off and we may accept pretty large positive ones.
3364 if (M == CodeModel::Kernel && Offset > 0)
3370 /// isCalleePop - Determines whether the callee is required to pop its
3371 /// own arguments. Callee pop is necessary to support tail calls.
3372 bool X86::isCalleePop(CallingConv::ID CallingConv,
3373 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3377 switch (CallingConv) {
3380 case CallingConv::X86_StdCall:
3382 case CallingConv::X86_FastCall:
3384 case CallingConv::X86_ThisCall:
3386 case CallingConv::Fast:
3388 case CallingConv::GHC:
3390 case CallingConv::HiPE:
3395 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3396 /// specific condition code, returning the condition code and the LHS/RHS of the
3397 /// comparison to make.
3398 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3399 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3401 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3402 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3403 // X > -1 -> X == 0, jump !sign.
3404 RHS = DAG.getConstant(0, RHS.getValueType());
3405 return X86::COND_NS;
3407 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3408 // X < 0 -> X == 0, jump on sign.
3411 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3413 RHS = DAG.getConstant(0, RHS.getValueType());
3414 return X86::COND_LE;
3418 switch (SetCCOpcode) {
3419 default: llvm_unreachable("Invalid integer condition!");
3420 case ISD::SETEQ: return X86::COND_E;
3421 case ISD::SETGT: return X86::COND_G;
3422 case ISD::SETGE: return X86::COND_GE;
3423 case ISD::SETLT: return X86::COND_L;
3424 case ISD::SETLE: return X86::COND_LE;
3425 case ISD::SETNE: return X86::COND_NE;
3426 case ISD::SETULT: return X86::COND_B;
3427 case ISD::SETUGT: return X86::COND_A;
3428 case ISD::SETULE: return X86::COND_BE;
3429 case ISD::SETUGE: return X86::COND_AE;
3433 // First determine if it is required or is profitable to flip the operands.
3435 // If LHS is a foldable load, but RHS is not, flip the condition.
3436 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3437 !ISD::isNON_EXTLoad(RHS.getNode())) {
3438 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3439 std::swap(LHS, RHS);
3442 switch (SetCCOpcode) {
3448 std::swap(LHS, RHS);
3452 // On a floating point condition, the flags are set as follows:
3454 // 0 | 0 | 0 | X > Y
3455 // 0 | 0 | 1 | X < Y
3456 // 1 | 0 | 0 | X == Y
3457 // 1 | 1 | 1 | unordered
3458 switch (SetCCOpcode) {
3459 default: llvm_unreachable("Condcode should be pre-legalized away");
3461 case ISD::SETEQ: return X86::COND_E;
3462 case ISD::SETOLT: // flipped
3464 case ISD::SETGT: return X86::COND_A;
3465 case ISD::SETOLE: // flipped
3467 case ISD::SETGE: return X86::COND_AE;
3468 case ISD::SETUGT: // flipped
3470 case ISD::SETLT: return X86::COND_B;
3471 case ISD::SETUGE: // flipped
3473 case ISD::SETLE: return X86::COND_BE;
3475 case ISD::SETNE: return X86::COND_NE;
3476 case ISD::SETUO: return X86::COND_P;
3477 case ISD::SETO: return X86::COND_NP;
3479 case ISD::SETUNE: return X86::COND_INVALID;
3483 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3484 /// code. Current x86 isa includes the following FP cmov instructions:
3485 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3486 static bool hasFPCMov(unsigned X86CC) {
3502 /// isFPImmLegal - Returns true if the target can instruction select the
3503 /// specified FP immediate natively. If false, the legalizer will
3504 /// materialize the FP immediate as a load from a constant pool.
3505 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3506 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3507 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3513 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3514 /// the specified range (L, H].
3515 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3516 return (Val < 0) || (Val >= Low && Val < Hi);
3519 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3520 /// specified value.
3521 static bool isUndefOrEqual(int Val, int CmpVal) {
3522 return (Val < 0 || Val == CmpVal);
3525 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3526 /// from position Pos and ending in Pos+Size, falls within the specified
3527 /// sequential range (L, L+Pos]. or is undef.
3528 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3529 unsigned Pos, unsigned Size, int Low) {
3530 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3531 if (!isUndefOrEqual(Mask[i], Low))
3536 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3537 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3538 /// the second operand.
3539 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3540 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3541 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3542 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3543 return (Mask[0] < 2 && Mask[1] < 2);
3547 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3548 /// is suitable for input to PSHUFHW.
3549 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3550 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3553 // Lower quadword copied in order or undef.
3554 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3557 // Upper quadword shuffled.
3558 for (unsigned i = 4; i != 8; ++i)
3559 if (!isUndefOrInRange(Mask[i], 4, 8))
3562 if (VT == MVT::v16i16) {
3563 // Lower quadword copied in order or undef.
3564 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3567 // Upper quadword shuffled.
3568 for (unsigned i = 12; i != 16; ++i)
3569 if (!isUndefOrInRange(Mask[i], 12, 16))
3576 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3577 /// is suitable for input to PSHUFLW.
3578 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3579 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3582 // Upper quadword copied in order.
3583 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3586 // Lower quadword shuffled.
3587 for (unsigned i = 0; i != 4; ++i)
3588 if (!isUndefOrInRange(Mask[i], 0, 4))
3591 if (VT == MVT::v16i16) {
3592 // Upper quadword copied in order.
3593 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3596 // Lower quadword shuffled.
3597 for (unsigned i = 8; i != 12; ++i)
3598 if (!isUndefOrInRange(Mask[i], 8, 12))
3605 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3606 /// is suitable for input to PALIGNR.
3607 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3608 const X86Subtarget *Subtarget) {
3609 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3610 (VT.is256BitVector() && !Subtarget->hasInt256()))
3613 unsigned NumElts = VT.getVectorNumElements();
3614 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3615 unsigned NumLaneElts = NumElts/NumLanes;
3617 // Do not handle 64-bit element shuffles with palignr.
3618 if (NumLaneElts == 2)
3621 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3623 for (i = 0; i != NumLaneElts; ++i) {
3628 // Lane is all undef, go to next lane
3629 if (i == NumLaneElts)
3632 int Start = Mask[i+l];
3634 // Make sure its in this lane in one of the sources
3635 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3636 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3639 // If not lane 0, then we must match lane 0
3640 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3643 // Correct second source to be contiguous with first source
3644 if (Start >= (int)NumElts)
3645 Start -= NumElts - NumLaneElts;
3647 // Make sure we're shifting in the right direction.
3648 if (Start <= (int)(i+l))
3653 // Check the rest of the elements to see if they are consecutive.
3654 for (++i; i != NumLaneElts; ++i) {
3655 int Idx = Mask[i+l];
3657 // Make sure its in this lane
3658 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3659 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3662 // If not lane 0, then we must match lane 0
3663 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3666 if (Idx >= (int)NumElts)
3667 Idx -= NumElts - NumLaneElts;
3669 if (!isUndefOrEqual(Idx, Start+i))
3678 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3679 /// the two vector operands have swapped position.
3680 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3681 unsigned NumElems) {
3682 for (unsigned i = 0; i != NumElems; ++i) {
3686 else if (idx < (int)NumElems)
3687 Mask[i] = idx + NumElems;
3689 Mask[i] = idx - NumElems;
3693 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3694 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3695 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3696 /// reverse of what x86 shuffles want.
3697 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3699 unsigned NumElems = VT.getVectorNumElements();
3700 unsigned NumLanes = VT.getSizeInBits()/128;
3701 unsigned NumLaneElems = NumElems/NumLanes;
3703 if (NumLaneElems != 2 && NumLaneElems != 4)
3706 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3707 bool symetricMaskRequired =
3708 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3710 // VSHUFPSY divides the resulting vector into 4 chunks.
3711 // The sources are also splitted into 4 chunks, and each destination
3712 // chunk must come from a different source chunk.
3714 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3715 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3717 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3718 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3720 // VSHUFPDY divides the resulting vector into 4 chunks.
3721 // The sources are also splitted into 4 chunks, and each destination
3722 // chunk must come from a different source chunk.
3724 // SRC1 => X3 X2 X1 X0
3725 // SRC2 => Y3 Y2 Y1 Y0
3727 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3729 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3730 unsigned HalfLaneElems = NumLaneElems/2;
3731 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3732 for (unsigned i = 0; i != NumLaneElems; ++i) {
3733 int Idx = Mask[i+l];
3734 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3735 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3737 // For VSHUFPSY, the mask of the second half must be the same as the
3738 // first but with the appropriate offsets. This works in the same way as
3739 // VPERMILPS works with masks.
3740 if (!symetricMaskRequired || Idx < 0)
3742 if (MaskVal[i] < 0) {
3743 MaskVal[i] = Idx - l;
3746 if ((signed)(Idx - l) != MaskVal[i])
3754 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3755 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3756 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3757 if (!VT.is128BitVector())
3760 unsigned NumElems = VT.getVectorNumElements();
3765 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3766 return isUndefOrEqual(Mask[0], 6) &&
3767 isUndefOrEqual(Mask[1], 7) &&
3768 isUndefOrEqual(Mask[2], 2) &&
3769 isUndefOrEqual(Mask[3], 3);
3772 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3773 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3775 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3776 if (!VT.is128BitVector())
3779 unsigned NumElems = VT.getVectorNumElements();
3784 return isUndefOrEqual(Mask[0], 2) &&
3785 isUndefOrEqual(Mask[1], 3) &&
3786 isUndefOrEqual(Mask[2], 2) &&
3787 isUndefOrEqual(Mask[3], 3);
3790 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3791 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3792 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3793 if (!VT.is128BitVector())
3796 unsigned NumElems = VT.getVectorNumElements();
3798 if (NumElems != 2 && NumElems != 4)
3801 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3802 if (!isUndefOrEqual(Mask[i], i + NumElems))
3805 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3806 if (!isUndefOrEqual(Mask[i], i))
3812 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3813 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3814 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3815 if (!VT.is128BitVector())
3818 unsigned NumElems = VT.getVectorNumElements();
3820 if (NumElems != 2 && NumElems != 4)
3823 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3824 if (!isUndefOrEqual(Mask[i], i))
3827 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3828 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3835 // Some special combinations that can be optimized.
3838 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3839 SelectionDAG &DAG) {
3840 MVT VT = SVOp->getSimpleValueType(0);
3843 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3846 ArrayRef<int> Mask = SVOp->getMask();
3848 // These are the special masks that may be optimized.
3849 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3850 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3851 bool MatchEvenMask = true;
3852 bool MatchOddMask = true;
3853 for (int i=0; i<8; ++i) {
3854 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3855 MatchEvenMask = false;
3856 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3857 MatchOddMask = false;
3860 if (!MatchEvenMask && !MatchOddMask)
3863 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3865 SDValue Op0 = SVOp->getOperand(0);
3866 SDValue Op1 = SVOp->getOperand(1);
3868 if (MatchEvenMask) {
3869 // Shift the second operand right to 32 bits.
3870 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3871 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3873 // Shift the first operand left to 32 bits.
3874 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3875 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3877 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3878 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3881 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3882 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3883 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3884 bool HasInt256, bool V2IsSplat = false) {
3886 assert(VT.getSizeInBits() >= 128 &&
3887 "Unsupported vector type for unpckl");
3889 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3891 unsigned NumOf256BitLanes;
3892 unsigned NumElts = VT.getVectorNumElements();
3893 if (VT.is256BitVector()) {
3894 if (NumElts != 4 && NumElts != 8 &&
3895 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3898 NumOf256BitLanes = 1;
3899 } else if (VT.is512BitVector()) {
3900 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3901 "Unsupported vector type for unpckh");
3903 NumOf256BitLanes = 2;
3906 NumOf256BitLanes = 1;
3909 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3910 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3912 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3913 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3914 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3915 int BitI = Mask[l256*NumEltsInStride+l+i];
3916 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3917 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3919 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3921 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3929 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3930 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3931 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3932 bool HasInt256, bool V2IsSplat = false) {
3933 assert(VT.getSizeInBits() >= 128 &&
3934 "Unsupported vector type for unpckh");
3936 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3938 unsigned NumOf256BitLanes;
3939 unsigned NumElts = VT.getVectorNumElements();
3940 if (VT.is256BitVector()) {
3941 if (NumElts != 4 && NumElts != 8 &&
3942 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3945 NumOf256BitLanes = 1;
3946 } else if (VT.is512BitVector()) {
3947 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3948 "Unsupported vector type for unpckh");
3950 NumOf256BitLanes = 2;
3953 NumOf256BitLanes = 1;
3956 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3957 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3959 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3960 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3961 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3962 int BitI = Mask[l256*NumEltsInStride+l+i];
3963 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3964 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3966 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3968 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3976 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3977 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3979 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3980 unsigned NumElts = VT.getVectorNumElements();
3981 bool Is256BitVec = VT.is256BitVector();
3983 if (VT.is512BitVector())
3985 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3986 "Unsupported vector type for unpckh");
3988 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3989 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3992 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3993 // FIXME: Need a better way to get rid of this, there's no latency difference
3994 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3995 // the former later. We should also remove the "_undef" special mask.
3996 if (NumElts == 4 && Is256BitVec)
3999 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4000 // independently on 128-bit lanes.
4001 unsigned NumLanes = VT.getSizeInBits()/128;
4002 unsigned NumLaneElts = NumElts/NumLanes;
4004 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4005 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4006 int BitI = Mask[l+i];
4007 int BitI1 = Mask[l+i+1];
4009 if (!isUndefOrEqual(BitI, j))
4011 if (!isUndefOrEqual(BitI1, j))
4019 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4020 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4022 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4023 unsigned NumElts = VT.getVectorNumElements();
4025 if (VT.is512BitVector())
4028 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4029 "Unsupported vector type for unpckh");
4031 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4032 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4035 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4036 // independently on 128-bit lanes.
4037 unsigned NumLanes = VT.getSizeInBits()/128;
4038 unsigned NumLaneElts = NumElts/NumLanes;
4040 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4041 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4042 int BitI = Mask[l+i];
4043 int BitI1 = Mask[l+i+1];
4044 if (!isUndefOrEqual(BitI, j))
4046 if (!isUndefOrEqual(BitI1, j))
4053 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4054 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4055 /// MOVSD, and MOVD, i.e. setting the lowest element.
4056 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4057 if (VT.getVectorElementType().getSizeInBits() < 32)
4059 if (!VT.is128BitVector())
4062 unsigned NumElts = VT.getVectorNumElements();
4064 if (!isUndefOrEqual(Mask[0], NumElts))
4067 for (unsigned i = 1; i != NumElts; ++i)
4068 if (!isUndefOrEqual(Mask[i], i))
4074 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4075 /// as permutations between 128-bit chunks or halves. As an example: this
4077 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4078 /// The first half comes from the second half of V1 and the second half from the
4079 /// the second half of V2.
4080 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4081 if (!HasFp256 || !VT.is256BitVector())
4084 // The shuffle result is divided into half A and half B. In total the two
4085 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4086 // B must come from C, D, E or F.
4087 unsigned HalfSize = VT.getVectorNumElements()/2;
4088 bool MatchA = false, MatchB = false;
4090 // Check if A comes from one of C, D, E, F.
4091 for (unsigned Half = 0; Half != 4; ++Half) {
4092 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4098 // Check if B comes from one of C, D, E, F.
4099 for (unsigned Half = 0; Half != 4; ++Half) {
4100 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4106 return MatchA && MatchB;
4109 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4110 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4111 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4112 MVT VT = SVOp->getSimpleValueType(0);
4114 unsigned HalfSize = VT.getVectorNumElements()/2;
4116 unsigned FstHalf = 0, SndHalf = 0;
4117 for (unsigned i = 0; i < HalfSize; ++i) {
4118 if (SVOp->getMaskElt(i) > 0) {
4119 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4123 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4124 if (SVOp->getMaskElt(i) > 0) {
4125 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4130 return (FstHalf | (SndHalf << 4));
4133 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4134 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4135 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4139 unsigned NumElts = VT.getVectorNumElements();
4141 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4142 for (unsigned i = 0; i != NumElts; ++i) {
4145 Imm8 |= Mask[i] << (i*2);
4150 unsigned LaneSize = 4;
4151 SmallVector<int, 4> MaskVal(LaneSize, -1);
4153 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4154 for (unsigned i = 0; i != LaneSize; ++i) {
4155 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4159 if (MaskVal[i] < 0) {
4160 MaskVal[i] = Mask[i+l] - l;
4161 Imm8 |= MaskVal[i] << (i*2);
4164 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4171 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4172 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4173 /// Note that VPERMIL mask matching is different depending whether theunderlying
4174 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4175 /// to the same elements of the low, but to the higher half of the source.
4176 /// In VPERMILPD the two lanes could be shuffled independently of each other
4177 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4178 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4179 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4180 if (VT.getSizeInBits() < 256 || EltSize < 32)
4182 bool symetricMaskRequired = (EltSize == 32);
4183 unsigned NumElts = VT.getVectorNumElements();
4185 unsigned NumLanes = VT.getSizeInBits()/128;
4186 unsigned LaneSize = NumElts/NumLanes;
4187 // 2 or 4 elements in one lane
4189 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4190 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4191 for (unsigned i = 0; i != LaneSize; ++i) {
4192 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4194 if (symetricMaskRequired) {
4195 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4196 ExpectedMaskVal[i] = Mask[i+l] - l;
4199 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4207 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4208 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4209 /// element of vector 2 and the other elements to come from vector 1 in order.
4210 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4211 bool V2IsSplat = false, bool V2IsUndef = false) {
4212 if (!VT.is128BitVector())
4215 unsigned NumOps = VT.getVectorNumElements();
4216 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4219 if (!isUndefOrEqual(Mask[0], 0))
4222 for (unsigned i = 1; i != NumOps; ++i)
4223 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4224 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4225 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4231 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4232 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4233 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4234 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4235 const X86Subtarget *Subtarget) {
4236 if (!Subtarget->hasSSE3())
4239 unsigned NumElems = VT.getVectorNumElements();
4241 if ((VT.is128BitVector() && NumElems != 4) ||
4242 (VT.is256BitVector() && NumElems != 8) ||
4243 (VT.is512BitVector() && NumElems != 16))
4246 // "i+1" is the value the indexed mask element must have
4247 for (unsigned i = 0; i != NumElems; i += 2)
4248 if (!isUndefOrEqual(Mask[i], i+1) ||
4249 !isUndefOrEqual(Mask[i+1], i+1))
4255 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4256 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4257 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4258 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4259 const X86Subtarget *Subtarget) {
4260 if (!Subtarget->hasSSE3())
4263 unsigned NumElems = VT.getVectorNumElements();
4265 if ((VT.is128BitVector() && NumElems != 4) ||
4266 (VT.is256BitVector() && NumElems != 8) ||
4267 (VT.is512BitVector() && NumElems != 16))
4270 // "i" is the value the indexed mask element must have
4271 for (unsigned i = 0; i != NumElems; i += 2)
4272 if (!isUndefOrEqual(Mask[i], i) ||
4273 !isUndefOrEqual(Mask[i+1], i))
4279 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4280 /// specifies a shuffle of elements that is suitable for input to 256-bit
4281 /// version of MOVDDUP.
4282 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4283 if (!HasFp256 || !VT.is256BitVector())
4286 unsigned NumElts = VT.getVectorNumElements();
4290 for (unsigned i = 0; i != NumElts/2; ++i)
4291 if (!isUndefOrEqual(Mask[i], 0))
4293 for (unsigned i = NumElts/2; i != NumElts; ++i)
4294 if (!isUndefOrEqual(Mask[i], NumElts/2))
4299 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4300 /// specifies a shuffle of elements that is suitable for input to 128-bit
4301 /// version of MOVDDUP.
4302 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4303 if (!VT.is128BitVector())
4306 unsigned e = VT.getVectorNumElements() / 2;
4307 for (unsigned i = 0; i != e; ++i)
4308 if (!isUndefOrEqual(Mask[i], i))
4310 for (unsigned i = 0; i != e; ++i)
4311 if (!isUndefOrEqual(Mask[e+i], i))
4316 /// isVEXTRACTIndex - Return true if the specified
4317 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4318 /// suitable for instruction that extract 128 or 256 bit vectors
4319 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4320 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4321 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4324 // The index should be aligned on a vecWidth-bit boundary.
4326 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4328 MVT VT = N->getSimpleValueType(0);
4329 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4330 bool Result = (Index * ElSize) % vecWidth == 0;
4335 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4336 /// operand specifies a subvector insert that is suitable for input to
4337 /// insertion of 128 or 256-bit subvectors
4338 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4339 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4340 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4342 // The index should be aligned on a vecWidth-bit boundary.
4344 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4346 MVT VT = N->getSimpleValueType(0);
4347 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4348 bool Result = (Index * ElSize) % vecWidth == 0;
4353 bool X86::isVINSERT128Index(SDNode *N) {
4354 return isVINSERTIndex(N, 128);
4357 bool X86::isVINSERT256Index(SDNode *N) {
4358 return isVINSERTIndex(N, 256);
4361 bool X86::isVEXTRACT128Index(SDNode *N) {
4362 return isVEXTRACTIndex(N, 128);
4365 bool X86::isVEXTRACT256Index(SDNode *N) {
4366 return isVEXTRACTIndex(N, 256);
4369 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4370 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4371 /// Handles 128-bit and 256-bit.
4372 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4373 MVT VT = N->getSimpleValueType(0);
4375 assert((VT.getSizeInBits() >= 128) &&
4376 "Unsupported vector type for PSHUF/SHUFP");
4378 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4379 // independently on 128-bit lanes.
4380 unsigned NumElts = VT.getVectorNumElements();
4381 unsigned NumLanes = VT.getSizeInBits()/128;
4382 unsigned NumLaneElts = NumElts/NumLanes;
4384 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4385 "Only supports 2, 4 or 8 elements per lane");
4387 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4389 for (unsigned i = 0; i != NumElts; ++i) {
4390 int Elt = N->getMaskElt(i);
4391 if (Elt < 0) continue;
4392 Elt &= NumLaneElts - 1;
4393 unsigned ShAmt = (i << Shift) % 8;
4394 Mask |= Elt << ShAmt;
4400 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4401 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4402 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4403 MVT VT = N->getSimpleValueType(0);
4405 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4406 "Unsupported vector type for PSHUFHW");
4408 unsigned NumElts = VT.getVectorNumElements();
4411 for (unsigned l = 0; l != NumElts; l += 8) {
4412 // 8 nodes per lane, but we only care about the last 4.
4413 for (unsigned i = 0; i < 4; ++i) {
4414 int Elt = N->getMaskElt(l+i+4);
4415 if (Elt < 0) continue;
4416 Elt &= 0x3; // only 2-bits.
4417 Mask |= Elt << (i * 2);
4424 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4425 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4426 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4427 MVT VT = N->getSimpleValueType(0);
4429 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4430 "Unsupported vector type for PSHUFHW");
4432 unsigned NumElts = VT.getVectorNumElements();
4435 for (unsigned l = 0; l != NumElts; l += 8) {
4436 // 8 nodes per lane, but we only care about the first 4.
4437 for (unsigned i = 0; i < 4; ++i) {
4438 int Elt = N->getMaskElt(l+i);
4439 if (Elt < 0) continue;
4440 Elt &= 0x3; // only 2-bits
4441 Mask |= Elt << (i * 2);
4448 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4449 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4450 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4451 MVT VT = SVOp->getSimpleValueType(0);
4452 unsigned EltSize = VT.is512BitVector() ? 1 :
4453 VT.getVectorElementType().getSizeInBits() >> 3;
4455 unsigned NumElts = VT.getVectorNumElements();
4456 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4457 unsigned NumLaneElts = NumElts/NumLanes;
4461 for (i = 0; i != NumElts; ++i) {
4462 Val = SVOp->getMaskElt(i);
4466 if (Val >= (int)NumElts)
4467 Val -= NumElts - NumLaneElts;
4469 assert(Val - i > 0 && "PALIGNR imm should be positive");
4470 return (Val - i) * EltSize;
4473 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4474 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4475 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4476 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4479 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4481 MVT VecVT = N->getOperand(0).getSimpleValueType();
4482 MVT ElVT = VecVT.getVectorElementType();
4484 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4485 return Index / NumElemsPerChunk;
4488 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4489 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4490 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4491 llvm_unreachable("Illegal insert subvector for VINSERT");
4494 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4496 MVT VecVT = N->getSimpleValueType(0);
4497 MVT ElVT = VecVT.getVectorElementType();
4499 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4500 return Index / NumElemsPerChunk;
4503 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4504 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4505 /// and VINSERTI128 instructions.
4506 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4507 return getExtractVEXTRACTImmediate(N, 128);
4510 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4511 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4512 /// and VINSERTI64x4 instructions.
4513 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4514 return getExtractVEXTRACTImmediate(N, 256);
4517 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4518 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4519 /// and VINSERTI128 instructions.
4520 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4521 return getInsertVINSERTImmediate(N, 128);
4524 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4525 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4526 /// and VINSERTI64x4 instructions.
4527 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4528 return getInsertVINSERTImmediate(N, 256);
4531 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4533 bool X86::isZeroNode(SDValue Elt) {
4534 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4535 return CN->isNullValue();
4536 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4537 return CFP->getValueAPF().isPosZero();
4541 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4542 /// their permute mask.
4543 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4544 SelectionDAG &DAG) {
4545 MVT VT = SVOp->getSimpleValueType(0);
4546 unsigned NumElems = VT.getVectorNumElements();
4547 SmallVector<int, 8> MaskVec;
4549 for (unsigned i = 0; i != NumElems; ++i) {
4550 int Idx = SVOp->getMaskElt(i);
4552 if (Idx < (int)NumElems)
4557 MaskVec.push_back(Idx);
4559 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4560 SVOp->getOperand(0), &MaskVec[0]);
4563 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4564 /// match movhlps. The lower half elements should come from upper half of
4565 /// V1 (and in order), and the upper half elements should come from the upper
4566 /// half of V2 (and in order).
4567 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4568 if (!VT.is128BitVector())
4570 if (VT.getVectorNumElements() != 4)
4572 for (unsigned i = 0, e = 2; i != e; ++i)
4573 if (!isUndefOrEqual(Mask[i], i+2))
4575 for (unsigned i = 2; i != 4; ++i)
4576 if (!isUndefOrEqual(Mask[i], i+4))
4581 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4582 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4584 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4585 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4587 N = N->getOperand(0).getNode();
4588 if (!ISD::isNON_EXTLoad(N))
4591 *LD = cast<LoadSDNode>(N);
4595 // Test whether the given value is a vector value which will be legalized
4597 static bool WillBeConstantPoolLoad(SDNode *N) {
4598 if (N->getOpcode() != ISD::BUILD_VECTOR)
4601 // Check for any non-constant elements.
4602 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4603 switch (N->getOperand(i).getNode()->getOpcode()) {
4605 case ISD::ConstantFP:
4612 // Vectors of all-zeros and all-ones are materialized with special
4613 // instructions rather than being loaded.
4614 return !ISD::isBuildVectorAllZeros(N) &&
4615 !ISD::isBuildVectorAllOnes(N);
4618 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4619 /// match movlp{s|d}. The lower half elements should come from lower half of
4620 /// V1 (and in order), and the upper half elements should come from the upper
4621 /// half of V2 (and in order). And since V1 will become the source of the
4622 /// MOVLP, it must be either a vector load or a scalar load to vector.
4623 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4624 ArrayRef<int> Mask, MVT VT) {
4625 if (!VT.is128BitVector())
4628 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4630 // Is V2 is a vector load, don't do this transformation. We will try to use
4631 // load folding shufps op.
4632 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4635 unsigned NumElems = VT.getVectorNumElements();
4637 if (NumElems != 2 && NumElems != 4)
4639 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4640 if (!isUndefOrEqual(Mask[i], i))
4642 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4643 if (!isUndefOrEqual(Mask[i], i+NumElems))
4648 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4650 static bool isSplatVector(SDNode *N) {
4651 if (N->getOpcode() != ISD::BUILD_VECTOR)
4654 SDValue SplatValue = N->getOperand(0);
4655 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4656 if (N->getOperand(i) != SplatValue)
4661 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4662 /// to an zero vector.
4663 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4664 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4665 SDValue V1 = N->getOperand(0);
4666 SDValue V2 = N->getOperand(1);
4667 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4668 for (unsigned i = 0; i != NumElems; ++i) {
4669 int Idx = N->getMaskElt(i);
4670 if (Idx >= (int)NumElems) {
4671 unsigned Opc = V2.getOpcode();
4672 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4674 if (Opc != ISD::BUILD_VECTOR ||
4675 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4677 } else if (Idx >= 0) {
4678 unsigned Opc = V1.getOpcode();
4679 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4681 if (Opc != ISD::BUILD_VECTOR ||
4682 !X86::isZeroNode(V1.getOperand(Idx)))
4689 /// getZeroVector - Returns a vector of specified type with all zero elements.
4691 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4692 SelectionDAG &DAG, SDLoc dl) {
4693 assert(VT.isVector() && "Expected a vector type");
4695 // Always build SSE zero vectors as <4 x i32> bitcasted
4696 // to their dest type. This ensures they get CSE'd.
4698 if (VT.is128BitVector()) { // SSE
4699 if (Subtarget->hasSSE2()) { // SSE2
4700 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4701 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4703 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4704 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4706 } else if (VT.is256BitVector()) { // AVX
4707 if (Subtarget->hasInt256()) { // AVX2
4708 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4709 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4710 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4711 array_lengthof(Ops));
4713 // 256-bit logic and arithmetic instructions in AVX are all
4714 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4715 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4716 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4717 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4718 array_lengthof(Ops));
4720 } else if (VT.is512BitVector()) { // AVX-512
4721 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4722 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4723 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4724 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4726 llvm_unreachable("Unexpected vector type");
4728 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4731 /// getOnesVector - Returns a vector of specified type with all bits set.
4732 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4733 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4734 /// Then bitcast to their original type, ensuring they get CSE'd.
4735 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4737 assert(VT.isVector() && "Expected a vector type");
4739 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4741 if (VT.is256BitVector()) {
4742 if (HasInt256) { // AVX2
4743 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4744 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4745 array_lengthof(Ops));
4747 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4748 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4750 } else if (VT.is128BitVector()) {
4751 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4753 llvm_unreachable("Unexpected vector type");
4755 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4758 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4759 /// that point to V2 points to its first element.
4760 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4761 for (unsigned i = 0; i != NumElems; ++i) {
4762 if (Mask[i] > (int)NumElems) {
4768 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4769 /// operation of specified width.
4770 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4772 unsigned NumElems = VT.getVectorNumElements();
4773 SmallVector<int, 8> Mask;
4774 Mask.push_back(NumElems);
4775 for (unsigned i = 1; i != NumElems; ++i)
4777 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4780 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4781 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4783 unsigned NumElems = VT.getVectorNumElements();
4784 SmallVector<int, 8> Mask;
4785 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4787 Mask.push_back(i + NumElems);
4789 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4792 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4793 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4795 unsigned NumElems = VT.getVectorNumElements();
4796 SmallVector<int, 8> Mask;
4797 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4798 Mask.push_back(i + Half);
4799 Mask.push_back(i + NumElems + Half);
4801 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4804 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4805 // a generic shuffle instruction because the target has no such instructions.
4806 // Generate shuffles which repeat i16 and i8 several times until they can be
4807 // represented by v4f32 and then be manipulated by target suported shuffles.
4808 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4809 MVT VT = V.getSimpleValueType();
4810 int NumElems = VT.getVectorNumElements();
4813 while (NumElems > 4) {
4814 if (EltNo < NumElems/2) {
4815 V = getUnpackl(DAG, dl, VT, V, V);
4817 V = getUnpackh(DAG, dl, VT, V, V);
4818 EltNo -= NumElems/2;
4825 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4826 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4827 MVT VT = V.getSimpleValueType();
4830 if (VT.is128BitVector()) {
4831 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4832 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4833 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4835 } else if (VT.is256BitVector()) {
4836 // To use VPERMILPS to splat scalars, the second half of indicies must
4837 // refer to the higher part, which is a duplication of the lower one,
4838 // because VPERMILPS can only handle in-lane permutations.
4839 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4840 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4842 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4843 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4846 llvm_unreachable("Vector size not supported");
4848 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4851 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4852 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4853 MVT SrcVT = SV->getSimpleValueType(0);
4854 SDValue V1 = SV->getOperand(0);
4857 int EltNo = SV->getSplatIndex();
4858 int NumElems = SrcVT.getVectorNumElements();
4859 bool Is256BitVec = SrcVT.is256BitVector();
4861 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4862 "Unknown how to promote splat for type");
4864 // Extract the 128-bit part containing the splat element and update
4865 // the splat element index when it refers to the higher register.
4867 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4868 if (EltNo >= NumElems/2)
4869 EltNo -= NumElems/2;
4872 // All i16 and i8 vector types can't be used directly by a generic shuffle
4873 // instruction because the target has no such instruction. Generate shuffles
4874 // which repeat i16 and i8 several times until they fit in i32, and then can
4875 // be manipulated by target suported shuffles.
4876 MVT EltVT = SrcVT.getVectorElementType();
4877 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4878 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4880 // Recreate the 256-bit vector and place the same 128-bit vector
4881 // into the low and high part. This is necessary because we want
4882 // to use VPERM* to shuffle the vectors
4884 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4887 return getLegalSplat(DAG, V1, EltNo);
4890 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4891 /// vector of zero or undef vector. This produces a shuffle where the low
4892 /// element of V2 is swizzled into the zero/undef vector, landing at element
4893 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4894 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4896 const X86Subtarget *Subtarget,
4897 SelectionDAG &DAG) {
4898 MVT VT = V2.getSimpleValueType();
4900 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4901 unsigned NumElems = VT.getVectorNumElements();
4902 SmallVector<int, 16> MaskVec;
4903 for (unsigned i = 0; i != NumElems; ++i)
4904 // If this is the insertion idx, put the low elt of V2 here.
4905 MaskVec.push_back(i == Idx ? NumElems : i);
4906 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4909 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4910 /// target specific opcode. Returns true if the Mask could be calculated.
4911 /// Sets IsUnary to true if only uses one source.
4912 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4913 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4914 unsigned NumElems = VT.getVectorNumElements();
4918 switch(N->getOpcode()) {
4920 ImmN = N->getOperand(N->getNumOperands()-1);
4921 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4923 case X86ISD::UNPCKH:
4924 DecodeUNPCKHMask(VT, Mask);
4926 case X86ISD::UNPCKL:
4927 DecodeUNPCKLMask(VT, Mask);
4929 case X86ISD::MOVHLPS:
4930 DecodeMOVHLPSMask(NumElems, Mask);
4932 case X86ISD::MOVLHPS:
4933 DecodeMOVLHPSMask(NumElems, Mask);
4935 case X86ISD::PALIGNR:
4936 ImmN = N->getOperand(N->getNumOperands()-1);
4937 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4939 case X86ISD::PSHUFD:
4940 case X86ISD::VPERMILP:
4941 ImmN = N->getOperand(N->getNumOperands()-1);
4942 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4945 case X86ISD::PSHUFHW:
4946 ImmN = N->getOperand(N->getNumOperands()-1);
4947 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4950 case X86ISD::PSHUFLW:
4951 ImmN = N->getOperand(N->getNumOperands()-1);
4952 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4955 case X86ISD::VPERMI:
4956 ImmN = N->getOperand(N->getNumOperands()-1);
4957 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4961 case X86ISD::MOVSD: {
4962 // The index 0 always comes from the first element of the second source,
4963 // this is why MOVSS and MOVSD are used in the first place. The other
4964 // elements come from the other positions of the first source vector
4965 Mask.push_back(NumElems);
4966 for (unsigned i = 1; i != NumElems; ++i) {
4971 case X86ISD::VPERM2X128:
4972 ImmN = N->getOperand(N->getNumOperands()-1);
4973 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4974 if (Mask.empty()) return false;
4976 case X86ISD::MOVDDUP:
4977 case X86ISD::MOVLHPD:
4978 case X86ISD::MOVLPD:
4979 case X86ISD::MOVLPS:
4980 case X86ISD::MOVSHDUP:
4981 case X86ISD::MOVSLDUP:
4982 // Not yet implemented
4984 default: llvm_unreachable("unknown target shuffle node");
4990 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4991 /// element of the result of the vector shuffle.
4992 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4995 return SDValue(); // Limit search depth.
4997 SDValue V = SDValue(N, 0);
4998 EVT VT = V.getValueType();
4999 unsigned Opcode = V.getOpcode();
5001 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5002 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5003 int Elt = SV->getMaskElt(Index);
5006 return DAG.getUNDEF(VT.getVectorElementType());
5008 unsigned NumElems = VT.getVectorNumElements();
5009 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5010 : SV->getOperand(1);
5011 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5014 // Recurse into target specific vector shuffles to find scalars.
5015 if (isTargetShuffle(Opcode)) {
5016 MVT ShufVT = V.getSimpleValueType();
5017 unsigned NumElems = ShufVT.getVectorNumElements();
5018 SmallVector<int, 16> ShuffleMask;
5021 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5024 int Elt = ShuffleMask[Index];
5026 return DAG.getUNDEF(ShufVT.getVectorElementType());
5028 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5030 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5034 // Actual nodes that may contain scalar elements
5035 if (Opcode == ISD::BITCAST) {
5036 V = V.getOperand(0);
5037 EVT SrcVT = V.getValueType();
5038 unsigned NumElems = VT.getVectorNumElements();
5040 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5044 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5045 return (Index == 0) ? V.getOperand(0)
5046 : DAG.getUNDEF(VT.getVectorElementType());
5048 if (V.getOpcode() == ISD::BUILD_VECTOR)
5049 return V.getOperand(Index);
5054 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5055 /// shuffle operation which come from a consecutively from a zero. The
5056 /// search can start in two different directions, from left or right.
5057 /// We count undefs as zeros until PreferredNum is reached.
5058 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5059 unsigned NumElems, bool ZerosFromLeft,
5061 unsigned PreferredNum = -1U) {
5062 unsigned NumZeros = 0;
5063 for (unsigned i = 0; i != NumElems; ++i) {
5064 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5065 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5069 if (X86::isZeroNode(Elt))
5071 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5072 NumZeros = std::min(NumZeros + 1, PreferredNum);
5080 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5081 /// correspond consecutively to elements from one of the vector operands,
5082 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5084 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5085 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5086 unsigned NumElems, unsigned &OpNum) {
5087 bool SeenV1 = false;
5088 bool SeenV2 = false;
5090 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5091 int Idx = SVOp->getMaskElt(i);
5092 // Ignore undef indicies
5096 if (Idx < (int)NumElems)
5101 // Only accept consecutive elements from the same vector
5102 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5106 OpNum = SeenV1 ? 0 : 1;
5110 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5111 /// logical left shift of a vector.
5112 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5113 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5115 SVOp->getSimpleValueType(0).getVectorNumElements();
5116 unsigned NumZeros = getNumOfConsecutiveZeros(
5117 SVOp, NumElems, false /* check zeros from right */, DAG,
5118 SVOp->getMaskElt(0));
5124 // Considering the elements in the mask that are not consecutive zeros,
5125 // check if they consecutively come from only one of the source vectors.
5127 // V1 = {X, A, B, C} 0
5129 // vector_shuffle V1, V2 <1, 2, 3, X>
5131 if (!isShuffleMaskConsecutive(SVOp,
5132 0, // Mask Start Index
5133 NumElems-NumZeros, // Mask End Index(exclusive)
5134 NumZeros, // Where to start looking in the src vector
5135 NumElems, // Number of elements in vector
5136 OpSrc)) // Which source operand ?
5141 ShVal = SVOp->getOperand(OpSrc);
5145 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5146 /// logical left shift of a vector.
5147 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5148 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5150 SVOp->getSimpleValueType(0).getVectorNumElements();
5151 unsigned NumZeros = getNumOfConsecutiveZeros(
5152 SVOp, NumElems, true /* check zeros from left */, DAG,
5153 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5159 // Considering the elements in the mask that are not consecutive zeros,
5160 // check if they consecutively come from only one of the source vectors.
5162 // 0 { A, B, X, X } = V2
5164 // vector_shuffle V1, V2 <X, X, 4, 5>
5166 if (!isShuffleMaskConsecutive(SVOp,
5167 NumZeros, // Mask Start Index
5168 NumElems, // Mask End Index(exclusive)
5169 0, // Where to start looking in the src vector
5170 NumElems, // Number of elements in vector
5171 OpSrc)) // Which source operand ?
5176 ShVal = SVOp->getOperand(OpSrc);
5180 /// isVectorShift - Returns true if the shuffle can be implemented as a
5181 /// logical left or right shift of a vector.
5182 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5183 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5184 // Although the logic below support any bitwidth size, there are no
5185 // shift instructions which handle more than 128-bit vectors.
5186 if (!SVOp->getSimpleValueType(0).is128BitVector())
5189 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5190 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5196 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5198 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5199 unsigned NumNonZero, unsigned NumZero,
5201 const X86Subtarget* Subtarget,
5202 const TargetLowering &TLI) {
5209 for (unsigned i = 0; i < 16; ++i) {
5210 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5211 if (ThisIsNonZero && First) {
5213 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5215 V = DAG.getUNDEF(MVT::v8i16);
5220 SDValue ThisElt(0, 0), LastElt(0, 0);
5221 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5222 if (LastIsNonZero) {
5223 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5224 MVT::i16, Op.getOperand(i-1));
5226 if (ThisIsNonZero) {
5227 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5228 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5229 ThisElt, DAG.getConstant(8, MVT::i8));
5231 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5235 if (ThisElt.getNode())
5236 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5237 DAG.getIntPtrConstant(i/2));
5241 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5244 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5246 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5247 unsigned NumNonZero, unsigned NumZero,
5249 const X86Subtarget* Subtarget,
5250 const TargetLowering &TLI) {
5257 for (unsigned i = 0; i < 8; ++i) {
5258 bool isNonZero = (NonZeros & (1 << i)) != 0;
5262 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5264 V = DAG.getUNDEF(MVT::v8i16);
5267 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5268 MVT::v8i16, V, Op.getOperand(i),
5269 DAG.getIntPtrConstant(i));
5276 /// getVShift - Return a vector logical shift node.
5278 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5279 unsigned NumBits, SelectionDAG &DAG,
5280 const TargetLowering &TLI, SDLoc dl) {
5281 assert(VT.is128BitVector() && "Unknown type for VShift");
5282 EVT ShVT = MVT::v2i64;
5283 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5284 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5285 return DAG.getNode(ISD::BITCAST, dl, VT,
5286 DAG.getNode(Opc, dl, ShVT, SrcOp,
5287 DAG.getConstant(NumBits,
5288 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5292 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5294 // Check if the scalar load can be widened into a vector load. And if
5295 // the address is "base + cst" see if the cst can be "absorbed" into
5296 // the shuffle mask.
5297 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5298 SDValue Ptr = LD->getBasePtr();
5299 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5301 EVT PVT = LD->getValueType(0);
5302 if (PVT != MVT::i32 && PVT != MVT::f32)
5307 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5308 FI = FINode->getIndex();
5310 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5311 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5312 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5313 Offset = Ptr.getConstantOperandVal(1);
5314 Ptr = Ptr.getOperand(0);
5319 // FIXME: 256-bit vector instructions don't require a strict alignment,
5320 // improve this code to support it better.
5321 unsigned RequiredAlign = VT.getSizeInBits()/8;
5322 SDValue Chain = LD->getChain();
5323 // Make sure the stack object alignment is at least 16 or 32.
5324 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5325 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5326 if (MFI->isFixedObjectIndex(FI)) {
5327 // Can't change the alignment. FIXME: It's possible to compute
5328 // the exact stack offset and reference FI + adjust offset instead.
5329 // If someone *really* cares about this. That's the way to implement it.
5332 MFI->setObjectAlignment(FI, RequiredAlign);
5336 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5337 // Ptr + (Offset & ~15).
5340 if ((Offset % RequiredAlign) & 3)
5342 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5344 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5345 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5347 int EltNo = (Offset - StartOffset) >> 2;
5348 unsigned NumElems = VT.getVectorNumElements();
5350 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5351 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5352 LD->getPointerInfo().getWithOffset(StartOffset),
5353 false, false, false, 0);
5355 SmallVector<int, 8> Mask;
5356 for (unsigned i = 0; i != NumElems; ++i)
5357 Mask.push_back(EltNo);
5359 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5365 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5366 /// vector of type 'VT', see if the elements can be replaced by a single large
5367 /// load which has the same value as a build_vector whose operands are 'elts'.
5369 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5371 /// FIXME: we'd also like to handle the case where the last elements are zero
5372 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5373 /// There's even a handy isZeroNode for that purpose.
5374 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5375 SDLoc &DL, SelectionDAG &DAG) {
5376 EVT EltVT = VT.getVectorElementType();
5377 unsigned NumElems = Elts.size();
5379 LoadSDNode *LDBase = NULL;
5380 unsigned LastLoadedElt = -1U;
5382 // For each element in the initializer, see if we've found a load or an undef.
5383 // If we don't find an initial load element, or later load elements are
5384 // non-consecutive, bail out.
5385 for (unsigned i = 0; i < NumElems; ++i) {
5386 SDValue Elt = Elts[i];
5388 if (!Elt.getNode() ||
5389 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5392 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5394 LDBase = cast<LoadSDNode>(Elt.getNode());
5398 if (Elt.getOpcode() == ISD::UNDEF)
5401 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5402 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5407 // If we have found an entire vector of loads and undefs, then return a large
5408 // load of the entire vector width starting at the base pointer. If we found
5409 // consecutive loads for the low half, generate a vzext_load node.
5410 if (LastLoadedElt == NumElems - 1) {
5411 SDValue NewLd = SDValue();
5412 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5413 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5414 LDBase->getPointerInfo(),
5415 LDBase->isVolatile(), LDBase->isNonTemporal(),
5416 LDBase->isInvariant(), 0);
5417 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5418 LDBase->getPointerInfo(),
5419 LDBase->isVolatile(), LDBase->isNonTemporal(),
5420 LDBase->isInvariant(), LDBase->getAlignment());
5422 if (LDBase->hasAnyUseOfValue(1)) {
5423 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5425 SDValue(NewLd.getNode(), 1));
5426 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5427 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5428 SDValue(NewLd.getNode(), 1));
5433 if (NumElems == 4 && LastLoadedElt == 1 &&
5434 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5435 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5436 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5438 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5439 array_lengthof(Ops), MVT::i64,
5440 LDBase->getPointerInfo(),
5441 LDBase->getAlignment(),
5442 false/*isVolatile*/, true/*ReadMem*/,
5445 // Make sure the newly-created LOAD is in the same position as LDBase in
5446 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5447 // update uses of LDBase's output chain to use the TokenFactor.
5448 if (LDBase->hasAnyUseOfValue(1)) {
5449 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5450 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5451 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5452 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5453 SDValue(ResNode.getNode(), 1));
5456 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5461 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5462 /// to generate a splat value for the following cases:
5463 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5464 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5465 /// a scalar load, or a constant.
5466 /// The VBROADCAST node is returned when a pattern is found,
5467 /// or SDValue() otherwise.
5468 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5469 SelectionDAG &DAG) {
5470 if (!Subtarget->hasFp256())
5473 MVT VT = Op.getSimpleValueType();
5476 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5477 "Unsupported vector type for broadcast.");
5482 switch (Op.getOpcode()) {
5484 // Unknown pattern found.
5487 case ISD::BUILD_VECTOR: {
5488 // The BUILD_VECTOR node must be a splat.
5489 if (!isSplatVector(Op.getNode()))
5492 Ld = Op.getOperand(0);
5493 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5494 Ld.getOpcode() == ISD::ConstantFP);
5496 // The suspected load node has several users. Make sure that all
5497 // of its users are from the BUILD_VECTOR node.
5498 // Constants may have multiple users.
5499 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5504 case ISD::VECTOR_SHUFFLE: {
5505 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5507 // Shuffles must have a splat mask where the first element is
5509 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5512 SDValue Sc = Op.getOperand(0);
5513 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5514 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5516 if (!Subtarget->hasInt256())
5519 // Use the register form of the broadcast instruction available on AVX2.
5520 if (VT.getSizeInBits() >= 256)
5521 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5522 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5525 Ld = Sc.getOperand(0);
5526 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5527 Ld.getOpcode() == ISD::ConstantFP);
5529 // The scalar_to_vector node and the suspected
5530 // load node must have exactly one user.
5531 // Constants may have multiple users.
5533 // AVX-512 has register version of the broadcast
5534 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5535 Ld.getValueType().getSizeInBits() >= 32;
5536 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5543 bool IsGE256 = (VT.getSizeInBits() >= 256);
5545 // Handle the broadcasting a single constant scalar from the constant pool
5546 // into a vector. On Sandybridge it is still better to load a constant vector
5547 // from the constant pool and not to broadcast it from a scalar.
5548 if (ConstSplatVal && Subtarget->hasInt256()) {
5549 EVT CVT = Ld.getValueType();
5550 assert(!CVT.isVector() && "Must not broadcast a vector type");
5551 unsigned ScalarSize = CVT.getSizeInBits();
5553 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5554 const Constant *C = 0;
5555 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5556 C = CI->getConstantIntValue();
5557 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5558 C = CF->getConstantFPValue();
5560 assert(C && "Invalid constant type");
5562 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5563 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5564 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5565 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5566 MachinePointerInfo::getConstantPool(),
5567 false, false, false, Alignment);
5569 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5573 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5574 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5576 // Handle AVX2 in-register broadcasts.
5577 if (!IsLoad && Subtarget->hasInt256() &&
5578 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5579 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5581 // The scalar source must be a normal load.
5585 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5586 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5588 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5589 // double since there is no vbroadcastsd xmm
5590 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5591 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5592 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5595 // Unsupported broadcast.
5599 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5600 MVT VT = Op.getSimpleValueType();
5602 // Skip if insert_vec_elt is not supported.
5603 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5604 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5608 unsigned NumElems = Op.getNumOperands();
5612 SmallVector<unsigned, 4> InsertIndices;
5613 SmallVector<int, 8> Mask(NumElems, -1);
5615 for (unsigned i = 0; i != NumElems; ++i) {
5616 unsigned Opc = Op.getOperand(i).getOpcode();
5618 if (Opc == ISD::UNDEF)
5621 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5622 // Quit if more than 1 elements need inserting.
5623 if (InsertIndices.size() > 1)
5626 InsertIndices.push_back(i);
5630 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5631 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5633 // Quit if extracted from vector of different type.
5634 if (ExtractedFromVec.getValueType() != VT)
5637 // Quit if non-constant index.
5638 if (!isa<ConstantSDNode>(ExtIdx))
5641 if (VecIn1.getNode() == 0)
5642 VecIn1 = ExtractedFromVec;
5643 else if (VecIn1 != ExtractedFromVec) {
5644 if (VecIn2.getNode() == 0)
5645 VecIn2 = ExtractedFromVec;
5646 else if (VecIn2 != ExtractedFromVec)
5647 // Quit if more than 2 vectors to shuffle
5651 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5653 if (ExtractedFromVec == VecIn1)
5655 else if (ExtractedFromVec == VecIn2)
5656 Mask[i] = Idx + NumElems;
5659 if (VecIn1.getNode() == 0)
5662 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5663 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5664 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5665 unsigned Idx = InsertIndices[i];
5666 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5667 DAG.getIntPtrConstant(Idx));
5673 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5675 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5677 MVT VT = Op.getSimpleValueType();
5678 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5679 "Unexpected type in LowerBUILD_VECTORvXi1!");
5682 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5683 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5684 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5685 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5686 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5687 Ops, VT.getVectorNumElements());
5690 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5691 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5692 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5693 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5694 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5695 Ops, VT.getVectorNumElements());
5698 bool AllContants = true;
5699 uint64_t Immediate = 0;
5700 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5701 SDValue In = Op.getOperand(idx);
5702 if (In.getOpcode() == ISD::UNDEF)
5704 if (!isa<ConstantSDNode>(In)) {
5705 AllContants = false;
5708 if (cast<ConstantSDNode>(In)->getZExtValue())
5709 Immediate |= (1ULL << idx);
5713 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5714 DAG.getConstant(Immediate, MVT::i16));
5715 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5716 DAG.getIntPtrConstant(0));
5719 // Splat vector (with undefs)
5720 SDValue In = Op.getOperand(0);
5721 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5722 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5723 llvm_unreachable("Unsupported predicate operation");
5726 SDValue EFLAGS, X86CC;
5727 if (In.getOpcode() == ISD::SETCC) {
5728 SDValue Op0 = In.getOperand(0);
5729 SDValue Op1 = In.getOperand(1);
5730 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5731 bool isFP = Op1.getValueType().isFloatingPoint();
5732 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5734 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5736 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5737 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5738 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5739 } else if (In.getOpcode() == X86ISD::SETCC) {
5740 X86CC = In.getOperand(0);
5741 EFLAGS = In.getOperand(1);
5750 // res = allOnes ### CMOVNE -1, %res
5753 MVT InVT = In.getSimpleValueType();
5754 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5755 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5756 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5759 if (VT == MVT::v16i1) {
5760 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5761 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5762 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5763 Cst0, Cst1, X86CC, EFLAGS);
5764 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5767 if (VT == MVT::v8i1) {
5768 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5769 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5770 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5771 Cst0, Cst1, X86CC, EFLAGS);
5772 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5773 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5775 llvm_unreachable("Unsupported predicate operation");
5779 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5782 MVT VT = Op.getSimpleValueType();
5783 MVT ExtVT = VT.getVectorElementType();
5784 unsigned NumElems = Op.getNumOperands();
5786 // Generate vectors for predicate vectors.
5787 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5788 return LowerBUILD_VECTORvXi1(Op, DAG);
5790 // Vectors containing all zeros can be matched by pxor and xorps later
5791 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5792 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5793 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5794 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5797 return getZeroVector(VT, Subtarget, DAG, dl);
5800 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5801 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5802 // vpcmpeqd on 256-bit vectors.
5803 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5804 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5807 if (!VT.is512BitVector())
5808 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5811 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5812 if (Broadcast.getNode())
5815 unsigned EVTBits = ExtVT.getSizeInBits();
5817 unsigned NumZero = 0;
5818 unsigned NumNonZero = 0;
5819 unsigned NonZeros = 0;
5820 bool IsAllConstants = true;
5821 SmallSet<SDValue, 8> Values;
5822 for (unsigned i = 0; i < NumElems; ++i) {
5823 SDValue Elt = Op.getOperand(i);
5824 if (Elt.getOpcode() == ISD::UNDEF)
5827 if (Elt.getOpcode() != ISD::Constant &&
5828 Elt.getOpcode() != ISD::ConstantFP)
5829 IsAllConstants = false;
5830 if (X86::isZeroNode(Elt))
5833 NonZeros |= (1 << i);
5838 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5839 if (NumNonZero == 0)
5840 return DAG.getUNDEF(VT);
5842 // Special case for single non-zero, non-undef, element.
5843 if (NumNonZero == 1) {
5844 unsigned Idx = countTrailingZeros(NonZeros);
5845 SDValue Item = Op.getOperand(Idx);
5847 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5848 // the value are obviously zero, truncate the value to i32 and do the
5849 // insertion that way. Only do this if the value is non-constant or if the
5850 // value is a constant being inserted into element 0. It is cheaper to do
5851 // a constant pool load than it is to do a movd + shuffle.
5852 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5853 (!IsAllConstants || Idx == 0)) {
5854 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5856 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5857 EVT VecVT = MVT::v4i32;
5858 unsigned VecElts = 4;
5860 // Truncate the value (which may itself be a constant) to i32, and
5861 // convert it to a vector with movd (S2V+shuffle to zero extend).
5862 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5863 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5864 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5866 // Now we have our 32-bit value zero extended in the low element of
5867 // a vector. If Idx != 0, swizzle it into place.
5869 SmallVector<int, 4> Mask;
5870 Mask.push_back(Idx);
5871 for (unsigned i = 1; i != VecElts; ++i)
5873 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5876 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5880 // If we have a constant or non-constant insertion into the low element of
5881 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5882 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5883 // depending on what the source datatype is.
5886 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5888 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5889 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5890 if (VT.is256BitVector() || VT.is512BitVector()) {
5891 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5892 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5893 Item, DAG.getIntPtrConstant(0));
5895 assert(VT.is128BitVector() && "Expected an SSE value type!");
5896 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5897 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5898 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5901 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5902 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5903 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5904 if (VT.is256BitVector()) {
5905 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5906 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5908 assert(VT.is128BitVector() && "Expected an SSE value type!");
5909 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5911 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5915 // Is it a vector logical left shift?
5916 if (NumElems == 2 && Idx == 1 &&
5917 X86::isZeroNode(Op.getOperand(0)) &&
5918 !X86::isZeroNode(Op.getOperand(1))) {
5919 unsigned NumBits = VT.getSizeInBits();
5920 return getVShift(true, VT,
5921 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5922 VT, Op.getOperand(1)),
5923 NumBits/2, DAG, *this, dl);
5926 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5929 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5930 // is a non-constant being inserted into an element other than the low one,
5931 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5932 // movd/movss) to move this into the low element, then shuffle it into
5934 if (EVTBits == 32) {
5935 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5937 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5938 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5939 SmallVector<int, 8> MaskVec;
5940 for (unsigned i = 0; i != NumElems; ++i)
5941 MaskVec.push_back(i == Idx ? 0 : 1);
5942 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5946 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5947 if (Values.size() == 1) {
5948 if (EVTBits == 32) {
5949 // Instead of a shuffle like this:
5950 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5951 // Check if it's possible to issue this instead.
5952 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5953 unsigned Idx = countTrailingZeros(NonZeros);
5954 SDValue Item = Op.getOperand(Idx);
5955 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5956 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5961 // A vector full of immediates; various special cases are already
5962 // handled, so this is best done with a single constant-pool load.
5966 // For AVX-length vectors, build the individual 128-bit pieces and use
5967 // shuffles to put them in place.
5968 if (VT.is256BitVector()) {
5969 SmallVector<SDValue, 32> V;
5970 for (unsigned i = 0; i != NumElems; ++i)
5971 V.push_back(Op.getOperand(i));
5973 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5975 // Build both the lower and upper subvector.
5976 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5977 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5980 // Recreate the wider vector with the lower and upper part.
5981 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5984 // Let legalizer expand 2-wide build_vectors.
5985 if (EVTBits == 64) {
5986 if (NumNonZero == 1) {
5987 // One half is zero or undef.
5988 unsigned Idx = countTrailingZeros(NonZeros);
5989 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5990 Op.getOperand(Idx));
5991 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5996 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5997 if (EVTBits == 8 && NumElems == 16) {
5998 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6000 if (V.getNode()) return V;
6003 if (EVTBits == 16 && NumElems == 8) {
6004 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6006 if (V.getNode()) return V;
6009 // If element VT is == 32 bits, turn it into a number of shuffles.
6010 SmallVector<SDValue, 8> V(NumElems);
6011 if (NumElems == 4 && NumZero > 0) {
6012 for (unsigned i = 0; i < 4; ++i) {
6013 bool isZero = !(NonZeros & (1 << i));
6015 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6017 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6020 for (unsigned i = 0; i < 2; ++i) {
6021 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6024 V[i] = V[i*2]; // Must be a zero vector.
6027 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6030 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6033 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6038 bool Reverse1 = (NonZeros & 0x3) == 2;
6039 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6043 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6044 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6046 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6049 if (Values.size() > 1 && VT.is128BitVector()) {
6050 // Check for a build vector of consecutive loads.
6051 for (unsigned i = 0; i < NumElems; ++i)
6052 V[i] = Op.getOperand(i);
6054 // Check for elements which are consecutive loads.
6055 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6059 // Check for a build vector from mostly shuffle plus few inserting.
6060 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6064 // For SSE 4.1, use insertps to put the high elements into the low element.
6065 if (getSubtarget()->hasSSE41()) {
6067 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6068 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6070 Result = DAG.getUNDEF(VT);
6072 for (unsigned i = 1; i < NumElems; ++i) {
6073 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6074 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6075 Op.getOperand(i), DAG.getIntPtrConstant(i));
6080 // Otherwise, expand into a number of unpckl*, start by extending each of
6081 // our (non-undef) elements to the full vector width with the element in the
6082 // bottom slot of the vector (which generates no code for SSE).
6083 for (unsigned i = 0; i < NumElems; ++i) {
6084 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6085 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6087 V[i] = DAG.getUNDEF(VT);
6090 // Next, we iteratively mix elements, e.g. for v4f32:
6091 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6092 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6093 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6094 unsigned EltStride = NumElems >> 1;
6095 while (EltStride != 0) {
6096 for (unsigned i = 0; i < EltStride; ++i) {
6097 // If V[i+EltStride] is undef and this is the first round of mixing,
6098 // then it is safe to just drop this shuffle: V[i] is already in the
6099 // right place, the one element (since it's the first round) being
6100 // inserted as undef can be dropped. This isn't safe for successive
6101 // rounds because they will permute elements within both vectors.
6102 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6103 EltStride == NumElems/2)
6106 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6115 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6116 // to create 256-bit vectors from two other 128-bit ones.
6117 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6119 MVT ResVT = Op.getSimpleValueType();
6121 assert((ResVT.is256BitVector() ||
6122 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6124 SDValue V1 = Op.getOperand(0);
6125 SDValue V2 = Op.getOperand(1);
6126 unsigned NumElems = ResVT.getVectorNumElements();
6127 if(ResVT.is256BitVector())
6128 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6130 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6134 assert(Op.getNumOperands() == 2);
6136 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6137 // from two other 128-bit ones.
6138 return LowerAVXCONCAT_VECTORS(Op, DAG);
6141 // Try to lower a shuffle node into a simple blend instruction.
6143 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6144 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6145 SDValue V1 = SVOp->getOperand(0);
6146 SDValue V2 = SVOp->getOperand(1);
6148 MVT VT = SVOp->getSimpleValueType(0);
6149 MVT EltVT = VT.getVectorElementType();
6150 unsigned NumElems = VT.getVectorNumElements();
6152 // There is no blend with immediate in AVX-512.
6153 if (VT.is512BitVector())
6156 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6158 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6161 // Check the mask for BLEND and build the value.
6162 unsigned MaskValue = 0;
6163 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6164 unsigned NumLanes = (NumElems-1)/8 + 1;
6165 unsigned NumElemsInLane = NumElems / NumLanes;
6167 // Blend for v16i16 should be symetric for the both lanes.
6168 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6170 int SndLaneEltIdx = (NumLanes == 2) ?
6171 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6172 int EltIdx = SVOp->getMaskElt(i);
6174 if ((EltIdx < 0 || EltIdx == (int)i) &&
6175 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6178 if (((unsigned)EltIdx == (i + NumElems)) &&
6179 (SndLaneEltIdx < 0 ||
6180 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6181 MaskValue |= (1<<i);
6186 // Convert i32 vectors to floating point if it is not AVX2.
6187 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6189 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6190 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6192 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6193 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6196 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6197 DAG.getConstant(MaskValue, MVT::i32));
6198 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6201 // v8i16 shuffles - Prefer shuffles in the following order:
6202 // 1. [all] pshuflw, pshufhw, optional move
6203 // 2. [ssse3] 1 x pshufb
6204 // 3. [ssse3] 2 x pshufb + 1 x por
6205 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6207 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6208 SelectionDAG &DAG) {
6209 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6210 SDValue V1 = SVOp->getOperand(0);
6211 SDValue V2 = SVOp->getOperand(1);
6213 SmallVector<int, 8> MaskVals;
6215 // Determine if more than 1 of the words in each of the low and high quadwords
6216 // of the result come from the same quadword of one of the two inputs. Undef
6217 // mask values count as coming from any quadword, for better codegen.
6218 unsigned LoQuad[] = { 0, 0, 0, 0 };
6219 unsigned HiQuad[] = { 0, 0, 0, 0 };
6220 std::bitset<4> InputQuads;
6221 for (unsigned i = 0; i < 8; ++i) {
6222 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6223 int EltIdx = SVOp->getMaskElt(i);
6224 MaskVals.push_back(EltIdx);
6233 InputQuads.set(EltIdx / 4);
6236 int BestLoQuad = -1;
6237 unsigned MaxQuad = 1;
6238 for (unsigned i = 0; i < 4; ++i) {
6239 if (LoQuad[i] > MaxQuad) {
6241 MaxQuad = LoQuad[i];
6245 int BestHiQuad = -1;
6247 for (unsigned i = 0; i < 4; ++i) {
6248 if (HiQuad[i] > MaxQuad) {
6250 MaxQuad = HiQuad[i];
6254 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6255 // of the two input vectors, shuffle them into one input vector so only a
6256 // single pshufb instruction is necessary. If There are more than 2 input
6257 // quads, disable the next transformation since it does not help SSSE3.
6258 bool V1Used = InputQuads[0] || InputQuads[1];
6259 bool V2Used = InputQuads[2] || InputQuads[3];
6260 if (Subtarget->hasSSSE3()) {
6261 if (InputQuads.count() == 2 && V1Used && V2Used) {
6262 BestLoQuad = InputQuads[0] ? 0 : 1;
6263 BestHiQuad = InputQuads[2] ? 2 : 3;
6265 if (InputQuads.count() > 2) {
6271 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6272 // the shuffle mask. If a quad is scored as -1, that means that it contains
6273 // words from all 4 input quadwords.
6275 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6277 BestLoQuad < 0 ? 0 : BestLoQuad,
6278 BestHiQuad < 0 ? 1 : BestHiQuad
6280 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6281 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6282 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6283 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6285 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6286 // source words for the shuffle, to aid later transformations.
6287 bool AllWordsInNewV = true;
6288 bool InOrder[2] = { true, true };
6289 for (unsigned i = 0; i != 8; ++i) {
6290 int idx = MaskVals[i];
6292 InOrder[i/4] = false;
6293 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6295 AllWordsInNewV = false;
6299 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6300 if (AllWordsInNewV) {
6301 for (int i = 0; i != 8; ++i) {
6302 int idx = MaskVals[i];
6305 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6306 if ((idx != i) && idx < 4)
6308 if ((idx != i) && idx > 3)
6317 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6318 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6319 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6320 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6321 unsigned TargetMask = 0;
6322 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6323 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6325 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6326 getShufflePSHUFLWImmediate(SVOp);
6327 V1 = NewV.getOperand(0);
6328 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6332 // Promote splats to a larger type which usually leads to more efficient code.
6333 // FIXME: Is this true if pshufb is available?
6334 if (SVOp->isSplat())
6335 return PromoteSplat(SVOp, DAG);
6337 // If we have SSSE3, and all words of the result are from 1 input vector,
6338 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6339 // is present, fall back to case 4.
6340 if (Subtarget->hasSSSE3()) {
6341 SmallVector<SDValue,16> pshufbMask;
6343 // If we have elements from both input vectors, set the high bit of the
6344 // shuffle mask element to zero out elements that come from V2 in the V1
6345 // mask, and elements that come from V1 in the V2 mask, so that the two
6346 // results can be OR'd together.
6347 bool TwoInputs = V1Used && V2Used;
6348 for (unsigned i = 0; i != 8; ++i) {
6349 int EltIdx = MaskVals[i] * 2;
6350 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6351 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6352 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6353 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6355 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6356 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6357 DAG.getNode(ISD::BUILD_VECTOR, dl,
6358 MVT::v16i8, &pshufbMask[0], 16));
6360 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6362 // Calculate the shuffle mask for the second input, shuffle it, and
6363 // OR it with the first shuffled input.
6365 for (unsigned i = 0; i != 8; ++i) {
6366 int EltIdx = MaskVals[i] * 2;
6367 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6368 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6369 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6370 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6372 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6373 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6374 DAG.getNode(ISD::BUILD_VECTOR, dl,
6375 MVT::v16i8, &pshufbMask[0], 16));
6376 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6377 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6380 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6381 // and update MaskVals with new element order.
6382 std::bitset<8> InOrder;
6383 if (BestLoQuad >= 0) {
6384 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6385 for (int i = 0; i != 4; ++i) {
6386 int idx = MaskVals[i];
6389 } else if ((idx / 4) == BestLoQuad) {
6394 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6397 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6399 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6401 getShufflePSHUFLWImmediate(SVOp), DAG);
6405 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6406 // and update MaskVals with the new element order.
6407 if (BestHiQuad >= 0) {
6408 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6409 for (unsigned i = 4; i != 8; ++i) {
6410 int idx = MaskVals[i];
6413 } else if ((idx / 4) == BestHiQuad) {
6414 MaskV[i] = (idx & 3) + 4;
6418 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6421 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6422 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6423 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6425 getShufflePSHUFHWImmediate(SVOp), DAG);
6429 // In case BestHi & BestLo were both -1, which means each quadword has a word
6430 // from each of the four input quadwords, calculate the InOrder bitvector now
6431 // before falling through to the insert/extract cleanup.
6432 if (BestLoQuad == -1 && BestHiQuad == -1) {
6434 for (int i = 0; i != 8; ++i)
6435 if (MaskVals[i] < 0 || MaskVals[i] == i)
6439 // The other elements are put in the right place using pextrw and pinsrw.
6440 for (unsigned i = 0; i != 8; ++i) {
6443 int EltIdx = MaskVals[i];
6446 SDValue ExtOp = (EltIdx < 8) ?
6447 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6448 DAG.getIntPtrConstant(EltIdx)) :
6449 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6450 DAG.getIntPtrConstant(EltIdx - 8));
6451 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6452 DAG.getIntPtrConstant(i));
6457 // v16i8 shuffles - Prefer shuffles in the following order:
6458 // 1. [ssse3] 1 x pshufb
6459 // 2. [ssse3] 2 x pshufb + 1 x por
6460 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6461 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6462 const X86Subtarget* Subtarget,
6463 SelectionDAG &DAG) {
6464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6465 SDValue V1 = SVOp->getOperand(0);
6466 SDValue V2 = SVOp->getOperand(1);
6468 ArrayRef<int> MaskVals = SVOp->getMask();
6470 // Promote splats to a larger type which usually leads to more efficient code.
6471 // FIXME: Is this true if pshufb is available?
6472 if (SVOp->isSplat())
6473 return PromoteSplat(SVOp, DAG);
6475 // If we have SSSE3, case 1 is generated when all result bytes come from
6476 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6477 // present, fall back to case 3.
6479 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6480 if (Subtarget->hasSSSE3()) {
6481 SmallVector<SDValue,16> pshufbMask;
6483 // If all result elements are from one input vector, then only translate
6484 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6486 // Otherwise, we have elements from both input vectors, and must zero out
6487 // elements that come from V2 in the first mask, and V1 in the second mask
6488 // so that we can OR them together.
6489 for (unsigned i = 0; i != 16; ++i) {
6490 int EltIdx = MaskVals[i];
6491 if (EltIdx < 0 || EltIdx >= 16)
6493 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6495 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6496 DAG.getNode(ISD::BUILD_VECTOR, dl,
6497 MVT::v16i8, &pshufbMask[0], 16));
6499 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6500 // the 2nd operand if it's undefined or zero.
6501 if (V2.getOpcode() == ISD::UNDEF ||
6502 ISD::isBuildVectorAllZeros(V2.getNode()))
6505 // Calculate the shuffle mask for the second input, shuffle it, and
6506 // OR it with the first shuffled input.
6508 for (unsigned i = 0; i != 16; ++i) {
6509 int EltIdx = MaskVals[i];
6510 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6511 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6513 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6514 DAG.getNode(ISD::BUILD_VECTOR, dl,
6515 MVT::v16i8, &pshufbMask[0], 16));
6516 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6519 // No SSSE3 - Calculate in place words and then fix all out of place words
6520 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6521 // the 16 different words that comprise the two doublequadword input vectors.
6522 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6523 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6525 for (int i = 0; i != 8; ++i) {
6526 int Elt0 = MaskVals[i*2];
6527 int Elt1 = MaskVals[i*2+1];
6529 // This word of the result is all undef, skip it.
6530 if (Elt0 < 0 && Elt1 < 0)
6533 // This word of the result is already in the correct place, skip it.
6534 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6537 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6538 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6541 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6542 // using a single extract together, load it and store it.
6543 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6544 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6545 DAG.getIntPtrConstant(Elt1 / 2));
6546 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6547 DAG.getIntPtrConstant(i));
6551 // If Elt1 is defined, extract it from the appropriate source. If the
6552 // source byte is not also odd, shift the extracted word left 8 bits
6553 // otherwise clear the bottom 8 bits if we need to do an or.
6555 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6556 DAG.getIntPtrConstant(Elt1 / 2));
6557 if ((Elt1 & 1) == 0)
6558 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6560 TLI.getShiftAmountTy(InsElt.getValueType())));
6562 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6563 DAG.getConstant(0xFF00, MVT::i16));
6565 // If Elt0 is defined, extract it from the appropriate source. If the
6566 // source byte is not also even, shift the extracted word right 8 bits. If
6567 // Elt1 was also defined, OR the extracted values together before
6568 // inserting them in the result.
6570 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6571 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6572 if ((Elt0 & 1) != 0)
6573 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6575 TLI.getShiftAmountTy(InsElt0.getValueType())));
6577 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6578 DAG.getConstant(0x00FF, MVT::i16));
6579 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6582 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6583 DAG.getIntPtrConstant(i));
6585 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6588 // v32i8 shuffles - Translate to VPSHUFB if possible.
6590 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6591 const X86Subtarget *Subtarget,
6592 SelectionDAG &DAG) {
6593 MVT VT = SVOp->getSimpleValueType(0);
6594 SDValue V1 = SVOp->getOperand(0);
6595 SDValue V2 = SVOp->getOperand(1);
6597 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6599 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6600 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6601 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6603 // VPSHUFB may be generated if
6604 // (1) one of input vector is undefined or zeroinitializer.
6605 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6606 // And (2) the mask indexes don't cross the 128-bit lane.
6607 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6608 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6611 if (V1IsAllZero && !V2IsAllZero) {
6612 CommuteVectorShuffleMask(MaskVals, 32);
6615 SmallVector<SDValue, 32> pshufbMask;
6616 for (unsigned i = 0; i != 32; i++) {
6617 int EltIdx = MaskVals[i];
6618 if (EltIdx < 0 || EltIdx >= 32)
6621 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6622 // Cross lane is not allowed.
6626 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6628 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6629 DAG.getNode(ISD::BUILD_VECTOR, dl,
6630 MVT::v32i8, &pshufbMask[0], 32));
6633 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6634 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6635 /// done when every pair / quad of shuffle mask elements point to elements in
6636 /// the right sequence. e.g.
6637 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6639 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6640 SelectionDAG &DAG) {
6641 MVT VT = SVOp->getSimpleValueType(0);
6643 unsigned NumElems = VT.getVectorNumElements();
6646 switch (VT.SimpleTy) {
6647 default: llvm_unreachable("Unexpected!");
6648 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6649 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6650 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6651 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6652 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6653 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6656 SmallVector<int, 8> MaskVec;
6657 for (unsigned i = 0; i != NumElems; i += Scale) {
6659 for (unsigned j = 0; j != Scale; ++j) {
6660 int EltIdx = SVOp->getMaskElt(i+j);
6664 StartIdx = (EltIdx / Scale);
6665 if (EltIdx != (int)(StartIdx*Scale + j))
6668 MaskVec.push_back(StartIdx);
6671 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6672 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6673 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6676 /// getVZextMovL - Return a zero-extending vector move low node.
6678 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6679 SDValue SrcOp, SelectionDAG &DAG,
6680 const X86Subtarget *Subtarget, SDLoc dl) {
6681 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6682 LoadSDNode *LD = NULL;
6683 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6684 LD = dyn_cast<LoadSDNode>(SrcOp);
6686 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6688 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6689 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6690 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6691 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6692 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6694 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6695 return DAG.getNode(ISD::BITCAST, dl, VT,
6696 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6697 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6705 return DAG.getNode(ISD::BITCAST, dl, VT,
6706 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6707 DAG.getNode(ISD::BITCAST, dl,
6711 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6712 /// which could not be matched by any known target speficic shuffle
6714 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6716 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6717 if (NewOp.getNode())
6720 MVT VT = SVOp->getSimpleValueType(0);
6722 unsigned NumElems = VT.getVectorNumElements();
6723 unsigned NumLaneElems = NumElems / 2;
6726 MVT EltVT = VT.getVectorElementType();
6727 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6730 SmallVector<int, 16> Mask;
6731 for (unsigned l = 0; l < 2; ++l) {
6732 // Build a shuffle mask for the output, discovering on the fly which
6733 // input vectors to use as shuffle operands (recorded in InputUsed).
6734 // If building a suitable shuffle vector proves too hard, then bail
6735 // out with UseBuildVector set.
6736 bool UseBuildVector = false;
6737 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6738 unsigned LaneStart = l * NumLaneElems;
6739 for (unsigned i = 0; i != NumLaneElems; ++i) {
6740 // The mask element. This indexes into the input.
6741 int Idx = SVOp->getMaskElt(i+LaneStart);
6743 // the mask element does not index into any input vector.
6748 // The input vector this mask element indexes into.
6749 int Input = Idx / NumLaneElems;
6751 // Turn the index into an offset from the start of the input vector.
6752 Idx -= Input * NumLaneElems;
6754 // Find or create a shuffle vector operand to hold this input.
6756 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6757 if (InputUsed[OpNo] == Input)
6758 // This input vector is already an operand.
6760 if (InputUsed[OpNo] < 0) {
6761 // Create a new operand for this input vector.
6762 InputUsed[OpNo] = Input;
6767 if (OpNo >= array_lengthof(InputUsed)) {
6768 // More than two input vectors used! Give up on trying to create a
6769 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6770 UseBuildVector = true;
6774 // Add the mask index for the new shuffle vector.
6775 Mask.push_back(Idx + OpNo * NumLaneElems);
6778 if (UseBuildVector) {
6779 SmallVector<SDValue, 16> SVOps;
6780 for (unsigned i = 0; i != NumLaneElems; ++i) {
6781 // The mask element. This indexes into the input.
6782 int Idx = SVOp->getMaskElt(i+LaneStart);
6784 SVOps.push_back(DAG.getUNDEF(EltVT));
6788 // The input vector this mask element indexes into.
6789 int Input = Idx / NumElems;
6791 // Turn the index into an offset from the start of the input vector.
6792 Idx -= Input * NumElems;
6794 // Extract the vector element by hand.
6795 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6796 SVOp->getOperand(Input),
6797 DAG.getIntPtrConstant(Idx)));
6800 // Construct the output using a BUILD_VECTOR.
6801 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6803 } else if (InputUsed[0] < 0) {
6804 // No input vectors were used! The result is undefined.
6805 Output[l] = DAG.getUNDEF(NVT);
6807 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6808 (InputUsed[0] % 2) * NumLaneElems,
6810 // If only one input was used, use an undefined vector for the other.
6811 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6812 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6813 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6814 // At least one input vector was used. Create a new shuffle vector.
6815 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6821 // Concatenate the result back
6822 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6825 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6826 /// 4 elements, and match them with several different shuffle types.
6828 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6829 SDValue V1 = SVOp->getOperand(0);
6830 SDValue V2 = SVOp->getOperand(1);
6832 MVT VT = SVOp->getSimpleValueType(0);
6834 assert(VT.is128BitVector() && "Unsupported vector size");
6836 std::pair<int, int> Locs[4];
6837 int Mask1[] = { -1, -1, -1, -1 };
6838 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6842 for (unsigned i = 0; i != 4; ++i) {
6843 int Idx = PermMask[i];
6845 Locs[i] = std::make_pair(-1, -1);
6847 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6849 Locs[i] = std::make_pair(0, NumLo);
6853 Locs[i] = std::make_pair(1, NumHi);
6855 Mask1[2+NumHi] = Idx;
6861 if (NumLo <= 2 && NumHi <= 2) {
6862 // If no more than two elements come from either vector. This can be
6863 // implemented with two shuffles. First shuffle gather the elements.
6864 // The second shuffle, which takes the first shuffle as both of its
6865 // vector operands, put the elements into the right order.
6866 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6868 int Mask2[] = { -1, -1, -1, -1 };
6870 for (unsigned i = 0; i != 4; ++i)
6871 if (Locs[i].first != -1) {
6872 unsigned Idx = (i < 2) ? 0 : 4;
6873 Idx += Locs[i].first * 2 + Locs[i].second;
6877 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6880 if (NumLo == 3 || NumHi == 3) {
6881 // Otherwise, we must have three elements from one vector, call it X, and
6882 // one element from the other, call it Y. First, use a shufps to build an
6883 // intermediate vector with the one element from Y and the element from X
6884 // that will be in the same half in the final destination (the indexes don't
6885 // matter). Then, use a shufps to build the final vector, taking the half
6886 // containing the element from Y from the intermediate, and the other half
6889 // Normalize it so the 3 elements come from V1.
6890 CommuteVectorShuffleMask(PermMask, 4);
6894 // Find the element from V2.
6896 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6897 int Val = PermMask[HiIndex];
6904 Mask1[0] = PermMask[HiIndex];
6906 Mask1[2] = PermMask[HiIndex^1];
6908 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6911 Mask1[0] = PermMask[0];
6912 Mask1[1] = PermMask[1];
6913 Mask1[2] = HiIndex & 1 ? 6 : 4;
6914 Mask1[3] = HiIndex & 1 ? 4 : 6;
6915 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6918 Mask1[0] = HiIndex & 1 ? 2 : 0;
6919 Mask1[1] = HiIndex & 1 ? 0 : 2;
6920 Mask1[2] = PermMask[2];
6921 Mask1[3] = PermMask[3];
6926 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6929 // Break it into (shuffle shuffle_hi, shuffle_lo).
6930 int LoMask[] = { -1, -1, -1, -1 };
6931 int HiMask[] = { -1, -1, -1, -1 };
6933 int *MaskPtr = LoMask;
6934 unsigned MaskIdx = 0;
6937 for (unsigned i = 0; i != 4; ++i) {
6944 int Idx = PermMask[i];
6946 Locs[i] = std::make_pair(-1, -1);
6947 } else if (Idx < 4) {
6948 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6949 MaskPtr[LoIdx] = Idx;
6952 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6953 MaskPtr[HiIdx] = Idx;
6958 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6959 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6960 int MaskOps[] = { -1, -1, -1, -1 };
6961 for (unsigned i = 0; i != 4; ++i)
6962 if (Locs[i].first != -1)
6963 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6964 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6967 static bool MayFoldVectorLoad(SDValue V) {
6968 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6969 V = V.getOperand(0);
6971 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6972 V = V.getOperand(0);
6973 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6974 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6975 // BUILD_VECTOR (load), undef
6976 V = V.getOperand(0);
6978 return MayFoldLoad(V);
6982 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6983 MVT VT = Op.getSimpleValueType();
6985 // Canonizalize to v2f64.
6986 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6987 return DAG.getNode(ISD::BITCAST, dl, VT,
6988 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6993 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6995 SDValue V1 = Op.getOperand(0);
6996 SDValue V2 = Op.getOperand(1);
6997 MVT VT = Op.getSimpleValueType();
6999 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7001 if (HasSSE2 && VT == MVT::v2f64)
7002 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7004 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7005 return DAG.getNode(ISD::BITCAST, dl, VT,
7006 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7007 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7008 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7012 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7013 SDValue V1 = Op.getOperand(0);
7014 SDValue V2 = Op.getOperand(1);
7015 MVT VT = Op.getSimpleValueType();
7017 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7018 "unsupported shuffle type");
7020 if (V2.getOpcode() == ISD::UNDEF)
7024 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7028 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7029 SDValue V1 = Op.getOperand(0);
7030 SDValue V2 = Op.getOperand(1);
7031 MVT VT = Op.getSimpleValueType();
7032 unsigned NumElems = VT.getVectorNumElements();
7034 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7035 // operand of these instructions is only memory, so check if there's a
7036 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7038 bool CanFoldLoad = false;
7040 // Trivial case, when V2 comes from a load.
7041 if (MayFoldVectorLoad(V2))
7044 // When V1 is a load, it can be folded later into a store in isel, example:
7045 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7047 // (MOVLPSmr addr:$src1, VR128:$src2)
7048 // So, recognize this potential and also use MOVLPS or MOVLPD
7049 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7054 if (HasSSE2 && NumElems == 2)
7055 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7058 // If we don't care about the second element, proceed to use movss.
7059 if (SVOp->getMaskElt(1) != -1)
7060 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7063 // movl and movlp will both match v2i64, but v2i64 is never matched by
7064 // movl earlier because we make it strict to avoid messing with the movlp load
7065 // folding logic (see the code above getMOVLP call). Match it here then,
7066 // this is horrible, but will stay like this until we move all shuffle
7067 // matching to x86 specific nodes. Note that for the 1st condition all
7068 // types are matched with movsd.
7070 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7071 // as to remove this logic from here, as much as possible
7072 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7073 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7074 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7077 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7079 // Invert the operand order and use SHUFPS to match it.
7080 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7081 getShuffleSHUFImmediate(SVOp), DAG);
7084 // Reduce a vector shuffle to zext.
7085 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7086 SelectionDAG &DAG) {
7087 // PMOVZX is only available from SSE41.
7088 if (!Subtarget->hasSSE41())
7091 MVT VT = Op.getSimpleValueType();
7093 // Only AVX2 support 256-bit vector integer extending.
7094 if (!Subtarget->hasInt256() && VT.is256BitVector())
7097 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7099 SDValue V1 = Op.getOperand(0);
7100 SDValue V2 = Op.getOperand(1);
7101 unsigned NumElems = VT.getVectorNumElements();
7103 // Extending is an unary operation and the element type of the source vector
7104 // won't be equal to or larger than i64.
7105 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7106 VT.getVectorElementType() == MVT::i64)
7109 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7110 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7111 while ((1U << Shift) < NumElems) {
7112 if (SVOp->getMaskElt(1U << Shift) == 1)
7115 // The maximal ratio is 8, i.e. from i8 to i64.
7120 // Check the shuffle mask.
7121 unsigned Mask = (1U << Shift) - 1;
7122 for (unsigned i = 0; i != NumElems; ++i) {
7123 int EltIdx = SVOp->getMaskElt(i);
7124 if ((i & Mask) != 0 && EltIdx != -1)
7126 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7130 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7131 MVT NeVT = MVT::getIntegerVT(NBits);
7132 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7134 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7137 // Simplify the operand as it's prepared to be fed into shuffle.
7138 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7139 if (V1.getOpcode() == ISD::BITCAST &&
7140 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7141 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7142 V1.getOperand(0).getOperand(0)
7143 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7144 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7145 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7146 ConstantSDNode *CIdx =
7147 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7148 // If it's foldable, i.e. normal load with single use, we will let code
7149 // selection to fold it. Otherwise, we will short the conversion sequence.
7150 if (CIdx && CIdx->getZExtValue() == 0 &&
7151 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7152 MVT FullVT = V.getSimpleValueType();
7153 MVT V1VT = V1.getSimpleValueType();
7154 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7155 // The "ext_vec_elt" node is wider than the result node.
7156 // In this case we should extract subvector from V.
7157 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7158 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7159 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7160 FullVT.getVectorNumElements()/Ratio);
7161 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7162 DAG.getIntPtrConstant(0));
7164 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7168 return DAG.getNode(ISD::BITCAST, DL, VT,
7169 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7173 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7174 SelectionDAG &DAG) {
7175 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7176 MVT VT = Op.getSimpleValueType();
7178 SDValue V1 = Op.getOperand(0);
7179 SDValue V2 = Op.getOperand(1);
7181 if (isZeroShuffle(SVOp))
7182 return getZeroVector(VT, Subtarget, DAG, dl);
7184 // Handle splat operations
7185 if (SVOp->isSplat()) {
7186 // Use vbroadcast whenever the splat comes from a foldable load
7187 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7188 if (Broadcast.getNode())
7192 // Check integer expanding shuffles.
7193 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7194 if (NewOp.getNode())
7197 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7199 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7200 VT == MVT::v16i16 || VT == MVT::v32i8) {
7201 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7202 if (NewOp.getNode())
7203 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7204 } else if ((VT == MVT::v4i32 ||
7205 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7206 // FIXME: Figure out a cleaner way to do this.
7207 // Try to make use of movq to zero out the top part.
7208 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7209 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7210 if (NewOp.getNode()) {
7211 MVT NewVT = NewOp.getSimpleValueType();
7212 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7213 NewVT, true, false))
7214 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7215 DAG, Subtarget, dl);
7217 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7218 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7219 if (NewOp.getNode()) {
7220 MVT NewVT = NewOp.getSimpleValueType();
7221 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7222 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7223 DAG, Subtarget, dl);
7231 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7232 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7233 SDValue V1 = Op.getOperand(0);
7234 SDValue V2 = Op.getOperand(1);
7235 MVT VT = Op.getSimpleValueType();
7237 unsigned NumElems = VT.getVectorNumElements();
7238 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7239 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7240 bool V1IsSplat = false;
7241 bool V2IsSplat = false;
7242 bool HasSSE2 = Subtarget->hasSSE2();
7243 bool HasFp256 = Subtarget->hasFp256();
7244 bool HasInt256 = Subtarget->hasInt256();
7245 MachineFunction &MF = DAG.getMachineFunction();
7246 bool OptForSize = MF.getFunction()->getAttributes().
7247 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7249 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7251 if (V1IsUndef && V2IsUndef)
7252 return DAG.getUNDEF(VT);
7254 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7256 // Vector shuffle lowering takes 3 steps:
7258 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7259 // narrowing and commutation of operands should be handled.
7260 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7262 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7263 // so the shuffle can be broken into other shuffles and the legalizer can
7264 // try the lowering again.
7266 // The general idea is that no vector_shuffle operation should be left to
7267 // be matched during isel, all of them must be converted to a target specific
7270 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7271 // narrowing and commutation of operands should be handled. The actual code
7272 // doesn't include all of those, work in progress...
7273 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7274 if (NewOp.getNode())
7277 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7279 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7280 // unpckh_undef). Only use pshufd if speed is more important than size.
7281 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7282 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7283 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7284 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7286 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7287 V2IsUndef && MayFoldVectorLoad(V1))
7288 return getMOVDDup(Op, dl, V1, DAG);
7290 if (isMOVHLPS_v_undef_Mask(M, VT))
7291 return getMOVHighToLow(Op, dl, DAG);
7293 // Use to match splats
7294 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7295 (VT == MVT::v2f64 || VT == MVT::v2i64))
7296 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7298 if (isPSHUFDMask(M, VT)) {
7299 // The actual implementation will match the mask in the if above and then
7300 // during isel it can match several different instructions, not only pshufd
7301 // as its name says, sad but true, emulate the behavior for now...
7302 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7303 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7305 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7307 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7308 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7310 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7311 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7314 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7318 if (isPALIGNRMask(M, VT, Subtarget))
7319 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7320 getShufflePALIGNRImmediate(SVOp),
7323 // Check if this can be converted into a logical shift.
7324 bool isLeft = false;
7327 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7328 if (isShift && ShVal.hasOneUse()) {
7329 // If the shifted value has multiple uses, it may be cheaper to use
7330 // v_set0 + movlhps or movhlps, etc.
7331 MVT EltVT = VT.getVectorElementType();
7332 ShAmt *= EltVT.getSizeInBits();
7333 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7336 if (isMOVLMask(M, VT)) {
7337 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7338 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7339 if (!isMOVLPMask(M, VT)) {
7340 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7341 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7343 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7344 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7348 // FIXME: fold these into legal mask.
7349 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7350 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7352 if (isMOVHLPSMask(M, VT))
7353 return getMOVHighToLow(Op, dl, DAG);
7355 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7356 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7358 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7359 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7361 if (isMOVLPMask(M, VT))
7362 return getMOVLP(Op, dl, DAG, HasSSE2);
7364 if (ShouldXformToMOVHLPS(M, VT) ||
7365 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7366 return CommuteVectorShuffle(SVOp, DAG);
7369 // No better options. Use a vshldq / vsrldq.
7370 MVT EltVT = VT.getVectorElementType();
7371 ShAmt *= EltVT.getSizeInBits();
7372 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7375 bool Commuted = false;
7376 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7377 // 1,1,1,1 -> v8i16 though.
7378 V1IsSplat = isSplatVector(V1.getNode());
7379 V2IsSplat = isSplatVector(V2.getNode());
7381 // Canonicalize the splat or undef, if present, to be on the RHS.
7382 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7383 CommuteVectorShuffleMask(M, NumElems);
7385 std::swap(V1IsSplat, V2IsSplat);
7389 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7390 // Shuffling low element of v1 into undef, just return v1.
7393 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7394 // the instruction selector will not match, so get a canonical MOVL with
7395 // swapped operands to undo the commute.
7396 return getMOVL(DAG, dl, VT, V2, V1);
7399 if (isUNPCKLMask(M, VT, HasInt256))
7400 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7402 if (isUNPCKHMask(M, VT, HasInt256))
7403 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7406 // Normalize mask so all entries that point to V2 points to its first
7407 // element then try to match unpck{h|l} again. If match, return a
7408 // new vector_shuffle with the corrected mask.p
7409 SmallVector<int, 8> NewMask(M.begin(), M.end());
7410 NormalizeMask(NewMask, NumElems);
7411 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7412 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7413 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7414 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7418 // Commute is back and try unpck* again.
7419 // FIXME: this seems wrong.
7420 CommuteVectorShuffleMask(M, NumElems);
7422 std::swap(V1IsSplat, V2IsSplat);
7425 if (isUNPCKLMask(M, VT, HasInt256))
7426 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7428 if (isUNPCKHMask(M, VT, HasInt256))
7429 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7432 // Normalize the node to match x86 shuffle ops if needed
7433 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7434 return CommuteVectorShuffle(SVOp, DAG);
7436 // The checks below are all present in isShuffleMaskLegal, but they are
7437 // inlined here right now to enable us to directly emit target specific
7438 // nodes, and remove one by one until they don't return Op anymore.
7440 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7441 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7442 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7443 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7446 if (isPSHUFHWMask(M, VT, HasInt256))
7447 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7448 getShufflePSHUFHWImmediate(SVOp),
7451 if (isPSHUFLWMask(M, VT, HasInt256))
7452 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7453 getShufflePSHUFLWImmediate(SVOp),
7456 if (isSHUFPMask(M, VT))
7457 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7458 getShuffleSHUFImmediate(SVOp), DAG);
7460 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7461 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7462 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7463 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7465 //===--------------------------------------------------------------------===//
7466 // Generate target specific nodes for 128 or 256-bit shuffles only
7467 // supported in the AVX instruction set.
7470 // Handle VMOVDDUPY permutations
7471 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7472 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7474 // Handle VPERMILPS/D* permutations
7475 if (isVPERMILPMask(M, VT)) {
7476 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7477 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7478 getShuffleSHUFImmediate(SVOp), DAG);
7479 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7480 getShuffleSHUFImmediate(SVOp), DAG);
7483 // Handle VPERM2F128/VPERM2I128 permutations
7484 if (isVPERM2X128Mask(M, VT, HasFp256))
7485 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7486 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7488 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7489 if (BlendOp.getNode())
7493 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7494 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7496 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7497 VT.is512BitVector()) {
7498 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7499 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7500 SmallVector<SDValue, 16> permclMask;
7501 for (unsigned i = 0; i != NumElems; ++i) {
7502 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7505 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7506 &permclMask[0], NumElems);
7508 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7509 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7510 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7511 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7512 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7515 //===--------------------------------------------------------------------===//
7516 // Since no target specific shuffle was selected for this generic one,
7517 // lower it into other known shuffles. FIXME: this isn't true yet, but
7518 // this is the plan.
7521 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7522 if (VT == MVT::v8i16) {
7523 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7524 if (NewOp.getNode())
7528 if (VT == MVT::v16i8) {
7529 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7530 if (NewOp.getNode())
7534 if (VT == MVT::v32i8) {
7535 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7536 if (NewOp.getNode())
7540 // Handle all 128-bit wide vectors with 4 elements, and match them with
7541 // several different shuffle types.
7542 if (NumElems == 4 && VT.is128BitVector())
7543 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7545 // Handle general 256-bit shuffles
7546 if (VT.is256BitVector())
7547 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7552 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7553 MVT VT = Op.getSimpleValueType();
7556 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7559 if (VT.getSizeInBits() == 8) {
7560 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7561 Op.getOperand(0), Op.getOperand(1));
7562 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7563 DAG.getValueType(VT));
7564 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7567 if (VT.getSizeInBits() == 16) {
7568 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7569 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7571 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7572 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7573 DAG.getNode(ISD::BITCAST, dl,
7577 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7578 Op.getOperand(0), Op.getOperand(1));
7579 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7580 DAG.getValueType(VT));
7581 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7584 if (VT == MVT::f32) {
7585 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7586 // the result back to FR32 register. It's only worth matching if the
7587 // result has a single use which is a store or a bitcast to i32. And in
7588 // the case of a store, it's not worth it if the index is a constant 0,
7589 // because a MOVSSmr can be used instead, which is smaller and faster.
7590 if (!Op.hasOneUse())
7592 SDNode *User = *Op.getNode()->use_begin();
7593 if ((User->getOpcode() != ISD::STORE ||
7594 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7595 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7596 (User->getOpcode() != ISD::BITCAST ||
7597 User->getValueType(0) != MVT::i32))
7599 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7600 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7603 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7606 if (VT == MVT::i32 || VT == MVT::i64) {
7607 // ExtractPS/pextrq works with constant index.
7608 if (isa<ConstantSDNode>(Op.getOperand(1)))
7615 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7616 SelectionDAG &DAG) const {
7618 SDValue Vec = Op.getOperand(0);
7619 MVT VecVT = Vec.getSimpleValueType();
7620 SDValue Idx = Op.getOperand(1);
7621 if (!isa<ConstantSDNode>(Idx)) {
7622 if (VecVT.is512BitVector() ||
7623 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7624 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7627 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7628 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7629 MaskEltVT.getSizeInBits());
7631 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7632 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7633 getZeroVector(MaskVT, Subtarget, DAG, dl),
7634 Idx, DAG.getConstant(0, getPointerTy()));
7635 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7636 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7637 Perm, DAG.getConstant(0, getPointerTy()));
7642 // If this is a 256-bit vector result, first extract the 128-bit vector and
7643 // then extract the element from the 128-bit vector.
7644 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7646 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7647 // Get the 128-bit vector.
7648 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7649 MVT EltVT = VecVT.getVectorElementType();
7651 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7653 //if (IdxVal >= NumElems/2)
7654 // IdxVal -= NumElems/2;
7655 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7656 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7657 DAG.getConstant(IdxVal, MVT::i32));
7660 assert(VecVT.is128BitVector() && "Unexpected vector length");
7662 if (Subtarget->hasSSE41()) {
7663 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7668 MVT VT = Op.getSimpleValueType();
7669 // TODO: handle v16i8.
7670 if (VT.getSizeInBits() == 16) {
7671 SDValue Vec = Op.getOperand(0);
7672 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7674 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7675 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7676 DAG.getNode(ISD::BITCAST, dl,
7679 // Transform it so it match pextrw which produces a 32-bit result.
7680 MVT EltVT = MVT::i32;
7681 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7682 Op.getOperand(0), Op.getOperand(1));
7683 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7684 DAG.getValueType(VT));
7685 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7688 if (VT.getSizeInBits() == 32) {
7689 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7693 // SHUFPS the element to the lowest double word, then movss.
7694 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7695 MVT VVT = Op.getOperand(0).getSimpleValueType();
7696 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7697 DAG.getUNDEF(VVT), Mask);
7698 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7699 DAG.getIntPtrConstant(0));
7702 if (VT.getSizeInBits() == 64) {
7703 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7704 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7705 // to match extract_elt for f64.
7706 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7710 // UNPCKHPD the element to the lowest double word, then movsd.
7711 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7712 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7713 int Mask[2] = { 1, -1 };
7714 MVT VVT = Op.getOperand(0).getSimpleValueType();
7715 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7716 DAG.getUNDEF(VVT), Mask);
7717 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7718 DAG.getIntPtrConstant(0));
7724 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7725 MVT VT = Op.getSimpleValueType();
7726 MVT EltVT = VT.getVectorElementType();
7729 SDValue N0 = Op.getOperand(0);
7730 SDValue N1 = Op.getOperand(1);
7731 SDValue N2 = Op.getOperand(2);
7733 if (!VT.is128BitVector())
7736 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7737 isa<ConstantSDNode>(N2)) {
7739 if (VT == MVT::v8i16)
7740 Opc = X86ISD::PINSRW;
7741 else if (VT == MVT::v16i8)
7742 Opc = X86ISD::PINSRB;
7744 Opc = X86ISD::PINSRB;
7746 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7748 if (N1.getValueType() != MVT::i32)
7749 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7750 if (N2.getValueType() != MVT::i32)
7751 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7752 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7755 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7756 // Bits [7:6] of the constant are the source select. This will always be
7757 // zero here. The DAG Combiner may combine an extract_elt index into these
7758 // bits. For example (insert (extract, 3), 2) could be matched by putting
7759 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7760 // Bits [5:4] of the constant are the destination select. This is the
7761 // value of the incoming immediate.
7762 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7763 // combine either bitwise AND or insert of float 0.0 to set these bits.
7764 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7765 // Create this as a scalar to vector..
7766 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7767 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7770 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7771 // PINSR* works with constant index.
7778 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7779 MVT VT = Op.getSimpleValueType();
7780 MVT EltVT = VT.getVectorElementType();
7783 SDValue N0 = Op.getOperand(0);
7784 SDValue N1 = Op.getOperand(1);
7785 SDValue N2 = Op.getOperand(2);
7787 // If this is a 256-bit vector result, first extract the 128-bit vector,
7788 // insert the element into the extracted half and then place it back.
7789 if (VT.is256BitVector() || VT.is512BitVector()) {
7790 if (!isa<ConstantSDNode>(N2))
7793 // Get the desired 128-bit vector half.
7794 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7795 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7797 // Insert the element into the desired half.
7798 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7799 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7801 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7802 DAG.getConstant(IdxIn128, MVT::i32));
7804 // Insert the changed part back to the 256-bit vector
7805 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7808 if (Subtarget->hasSSE41())
7809 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7811 if (EltVT == MVT::i8)
7814 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7815 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7816 // as its second argument.
7817 if (N1.getValueType() != MVT::i32)
7818 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7819 if (N2.getValueType() != MVT::i32)
7820 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7821 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7826 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7828 MVT OpVT = Op.getSimpleValueType();
7830 // If this is a 256-bit vector result, first insert into a 128-bit
7831 // vector and then insert into the 256-bit vector.
7832 if (!OpVT.is128BitVector()) {
7833 // Insert into a 128-bit vector.
7834 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7835 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7836 OpVT.getVectorNumElements() / SizeFactor);
7838 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7840 // Insert the 128-bit vector.
7841 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7844 if (OpVT == MVT::v1i64 &&
7845 Op.getOperand(0).getValueType() == MVT::i64)
7846 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7848 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7849 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7850 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7851 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7854 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7855 // a simple subregister reference or explicit instructions to grab
7856 // upper bits of a vector.
7857 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7858 SelectionDAG &DAG) {
7860 SDValue In = Op.getOperand(0);
7861 SDValue Idx = Op.getOperand(1);
7862 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7863 MVT ResVT = Op.getSimpleValueType();
7864 MVT InVT = In.getSimpleValueType();
7866 if (Subtarget->hasFp256()) {
7867 if (ResVT.is128BitVector() &&
7868 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7869 isa<ConstantSDNode>(Idx)) {
7870 return Extract128BitVector(In, IdxVal, DAG, dl);
7872 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7873 isa<ConstantSDNode>(Idx)) {
7874 return Extract256BitVector(In, IdxVal, DAG, dl);
7880 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7881 // simple superregister reference or explicit instructions to insert
7882 // the upper bits of a vector.
7883 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7884 SelectionDAG &DAG) {
7885 if (Subtarget->hasFp256()) {
7886 SDLoc dl(Op.getNode());
7887 SDValue Vec = Op.getNode()->getOperand(0);
7888 SDValue SubVec = Op.getNode()->getOperand(1);
7889 SDValue Idx = Op.getNode()->getOperand(2);
7891 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7892 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7893 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7894 isa<ConstantSDNode>(Idx)) {
7895 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7896 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7899 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7900 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7901 isa<ConstantSDNode>(Idx)) {
7902 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7903 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7909 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7910 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7911 // one of the above mentioned nodes. It has to be wrapped because otherwise
7912 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7913 // be used to form addressing mode. These wrapped nodes will be selected
7916 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7917 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7919 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7921 unsigned char OpFlag = 0;
7922 unsigned WrapperKind = X86ISD::Wrapper;
7923 CodeModel::Model M = getTargetMachine().getCodeModel();
7925 if (Subtarget->isPICStyleRIPRel() &&
7926 (M == CodeModel::Small || M == CodeModel::Kernel))
7927 WrapperKind = X86ISD::WrapperRIP;
7928 else if (Subtarget->isPICStyleGOT())
7929 OpFlag = X86II::MO_GOTOFF;
7930 else if (Subtarget->isPICStyleStubPIC())
7931 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7933 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7935 CP->getOffset(), OpFlag);
7937 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7938 // With PIC, the address is actually $g + Offset.
7940 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7941 DAG.getNode(X86ISD::GlobalBaseReg,
7942 SDLoc(), getPointerTy()),
7949 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7950 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7952 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7954 unsigned char OpFlag = 0;
7955 unsigned WrapperKind = X86ISD::Wrapper;
7956 CodeModel::Model M = getTargetMachine().getCodeModel();
7958 if (Subtarget->isPICStyleRIPRel() &&
7959 (M == CodeModel::Small || M == CodeModel::Kernel))
7960 WrapperKind = X86ISD::WrapperRIP;
7961 else if (Subtarget->isPICStyleGOT())
7962 OpFlag = X86II::MO_GOTOFF;
7963 else if (Subtarget->isPICStyleStubPIC())
7964 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7966 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7969 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7971 // With PIC, the address is actually $g + Offset.
7973 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7974 DAG.getNode(X86ISD::GlobalBaseReg,
7975 SDLoc(), getPointerTy()),
7982 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7983 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7985 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7987 unsigned char OpFlag = 0;
7988 unsigned WrapperKind = X86ISD::Wrapper;
7989 CodeModel::Model M = getTargetMachine().getCodeModel();
7991 if (Subtarget->isPICStyleRIPRel() &&
7992 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7993 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7994 OpFlag = X86II::MO_GOTPCREL;
7995 WrapperKind = X86ISD::WrapperRIP;
7996 } else if (Subtarget->isPICStyleGOT()) {
7997 OpFlag = X86II::MO_GOT;
7998 } else if (Subtarget->isPICStyleStubPIC()) {
7999 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8000 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8001 OpFlag = X86II::MO_DARWIN_NONLAZY;
8004 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8007 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8009 // With PIC, the address is actually $g + Offset.
8010 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8011 !Subtarget->is64Bit()) {
8012 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8013 DAG.getNode(X86ISD::GlobalBaseReg,
8014 SDLoc(), getPointerTy()),
8018 // For symbols that require a load from a stub to get the address, emit the
8020 if (isGlobalStubReference(OpFlag))
8021 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8022 MachinePointerInfo::getGOT(), false, false, false, 0);
8028 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8029 // Create the TargetBlockAddressAddress node.
8030 unsigned char OpFlags =
8031 Subtarget->ClassifyBlockAddressReference();
8032 CodeModel::Model M = getTargetMachine().getCodeModel();
8033 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8034 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8036 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8039 if (Subtarget->isPICStyleRIPRel() &&
8040 (M == CodeModel::Small || M == CodeModel::Kernel))
8041 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8043 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8045 // With PIC, the address is actually $g + Offset.
8046 if (isGlobalRelativeToPICBase(OpFlags)) {
8047 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8048 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8056 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8057 int64_t Offset, SelectionDAG &DAG) const {
8058 // Create the TargetGlobalAddress node, folding in the constant
8059 // offset if it is legal.
8060 unsigned char OpFlags =
8061 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8062 CodeModel::Model M = getTargetMachine().getCodeModel();
8064 if (OpFlags == X86II::MO_NO_FLAG &&
8065 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8066 // A direct static reference to a global.
8067 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8070 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8073 if (Subtarget->isPICStyleRIPRel() &&
8074 (M == CodeModel::Small || M == CodeModel::Kernel))
8075 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8077 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8079 // With PIC, the address is actually $g + Offset.
8080 if (isGlobalRelativeToPICBase(OpFlags)) {
8081 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8082 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8086 // For globals that require a load from a stub to get the address, emit the
8088 if (isGlobalStubReference(OpFlags))
8089 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8090 MachinePointerInfo::getGOT(), false, false, false, 0);
8092 // If there was a non-zero offset that we didn't fold, create an explicit
8095 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8096 DAG.getConstant(Offset, getPointerTy()));
8102 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8103 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8104 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8105 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8109 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8110 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8111 unsigned char OperandFlags, bool LocalDynamic = false) {
8112 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8113 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8115 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8116 GA->getValueType(0),
8120 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8124 SDValue Ops[] = { Chain, TGA, *InFlag };
8125 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8127 SDValue Ops[] = { Chain, TGA };
8128 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8131 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8132 MFI->setAdjustsStack(true);
8134 SDValue Flag = Chain.getValue(1);
8135 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8138 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8140 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8143 SDLoc dl(GA); // ? function entry point might be better
8144 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8145 DAG.getNode(X86ISD::GlobalBaseReg,
8146 SDLoc(), PtrVT), InFlag);
8147 InFlag = Chain.getValue(1);
8149 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8152 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8154 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8156 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8157 X86::RAX, X86II::MO_TLSGD);
8160 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8166 // Get the start address of the TLS block for this module.
8167 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8168 .getInfo<X86MachineFunctionInfo>();
8169 MFI->incNumLocalDynamicTLSAccesses();
8173 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8174 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8177 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8178 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8179 InFlag = Chain.getValue(1);
8180 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8181 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8184 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8188 unsigned char OperandFlags = X86II::MO_DTPOFF;
8189 unsigned WrapperKind = X86ISD::Wrapper;
8190 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8191 GA->getValueType(0),
8192 GA->getOffset(), OperandFlags);
8193 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8195 // Add x@dtpoff with the base.
8196 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8199 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8200 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8201 const EVT PtrVT, TLSModel::Model model,
8202 bool is64Bit, bool isPIC) {
8205 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8206 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8207 is64Bit ? 257 : 256));
8209 SDValue ThreadPointer =
8210 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8211 MachinePointerInfo(Ptr), false, false, false, 0);
8213 unsigned char OperandFlags = 0;
8214 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8216 unsigned WrapperKind = X86ISD::Wrapper;
8217 if (model == TLSModel::LocalExec) {
8218 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8219 } else if (model == TLSModel::InitialExec) {
8221 OperandFlags = X86II::MO_GOTTPOFF;
8222 WrapperKind = X86ISD::WrapperRIP;
8224 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8227 llvm_unreachable("Unexpected model");
8230 // emit "addl x@ntpoff,%eax" (local exec)
8231 // or "addl x@indntpoff,%eax" (initial exec)
8232 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8234 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8235 GA->getOffset(), OperandFlags);
8236 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8238 if (model == TLSModel::InitialExec) {
8239 if (isPIC && !is64Bit) {
8240 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8241 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8245 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8246 MachinePointerInfo::getGOT(), false, false, false, 0);
8249 // The address of the thread local variable is the add of the thread
8250 // pointer with the offset of the variable.
8251 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8255 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8257 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8258 const GlobalValue *GV = GA->getGlobal();
8260 if (Subtarget->isTargetELF()) {
8261 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8264 case TLSModel::GeneralDynamic:
8265 if (Subtarget->is64Bit())
8266 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8267 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8268 case TLSModel::LocalDynamic:
8269 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8270 Subtarget->is64Bit());
8271 case TLSModel::InitialExec:
8272 case TLSModel::LocalExec:
8273 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8274 Subtarget->is64Bit(),
8275 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8277 llvm_unreachable("Unknown TLS model.");
8280 if (Subtarget->isTargetDarwin()) {
8281 // Darwin only has one model of TLS. Lower to that.
8282 unsigned char OpFlag = 0;
8283 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8284 X86ISD::WrapperRIP : X86ISD::Wrapper;
8286 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8288 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8289 !Subtarget->is64Bit();
8291 OpFlag = X86II::MO_TLVP_PIC_BASE;
8293 OpFlag = X86II::MO_TLVP;
8295 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8296 GA->getValueType(0),
8297 GA->getOffset(), OpFlag);
8298 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8300 // With PIC32, the address is actually $g + Offset.
8302 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8303 DAG.getNode(X86ISD::GlobalBaseReg,
8304 SDLoc(), getPointerTy()),
8307 // Lowering the machine isd will make sure everything is in the right
8309 SDValue Chain = DAG.getEntryNode();
8310 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8311 SDValue Args[] = { Chain, Offset };
8312 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8314 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8315 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8316 MFI->setAdjustsStack(true);
8318 // And our return value (tls address) is in the standard call return value
8320 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8321 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8325 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8326 // Just use the implicit TLS architecture
8327 // Need to generate someting similar to:
8328 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8330 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8331 // mov rcx, qword [rdx+rcx*8]
8332 // mov eax, .tls$:tlsvar
8333 // [rax+rcx] contains the address
8334 // Windows 64bit: gs:0x58
8335 // Windows 32bit: fs:__tls_array
8337 // If GV is an alias then use the aliasee for determining
8338 // thread-localness.
8339 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8340 GV = GA->resolveAliasedGlobal(false);
8342 SDValue Chain = DAG.getEntryNode();
8344 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8345 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8346 // use its literal value of 0x2C.
8347 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8348 ? Type::getInt8PtrTy(*DAG.getContext(),
8350 : Type::getInt32PtrTy(*DAG.getContext(),
8353 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8354 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8355 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8357 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8358 MachinePointerInfo(Ptr),
8359 false, false, false, 0);
8361 // Load the _tls_index variable
8362 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8363 if (Subtarget->is64Bit())
8364 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8365 IDX, MachinePointerInfo(), MVT::i32,
8368 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8369 false, false, false, 0);
8371 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8373 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8375 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8376 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8377 false, false, false, 0);
8379 // Get the offset of start of .tls section
8380 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8381 GA->getValueType(0),
8382 GA->getOffset(), X86II::MO_SECREL);
8383 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8385 // The address of the thread local variable is the add of the thread
8386 // pointer with the offset of the variable.
8387 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8390 llvm_unreachable("TLS not implemented for this target.");
8393 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8394 /// and take a 2 x i32 value to shift plus a shift amount.
8395 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8396 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8397 EVT VT = Op.getValueType();
8398 unsigned VTBits = VT.getSizeInBits();
8400 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8401 SDValue ShOpLo = Op.getOperand(0);
8402 SDValue ShOpHi = Op.getOperand(1);
8403 SDValue ShAmt = Op.getOperand(2);
8404 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8405 DAG.getConstant(VTBits - 1, MVT::i8))
8406 : DAG.getConstant(0, VT);
8409 if (Op.getOpcode() == ISD::SHL_PARTS) {
8410 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8411 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8413 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8414 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8417 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8418 DAG.getConstant(VTBits, MVT::i8));
8419 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8420 AndNode, DAG.getConstant(0, MVT::i8));
8423 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8424 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8425 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8427 if (Op.getOpcode() == ISD::SHL_PARTS) {
8428 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8429 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8431 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8432 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8435 SDValue Ops[2] = { Lo, Hi };
8436 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8439 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8440 SelectionDAG &DAG) const {
8441 EVT SrcVT = Op.getOperand(0).getValueType();
8443 if (SrcVT.isVector())
8446 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8447 "Unknown SINT_TO_FP to lower!");
8449 // These are really Legal; return the operand so the caller accepts it as
8451 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8453 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8454 Subtarget->is64Bit()) {
8459 unsigned Size = SrcVT.getSizeInBits()/8;
8460 MachineFunction &MF = DAG.getMachineFunction();
8461 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8462 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8463 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8465 MachinePointerInfo::getFixedStack(SSFI),
8467 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8470 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8472 SelectionDAG &DAG) const {
8476 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8478 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8480 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8482 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8484 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8485 MachineMemOperand *MMO;
8487 int SSFI = FI->getIndex();
8489 DAG.getMachineFunction()
8490 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8491 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8493 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8494 StackSlot = StackSlot.getOperand(1);
8496 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8497 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8499 Tys, Ops, array_lengthof(Ops),
8503 Chain = Result.getValue(1);
8504 SDValue InFlag = Result.getValue(2);
8506 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8507 // shouldn't be necessary except that RFP cannot be live across
8508 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8509 MachineFunction &MF = DAG.getMachineFunction();
8510 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8511 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8512 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8513 Tys = DAG.getVTList(MVT::Other);
8515 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8517 MachineMemOperand *MMO =
8518 DAG.getMachineFunction()
8519 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8520 MachineMemOperand::MOStore, SSFISize, SSFISize);
8522 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8523 Ops, array_lengthof(Ops),
8524 Op.getValueType(), MMO);
8525 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8526 MachinePointerInfo::getFixedStack(SSFI),
8527 false, false, false, 0);
8533 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8534 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8535 SelectionDAG &DAG) const {
8536 // This algorithm is not obvious. Here it is what we're trying to output:
8539 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8540 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8544 pshufd $0x4e, %xmm0, %xmm1
8550 LLVMContext *Context = DAG.getContext();
8552 // Build some magic constants.
8553 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8554 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8555 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8557 SmallVector<Constant*,2> CV1;
8559 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8560 APInt(64, 0x4330000000000000ULL))));
8562 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8563 APInt(64, 0x4530000000000000ULL))));
8564 Constant *C1 = ConstantVector::get(CV1);
8565 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8567 // Load the 64-bit value into an XMM register.
8568 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8570 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8571 MachinePointerInfo::getConstantPool(),
8572 false, false, false, 16);
8573 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8574 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8577 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8578 MachinePointerInfo::getConstantPool(),
8579 false, false, false, 16);
8580 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8581 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8584 if (Subtarget->hasSSE3()) {
8585 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8586 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8588 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8589 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8591 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8592 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8596 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8597 DAG.getIntPtrConstant(0));
8600 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8601 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8602 SelectionDAG &DAG) const {
8604 // FP constant to bias correct the final result.
8605 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8608 // Load the 32-bit value into an XMM register.
8609 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8612 // Zero out the upper parts of the register.
8613 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8615 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8616 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8617 DAG.getIntPtrConstant(0));
8619 // Or the load with the bias.
8620 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8621 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8622 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8624 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8625 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8626 MVT::v2f64, Bias)));
8627 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8628 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8629 DAG.getIntPtrConstant(0));
8631 // Subtract the bias.
8632 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8634 // Handle final rounding.
8635 EVT DestVT = Op.getValueType();
8637 if (DestVT.bitsLT(MVT::f64))
8638 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8639 DAG.getIntPtrConstant(0));
8640 if (DestVT.bitsGT(MVT::f64))
8641 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8643 // Handle final rounding.
8647 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8648 SelectionDAG &DAG) const {
8649 SDValue N0 = Op.getOperand(0);
8650 EVT SVT = N0.getValueType();
8653 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8654 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8655 "Custom UINT_TO_FP is not supported!");
8657 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8658 SVT.getVectorNumElements());
8659 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8660 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8663 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8664 SelectionDAG &DAG) const {
8665 SDValue N0 = Op.getOperand(0);
8668 if (Op.getValueType().isVector())
8669 return lowerUINT_TO_FP_vec(Op, DAG);
8671 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8672 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8673 // the optimization here.
8674 if (DAG.SignBitIsZero(N0))
8675 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8677 EVT SrcVT = N0.getValueType();
8678 EVT DstVT = Op.getValueType();
8679 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8680 return LowerUINT_TO_FP_i64(Op, DAG);
8681 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8682 return LowerUINT_TO_FP_i32(Op, DAG);
8683 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8686 // Make a 64-bit buffer, and use it to build an FILD.
8687 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8688 if (SrcVT == MVT::i32) {
8689 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8690 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8691 getPointerTy(), StackSlot, WordOff);
8692 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8693 StackSlot, MachinePointerInfo(),
8695 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8696 OffsetSlot, MachinePointerInfo(),
8698 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8702 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8703 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8704 StackSlot, MachinePointerInfo(),
8706 // For i64 source, we need to add the appropriate power of 2 if the input
8707 // was negative. This is the same as the optimization in
8708 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8709 // we must be careful to do the computation in x87 extended precision, not
8710 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8711 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8712 MachineMemOperand *MMO =
8713 DAG.getMachineFunction()
8714 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8715 MachineMemOperand::MOLoad, 8, 8);
8717 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8718 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8719 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8720 array_lengthof(Ops), MVT::i64, MMO);
8722 APInt FF(32, 0x5F800000ULL);
8724 // Check whether the sign bit is set.
8725 SDValue SignSet = DAG.getSetCC(dl,
8726 getSetCCResultType(*DAG.getContext(), MVT::i64),
8727 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8730 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8731 SDValue FudgePtr = DAG.getConstantPool(
8732 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8735 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8736 SDValue Zero = DAG.getIntPtrConstant(0);
8737 SDValue Four = DAG.getIntPtrConstant(4);
8738 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8740 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8742 // Load the value out, extending it from f32 to f80.
8743 // FIXME: Avoid the extend by constructing the right constant pool?
8744 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8745 FudgePtr, MachinePointerInfo::getConstantPool(),
8746 MVT::f32, false, false, 4);
8747 // Extend everything to 80 bits to force it to be done on x87.
8748 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8749 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8752 std::pair<SDValue,SDValue>
8753 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8754 bool IsSigned, bool IsReplace) const {
8757 EVT DstTy = Op.getValueType();
8759 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8760 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8764 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8765 DstTy.getSimpleVT() >= MVT::i16 &&
8766 "Unknown FP_TO_INT to lower!");
8768 // These are really Legal.
8769 if (DstTy == MVT::i32 &&
8770 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8771 return std::make_pair(SDValue(), SDValue());
8772 if (Subtarget->is64Bit() &&
8773 DstTy == MVT::i64 &&
8774 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8775 return std::make_pair(SDValue(), SDValue());
8777 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8778 // stack slot, or into the FTOL runtime function.
8779 MachineFunction &MF = DAG.getMachineFunction();
8780 unsigned MemSize = DstTy.getSizeInBits()/8;
8781 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8782 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8785 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8786 Opc = X86ISD::WIN_FTOL;
8788 switch (DstTy.getSimpleVT().SimpleTy) {
8789 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8790 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8791 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8792 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8795 SDValue Chain = DAG.getEntryNode();
8796 SDValue Value = Op.getOperand(0);
8797 EVT TheVT = Op.getOperand(0).getValueType();
8798 // FIXME This causes a redundant load/store if the SSE-class value is already
8799 // in memory, such as if it is on the callstack.
8800 if (isScalarFPTypeInSSEReg(TheVT)) {
8801 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8802 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8803 MachinePointerInfo::getFixedStack(SSFI),
8805 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8807 Chain, StackSlot, DAG.getValueType(TheVT)
8810 MachineMemOperand *MMO =
8811 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8812 MachineMemOperand::MOLoad, MemSize, MemSize);
8813 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8814 array_lengthof(Ops), DstTy, MMO);
8815 Chain = Value.getValue(1);
8816 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8817 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8820 MachineMemOperand *MMO =
8821 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8822 MachineMemOperand::MOStore, MemSize, MemSize);
8824 if (Opc != X86ISD::WIN_FTOL) {
8825 // Build the FP_TO_INT*_IN_MEM
8826 SDValue Ops[] = { Chain, Value, StackSlot };
8827 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8828 Ops, array_lengthof(Ops), DstTy,
8830 return std::make_pair(FIST, StackSlot);
8832 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8833 DAG.getVTList(MVT::Other, MVT::Glue),
8835 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8836 MVT::i32, ftol.getValue(1));
8837 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8838 MVT::i32, eax.getValue(2));
8839 SDValue Ops[] = { eax, edx };
8840 SDValue pair = IsReplace
8841 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8842 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8843 return std::make_pair(pair, SDValue());
8847 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8848 const X86Subtarget *Subtarget) {
8849 MVT VT = Op->getSimpleValueType(0);
8850 SDValue In = Op->getOperand(0);
8851 MVT InVT = In.getSimpleValueType();
8854 // Optimize vectors in AVX mode:
8857 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8858 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8859 // Concat upper and lower parts.
8862 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8863 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8864 // Concat upper and lower parts.
8867 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8868 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8871 if (Subtarget->hasInt256())
8872 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8874 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8875 SDValue Undef = DAG.getUNDEF(InVT);
8876 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8877 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8878 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8880 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8881 VT.getVectorNumElements()/2);
8883 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8884 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8886 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8889 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8890 SelectionDAG &DAG) {
8891 MVT VT = Op->getValueType(0).getSimpleVT();
8892 SDValue In = Op->getOperand(0);
8893 MVT InVT = In.getValueType().getSimpleVT();
8895 unsigned int NumElts = VT.getVectorNumElements();
8896 if (NumElts != 8 && NumElts != 16)
8899 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8900 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8902 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8904 // Now we have only mask extension
8905 assert(InVT.getVectorElementType() == MVT::i1);
8906 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8907 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8908 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8909 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8910 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8911 MachinePointerInfo::getConstantPool(),
8912 false, false, false, Alignment);
8914 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8915 if (VT.is512BitVector())
8917 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8920 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8921 SelectionDAG &DAG) {
8922 if (Subtarget->hasFp256()) {
8923 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8931 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8932 SelectionDAG &DAG) {
8934 MVT VT = Op.getSimpleValueType();
8935 SDValue In = Op.getOperand(0);
8936 MVT SVT = In.getSimpleValueType();
8938 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8939 return LowerZERO_EXTEND_AVX512(Op, DAG);
8941 if (Subtarget->hasFp256()) {
8942 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8947 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8948 VT.getVectorNumElements() != SVT.getVectorNumElements())
8951 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8953 // AVX2 has better support of integer extending.
8954 if (Subtarget->hasInt256())
8955 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8957 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8958 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8959 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8960 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8961 DAG.getUNDEF(MVT::v8i16),
8964 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8967 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8969 MVT VT = Op.getSimpleValueType();
8970 SDValue In = Op.getOperand(0);
8971 MVT InVT = In.getSimpleValueType();
8972 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8973 "Invalid TRUNCATE operation");
8975 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
8976 if (VT.getVectorElementType().getSizeInBits() >=8)
8977 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
8979 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
8980 unsigned NumElts = InVT.getVectorNumElements();
8981 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
8982 if (InVT.getSizeInBits() < 512) {
8983 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
8984 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
8987 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
8988 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8989 SDValue CP = DAG.getConstantPool(C, getPointerTy());
8990 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8991 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8992 MachinePointerInfo::getConstantPool(),
8993 false, false, false, Alignment);
8994 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
8995 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
8996 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
8999 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9000 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9001 if (Subtarget->hasInt256()) {
9002 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9003 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9004 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9006 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9007 DAG.getIntPtrConstant(0));
9010 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9011 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9012 DAG.getIntPtrConstant(0));
9013 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9014 DAG.getIntPtrConstant(2));
9016 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9017 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9020 static const int ShufMask1[] = {0, 2, 0, 0};
9021 SDValue Undef = DAG.getUNDEF(VT);
9022 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9023 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9025 // The MOVLHPS mask:
9026 static const int ShufMask2[] = {0, 1, 4, 5};
9027 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9030 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9031 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9032 if (Subtarget->hasInt256()) {
9033 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9035 SmallVector<SDValue,32> pshufbMask;
9036 for (unsigned i = 0; i < 2; ++i) {
9037 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9038 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9039 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9040 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9041 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9042 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9043 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9044 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9045 for (unsigned j = 0; j < 8; ++j)
9046 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9048 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9049 &pshufbMask[0], 32);
9050 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9051 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9053 static const int ShufMask[] = {0, 2, -1, -1};
9054 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9056 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9057 DAG.getIntPtrConstant(0));
9058 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9061 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9062 DAG.getIntPtrConstant(0));
9064 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9065 DAG.getIntPtrConstant(4));
9067 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9068 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9071 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9072 -1, -1, -1, -1, -1, -1, -1, -1};
9074 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9075 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9076 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9078 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9079 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9081 // The MOVLHPS Mask:
9082 static const int ShufMask2[] = {0, 1, 4, 5};
9083 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9084 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9087 // Handle truncation of V256 to V128 using shuffles.
9088 if (!VT.is128BitVector() || !InVT.is256BitVector())
9091 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9093 unsigned NumElems = VT.getVectorNumElements();
9094 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9097 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9098 // Prepare truncation shuffle mask
9099 for (unsigned i = 0; i != NumElems; ++i)
9101 SDValue V = DAG.getVectorShuffle(NVT, DL,
9102 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9103 DAG.getUNDEF(NVT), &MaskVec[0]);
9104 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9105 DAG.getIntPtrConstant(0));
9108 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9109 SelectionDAG &DAG) const {
9110 MVT VT = Op.getSimpleValueType();
9111 if (VT.isVector()) {
9112 if (VT == MVT::v8i16)
9113 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9114 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9115 MVT::v8i32, Op.getOperand(0)));
9119 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9120 /*IsSigned=*/ true, /*IsReplace=*/ false);
9121 SDValue FIST = Vals.first, StackSlot = Vals.second;
9122 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9123 if (FIST.getNode() == 0) return Op;
9125 if (StackSlot.getNode())
9127 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9128 FIST, StackSlot, MachinePointerInfo(),
9129 false, false, false, 0);
9131 // The node is the result.
9135 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9136 SelectionDAG &DAG) const {
9137 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9138 /*IsSigned=*/ false, /*IsReplace=*/ false);
9139 SDValue FIST = Vals.first, StackSlot = Vals.second;
9140 assert(FIST.getNode() && "Unexpected failure");
9142 if (StackSlot.getNode())
9144 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9145 FIST, StackSlot, MachinePointerInfo(),
9146 false, false, false, 0);
9148 // The node is the result.
9152 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9154 MVT VT = Op.getSimpleValueType();
9155 SDValue In = Op.getOperand(0);
9156 MVT SVT = In.getSimpleValueType();
9158 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9160 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9161 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9162 In, DAG.getUNDEF(SVT)));
9165 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9166 LLVMContext *Context = DAG.getContext();
9168 MVT VT = Op.getSimpleValueType();
9170 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9171 if (VT.isVector()) {
9172 EltVT = VT.getVectorElementType();
9173 NumElts = VT.getVectorNumElements();
9176 if (EltVT == MVT::f64)
9177 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9178 APInt(64, ~(1ULL << 63))));
9180 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9181 APInt(32, ~(1U << 31))));
9182 C = ConstantVector::getSplat(NumElts, C);
9183 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9184 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9185 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9186 MachinePointerInfo::getConstantPool(),
9187 false, false, false, Alignment);
9188 if (VT.isVector()) {
9189 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9190 return DAG.getNode(ISD::BITCAST, dl, VT,
9191 DAG.getNode(ISD::AND, dl, ANDVT,
9192 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9194 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9196 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9199 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9200 LLVMContext *Context = DAG.getContext();
9202 MVT VT = Op.getSimpleValueType();
9204 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9205 if (VT.isVector()) {
9206 EltVT = VT.getVectorElementType();
9207 NumElts = VT.getVectorNumElements();
9210 if (EltVT == MVT::f64)
9211 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9212 APInt(64, 1ULL << 63)));
9214 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9215 APInt(32, 1U << 31)));
9216 C = ConstantVector::getSplat(NumElts, C);
9217 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9218 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9219 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9220 MachinePointerInfo::getConstantPool(),
9221 false, false, false, Alignment);
9222 if (VT.isVector()) {
9223 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9224 return DAG.getNode(ISD::BITCAST, dl, VT,
9225 DAG.getNode(ISD::XOR, dl, XORVT,
9226 DAG.getNode(ISD::BITCAST, dl, XORVT,
9228 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9231 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9234 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9235 LLVMContext *Context = DAG.getContext();
9236 SDValue Op0 = Op.getOperand(0);
9237 SDValue Op1 = Op.getOperand(1);
9239 MVT VT = Op.getSimpleValueType();
9240 MVT SrcVT = Op1.getSimpleValueType();
9242 // If second operand is smaller, extend it first.
9243 if (SrcVT.bitsLT(VT)) {
9244 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9247 // And if it is bigger, shrink it first.
9248 if (SrcVT.bitsGT(VT)) {
9249 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9253 // At this point the operands and the result should have the same
9254 // type, and that won't be f80 since that is not custom lowered.
9256 // First get the sign bit of second operand.
9257 SmallVector<Constant*,4> CV;
9258 if (SrcVT == MVT::f64) {
9259 const fltSemantics &Sem = APFloat::IEEEdouble;
9260 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9261 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9263 const fltSemantics &Sem = APFloat::IEEEsingle;
9264 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9265 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9266 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9267 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9269 Constant *C = ConstantVector::get(CV);
9270 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9271 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9272 MachinePointerInfo::getConstantPool(),
9273 false, false, false, 16);
9274 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9276 // Shift sign bit right or left if the two operands have different types.
9277 if (SrcVT.bitsGT(VT)) {
9278 // Op0 is MVT::f32, Op1 is MVT::f64.
9279 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9280 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9281 DAG.getConstant(32, MVT::i32));
9282 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9283 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9284 DAG.getIntPtrConstant(0));
9287 // Clear first operand sign bit.
9289 if (VT == MVT::f64) {
9290 const fltSemantics &Sem = APFloat::IEEEdouble;
9291 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9292 APInt(64, ~(1ULL << 63)))));
9293 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9295 const fltSemantics &Sem = APFloat::IEEEsingle;
9296 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9297 APInt(32, ~(1U << 31)))));
9298 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9299 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9300 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9302 C = ConstantVector::get(CV);
9303 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9304 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9305 MachinePointerInfo::getConstantPool(),
9306 false, false, false, 16);
9307 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9309 // Or the value with the sign bit.
9310 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9313 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9314 SDValue N0 = Op.getOperand(0);
9316 MVT VT = Op.getSimpleValueType();
9318 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9319 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9320 DAG.getConstant(1, VT));
9321 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9324 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9326 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9327 SelectionDAG &DAG) {
9328 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9330 if (!Subtarget->hasSSE41())
9333 if (!Op->hasOneUse())
9336 SDNode *N = Op.getNode();
9339 SmallVector<SDValue, 8> Opnds;
9340 DenseMap<SDValue, unsigned> VecInMap;
9341 EVT VT = MVT::Other;
9343 // Recognize a special case where a vector is casted into wide integer to
9345 Opnds.push_back(N->getOperand(0));
9346 Opnds.push_back(N->getOperand(1));
9348 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9349 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9350 // BFS traverse all OR'd operands.
9351 if (I->getOpcode() == ISD::OR) {
9352 Opnds.push_back(I->getOperand(0));
9353 Opnds.push_back(I->getOperand(1));
9354 // Re-evaluate the number of nodes to be traversed.
9355 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9359 // Quit if a non-EXTRACT_VECTOR_ELT
9360 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9363 // Quit if without a constant index.
9364 SDValue Idx = I->getOperand(1);
9365 if (!isa<ConstantSDNode>(Idx))
9368 SDValue ExtractedFromVec = I->getOperand(0);
9369 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9370 if (M == VecInMap.end()) {
9371 VT = ExtractedFromVec.getValueType();
9372 // Quit if not 128/256-bit vector.
9373 if (!VT.is128BitVector() && !VT.is256BitVector())
9375 // Quit if not the same type.
9376 if (VecInMap.begin() != VecInMap.end() &&
9377 VT != VecInMap.begin()->first.getValueType())
9379 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9381 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9384 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9385 "Not extracted from 128-/256-bit vector.");
9387 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9388 SmallVector<SDValue, 8> VecIns;
9390 for (DenseMap<SDValue, unsigned>::const_iterator
9391 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9392 // Quit if not all elements are used.
9393 if (I->second != FullMask)
9395 VecIns.push_back(I->first);
9398 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9400 // Cast all vectors into TestVT for PTEST.
9401 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9402 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9404 // If more than one full vectors are evaluated, OR them first before PTEST.
9405 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9406 // Each iteration will OR 2 nodes and append the result until there is only
9407 // 1 node left, i.e. the final OR'd value of all vectors.
9408 SDValue LHS = VecIns[Slot];
9409 SDValue RHS = VecIns[Slot + 1];
9410 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9413 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9414 VecIns.back(), VecIns.back());
9417 /// Emit nodes that will be selected as "test Op0,Op0", or something
9419 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9420 SelectionDAG &DAG) const {
9423 // CF and OF aren't always set the way we want. Determine which
9424 // of these we need.
9425 bool NeedCF = false;
9426 bool NeedOF = false;
9429 case X86::COND_A: case X86::COND_AE:
9430 case X86::COND_B: case X86::COND_BE:
9433 case X86::COND_G: case X86::COND_GE:
9434 case X86::COND_L: case X86::COND_LE:
9435 case X86::COND_O: case X86::COND_NO:
9440 // See if we can use the EFLAGS value from the operand instead of
9441 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9442 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9443 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9444 // Emit a CMP with 0, which is the TEST pattern.
9445 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9446 DAG.getConstant(0, Op.getValueType()));
9448 unsigned Opcode = 0;
9449 unsigned NumOperands = 0;
9451 // Truncate operations may prevent the merge of the SETCC instruction
9452 // and the arithmetic instruction before it. Attempt to truncate the operands
9453 // of the arithmetic instruction and use a reduced bit-width instruction.
9454 bool NeedTruncation = false;
9455 SDValue ArithOp = Op;
9456 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9457 SDValue Arith = Op->getOperand(0);
9458 // Both the trunc and the arithmetic op need to have one user each.
9459 if (Arith->hasOneUse())
9460 switch (Arith.getOpcode()) {
9467 NeedTruncation = true;
9473 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9474 // which may be the result of a CAST. We use the variable 'Op', which is the
9475 // non-casted variable when we check for possible users.
9476 switch (ArithOp.getOpcode()) {
9478 // Due to an isel shortcoming, be conservative if this add is likely to be
9479 // selected as part of a load-modify-store instruction. When the root node
9480 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9481 // uses of other nodes in the match, such as the ADD in this case. This
9482 // leads to the ADD being left around and reselected, with the result being
9483 // two adds in the output. Alas, even if none our users are stores, that
9484 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9485 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9486 // climbing the DAG back to the root, and it doesn't seem to be worth the
9488 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9489 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9490 if (UI->getOpcode() != ISD::CopyToReg &&
9491 UI->getOpcode() != ISD::SETCC &&
9492 UI->getOpcode() != ISD::STORE)
9495 if (ConstantSDNode *C =
9496 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9497 // An add of one will be selected as an INC.
9498 if (C->getAPIntValue() == 1) {
9499 Opcode = X86ISD::INC;
9504 // An add of negative one (subtract of one) will be selected as a DEC.
9505 if (C->getAPIntValue().isAllOnesValue()) {
9506 Opcode = X86ISD::DEC;
9512 // Otherwise use a regular EFLAGS-setting add.
9513 Opcode = X86ISD::ADD;
9517 // If the primary and result isn't used, don't bother using X86ISD::AND,
9518 // because a TEST instruction will be better.
9519 bool NonFlagUse = false;
9520 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9521 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9523 unsigned UOpNo = UI.getOperandNo();
9524 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9525 // Look pass truncate.
9526 UOpNo = User->use_begin().getOperandNo();
9527 User = *User->use_begin();
9530 if (User->getOpcode() != ISD::BRCOND &&
9531 User->getOpcode() != ISD::SETCC &&
9532 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9545 // Due to the ISEL shortcoming noted above, be conservative if this op is
9546 // likely to be selected as part of a load-modify-store instruction.
9547 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9548 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9549 if (UI->getOpcode() == ISD::STORE)
9552 // Otherwise use a regular EFLAGS-setting instruction.
9553 switch (ArithOp.getOpcode()) {
9554 default: llvm_unreachable("unexpected operator!");
9555 case ISD::SUB: Opcode = X86ISD::SUB; break;
9556 case ISD::XOR: Opcode = X86ISD::XOR; break;
9557 case ISD::AND: Opcode = X86ISD::AND; break;
9559 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9560 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9561 if (EFLAGS.getNode())
9564 Opcode = X86ISD::OR;
9578 return SDValue(Op.getNode(), 1);
9584 // If we found that truncation is beneficial, perform the truncation and
9586 if (NeedTruncation) {
9587 EVT VT = Op.getValueType();
9588 SDValue WideVal = Op->getOperand(0);
9589 EVT WideVT = WideVal.getValueType();
9590 unsigned ConvertedOp = 0;
9591 // Use a target machine opcode to prevent further DAGCombine
9592 // optimizations that may separate the arithmetic operations
9593 // from the setcc node.
9594 switch (WideVal.getOpcode()) {
9596 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9597 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9598 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9599 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9600 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9604 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9605 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9606 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9607 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9608 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9614 // Emit a CMP with 0, which is the TEST pattern.
9615 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9616 DAG.getConstant(0, Op.getValueType()));
9618 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9619 SmallVector<SDValue, 4> Ops;
9620 for (unsigned i = 0; i != NumOperands; ++i)
9621 Ops.push_back(Op.getOperand(i));
9623 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9624 DAG.ReplaceAllUsesWith(Op, New);
9625 return SDValue(New.getNode(), 1);
9628 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9630 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9631 SelectionDAG &DAG) const {
9632 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9633 if (C->getAPIntValue() == 0)
9634 return EmitTest(Op0, X86CC, DAG);
9637 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9638 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9639 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9640 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9641 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9643 return SDValue(Sub.getNode(), 1);
9645 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9648 /// Convert a comparison if required by the subtarget.
9649 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9650 SelectionDAG &DAG) const {
9651 // If the subtarget does not support the FUCOMI instruction, floating-point
9652 // comparisons have to be converted.
9653 if (Subtarget->hasCMov() ||
9654 Cmp.getOpcode() != X86ISD::CMP ||
9655 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9656 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9659 // The instruction selector will select an FUCOM instruction instead of
9660 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9661 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9662 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9664 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9665 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9666 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9667 DAG.getConstant(8, MVT::i8));
9668 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9669 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9672 static bool isAllOnes(SDValue V) {
9673 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9674 return C && C->isAllOnesValue();
9677 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9678 /// if it's possible.
9679 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9680 SDLoc dl, SelectionDAG &DAG) const {
9681 SDValue Op0 = And.getOperand(0);
9682 SDValue Op1 = And.getOperand(1);
9683 if (Op0.getOpcode() == ISD::TRUNCATE)
9684 Op0 = Op0.getOperand(0);
9685 if (Op1.getOpcode() == ISD::TRUNCATE)
9686 Op1 = Op1.getOperand(0);
9689 if (Op1.getOpcode() == ISD::SHL)
9690 std::swap(Op0, Op1);
9691 if (Op0.getOpcode() == ISD::SHL) {
9692 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9693 if (And00C->getZExtValue() == 1) {
9694 // If we looked past a truncate, check that it's only truncating away
9696 unsigned BitWidth = Op0.getValueSizeInBits();
9697 unsigned AndBitWidth = And.getValueSizeInBits();
9698 if (BitWidth > AndBitWidth) {
9700 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9701 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9705 RHS = Op0.getOperand(1);
9707 } else if (Op1.getOpcode() == ISD::Constant) {
9708 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9709 uint64_t AndRHSVal = AndRHS->getZExtValue();
9710 SDValue AndLHS = Op0;
9712 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9713 LHS = AndLHS.getOperand(0);
9714 RHS = AndLHS.getOperand(1);
9717 // Use BT if the immediate can't be encoded in a TEST instruction.
9718 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9720 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9724 if (LHS.getNode()) {
9725 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9726 // instruction. Since the shift amount is in-range-or-undefined, we know
9727 // that doing a bittest on the i32 value is ok. We extend to i32 because
9728 // the encoding for the i16 version is larger than the i32 version.
9729 // Also promote i16 to i32 for performance / code size reason.
9730 if (LHS.getValueType() == MVT::i8 ||
9731 LHS.getValueType() == MVT::i16)
9732 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9734 // If the operand types disagree, extend the shift amount to match. Since
9735 // BT ignores high bits (like shifts) we can use anyextend.
9736 if (LHS.getValueType() != RHS.getValueType())
9737 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9739 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9740 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9741 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9742 DAG.getConstant(Cond, MVT::i8), BT);
9748 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9750 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9755 // SSE Condition code mapping:
9764 switch (SetCCOpcode) {
9765 default: llvm_unreachable("Unexpected SETCC condition");
9767 case ISD::SETEQ: SSECC = 0; break;
9769 case ISD::SETGT: Swap = true; // Fallthrough
9771 case ISD::SETOLT: SSECC = 1; break;
9773 case ISD::SETGE: Swap = true; // Fallthrough
9775 case ISD::SETOLE: SSECC = 2; break;
9776 case ISD::SETUO: SSECC = 3; break;
9778 case ISD::SETNE: SSECC = 4; break;
9779 case ISD::SETULE: Swap = true; // Fallthrough
9780 case ISD::SETUGE: SSECC = 5; break;
9781 case ISD::SETULT: Swap = true; // Fallthrough
9782 case ISD::SETUGT: SSECC = 6; break;
9783 case ISD::SETO: SSECC = 7; break;
9785 case ISD::SETONE: SSECC = 8; break;
9788 std::swap(Op0, Op1);
9793 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9794 // ones, and then concatenate the result back.
9795 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9796 MVT VT = Op.getSimpleValueType();
9798 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9799 "Unsupported value type for operation");
9801 unsigned NumElems = VT.getVectorNumElements();
9803 SDValue CC = Op.getOperand(2);
9805 // Extract the LHS vectors
9806 SDValue LHS = Op.getOperand(0);
9807 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9808 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9810 // Extract the RHS vectors
9811 SDValue RHS = Op.getOperand(1);
9812 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9813 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9815 // Issue the operation on the smaller types and concatenate the result back
9816 MVT EltVT = VT.getVectorElementType();
9817 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9818 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9819 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9820 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9823 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9824 SDValue Op0 = Op.getOperand(0);
9825 SDValue Op1 = Op.getOperand(1);
9826 SDValue CC = Op.getOperand(2);
9827 MVT VT = Op.getSimpleValueType();
9829 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9830 Op.getValueType().getScalarType() == MVT::i1 &&
9831 "Cannot set masked compare for this operation");
9833 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9836 bool Unsigned = false;
9838 switch (SetCCOpcode) {
9839 default: llvm_unreachable("Unexpected SETCC condition");
9840 case ISD::SETNE: SSECC = 4; break;
9841 case ISD::SETEQ: SSECC = 0; break;
9842 case ISD::SETUGT: Unsigned = true;
9843 case ISD::SETGT: SSECC = 6; break; // NLE
9844 case ISD::SETULT: Unsigned = true;
9845 case ISD::SETLT: SSECC = 1; break;
9846 case ISD::SETUGE: Unsigned = true;
9847 case ISD::SETGE: SSECC = 5; break; // NLT
9848 case ISD::SETULE: Unsigned = true;
9849 case ISD::SETLE: SSECC = 2; break;
9851 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9852 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9853 DAG.getConstant(SSECC, MVT::i8));
9857 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9858 SelectionDAG &DAG) {
9859 SDValue Op0 = Op.getOperand(0);
9860 SDValue Op1 = Op.getOperand(1);
9861 SDValue CC = Op.getOperand(2);
9862 MVT VT = Op.getSimpleValueType();
9863 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9864 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9869 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9870 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9873 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9874 unsigned Opc = X86ISD::CMPP;
9875 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9876 assert(VT.getVectorNumElements() <= 16);
9879 // In the two special cases we can't handle, emit two comparisons.
9882 unsigned CombineOpc;
9883 if (SetCCOpcode == ISD::SETUEQ) {
9884 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9886 assert(SetCCOpcode == ISD::SETONE);
9887 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9890 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9891 DAG.getConstant(CC0, MVT::i8));
9892 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9893 DAG.getConstant(CC1, MVT::i8));
9894 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9896 // Handle all other FP comparisons here.
9897 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9898 DAG.getConstant(SSECC, MVT::i8));
9901 // Break 256-bit integer vector compare into smaller ones.
9902 if (VT.is256BitVector() && !Subtarget->hasInt256())
9903 return Lower256IntVSETCC(Op, DAG);
9905 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9906 EVT OpVT = Op1.getValueType();
9907 if (Subtarget->hasAVX512()) {
9908 if (Op1.getValueType().is512BitVector() ||
9909 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9910 return LowerIntVSETCC_AVX512(Op, DAG);
9912 // In AVX-512 architecture setcc returns mask with i1 elements,
9913 // But there is no compare instruction for i8 and i16 elements.
9914 // We are not talking about 512-bit operands in this case, these
9915 // types are illegal.
9917 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9918 OpVT.getVectorElementType().getSizeInBits() >= 8))
9919 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9920 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9923 // We are handling one of the integer comparisons here. Since SSE only has
9924 // GT and EQ comparisons for integer, swapping operands and multiple
9925 // operations may be required for some comparisons.
9927 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9929 switch (SetCCOpcode) {
9930 default: llvm_unreachable("Unexpected SETCC condition");
9931 case ISD::SETNE: Invert = true;
9932 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9933 case ISD::SETLT: Swap = true;
9934 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9935 case ISD::SETGE: Swap = true;
9936 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9937 Invert = true; break;
9938 case ISD::SETULT: Swap = true;
9939 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9940 FlipSigns = true; break;
9941 case ISD::SETUGE: Swap = true;
9942 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9943 FlipSigns = true; Invert = true; break;
9946 // Special case: Use min/max operations for SETULE/SETUGE
9947 MVT VET = VT.getVectorElementType();
9949 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9950 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9953 switch (SetCCOpcode) {
9955 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9956 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9959 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9963 std::swap(Op0, Op1);
9965 // Check that the operation in question is available (most are plain SSE2,
9966 // but PCMPGTQ and PCMPEQQ have different requirements).
9967 if (VT == MVT::v2i64) {
9968 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9969 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9971 // First cast everything to the right type.
9972 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9973 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9975 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9976 // bits of the inputs before performing those operations. The lower
9977 // compare is always unsigned.
9980 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9982 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9983 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9984 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9985 Sign, Zero, Sign, Zero);
9987 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9988 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9990 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9991 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9992 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9994 // Create masks for only the low parts/high parts of the 64 bit integers.
9995 static const int MaskHi[] = { 1, 1, 3, 3 };
9996 static const int MaskLo[] = { 0, 0, 2, 2 };
9997 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9998 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9999 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10001 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10002 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10005 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10007 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10010 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10011 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10012 // pcmpeqd + pshufd + pand.
10013 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10015 // First cast everything to the right type.
10016 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10017 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10020 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10022 // Make sure the lower and upper halves are both all-ones.
10023 static const int Mask[] = { 1, 0, 3, 2 };
10024 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10025 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10028 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10030 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10034 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10035 // bits of the inputs before performing those operations.
10037 EVT EltVT = VT.getVectorElementType();
10038 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10039 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10040 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10043 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10045 // If the logical-not of the result is required, perform that now.
10047 Result = DAG.getNOT(dl, Result, VT);
10050 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10055 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10057 MVT VT = Op.getSimpleValueType();
10059 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10061 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10062 SDValue Op0 = Op.getOperand(0);
10063 SDValue Op1 = Op.getOperand(1);
10065 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10067 // Optimize to BT if possible.
10068 // Lower (X & (1 << N)) == 0 to BT(X, N).
10069 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10070 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10071 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10072 Op1.getOpcode() == ISD::Constant &&
10073 cast<ConstantSDNode>(Op1)->isNullValue() &&
10074 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10075 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10076 if (NewSetCC.getNode())
10080 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10082 if (Op1.getOpcode() == ISD::Constant &&
10083 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10084 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10085 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10087 // If the input is a setcc, then reuse the input setcc or use a new one with
10088 // the inverted condition.
10089 if (Op0.getOpcode() == X86ISD::SETCC) {
10090 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10091 bool Invert = (CC == ISD::SETNE) ^
10092 cast<ConstantSDNode>(Op1)->isNullValue();
10093 if (!Invert) return Op0;
10095 CCode = X86::GetOppositeBranchCondition(CCode);
10096 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10097 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10101 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10102 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10103 if (X86CC == X86::COND_INVALID)
10106 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10107 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10108 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10109 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10112 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10113 static bool isX86LogicalCmp(SDValue Op) {
10114 unsigned Opc = Op.getNode()->getOpcode();
10115 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10116 Opc == X86ISD::SAHF)
10118 if (Op.getResNo() == 1 &&
10119 (Opc == X86ISD::ADD ||
10120 Opc == X86ISD::SUB ||
10121 Opc == X86ISD::ADC ||
10122 Opc == X86ISD::SBB ||
10123 Opc == X86ISD::SMUL ||
10124 Opc == X86ISD::UMUL ||
10125 Opc == X86ISD::INC ||
10126 Opc == X86ISD::DEC ||
10127 Opc == X86ISD::OR ||
10128 Opc == X86ISD::XOR ||
10129 Opc == X86ISD::AND))
10132 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10138 static bool isZero(SDValue V) {
10139 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10140 return C && C->isNullValue();
10143 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10144 if (V.getOpcode() != ISD::TRUNCATE)
10147 SDValue VOp0 = V.getOperand(0);
10148 unsigned InBits = VOp0.getValueSizeInBits();
10149 unsigned Bits = V.getValueSizeInBits();
10150 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10153 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10154 bool addTest = true;
10155 SDValue Cond = Op.getOperand(0);
10156 SDValue Op1 = Op.getOperand(1);
10157 SDValue Op2 = Op.getOperand(2);
10159 EVT VT = Op1.getValueType();
10162 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10163 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10164 // sequence later on.
10165 if (Cond.getOpcode() == ISD::SETCC &&
10166 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10167 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10168 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10169 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10170 int SSECC = translateX86FSETCC(
10171 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10174 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10175 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10176 DAG.getConstant(SSECC, MVT::i8));
10177 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10178 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10179 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10183 if (Cond.getOpcode() == ISD::SETCC) {
10184 SDValue NewCond = LowerSETCC(Cond, DAG);
10185 if (NewCond.getNode())
10189 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10190 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10191 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10192 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10193 if (Cond.getOpcode() == X86ISD::SETCC &&
10194 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10195 isZero(Cond.getOperand(1).getOperand(1))) {
10196 SDValue Cmp = Cond.getOperand(1);
10198 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10200 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10201 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10202 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10204 SDValue CmpOp0 = Cmp.getOperand(0);
10205 // Apply further optimizations for special cases
10206 // (select (x != 0), -1, 0) -> neg & sbb
10207 // (select (x == 0), 0, -1) -> neg & sbb
10208 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10209 if (YC->isNullValue() &&
10210 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10211 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10212 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10213 DAG.getConstant(0, CmpOp0.getValueType()),
10215 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10216 DAG.getConstant(X86::COND_B, MVT::i8),
10217 SDValue(Neg.getNode(), 1));
10221 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10222 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10223 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10225 SDValue Res = // Res = 0 or -1.
10226 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10227 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10229 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10230 Res = DAG.getNOT(DL, Res, Res.getValueType());
10232 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10233 if (N2C == 0 || !N2C->isNullValue())
10234 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10239 // Look past (and (setcc_carry (cmp ...)), 1).
10240 if (Cond.getOpcode() == ISD::AND &&
10241 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10242 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10243 if (C && C->getAPIntValue() == 1)
10244 Cond = Cond.getOperand(0);
10247 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10248 // setting operand in place of the X86ISD::SETCC.
10249 unsigned CondOpcode = Cond.getOpcode();
10250 if (CondOpcode == X86ISD::SETCC ||
10251 CondOpcode == X86ISD::SETCC_CARRY) {
10252 CC = Cond.getOperand(0);
10254 SDValue Cmp = Cond.getOperand(1);
10255 unsigned Opc = Cmp.getOpcode();
10256 MVT VT = Op.getSimpleValueType();
10258 bool IllegalFPCMov = false;
10259 if (VT.isFloatingPoint() && !VT.isVector() &&
10260 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10261 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10263 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10264 Opc == X86ISD::BT) { // FIXME
10268 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10269 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10270 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10271 Cond.getOperand(0).getValueType() != MVT::i8)) {
10272 SDValue LHS = Cond.getOperand(0);
10273 SDValue RHS = Cond.getOperand(1);
10274 unsigned X86Opcode;
10277 switch (CondOpcode) {
10278 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10279 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10280 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10281 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10282 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10283 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10284 default: llvm_unreachable("unexpected overflowing operator");
10286 if (CondOpcode == ISD::UMULO)
10287 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10290 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10292 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10294 if (CondOpcode == ISD::UMULO)
10295 Cond = X86Op.getValue(2);
10297 Cond = X86Op.getValue(1);
10299 CC = DAG.getConstant(X86Cond, MVT::i8);
10304 // Look pass the truncate if the high bits are known zero.
10305 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10306 Cond = Cond.getOperand(0);
10308 // We know the result of AND is compared against zero. Try to match
10310 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10311 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10312 if (NewSetCC.getNode()) {
10313 CC = NewSetCC.getOperand(0);
10314 Cond = NewSetCC.getOperand(1);
10321 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10322 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10325 // a < b ? -1 : 0 -> RES = ~setcc_carry
10326 // a < b ? 0 : -1 -> RES = setcc_carry
10327 // a >= b ? -1 : 0 -> RES = setcc_carry
10328 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10329 if (Cond.getOpcode() == X86ISD::SUB) {
10330 Cond = ConvertCmpIfNecessary(Cond, DAG);
10331 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10333 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10334 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10335 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10336 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10337 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10338 return DAG.getNOT(DL, Res, Res.getValueType());
10343 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10344 // widen the cmov and push the truncate through. This avoids introducing a new
10345 // branch during isel and doesn't add any extensions.
10346 if (Op.getValueType() == MVT::i8 &&
10347 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10348 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10349 if (T1.getValueType() == T2.getValueType() &&
10350 // Blacklist CopyFromReg to avoid partial register stalls.
10351 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10352 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10353 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10354 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10358 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10359 // condition is true.
10360 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10361 SDValue Ops[] = { Op2, Op1, CC, Cond };
10362 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10365 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10366 MVT VT = Op->getSimpleValueType(0);
10367 SDValue In = Op->getOperand(0);
10368 MVT InVT = In.getSimpleValueType();
10371 unsigned int NumElts = VT.getVectorNumElements();
10372 if (NumElts != 8 && NumElts != 16)
10375 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10376 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10378 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10379 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10381 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10382 Constant *C = ConstantInt::get(*DAG.getContext(),
10383 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10385 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10386 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10387 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10388 MachinePointerInfo::getConstantPool(),
10389 false, false, false, Alignment);
10390 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10391 if (VT.is512BitVector())
10393 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10396 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10397 SelectionDAG &DAG) {
10398 MVT VT = Op->getSimpleValueType(0);
10399 SDValue In = Op->getOperand(0);
10400 MVT InVT = In.getSimpleValueType();
10403 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10404 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10406 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10407 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10410 if (Subtarget->hasInt256())
10411 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10413 // Optimize vectors in AVX mode
10414 // Sign extend v8i16 to v8i32 and
10417 // Divide input vector into two parts
10418 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10419 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10420 // concat the vectors to original VT
10422 unsigned NumElems = InVT.getVectorNumElements();
10423 SDValue Undef = DAG.getUNDEF(InVT);
10425 SmallVector<int,8> ShufMask1(NumElems, -1);
10426 for (unsigned i = 0; i != NumElems/2; ++i)
10429 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10431 SmallVector<int,8> ShufMask2(NumElems, -1);
10432 for (unsigned i = 0; i != NumElems/2; ++i)
10433 ShufMask2[i] = i + NumElems/2;
10435 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10437 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10438 VT.getVectorNumElements()/2);
10440 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10441 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10443 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10446 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10447 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10448 // from the AND / OR.
10449 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10450 Opc = Op.getOpcode();
10451 if (Opc != ISD::OR && Opc != ISD::AND)
10453 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10454 Op.getOperand(0).hasOneUse() &&
10455 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10456 Op.getOperand(1).hasOneUse());
10459 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10460 // 1 and that the SETCC node has a single use.
10461 static bool isXor1OfSetCC(SDValue Op) {
10462 if (Op.getOpcode() != ISD::XOR)
10464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10465 if (N1C && N1C->getAPIntValue() == 1) {
10466 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10467 Op.getOperand(0).hasOneUse();
10472 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10473 bool addTest = true;
10474 SDValue Chain = Op.getOperand(0);
10475 SDValue Cond = Op.getOperand(1);
10476 SDValue Dest = Op.getOperand(2);
10479 bool Inverted = false;
10481 if (Cond.getOpcode() == ISD::SETCC) {
10482 // Check for setcc([su]{add,sub,mul}o == 0).
10483 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10484 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10485 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10486 Cond.getOperand(0).getResNo() == 1 &&
10487 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10488 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10489 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10490 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10491 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10492 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10494 Cond = Cond.getOperand(0);
10496 SDValue NewCond = LowerSETCC(Cond, DAG);
10497 if (NewCond.getNode())
10502 // FIXME: LowerXALUO doesn't handle these!!
10503 else if (Cond.getOpcode() == X86ISD::ADD ||
10504 Cond.getOpcode() == X86ISD::SUB ||
10505 Cond.getOpcode() == X86ISD::SMUL ||
10506 Cond.getOpcode() == X86ISD::UMUL)
10507 Cond = LowerXALUO(Cond, DAG);
10510 // Look pass (and (setcc_carry (cmp ...)), 1).
10511 if (Cond.getOpcode() == ISD::AND &&
10512 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10513 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10514 if (C && C->getAPIntValue() == 1)
10515 Cond = Cond.getOperand(0);
10518 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10519 // setting operand in place of the X86ISD::SETCC.
10520 unsigned CondOpcode = Cond.getOpcode();
10521 if (CondOpcode == X86ISD::SETCC ||
10522 CondOpcode == X86ISD::SETCC_CARRY) {
10523 CC = Cond.getOperand(0);
10525 SDValue Cmp = Cond.getOperand(1);
10526 unsigned Opc = Cmp.getOpcode();
10527 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10528 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10532 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10536 // These can only come from an arithmetic instruction with overflow,
10537 // e.g. SADDO, UADDO.
10538 Cond = Cond.getNode()->getOperand(1);
10544 CondOpcode = Cond.getOpcode();
10545 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10546 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10547 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10548 Cond.getOperand(0).getValueType() != MVT::i8)) {
10549 SDValue LHS = Cond.getOperand(0);
10550 SDValue RHS = Cond.getOperand(1);
10551 unsigned X86Opcode;
10554 switch (CondOpcode) {
10555 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10556 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10557 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10558 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10559 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10560 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10561 default: llvm_unreachable("unexpected overflowing operator");
10564 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10565 if (CondOpcode == ISD::UMULO)
10566 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10569 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10571 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10573 if (CondOpcode == ISD::UMULO)
10574 Cond = X86Op.getValue(2);
10576 Cond = X86Op.getValue(1);
10578 CC = DAG.getConstant(X86Cond, MVT::i8);
10582 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10583 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10584 if (CondOpc == ISD::OR) {
10585 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10586 // two branches instead of an explicit OR instruction with a
10588 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10589 isX86LogicalCmp(Cmp)) {
10590 CC = Cond.getOperand(0).getOperand(0);
10591 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10592 Chain, Dest, CC, Cmp);
10593 CC = Cond.getOperand(1).getOperand(0);
10597 } else { // ISD::AND
10598 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10599 // two branches instead of an explicit AND instruction with a
10600 // separate test. However, we only do this if this block doesn't
10601 // have a fall-through edge, because this requires an explicit
10602 // jmp when the condition is false.
10603 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10604 isX86LogicalCmp(Cmp) &&
10605 Op.getNode()->hasOneUse()) {
10606 X86::CondCode CCode =
10607 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10608 CCode = X86::GetOppositeBranchCondition(CCode);
10609 CC = DAG.getConstant(CCode, MVT::i8);
10610 SDNode *User = *Op.getNode()->use_begin();
10611 // Look for an unconditional branch following this conditional branch.
10612 // We need this because we need to reverse the successors in order
10613 // to implement FCMP_OEQ.
10614 if (User->getOpcode() == ISD::BR) {
10615 SDValue FalseBB = User->getOperand(1);
10617 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10618 assert(NewBR == User);
10622 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10623 Chain, Dest, CC, Cmp);
10624 X86::CondCode CCode =
10625 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10626 CCode = X86::GetOppositeBranchCondition(CCode);
10627 CC = DAG.getConstant(CCode, MVT::i8);
10633 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10634 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10635 // It should be transformed during dag combiner except when the condition
10636 // is set by a arithmetics with overflow node.
10637 X86::CondCode CCode =
10638 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10639 CCode = X86::GetOppositeBranchCondition(CCode);
10640 CC = DAG.getConstant(CCode, MVT::i8);
10641 Cond = Cond.getOperand(0).getOperand(1);
10643 } else if (Cond.getOpcode() == ISD::SETCC &&
10644 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10645 // For FCMP_OEQ, we can emit
10646 // two branches instead of an explicit AND instruction with a
10647 // separate test. However, we only do this if this block doesn't
10648 // have a fall-through edge, because this requires an explicit
10649 // jmp when the condition is false.
10650 if (Op.getNode()->hasOneUse()) {
10651 SDNode *User = *Op.getNode()->use_begin();
10652 // Look for an unconditional branch following this conditional branch.
10653 // We need this because we need to reverse the successors in order
10654 // to implement FCMP_OEQ.
10655 if (User->getOpcode() == ISD::BR) {
10656 SDValue FalseBB = User->getOperand(1);
10658 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10659 assert(NewBR == User);
10663 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10664 Cond.getOperand(0), Cond.getOperand(1));
10665 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10666 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10667 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10668 Chain, Dest, CC, Cmp);
10669 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10674 } else if (Cond.getOpcode() == ISD::SETCC &&
10675 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10676 // For FCMP_UNE, we can emit
10677 // two branches instead of an explicit AND instruction with a
10678 // separate test. However, we only do this if this block doesn't
10679 // have a fall-through edge, because this requires an explicit
10680 // jmp when the condition is false.
10681 if (Op.getNode()->hasOneUse()) {
10682 SDNode *User = *Op.getNode()->use_begin();
10683 // Look for an unconditional branch following this conditional branch.
10684 // We need this because we need to reverse the successors in order
10685 // to implement FCMP_UNE.
10686 if (User->getOpcode() == ISD::BR) {
10687 SDValue FalseBB = User->getOperand(1);
10689 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10690 assert(NewBR == User);
10693 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10694 Cond.getOperand(0), Cond.getOperand(1));
10695 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10696 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10697 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10698 Chain, Dest, CC, Cmp);
10699 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10709 // Look pass the truncate if the high bits are known zero.
10710 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10711 Cond = Cond.getOperand(0);
10713 // We know the result of AND is compared against zero. Try to match
10715 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10716 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10717 if (NewSetCC.getNode()) {
10718 CC = NewSetCC.getOperand(0);
10719 Cond = NewSetCC.getOperand(1);
10726 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10727 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10729 Cond = ConvertCmpIfNecessary(Cond, DAG);
10730 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10731 Chain, Dest, CC, Cond);
10734 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10735 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10736 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10737 // that the guard pages used by the OS virtual memory manager are allocated in
10738 // correct sequence.
10740 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10741 SelectionDAG &DAG) const {
10742 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10743 getTargetMachine().Options.EnableSegmentedStacks) &&
10744 "This should be used only on Windows targets or when segmented stacks "
10746 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10750 SDValue Chain = Op.getOperand(0);
10751 SDValue Size = Op.getOperand(1);
10752 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10753 EVT VT = Op.getNode()->getValueType(0);
10755 bool Is64Bit = Subtarget->is64Bit();
10756 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10758 if (getTargetMachine().Options.EnableSegmentedStacks) {
10759 MachineFunction &MF = DAG.getMachineFunction();
10760 MachineRegisterInfo &MRI = MF.getRegInfo();
10763 // The 64 bit implementation of segmented stacks needs to clobber both r10
10764 // r11. This makes it impossible to use it along with nested parameters.
10765 const Function *F = MF.getFunction();
10767 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10769 if (I->hasNestAttr())
10770 report_fatal_error("Cannot use segmented stacks with functions that "
10771 "have nested arguments.");
10774 const TargetRegisterClass *AddrRegClass =
10775 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10776 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10777 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10778 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10779 DAG.getRegister(Vreg, SPTy));
10780 SDValue Ops1[2] = { Value, Chain };
10781 return DAG.getMergeValues(Ops1, 2, dl);
10784 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10786 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10787 Flag = Chain.getValue(1);
10788 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10790 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10792 const X86RegisterInfo *RegInfo =
10793 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10794 unsigned SPReg = RegInfo->getStackRegister();
10795 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10796 Chain = SP.getValue(1);
10799 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10800 DAG.getConstant(-(uint64_t)Align, VT));
10801 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10804 SDValue Ops1[2] = { SP, Chain };
10805 return DAG.getMergeValues(Ops1, 2, dl);
10809 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10810 MachineFunction &MF = DAG.getMachineFunction();
10811 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10813 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10816 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10817 // vastart just stores the address of the VarArgsFrameIndex slot into the
10818 // memory location argument.
10819 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10821 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10822 MachinePointerInfo(SV), false, false, 0);
10826 // gp_offset (0 - 6 * 8)
10827 // fp_offset (48 - 48 + 8 * 16)
10828 // overflow_arg_area (point to parameters coming in memory).
10830 SmallVector<SDValue, 8> MemOps;
10831 SDValue FIN = Op.getOperand(1);
10833 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10834 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10836 FIN, MachinePointerInfo(SV), false, false, 0);
10837 MemOps.push_back(Store);
10840 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10841 FIN, DAG.getIntPtrConstant(4));
10842 Store = DAG.getStore(Op.getOperand(0), DL,
10843 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10845 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10846 MemOps.push_back(Store);
10848 // Store ptr to overflow_arg_area
10849 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10850 FIN, DAG.getIntPtrConstant(4));
10851 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10853 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10854 MachinePointerInfo(SV, 8),
10856 MemOps.push_back(Store);
10858 // Store ptr to reg_save_area.
10859 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10860 FIN, DAG.getIntPtrConstant(8));
10861 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10863 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10864 MachinePointerInfo(SV, 16), false, false, 0);
10865 MemOps.push_back(Store);
10866 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10867 &MemOps[0], MemOps.size());
10870 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10871 assert(Subtarget->is64Bit() &&
10872 "LowerVAARG only handles 64-bit va_arg!");
10873 assert((Subtarget->isTargetLinux() ||
10874 Subtarget->isTargetDarwin()) &&
10875 "Unhandled target in LowerVAARG");
10876 assert(Op.getNode()->getNumOperands() == 4);
10877 SDValue Chain = Op.getOperand(0);
10878 SDValue SrcPtr = Op.getOperand(1);
10879 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10880 unsigned Align = Op.getConstantOperandVal(3);
10883 EVT ArgVT = Op.getNode()->getValueType(0);
10884 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10885 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10888 // Decide which area this value should be read from.
10889 // TODO: Implement the AMD64 ABI in its entirety. This simple
10890 // selection mechanism works only for the basic types.
10891 if (ArgVT == MVT::f80) {
10892 llvm_unreachable("va_arg for f80 not yet implemented");
10893 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10894 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10895 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10896 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10898 llvm_unreachable("Unhandled argument type in LowerVAARG");
10901 if (ArgMode == 2) {
10902 // Sanity Check: Make sure using fp_offset makes sense.
10903 assert(!getTargetMachine().Options.UseSoftFloat &&
10904 !(DAG.getMachineFunction()
10905 .getFunction()->getAttributes()
10906 .hasAttribute(AttributeSet::FunctionIndex,
10907 Attribute::NoImplicitFloat)) &&
10908 Subtarget->hasSSE1());
10911 // Insert VAARG_64 node into the DAG
10912 // VAARG_64 returns two values: Variable Argument Address, Chain
10913 SmallVector<SDValue, 11> InstOps;
10914 InstOps.push_back(Chain);
10915 InstOps.push_back(SrcPtr);
10916 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10917 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10918 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10919 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10920 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10921 VTs, &InstOps[0], InstOps.size(),
10923 MachinePointerInfo(SV),
10925 /*Volatile=*/false,
10927 /*WriteMem=*/true);
10928 Chain = VAARG.getValue(1);
10930 // Load the next argument and return it
10931 return DAG.getLoad(ArgVT, dl,
10934 MachinePointerInfo(),
10935 false, false, false, 0);
10938 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10939 SelectionDAG &DAG) {
10940 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10941 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10942 SDValue Chain = Op.getOperand(0);
10943 SDValue DstPtr = Op.getOperand(1);
10944 SDValue SrcPtr = Op.getOperand(2);
10945 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10946 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10949 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10950 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10952 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10955 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10956 // may or may not be a constant. Takes immediate version of shift as input.
10957 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10958 SDValue SrcOp, SDValue ShAmt,
10959 SelectionDAG &DAG) {
10960 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10962 if (isa<ConstantSDNode>(ShAmt)) {
10963 // Constant may be a TargetConstant. Use a regular constant.
10964 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10966 default: llvm_unreachable("Unknown target vector shift node");
10967 case X86ISD::VSHLI:
10968 case X86ISD::VSRLI:
10969 case X86ISD::VSRAI:
10970 return DAG.getNode(Opc, dl, VT, SrcOp,
10971 DAG.getConstant(ShiftAmt, MVT::i32));
10975 // Change opcode to non-immediate version
10977 default: llvm_unreachable("Unknown target vector shift node");
10978 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10979 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10980 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10983 // Need to build a vector containing shift amount
10984 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10987 ShOps[1] = DAG.getConstant(0, MVT::i32);
10988 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10989 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10991 // The return type has to be a 128-bit type with the same element
10992 // type as the input type.
10993 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10994 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10996 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10997 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11000 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11002 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11004 default: return SDValue(); // Don't custom lower most intrinsics.
11005 // Comparison intrinsics.
11006 case Intrinsic::x86_sse_comieq_ss:
11007 case Intrinsic::x86_sse_comilt_ss:
11008 case Intrinsic::x86_sse_comile_ss:
11009 case Intrinsic::x86_sse_comigt_ss:
11010 case Intrinsic::x86_sse_comige_ss:
11011 case Intrinsic::x86_sse_comineq_ss:
11012 case Intrinsic::x86_sse_ucomieq_ss:
11013 case Intrinsic::x86_sse_ucomilt_ss:
11014 case Intrinsic::x86_sse_ucomile_ss:
11015 case Intrinsic::x86_sse_ucomigt_ss:
11016 case Intrinsic::x86_sse_ucomige_ss:
11017 case Intrinsic::x86_sse_ucomineq_ss:
11018 case Intrinsic::x86_sse2_comieq_sd:
11019 case Intrinsic::x86_sse2_comilt_sd:
11020 case Intrinsic::x86_sse2_comile_sd:
11021 case Intrinsic::x86_sse2_comigt_sd:
11022 case Intrinsic::x86_sse2_comige_sd:
11023 case Intrinsic::x86_sse2_comineq_sd:
11024 case Intrinsic::x86_sse2_ucomieq_sd:
11025 case Intrinsic::x86_sse2_ucomilt_sd:
11026 case Intrinsic::x86_sse2_ucomile_sd:
11027 case Intrinsic::x86_sse2_ucomigt_sd:
11028 case Intrinsic::x86_sse2_ucomige_sd:
11029 case Intrinsic::x86_sse2_ucomineq_sd: {
11033 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11034 case Intrinsic::x86_sse_comieq_ss:
11035 case Intrinsic::x86_sse2_comieq_sd:
11036 Opc = X86ISD::COMI;
11039 case Intrinsic::x86_sse_comilt_ss:
11040 case Intrinsic::x86_sse2_comilt_sd:
11041 Opc = X86ISD::COMI;
11044 case Intrinsic::x86_sse_comile_ss:
11045 case Intrinsic::x86_sse2_comile_sd:
11046 Opc = X86ISD::COMI;
11049 case Intrinsic::x86_sse_comigt_ss:
11050 case Intrinsic::x86_sse2_comigt_sd:
11051 Opc = X86ISD::COMI;
11054 case Intrinsic::x86_sse_comige_ss:
11055 case Intrinsic::x86_sse2_comige_sd:
11056 Opc = X86ISD::COMI;
11059 case Intrinsic::x86_sse_comineq_ss:
11060 case Intrinsic::x86_sse2_comineq_sd:
11061 Opc = X86ISD::COMI;
11064 case Intrinsic::x86_sse_ucomieq_ss:
11065 case Intrinsic::x86_sse2_ucomieq_sd:
11066 Opc = X86ISD::UCOMI;
11069 case Intrinsic::x86_sse_ucomilt_ss:
11070 case Intrinsic::x86_sse2_ucomilt_sd:
11071 Opc = X86ISD::UCOMI;
11074 case Intrinsic::x86_sse_ucomile_ss:
11075 case Intrinsic::x86_sse2_ucomile_sd:
11076 Opc = X86ISD::UCOMI;
11079 case Intrinsic::x86_sse_ucomigt_ss:
11080 case Intrinsic::x86_sse2_ucomigt_sd:
11081 Opc = X86ISD::UCOMI;
11084 case Intrinsic::x86_sse_ucomige_ss:
11085 case Intrinsic::x86_sse2_ucomige_sd:
11086 Opc = X86ISD::UCOMI;
11089 case Intrinsic::x86_sse_ucomineq_ss:
11090 case Intrinsic::x86_sse2_ucomineq_sd:
11091 Opc = X86ISD::UCOMI;
11096 SDValue LHS = Op.getOperand(1);
11097 SDValue RHS = Op.getOperand(2);
11098 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11099 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11100 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11101 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11102 DAG.getConstant(X86CC, MVT::i8), Cond);
11103 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11106 // Arithmetic intrinsics.
11107 case Intrinsic::x86_sse2_pmulu_dq:
11108 case Intrinsic::x86_avx2_pmulu_dq:
11109 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11110 Op.getOperand(1), Op.getOperand(2));
11112 // SSE2/AVX2 sub with unsigned saturation intrinsics
11113 case Intrinsic::x86_sse2_psubus_b:
11114 case Intrinsic::x86_sse2_psubus_w:
11115 case Intrinsic::x86_avx2_psubus_b:
11116 case Intrinsic::x86_avx2_psubus_w:
11117 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11118 Op.getOperand(1), Op.getOperand(2));
11120 // SSE3/AVX horizontal add/sub intrinsics
11121 case Intrinsic::x86_sse3_hadd_ps:
11122 case Intrinsic::x86_sse3_hadd_pd:
11123 case Intrinsic::x86_avx_hadd_ps_256:
11124 case Intrinsic::x86_avx_hadd_pd_256:
11125 case Intrinsic::x86_sse3_hsub_ps:
11126 case Intrinsic::x86_sse3_hsub_pd:
11127 case Intrinsic::x86_avx_hsub_ps_256:
11128 case Intrinsic::x86_avx_hsub_pd_256:
11129 case Intrinsic::x86_ssse3_phadd_w_128:
11130 case Intrinsic::x86_ssse3_phadd_d_128:
11131 case Intrinsic::x86_avx2_phadd_w:
11132 case Intrinsic::x86_avx2_phadd_d:
11133 case Intrinsic::x86_ssse3_phsub_w_128:
11134 case Intrinsic::x86_ssse3_phsub_d_128:
11135 case Intrinsic::x86_avx2_phsub_w:
11136 case Intrinsic::x86_avx2_phsub_d: {
11139 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11140 case Intrinsic::x86_sse3_hadd_ps:
11141 case Intrinsic::x86_sse3_hadd_pd:
11142 case Intrinsic::x86_avx_hadd_ps_256:
11143 case Intrinsic::x86_avx_hadd_pd_256:
11144 Opcode = X86ISD::FHADD;
11146 case Intrinsic::x86_sse3_hsub_ps:
11147 case Intrinsic::x86_sse3_hsub_pd:
11148 case Intrinsic::x86_avx_hsub_ps_256:
11149 case Intrinsic::x86_avx_hsub_pd_256:
11150 Opcode = X86ISD::FHSUB;
11152 case Intrinsic::x86_ssse3_phadd_w_128:
11153 case Intrinsic::x86_ssse3_phadd_d_128:
11154 case Intrinsic::x86_avx2_phadd_w:
11155 case Intrinsic::x86_avx2_phadd_d:
11156 Opcode = X86ISD::HADD;
11158 case Intrinsic::x86_ssse3_phsub_w_128:
11159 case Intrinsic::x86_ssse3_phsub_d_128:
11160 case Intrinsic::x86_avx2_phsub_w:
11161 case Intrinsic::x86_avx2_phsub_d:
11162 Opcode = X86ISD::HSUB;
11165 return DAG.getNode(Opcode, dl, Op.getValueType(),
11166 Op.getOperand(1), Op.getOperand(2));
11169 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11170 case Intrinsic::x86_sse2_pmaxu_b:
11171 case Intrinsic::x86_sse41_pmaxuw:
11172 case Intrinsic::x86_sse41_pmaxud:
11173 case Intrinsic::x86_avx2_pmaxu_b:
11174 case Intrinsic::x86_avx2_pmaxu_w:
11175 case Intrinsic::x86_avx2_pmaxu_d:
11176 case Intrinsic::x86_sse2_pminu_b:
11177 case Intrinsic::x86_sse41_pminuw:
11178 case Intrinsic::x86_sse41_pminud:
11179 case Intrinsic::x86_avx2_pminu_b:
11180 case Intrinsic::x86_avx2_pminu_w:
11181 case Intrinsic::x86_avx2_pminu_d:
11182 case Intrinsic::x86_sse41_pmaxsb:
11183 case Intrinsic::x86_sse2_pmaxs_w:
11184 case Intrinsic::x86_sse41_pmaxsd:
11185 case Intrinsic::x86_avx2_pmaxs_b:
11186 case Intrinsic::x86_avx2_pmaxs_w:
11187 case Intrinsic::x86_avx2_pmaxs_d:
11188 case Intrinsic::x86_sse41_pminsb:
11189 case Intrinsic::x86_sse2_pmins_w:
11190 case Intrinsic::x86_sse41_pminsd:
11191 case Intrinsic::x86_avx2_pmins_b:
11192 case Intrinsic::x86_avx2_pmins_w:
11193 case Intrinsic::x86_avx2_pmins_d: {
11196 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11197 case Intrinsic::x86_sse2_pmaxu_b:
11198 case Intrinsic::x86_sse41_pmaxuw:
11199 case Intrinsic::x86_sse41_pmaxud:
11200 case Intrinsic::x86_avx2_pmaxu_b:
11201 case Intrinsic::x86_avx2_pmaxu_w:
11202 case Intrinsic::x86_avx2_pmaxu_d:
11203 Opcode = X86ISD::UMAX;
11205 case Intrinsic::x86_sse2_pminu_b:
11206 case Intrinsic::x86_sse41_pminuw:
11207 case Intrinsic::x86_sse41_pminud:
11208 case Intrinsic::x86_avx2_pminu_b:
11209 case Intrinsic::x86_avx2_pminu_w:
11210 case Intrinsic::x86_avx2_pminu_d:
11211 Opcode = X86ISD::UMIN;
11213 case Intrinsic::x86_sse41_pmaxsb:
11214 case Intrinsic::x86_sse2_pmaxs_w:
11215 case Intrinsic::x86_sse41_pmaxsd:
11216 case Intrinsic::x86_avx2_pmaxs_b:
11217 case Intrinsic::x86_avx2_pmaxs_w:
11218 case Intrinsic::x86_avx2_pmaxs_d:
11219 Opcode = X86ISD::SMAX;
11221 case Intrinsic::x86_sse41_pminsb:
11222 case Intrinsic::x86_sse2_pmins_w:
11223 case Intrinsic::x86_sse41_pminsd:
11224 case Intrinsic::x86_avx2_pmins_b:
11225 case Intrinsic::x86_avx2_pmins_w:
11226 case Intrinsic::x86_avx2_pmins_d:
11227 Opcode = X86ISD::SMIN;
11230 return DAG.getNode(Opcode, dl, Op.getValueType(),
11231 Op.getOperand(1), Op.getOperand(2));
11234 // SSE/SSE2/AVX floating point max/min intrinsics.
11235 case Intrinsic::x86_sse_max_ps:
11236 case Intrinsic::x86_sse2_max_pd:
11237 case Intrinsic::x86_avx_max_ps_256:
11238 case Intrinsic::x86_avx_max_pd_256:
11239 case Intrinsic::x86_avx512_max_ps_512:
11240 case Intrinsic::x86_avx512_max_pd_512:
11241 case Intrinsic::x86_sse_min_ps:
11242 case Intrinsic::x86_sse2_min_pd:
11243 case Intrinsic::x86_avx_min_ps_256:
11244 case Intrinsic::x86_avx_min_pd_256:
11245 case Intrinsic::x86_avx512_min_ps_512:
11246 case Intrinsic::x86_avx512_min_pd_512: {
11249 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11250 case Intrinsic::x86_sse_max_ps:
11251 case Intrinsic::x86_sse2_max_pd:
11252 case Intrinsic::x86_avx_max_ps_256:
11253 case Intrinsic::x86_avx_max_pd_256:
11254 case Intrinsic::x86_avx512_max_ps_512:
11255 case Intrinsic::x86_avx512_max_pd_512:
11256 Opcode = X86ISD::FMAX;
11258 case Intrinsic::x86_sse_min_ps:
11259 case Intrinsic::x86_sse2_min_pd:
11260 case Intrinsic::x86_avx_min_ps_256:
11261 case Intrinsic::x86_avx_min_pd_256:
11262 case Intrinsic::x86_avx512_min_ps_512:
11263 case Intrinsic::x86_avx512_min_pd_512:
11264 Opcode = X86ISD::FMIN;
11267 return DAG.getNode(Opcode, dl, Op.getValueType(),
11268 Op.getOperand(1), Op.getOperand(2));
11271 // AVX2 variable shift intrinsics
11272 case Intrinsic::x86_avx2_psllv_d:
11273 case Intrinsic::x86_avx2_psllv_q:
11274 case Intrinsic::x86_avx2_psllv_d_256:
11275 case Intrinsic::x86_avx2_psllv_q_256:
11276 case Intrinsic::x86_avx2_psrlv_d:
11277 case Intrinsic::x86_avx2_psrlv_q:
11278 case Intrinsic::x86_avx2_psrlv_d_256:
11279 case Intrinsic::x86_avx2_psrlv_q_256:
11280 case Intrinsic::x86_avx2_psrav_d:
11281 case Intrinsic::x86_avx2_psrav_d_256: {
11284 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11285 case Intrinsic::x86_avx2_psllv_d:
11286 case Intrinsic::x86_avx2_psllv_q:
11287 case Intrinsic::x86_avx2_psllv_d_256:
11288 case Intrinsic::x86_avx2_psllv_q_256:
11291 case Intrinsic::x86_avx2_psrlv_d:
11292 case Intrinsic::x86_avx2_psrlv_q:
11293 case Intrinsic::x86_avx2_psrlv_d_256:
11294 case Intrinsic::x86_avx2_psrlv_q_256:
11297 case Intrinsic::x86_avx2_psrav_d:
11298 case Intrinsic::x86_avx2_psrav_d_256:
11302 return DAG.getNode(Opcode, dl, Op.getValueType(),
11303 Op.getOperand(1), Op.getOperand(2));
11306 case Intrinsic::x86_ssse3_pshuf_b_128:
11307 case Intrinsic::x86_avx2_pshuf_b:
11308 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11309 Op.getOperand(1), Op.getOperand(2));
11311 case Intrinsic::x86_ssse3_psign_b_128:
11312 case Intrinsic::x86_ssse3_psign_w_128:
11313 case Intrinsic::x86_ssse3_psign_d_128:
11314 case Intrinsic::x86_avx2_psign_b:
11315 case Intrinsic::x86_avx2_psign_w:
11316 case Intrinsic::x86_avx2_psign_d:
11317 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11318 Op.getOperand(1), Op.getOperand(2));
11320 case Intrinsic::x86_sse41_insertps:
11321 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11322 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11324 case Intrinsic::x86_avx_vperm2f128_ps_256:
11325 case Intrinsic::x86_avx_vperm2f128_pd_256:
11326 case Intrinsic::x86_avx_vperm2f128_si_256:
11327 case Intrinsic::x86_avx2_vperm2i128:
11328 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11329 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11331 case Intrinsic::x86_avx2_permd:
11332 case Intrinsic::x86_avx2_permps:
11333 // Operands intentionally swapped. Mask is last operand to intrinsic,
11334 // but second operand for node/instruction.
11335 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11336 Op.getOperand(2), Op.getOperand(1));
11338 case Intrinsic::x86_sse_sqrt_ps:
11339 case Intrinsic::x86_sse2_sqrt_pd:
11340 case Intrinsic::x86_avx_sqrt_ps_256:
11341 case Intrinsic::x86_avx_sqrt_pd_256:
11342 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11344 // ptest and testp intrinsics. The intrinsic these come from are designed to
11345 // return an integer value, not just an instruction so lower it to the ptest
11346 // or testp pattern and a setcc for the result.
11347 case Intrinsic::x86_sse41_ptestz:
11348 case Intrinsic::x86_sse41_ptestc:
11349 case Intrinsic::x86_sse41_ptestnzc:
11350 case Intrinsic::x86_avx_ptestz_256:
11351 case Intrinsic::x86_avx_ptestc_256:
11352 case Intrinsic::x86_avx_ptestnzc_256:
11353 case Intrinsic::x86_avx_vtestz_ps:
11354 case Intrinsic::x86_avx_vtestc_ps:
11355 case Intrinsic::x86_avx_vtestnzc_ps:
11356 case Intrinsic::x86_avx_vtestz_pd:
11357 case Intrinsic::x86_avx_vtestc_pd:
11358 case Intrinsic::x86_avx_vtestnzc_pd:
11359 case Intrinsic::x86_avx_vtestz_ps_256:
11360 case Intrinsic::x86_avx_vtestc_ps_256:
11361 case Intrinsic::x86_avx_vtestnzc_ps_256:
11362 case Intrinsic::x86_avx_vtestz_pd_256:
11363 case Intrinsic::x86_avx_vtestc_pd_256:
11364 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11365 bool IsTestPacked = false;
11368 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11369 case Intrinsic::x86_avx_vtestz_ps:
11370 case Intrinsic::x86_avx_vtestz_pd:
11371 case Intrinsic::x86_avx_vtestz_ps_256:
11372 case Intrinsic::x86_avx_vtestz_pd_256:
11373 IsTestPacked = true; // Fallthrough
11374 case Intrinsic::x86_sse41_ptestz:
11375 case Intrinsic::x86_avx_ptestz_256:
11377 X86CC = X86::COND_E;
11379 case Intrinsic::x86_avx_vtestc_ps:
11380 case Intrinsic::x86_avx_vtestc_pd:
11381 case Intrinsic::x86_avx_vtestc_ps_256:
11382 case Intrinsic::x86_avx_vtestc_pd_256:
11383 IsTestPacked = true; // Fallthrough
11384 case Intrinsic::x86_sse41_ptestc:
11385 case Intrinsic::x86_avx_ptestc_256:
11387 X86CC = X86::COND_B;
11389 case Intrinsic::x86_avx_vtestnzc_ps:
11390 case Intrinsic::x86_avx_vtestnzc_pd:
11391 case Intrinsic::x86_avx_vtestnzc_ps_256:
11392 case Intrinsic::x86_avx_vtestnzc_pd_256:
11393 IsTestPacked = true; // Fallthrough
11394 case Intrinsic::x86_sse41_ptestnzc:
11395 case Intrinsic::x86_avx_ptestnzc_256:
11397 X86CC = X86::COND_A;
11401 SDValue LHS = Op.getOperand(1);
11402 SDValue RHS = Op.getOperand(2);
11403 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11404 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11405 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11406 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11407 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11409 case Intrinsic::x86_avx512_kortestz:
11410 case Intrinsic::x86_avx512_kortestc: {
11411 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11412 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11413 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11414 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11415 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11416 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11417 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11420 // SSE/AVX shift intrinsics
11421 case Intrinsic::x86_sse2_psll_w:
11422 case Intrinsic::x86_sse2_psll_d:
11423 case Intrinsic::x86_sse2_psll_q:
11424 case Intrinsic::x86_avx2_psll_w:
11425 case Intrinsic::x86_avx2_psll_d:
11426 case Intrinsic::x86_avx2_psll_q:
11427 case Intrinsic::x86_sse2_psrl_w:
11428 case Intrinsic::x86_sse2_psrl_d:
11429 case Intrinsic::x86_sse2_psrl_q:
11430 case Intrinsic::x86_avx2_psrl_w:
11431 case Intrinsic::x86_avx2_psrl_d:
11432 case Intrinsic::x86_avx2_psrl_q:
11433 case Intrinsic::x86_sse2_psra_w:
11434 case Intrinsic::x86_sse2_psra_d:
11435 case Intrinsic::x86_avx2_psra_w:
11436 case Intrinsic::x86_avx2_psra_d: {
11439 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11440 case Intrinsic::x86_sse2_psll_w:
11441 case Intrinsic::x86_sse2_psll_d:
11442 case Intrinsic::x86_sse2_psll_q:
11443 case Intrinsic::x86_avx2_psll_w:
11444 case Intrinsic::x86_avx2_psll_d:
11445 case Intrinsic::x86_avx2_psll_q:
11446 Opcode = X86ISD::VSHL;
11448 case Intrinsic::x86_sse2_psrl_w:
11449 case Intrinsic::x86_sse2_psrl_d:
11450 case Intrinsic::x86_sse2_psrl_q:
11451 case Intrinsic::x86_avx2_psrl_w:
11452 case Intrinsic::x86_avx2_psrl_d:
11453 case Intrinsic::x86_avx2_psrl_q:
11454 Opcode = X86ISD::VSRL;
11456 case Intrinsic::x86_sse2_psra_w:
11457 case Intrinsic::x86_sse2_psra_d:
11458 case Intrinsic::x86_avx2_psra_w:
11459 case Intrinsic::x86_avx2_psra_d:
11460 Opcode = X86ISD::VSRA;
11463 return DAG.getNode(Opcode, dl, Op.getValueType(),
11464 Op.getOperand(1), Op.getOperand(2));
11467 // SSE/AVX immediate shift intrinsics
11468 case Intrinsic::x86_sse2_pslli_w:
11469 case Intrinsic::x86_sse2_pslli_d:
11470 case Intrinsic::x86_sse2_pslli_q:
11471 case Intrinsic::x86_avx2_pslli_w:
11472 case Intrinsic::x86_avx2_pslli_d:
11473 case Intrinsic::x86_avx2_pslli_q:
11474 case Intrinsic::x86_sse2_psrli_w:
11475 case Intrinsic::x86_sse2_psrli_d:
11476 case Intrinsic::x86_sse2_psrli_q:
11477 case Intrinsic::x86_avx2_psrli_w:
11478 case Intrinsic::x86_avx2_psrli_d:
11479 case Intrinsic::x86_avx2_psrli_q:
11480 case Intrinsic::x86_sse2_psrai_w:
11481 case Intrinsic::x86_sse2_psrai_d:
11482 case Intrinsic::x86_avx2_psrai_w:
11483 case Intrinsic::x86_avx2_psrai_d: {
11486 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11487 case Intrinsic::x86_sse2_pslli_w:
11488 case Intrinsic::x86_sse2_pslli_d:
11489 case Intrinsic::x86_sse2_pslli_q:
11490 case Intrinsic::x86_avx2_pslli_w:
11491 case Intrinsic::x86_avx2_pslli_d:
11492 case Intrinsic::x86_avx2_pslli_q:
11493 Opcode = X86ISD::VSHLI;
11495 case Intrinsic::x86_sse2_psrli_w:
11496 case Intrinsic::x86_sse2_psrli_d:
11497 case Intrinsic::x86_sse2_psrli_q:
11498 case Intrinsic::x86_avx2_psrli_w:
11499 case Intrinsic::x86_avx2_psrli_d:
11500 case Intrinsic::x86_avx2_psrli_q:
11501 Opcode = X86ISD::VSRLI;
11503 case Intrinsic::x86_sse2_psrai_w:
11504 case Intrinsic::x86_sse2_psrai_d:
11505 case Intrinsic::x86_avx2_psrai_w:
11506 case Intrinsic::x86_avx2_psrai_d:
11507 Opcode = X86ISD::VSRAI;
11510 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11511 Op.getOperand(1), Op.getOperand(2), DAG);
11514 case Intrinsic::x86_sse42_pcmpistria128:
11515 case Intrinsic::x86_sse42_pcmpestria128:
11516 case Intrinsic::x86_sse42_pcmpistric128:
11517 case Intrinsic::x86_sse42_pcmpestric128:
11518 case Intrinsic::x86_sse42_pcmpistrio128:
11519 case Intrinsic::x86_sse42_pcmpestrio128:
11520 case Intrinsic::x86_sse42_pcmpistris128:
11521 case Intrinsic::x86_sse42_pcmpestris128:
11522 case Intrinsic::x86_sse42_pcmpistriz128:
11523 case Intrinsic::x86_sse42_pcmpestriz128: {
11527 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11528 case Intrinsic::x86_sse42_pcmpistria128:
11529 Opcode = X86ISD::PCMPISTRI;
11530 X86CC = X86::COND_A;
11532 case Intrinsic::x86_sse42_pcmpestria128:
11533 Opcode = X86ISD::PCMPESTRI;
11534 X86CC = X86::COND_A;
11536 case Intrinsic::x86_sse42_pcmpistric128:
11537 Opcode = X86ISD::PCMPISTRI;
11538 X86CC = X86::COND_B;
11540 case Intrinsic::x86_sse42_pcmpestric128:
11541 Opcode = X86ISD::PCMPESTRI;
11542 X86CC = X86::COND_B;
11544 case Intrinsic::x86_sse42_pcmpistrio128:
11545 Opcode = X86ISD::PCMPISTRI;
11546 X86CC = X86::COND_O;
11548 case Intrinsic::x86_sse42_pcmpestrio128:
11549 Opcode = X86ISD::PCMPESTRI;
11550 X86CC = X86::COND_O;
11552 case Intrinsic::x86_sse42_pcmpistris128:
11553 Opcode = X86ISD::PCMPISTRI;
11554 X86CC = X86::COND_S;
11556 case Intrinsic::x86_sse42_pcmpestris128:
11557 Opcode = X86ISD::PCMPESTRI;
11558 X86CC = X86::COND_S;
11560 case Intrinsic::x86_sse42_pcmpistriz128:
11561 Opcode = X86ISD::PCMPISTRI;
11562 X86CC = X86::COND_E;
11564 case Intrinsic::x86_sse42_pcmpestriz128:
11565 Opcode = X86ISD::PCMPESTRI;
11566 X86CC = X86::COND_E;
11569 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11570 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11571 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11572 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11573 DAG.getConstant(X86CC, MVT::i8),
11574 SDValue(PCMP.getNode(), 1));
11575 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11578 case Intrinsic::x86_sse42_pcmpistri128:
11579 case Intrinsic::x86_sse42_pcmpestri128: {
11581 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11582 Opcode = X86ISD::PCMPISTRI;
11584 Opcode = X86ISD::PCMPESTRI;
11586 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11587 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11588 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11590 case Intrinsic::x86_fma_vfmadd_ps:
11591 case Intrinsic::x86_fma_vfmadd_pd:
11592 case Intrinsic::x86_fma_vfmsub_ps:
11593 case Intrinsic::x86_fma_vfmsub_pd:
11594 case Intrinsic::x86_fma_vfnmadd_ps:
11595 case Intrinsic::x86_fma_vfnmadd_pd:
11596 case Intrinsic::x86_fma_vfnmsub_ps:
11597 case Intrinsic::x86_fma_vfnmsub_pd:
11598 case Intrinsic::x86_fma_vfmaddsub_ps:
11599 case Intrinsic::x86_fma_vfmaddsub_pd:
11600 case Intrinsic::x86_fma_vfmsubadd_ps:
11601 case Intrinsic::x86_fma_vfmsubadd_pd:
11602 case Intrinsic::x86_fma_vfmadd_ps_256:
11603 case Intrinsic::x86_fma_vfmadd_pd_256:
11604 case Intrinsic::x86_fma_vfmsub_ps_256:
11605 case Intrinsic::x86_fma_vfmsub_pd_256:
11606 case Intrinsic::x86_fma_vfnmadd_ps_256:
11607 case Intrinsic::x86_fma_vfnmadd_pd_256:
11608 case Intrinsic::x86_fma_vfnmsub_ps_256:
11609 case Intrinsic::x86_fma_vfnmsub_pd_256:
11610 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11611 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11612 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11613 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11616 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11617 case Intrinsic::x86_fma_vfmadd_ps:
11618 case Intrinsic::x86_fma_vfmadd_pd:
11619 case Intrinsic::x86_fma_vfmadd_ps_256:
11620 case Intrinsic::x86_fma_vfmadd_pd_256:
11621 Opc = X86ISD::FMADD;
11623 case Intrinsic::x86_fma_vfmsub_ps:
11624 case Intrinsic::x86_fma_vfmsub_pd:
11625 case Intrinsic::x86_fma_vfmsub_ps_256:
11626 case Intrinsic::x86_fma_vfmsub_pd_256:
11627 Opc = X86ISD::FMSUB;
11629 case Intrinsic::x86_fma_vfnmadd_ps:
11630 case Intrinsic::x86_fma_vfnmadd_pd:
11631 case Intrinsic::x86_fma_vfnmadd_ps_256:
11632 case Intrinsic::x86_fma_vfnmadd_pd_256:
11633 Opc = X86ISD::FNMADD;
11635 case Intrinsic::x86_fma_vfnmsub_ps:
11636 case Intrinsic::x86_fma_vfnmsub_pd:
11637 case Intrinsic::x86_fma_vfnmsub_ps_256:
11638 case Intrinsic::x86_fma_vfnmsub_pd_256:
11639 Opc = X86ISD::FNMSUB;
11641 case Intrinsic::x86_fma_vfmaddsub_ps:
11642 case Intrinsic::x86_fma_vfmaddsub_pd:
11643 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11644 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11645 Opc = X86ISD::FMADDSUB;
11647 case Intrinsic::x86_fma_vfmsubadd_ps:
11648 case Intrinsic::x86_fma_vfmsubadd_pd:
11649 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11650 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11651 Opc = X86ISD::FMSUBADD;
11655 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11656 Op.getOperand(2), Op.getOperand(3));
11661 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11662 SDValue Base, SDValue Index,
11663 SDValue ScaleOp, SDValue Chain,
11664 const X86Subtarget * Subtarget) {
11666 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11667 assert(C && "Invalid scale type");
11668 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11669 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11670 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11671 Index.getValueType().getVectorNumElements());
11672 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11673 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11674 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11675 SDValue Segment = DAG.getRegister(0, MVT::i32);
11676 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11677 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11678 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11679 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11682 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11683 SDValue Src, SDValue Mask, SDValue Base,
11684 SDValue Index, SDValue ScaleOp, SDValue Chain,
11685 const X86Subtarget * Subtarget) {
11687 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11688 assert(C && "Invalid scale type");
11689 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11690 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11691 Index.getValueType().getVectorNumElements());
11692 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11693 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11694 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11695 SDValue Segment = DAG.getRegister(0, MVT::i32);
11696 if (Src.getOpcode() == ISD::UNDEF)
11697 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11698 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11699 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11700 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11701 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11704 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11705 SDValue Src, SDValue Base, SDValue Index,
11706 SDValue ScaleOp, SDValue Chain) {
11708 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11709 assert(C && "Invalid scale type");
11710 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11711 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11712 SDValue Segment = DAG.getRegister(0, MVT::i32);
11713 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11714 Index.getValueType().getVectorNumElements());
11715 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11716 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11717 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11718 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11719 return SDValue(Res, 1);
11722 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11723 SDValue Src, SDValue Mask, SDValue Base,
11724 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11726 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11727 assert(C && "Invalid scale type");
11728 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11729 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11730 SDValue Segment = DAG.getRegister(0, MVT::i32);
11731 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11732 Index.getValueType().getVectorNumElements());
11733 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11734 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11735 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11736 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11737 return SDValue(Res, 1);
11740 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11741 SelectionDAG &DAG) {
11743 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11745 default: return SDValue(); // Don't custom lower most intrinsics.
11747 // RDRAND/RDSEED intrinsics.
11748 case Intrinsic::x86_rdrand_16:
11749 case Intrinsic::x86_rdrand_32:
11750 case Intrinsic::x86_rdrand_64:
11751 case Intrinsic::x86_rdseed_16:
11752 case Intrinsic::x86_rdseed_32:
11753 case Intrinsic::x86_rdseed_64: {
11754 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11755 IntNo == Intrinsic::x86_rdseed_32 ||
11756 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11758 // Emit the node with the right value type.
11759 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11760 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11762 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11763 // Otherwise return the value from Rand, which is always 0, casted to i32.
11764 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11765 DAG.getConstant(1, Op->getValueType(1)),
11766 DAG.getConstant(X86::COND_B, MVT::i32),
11767 SDValue(Result.getNode(), 1) };
11768 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11769 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11770 Ops, array_lengthof(Ops));
11772 // Return { result, isValid, chain }.
11773 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11774 SDValue(Result.getNode(), 2));
11776 //int_gather(index, base, scale);
11777 case Intrinsic::x86_avx512_gather_qpd_512:
11778 case Intrinsic::x86_avx512_gather_qps_512:
11779 case Intrinsic::x86_avx512_gather_dpd_512:
11780 case Intrinsic::x86_avx512_gather_qpi_512:
11781 case Intrinsic::x86_avx512_gather_qpq_512:
11782 case Intrinsic::x86_avx512_gather_dpq_512:
11783 case Intrinsic::x86_avx512_gather_dps_512:
11784 case Intrinsic::x86_avx512_gather_dpi_512: {
11787 default: llvm_unreachable("Unexpected intrinsic!");
11788 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11789 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11790 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11791 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11792 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11793 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11794 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11795 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11797 SDValue Chain = Op.getOperand(0);
11798 SDValue Index = Op.getOperand(2);
11799 SDValue Base = Op.getOperand(3);
11800 SDValue Scale = Op.getOperand(4);
11801 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11803 //int_gather_mask(v1, mask, index, base, scale);
11804 case Intrinsic::x86_avx512_gather_qps_mask_512:
11805 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11806 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11807 case Intrinsic::x86_avx512_gather_dps_mask_512:
11808 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11809 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11810 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11811 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11814 default: llvm_unreachable("Unexpected intrinsic!");
11815 case Intrinsic::x86_avx512_gather_qps_mask_512:
11816 Opc = X86::VGATHERQPSZrm; break;
11817 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11818 Opc = X86::VGATHERQPDZrm; break;
11819 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11820 Opc = X86::VGATHERDPDZrm; break;
11821 case Intrinsic::x86_avx512_gather_dps_mask_512:
11822 Opc = X86::VGATHERDPSZrm; break;
11823 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11824 Opc = X86::VPGATHERQDZrm; break;
11825 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11826 Opc = X86::VPGATHERQQZrm; break;
11827 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11828 Opc = X86::VPGATHERDDZrm; break;
11829 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11830 Opc = X86::VPGATHERDQZrm; break;
11832 SDValue Chain = Op.getOperand(0);
11833 SDValue Src = Op.getOperand(2);
11834 SDValue Mask = Op.getOperand(3);
11835 SDValue Index = Op.getOperand(4);
11836 SDValue Base = Op.getOperand(5);
11837 SDValue Scale = Op.getOperand(6);
11838 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11841 //int_scatter(base, index, v1, scale);
11842 case Intrinsic::x86_avx512_scatter_qpd_512:
11843 case Intrinsic::x86_avx512_scatter_qps_512:
11844 case Intrinsic::x86_avx512_scatter_dpd_512:
11845 case Intrinsic::x86_avx512_scatter_qpi_512:
11846 case Intrinsic::x86_avx512_scatter_qpq_512:
11847 case Intrinsic::x86_avx512_scatter_dpq_512:
11848 case Intrinsic::x86_avx512_scatter_dps_512:
11849 case Intrinsic::x86_avx512_scatter_dpi_512: {
11852 default: llvm_unreachable("Unexpected intrinsic!");
11853 case Intrinsic::x86_avx512_scatter_qpd_512:
11854 Opc = X86::VSCATTERQPDZmr; break;
11855 case Intrinsic::x86_avx512_scatter_qps_512:
11856 Opc = X86::VSCATTERQPSZmr; break;
11857 case Intrinsic::x86_avx512_scatter_dpd_512:
11858 Opc = X86::VSCATTERDPDZmr; break;
11859 case Intrinsic::x86_avx512_scatter_dps_512:
11860 Opc = X86::VSCATTERDPSZmr; break;
11861 case Intrinsic::x86_avx512_scatter_qpi_512:
11862 Opc = X86::VPSCATTERQDZmr; break;
11863 case Intrinsic::x86_avx512_scatter_qpq_512:
11864 Opc = X86::VPSCATTERQQZmr; break;
11865 case Intrinsic::x86_avx512_scatter_dpq_512:
11866 Opc = X86::VPSCATTERDQZmr; break;
11867 case Intrinsic::x86_avx512_scatter_dpi_512:
11868 Opc = X86::VPSCATTERDDZmr; break;
11870 SDValue Chain = Op.getOperand(0);
11871 SDValue Base = Op.getOperand(2);
11872 SDValue Index = Op.getOperand(3);
11873 SDValue Src = Op.getOperand(4);
11874 SDValue Scale = Op.getOperand(5);
11875 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11877 //int_scatter_mask(base, mask, index, v1, scale);
11878 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11879 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11880 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11881 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11882 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11883 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11884 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11885 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11888 default: llvm_unreachable("Unexpected intrinsic!");
11889 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11890 Opc = X86::VSCATTERQPDZmr; break;
11891 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11892 Opc = X86::VSCATTERQPSZmr; break;
11893 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11894 Opc = X86::VSCATTERDPDZmr; break;
11895 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11896 Opc = X86::VSCATTERDPSZmr; break;
11897 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11898 Opc = X86::VPSCATTERQDZmr; break;
11899 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11900 Opc = X86::VPSCATTERQQZmr; break;
11901 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11902 Opc = X86::VPSCATTERDQZmr; break;
11903 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11904 Opc = X86::VPSCATTERDDZmr; break;
11906 SDValue Chain = Op.getOperand(0);
11907 SDValue Base = Op.getOperand(2);
11908 SDValue Mask = Op.getOperand(3);
11909 SDValue Index = Op.getOperand(4);
11910 SDValue Src = Op.getOperand(5);
11911 SDValue Scale = Op.getOperand(6);
11912 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11914 // XTEST intrinsics.
11915 case Intrinsic::x86_xtest: {
11916 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11917 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11918 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11919 DAG.getConstant(X86::COND_NE, MVT::i8),
11921 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11922 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11923 Ret, SDValue(InTrans.getNode(), 1));
11928 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11929 SelectionDAG &DAG) const {
11930 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11931 MFI->setReturnAddressIsTaken(true);
11933 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11935 EVT PtrVT = getPointerTy();
11938 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11939 const X86RegisterInfo *RegInfo =
11940 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11941 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11942 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11943 DAG.getNode(ISD::ADD, dl, PtrVT,
11944 FrameAddr, Offset),
11945 MachinePointerInfo(), false, false, false, 0);
11948 // Just load the return address.
11949 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11950 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11951 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11954 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11955 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11956 MFI->setFrameAddressIsTaken(true);
11958 EVT VT = Op.getValueType();
11959 SDLoc dl(Op); // FIXME probably not meaningful
11960 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11961 const X86RegisterInfo *RegInfo =
11962 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11963 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11964 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11965 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11966 "Invalid Frame Register!");
11967 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11969 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11970 MachinePointerInfo(),
11971 false, false, false, 0);
11975 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11976 SelectionDAG &DAG) const {
11977 const X86RegisterInfo *RegInfo =
11978 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11979 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11982 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11983 SDValue Chain = Op.getOperand(0);
11984 SDValue Offset = Op.getOperand(1);
11985 SDValue Handler = Op.getOperand(2);
11988 EVT PtrVT = getPointerTy();
11989 const X86RegisterInfo *RegInfo =
11990 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11991 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11992 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11993 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11994 "Invalid Frame Register!");
11995 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11996 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11998 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11999 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12000 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12001 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12003 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12005 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12006 DAG.getRegister(StoreAddrReg, PtrVT));
12009 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12010 SelectionDAG &DAG) const {
12012 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12013 DAG.getVTList(MVT::i32, MVT::Other),
12014 Op.getOperand(0), Op.getOperand(1));
12017 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12018 SelectionDAG &DAG) const {
12020 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12021 Op.getOperand(0), Op.getOperand(1));
12024 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12025 return Op.getOperand(0);
12028 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12029 SelectionDAG &DAG) const {
12030 SDValue Root = Op.getOperand(0);
12031 SDValue Trmp = Op.getOperand(1); // trampoline
12032 SDValue FPtr = Op.getOperand(2); // nested function
12033 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12036 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12037 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12039 if (Subtarget->is64Bit()) {
12040 SDValue OutChains[6];
12042 // Large code-model.
12043 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12044 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12046 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12047 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12049 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12051 // Load the pointer to the nested function into R11.
12052 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12053 SDValue Addr = Trmp;
12054 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12055 Addr, MachinePointerInfo(TrmpAddr),
12058 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12059 DAG.getConstant(2, MVT::i64));
12060 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12061 MachinePointerInfo(TrmpAddr, 2),
12064 // Load the 'nest' parameter value into R10.
12065 // R10 is specified in X86CallingConv.td
12066 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12067 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12068 DAG.getConstant(10, MVT::i64));
12069 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12070 Addr, MachinePointerInfo(TrmpAddr, 10),
12073 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12074 DAG.getConstant(12, MVT::i64));
12075 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12076 MachinePointerInfo(TrmpAddr, 12),
12079 // Jump to the nested function.
12080 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12081 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12082 DAG.getConstant(20, MVT::i64));
12083 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12084 Addr, MachinePointerInfo(TrmpAddr, 20),
12087 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12088 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12089 DAG.getConstant(22, MVT::i64));
12090 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12091 MachinePointerInfo(TrmpAddr, 22),
12094 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12096 const Function *Func =
12097 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12098 CallingConv::ID CC = Func->getCallingConv();
12103 llvm_unreachable("Unsupported calling convention");
12104 case CallingConv::C:
12105 case CallingConv::X86_StdCall: {
12106 // Pass 'nest' parameter in ECX.
12107 // Must be kept in sync with X86CallingConv.td
12108 NestReg = X86::ECX;
12110 // Check that ECX wasn't needed by an 'inreg' parameter.
12111 FunctionType *FTy = Func->getFunctionType();
12112 const AttributeSet &Attrs = Func->getAttributes();
12114 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12115 unsigned InRegCount = 0;
12118 for (FunctionType::param_iterator I = FTy->param_begin(),
12119 E = FTy->param_end(); I != E; ++I, ++Idx)
12120 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12121 // FIXME: should only count parameters that are lowered to integers.
12122 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12124 if (InRegCount > 2) {
12125 report_fatal_error("Nest register in use - reduce number of inreg"
12131 case CallingConv::X86_FastCall:
12132 case CallingConv::X86_ThisCall:
12133 case CallingConv::Fast:
12134 // Pass 'nest' parameter in EAX.
12135 // Must be kept in sync with X86CallingConv.td
12136 NestReg = X86::EAX;
12140 SDValue OutChains[4];
12141 SDValue Addr, Disp;
12143 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12144 DAG.getConstant(10, MVT::i32));
12145 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12147 // This is storing the opcode for MOV32ri.
12148 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12149 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12150 OutChains[0] = DAG.getStore(Root, dl,
12151 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12152 Trmp, MachinePointerInfo(TrmpAddr),
12155 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12156 DAG.getConstant(1, MVT::i32));
12157 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12158 MachinePointerInfo(TrmpAddr, 1),
12161 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12162 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12163 DAG.getConstant(5, MVT::i32));
12164 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12165 MachinePointerInfo(TrmpAddr, 5),
12168 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12169 DAG.getConstant(6, MVT::i32));
12170 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12171 MachinePointerInfo(TrmpAddr, 6),
12174 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12178 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12179 SelectionDAG &DAG) const {
12181 The rounding mode is in bits 11:10 of FPSR, and has the following
12183 00 Round to nearest
12188 FLT_ROUNDS, on the other hand, expects the following:
12195 To perform the conversion, we do:
12196 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12199 MachineFunction &MF = DAG.getMachineFunction();
12200 const TargetMachine &TM = MF.getTarget();
12201 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12202 unsigned StackAlignment = TFI.getStackAlignment();
12203 EVT VT = Op.getValueType();
12206 // Save FP Control Word to stack slot
12207 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12208 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12210 MachineMemOperand *MMO =
12211 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12212 MachineMemOperand::MOStore, 2, 2);
12214 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12215 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12216 DAG.getVTList(MVT::Other),
12217 Ops, array_lengthof(Ops), MVT::i16,
12220 // Load FP Control Word from stack slot
12221 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12222 MachinePointerInfo(), false, false, false, 0);
12224 // Transform as necessary
12226 DAG.getNode(ISD::SRL, DL, MVT::i16,
12227 DAG.getNode(ISD::AND, DL, MVT::i16,
12228 CWD, DAG.getConstant(0x800, MVT::i16)),
12229 DAG.getConstant(11, MVT::i8));
12231 DAG.getNode(ISD::SRL, DL, MVT::i16,
12232 DAG.getNode(ISD::AND, DL, MVT::i16,
12233 CWD, DAG.getConstant(0x400, MVT::i16)),
12234 DAG.getConstant(9, MVT::i8));
12237 DAG.getNode(ISD::AND, DL, MVT::i16,
12238 DAG.getNode(ISD::ADD, DL, MVT::i16,
12239 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12240 DAG.getConstant(1, MVT::i16)),
12241 DAG.getConstant(3, MVT::i16));
12243 return DAG.getNode((VT.getSizeInBits() < 16 ?
12244 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12247 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12248 EVT VT = Op.getValueType();
12250 unsigned NumBits = VT.getSizeInBits();
12253 Op = Op.getOperand(0);
12254 if (VT == MVT::i8) {
12255 // Zero extend to i32 since there is not an i8 bsr.
12257 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12260 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12261 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12262 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12264 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12267 DAG.getConstant(NumBits+NumBits-1, OpVT),
12268 DAG.getConstant(X86::COND_E, MVT::i8),
12271 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12273 // Finally xor with NumBits-1.
12274 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12277 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12281 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12282 EVT VT = Op.getValueType();
12284 unsigned NumBits = VT.getSizeInBits();
12287 Op = Op.getOperand(0);
12288 if (VT == MVT::i8) {
12289 // Zero extend to i32 since there is not an i8 bsr.
12291 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12294 // Issue a bsr (scan bits in reverse).
12295 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12296 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12298 // And xor with NumBits-1.
12299 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12302 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12306 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12307 EVT VT = Op.getValueType();
12308 unsigned NumBits = VT.getSizeInBits();
12310 Op = Op.getOperand(0);
12312 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12313 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12314 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12316 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12319 DAG.getConstant(NumBits, VT),
12320 DAG.getConstant(X86::COND_E, MVT::i8),
12323 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12326 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12327 // ones, and then concatenate the result back.
12328 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12329 EVT VT = Op.getValueType();
12331 assert(VT.is256BitVector() && VT.isInteger() &&
12332 "Unsupported value type for operation");
12334 unsigned NumElems = VT.getVectorNumElements();
12337 // Extract the LHS vectors
12338 SDValue LHS = Op.getOperand(0);
12339 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12340 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12342 // Extract the RHS vectors
12343 SDValue RHS = Op.getOperand(1);
12344 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12345 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12347 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12348 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12350 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12351 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12352 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12355 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12356 assert(Op.getValueType().is256BitVector() &&
12357 Op.getValueType().isInteger() &&
12358 "Only handle AVX 256-bit vector integer operation");
12359 return Lower256IntArith(Op, DAG);
12362 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12363 assert(Op.getValueType().is256BitVector() &&
12364 Op.getValueType().isInteger() &&
12365 "Only handle AVX 256-bit vector integer operation");
12366 return Lower256IntArith(Op, DAG);
12369 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12370 SelectionDAG &DAG) {
12372 EVT VT = Op.getValueType();
12374 // Decompose 256-bit ops into smaller 128-bit ops.
12375 if (VT.is256BitVector() && !Subtarget->hasInt256())
12376 return Lower256IntArith(Op, DAG);
12378 SDValue A = Op.getOperand(0);
12379 SDValue B = Op.getOperand(1);
12381 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12382 if (VT == MVT::v4i32) {
12383 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12384 "Should not custom lower when pmuldq is available!");
12386 // Extract the odd parts.
12387 static const int UnpackMask[] = { 1, -1, 3, -1 };
12388 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12389 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12391 // Multiply the even parts.
12392 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12393 // Now multiply odd parts.
12394 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12396 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12397 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12399 // Merge the two vectors back together with a shuffle. This expands into 2
12401 static const int ShufMask[] = { 0, 4, 2, 6 };
12402 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12405 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
12406 "Only know how to lower V2I64/V4I64 multiply");
12408 // Ahi = psrlqi(a, 32);
12409 // Bhi = psrlqi(b, 32);
12411 // AloBlo = pmuludq(a, b);
12412 // AloBhi = pmuludq(a, Bhi);
12413 // AhiBlo = pmuludq(Ahi, b);
12415 // AloBhi = psllqi(AloBhi, 32);
12416 // AhiBlo = psllqi(AhiBlo, 32);
12417 // return AloBlo + AloBhi + AhiBlo;
12419 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
12421 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
12422 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
12424 // Bit cast to 32-bit vectors for MULUDQ
12425 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
12426 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12427 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12428 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12429 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12431 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12432 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12433 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12435 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
12436 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
12438 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12439 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12442 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12443 EVT VT = Op.getValueType();
12444 EVT EltTy = VT.getVectorElementType();
12445 unsigned NumElts = VT.getVectorNumElements();
12446 SDValue N0 = Op.getOperand(0);
12449 // Lower sdiv X, pow2-const.
12450 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12454 APInt SplatValue, SplatUndef;
12455 unsigned SplatBitSize;
12457 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12459 EltTy.getSizeInBits() < SplatBitSize)
12462 if ((SplatValue != 0) &&
12463 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12464 unsigned lg2 = SplatValue.countTrailingZeros();
12465 // Splat the sign bit.
12466 SmallVector<SDValue, 16> Sz(NumElts,
12467 DAG.getConstant(EltTy.getSizeInBits() - 1,
12469 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12470 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12472 // Add (N0 < 0) ? abs2 - 1 : 0;
12473 SmallVector<SDValue, 16> Amt(NumElts,
12474 DAG.getConstant(EltTy.getSizeInBits() - lg2,
12476 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12477 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12479 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12480 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(lg2, EltTy));
12481 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12482 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12485 // If we're dividing by a positive value, we're done. Otherwise, we must
12486 // negate the result.
12487 if (SplatValue.isNonNegative())
12490 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12491 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12492 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12497 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12498 const X86Subtarget *Subtarget) {
12499 EVT VT = Op.getValueType();
12501 SDValue R = Op.getOperand(0);
12502 SDValue Amt = Op.getOperand(1);
12504 // Optimize shl/srl/sra with constant shift amount.
12505 if (isSplatVector(Amt.getNode())) {
12506 SDValue SclrAmt = Amt->getOperand(0);
12507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12508 uint64_t ShiftAmt = C->getZExtValue();
12510 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12511 (Subtarget->hasInt256() &&
12512 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12513 (Subtarget->hasAVX512() &&
12514 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12515 if (Op.getOpcode() == ISD::SHL)
12516 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12517 DAG.getConstant(ShiftAmt, MVT::i32));
12518 if (Op.getOpcode() == ISD::SRL)
12519 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12520 DAG.getConstant(ShiftAmt, MVT::i32));
12521 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12522 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12523 DAG.getConstant(ShiftAmt, MVT::i32));
12526 if (VT == MVT::v16i8) {
12527 if (Op.getOpcode() == ISD::SHL) {
12528 // Make a large shift.
12529 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
12530 DAG.getConstant(ShiftAmt, MVT::i32));
12531 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12532 // Zero out the rightmost bits.
12533 SmallVector<SDValue, 16> V(16,
12534 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12536 return DAG.getNode(ISD::AND, dl, VT, SHL,
12537 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12539 if (Op.getOpcode() == ISD::SRL) {
12540 // Make a large shift.
12541 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
12542 DAG.getConstant(ShiftAmt, MVT::i32));
12543 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12544 // Zero out the leftmost bits.
12545 SmallVector<SDValue, 16> V(16,
12546 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12548 return DAG.getNode(ISD::AND, dl, VT, SRL,
12549 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12551 if (Op.getOpcode() == ISD::SRA) {
12552 if (ShiftAmt == 7) {
12553 // R s>> 7 === R s< 0
12554 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12555 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12558 // R s>> a === ((R u>> a) ^ m) - m
12559 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12560 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12562 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12563 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12564 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12567 llvm_unreachable("Unknown shift opcode.");
12570 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12571 if (Op.getOpcode() == ISD::SHL) {
12572 // Make a large shift.
12573 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
12574 DAG.getConstant(ShiftAmt, MVT::i32));
12575 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12576 // Zero out the rightmost bits.
12577 SmallVector<SDValue, 32> V(32,
12578 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12580 return DAG.getNode(ISD::AND, dl, VT, SHL,
12581 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12583 if (Op.getOpcode() == ISD::SRL) {
12584 // Make a large shift.
12585 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
12586 DAG.getConstant(ShiftAmt, MVT::i32));
12587 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12588 // Zero out the leftmost bits.
12589 SmallVector<SDValue, 32> V(32,
12590 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12592 return DAG.getNode(ISD::AND, dl, VT, SRL,
12593 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12595 if (Op.getOpcode() == ISD::SRA) {
12596 if (ShiftAmt == 7) {
12597 // R s>> 7 === R s< 0
12598 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12599 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12602 // R s>> a === ((R u>> a) ^ m) - m
12603 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12604 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12606 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12607 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12608 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12611 llvm_unreachable("Unknown shift opcode.");
12616 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12617 if (!Subtarget->is64Bit() &&
12618 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12619 Amt.getOpcode() == ISD::BITCAST &&
12620 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12621 Amt = Amt.getOperand(0);
12622 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12623 VT.getVectorNumElements();
12624 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12625 uint64_t ShiftAmt = 0;
12626 for (unsigned i = 0; i != Ratio; ++i) {
12627 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12631 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12633 // Check remaining shift amounts.
12634 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12635 uint64_t ShAmt = 0;
12636 for (unsigned j = 0; j != Ratio; ++j) {
12637 ConstantSDNode *C =
12638 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12642 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12644 if (ShAmt != ShiftAmt)
12647 switch (Op.getOpcode()) {
12649 llvm_unreachable("Unknown shift opcode!");
12651 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12652 DAG.getConstant(ShiftAmt, MVT::i32));
12654 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12655 DAG.getConstant(ShiftAmt, MVT::i32));
12657 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12658 DAG.getConstant(ShiftAmt, MVT::i32));
12665 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12666 const X86Subtarget* Subtarget) {
12667 EVT VT = Op.getValueType();
12669 SDValue R = Op.getOperand(0);
12670 SDValue Amt = Op.getOperand(1);
12672 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12673 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12674 (Subtarget->hasInt256() &&
12675 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12676 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12677 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12679 EVT EltVT = VT.getVectorElementType();
12681 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12682 unsigned NumElts = VT.getVectorNumElements();
12684 for (i = 0; i != NumElts; ++i) {
12685 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12689 for (j = i; j != NumElts; ++j) {
12690 SDValue Arg = Amt.getOperand(j);
12691 if (Arg.getOpcode() == ISD::UNDEF) continue;
12692 if (Arg != Amt.getOperand(i))
12695 if (i != NumElts && j == NumElts)
12696 BaseShAmt = Amt.getOperand(i);
12698 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12699 Amt = Amt.getOperand(0);
12700 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12701 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12702 SDValue InVec = Amt.getOperand(0);
12703 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12704 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12706 for (; i != NumElts; ++i) {
12707 SDValue Arg = InVec.getOperand(i);
12708 if (Arg.getOpcode() == ISD::UNDEF) continue;
12712 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12713 if (ConstantSDNode *C =
12714 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12715 unsigned SplatIdx =
12716 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12717 if (C->getZExtValue() == SplatIdx)
12718 BaseShAmt = InVec.getOperand(1);
12721 if (BaseShAmt.getNode() == 0)
12722 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12723 DAG.getIntPtrConstant(0));
12727 if (BaseShAmt.getNode()) {
12728 if (EltVT.bitsGT(MVT::i32))
12729 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12730 else if (EltVT.bitsLT(MVT::i32))
12731 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12733 switch (Op.getOpcode()) {
12735 llvm_unreachable("Unknown shift opcode!");
12737 switch (VT.getSimpleVT().SimpleTy) {
12738 default: return SDValue();
12747 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12750 switch (VT.getSimpleVT().SimpleTy) {
12751 default: return SDValue();
12758 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12761 switch (VT.getSimpleVT().SimpleTy) {
12762 default: return SDValue();
12771 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12777 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12778 if (!Subtarget->is64Bit() &&
12779 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12780 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12781 Amt.getOpcode() == ISD::BITCAST &&
12782 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12783 Amt = Amt.getOperand(0);
12784 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12785 VT.getVectorNumElements();
12786 std::vector<SDValue> Vals(Ratio);
12787 for (unsigned i = 0; i != Ratio; ++i)
12788 Vals[i] = Amt.getOperand(i);
12789 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12790 for (unsigned j = 0; j != Ratio; ++j)
12791 if (Vals[j] != Amt.getOperand(i + j))
12794 switch (Op.getOpcode()) {
12796 llvm_unreachable("Unknown shift opcode!");
12798 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12800 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12802 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12809 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12810 SelectionDAG &DAG) {
12812 EVT VT = Op.getValueType();
12814 SDValue R = Op.getOperand(0);
12815 SDValue Amt = Op.getOperand(1);
12818 if (!Subtarget->hasSSE2())
12821 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12825 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12829 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12831 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12832 if (Subtarget->hasInt256()) {
12833 if (Op.getOpcode() == ISD::SRL &&
12834 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12835 VT == MVT::v4i64 || VT == MVT::v8i32))
12837 if (Op.getOpcode() == ISD::SHL &&
12838 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12839 VT == MVT::v4i64 || VT == MVT::v8i32))
12841 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12845 // Lower SHL with variable shift amount.
12846 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12847 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12849 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12850 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12851 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12852 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12854 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12855 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12858 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12859 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12861 // Turn 'a' into a mask suitable for VSELECT
12862 SDValue VSelM = DAG.getConstant(0x80, VT);
12863 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12864 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12866 SDValue CM1 = DAG.getConstant(0x0f, VT);
12867 SDValue CM2 = DAG.getConstant(0x3f, VT);
12869 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12870 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12871 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12872 DAG.getConstant(4, MVT::i32), DAG);
12873 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12874 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12877 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12878 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12879 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12881 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12882 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12883 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12884 DAG.getConstant(2, MVT::i32), DAG);
12885 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12886 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12889 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12890 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12891 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12893 // return VSELECT(r, r+r, a);
12894 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12895 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12899 // Decompose 256-bit shifts into smaller 128-bit shifts.
12900 if (VT.is256BitVector()) {
12901 unsigned NumElems = VT.getVectorNumElements();
12902 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12903 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12905 // Extract the two vectors
12906 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12907 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12909 // Recreate the shift amount vectors
12910 SDValue Amt1, Amt2;
12911 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12912 // Constant shift amount
12913 SmallVector<SDValue, 4> Amt1Csts;
12914 SmallVector<SDValue, 4> Amt2Csts;
12915 for (unsigned i = 0; i != NumElems/2; ++i)
12916 Amt1Csts.push_back(Amt->getOperand(i));
12917 for (unsigned i = NumElems/2; i != NumElems; ++i)
12918 Amt2Csts.push_back(Amt->getOperand(i));
12920 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12921 &Amt1Csts[0], NumElems/2);
12922 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12923 &Amt2Csts[0], NumElems/2);
12925 // Variable shift amount
12926 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12927 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12930 // Issue new vector shifts for the smaller types
12931 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12932 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12934 // Concatenate the result back
12935 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12941 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12942 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12943 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12944 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12945 // has only one use.
12946 SDNode *N = Op.getNode();
12947 SDValue LHS = N->getOperand(0);
12948 SDValue RHS = N->getOperand(1);
12949 unsigned BaseOp = 0;
12952 switch (Op.getOpcode()) {
12953 default: llvm_unreachable("Unknown ovf instruction!");
12955 // A subtract of one will be selected as a INC. Note that INC doesn't
12956 // set CF, so we can't do this for UADDO.
12957 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12959 BaseOp = X86ISD::INC;
12960 Cond = X86::COND_O;
12963 BaseOp = X86ISD::ADD;
12964 Cond = X86::COND_O;
12967 BaseOp = X86ISD::ADD;
12968 Cond = X86::COND_B;
12971 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12972 // set CF, so we can't do this for USUBO.
12973 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12975 BaseOp = X86ISD::DEC;
12976 Cond = X86::COND_O;
12979 BaseOp = X86ISD::SUB;
12980 Cond = X86::COND_O;
12983 BaseOp = X86ISD::SUB;
12984 Cond = X86::COND_B;
12987 BaseOp = X86ISD::SMUL;
12988 Cond = X86::COND_O;
12990 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12991 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12993 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12996 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12997 DAG.getConstant(X86::COND_O, MVT::i32),
12998 SDValue(Sum.getNode(), 2));
13000 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13004 // Also sets EFLAGS.
13005 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13006 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13009 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13010 DAG.getConstant(Cond, MVT::i32),
13011 SDValue(Sum.getNode(), 1));
13013 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13016 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13017 SelectionDAG &DAG) const {
13019 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13020 EVT VT = Op.getValueType();
13022 if (!Subtarget->hasSSE2() || !VT.isVector())
13025 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13026 ExtraVT.getScalarType().getSizeInBits();
13027 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
13029 switch (VT.getSimpleVT().SimpleTy) {
13030 default: return SDValue();
13033 if (!Subtarget->hasFp256())
13035 if (!Subtarget->hasInt256()) {
13036 // needs to be split
13037 unsigned NumElems = VT.getVectorNumElements();
13039 // Extract the LHS vectors
13040 SDValue LHS = Op.getOperand(0);
13041 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13042 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13044 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13045 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13047 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13048 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13049 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13051 SDValue Extra = DAG.getValueType(ExtraVT);
13053 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13054 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13056 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13061 // (sext (vzext x)) -> (vsext x)
13062 SDValue Op0 = Op.getOperand(0);
13063 SDValue Op00 = Op0.getOperand(0);
13065 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13066 if (Op0.getOpcode() == ISD::BITCAST &&
13067 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13068 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13069 if (Tmp1.getNode()) {
13070 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13071 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13072 "This optimization is invalid without a VZEXT.");
13073 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13076 // If the above didn't work, then just use Shift-Left + Shift-Right.
13077 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
13078 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
13083 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13084 SelectionDAG &DAG) {
13086 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13087 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13088 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13089 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13091 // The only fence that needs an instruction is a sequentially-consistent
13092 // cross-thread fence.
13093 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13094 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13095 // no-sse2). There isn't any reason to disable it if the target processor
13097 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13098 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13100 SDValue Chain = Op.getOperand(0);
13101 SDValue Zero = DAG.getConstant(0, MVT::i32);
13103 DAG.getRegister(X86::ESP, MVT::i32), // Base
13104 DAG.getTargetConstant(1, MVT::i8), // Scale
13105 DAG.getRegister(0, MVT::i32), // Index
13106 DAG.getTargetConstant(0, MVT::i32), // Disp
13107 DAG.getRegister(0, MVT::i32), // Segment.
13111 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13112 return SDValue(Res, 0);
13115 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13116 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13119 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13120 SelectionDAG &DAG) {
13121 EVT T = Op.getValueType();
13125 switch(T.getSimpleVT().SimpleTy) {
13126 default: llvm_unreachable("Invalid value type!");
13127 case MVT::i8: Reg = X86::AL; size = 1; break;
13128 case MVT::i16: Reg = X86::AX; size = 2; break;
13129 case MVT::i32: Reg = X86::EAX; size = 4; break;
13131 assert(Subtarget->is64Bit() && "Node not type legal!");
13132 Reg = X86::RAX; size = 8;
13135 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13136 Op.getOperand(2), SDValue());
13137 SDValue Ops[] = { cpIn.getValue(0),
13140 DAG.getTargetConstant(size, MVT::i8),
13141 cpIn.getValue(1) };
13142 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13143 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13144 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13145 Ops, array_lengthof(Ops), T, MMO);
13147 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13151 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13152 SelectionDAG &DAG) {
13153 assert(Subtarget->is64Bit() && "Result not type legalized?");
13154 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13155 SDValue TheChain = Op.getOperand(0);
13157 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13158 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13159 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13161 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13162 DAG.getConstant(32, MVT::i8));
13164 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13167 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13170 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13171 SelectionDAG &DAG) {
13172 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13173 MVT DstVT = Op.getSimpleValueType();
13174 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13175 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13176 assert((DstVT == MVT::i64 ||
13177 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13178 "Unexpected custom BITCAST");
13179 // i64 <=> MMX conversions are Legal.
13180 if (SrcVT==MVT::i64 && DstVT.isVector())
13182 if (DstVT==MVT::i64 && SrcVT.isVector())
13184 // MMX <=> MMX conversions are Legal.
13185 if (SrcVT.isVector() && DstVT.isVector())
13187 // All other conversions need to be expanded.
13191 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13192 SDNode *Node = Op.getNode();
13194 EVT T = Node->getValueType(0);
13195 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13196 DAG.getConstant(0, T), Node->getOperand(2));
13197 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13198 cast<AtomicSDNode>(Node)->getMemoryVT(),
13199 Node->getOperand(0),
13200 Node->getOperand(1), negOp,
13201 cast<AtomicSDNode>(Node)->getSrcValue(),
13202 cast<AtomicSDNode>(Node)->getAlignment(),
13203 cast<AtomicSDNode>(Node)->getOrdering(),
13204 cast<AtomicSDNode>(Node)->getSynchScope());
13207 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13208 SDNode *Node = Op.getNode();
13210 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13212 // Convert seq_cst store -> xchg
13213 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13214 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13215 // (The only way to get a 16-byte store is cmpxchg16b)
13216 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13217 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13218 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13219 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13220 cast<AtomicSDNode>(Node)->getMemoryVT(),
13221 Node->getOperand(0),
13222 Node->getOperand(1), Node->getOperand(2),
13223 cast<AtomicSDNode>(Node)->getMemOperand(),
13224 cast<AtomicSDNode>(Node)->getOrdering(),
13225 cast<AtomicSDNode>(Node)->getSynchScope());
13226 return Swap.getValue(1);
13228 // Other atomic stores have a simple pattern.
13232 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13233 EVT VT = Op.getNode()->getValueType(0);
13235 // Let legalize expand this if it isn't a legal type yet.
13236 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13239 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13242 bool ExtraOp = false;
13243 switch (Op.getOpcode()) {
13244 default: llvm_unreachable("Invalid code");
13245 case ISD::ADDC: Opc = X86ISD::ADD; break;
13246 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13247 case ISD::SUBC: Opc = X86ISD::SUB; break;
13248 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13252 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13254 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13255 Op.getOperand(1), Op.getOperand(2));
13258 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13259 SelectionDAG &DAG) {
13260 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13262 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13263 // which returns the values as { float, float } (in XMM0) or
13264 // { double, double } (which is returned in XMM0, XMM1).
13266 SDValue Arg = Op.getOperand(0);
13267 EVT ArgVT = Arg.getValueType();
13268 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13270 TargetLowering::ArgListTy Args;
13271 TargetLowering::ArgListEntry Entry;
13275 Entry.isSExt = false;
13276 Entry.isZExt = false;
13277 Args.push_back(Entry);
13279 bool isF64 = ArgVT == MVT::f64;
13280 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13281 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13282 // the results are returned via SRet in memory.
13283 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13284 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13285 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13287 Type *RetTy = isF64
13288 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13289 : (Type*)VectorType::get(ArgTy, 4);
13291 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13292 false, false, false, false, 0,
13293 CallingConv::C, /*isTaillCall=*/false,
13294 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13295 Callee, Args, DAG, dl);
13296 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13299 // Returned in xmm0 and xmm1.
13300 return CallResult.first;
13302 // Returned in bits 0:31 and 32:64 xmm0.
13303 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13304 CallResult.first, DAG.getIntPtrConstant(0));
13305 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13306 CallResult.first, DAG.getIntPtrConstant(1));
13307 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13308 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13311 /// LowerOperation - Provide custom lowering hooks for some operations.
13313 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13314 switch (Op.getOpcode()) {
13315 default: llvm_unreachable("Should not custom lower this!");
13316 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13317 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13318 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13319 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13320 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13321 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13322 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13323 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13324 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13325 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13326 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13327 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13328 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13329 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13330 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13331 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13332 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13333 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13334 case ISD::SHL_PARTS:
13335 case ISD::SRA_PARTS:
13336 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13337 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13338 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13339 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13340 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13341 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13342 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13343 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13344 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13345 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13346 case ISD::FABS: return LowerFABS(Op, DAG);
13347 case ISD::FNEG: return LowerFNEG(Op, DAG);
13348 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13349 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13350 case ISD::SETCC: return LowerSETCC(Op, DAG);
13351 case ISD::SELECT: return LowerSELECT(Op, DAG);
13352 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13353 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13354 case ISD::VASTART: return LowerVASTART(Op, DAG);
13355 case ISD::VAARG: return LowerVAARG(Op, DAG);
13356 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13357 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13358 case ISD::INTRINSIC_VOID:
13359 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13360 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13361 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13362 case ISD::FRAME_TO_ARGS_OFFSET:
13363 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13364 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13365 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13366 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13367 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13368 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13369 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13370 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13371 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13372 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13373 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13374 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13377 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13383 case ISD::UMULO: return LowerXALUO(Op, DAG);
13384 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13385 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13389 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13390 case ISD::ADD: return LowerADD(Op, DAG);
13391 case ISD::SUB: return LowerSUB(Op, DAG);
13392 case ISD::SDIV: return LowerSDIV(Op, DAG);
13393 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13397 static void ReplaceATOMIC_LOAD(SDNode *Node,
13398 SmallVectorImpl<SDValue> &Results,
13399 SelectionDAG &DAG) {
13401 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13403 // Convert wide load -> cmpxchg8b/cmpxchg16b
13404 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13405 // (The only way to get a 16-byte load is cmpxchg16b)
13406 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13407 SDValue Zero = DAG.getConstant(0, VT);
13408 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13409 Node->getOperand(0),
13410 Node->getOperand(1), Zero, Zero,
13411 cast<AtomicSDNode>(Node)->getMemOperand(),
13412 cast<AtomicSDNode>(Node)->getOrdering(),
13413 cast<AtomicSDNode>(Node)->getSynchScope());
13414 Results.push_back(Swap.getValue(0));
13415 Results.push_back(Swap.getValue(1));
13419 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13420 SelectionDAG &DAG, unsigned NewOp) {
13422 assert (Node->getValueType(0) == MVT::i64 &&
13423 "Only know how to expand i64 atomics");
13425 SDValue Chain = Node->getOperand(0);
13426 SDValue In1 = Node->getOperand(1);
13427 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13428 Node->getOperand(2), DAG.getIntPtrConstant(0));
13429 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13430 Node->getOperand(2), DAG.getIntPtrConstant(1));
13431 SDValue Ops[] = { Chain, In1, In2L, In2H };
13432 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13434 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13435 cast<MemSDNode>(Node)->getMemOperand());
13436 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13437 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13438 Results.push_back(Result.getValue(2));
13441 /// ReplaceNodeResults - Replace a node with an illegal result type
13442 /// with a new node built out of custom code.
13443 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13444 SmallVectorImpl<SDValue>&Results,
13445 SelectionDAG &DAG) const {
13447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13448 switch (N->getOpcode()) {
13450 llvm_unreachable("Do not know how to custom type legalize this operation!");
13451 case ISD::SIGN_EXTEND_INREG:
13456 // We don't want to expand or promote these.
13458 case ISD::FP_TO_SINT:
13459 case ISD::FP_TO_UINT: {
13460 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13462 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13465 std::pair<SDValue,SDValue> Vals =
13466 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13467 SDValue FIST = Vals.first, StackSlot = Vals.second;
13468 if (FIST.getNode() != 0) {
13469 EVT VT = N->getValueType(0);
13470 // Return a load from the stack slot.
13471 if (StackSlot.getNode() != 0)
13472 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13473 MachinePointerInfo(),
13474 false, false, false, 0));
13476 Results.push_back(FIST);
13480 case ISD::UINT_TO_FP: {
13481 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13482 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13483 N->getValueType(0) != MVT::v2f32)
13485 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13487 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13489 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13490 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13491 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13492 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13493 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13494 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13497 case ISD::FP_ROUND: {
13498 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13500 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13501 Results.push_back(V);
13504 case ISD::READCYCLECOUNTER: {
13505 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13506 SDValue TheChain = N->getOperand(0);
13507 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13508 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13510 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13512 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13513 SDValue Ops[] = { eax, edx };
13514 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13515 array_lengthof(Ops)));
13516 Results.push_back(edx.getValue(1));
13519 case ISD::ATOMIC_CMP_SWAP: {
13520 EVT T = N->getValueType(0);
13521 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13522 bool Regs64bit = T == MVT::i128;
13523 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13524 SDValue cpInL, cpInH;
13525 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13526 DAG.getConstant(0, HalfT));
13527 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13528 DAG.getConstant(1, HalfT));
13529 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13530 Regs64bit ? X86::RAX : X86::EAX,
13532 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13533 Regs64bit ? X86::RDX : X86::EDX,
13534 cpInH, cpInL.getValue(1));
13535 SDValue swapInL, swapInH;
13536 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13537 DAG.getConstant(0, HalfT));
13538 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13539 DAG.getConstant(1, HalfT));
13540 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13541 Regs64bit ? X86::RBX : X86::EBX,
13542 swapInL, cpInH.getValue(1));
13543 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13544 Regs64bit ? X86::RCX : X86::ECX,
13545 swapInH, swapInL.getValue(1));
13546 SDValue Ops[] = { swapInH.getValue(0),
13548 swapInH.getValue(1) };
13549 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13550 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13551 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13552 X86ISD::LCMPXCHG8_DAG;
13553 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13554 Ops, array_lengthof(Ops), T, MMO);
13555 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13556 Regs64bit ? X86::RAX : X86::EAX,
13557 HalfT, Result.getValue(1));
13558 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13559 Regs64bit ? X86::RDX : X86::EDX,
13560 HalfT, cpOutL.getValue(2));
13561 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13562 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13563 Results.push_back(cpOutH.getValue(1));
13566 case ISD::ATOMIC_LOAD_ADD:
13567 case ISD::ATOMIC_LOAD_AND:
13568 case ISD::ATOMIC_LOAD_NAND:
13569 case ISD::ATOMIC_LOAD_OR:
13570 case ISD::ATOMIC_LOAD_SUB:
13571 case ISD::ATOMIC_LOAD_XOR:
13572 case ISD::ATOMIC_LOAD_MAX:
13573 case ISD::ATOMIC_LOAD_MIN:
13574 case ISD::ATOMIC_LOAD_UMAX:
13575 case ISD::ATOMIC_LOAD_UMIN:
13576 case ISD::ATOMIC_SWAP: {
13578 switch (N->getOpcode()) {
13579 default: llvm_unreachable("Unexpected opcode");
13580 case ISD::ATOMIC_LOAD_ADD:
13581 Opc = X86ISD::ATOMADD64_DAG;
13583 case ISD::ATOMIC_LOAD_AND:
13584 Opc = X86ISD::ATOMAND64_DAG;
13586 case ISD::ATOMIC_LOAD_NAND:
13587 Opc = X86ISD::ATOMNAND64_DAG;
13589 case ISD::ATOMIC_LOAD_OR:
13590 Opc = X86ISD::ATOMOR64_DAG;
13592 case ISD::ATOMIC_LOAD_SUB:
13593 Opc = X86ISD::ATOMSUB64_DAG;
13595 case ISD::ATOMIC_LOAD_XOR:
13596 Opc = X86ISD::ATOMXOR64_DAG;
13598 case ISD::ATOMIC_LOAD_MAX:
13599 Opc = X86ISD::ATOMMAX64_DAG;
13601 case ISD::ATOMIC_LOAD_MIN:
13602 Opc = X86ISD::ATOMMIN64_DAG;
13604 case ISD::ATOMIC_LOAD_UMAX:
13605 Opc = X86ISD::ATOMUMAX64_DAG;
13607 case ISD::ATOMIC_LOAD_UMIN:
13608 Opc = X86ISD::ATOMUMIN64_DAG;
13610 case ISD::ATOMIC_SWAP:
13611 Opc = X86ISD::ATOMSWAP64_DAG;
13614 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13617 case ISD::ATOMIC_LOAD:
13618 ReplaceATOMIC_LOAD(N, Results, DAG);
13622 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13624 default: return NULL;
13625 case X86ISD::BSF: return "X86ISD::BSF";
13626 case X86ISD::BSR: return "X86ISD::BSR";
13627 case X86ISD::SHLD: return "X86ISD::SHLD";
13628 case X86ISD::SHRD: return "X86ISD::SHRD";
13629 case X86ISD::FAND: return "X86ISD::FAND";
13630 case X86ISD::FANDN: return "X86ISD::FANDN";
13631 case X86ISD::FOR: return "X86ISD::FOR";
13632 case X86ISD::FXOR: return "X86ISD::FXOR";
13633 case X86ISD::FSRL: return "X86ISD::FSRL";
13634 case X86ISD::FILD: return "X86ISD::FILD";
13635 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13636 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13637 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13638 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13639 case X86ISD::FLD: return "X86ISD::FLD";
13640 case X86ISD::FST: return "X86ISD::FST";
13641 case X86ISD::CALL: return "X86ISD::CALL";
13642 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13643 case X86ISD::BT: return "X86ISD::BT";
13644 case X86ISD::CMP: return "X86ISD::CMP";
13645 case X86ISD::COMI: return "X86ISD::COMI";
13646 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13647 case X86ISD::CMPM: return "X86ISD::CMPM";
13648 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13649 case X86ISD::SETCC: return "X86ISD::SETCC";
13650 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13651 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13652 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13653 case X86ISD::CMOV: return "X86ISD::CMOV";
13654 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13655 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13656 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13657 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13658 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13659 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13660 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13661 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13662 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13663 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13664 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13665 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13666 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13667 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13668 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13669 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13670 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13671 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13672 case X86ISD::HADD: return "X86ISD::HADD";
13673 case X86ISD::HSUB: return "X86ISD::HSUB";
13674 case X86ISD::FHADD: return "X86ISD::FHADD";
13675 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13676 case X86ISD::UMAX: return "X86ISD::UMAX";
13677 case X86ISD::UMIN: return "X86ISD::UMIN";
13678 case X86ISD::SMAX: return "X86ISD::SMAX";
13679 case X86ISD::SMIN: return "X86ISD::SMIN";
13680 case X86ISD::FMAX: return "X86ISD::FMAX";
13681 case X86ISD::FMIN: return "X86ISD::FMIN";
13682 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13683 case X86ISD::FMINC: return "X86ISD::FMINC";
13684 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13685 case X86ISD::FRCP: return "X86ISD::FRCP";
13686 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13687 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13688 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13689 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13690 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13691 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13692 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13693 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13694 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13695 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13696 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13697 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13698 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13699 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13700 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13701 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13702 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13703 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13704 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13705 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13706 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13707 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13708 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13709 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13710 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13711 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13712 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13713 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13714 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13715 case X86ISD::VSHL: return "X86ISD::VSHL";
13716 case X86ISD::VSRL: return "X86ISD::VSRL";
13717 case X86ISD::VSRA: return "X86ISD::VSRA";
13718 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13719 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13720 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13721 case X86ISD::CMPP: return "X86ISD::CMPP";
13722 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13723 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13724 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13725 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13726 case X86ISD::ADD: return "X86ISD::ADD";
13727 case X86ISD::SUB: return "X86ISD::SUB";
13728 case X86ISD::ADC: return "X86ISD::ADC";
13729 case X86ISD::SBB: return "X86ISD::SBB";
13730 case X86ISD::SMUL: return "X86ISD::SMUL";
13731 case X86ISD::UMUL: return "X86ISD::UMUL";
13732 case X86ISD::INC: return "X86ISD::INC";
13733 case X86ISD::DEC: return "X86ISD::DEC";
13734 case X86ISD::OR: return "X86ISD::OR";
13735 case X86ISD::XOR: return "X86ISD::XOR";
13736 case X86ISD::AND: return "X86ISD::AND";
13737 case X86ISD::BLSI: return "X86ISD::BLSI";
13738 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13739 case X86ISD::BLSR: return "X86ISD::BLSR";
13740 case X86ISD::BZHI: return "X86ISD::BZHI";
13741 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13742 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13743 case X86ISD::PTEST: return "X86ISD::PTEST";
13744 case X86ISD::TESTP: return "X86ISD::TESTP";
13745 case X86ISD::TESTM: return "X86ISD::TESTM";
13746 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13747 case X86ISD::KTEST: return "X86ISD::KTEST";
13748 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13749 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13750 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13751 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13752 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13753 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13754 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13755 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13756 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13757 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13758 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13759 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13760 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13761 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13762 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13763 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13764 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13765 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13766 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13767 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13768 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13769 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13770 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13771 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13772 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13773 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13774 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13775 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13776 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13777 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13778 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13779 case X86ISD::SAHF: return "X86ISD::SAHF";
13780 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13781 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13782 case X86ISD::FMADD: return "X86ISD::FMADD";
13783 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13784 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13785 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13786 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13787 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13788 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13789 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13790 case X86ISD::XTEST: return "X86ISD::XTEST";
13794 // isLegalAddressingMode - Return true if the addressing mode represented
13795 // by AM is legal for this target, for a load/store of the specified type.
13796 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13798 // X86 supports extremely general addressing modes.
13799 CodeModel::Model M = getTargetMachine().getCodeModel();
13800 Reloc::Model R = getTargetMachine().getRelocationModel();
13802 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13803 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13808 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13810 // If a reference to this global requires an extra load, we can't fold it.
13811 if (isGlobalStubReference(GVFlags))
13814 // If BaseGV requires a register for the PIC base, we cannot also have a
13815 // BaseReg specified.
13816 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13819 // If lower 4G is not available, then we must use rip-relative addressing.
13820 if ((M != CodeModel::Small || R != Reloc::Static) &&
13821 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13825 switch (AM.Scale) {
13831 // These scales always work.
13836 // These scales are formed with basereg+scalereg. Only accept if there is
13841 default: // Other stuff never works.
13848 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13849 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13851 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13852 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13853 return NumBits1 > NumBits2;
13856 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13857 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13860 if (!isTypeLegal(EVT::getEVT(Ty1)))
13863 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13865 // Assuming the caller doesn't have a zeroext or signext return parameter,
13866 // truncation all the way down to i1 is valid.
13870 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13871 return isInt<32>(Imm);
13874 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13875 // Can also use sub to handle negated immediates.
13876 return isInt<32>(Imm);
13879 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13880 if (!VT1.isInteger() || !VT2.isInteger())
13882 unsigned NumBits1 = VT1.getSizeInBits();
13883 unsigned NumBits2 = VT2.getSizeInBits();
13884 return NumBits1 > NumBits2;
13887 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13888 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13889 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13892 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13893 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13894 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13897 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13898 EVT VT1 = Val.getValueType();
13899 if (isZExtFree(VT1, VT2))
13902 if (Val.getOpcode() != ISD::LOAD)
13905 if (!VT1.isSimple() || !VT1.isInteger() ||
13906 !VT2.isSimple() || !VT2.isInteger())
13909 switch (VT1.getSimpleVT().SimpleTy) {
13914 // X86 has 8, 16, and 32-bit zero-extending loads.
13922 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13923 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13926 VT = VT.getScalarType();
13928 if (!VT.isSimple())
13931 switch (VT.getSimpleVT().SimpleTy) {
13942 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13943 // i16 instructions are longer (0x66 prefix) and potentially slower.
13944 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13947 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13948 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13949 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13950 /// are assumed to be legal.
13952 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13954 if (!VT.isSimple())
13957 MVT SVT = VT.getSimpleVT();
13959 // Very little shuffling can be done for 64-bit vectors right now.
13960 if (VT.getSizeInBits() == 64)
13963 // FIXME: pshufb, blends, shifts.
13964 return (SVT.getVectorNumElements() == 2 ||
13965 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13966 isMOVLMask(M, SVT) ||
13967 isSHUFPMask(M, SVT) ||
13968 isPSHUFDMask(M, SVT) ||
13969 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13970 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13971 isPALIGNRMask(M, SVT, Subtarget) ||
13972 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13973 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13974 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13975 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
13979 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13981 if (!VT.isSimple())
13984 MVT SVT = VT.getSimpleVT();
13985 unsigned NumElts = SVT.getVectorNumElements();
13986 // FIXME: This collection of masks seems suspect.
13989 if (NumElts == 4 && SVT.is128BitVector()) {
13990 return (isMOVLMask(Mask, SVT) ||
13991 isCommutedMOVLMask(Mask, SVT, true) ||
13992 isSHUFPMask(Mask, SVT) ||
13993 isSHUFPMask(Mask, SVT, /* Commuted */ true));
13998 //===----------------------------------------------------------------------===//
13999 // X86 Scheduler Hooks
14000 //===----------------------------------------------------------------------===//
14002 /// Utility function to emit xbegin specifying the start of an RTM region.
14003 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14004 const TargetInstrInfo *TII) {
14005 DebugLoc DL = MI->getDebugLoc();
14007 const BasicBlock *BB = MBB->getBasicBlock();
14008 MachineFunction::iterator I = MBB;
14011 // For the v = xbegin(), we generate
14022 MachineBasicBlock *thisMBB = MBB;
14023 MachineFunction *MF = MBB->getParent();
14024 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14025 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14026 MF->insert(I, mainMBB);
14027 MF->insert(I, sinkMBB);
14029 // Transfer the remainder of BB and its successor edges to sinkMBB.
14030 sinkMBB->splice(sinkMBB->begin(), MBB,
14031 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14032 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14036 // # fallthrough to mainMBB
14037 // # abortion to sinkMBB
14038 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14039 thisMBB->addSuccessor(mainMBB);
14040 thisMBB->addSuccessor(sinkMBB);
14044 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14045 mainMBB->addSuccessor(sinkMBB);
14048 // EAX is live into the sinkMBB
14049 sinkMBB->addLiveIn(X86::EAX);
14050 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14051 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14054 MI->eraseFromParent();
14058 // Get CMPXCHG opcode for the specified data type.
14059 static unsigned getCmpXChgOpcode(EVT VT) {
14060 switch (VT.getSimpleVT().SimpleTy) {
14061 case MVT::i8: return X86::LCMPXCHG8;
14062 case MVT::i16: return X86::LCMPXCHG16;
14063 case MVT::i32: return X86::LCMPXCHG32;
14064 case MVT::i64: return X86::LCMPXCHG64;
14068 llvm_unreachable("Invalid operand size!");
14071 // Get LOAD opcode for the specified data type.
14072 static unsigned getLoadOpcode(EVT VT) {
14073 switch (VT.getSimpleVT().SimpleTy) {
14074 case MVT::i8: return X86::MOV8rm;
14075 case MVT::i16: return X86::MOV16rm;
14076 case MVT::i32: return X86::MOV32rm;
14077 case MVT::i64: return X86::MOV64rm;
14081 llvm_unreachable("Invalid operand size!");
14084 // Get opcode of the non-atomic one from the specified atomic instruction.
14085 static unsigned getNonAtomicOpcode(unsigned Opc) {
14087 case X86::ATOMAND8: return X86::AND8rr;
14088 case X86::ATOMAND16: return X86::AND16rr;
14089 case X86::ATOMAND32: return X86::AND32rr;
14090 case X86::ATOMAND64: return X86::AND64rr;
14091 case X86::ATOMOR8: return X86::OR8rr;
14092 case X86::ATOMOR16: return X86::OR16rr;
14093 case X86::ATOMOR32: return X86::OR32rr;
14094 case X86::ATOMOR64: return X86::OR64rr;
14095 case X86::ATOMXOR8: return X86::XOR8rr;
14096 case X86::ATOMXOR16: return X86::XOR16rr;
14097 case X86::ATOMXOR32: return X86::XOR32rr;
14098 case X86::ATOMXOR64: return X86::XOR64rr;
14100 llvm_unreachable("Unhandled atomic-load-op opcode!");
14103 // Get opcode of the non-atomic one from the specified atomic instruction with
14105 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14106 unsigned &ExtraOpc) {
14108 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14109 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14110 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14111 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14112 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14113 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14114 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14115 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14116 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14117 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14118 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14119 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14120 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14121 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14122 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14123 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14124 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14125 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14126 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14127 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14129 llvm_unreachable("Unhandled atomic-load-op opcode!");
14132 // Get opcode of the non-atomic one from the specified atomic instruction for
14133 // 64-bit data type on 32-bit target.
14134 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14136 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14137 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14138 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14139 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14140 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14141 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14142 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14143 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14144 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14145 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14147 llvm_unreachable("Unhandled atomic-load-op opcode!");
14150 // Get opcode of the non-atomic one from the specified atomic instruction for
14151 // 64-bit data type on 32-bit target with extra opcode.
14152 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14154 unsigned &ExtraOpc) {
14156 case X86::ATOMNAND6432:
14157 ExtraOpc = X86::NOT32r;
14158 HiOpc = X86::AND32rr;
14159 return X86::AND32rr;
14161 llvm_unreachable("Unhandled atomic-load-op opcode!");
14164 // Get pseudo CMOV opcode from the specified data type.
14165 static unsigned getPseudoCMOVOpc(EVT VT) {
14166 switch (VT.getSimpleVT().SimpleTy) {
14167 case MVT::i8: return X86::CMOV_GR8;
14168 case MVT::i16: return X86::CMOV_GR16;
14169 case MVT::i32: return X86::CMOV_GR32;
14173 llvm_unreachable("Unknown CMOV opcode!");
14176 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14177 // They will be translated into a spin-loop or compare-exchange loop from
14180 // dst = atomic-fetch-op MI.addr, MI.val
14186 // t1 = LOAD MI.addr
14188 // t4 = phi(t1, t3 / loop)
14189 // t2 = OP MI.val, t4
14191 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14197 MachineBasicBlock *
14198 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14199 MachineBasicBlock *MBB) const {
14200 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14201 DebugLoc DL = MI->getDebugLoc();
14203 MachineFunction *MF = MBB->getParent();
14204 MachineRegisterInfo &MRI = MF->getRegInfo();
14206 const BasicBlock *BB = MBB->getBasicBlock();
14207 MachineFunction::iterator I = MBB;
14210 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14211 "Unexpected number of operands");
14213 assert(MI->hasOneMemOperand() &&
14214 "Expected atomic-load-op to have one memoperand");
14216 // Memory Reference
14217 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14218 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14220 unsigned DstReg, SrcReg;
14221 unsigned MemOpndSlot;
14223 unsigned CurOp = 0;
14225 DstReg = MI->getOperand(CurOp++).getReg();
14226 MemOpndSlot = CurOp;
14227 CurOp += X86::AddrNumOperands;
14228 SrcReg = MI->getOperand(CurOp++).getReg();
14230 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14231 MVT::SimpleValueType VT = *RC->vt_begin();
14232 unsigned t1 = MRI.createVirtualRegister(RC);
14233 unsigned t2 = MRI.createVirtualRegister(RC);
14234 unsigned t3 = MRI.createVirtualRegister(RC);
14235 unsigned t4 = MRI.createVirtualRegister(RC);
14236 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14238 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14239 unsigned LOADOpc = getLoadOpcode(VT);
14241 // For the atomic load-arith operator, we generate
14244 // t1 = LOAD [MI.addr]
14246 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14247 // t1 = OP MI.val, EAX
14249 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14255 MachineBasicBlock *thisMBB = MBB;
14256 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14257 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14258 MF->insert(I, mainMBB);
14259 MF->insert(I, sinkMBB);
14261 MachineInstrBuilder MIB;
14263 // Transfer the remainder of BB and its successor edges to sinkMBB.
14264 sinkMBB->splice(sinkMBB->begin(), MBB,
14265 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14266 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14269 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14270 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14271 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14273 NewMO.setIsKill(false);
14274 MIB.addOperand(NewMO);
14276 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14277 unsigned flags = (*MMOI)->getFlags();
14278 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14279 MachineMemOperand *MMO =
14280 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14281 (*MMOI)->getSize(),
14282 (*MMOI)->getBaseAlignment(),
14283 (*MMOI)->getTBAAInfo(),
14284 (*MMOI)->getRanges());
14285 MIB.addMemOperand(MMO);
14288 thisMBB->addSuccessor(mainMBB);
14291 MachineBasicBlock *origMainMBB = mainMBB;
14294 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14295 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14297 unsigned Opc = MI->getOpcode();
14300 llvm_unreachable("Unhandled atomic-load-op opcode!");
14301 case X86::ATOMAND8:
14302 case X86::ATOMAND16:
14303 case X86::ATOMAND32:
14304 case X86::ATOMAND64:
14306 case X86::ATOMOR16:
14307 case X86::ATOMOR32:
14308 case X86::ATOMOR64:
14309 case X86::ATOMXOR8:
14310 case X86::ATOMXOR16:
14311 case X86::ATOMXOR32:
14312 case X86::ATOMXOR64: {
14313 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14314 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14318 case X86::ATOMNAND8:
14319 case X86::ATOMNAND16:
14320 case X86::ATOMNAND32:
14321 case X86::ATOMNAND64: {
14322 unsigned Tmp = MRI.createVirtualRegister(RC);
14324 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14325 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14327 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14330 case X86::ATOMMAX8:
14331 case X86::ATOMMAX16:
14332 case X86::ATOMMAX32:
14333 case X86::ATOMMAX64:
14334 case X86::ATOMMIN8:
14335 case X86::ATOMMIN16:
14336 case X86::ATOMMIN32:
14337 case X86::ATOMMIN64:
14338 case X86::ATOMUMAX8:
14339 case X86::ATOMUMAX16:
14340 case X86::ATOMUMAX32:
14341 case X86::ATOMUMAX64:
14342 case X86::ATOMUMIN8:
14343 case X86::ATOMUMIN16:
14344 case X86::ATOMUMIN32:
14345 case X86::ATOMUMIN64: {
14347 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14349 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14353 if (Subtarget->hasCMov()) {
14354 if (VT != MVT::i8) {
14356 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14360 // Promote i8 to i32 to use CMOV32
14361 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14362 const TargetRegisterClass *RC32 =
14363 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14364 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14365 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14366 unsigned Tmp = MRI.createVirtualRegister(RC32);
14368 unsigned Undef = MRI.createVirtualRegister(RC32);
14369 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14371 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14374 .addImm(X86::sub_8bit);
14375 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14378 .addImm(X86::sub_8bit);
14380 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14384 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14385 .addReg(Tmp, 0, X86::sub_8bit);
14388 // Use pseudo select and lower them.
14389 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14390 "Invalid atomic-load-op transformation!");
14391 unsigned SelOpc = getPseudoCMOVOpc(VT);
14392 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14393 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14394 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14395 .addReg(SrcReg).addReg(t4)
14397 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14398 // Replace the original PHI node as mainMBB is changed after CMOV
14400 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14401 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14402 Phi->eraseFromParent();
14408 // Copy PhyReg back from virtual register.
14409 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14412 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14413 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14414 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14416 NewMO.setIsKill(false);
14417 MIB.addOperand(NewMO);
14420 MIB.setMemRefs(MMOBegin, MMOEnd);
14422 // Copy PhyReg back to virtual register.
14423 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14426 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14428 mainMBB->addSuccessor(origMainMBB);
14429 mainMBB->addSuccessor(sinkMBB);
14432 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14433 TII->get(TargetOpcode::COPY), DstReg)
14436 MI->eraseFromParent();
14440 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14441 // instructions. They will be translated into a spin-loop or compare-exchange
14445 // dst = atomic-fetch-op MI.addr, MI.val
14451 // t1L = LOAD [MI.addr + 0]
14452 // t1H = LOAD [MI.addr + 4]
14454 // t4L = phi(t1L, t3L / loop)
14455 // t4H = phi(t1H, t3H / loop)
14456 // t2L = OP MI.val.lo, t4L
14457 // t2H = OP MI.val.hi, t4H
14462 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14470 MachineBasicBlock *
14471 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14472 MachineBasicBlock *MBB) const {
14473 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14474 DebugLoc DL = MI->getDebugLoc();
14476 MachineFunction *MF = MBB->getParent();
14477 MachineRegisterInfo &MRI = MF->getRegInfo();
14479 const BasicBlock *BB = MBB->getBasicBlock();
14480 MachineFunction::iterator I = MBB;
14483 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14484 "Unexpected number of operands");
14486 assert(MI->hasOneMemOperand() &&
14487 "Expected atomic-load-op32 to have one memoperand");
14489 // Memory Reference
14490 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14491 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14493 unsigned DstLoReg, DstHiReg;
14494 unsigned SrcLoReg, SrcHiReg;
14495 unsigned MemOpndSlot;
14497 unsigned CurOp = 0;
14499 DstLoReg = MI->getOperand(CurOp++).getReg();
14500 DstHiReg = MI->getOperand(CurOp++).getReg();
14501 MemOpndSlot = CurOp;
14502 CurOp += X86::AddrNumOperands;
14503 SrcLoReg = MI->getOperand(CurOp++).getReg();
14504 SrcHiReg = MI->getOperand(CurOp++).getReg();
14506 const TargetRegisterClass *RC = &X86::GR32RegClass;
14507 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14509 unsigned t1L = MRI.createVirtualRegister(RC);
14510 unsigned t1H = MRI.createVirtualRegister(RC);
14511 unsigned t2L = MRI.createVirtualRegister(RC);
14512 unsigned t2H = MRI.createVirtualRegister(RC);
14513 unsigned t3L = MRI.createVirtualRegister(RC);
14514 unsigned t3H = MRI.createVirtualRegister(RC);
14515 unsigned t4L = MRI.createVirtualRegister(RC);
14516 unsigned t4H = MRI.createVirtualRegister(RC);
14518 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14519 unsigned LOADOpc = X86::MOV32rm;
14521 // For the atomic load-arith operator, we generate
14524 // t1L = LOAD [MI.addr + 0]
14525 // t1H = LOAD [MI.addr + 4]
14527 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14528 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14529 // t2L = OP MI.val.lo, t4L
14530 // t2H = OP MI.val.hi, t4H
14533 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14541 MachineBasicBlock *thisMBB = MBB;
14542 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14543 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14544 MF->insert(I, mainMBB);
14545 MF->insert(I, sinkMBB);
14547 MachineInstrBuilder MIB;
14549 // Transfer the remainder of BB and its successor edges to sinkMBB.
14550 sinkMBB->splice(sinkMBB->begin(), MBB,
14551 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14552 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14556 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14557 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14558 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14560 NewMO.setIsKill(false);
14561 MIB.addOperand(NewMO);
14563 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14564 unsigned flags = (*MMOI)->getFlags();
14565 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14566 MachineMemOperand *MMO =
14567 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14568 (*MMOI)->getSize(),
14569 (*MMOI)->getBaseAlignment(),
14570 (*MMOI)->getTBAAInfo(),
14571 (*MMOI)->getRanges());
14572 MIB.addMemOperand(MMO);
14574 MachineInstr *LowMI = MIB;
14577 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14578 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14579 if (i == X86::AddrDisp) {
14580 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14582 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14584 NewMO.setIsKill(false);
14585 MIB.addOperand(NewMO);
14588 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14590 thisMBB->addSuccessor(mainMBB);
14593 MachineBasicBlock *origMainMBB = mainMBB;
14596 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14597 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14598 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14599 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14601 unsigned Opc = MI->getOpcode();
14604 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14605 case X86::ATOMAND6432:
14606 case X86::ATOMOR6432:
14607 case X86::ATOMXOR6432:
14608 case X86::ATOMADD6432:
14609 case X86::ATOMSUB6432: {
14611 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14612 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14614 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14618 case X86::ATOMNAND6432: {
14619 unsigned HiOpc, NOTOpc;
14620 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14621 unsigned TmpL = MRI.createVirtualRegister(RC);
14622 unsigned TmpH = MRI.createVirtualRegister(RC);
14623 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14625 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14627 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14628 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14631 case X86::ATOMMAX6432:
14632 case X86::ATOMMIN6432:
14633 case X86::ATOMUMAX6432:
14634 case X86::ATOMUMIN6432: {
14636 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14637 unsigned cL = MRI.createVirtualRegister(RC8);
14638 unsigned cH = MRI.createVirtualRegister(RC8);
14639 unsigned cL32 = MRI.createVirtualRegister(RC);
14640 unsigned cH32 = MRI.createVirtualRegister(RC);
14641 unsigned cc = MRI.createVirtualRegister(RC);
14642 // cl := cmp src_lo, lo
14643 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14644 .addReg(SrcLoReg).addReg(t4L);
14645 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14646 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14647 // ch := cmp src_hi, hi
14648 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14649 .addReg(SrcHiReg).addReg(t4H);
14650 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14651 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14652 // cc := if (src_hi == hi) ? cl : ch;
14653 if (Subtarget->hasCMov()) {
14654 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14655 .addReg(cH32).addReg(cL32);
14657 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14658 .addReg(cH32).addReg(cL32)
14659 .addImm(X86::COND_E);
14660 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14662 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14663 if (Subtarget->hasCMov()) {
14664 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14665 .addReg(SrcLoReg).addReg(t4L);
14666 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14667 .addReg(SrcHiReg).addReg(t4H);
14669 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14670 .addReg(SrcLoReg).addReg(t4L)
14671 .addImm(X86::COND_NE);
14672 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14673 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14674 // 2nd CMOV lowering.
14675 mainMBB->addLiveIn(X86::EFLAGS);
14676 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14677 .addReg(SrcHiReg).addReg(t4H)
14678 .addImm(X86::COND_NE);
14679 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14680 // Replace the original PHI node as mainMBB is changed after CMOV
14682 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14683 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14684 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14685 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14686 PhiL->eraseFromParent();
14687 PhiH->eraseFromParent();
14691 case X86::ATOMSWAP6432: {
14693 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14694 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14695 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14700 // Copy EDX:EAX back from HiReg:LoReg
14701 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14702 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14703 // Copy ECX:EBX from t1H:t1L
14704 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14705 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14707 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14708 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14709 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14711 NewMO.setIsKill(false);
14712 MIB.addOperand(NewMO);
14714 MIB.setMemRefs(MMOBegin, MMOEnd);
14716 // Copy EDX:EAX back to t3H:t3L
14717 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14718 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14720 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14722 mainMBB->addSuccessor(origMainMBB);
14723 mainMBB->addSuccessor(sinkMBB);
14726 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14727 TII->get(TargetOpcode::COPY), DstLoReg)
14729 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14730 TII->get(TargetOpcode::COPY), DstHiReg)
14733 MI->eraseFromParent();
14737 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14738 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14739 // in the .td file.
14740 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14741 const TargetInstrInfo *TII) {
14743 switch (MI->getOpcode()) {
14744 default: llvm_unreachable("illegal opcode!");
14745 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14746 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14747 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14748 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14749 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14750 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14751 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14752 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14755 DebugLoc dl = MI->getDebugLoc();
14756 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14758 unsigned NumArgs = MI->getNumOperands();
14759 for (unsigned i = 1; i < NumArgs; ++i) {
14760 MachineOperand &Op = MI->getOperand(i);
14761 if (!(Op.isReg() && Op.isImplicit()))
14762 MIB.addOperand(Op);
14764 if (MI->hasOneMemOperand())
14765 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14767 BuildMI(*BB, MI, dl,
14768 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14769 .addReg(X86::XMM0);
14771 MI->eraseFromParent();
14775 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14776 // defs in an instruction pattern
14777 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14778 const TargetInstrInfo *TII) {
14780 switch (MI->getOpcode()) {
14781 default: llvm_unreachable("illegal opcode!");
14782 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14783 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14784 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14785 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14786 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14787 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14788 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14789 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14792 DebugLoc dl = MI->getDebugLoc();
14793 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14795 unsigned NumArgs = MI->getNumOperands(); // remove the results
14796 for (unsigned i = 1; i < NumArgs; ++i) {
14797 MachineOperand &Op = MI->getOperand(i);
14798 if (!(Op.isReg() && Op.isImplicit()))
14799 MIB.addOperand(Op);
14801 if (MI->hasOneMemOperand())
14802 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14804 BuildMI(*BB, MI, dl,
14805 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14808 MI->eraseFromParent();
14812 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14813 const TargetInstrInfo *TII,
14814 const X86Subtarget* Subtarget) {
14815 DebugLoc dl = MI->getDebugLoc();
14817 // Address into RAX/EAX, other two args into ECX, EDX.
14818 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14819 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14820 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14821 for (int i = 0; i < X86::AddrNumOperands; ++i)
14822 MIB.addOperand(MI->getOperand(i));
14824 unsigned ValOps = X86::AddrNumOperands;
14825 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14826 .addReg(MI->getOperand(ValOps).getReg());
14827 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14828 .addReg(MI->getOperand(ValOps+1).getReg());
14830 // The instruction doesn't actually take any operands though.
14831 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14833 MI->eraseFromParent(); // The pseudo is gone now.
14837 MachineBasicBlock *
14838 X86TargetLowering::EmitVAARG64WithCustomInserter(
14840 MachineBasicBlock *MBB) const {
14841 // Emit va_arg instruction on X86-64.
14843 // Operands to this pseudo-instruction:
14844 // 0 ) Output : destination address (reg)
14845 // 1-5) Input : va_list address (addr, i64mem)
14846 // 6 ) ArgSize : Size (in bytes) of vararg type
14847 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14848 // 8 ) Align : Alignment of type
14849 // 9 ) EFLAGS (implicit-def)
14851 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14852 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14854 unsigned DestReg = MI->getOperand(0).getReg();
14855 MachineOperand &Base = MI->getOperand(1);
14856 MachineOperand &Scale = MI->getOperand(2);
14857 MachineOperand &Index = MI->getOperand(3);
14858 MachineOperand &Disp = MI->getOperand(4);
14859 MachineOperand &Segment = MI->getOperand(5);
14860 unsigned ArgSize = MI->getOperand(6).getImm();
14861 unsigned ArgMode = MI->getOperand(7).getImm();
14862 unsigned Align = MI->getOperand(8).getImm();
14864 // Memory Reference
14865 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14866 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14867 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14869 // Machine Information
14870 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14871 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14872 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14873 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14874 DebugLoc DL = MI->getDebugLoc();
14876 // struct va_list {
14879 // i64 overflow_area (address)
14880 // i64 reg_save_area (address)
14882 // sizeof(va_list) = 24
14883 // alignment(va_list) = 8
14885 unsigned TotalNumIntRegs = 6;
14886 unsigned TotalNumXMMRegs = 8;
14887 bool UseGPOffset = (ArgMode == 1);
14888 bool UseFPOffset = (ArgMode == 2);
14889 unsigned MaxOffset = TotalNumIntRegs * 8 +
14890 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14892 /* Align ArgSize to a multiple of 8 */
14893 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14894 bool NeedsAlign = (Align > 8);
14896 MachineBasicBlock *thisMBB = MBB;
14897 MachineBasicBlock *overflowMBB;
14898 MachineBasicBlock *offsetMBB;
14899 MachineBasicBlock *endMBB;
14901 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14902 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14903 unsigned OffsetReg = 0;
14905 if (!UseGPOffset && !UseFPOffset) {
14906 // If we only pull from the overflow region, we don't create a branch.
14907 // We don't need to alter control flow.
14908 OffsetDestReg = 0; // unused
14909 OverflowDestReg = DestReg;
14912 overflowMBB = thisMBB;
14915 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14916 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14917 // If not, pull from overflow_area. (branch to overflowMBB)
14922 // offsetMBB overflowMBB
14927 // Registers for the PHI in endMBB
14928 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14929 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14931 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14932 MachineFunction *MF = MBB->getParent();
14933 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14934 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14935 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14937 MachineFunction::iterator MBBIter = MBB;
14940 // Insert the new basic blocks
14941 MF->insert(MBBIter, offsetMBB);
14942 MF->insert(MBBIter, overflowMBB);
14943 MF->insert(MBBIter, endMBB);
14945 // Transfer the remainder of MBB and its successor edges to endMBB.
14946 endMBB->splice(endMBB->begin(), thisMBB,
14947 llvm::next(MachineBasicBlock::iterator(MI)),
14949 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14951 // Make offsetMBB and overflowMBB successors of thisMBB
14952 thisMBB->addSuccessor(offsetMBB);
14953 thisMBB->addSuccessor(overflowMBB);
14955 // endMBB is a successor of both offsetMBB and overflowMBB
14956 offsetMBB->addSuccessor(endMBB);
14957 overflowMBB->addSuccessor(endMBB);
14959 // Load the offset value into a register
14960 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14961 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14965 .addDisp(Disp, UseFPOffset ? 4 : 0)
14966 .addOperand(Segment)
14967 .setMemRefs(MMOBegin, MMOEnd);
14969 // Check if there is enough room left to pull this argument.
14970 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14972 .addImm(MaxOffset + 8 - ArgSizeA8);
14974 // Branch to "overflowMBB" if offset >= max
14975 // Fall through to "offsetMBB" otherwise
14976 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14977 .addMBB(overflowMBB);
14980 // In offsetMBB, emit code to use the reg_save_area.
14982 assert(OffsetReg != 0);
14984 // Read the reg_save_area address.
14985 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14986 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14991 .addOperand(Segment)
14992 .setMemRefs(MMOBegin, MMOEnd);
14994 // Zero-extend the offset
14995 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14996 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
14999 .addImm(X86::sub_32bit);
15001 // Add the offset to the reg_save_area to get the final address.
15002 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15003 .addReg(OffsetReg64)
15004 .addReg(RegSaveReg);
15006 // Compute the offset for the next argument
15007 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15008 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15010 .addImm(UseFPOffset ? 16 : 8);
15012 // Store it back into the va_list.
15013 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15017 .addDisp(Disp, UseFPOffset ? 4 : 0)
15018 .addOperand(Segment)
15019 .addReg(NextOffsetReg)
15020 .setMemRefs(MMOBegin, MMOEnd);
15023 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15028 // Emit code to use overflow area
15031 // Load the overflow_area address into a register.
15032 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15033 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15038 .addOperand(Segment)
15039 .setMemRefs(MMOBegin, MMOEnd);
15041 // If we need to align it, do so. Otherwise, just copy the address
15042 // to OverflowDestReg.
15044 // Align the overflow address
15045 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15046 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15048 // aligned_addr = (addr + (align-1)) & ~(align-1)
15049 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15050 .addReg(OverflowAddrReg)
15053 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15055 .addImm(~(uint64_t)(Align-1));
15057 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15058 .addReg(OverflowAddrReg);
15061 // Compute the next overflow address after this argument.
15062 // (the overflow address should be kept 8-byte aligned)
15063 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15064 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15065 .addReg(OverflowDestReg)
15066 .addImm(ArgSizeA8);
15068 // Store the new overflow address.
15069 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15074 .addOperand(Segment)
15075 .addReg(NextAddrReg)
15076 .setMemRefs(MMOBegin, MMOEnd);
15078 // If we branched, emit the PHI to the front of endMBB.
15080 BuildMI(*endMBB, endMBB->begin(), DL,
15081 TII->get(X86::PHI), DestReg)
15082 .addReg(OffsetDestReg).addMBB(offsetMBB)
15083 .addReg(OverflowDestReg).addMBB(overflowMBB);
15086 // Erase the pseudo instruction
15087 MI->eraseFromParent();
15092 MachineBasicBlock *
15093 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15095 MachineBasicBlock *MBB) const {
15096 // Emit code to save XMM registers to the stack. The ABI says that the
15097 // number of registers to save is given in %al, so it's theoretically
15098 // possible to do an indirect jump trick to avoid saving all of them,
15099 // however this code takes a simpler approach and just executes all
15100 // of the stores if %al is non-zero. It's less code, and it's probably
15101 // easier on the hardware branch predictor, and stores aren't all that
15102 // expensive anyway.
15104 // Create the new basic blocks. One block contains all the XMM stores,
15105 // and one block is the final destination regardless of whether any
15106 // stores were performed.
15107 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15108 MachineFunction *F = MBB->getParent();
15109 MachineFunction::iterator MBBIter = MBB;
15111 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15112 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15113 F->insert(MBBIter, XMMSaveMBB);
15114 F->insert(MBBIter, EndMBB);
15116 // Transfer the remainder of MBB and its successor edges to EndMBB.
15117 EndMBB->splice(EndMBB->begin(), MBB,
15118 llvm::next(MachineBasicBlock::iterator(MI)),
15120 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15122 // The original block will now fall through to the XMM save block.
15123 MBB->addSuccessor(XMMSaveMBB);
15124 // The XMMSaveMBB will fall through to the end block.
15125 XMMSaveMBB->addSuccessor(EndMBB);
15127 // Now add the instructions.
15128 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15129 DebugLoc DL = MI->getDebugLoc();
15131 unsigned CountReg = MI->getOperand(0).getReg();
15132 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15133 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15135 if (!Subtarget->isTargetWin64()) {
15136 // If %al is 0, branch around the XMM save block.
15137 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15138 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15139 MBB->addSuccessor(EndMBB);
15142 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15143 // In the XMM save block, save all the XMM argument registers.
15144 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15145 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15146 MachineMemOperand *MMO =
15147 F->getMachineMemOperand(
15148 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15149 MachineMemOperand::MOStore,
15150 /*Size=*/16, /*Align=*/16);
15151 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15152 .addFrameIndex(RegSaveFrameIndex)
15153 .addImm(/*Scale=*/1)
15154 .addReg(/*IndexReg=*/0)
15155 .addImm(/*Disp=*/Offset)
15156 .addReg(/*Segment=*/0)
15157 .addReg(MI->getOperand(i).getReg())
15158 .addMemOperand(MMO);
15161 MI->eraseFromParent(); // The pseudo instruction is gone now.
15166 // The EFLAGS operand of SelectItr might be missing a kill marker
15167 // because there were multiple uses of EFLAGS, and ISel didn't know
15168 // which to mark. Figure out whether SelectItr should have had a
15169 // kill marker, and set it if it should. Returns the correct kill
15171 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15172 MachineBasicBlock* BB,
15173 const TargetRegisterInfo* TRI) {
15174 // Scan forward through BB for a use/def of EFLAGS.
15175 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15176 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15177 const MachineInstr& mi = *miI;
15178 if (mi.readsRegister(X86::EFLAGS))
15180 if (mi.definesRegister(X86::EFLAGS))
15181 break; // Should have kill-flag - update below.
15184 // If we hit the end of the block, check whether EFLAGS is live into a
15186 if (miI == BB->end()) {
15187 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15188 sEnd = BB->succ_end();
15189 sItr != sEnd; ++sItr) {
15190 MachineBasicBlock* succ = *sItr;
15191 if (succ->isLiveIn(X86::EFLAGS))
15196 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15197 // out. SelectMI should have a kill flag on EFLAGS.
15198 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15202 MachineBasicBlock *
15203 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15204 MachineBasicBlock *BB) const {
15205 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15206 DebugLoc DL = MI->getDebugLoc();
15208 // To "insert" a SELECT_CC instruction, we actually have to insert the
15209 // diamond control-flow pattern. The incoming instruction knows the
15210 // destination vreg to set, the condition code register to branch on, the
15211 // true/false values to select between, and a branch opcode to use.
15212 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15213 MachineFunction::iterator It = BB;
15219 // cmpTY ccX, r1, r2
15221 // fallthrough --> copy0MBB
15222 MachineBasicBlock *thisMBB = BB;
15223 MachineFunction *F = BB->getParent();
15224 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15225 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15226 F->insert(It, copy0MBB);
15227 F->insert(It, sinkMBB);
15229 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15230 // live into the sink and copy blocks.
15231 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15232 if (!MI->killsRegister(X86::EFLAGS) &&
15233 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15234 copy0MBB->addLiveIn(X86::EFLAGS);
15235 sinkMBB->addLiveIn(X86::EFLAGS);
15238 // Transfer the remainder of BB and its successor edges to sinkMBB.
15239 sinkMBB->splice(sinkMBB->begin(), BB,
15240 llvm::next(MachineBasicBlock::iterator(MI)),
15242 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15244 // Add the true and fallthrough blocks as its successors.
15245 BB->addSuccessor(copy0MBB);
15246 BB->addSuccessor(sinkMBB);
15248 // Create the conditional branch instruction.
15250 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15251 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15254 // %FalseValue = ...
15255 // # fallthrough to sinkMBB
15256 copy0MBB->addSuccessor(sinkMBB);
15259 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15261 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15262 TII->get(X86::PHI), MI->getOperand(0).getReg())
15263 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15264 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15266 MI->eraseFromParent(); // The pseudo instruction is gone now.
15270 MachineBasicBlock *
15271 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15272 bool Is64Bit) const {
15273 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15274 DebugLoc DL = MI->getDebugLoc();
15275 MachineFunction *MF = BB->getParent();
15276 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15278 assert(getTargetMachine().Options.EnableSegmentedStacks);
15280 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15281 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15284 // ... [Till the alloca]
15285 // If stacklet is not large enough, jump to mallocMBB
15288 // Allocate by subtracting from RSP
15289 // Jump to continueMBB
15292 // Allocate by call to runtime
15296 // [rest of original BB]
15299 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15300 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15301 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15303 MachineRegisterInfo &MRI = MF->getRegInfo();
15304 const TargetRegisterClass *AddrRegClass =
15305 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15307 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15308 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15309 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15310 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15311 sizeVReg = MI->getOperand(1).getReg(),
15312 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15314 MachineFunction::iterator MBBIter = BB;
15317 MF->insert(MBBIter, bumpMBB);
15318 MF->insert(MBBIter, mallocMBB);
15319 MF->insert(MBBIter, continueMBB);
15321 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15322 (MachineBasicBlock::iterator(MI)), BB->end());
15323 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15325 // Add code to the main basic block to check if the stack limit has been hit,
15326 // and if so, jump to mallocMBB otherwise to bumpMBB.
15327 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15328 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15329 .addReg(tmpSPVReg).addReg(sizeVReg);
15330 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15331 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15332 .addReg(SPLimitVReg);
15333 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15335 // bumpMBB simply decreases the stack pointer, since we know the current
15336 // stacklet has enough space.
15337 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15338 .addReg(SPLimitVReg);
15339 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15340 .addReg(SPLimitVReg);
15341 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15343 // Calls into a routine in libgcc to allocate more space from the heap.
15344 const uint32_t *RegMask =
15345 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15347 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15349 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15350 .addExternalSymbol("__morestack_allocate_stack_space")
15351 .addRegMask(RegMask)
15352 .addReg(X86::RDI, RegState::Implicit)
15353 .addReg(X86::RAX, RegState::ImplicitDefine);
15355 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15357 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15358 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15359 .addExternalSymbol("__morestack_allocate_stack_space")
15360 .addRegMask(RegMask)
15361 .addReg(X86::EAX, RegState::ImplicitDefine);
15365 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15368 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15369 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15370 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15372 // Set up the CFG correctly.
15373 BB->addSuccessor(bumpMBB);
15374 BB->addSuccessor(mallocMBB);
15375 mallocMBB->addSuccessor(continueMBB);
15376 bumpMBB->addSuccessor(continueMBB);
15378 // Take care of the PHI nodes.
15379 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15380 MI->getOperand(0).getReg())
15381 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15382 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15384 // Delete the original pseudo instruction.
15385 MI->eraseFromParent();
15388 return continueMBB;
15391 MachineBasicBlock *
15392 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15393 MachineBasicBlock *BB) const {
15394 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15395 DebugLoc DL = MI->getDebugLoc();
15397 assert(!Subtarget->isTargetEnvMacho());
15399 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15400 // non-trivial part is impdef of ESP.
15402 if (Subtarget->isTargetWin64()) {
15403 if (Subtarget->isTargetCygMing()) {
15404 // ___chkstk(Mingw64):
15405 // Clobbers R10, R11, RAX and EFLAGS.
15407 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15408 .addExternalSymbol("___chkstk")
15409 .addReg(X86::RAX, RegState::Implicit)
15410 .addReg(X86::RSP, RegState::Implicit)
15411 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15412 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15413 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15415 // __chkstk(MSVCRT): does not update stack pointer.
15416 // Clobbers R10, R11 and EFLAGS.
15417 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15418 .addExternalSymbol("__chkstk")
15419 .addReg(X86::RAX, RegState::Implicit)
15420 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15421 // RAX has the offset to be subtracted from RSP.
15422 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15427 const char *StackProbeSymbol =
15428 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15430 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15431 .addExternalSymbol(StackProbeSymbol)
15432 .addReg(X86::EAX, RegState::Implicit)
15433 .addReg(X86::ESP, RegState::Implicit)
15434 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15435 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15436 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15439 MI->eraseFromParent(); // The pseudo instruction is gone now.
15443 MachineBasicBlock *
15444 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15445 MachineBasicBlock *BB) const {
15446 // This is pretty easy. We're taking the value that we received from
15447 // our load from the relocation, sticking it in either RDI (x86-64)
15448 // or EAX and doing an indirect call. The return value will then
15449 // be in the normal return register.
15450 const X86InstrInfo *TII
15451 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15452 DebugLoc DL = MI->getDebugLoc();
15453 MachineFunction *F = BB->getParent();
15455 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15456 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15458 // Get a register mask for the lowered call.
15459 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15460 // proper register mask.
15461 const uint32_t *RegMask =
15462 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15463 if (Subtarget->is64Bit()) {
15464 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15465 TII->get(X86::MOV64rm), X86::RDI)
15467 .addImm(0).addReg(0)
15468 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15469 MI->getOperand(3).getTargetFlags())
15471 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15472 addDirectMem(MIB, X86::RDI);
15473 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15474 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15475 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15476 TII->get(X86::MOV32rm), X86::EAX)
15478 .addImm(0).addReg(0)
15479 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15480 MI->getOperand(3).getTargetFlags())
15482 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15483 addDirectMem(MIB, X86::EAX);
15484 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15486 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15487 TII->get(X86::MOV32rm), X86::EAX)
15488 .addReg(TII->getGlobalBaseReg(F))
15489 .addImm(0).addReg(0)
15490 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15491 MI->getOperand(3).getTargetFlags())
15493 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15494 addDirectMem(MIB, X86::EAX);
15495 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15498 MI->eraseFromParent(); // The pseudo instruction is gone now.
15502 MachineBasicBlock *
15503 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15504 MachineBasicBlock *MBB) const {
15505 DebugLoc DL = MI->getDebugLoc();
15506 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15508 MachineFunction *MF = MBB->getParent();
15509 MachineRegisterInfo &MRI = MF->getRegInfo();
15511 const BasicBlock *BB = MBB->getBasicBlock();
15512 MachineFunction::iterator I = MBB;
15515 // Memory Reference
15516 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15517 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15520 unsigned MemOpndSlot = 0;
15522 unsigned CurOp = 0;
15524 DstReg = MI->getOperand(CurOp++).getReg();
15525 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15526 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15527 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15528 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15530 MemOpndSlot = CurOp;
15532 MVT PVT = getPointerTy();
15533 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15534 "Invalid Pointer Size!");
15536 // For v = setjmp(buf), we generate
15539 // buf[LabelOffset] = restoreMBB
15540 // SjLjSetup restoreMBB
15546 // v = phi(main, restore)
15551 MachineBasicBlock *thisMBB = MBB;
15552 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15553 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15554 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15555 MF->insert(I, mainMBB);
15556 MF->insert(I, sinkMBB);
15557 MF->push_back(restoreMBB);
15559 MachineInstrBuilder MIB;
15561 // Transfer the remainder of BB and its successor edges to sinkMBB.
15562 sinkMBB->splice(sinkMBB->begin(), MBB,
15563 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15564 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15567 unsigned PtrStoreOpc = 0;
15568 unsigned LabelReg = 0;
15569 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15570 Reloc::Model RM = getTargetMachine().getRelocationModel();
15571 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15572 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15574 // Prepare IP either in reg or imm.
15575 if (!UseImmLabel) {
15576 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15577 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15578 LabelReg = MRI.createVirtualRegister(PtrRC);
15579 if (Subtarget->is64Bit()) {
15580 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15584 .addMBB(restoreMBB)
15587 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15588 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15589 .addReg(XII->getGlobalBaseReg(MF))
15592 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15596 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15598 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15599 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15600 if (i == X86::AddrDisp)
15601 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15603 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15606 MIB.addReg(LabelReg);
15608 MIB.addMBB(restoreMBB);
15609 MIB.setMemRefs(MMOBegin, MMOEnd);
15611 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15612 .addMBB(restoreMBB);
15614 const X86RegisterInfo *RegInfo =
15615 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15616 MIB.addRegMask(RegInfo->getNoPreservedMask());
15617 thisMBB->addSuccessor(mainMBB);
15618 thisMBB->addSuccessor(restoreMBB);
15622 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15623 mainMBB->addSuccessor(sinkMBB);
15626 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15627 TII->get(X86::PHI), DstReg)
15628 .addReg(mainDstReg).addMBB(mainMBB)
15629 .addReg(restoreDstReg).addMBB(restoreMBB);
15632 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15633 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15634 restoreMBB->addSuccessor(sinkMBB);
15636 MI->eraseFromParent();
15640 MachineBasicBlock *
15641 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15642 MachineBasicBlock *MBB) const {
15643 DebugLoc DL = MI->getDebugLoc();
15644 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15646 MachineFunction *MF = MBB->getParent();
15647 MachineRegisterInfo &MRI = MF->getRegInfo();
15649 // Memory Reference
15650 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15651 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15653 MVT PVT = getPointerTy();
15654 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15655 "Invalid Pointer Size!");
15657 const TargetRegisterClass *RC =
15658 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15659 unsigned Tmp = MRI.createVirtualRegister(RC);
15660 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15661 const X86RegisterInfo *RegInfo =
15662 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15663 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15664 unsigned SP = RegInfo->getStackRegister();
15666 MachineInstrBuilder MIB;
15668 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15669 const int64_t SPOffset = 2 * PVT.getStoreSize();
15671 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15672 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15675 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15676 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15677 MIB.addOperand(MI->getOperand(i));
15678 MIB.setMemRefs(MMOBegin, MMOEnd);
15680 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15681 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15682 if (i == X86::AddrDisp)
15683 MIB.addDisp(MI->getOperand(i), LabelOffset);
15685 MIB.addOperand(MI->getOperand(i));
15687 MIB.setMemRefs(MMOBegin, MMOEnd);
15689 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15690 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15691 if (i == X86::AddrDisp)
15692 MIB.addDisp(MI->getOperand(i), SPOffset);
15694 MIB.addOperand(MI->getOperand(i));
15696 MIB.setMemRefs(MMOBegin, MMOEnd);
15698 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15700 MI->eraseFromParent();
15704 MachineBasicBlock *
15705 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15706 MachineBasicBlock *BB) const {
15707 switch (MI->getOpcode()) {
15708 default: llvm_unreachable("Unexpected instr type to insert");
15709 case X86::TAILJMPd64:
15710 case X86::TAILJMPr64:
15711 case X86::TAILJMPm64:
15712 llvm_unreachable("TAILJMP64 would not be touched here.");
15713 case X86::TCRETURNdi64:
15714 case X86::TCRETURNri64:
15715 case X86::TCRETURNmi64:
15717 case X86::WIN_ALLOCA:
15718 return EmitLoweredWinAlloca(MI, BB);
15719 case X86::SEG_ALLOCA_32:
15720 return EmitLoweredSegAlloca(MI, BB, false);
15721 case X86::SEG_ALLOCA_64:
15722 return EmitLoweredSegAlloca(MI, BB, true);
15723 case X86::TLSCall_32:
15724 case X86::TLSCall_64:
15725 return EmitLoweredTLSCall(MI, BB);
15726 case X86::CMOV_GR8:
15727 case X86::CMOV_FR32:
15728 case X86::CMOV_FR64:
15729 case X86::CMOV_V4F32:
15730 case X86::CMOV_V2F64:
15731 case X86::CMOV_V2I64:
15732 case X86::CMOV_V8F32:
15733 case X86::CMOV_V4F64:
15734 case X86::CMOV_V4I64:
15735 case X86::CMOV_GR16:
15736 case X86::CMOV_GR32:
15737 case X86::CMOV_RFP32:
15738 case X86::CMOV_RFP64:
15739 case X86::CMOV_RFP80:
15740 return EmitLoweredSelect(MI, BB);
15742 case X86::FP32_TO_INT16_IN_MEM:
15743 case X86::FP32_TO_INT32_IN_MEM:
15744 case X86::FP32_TO_INT64_IN_MEM:
15745 case X86::FP64_TO_INT16_IN_MEM:
15746 case X86::FP64_TO_INT32_IN_MEM:
15747 case X86::FP64_TO_INT64_IN_MEM:
15748 case X86::FP80_TO_INT16_IN_MEM:
15749 case X86::FP80_TO_INT32_IN_MEM:
15750 case X86::FP80_TO_INT64_IN_MEM: {
15751 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15752 DebugLoc DL = MI->getDebugLoc();
15754 // Change the floating point control register to use "round towards zero"
15755 // mode when truncating to an integer value.
15756 MachineFunction *F = BB->getParent();
15757 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15758 addFrameReference(BuildMI(*BB, MI, DL,
15759 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15761 // Load the old value of the high byte of the control word...
15763 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15764 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15767 // Set the high part to be round to zero...
15768 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15771 // Reload the modified control word now...
15772 addFrameReference(BuildMI(*BB, MI, DL,
15773 TII->get(X86::FLDCW16m)), CWFrameIdx);
15775 // Restore the memory image of control word to original value
15776 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15779 // Get the X86 opcode to use.
15781 switch (MI->getOpcode()) {
15782 default: llvm_unreachable("illegal opcode!");
15783 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15784 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15785 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15786 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15787 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15788 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15789 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15790 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15791 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15795 MachineOperand &Op = MI->getOperand(0);
15797 AM.BaseType = X86AddressMode::RegBase;
15798 AM.Base.Reg = Op.getReg();
15800 AM.BaseType = X86AddressMode::FrameIndexBase;
15801 AM.Base.FrameIndex = Op.getIndex();
15803 Op = MI->getOperand(1);
15805 AM.Scale = Op.getImm();
15806 Op = MI->getOperand(2);
15808 AM.IndexReg = Op.getImm();
15809 Op = MI->getOperand(3);
15810 if (Op.isGlobal()) {
15811 AM.GV = Op.getGlobal();
15813 AM.Disp = Op.getImm();
15815 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15816 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15818 // Reload the original control word now.
15819 addFrameReference(BuildMI(*BB, MI, DL,
15820 TII->get(X86::FLDCW16m)), CWFrameIdx);
15822 MI->eraseFromParent(); // The pseudo instruction is gone now.
15825 // String/text processing lowering.
15826 case X86::PCMPISTRM128REG:
15827 case X86::VPCMPISTRM128REG:
15828 case X86::PCMPISTRM128MEM:
15829 case X86::VPCMPISTRM128MEM:
15830 case X86::PCMPESTRM128REG:
15831 case X86::VPCMPESTRM128REG:
15832 case X86::PCMPESTRM128MEM:
15833 case X86::VPCMPESTRM128MEM:
15834 assert(Subtarget->hasSSE42() &&
15835 "Target must have SSE4.2 or AVX features enabled");
15836 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15838 // String/text processing lowering.
15839 case X86::PCMPISTRIREG:
15840 case X86::VPCMPISTRIREG:
15841 case X86::PCMPISTRIMEM:
15842 case X86::VPCMPISTRIMEM:
15843 case X86::PCMPESTRIREG:
15844 case X86::VPCMPESTRIREG:
15845 case X86::PCMPESTRIMEM:
15846 case X86::VPCMPESTRIMEM:
15847 assert(Subtarget->hasSSE42() &&
15848 "Target must have SSE4.2 or AVX features enabled");
15849 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15851 // Thread synchronization.
15853 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15857 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15859 // Atomic Lowering.
15860 case X86::ATOMAND8:
15861 case X86::ATOMAND16:
15862 case X86::ATOMAND32:
15863 case X86::ATOMAND64:
15866 case X86::ATOMOR16:
15867 case X86::ATOMOR32:
15868 case X86::ATOMOR64:
15870 case X86::ATOMXOR16:
15871 case X86::ATOMXOR8:
15872 case X86::ATOMXOR32:
15873 case X86::ATOMXOR64:
15875 case X86::ATOMNAND8:
15876 case X86::ATOMNAND16:
15877 case X86::ATOMNAND32:
15878 case X86::ATOMNAND64:
15880 case X86::ATOMMAX8:
15881 case X86::ATOMMAX16:
15882 case X86::ATOMMAX32:
15883 case X86::ATOMMAX64:
15885 case X86::ATOMMIN8:
15886 case X86::ATOMMIN16:
15887 case X86::ATOMMIN32:
15888 case X86::ATOMMIN64:
15890 case X86::ATOMUMAX8:
15891 case X86::ATOMUMAX16:
15892 case X86::ATOMUMAX32:
15893 case X86::ATOMUMAX64:
15895 case X86::ATOMUMIN8:
15896 case X86::ATOMUMIN16:
15897 case X86::ATOMUMIN32:
15898 case X86::ATOMUMIN64:
15899 return EmitAtomicLoadArith(MI, BB);
15901 // This group does 64-bit operations on a 32-bit host.
15902 case X86::ATOMAND6432:
15903 case X86::ATOMOR6432:
15904 case X86::ATOMXOR6432:
15905 case X86::ATOMNAND6432:
15906 case X86::ATOMADD6432:
15907 case X86::ATOMSUB6432:
15908 case X86::ATOMMAX6432:
15909 case X86::ATOMMIN6432:
15910 case X86::ATOMUMAX6432:
15911 case X86::ATOMUMIN6432:
15912 case X86::ATOMSWAP6432:
15913 return EmitAtomicLoadArith6432(MI, BB);
15915 case X86::VASTART_SAVE_XMM_REGS:
15916 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15918 case X86::VAARG_64:
15919 return EmitVAARG64WithCustomInserter(MI, BB);
15921 case X86::EH_SjLj_SetJmp32:
15922 case X86::EH_SjLj_SetJmp64:
15923 return emitEHSjLjSetJmp(MI, BB);
15925 case X86::EH_SjLj_LongJmp32:
15926 case X86::EH_SjLj_LongJmp64:
15927 return emitEHSjLjLongJmp(MI, BB);
15931 //===----------------------------------------------------------------------===//
15932 // X86 Optimization Hooks
15933 //===----------------------------------------------------------------------===//
15935 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15938 const SelectionDAG &DAG,
15939 unsigned Depth) const {
15940 unsigned BitWidth = KnownZero.getBitWidth();
15941 unsigned Opc = Op.getOpcode();
15942 assert((Opc >= ISD::BUILTIN_OP_END ||
15943 Opc == ISD::INTRINSIC_WO_CHAIN ||
15944 Opc == ISD::INTRINSIC_W_CHAIN ||
15945 Opc == ISD::INTRINSIC_VOID) &&
15946 "Should use MaskedValueIsZero if you don't know whether Op"
15947 " is a target node!");
15949 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15963 // These nodes' second result is a boolean.
15964 if (Op.getResNo() == 0)
15967 case X86ISD::SETCC:
15968 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15970 case ISD::INTRINSIC_WO_CHAIN: {
15971 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15972 unsigned NumLoBits = 0;
15975 case Intrinsic::x86_sse_movmsk_ps:
15976 case Intrinsic::x86_avx_movmsk_ps_256:
15977 case Intrinsic::x86_sse2_movmsk_pd:
15978 case Intrinsic::x86_avx_movmsk_pd_256:
15979 case Intrinsic::x86_mmx_pmovmskb:
15980 case Intrinsic::x86_sse2_pmovmskb_128:
15981 case Intrinsic::x86_avx2_pmovmskb: {
15982 // High bits of movmskp{s|d}, pmovmskb are known zero.
15984 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15985 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15986 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15987 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15988 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15989 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15990 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15991 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15993 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16002 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16003 unsigned Depth) const {
16004 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16005 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16006 return Op.getValueType().getScalarType().getSizeInBits();
16012 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16013 /// node is a GlobalAddress + offset.
16014 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16015 const GlobalValue* &GA,
16016 int64_t &Offset) const {
16017 if (N->getOpcode() == X86ISD::Wrapper) {
16018 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16019 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16020 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16024 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16027 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16028 /// same as extracting the high 128-bit part of 256-bit vector and then
16029 /// inserting the result into the low part of a new 256-bit vector
16030 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16031 EVT VT = SVOp->getValueType(0);
16032 unsigned NumElems = VT.getVectorNumElements();
16034 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16035 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16036 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16037 SVOp->getMaskElt(j) >= 0)
16043 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16044 /// same as extracting the low 128-bit part of 256-bit vector and then
16045 /// inserting the result into the high part of a new 256-bit vector
16046 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16047 EVT VT = SVOp->getValueType(0);
16048 unsigned NumElems = VT.getVectorNumElements();
16050 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16051 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16052 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16053 SVOp->getMaskElt(j) >= 0)
16059 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16060 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16061 TargetLowering::DAGCombinerInfo &DCI,
16062 const X86Subtarget* Subtarget) {
16064 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16065 SDValue V1 = SVOp->getOperand(0);
16066 SDValue V2 = SVOp->getOperand(1);
16067 EVT VT = SVOp->getValueType(0);
16068 unsigned NumElems = VT.getVectorNumElements();
16070 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16071 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16075 // V UNDEF BUILD_VECTOR UNDEF
16077 // CONCAT_VECTOR CONCAT_VECTOR
16080 // RESULT: V + zero extended
16082 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16083 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16084 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16087 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16090 // To match the shuffle mask, the first half of the mask should
16091 // be exactly the first vector, and all the rest a splat with the
16092 // first element of the second one.
16093 for (unsigned i = 0; i != NumElems/2; ++i)
16094 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16095 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16098 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16099 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16100 if (Ld->hasNUsesOfValue(1, 0)) {
16101 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16102 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16104 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16105 array_lengthof(Ops),
16107 Ld->getPointerInfo(),
16108 Ld->getAlignment(),
16109 false/*isVolatile*/, true/*ReadMem*/,
16110 false/*WriteMem*/);
16112 // Make sure the newly-created LOAD is in the same position as Ld in
16113 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16114 // and update uses of Ld's output chain to use the TokenFactor.
16115 if (Ld->hasAnyUseOfValue(1)) {
16116 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16117 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16118 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16119 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16120 SDValue(ResNode.getNode(), 1));
16123 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16127 // Emit a zeroed vector and insert the desired subvector on its
16129 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16130 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16131 return DCI.CombineTo(N, InsV);
16134 //===--------------------------------------------------------------------===//
16135 // Combine some shuffles into subvector extracts and inserts:
16138 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16139 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16140 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16141 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16142 return DCI.CombineTo(N, InsV);
16145 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16146 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16147 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16148 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16149 return DCI.CombineTo(N, InsV);
16155 static SDValue PerformConcatCombine(SDNode *N, SelectionDAG &DAG,
16156 TargetLowering::DAGCombinerInfo &DCI,
16157 const X86Subtarget *Subtarget) {
16158 // Creating a v8i16 from a v4i16 argument and an undef runs into trouble in
16159 // type legalization and ends up spilling to the stack. Avoid that by
16160 // creating a vector first and bitcasting the result rather than
16161 // bitcasting the source then creating the vector. Similar problems with
16164 // No point in doing this after legalize, so early exit for that.
16165 if (!DCI.isBeforeLegalize())
16168 EVT VT = N->getValueType(0);
16169 SDValue Op0 = N->getOperand(0);
16170 SDValue Op1 = N->getOperand(1);
16171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16172 if (VT.getSizeInBits() == 128 && N->getNumOperands() == 2 &&
16173 Op1->getOpcode() == ISD::UNDEF &&
16174 Op0->getOpcode() == ISD::BITCAST &&
16175 !TLI.isTypeLegal(Op0->getValueType(0)) &&
16176 TLI.isTypeLegal(Op0->getOperand(0)->getValueType(0))) {
16177 SDValue Scalar = Op0->getOperand(0);
16178 // Any legal type here will be a simple value type.
16179 MVT SVT = Scalar->getValueType(0).getSimpleVT();
16180 // As a special case, bail out on MMX values.
16181 if (SVT == MVT::x86mmx)
16183 EVT NVT = MVT::getVectorVT(SVT, 2);
16184 SDLoc dl = SDLoc(N);
16185 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
16186 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);
16193 /// PerformShuffleCombine - Performs several different shuffle combines.
16194 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16195 TargetLowering::DAGCombinerInfo &DCI,
16196 const X86Subtarget *Subtarget) {
16198 EVT VT = N->getValueType(0);
16200 // Don't create instructions with illegal types after legalize types has run.
16201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16202 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16205 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16206 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16207 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16208 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16210 // Only handle 128 wide vector from here on.
16211 if (!VT.is128BitVector())
16214 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16215 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16216 // consecutive, non-overlapping, and in the right order.
16217 SmallVector<SDValue, 16> Elts;
16218 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16219 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16221 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16224 /// PerformTruncateCombine - Converts truncate operation to
16225 /// a sequence of vector shuffle operations.
16226 /// It is possible when we truncate 256-bit vector to 128-bit vector
16227 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16228 TargetLowering::DAGCombinerInfo &DCI,
16229 const X86Subtarget *Subtarget) {
16233 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16234 /// specific shuffle of a load can be folded into a single element load.
16235 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16236 /// shuffles have been customed lowered so we need to handle those here.
16237 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16238 TargetLowering::DAGCombinerInfo &DCI) {
16239 if (DCI.isBeforeLegalizeOps())
16242 SDValue InVec = N->getOperand(0);
16243 SDValue EltNo = N->getOperand(1);
16245 if (!isa<ConstantSDNode>(EltNo))
16248 EVT VT = InVec.getValueType();
16250 bool HasShuffleIntoBitcast = false;
16251 if (InVec.getOpcode() == ISD::BITCAST) {
16252 // Don't duplicate a load with other uses.
16253 if (!InVec.hasOneUse())
16255 EVT BCVT = InVec.getOperand(0).getValueType();
16256 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16258 InVec = InVec.getOperand(0);
16259 HasShuffleIntoBitcast = true;
16262 if (!isTargetShuffle(InVec.getOpcode()))
16265 // Don't duplicate a load with other uses.
16266 if (!InVec.hasOneUse())
16269 SmallVector<int, 16> ShuffleMask;
16271 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16275 // Select the input vector, guarding against out of range extract vector.
16276 unsigned NumElems = VT.getVectorNumElements();
16277 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16278 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16279 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16280 : InVec.getOperand(1);
16282 // If inputs to shuffle are the same for both ops, then allow 2 uses
16283 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16285 if (LdNode.getOpcode() == ISD::BITCAST) {
16286 // Don't duplicate a load with other uses.
16287 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16290 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16291 LdNode = LdNode.getOperand(0);
16294 if (!ISD::isNormalLoad(LdNode.getNode()))
16297 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16299 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16302 if (HasShuffleIntoBitcast) {
16303 // If there's a bitcast before the shuffle, check if the load type and
16304 // alignment is valid.
16305 unsigned Align = LN0->getAlignment();
16306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16307 unsigned NewAlign = TLI.getDataLayout()->
16308 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16310 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16314 // All checks match so transform back to vector_shuffle so that DAG combiner
16315 // can finish the job
16318 // Create shuffle node taking into account the case that its a unary shuffle
16319 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16320 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16321 InVec.getOperand(0), Shuffle,
16323 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16324 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16328 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16329 /// generation and convert it from being a bunch of shuffles and extracts
16330 /// to a simple store and scalar loads to extract the elements.
16331 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16332 TargetLowering::DAGCombinerInfo &DCI) {
16333 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16334 if (NewOp.getNode())
16337 SDValue InputVector = N->getOperand(0);
16338 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16339 // from mmx to v2i32 has a single usage.
16340 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16341 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16342 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16343 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16344 N->getValueType(0),
16345 InputVector.getNode()->getOperand(0));
16347 // Only operate on vectors of 4 elements, where the alternative shuffling
16348 // gets to be more expensive.
16349 if (InputVector.getValueType() != MVT::v4i32)
16352 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16353 // single use which is a sign-extend or zero-extend, and all elements are
16355 SmallVector<SDNode *, 4> Uses;
16356 unsigned ExtractedElements = 0;
16357 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16358 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16359 if (UI.getUse().getResNo() != InputVector.getResNo())
16362 SDNode *Extract = *UI;
16363 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16366 if (Extract->getValueType(0) != MVT::i32)
16368 if (!Extract->hasOneUse())
16370 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16371 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16373 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16376 // Record which element was extracted.
16377 ExtractedElements |=
16378 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16380 Uses.push_back(Extract);
16383 // If not all the elements were used, this may not be worthwhile.
16384 if (ExtractedElements != 15)
16387 // Ok, we've now decided to do the transformation.
16388 SDLoc dl(InputVector);
16390 // Store the value to a temporary stack slot.
16391 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16392 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16393 MachinePointerInfo(), false, false, 0);
16395 // Replace each use (extract) with a load of the appropriate element.
16396 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16397 UE = Uses.end(); UI != UE; ++UI) {
16398 SDNode *Extract = *UI;
16400 // cOMpute the element's address.
16401 SDValue Idx = Extract->getOperand(1);
16403 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16404 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16405 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16406 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16408 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16409 StackPtr, OffsetVal);
16411 // Load the scalar.
16412 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16413 ScalarAddr, MachinePointerInfo(),
16414 false, false, false, 0);
16416 // Replace the exact with the load.
16417 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16420 // The replacement was made in place; don't return anything.
16424 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16425 static std::pair<unsigned, bool>
16426 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16427 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16428 if (!VT.isVector())
16429 return std::make_pair(0, false);
16431 bool NeedSplit = false;
16432 switch (VT.getSimpleVT().SimpleTy) {
16433 default: return std::make_pair(0, false);
16437 if (!Subtarget->hasAVX2())
16439 if (!Subtarget->hasAVX())
16440 return std::make_pair(0, false);
16445 if (!Subtarget->hasSSE2())
16446 return std::make_pair(0, false);
16449 // SSE2 has only a small subset of the operations.
16450 bool hasUnsigned = Subtarget->hasSSE41() ||
16451 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16452 bool hasSigned = Subtarget->hasSSE41() ||
16453 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16455 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16458 // Check for x CC y ? x : y.
16459 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16460 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16465 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16468 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16471 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16474 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16476 // Check for x CC y ? y : x -- a min/max with reversed arms.
16477 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16478 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16483 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16486 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16489 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16492 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16496 return std::make_pair(Opc, NeedSplit);
16499 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16501 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16502 TargetLowering::DAGCombinerInfo &DCI,
16503 const X86Subtarget *Subtarget) {
16505 SDValue Cond = N->getOperand(0);
16506 // Get the LHS/RHS of the select.
16507 SDValue LHS = N->getOperand(1);
16508 SDValue RHS = N->getOperand(2);
16509 EVT VT = LHS.getValueType();
16510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16512 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16513 // instructions match the semantics of the common C idiom x<y?x:y but not
16514 // x<=y?x:y, because of how they handle negative zero (which can be
16515 // ignored in unsafe-math mode).
16516 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16517 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16518 (Subtarget->hasSSE2() ||
16519 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16520 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16522 unsigned Opcode = 0;
16523 // Check for x CC y ? x : y.
16524 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16525 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16529 // Converting this to a min would handle NaNs incorrectly, and swapping
16530 // the operands would cause it to handle comparisons between positive
16531 // and negative zero incorrectly.
16532 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16533 if (!DAG.getTarget().Options.UnsafeFPMath &&
16534 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16536 std::swap(LHS, RHS);
16538 Opcode = X86ISD::FMIN;
16541 // Converting this to a min would handle comparisons between positive
16542 // and negative zero incorrectly.
16543 if (!DAG.getTarget().Options.UnsafeFPMath &&
16544 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16546 Opcode = X86ISD::FMIN;
16549 // Converting this to a min would handle both negative zeros and NaNs
16550 // incorrectly, but we can swap the operands to fix both.
16551 std::swap(LHS, RHS);
16555 Opcode = X86ISD::FMIN;
16559 // Converting this to a max would handle comparisons between positive
16560 // and negative zero incorrectly.
16561 if (!DAG.getTarget().Options.UnsafeFPMath &&
16562 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16564 Opcode = X86ISD::FMAX;
16567 // Converting this to a max would handle NaNs incorrectly, and swapping
16568 // the operands would cause it to handle comparisons between positive
16569 // and negative zero incorrectly.
16570 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16571 if (!DAG.getTarget().Options.UnsafeFPMath &&
16572 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16574 std::swap(LHS, RHS);
16576 Opcode = X86ISD::FMAX;
16579 // Converting this to a max would handle both negative zeros and NaNs
16580 // incorrectly, but we can swap the operands to fix both.
16581 std::swap(LHS, RHS);
16585 Opcode = X86ISD::FMAX;
16588 // Check for x CC y ? y : x -- a min/max with reversed arms.
16589 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16590 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16594 // Converting this to a min would handle comparisons between positive
16595 // and negative zero incorrectly, and swapping the operands would
16596 // cause it to handle NaNs incorrectly.
16597 if (!DAG.getTarget().Options.UnsafeFPMath &&
16598 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16599 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16601 std::swap(LHS, RHS);
16603 Opcode = X86ISD::FMIN;
16606 // Converting this to a min would handle NaNs incorrectly.
16607 if (!DAG.getTarget().Options.UnsafeFPMath &&
16608 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16610 Opcode = X86ISD::FMIN;
16613 // Converting this to a min would handle both negative zeros and NaNs
16614 // incorrectly, but we can swap the operands to fix both.
16615 std::swap(LHS, RHS);
16619 Opcode = X86ISD::FMIN;
16623 // Converting this to a max would handle NaNs incorrectly.
16624 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16626 Opcode = X86ISD::FMAX;
16629 // Converting this to a max would handle comparisons between positive
16630 // and negative zero incorrectly, and swapping the operands would
16631 // cause it to handle NaNs incorrectly.
16632 if (!DAG.getTarget().Options.UnsafeFPMath &&
16633 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16634 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16636 std::swap(LHS, RHS);
16638 Opcode = X86ISD::FMAX;
16641 // Converting this to a max would handle both negative zeros and NaNs
16642 // incorrectly, but we can swap the operands to fix both.
16643 std::swap(LHS, RHS);
16647 Opcode = X86ISD::FMAX;
16653 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16656 if (Subtarget->hasAVX512() && VT.isVector() &&
16657 Cond.getValueType().getVectorElementType() == MVT::i1) {
16658 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16659 // lowering on AVX-512. In this case we convert it to
16660 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16661 // The same situation for all 128 and 256-bit vectors of i8 and i16
16662 EVT OpVT = LHS.getValueType();
16663 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16664 (OpVT.getVectorElementType() == MVT::i8 ||
16665 OpVT.getVectorElementType() == MVT::i16)) {
16666 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16667 DCI.AddToWorklist(Cond.getNode());
16668 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16671 // If this is a select between two integer constants, try to do some
16673 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16674 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16675 // Don't do this for crazy integer types.
16676 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16677 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16678 // so that TrueC (the true value) is larger than FalseC.
16679 bool NeedsCondInvert = false;
16681 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16682 // Efficiently invertible.
16683 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16684 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16685 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16686 NeedsCondInvert = true;
16687 std::swap(TrueC, FalseC);
16690 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16691 if (FalseC->getAPIntValue() == 0 &&
16692 TrueC->getAPIntValue().isPowerOf2()) {
16693 if (NeedsCondInvert) // Invert the condition if needed.
16694 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16695 DAG.getConstant(1, Cond.getValueType()));
16697 // Zero extend the condition if needed.
16698 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16700 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16701 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16702 DAG.getConstant(ShAmt, MVT::i8));
16705 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16706 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16707 if (NeedsCondInvert) // Invert the condition if needed.
16708 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16709 DAG.getConstant(1, Cond.getValueType()));
16711 // Zero extend the condition if needed.
16712 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16713 FalseC->getValueType(0), Cond);
16714 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16715 SDValue(FalseC, 0));
16718 // Optimize cases that will turn into an LEA instruction. This requires
16719 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16720 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16721 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16722 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16724 bool isFastMultiplier = false;
16726 switch ((unsigned char)Diff) {
16728 case 1: // result = add base, cond
16729 case 2: // result = lea base( , cond*2)
16730 case 3: // result = lea base(cond, cond*2)
16731 case 4: // result = lea base( , cond*4)
16732 case 5: // result = lea base(cond, cond*4)
16733 case 8: // result = lea base( , cond*8)
16734 case 9: // result = lea base(cond, cond*8)
16735 isFastMultiplier = true;
16740 if (isFastMultiplier) {
16741 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16742 if (NeedsCondInvert) // Invert the condition if needed.
16743 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16744 DAG.getConstant(1, Cond.getValueType()));
16746 // Zero extend the condition if needed.
16747 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16749 // Scale the condition by the difference.
16751 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16752 DAG.getConstant(Diff, Cond.getValueType()));
16754 // Add the base if non-zero.
16755 if (FalseC->getAPIntValue() != 0)
16756 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16757 SDValue(FalseC, 0));
16764 // Canonicalize max and min:
16765 // (x > y) ? x : y -> (x >= y) ? x : y
16766 // (x < y) ? x : y -> (x <= y) ? x : y
16767 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16768 // the need for an extra compare
16769 // against zero. e.g.
16770 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16772 // testl %edi, %edi
16774 // cmovgl %edi, %eax
16778 // cmovsl %eax, %edi
16779 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16780 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16781 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16782 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16787 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16788 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16789 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16790 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16795 // Early exit check
16796 if (!TLI.isTypeLegal(VT))
16799 // Match VSELECTs into subs with unsigned saturation.
16800 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16801 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16802 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16803 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16804 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16806 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16807 // left side invert the predicate to simplify logic below.
16809 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16811 CC = ISD::getSetCCInverse(CC, true);
16812 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16816 if (Other.getNode() && Other->getNumOperands() == 2 &&
16817 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16818 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16819 SDValue CondRHS = Cond->getOperand(1);
16821 // Look for a general sub with unsigned saturation first.
16822 // x >= y ? x-y : 0 --> subus x, y
16823 // x > y ? x-y : 0 --> subus x, y
16824 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16825 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16826 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16828 // If the RHS is a constant we have to reverse the const canonicalization.
16829 // x > C-1 ? x+-C : 0 --> subus x, C
16830 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16831 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16832 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16833 if (CondRHS.getConstantOperandVal(0) == -A-1)
16834 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16835 DAG.getConstant(-A, VT));
16838 // Another special case: If C was a sign bit, the sub has been
16839 // canonicalized into a xor.
16840 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16841 // it's safe to decanonicalize the xor?
16842 // x s< 0 ? x^C : 0 --> subus x, C
16843 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16844 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16845 isSplatVector(OpRHS.getNode())) {
16846 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16848 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16853 // Try to match a min/max vector operation.
16854 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16855 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16856 unsigned Opc = ret.first;
16857 bool NeedSplit = ret.second;
16859 if (Opc && NeedSplit) {
16860 unsigned NumElems = VT.getVectorNumElements();
16861 // Extract the LHS vectors
16862 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16863 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16865 // Extract the RHS vectors
16866 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16867 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16869 // Create min/max for each subvector
16870 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16871 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16873 // Merge the result
16874 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16876 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16879 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16880 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16881 // Check if SETCC has already been promoted
16882 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16884 assert(Cond.getValueType().isVector() &&
16885 "vector select expects a vector selector!");
16887 EVT IntVT = Cond.getValueType();
16888 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16889 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16891 if (!TValIsAllOnes && !FValIsAllZeros) {
16892 // Try invert the condition if true value is not all 1s and false value
16894 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16895 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16897 if (TValIsAllZeros || FValIsAllOnes) {
16898 SDValue CC = Cond.getOperand(2);
16899 ISD::CondCode NewCC =
16900 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16901 Cond.getOperand(0).getValueType().isInteger());
16902 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16903 std::swap(LHS, RHS);
16904 TValIsAllOnes = FValIsAllOnes;
16905 FValIsAllZeros = TValIsAllZeros;
16909 if (TValIsAllOnes || FValIsAllZeros) {
16912 if (TValIsAllOnes && FValIsAllZeros)
16914 else if (TValIsAllOnes)
16915 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16916 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16917 else if (FValIsAllZeros)
16918 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16919 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16921 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16925 // If we know that this node is legal then we know that it is going to be
16926 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16927 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16928 // to simplify previous instructions.
16929 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16930 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16931 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16933 // Don't optimize vector selects that map to mask-registers.
16937 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16938 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16940 APInt KnownZero, KnownOne;
16941 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16942 DCI.isBeforeLegalizeOps());
16943 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16944 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16945 DCI.CommitTargetLoweringOpt(TLO);
16951 // Check whether a boolean test is testing a boolean value generated by
16952 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16955 // Simplify the following patterns:
16956 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16957 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16958 // to (Op EFLAGS Cond)
16960 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16961 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16962 // to (Op EFLAGS !Cond)
16964 // where Op could be BRCOND or CMOV.
16966 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16967 // Quit if not CMP and SUB with its value result used.
16968 if (Cmp.getOpcode() != X86ISD::CMP &&
16969 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16972 // Quit if not used as a boolean value.
16973 if (CC != X86::COND_E && CC != X86::COND_NE)
16976 // Check CMP operands. One of them should be 0 or 1 and the other should be
16977 // an SetCC or extended from it.
16978 SDValue Op1 = Cmp.getOperand(0);
16979 SDValue Op2 = Cmp.getOperand(1);
16982 const ConstantSDNode* C = 0;
16983 bool needOppositeCond = (CC == X86::COND_E);
16984 bool checkAgainstTrue = false; // Is it a comparison against 1?
16986 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16988 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16990 else // Quit if all operands are not constants.
16993 if (C->getZExtValue() == 1) {
16994 needOppositeCond = !needOppositeCond;
16995 checkAgainstTrue = true;
16996 } else if (C->getZExtValue() != 0)
16997 // Quit if the constant is neither 0 or 1.
17000 bool truncatedToBoolWithAnd = false;
17001 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17002 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17003 SetCC.getOpcode() == ISD::TRUNCATE ||
17004 SetCC.getOpcode() == ISD::AND) {
17005 if (SetCC.getOpcode() == ISD::AND) {
17007 ConstantSDNode *CS;
17008 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17009 CS->getZExtValue() == 1)
17011 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17012 CS->getZExtValue() == 1)
17016 SetCC = SetCC.getOperand(OpIdx);
17017 truncatedToBoolWithAnd = true;
17019 SetCC = SetCC.getOperand(0);
17022 switch (SetCC.getOpcode()) {
17023 case X86ISD::SETCC_CARRY:
17024 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17025 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17026 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17027 // truncated to i1 using 'and'.
17028 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17030 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17031 "Invalid use of SETCC_CARRY!");
17033 case X86ISD::SETCC:
17034 // Set the condition code or opposite one if necessary.
17035 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17036 if (needOppositeCond)
17037 CC = X86::GetOppositeBranchCondition(CC);
17038 return SetCC.getOperand(1);
17039 case X86ISD::CMOV: {
17040 // Check whether false/true value has canonical one, i.e. 0 or 1.
17041 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17042 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17043 // Quit if true value is not a constant.
17046 // Quit if false value is not a constant.
17048 SDValue Op = SetCC.getOperand(0);
17049 // Skip 'zext' or 'trunc' node.
17050 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17051 Op.getOpcode() == ISD::TRUNCATE)
17052 Op = Op.getOperand(0);
17053 // A special case for rdrand/rdseed, where 0 is set if false cond is
17055 if ((Op.getOpcode() != X86ISD::RDRAND &&
17056 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17059 // Quit if false value is not the constant 0 or 1.
17060 bool FValIsFalse = true;
17061 if (FVal && FVal->getZExtValue() != 0) {
17062 if (FVal->getZExtValue() != 1)
17064 // If FVal is 1, opposite cond is needed.
17065 needOppositeCond = !needOppositeCond;
17066 FValIsFalse = false;
17068 // Quit if TVal is not the constant opposite of FVal.
17069 if (FValIsFalse && TVal->getZExtValue() != 1)
17071 if (!FValIsFalse && TVal->getZExtValue() != 0)
17073 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17074 if (needOppositeCond)
17075 CC = X86::GetOppositeBranchCondition(CC);
17076 return SetCC.getOperand(3);
17083 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17084 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17085 TargetLowering::DAGCombinerInfo &DCI,
17086 const X86Subtarget *Subtarget) {
17089 // If the flag operand isn't dead, don't touch this CMOV.
17090 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17093 SDValue FalseOp = N->getOperand(0);
17094 SDValue TrueOp = N->getOperand(1);
17095 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17096 SDValue Cond = N->getOperand(3);
17098 if (CC == X86::COND_E || CC == X86::COND_NE) {
17099 switch (Cond.getOpcode()) {
17103 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17104 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17105 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17111 Flags = checkBoolTestSetCCCombine(Cond, CC);
17112 if (Flags.getNode() &&
17113 // Extra check as FCMOV only supports a subset of X86 cond.
17114 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17115 SDValue Ops[] = { FalseOp, TrueOp,
17116 DAG.getConstant(CC, MVT::i8), Flags };
17117 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17118 Ops, array_lengthof(Ops));
17121 // If this is a select between two integer constants, try to do some
17122 // optimizations. Note that the operands are ordered the opposite of SELECT
17124 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17125 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17126 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17127 // larger than FalseC (the false value).
17128 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17129 CC = X86::GetOppositeBranchCondition(CC);
17130 std::swap(TrueC, FalseC);
17131 std::swap(TrueOp, FalseOp);
17134 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17135 // This is efficient for any integer data type (including i8/i16) and
17137 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17138 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17139 DAG.getConstant(CC, MVT::i8), Cond);
17141 // Zero extend the condition if needed.
17142 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17144 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17145 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17146 DAG.getConstant(ShAmt, MVT::i8));
17147 if (N->getNumValues() == 2) // Dead flag value?
17148 return DCI.CombineTo(N, Cond, SDValue());
17152 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17153 // for any integer data type, including i8/i16.
17154 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17155 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17156 DAG.getConstant(CC, MVT::i8), Cond);
17158 // Zero extend the condition if needed.
17159 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17160 FalseC->getValueType(0), Cond);
17161 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17162 SDValue(FalseC, 0));
17164 if (N->getNumValues() == 2) // Dead flag value?
17165 return DCI.CombineTo(N, Cond, SDValue());
17169 // Optimize cases that will turn into an LEA instruction. This requires
17170 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17171 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17172 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17173 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17175 bool isFastMultiplier = false;
17177 switch ((unsigned char)Diff) {
17179 case 1: // result = add base, cond
17180 case 2: // result = lea base( , cond*2)
17181 case 3: // result = lea base(cond, cond*2)
17182 case 4: // result = lea base( , cond*4)
17183 case 5: // result = lea base(cond, cond*4)
17184 case 8: // result = lea base( , cond*8)
17185 case 9: // result = lea base(cond, cond*8)
17186 isFastMultiplier = true;
17191 if (isFastMultiplier) {
17192 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17193 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17194 DAG.getConstant(CC, MVT::i8), Cond);
17195 // Zero extend the condition if needed.
17196 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17198 // Scale the condition by the difference.
17200 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17201 DAG.getConstant(Diff, Cond.getValueType()));
17203 // Add the base if non-zero.
17204 if (FalseC->getAPIntValue() != 0)
17205 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17206 SDValue(FalseC, 0));
17207 if (N->getNumValues() == 2) // Dead flag value?
17208 return DCI.CombineTo(N, Cond, SDValue());
17215 // Handle these cases:
17216 // (select (x != c), e, c) -> select (x != c), e, x),
17217 // (select (x == c), c, e) -> select (x == c), x, e)
17218 // where the c is an integer constant, and the "select" is the combination
17219 // of CMOV and CMP.
17221 // The rationale for this change is that the conditional-move from a constant
17222 // needs two instructions, however, conditional-move from a register needs
17223 // only one instruction.
17225 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17226 // some instruction-combining opportunities. This opt needs to be
17227 // postponed as late as possible.
17229 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17230 // the DCI.xxxx conditions are provided to postpone the optimization as
17231 // late as possible.
17233 ConstantSDNode *CmpAgainst = 0;
17234 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17235 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17236 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17238 if (CC == X86::COND_NE &&
17239 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17240 CC = X86::GetOppositeBranchCondition(CC);
17241 std::swap(TrueOp, FalseOp);
17244 if (CC == X86::COND_E &&
17245 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17246 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17247 DAG.getConstant(CC, MVT::i8), Cond };
17248 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17249 array_lengthof(Ops));
17257 /// PerformMulCombine - Optimize a single multiply with constant into two
17258 /// in order to implement it with two cheaper instructions, e.g.
17259 /// LEA + SHL, LEA + LEA.
17260 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17261 TargetLowering::DAGCombinerInfo &DCI) {
17262 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17265 EVT VT = N->getValueType(0);
17266 if (VT != MVT::i64)
17269 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17272 uint64_t MulAmt = C->getZExtValue();
17273 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17276 uint64_t MulAmt1 = 0;
17277 uint64_t MulAmt2 = 0;
17278 if ((MulAmt % 9) == 0) {
17280 MulAmt2 = MulAmt / 9;
17281 } else if ((MulAmt % 5) == 0) {
17283 MulAmt2 = MulAmt / 5;
17284 } else if ((MulAmt % 3) == 0) {
17286 MulAmt2 = MulAmt / 3;
17289 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17292 if (isPowerOf2_64(MulAmt2) &&
17293 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17294 // If second multiplifer is pow2, issue it first. We want the multiply by
17295 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17297 std::swap(MulAmt1, MulAmt2);
17300 if (isPowerOf2_64(MulAmt1))
17301 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17302 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17304 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17305 DAG.getConstant(MulAmt1, VT));
17307 if (isPowerOf2_64(MulAmt2))
17308 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17309 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17311 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17312 DAG.getConstant(MulAmt2, VT));
17314 // Do not add new nodes to DAG combiner worklist.
17315 DCI.CombineTo(N, NewMul, false);
17320 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17321 SDValue N0 = N->getOperand(0);
17322 SDValue N1 = N->getOperand(1);
17323 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17324 EVT VT = N0.getValueType();
17326 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17327 // since the result of setcc_c is all zero's or all ones.
17328 if (VT.isInteger() && !VT.isVector() &&
17329 N1C && N0.getOpcode() == ISD::AND &&
17330 N0.getOperand(1).getOpcode() == ISD::Constant) {
17331 SDValue N00 = N0.getOperand(0);
17332 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17333 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17334 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17335 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17336 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17337 APInt ShAmt = N1C->getAPIntValue();
17338 Mask = Mask.shl(ShAmt);
17340 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17341 N00, DAG.getConstant(Mask, VT));
17345 // Hardware support for vector shifts is sparse which makes us scalarize the
17346 // vector operations in many cases. Also, on sandybridge ADD is faster than
17348 // (shl V, 1) -> add V,V
17349 if (isSplatVector(N1.getNode())) {
17350 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17351 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17352 // We shift all of the values by one. In many cases we do not have
17353 // hardware support for this operation. This is better expressed as an ADD
17355 if (N1C && (1 == N1C->getZExtValue())) {
17356 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17363 /// \brief Returns a vector of 0s if the node in input is a vector logical
17364 /// shift by a constant amount which is known to be bigger than or equal
17365 /// to the vector element size in bits.
17366 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17367 const X86Subtarget *Subtarget) {
17368 EVT VT = N->getValueType(0);
17370 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17371 (!Subtarget->hasInt256() ||
17372 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17375 SDValue Amt = N->getOperand(1);
17377 if (isSplatVector(Amt.getNode())) {
17378 SDValue SclrAmt = Amt->getOperand(0);
17379 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17380 APInt ShiftAmt = C->getAPIntValue();
17381 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17383 // SSE2/AVX2 logical shifts always return a vector of 0s
17384 // if the shift amount is bigger than or equal to
17385 // the element size. The constant shift amount will be
17386 // encoded as a 8-bit immediate.
17387 if (ShiftAmt.trunc(8).uge(MaxAmount))
17388 return getZeroVector(VT, Subtarget, DAG, DL);
17395 /// PerformShiftCombine - Combine shifts.
17396 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17397 TargetLowering::DAGCombinerInfo &DCI,
17398 const X86Subtarget *Subtarget) {
17399 if (N->getOpcode() == ISD::SHL) {
17400 SDValue V = PerformSHLCombine(N, DAG);
17401 if (V.getNode()) return V;
17404 if (N->getOpcode() != ISD::SRA) {
17405 // Try to fold this logical shift into a zero vector.
17406 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17407 if (V.getNode()) return V;
17413 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17414 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17415 // and friends. Likewise for OR -> CMPNEQSS.
17416 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17417 TargetLowering::DAGCombinerInfo &DCI,
17418 const X86Subtarget *Subtarget) {
17421 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17422 // we're requiring SSE2 for both.
17423 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17424 SDValue N0 = N->getOperand(0);
17425 SDValue N1 = N->getOperand(1);
17426 SDValue CMP0 = N0->getOperand(1);
17427 SDValue CMP1 = N1->getOperand(1);
17430 // The SETCCs should both refer to the same CMP.
17431 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17434 SDValue CMP00 = CMP0->getOperand(0);
17435 SDValue CMP01 = CMP0->getOperand(1);
17436 EVT VT = CMP00.getValueType();
17438 if (VT == MVT::f32 || VT == MVT::f64) {
17439 bool ExpectingFlags = false;
17440 // Check for any users that want flags:
17441 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17442 !ExpectingFlags && UI != UE; ++UI)
17443 switch (UI->getOpcode()) {
17448 ExpectingFlags = true;
17450 case ISD::CopyToReg:
17451 case ISD::SIGN_EXTEND:
17452 case ISD::ZERO_EXTEND:
17453 case ISD::ANY_EXTEND:
17457 if (!ExpectingFlags) {
17458 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17459 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17461 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17462 X86::CondCode tmp = cc0;
17467 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17468 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17469 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17470 X86ISD::NodeType NTOperator = is64BitFP ?
17471 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17472 // FIXME: need symbolic constants for these magic numbers.
17473 // See X86ATTInstPrinter.cpp:printSSECC().
17474 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17475 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17476 DAG.getConstant(x86cc, MVT::i8));
17477 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17479 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17480 DAG.getConstant(1, MVT::i32));
17481 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17482 return OneBitOfTruth;
17490 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17491 /// so it can be folded inside ANDNP.
17492 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17493 EVT VT = N->getValueType(0);
17495 // Match direct AllOnes for 128 and 256-bit vectors
17496 if (ISD::isBuildVectorAllOnes(N))
17499 // Look through a bit convert.
17500 if (N->getOpcode() == ISD::BITCAST)
17501 N = N->getOperand(0).getNode();
17503 // Sometimes the operand may come from a insert_subvector building a 256-bit
17505 if (VT.is256BitVector() &&
17506 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17507 SDValue V1 = N->getOperand(0);
17508 SDValue V2 = N->getOperand(1);
17510 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17511 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17512 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17513 ISD::isBuildVectorAllOnes(V2.getNode()))
17520 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17521 // register. In most cases we actually compare or select YMM-sized registers
17522 // and mixing the two types creates horrible code. This method optimizes
17523 // some of the transition sequences.
17524 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17525 TargetLowering::DAGCombinerInfo &DCI,
17526 const X86Subtarget *Subtarget) {
17527 EVT VT = N->getValueType(0);
17528 if (!VT.is256BitVector())
17531 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17532 N->getOpcode() == ISD::ZERO_EXTEND ||
17533 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17535 SDValue Narrow = N->getOperand(0);
17536 EVT NarrowVT = Narrow->getValueType(0);
17537 if (!NarrowVT.is128BitVector())
17540 if (Narrow->getOpcode() != ISD::XOR &&
17541 Narrow->getOpcode() != ISD::AND &&
17542 Narrow->getOpcode() != ISD::OR)
17545 SDValue N0 = Narrow->getOperand(0);
17546 SDValue N1 = Narrow->getOperand(1);
17549 // The Left side has to be a trunc.
17550 if (N0.getOpcode() != ISD::TRUNCATE)
17553 // The type of the truncated inputs.
17554 EVT WideVT = N0->getOperand(0)->getValueType(0);
17558 // The right side has to be a 'trunc' or a constant vector.
17559 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17560 bool RHSConst = (isSplatVector(N1.getNode()) &&
17561 isa<ConstantSDNode>(N1->getOperand(0)));
17562 if (!RHSTrunc && !RHSConst)
17565 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17567 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17570 // Set N0 and N1 to hold the inputs to the new wide operation.
17571 N0 = N0->getOperand(0);
17573 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17574 N1->getOperand(0));
17575 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17576 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17577 } else if (RHSTrunc) {
17578 N1 = N1->getOperand(0);
17581 // Generate the wide operation.
17582 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17583 unsigned Opcode = N->getOpcode();
17585 case ISD::ANY_EXTEND:
17587 case ISD::ZERO_EXTEND: {
17588 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17589 APInt Mask = APInt::getAllOnesValue(InBits);
17590 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17591 return DAG.getNode(ISD::AND, DL, VT,
17592 Op, DAG.getConstant(Mask, VT));
17594 case ISD::SIGN_EXTEND:
17595 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17596 Op, DAG.getValueType(NarrowVT));
17598 llvm_unreachable("Unexpected opcode");
17602 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17603 TargetLowering::DAGCombinerInfo &DCI,
17604 const X86Subtarget *Subtarget) {
17605 EVT VT = N->getValueType(0);
17606 if (DCI.isBeforeLegalizeOps())
17609 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17613 // Create BLSI, BLSR, and BZHI instructions
17614 // BLSI is X & (-X)
17615 // BLSR is X & (X-1)
17616 // BZHI is X & ((1 << Y) - 1)
17617 // BEXTR is ((X >> imm) & (2**size-1))
17618 if (VT == MVT::i32 || VT == MVT::i64) {
17619 SDValue N0 = N->getOperand(0);
17620 SDValue N1 = N->getOperand(1);
17623 if (Subtarget->hasBMI()) {
17624 // Check LHS for neg
17625 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17626 isZero(N0.getOperand(0)))
17627 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17629 // Check RHS for neg
17630 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17631 isZero(N1.getOperand(0)))
17632 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17634 // Check LHS for X-1
17635 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17636 isAllOnes(N0.getOperand(1)))
17637 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17639 // Check RHS for X-1
17640 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17641 isAllOnes(N1.getOperand(1)))
17642 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17645 if (Subtarget->hasBMI2()) {
17646 // Check for (and (add (shl 1, Y), -1), X)
17647 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17648 SDValue N00 = N0.getOperand(0);
17649 if (N00.getOpcode() == ISD::SHL) {
17650 SDValue N001 = N00.getOperand(1);
17651 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17652 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17653 if (C && C->getZExtValue() == 1)
17654 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17658 // Check for (and X, (add (shl 1, Y), -1))
17659 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17660 SDValue N10 = N1.getOperand(0);
17661 if (N10.getOpcode() == ISD::SHL) {
17662 SDValue N101 = N10.getOperand(1);
17663 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17664 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17665 if (C && C->getZExtValue() == 1)
17666 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17671 // Check for BEXTR.
17672 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17673 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17674 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17675 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17676 if (MaskNode && ShiftNode) {
17677 uint64_t Mask = MaskNode->getZExtValue();
17678 uint64_t Shift = ShiftNode->getZExtValue();
17679 if (isMask_64(Mask)) {
17680 uint64_t MaskSize = CountPopulation_64(Mask);
17681 if (Shift + MaskSize <= VT.getSizeInBits())
17682 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17683 DAG.getConstant(Shift | (MaskSize << 8), VT));
17691 // Want to form ANDNP nodes:
17692 // 1) In the hopes of then easily combining them with OR and AND nodes
17693 // to form PBLEND/PSIGN.
17694 // 2) To match ANDN packed intrinsics
17695 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17698 SDValue N0 = N->getOperand(0);
17699 SDValue N1 = N->getOperand(1);
17702 // Check LHS for vnot
17703 if (N0.getOpcode() == ISD::XOR &&
17704 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17705 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17706 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17708 // Check RHS for vnot
17709 if (N1.getOpcode() == ISD::XOR &&
17710 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17711 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17712 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17717 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17718 TargetLowering::DAGCombinerInfo &DCI,
17719 const X86Subtarget *Subtarget) {
17720 EVT VT = N->getValueType(0);
17721 if (DCI.isBeforeLegalizeOps())
17724 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17728 SDValue N0 = N->getOperand(0);
17729 SDValue N1 = N->getOperand(1);
17731 // look for psign/blend
17732 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17733 if (!Subtarget->hasSSSE3() ||
17734 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17737 // Canonicalize pandn to RHS
17738 if (N0.getOpcode() == X86ISD::ANDNP)
17740 // or (and (m, y), (pandn m, x))
17741 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17742 SDValue Mask = N1.getOperand(0);
17743 SDValue X = N1.getOperand(1);
17745 if (N0.getOperand(0) == Mask)
17746 Y = N0.getOperand(1);
17747 if (N0.getOperand(1) == Mask)
17748 Y = N0.getOperand(0);
17750 // Check to see if the mask appeared in both the AND and ANDNP and
17754 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17755 // Look through mask bitcast.
17756 if (Mask.getOpcode() == ISD::BITCAST)
17757 Mask = Mask.getOperand(0);
17758 if (X.getOpcode() == ISD::BITCAST)
17759 X = X.getOperand(0);
17760 if (Y.getOpcode() == ISD::BITCAST)
17761 Y = Y.getOperand(0);
17763 EVT MaskVT = Mask.getValueType();
17765 // Validate that the Mask operand is a vector sra node.
17766 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17767 // there is no psrai.b
17768 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17769 unsigned SraAmt = ~0;
17770 if (Mask.getOpcode() == ISD::SRA) {
17771 SDValue Amt = Mask.getOperand(1);
17772 if (isSplatVector(Amt.getNode())) {
17773 SDValue SclrAmt = Amt->getOperand(0);
17774 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17775 SraAmt = C->getZExtValue();
17777 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17778 SDValue SraC = Mask.getOperand(1);
17779 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17781 if ((SraAmt + 1) != EltBits)
17786 // Now we know we at least have a plendvb with the mask val. See if
17787 // we can form a psignb/w/d.
17788 // psign = x.type == y.type == mask.type && y = sub(0, x);
17789 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17790 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17791 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17792 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17793 "Unsupported VT for PSIGN");
17794 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17795 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17797 // PBLENDVB only available on SSE 4.1
17798 if (!Subtarget->hasSSE41())
17801 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17803 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17804 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17805 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17806 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17807 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17811 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17814 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17815 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17817 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17819 if (!N0.hasOneUse() || !N1.hasOneUse())
17822 SDValue ShAmt0 = N0.getOperand(1);
17823 if (ShAmt0.getValueType() != MVT::i8)
17825 SDValue ShAmt1 = N1.getOperand(1);
17826 if (ShAmt1.getValueType() != MVT::i8)
17828 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17829 ShAmt0 = ShAmt0.getOperand(0);
17830 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17831 ShAmt1 = ShAmt1.getOperand(0);
17834 unsigned Opc = X86ISD::SHLD;
17835 SDValue Op0 = N0.getOperand(0);
17836 SDValue Op1 = N1.getOperand(0);
17837 if (ShAmt0.getOpcode() == ISD::SUB) {
17838 Opc = X86ISD::SHRD;
17839 std::swap(Op0, Op1);
17840 std::swap(ShAmt0, ShAmt1);
17843 unsigned Bits = VT.getSizeInBits();
17844 if (ShAmt1.getOpcode() == ISD::SUB) {
17845 SDValue Sum = ShAmt1.getOperand(0);
17846 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17847 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17848 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17849 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17850 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17851 return DAG.getNode(Opc, DL, VT,
17853 DAG.getNode(ISD::TRUNCATE, DL,
17856 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17857 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17859 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17860 return DAG.getNode(Opc, DL, VT,
17861 N0.getOperand(0), N1.getOperand(0),
17862 DAG.getNode(ISD::TRUNCATE, DL,
17869 // Generate NEG and CMOV for integer abs.
17870 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17871 EVT VT = N->getValueType(0);
17873 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17874 // 8-bit integer abs to NEG and CMOV.
17875 if (VT.isInteger() && VT.getSizeInBits() == 8)
17878 SDValue N0 = N->getOperand(0);
17879 SDValue N1 = N->getOperand(1);
17882 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17883 // and change it to SUB and CMOV.
17884 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17885 N0.getOpcode() == ISD::ADD &&
17886 N0.getOperand(1) == N1 &&
17887 N1.getOpcode() == ISD::SRA &&
17888 N1.getOperand(0) == N0.getOperand(0))
17889 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17890 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17891 // Generate SUB & CMOV.
17892 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17893 DAG.getConstant(0, VT), N0.getOperand(0));
17895 SDValue Ops[] = { N0.getOperand(0), Neg,
17896 DAG.getConstant(X86::COND_GE, MVT::i8),
17897 SDValue(Neg.getNode(), 1) };
17898 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17899 Ops, array_lengthof(Ops));
17904 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17905 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17906 TargetLowering::DAGCombinerInfo &DCI,
17907 const X86Subtarget *Subtarget) {
17908 EVT VT = N->getValueType(0);
17909 if (DCI.isBeforeLegalizeOps())
17912 if (Subtarget->hasCMov()) {
17913 SDValue RV = performIntegerAbsCombine(N, DAG);
17918 // Try forming BMI if it is available.
17919 if (!Subtarget->hasBMI())
17922 if (VT != MVT::i32 && VT != MVT::i64)
17925 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17927 // Create BLSMSK instructions by finding X ^ (X-1)
17928 SDValue N0 = N->getOperand(0);
17929 SDValue N1 = N->getOperand(1);
17932 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17933 isAllOnes(N0.getOperand(1)))
17934 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17936 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17937 isAllOnes(N1.getOperand(1)))
17938 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17943 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17944 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17945 TargetLowering::DAGCombinerInfo &DCI,
17946 const X86Subtarget *Subtarget) {
17947 LoadSDNode *Ld = cast<LoadSDNode>(N);
17948 EVT RegVT = Ld->getValueType(0);
17949 EVT MemVT = Ld->getMemoryVT();
17951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17952 unsigned RegSz = RegVT.getSizeInBits();
17954 // On Sandybridge unaligned 256bit loads are inefficient.
17955 ISD::LoadExtType Ext = Ld->getExtensionType();
17956 unsigned Alignment = Ld->getAlignment();
17957 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17958 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17959 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17960 unsigned NumElems = RegVT.getVectorNumElements();
17964 SDValue Ptr = Ld->getBasePtr();
17965 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17967 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17969 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17970 Ld->getPointerInfo(), Ld->isVolatile(),
17971 Ld->isNonTemporal(), Ld->isInvariant(),
17973 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17974 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17975 Ld->getPointerInfo(), Ld->isVolatile(),
17976 Ld->isNonTemporal(), Ld->isInvariant(),
17977 std::min(16U, Alignment));
17978 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17980 Load2.getValue(1));
17982 SDValue NewVec = DAG.getUNDEF(RegVT);
17983 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17984 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17985 return DCI.CombineTo(N, NewVec, TF, true);
17988 // If this is a vector EXT Load then attempt to optimize it using a
17989 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17990 // expansion is still better than scalar code.
17991 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17992 // emit a shuffle and a arithmetic shift.
17993 // TODO: It is possible to support ZExt by zeroing the undef values
17994 // during the shuffle phase or after the shuffle.
17995 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
17996 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
17997 assert(MemVT != RegVT && "Cannot extend to the same type");
17998 assert(MemVT.isVector() && "Must load a vector from memory");
18000 unsigned NumElems = RegVT.getVectorNumElements();
18001 unsigned MemSz = MemVT.getSizeInBits();
18002 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18004 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18007 // All sizes must be a power of two.
18008 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18011 // Attempt to load the original value using scalar loads.
18012 // Find the largest scalar type that divides the total loaded size.
18013 MVT SclrLoadTy = MVT::i8;
18014 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18015 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18016 MVT Tp = (MVT::SimpleValueType)tp;
18017 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18022 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18023 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18025 SclrLoadTy = MVT::f64;
18027 // Calculate the number of scalar loads that we need to perform
18028 // in order to load our vector from memory.
18029 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18030 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18033 unsigned loadRegZize = RegSz;
18034 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18037 // Represent our vector as a sequence of elements which are the
18038 // largest scalar that we can load.
18039 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18040 loadRegZize/SclrLoadTy.getSizeInBits());
18042 // Represent the data using the same element type that is stored in
18043 // memory. In practice, we ''widen'' MemVT.
18045 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18046 loadRegZize/MemVT.getScalarType().getSizeInBits());
18048 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18049 "Invalid vector type");
18051 // We can't shuffle using an illegal type.
18052 if (!TLI.isTypeLegal(WideVecVT))
18055 SmallVector<SDValue, 8> Chains;
18056 SDValue Ptr = Ld->getBasePtr();
18057 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18058 TLI.getPointerTy());
18059 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18061 for (unsigned i = 0; i < NumLoads; ++i) {
18062 // Perform a single load.
18063 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18064 Ptr, Ld->getPointerInfo(),
18065 Ld->isVolatile(), Ld->isNonTemporal(),
18066 Ld->isInvariant(), Ld->getAlignment());
18067 Chains.push_back(ScalarLoad.getValue(1));
18068 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18069 // another round of DAGCombining.
18071 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18073 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18074 ScalarLoad, DAG.getIntPtrConstant(i));
18076 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18079 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18082 // Bitcast the loaded value to a vector of the original element type, in
18083 // the size of the target vector type.
18084 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18085 unsigned SizeRatio = RegSz/MemSz;
18087 if (Ext == ISD::SEXTLOAD) {
18088 // If we have SSE4.1 we can directly emit a VSEXT node.
18089 if (Subtarget->hasSSE41()) {
18090 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18091 return DCI.CombineTo(N, Sext, TF, true);
18094 // Otherwise we'll shuffle the small elements in the high bits of the
18095 // larger type and perform an arithmetic shift. If the shift is not legal
18096 // it's better to scalarize.
18097 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18100 // Redistribute the loaded elements into the different locations.
18101 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18102 for (unsigned i = 0; i != NumElems; ++i)
18103 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18105 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18106 DAG.getUNDEF(WideVecVT),
18109 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18111 // Build the arithmetic shift.
18112 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18113 MemVT.getVectorElementType().getSizeInBits();
18114 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18115 DAG.getConstant(Amt, RegVT));
18117 return DCI.CombineTo(N, Shuff, TF, true);
18120 // Redistribute the loaded elements into the different locations.
18121 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18122 for (unsigned i = 0; i != NumElems; ++i)
18123 ShuffleVec[i*SizeRatio] = i;
18125 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18126 DAG.getUNDEF(WideVecVT),
18129 // Bitcast to the requested type.
18130 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18131 // Replace the original load with the new sequence
18132 // and return the new chain.
18133 return DCI.CombineTo(N, Shuff, TF, true);
18139 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18140 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18141 const X86Subtarget *Subtarget) {
18142 StoreSDNode *St = cast<StoreSDNode>(N);
18143 EVT VT = St->getValue().getValueType();
18144 EVT StVT = St->getMemoryVT();
18146 SDValue StoredVal = St->getOperand(1);
18147 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18149 // If we are saving a concatenation of two XMM registers, perform two stores.
18150 // On Sandy Bridge, 256-bit memory operations are executed by two
18151 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18152 // memory operation.
18153 unsigned Alignment = St->getAlignment();
18154 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18155 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18156 StVT == VT && !IsAligned) {
18157 unsigned NumElems = VT.getVectorNumElements();
18161 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18162 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18164 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18165 SDValue Ptr0 = St->getBasePtr();
18166 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18168 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18169 St->getPointerInfo(), St->isVolatile(),
18170 St->isNonTemporal(), Alignment);
18171 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18172 St->getPointerInfo(), St->isVolatile(),
18173 St->isNonTemporal(),
18174 std::min(16U, Alignment));
18175 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18178 // Optimize trunc store (of multiple scalars) to shuffle and store.
18179 // First, pack all of the elements in one place. Next, store to memory
18180 // in fewer chunks.
18181 if (St->isTruncatingStore() && VT.isVector()) {
18182 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18183 unsigned NumElems = VT.getVectorNumElements();
18184 assert(StVT != VT && "Cannot truncate to the same type");
18185 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18186 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18188 // From, To sizes and ElemCount must be pow of two
18189 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18190 // We are going to use the original vector elt for storing.
18191 // Accumulated smaller vector elements must be a multiple of the store size.
18192 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18194 unsigned SizeRatio = FromSz / ToSz;
18196 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18198 // Create a type on which we perform the shuffle
18199 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18200 StVT.getScalarType(), NumElems*SizeRatio);
18202 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18204 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18205 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18206 for (unsigned i = 0; i != NumElems; ++i)
18207 ShuffleVec[i] = i * SizeRatio;
18209 // Can't shuffle using an illegal type.
18210 if (!TLI.isTypeLegal(WideVecVT))
18213 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18214 DAG.getUNDEF(WideVecVT),
18216 // At this point all of the data is stored at the bottom of the
18217 // register. We now need to save it to mem.
18219 // Find the largest store unit
18220 MVT StoreType = MVT::i8;
18221 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18222 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18223 MVT Tp = (MVT::SimpleValueType)tp;
18224 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18228 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18229 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18230 (64 <= NumElems * ToSz))
18231 StoreType = MVT::f64;
18233 // Bitcast the original vector into a vector of store-size units
18234 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18235 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18236 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18237 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18238 SmallVector<SDValue, 8> Chains;
18239 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18240 TLI.getPointerTy());
18241 SDValue Ptr = St->getBasePtr();
18243 // Perform one or more big stores into memory.
18244 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18245 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18246 StoreType, ShuffWide,
18247 DAG.getIntPtrConstant(i));
18248 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18249 St->getPointerInfo(), St->isVolatile(),
18250 St->isNonTemporal(), St->getAlignment());
18251 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18252 Chains.push_back(Ch);
18255 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18259 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18260 // the FP state in cases where an emms may be missing.
18261 // A preferable solution to the general problem is to figure out the right
18262 // places to insert EMMS. This qualifies as a quick hack.
18264 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18265 if (VT.getSizeInBits() != 64)
18268 const Function *F = DAG.getMachineFunction().getFunction();
18269 bool NoImplicitFloatOps = F->getAttributes().
18270 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18271 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18272 && Subtarget->hasSSE2();
18273 if ((VT.isVector() ||
18274 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18275 isa<LoadSDNode>(St->getValue()) &&
18276 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18277 St->getChain().hasOneUse() && !St->isVolatile()) {
18278 SDNode* LdVal = St->getValue().getNode();
18279 LoadSDNode *Ld = 0;
18280 int TokenFactorIndex = -1;
18281 SmallVector<SDValue, 8> Ops;
18282 SDNode* ChainVal = St->getChain().getNode();
18283 // Must be a store of a load. We currently handle two cases: the load
18284 // is a direct child, and it's under an intervening TokenFactor. It is
18285 // possible to dig deeper under nested TokenFactors.
18286 if (ChainVal == LdVal)
18287 Ld = cast<LoadSDNode>(St->getChain());
18288 else if (St->getValue().hasOneUse() &&
18289 ChainVal->getOpcode() == ISD::TokenFactor) {
18290 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18291 if (ChainVal->getOperand(i).getNode() == LdVal) {
18292 TokenFactorIndex = i;
18293 Ld = cast<LoadSDNode>(St->getValue());
18295 Ops.push_back(ChainVal->getOperand(i));
18299 if (!Ld || !ISD::isNormalLoad(Ld))
18302 // If this is not the MMX case, i.e. we are just turning i64 load/store
18303 // into f64 load/store, avoid the transformation if there are multiple
18304 // uses of the loaded value.
18305 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18310 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18311 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18313 if (Subtarget->is64Bit() || F64IsLegal) {
18314 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18315 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18316 Ld->getPointerInfo(), Ld->isVolatile(),
18317 Ld->isNonTemporal(), Ld->isInvariant(),
18318 Ld->getAlignment());
18319 SDValue NewChain = NewLd.getValue(1);
18320 if (TokenFactorIndex != -1) {
18321 Ops.push_back(NewChain);
18322 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18325 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18326 St->getPointerInfo(),
18327 St->isVolatile(), St->isNonTemporal(),
18328 St->getAlignment());
18331 // Otherwise, lower to two pairs of 32-bit loads / stores.
18332 SDValue LoAddr = Ld->getBasePtr();
18333 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18334 DAG.getConstant(4, MVT::i32));
18336 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18337 Ld->getPointerInfo(),
18338 Ld->isVolatile(), Ld->isNonTemporal(),
18339 Ld->isInvariant(), Ld->getAlignment());
18340 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18341 Ld->getPointerInfo().getWithOffset(4),
18342 Ld->isVolatile(), Ld->isNonTemporal(),
18344 MinAlign(Ld->getAlignment(), 4));
18346 SDValue NewChain = LoLd.getValue(1);
18347 if (TokenFactorIndex != -1) {
18348 Ops.push_back(LoLd);
18349 Ops.push_back(HiLd);
18350 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18354 LoAddr = St->getBasePtr();
18355 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18356 DAG.getConstant(4, MVT::i32));
18358 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18359 St->getPointerInfo(),
18360 St->isVolatile(), St->isNonTemporal(),
18361 St->getAlignment());
18362 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18363 St->getPointerInfo().getWithOffset(4),
18365 St->isNonTemporal(),
18366 MinAlign(St->getAlignment(), 4));
18367 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18372 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18373 /// and return the operands for the horizontal operation in LHS and RHS. A
18374 /// horizontal operation performs the binary operation on successive elements
18375 /// of its first operand, then on successive elements of its second operand,
18376 /// returning the resulting values in a vector. For example, if
18377 /// A = < float a0, float a1, float a2, float a3 >
18379 /// B = < float b0, float b1, float b2, float b3 >
18380 /// then the result of doing a horizontal operation on A and B is
18381 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18382 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18383 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18384 /// set to A, RHS to B, and the routine returns 'true'.
18385 /// Note that the binary operation should have the property that if one of the
18386 /// operands is UNDEF then the result is UNDEF.
18387 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18388 // Look for the following pattern: if
18389 // A = < float a0, float a1, float a2, float a3 >
18390 // B = < float b0, float b1, float b2, float b3 >
18392 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18393 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18394 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18395 // which is A horizontal-op B.
18397 // At least one of the operands should be a vector shuffle.
18398 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18399 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18402 MVT VT = LHS.getSimpleValueType();
18404 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18405 "Unsupported vector type for horizontal add/sub");
18407 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18408 // operate independently on 128-bit lanes.
18409 unsigned NumElts = VT.getVectorNumElements();
18410 unsigned NumLanes = VT.getSizeInBits()/128;
18411 unsigned NumLaneElts = NumElts / NumLanes;
18412 assert((NumLaneElts % 2 == 0) &&
18413 "Vector type should have an even number of elements in each lane");
18414 unsigned HalfLaneElts = NumLaneElts/2;
18416 // View LHS in the form
18417 // LHS = VECTOR_SHUFFLE A, B, LMask
18418 // If LHS is not a shuffle then pretend it is the shuffle
18419 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18420 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18423 SmallVector<int, 16> LMask(NumElts);
18424 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18425 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18426 A = LHS.getOperand(0);
18427 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18428 B = LHS.getOperand(1);
18429 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18430 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18432 if (LHS.getOpcode() != ISD::UNDEF)
18434 for (unsigned i = 0; i != NumElts; ++i)
18438 // Likewise, view RHS in the form
18439 // RHS = VECTOR_SHUFFLE C, D, RMask
18441 SmallVector<int, 16> RMask(NumElts);
18442 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18443 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18444 C = RHS.getOperand(0);
18445 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18446 D = RHS.getOperand(1);
18447 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18448 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18450 if (RHS.getOpcode() != ISD::UNDEF)
18452 for (unsigned i = 0; i != NumElts; ++i)
18456 // Check that the shuffles are both shuffling the same vectors.
18457 if (!(A == C && B == D) && !(A == D && B == C))
18460 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18461 if (!A.getNode() && !B.getNode())
18464 // If A and B occur in reverse order in RHS, then "swap" them (which means
18465 // rewriting the mask).
18467 CommuteVectorShuffleMask(RMask, NumElts);
18469 // At this point LHS and RHS are equivalent to
18470 // LHS = VECTOR_SHUFFLE A, B, LMask
18471 // RHS = VECTOR_SHUFFLE A, B, RMask
18472 // Check that the masks correspond to performing a horizontal operation.
18473 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18474 for (unsigned i = 0; i != NumLaneElts; ++i) {
18475 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18477 // Ignore any UNDEF components.
18478 if (LIdx < 0 || RIdx < 0 ||
18479 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18480 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18483 // Check that successive elements are being operated on. If not, this is
18484 // not a horizontal operation.
18485 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18486 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18487 if (!(LIdx == Index && RIdx == Index + 1) &&
18488 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18493 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18494 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18498 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18499 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18500 const X86Subtarget *Subtarget) {
18501 EVT VT = N->getValueType(0);
18502 SDValue LHS = N->getOperand(0);
18503 SDValue RHS = N->getOperand(1);
18505 // Try to synthesize horizontal adds from adds of shuffles.
18506 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18507 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18508 isHorizontalBinOp(LHS, RHS, true))
18509 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18513 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18514 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18515 const X86Subtarget *Subtarget) {
18516 EVT VT = N->getValueType(0);
18517 SDValue LHS = N->getOperand(0);
18518 SDValue RHS = N->getOperand(1);
18520 // Try to synthesize horizontal subs from subs of shuffles.
18521 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18522 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18523 isHorizontalBinOp(LHS, RHS, false))
18524 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18528 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18529 /// X86ISD::FXOR nodes.
18530 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18531 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18532 // F[X]OR(0.0, x) -> x
18533 // F[X]OR(x, 0.0) -> x
18534 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18535 if (C->getValueAPF().isPosZero())
18536 return N->getOperand(1);
18537 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18538 if (C->getValueAPF().isPosZero())
18539 return N->getOperand(0);
18543 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18544 /// X86ISD::FMAX nodes.
18545 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18546 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18548 // Only perform optimizations if UnsafeMath is used.
18549 if (!DAG.getTarget().Options.UnsafeFPMath)
18552 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18553 // into FMINC and FMAXC, which are Commutative operations.
18554 unsigned NewOp = 0;
18555 switch (N->getOpcode()) {
18556 default: llvm_unreachable("unknown opcode");
18557 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18558 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18561 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18562 N->getOperand(0), N->getOperand(1));
18565 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18566 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18567 // FAND(0.0, x) -> 0.0
18568 // FAND(x, 0.0) -> 0.0
18569 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18570 if (C->getValueAPF().isPosZero())
18571 return N->getOperand(0);
18572 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18573 if (C->getValueAPF().isPosZero())
18574 return N->getOperand(1);
18578 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18579 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18580 // FANDN(x, 0.0) -> 0.0
18581 // FANDN(0.0, x) -> x
18582 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18583 if (C->getValueAPF().isPosZero())
18584 return N->getOperand(1);
18585 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18586 if (C->getValueAPF().isPosZero())
18587 return N->getOperand(1);
18591 static SDValue PerformBTCombine(SDNode *N,
18593 TargetLowering::DAGCombinerInfo &DCI) {
18594 // BT ignores high bits in the bit index operand.
18595 SDValue Op1 = N->getOperand(1);
18596 if (Op1.hasOneUse()) {
18597 unsigned BitWidth = Op1.getValueSizeInBits();
18598 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18599 APInt KnownZero, KnownOne;
18600 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18601 !DCI.isBeforeLegalizeOps());
18602 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18603 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18604 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18605 DCI.CommitTargetLoweringOpt(TLO);
18610 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18611 SDValue Op = N->getOperand(0);
18612 if (Op.getOpcode() == ISD::BITCAST)
18613 Op = Op.getOperand(0);
18614 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18615 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18616 VT.getVectorElementType().getSizeInBits() ==
18617 OpVT.getVectorElementType().getSizeInBits()) {
18618 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18623 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18624 const X86Subtarget *Subtarget) {
18625 EVT VT = N->getValueType(0);
18626 if (!VT.isVector())
18629 SDValue N0 = N->getOperand(0);
18630 SDValue N1 = N->getOperand(1);
18631 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18634 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18635 // both SSE and AVX2 since there is no sign-extended shift right
18636 // operation on a vector with 64-bit elements.
18637 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18638 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18639 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18640 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18641 SDValue N00 = N0.getOperand(0);
18643 // EXTLOAD has a better solution on AVX2,
18644 // it may be replaced with X86ISD::VSEXT node.
18645 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18646 if (!ISD::isNormalLoad(N00.getNode()))
18649 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18650 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18652 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18658 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18659 TargetLowering::DAGCombinerInfo &DCI,
18660 const X86Subtarget *Subtarget) {
18661 if (!DCI.isBeforeLegalizeOps())
18664 if (!Subtarget->hasFp256())
18667 EVT VT = N->getValueType(0);
18668 if (VT.isVector() && VT.getSizeInBits() == 256) {
18669 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18677 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18678 const X86Subtarget* Subtarget) {
18680 EVT VT = N->getValueType(0);
18682 // Let legalize expand this if it isn't a legal type yet.
18683 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18686 EVT ScalarVT = VT.getScalarType();
18687 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18688 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18691 SDValue A = N->getOperand(0);
18692 SDValue B = N->getOperand(1);
18693 SDValue C = N->getOperand(2);
18695 bool NegA = (A.getOpcode() == ISD::FNEG);
18696 bool NegB = (B.getOpcode() == ISD::FNEG);
18697 bool NegC = (C.getOpcode() == ISD::FNEG);
18699 // Negative multiplication when NegA xor NegB
18700 bool NegMul = (NegA != NegB);
18702 A = A.getOperand(0);
18704 B = B.getOperand(0);
18706 C = C.getOperand(0);
18710 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18712 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18714 return DAG.getNode(Opcode, dl, VT, A, B, C);
18717 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18718 TargetLowering::DAGCombinerInfo &DCI,
18719 const X86Subtarget *Subtarget) {
18720 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18721 // (and (i32 x86isd::setcc_carry), 1)
18722 // This eliminates the zext. This transformation is necessary because
18723 // ISD::SETCC is always legalized to i8.
18725 SDValue N0 = N->getOperand(0);
18726 EVT VT = N->getValueType(0);
18728 if (N0.getOpcode() == ISD::AND &&
18730 N0.getOperand(0).hasOneUse()) {
18731 SDValue N00 = N0.getOperand(0);
18732 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18733 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18734 if (!C || C->getZExtValue() != 1)
18736 return DAG.getNode(ISD::AND, dl, VT,
18737 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18738 N00.getOperand(0), N00.getOperand(1)),
18739 DAG.getConstant(1, VT));
18743 if (VT.is256BitVector()) {
18744 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18752 // Optimize x == -y --> x+y == 0
18753 // x != -y --> x+y != 0
18754 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18755 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18756 SDValue LHS = N->getOperand(0);
18757 SDValue RHS = N->getOperand(1);
18759 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18760 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18761 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18762 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18763 LHS.getValueType(), RHS, LHS.getOperand(1));
18764 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18765 addV, DAG.getConstant(0, addV.getValueType()), CC);
18767 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18768 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18769 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18770 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18771 RHS.getValueType(), LHS, RHS.getOperand(1));
18772 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18773 addV, DAG.getConstant(0, addV.getValueType()), CC);
18778 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18779 // as "sbb reg,reg", since it can be extended without zext and produces
18780 // an all-ones bit which is more useful than 0/1 in some cases.
18781 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18782 return DAG.getNode(ISD::AND, DL, MVT::i8,
18783 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18784 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18785 DAG.getConstant(1, MVT::i8));
18788 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18789 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18790 TargetLowering::DAGCombinerInfo &DCI,
18791 const X86Subtarget *Subtarget) {
18793 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18794 SDValue EFLAGS = N->getOperand(1);
18796 if (CC == X86::COND_A) {
18797 // Try to convert COND_A into COND_B in an attempt to facilitate
18798 // materializing "setb reg".
18800 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18801 // cannot take an immediate as its first operand.
18803 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18804 EFLAGS.getValueType().isInteger() &&
18805 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18806 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18807 EFLAGS.getNode()->getVTList(),
18808 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18809 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18810 return MaterializeSETB(DL, NewEFLAGS, DAG);
18814 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18815 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18817 if (CC == X86::COND_B)
18818 return MaterializeSETB(DL, EFLAGS, DAG);
18822 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18823 if (Flags.getNode()) {
18824 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18825 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18831 // Optimize branch condition evaluation.
18833 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18834 TargetLowering::DAGCombinerInfo &DCI,
18835 const X86Subtarget *Subtarget) {
18837 SDValue Chain = N->getOperand(0);
18838 SDValue Dest = N->getOperand(1);
18839 SDValue EFLAGS = N->getOperand(3);
18840 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18844 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18845 if (Flags.getNode()) {
18846 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18847 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18854 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18855 const X86TargetLowering *XTLI) {
18856 SDValue Op0 = N->getOperand(0);
18857 EVT InVT = Op0->getValueType(0);
18859 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18860 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18862 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18863 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18864 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18867 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18868 // a 32-bit target where SSE doesn't support i64->FP operations.
18869 if (Op0.getOpcode() == ISD::LOAD) {
18870 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18871 EVT VT = Ld->getValueType(0);
18872 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18873 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18874 !XTLI->getSubtarget()->is64Bit() &&
18876 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18877 Ld->getChain(), Op0, DAG);
18878 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18885 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18886 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18887 X86TargetLowering::DAGCombinerInfo &DCI) {
18888 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18889 // the result is either zero or one (depending on the input carry bit).
18890 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18891 if (X86::isZeroNode(N->getOperand(0)) &&
18892 X86::isZeroNode(N->getOperand(1)) &&
18893 // We don't have a good way to replace an EFLAGS use, so only do this when
18895 SDValue(N, 1).use_empty()) {
18897 EVT VT = N->getValueType(0);
18898 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18899 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18900 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18901 DAG.getConstant(X86::COND_B,MVT::i8),
18903 DAG.getConstant(1, VT));
18904 return DCI.CombineTo(N, Res1, CarryOut);
18910 // fold (add Y, (sete X, 0)) -> adc 0, Y
18911 // (add Y, (setne X, 0)) -> sbb -1, Y
18912 // (sub (sete X, 0), Y) -> sbb 0, Y
18913 // (sub (setne X, 0), Y) -> adc -1, Y
18914 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18917 // Look through ZExts.
18918 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18919 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18922 SDValue SetCC = Ext.getOperand(0);
18923 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18926 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18927 if (CC != X86::COND_E && CC != X86::COND_NE)
18930 SDValue Cmp = SetCC.getOperand(1);
18931 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18932 !X86::isZeroNode(Cmp.getOperand(1)) ||
18933 !Cmp.getOperand(0).getValueType().isInteger())
18936 SDValue CmpOp0 = Cmp.getOperand(0);
18937 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18938 DAG.getConstant(1, CmpOp0.getValueType()));
18940 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18941 if (CC == X86::COND_NE)
18942 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18943 DL, OtherVal.getValueType(), OtherVal,
18944 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18945 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18946 DL, OtherVal.getValueType(), OtherVal,
18947 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18950 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18951 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18952 const X86Subtarget *Subtarget) {
18953 EVT VT = N->getValueType(0);
18954 SDValue Op0 = N->getOperand(0);
18955 SDValue Op1 = N->getOperand(1);
18957 // Try to synthesize horizontal adds from adds of shuffles.
18958 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18959 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18960 isHorizontalBinOp(Op0, Op1, true))
18961 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18963 return OptimizeConditionalInDecrement(N, DAG);
18966 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18967 const X86Subtarget *Subtarget) {
18968 SDValue Op0 = N->getOperand(0);
18969 SDValue Op1 = N->getOperand(1);
18971 // X86 can't encode an immediate LHS of a sub. See if we can push the
18972 // negation into a preceding instruction.
18973 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18974 // If the RHS of the sub is a XOR with one use and a constant, invert the
18975 // immediate. Then add one to the LHS of the sub so we can turn
18976 // X-Y -> X+~Y+1, saving one register.
18977 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18978 isa<ConstantSDNode>(Op1.getOperand(1))) {
18979 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18980 EVT VT = Op0.getValueType();
18981 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18983 DAG.getConstant(~XorC, VT));
18984 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18985 DAG.getConstant(C->getAPIntValue()+1, VT));
18989 // Try to synthesize horizontal adds from adds of shuffles.
18990 EVT VT = N->getValueType(0);
18991 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18992 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18993 isHorizontalBinOp(Op0, Op1, true))
18994 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
18996 return OptimizeConditionalInDecrement(N, DAG);
18999 /// performVZEXTCombine - Performs build vector combines
19000 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19001 TargetLowering::DAGCombinerInfo &DCI,
19002 const X86Subtarget *Subtarget) {
19003 // (vzext (bitcast (vzext (x)) -> (vzext x)
19004 SDValue In = N->getOperand(0);
19005 while (In.getOpcode() == ISD::BITCAST)
19006 In = In.getOperand(0);
19008 if (In.getOpcode() != X86ISD::VZEXT)
19011 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19015 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19016 DAGCombinerInfo &DCI) const {
19017 SelectionDAG &DAG = DCI.DAG;
19018 switch (N->getOpcode()) {
19020 case ISD::EXTRACT_VECTOR_ELT:
19021 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19023 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19024 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19025 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19026 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19027 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19028 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19031 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19032 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19033 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19034 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19035 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19036 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19037 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19038 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19039 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19041 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19043 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19044 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19045 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19046 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19047 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19048 case ISD::ANY_EXTEND:
19049 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19050 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19051 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19052 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19053 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19054 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19055 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19056 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19057 case X86ISD::SHUFP: // Handle all target specific shuffles
19058 case X86ISD::PALIGNR:
19059 case X86ISD::UNPCKH:
19060 case X86ISD::UNPCKL:
19061 case X86ISD::MOVHLPS:
19062 case X86ISD::MOVLHPS:
19063 case X86ISD::PSHUFD:
19064 case X86ISD::PSHUFHW:
19065 case X86ISD::PSHUFLW:
19066 case X86ISD::MOVSS:
19067 case X86ISD::MOVSD:
19068 case X86ISD::VPERMILP:
19069 case X86ISD::VPERM2X128:
19070 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19071 case ISD::CONCAT_VECTORS: return PerformConcatCombine(N, DAG, DCI, Subtarget);
19072 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19078 /// isTypeDesirableForOp - Return true if the target has native support for
19079 /// the specified value type and it is 'desirable' to use the type for the
19080 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19081 /// instruction encodings are longer and some i16 instructions are slow.
19082 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19083 if (!isTypeLegal(VT))
19085 if (VT != MVT::i16)
19092 case ISD::SIGN_EXTEND:
19093 case ISD::ZERO_EXTEND:
19094 case ISD::ANY_EXTEND:
19107 /// IsDesirableToPromoteOp - This method query the target whether it is
19108 /// beneficial for dag combiner to promote the specified node. If true, it
19109 /// should return the desired promotion type by reference.
19110 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19111 EVT VT = Op.getValueType();
19112 if (VT != MVT::i16)
19115 bool Promote = false;
19116 bool Commute = false;
19117 switch (Op.getOpcode()) {
19120 LoadSDNode *LD = cast<LoadSDNode>(Op);
19121 // If the non-extending load has a single use and it's not live out, then it
19122 // might be folded.
19123 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19124 Op.hasOneUse()*/) {
19125 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19126 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19127 // The only case where we'd want to promote LOAD (rather then it being
19128 // promoted as an operand is when it's only use is liveout.
19129 if (UI->getOpcode() != ISD::CopyToReg)
19136 case ISD::SIGN_EXTEND:
19137 case ISD::ZERO_EXTEND:
19138 case ISD::ANY_EXTEND:
19143 SDValue N0 = Op.getOperand(0);
19144 // Look out for (store (shl (load), x)).
19145 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19158 SDValue N0 = Op.getOperand(0);
19159 SDValue N1 = Op.getOperand(1);
19160 if (!Commute && MayFoldLoad(N1))
19162 // Avoid disabling potential load folding opportunities.
19163 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19165 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19175 //===----------------------------------------------------------------------===//
19176 // X86 Inline Assembly Support
19177 //===----------------------------------------------------------------------===//
19180 // Helper to match a string separated by whitespace.
19181 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19182 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19184 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19185 StringRef piece(*args[i]);
19186 if (!s.startswith(piece)) // Check if the piece matches.
19189 s = s.substr(piece.size());
19190 StringRef::size_type pos = s.find_first_not_of(" \t");
19191 if (pos == 0) // We matched a prefix.
19199 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19202 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19203 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19205 std::string AsmStr = IA->getAsmString();
19207 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19208 if (!Ty || Ty->getBitWidth() % 16 != 0)
19211 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19212 SmallVector<StringRef, 4> AsmPieces;
19213 SplitString(AsmStr, AsmPieces, ";\n");
19215 switch (AsmPieces.size()) {
19216 default: return false;
19218 // FIXME: this should verify that we are targeting a 486 or better. If not,
19219 // we will turn this bswap into something that will be lowered to logical
19220 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19221 // lower so don't worry about this.
19223 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19224 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19225 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19226 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19227 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19228 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19229 // No need to check constraints, nothing other than the equivalent of
19230 // "=r,0" would be valid here.
19231 return IntrinsicLowering::LowerToByteSwap(CI);
19234 // rorw $$8, ${0:w} --> llvm.bswap.i16
19235 if (CI->getType()->isIntegerTy(16) &&
19236 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19237 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19238 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19240 const std::string &ConstraintsStr = IA->getConstraintString();
19241 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19242 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19243 if (AsmPieces.size() == 4 &&
19244 AsmPieces[0] == "~{cc}" &&
19245 AsmPieces[1] == "~{dirflag}" &&
19246 AsmPieces[2] == "~{flags}" &&
19247 AsmPieces[3] == "~{fpsr}")
19248 return IntrinsicLowering::LowerToByteSwap(CI);
19252 if (CI->getType()->isIntegerTy(32) &&
19253 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19254 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19255 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19256 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19258 const std::string &ConstraintsStr = IA->getConstraintString();
19259 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19260 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19261 if (AsmPieces.size() == 4 &&
19262 AsmPieces[0] == "~{cc}" &&
19263 AsmPieces[1] == "~{dirflag}" &&
19264 AsmPieces[2] == "~{flags}" &&
19265 AsmPieces[3] == "~{fpsr}")
19266 return IntrinsicLowering::LowerToByteSwap(CI);
19269 if (CI->getType()->isIntegerTy(64)) {
19270 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19271 if (Constraints.size() >= 2 &&
19272 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19273 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19274 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19275 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19276 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19277 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19278 return IntrinsicLowering::LowerToByteSwap(CI);
19286 /// getConstraintType - Given a constraint letter, return the type of
19287 /// constraint it is for this target.
19288 X86TargetLowering::ConstraintType
19289 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19290 if (Constraint.size() == 1) {
19291 switch (Constraint[0]) {
19302 return C_RegisterClass;
19326 return TargetLowering::getConstraintType(Constraint);
19329 /// Examine constraint type and operand type and determine a weight value.
19330 /// This object must already have been set up with the operand type
19331 /// and the current alternative constraint selected.
19332 TargetLowering::ConstraintWeight
19333 X86TargetLowering::getSingleConstraintMatchWeight(
19334 AsmOperandInfo &info, const char *constraint) const {
19335 ConstraintWeight weight = CW_Invalid;
19336 Value *CallOperandVal = info.CallOperandVal;
19337 // If we don't have a value, we can't do a match,
19338 // but allow it at the lowest weight.
19339 if (CallOperandVal == NULL)
19341 Type *type = CallOperandVal->getType();
19342 // Look at the constraint type.
19343 switch (*constraint) {
19345 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19356 if (CallOperandVal->getType()->isIntegerTy())
19357 weight = CW_SpecificReg;
19362 if (type->isFloatingPointTy())
19363 weight = CW_SpecificReg;
19366 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19367 weight = CW_SpecificReg;
19371 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19372 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19373 weight = CW_Register;
19376 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19377 if (C->getZExtValue() <= 31)
19378 weight = CW_Constant;
19382 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19383 if (C->getZExtValue() <= 63)
19384 weight = CW_Constant;
19388 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19389 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19390 weight = CW_Constant;
19394 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19395 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19396 weight = CW_Constant;
19400 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19401 if (C->getZExtValue() <= 3)
19402 weight = CW_Constant;
19406 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19407 if (C->getZExtValue() <= 0xff)
19408 weight = CW_Constant;
19413 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19414 weight = CW_Constant;
19418 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19419 if ((C->getSExtValue() >= -0x80000000LL) &&
19420 (C->getSExtValue() <= 0x7fffffffLL))
19421 weight = CW_Constant;
19425 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19426 if (C->getZExtValue() <= 0xffffffff)
19427 weight = CW_Constant;
19434 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19435 /// with another that has more specific requirements based on the type of the
19436 /// corresponding operand.
19437 const char *X86TargetLowering::
19438 LowerXConstraint(EVT ConstraintVT) const {
19439 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19440 // 'f' like normal targets.
19441 if (ConstraintVT.isFloatingPoint()) {
19442 if (Subtarget->hasSSE2())
19444 if (Subtarget->hasSSE1())
19448 return TargetLowering::LowerXConstraint(ConstraintVT);
19451 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19452 /// vector. If it is invalid, don't add anything to Ops.
19453 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19454 std::string &Constraint,
19455 std::vector<SDValue>&Ops,
19456 SelectionDAG &DAG) const {
19457 SDValue Result(0, 0);
19459 // Only support length 1 constraints for now.
19460 if (Constraint.length() > 1) return;
19462 char ConstraintLetter = Constraint[0];
19463 switch (ConstraintLetter) {
19466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19467 if (C->getZExtValue() <= 31) {
19468 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19474 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19475 if (C->getZExtValue() <= 63) {
19476 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19483 if (isInt<8>(C->getSExtValue())) {
19484 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19491 if (C->getZExtValue() <= 255) {
19492 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19498 // 32-bit signed value
19499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19500 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19501 C->getSExtValue())) {
19502 // Widen to 64 bits here to get it sign extended.
19503 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19506 // FIXME gcc accepts some relocatable values here too, but only in certain
19507 // memory models; it's complicated.
19512 // 32-bit unsigned value
19513 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19514 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19515 C->getZExtValue())) {
19516 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19520 // FIXME gcc accepts some relocatable values here too, but only in certain
19521 // memory models; it's complicated.
19525 // Literal immediates are always ok.
19526 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19527 // Widen to 64 bits here to get it sign extended.
19528 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19532 // In any sort of PIC mode addresses need to be computed at runtime by
19533 // adding in a register or some sort of table lookup. These can't
19534 // be used as immediates.
19535 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19538 // If we are in non-pic codegen mode, we allow the address of a global (with
19539 // an optional displacement) to be used with 'i'.
19540 GlobalAddressSDNode *GA = 0;
19541 int64_t Offset = 0;
19543 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19545 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19546 Offset += GA->getOffset();
19548 } else if (Op.getOpcode() == ISD::ADD) {
19549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19550 Offset += C->getZExtValue();
19551 Op = Op.getOperand(0);
19554 } else if (Op.getOpcode() == ISD::SUB) {
19555 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19556 Offset += -C->getZExtValue();
19557 Op = Op.getOperand(0);
19562 // Otherwise, this isn't something we can handle, reject it.
19566 const GlobalValue *GV = GA->getGlobal();
19567 // If we require an extra load to get this address, as in PIC mode, we
19568 // can't accept it.
19569 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19570 getTargetMachine())))
19573 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19574 GA->getValueType(0), Offset);
19579 if (Result.getNode()) {
19580 Ops.push_back(Result);
19583 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19586 std::pair<unsigned, const TargetRegisterClass*>
19587 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19589 // First, see if this is a constraint that directly corresponds to an LLVM
19591 if (Constraint.size() == 1) {
19592 // GCC Constraint Letters
19593 switch (Constraint[0]) {
19595 // TODO: Slight differences here in allocation order and leaving
19596 // RIP in the class. Do they matter any more here than they do
19597 // in the normal allocation?
19598 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19599 if (Subtarget->is64Bit()) {
19600 if (VT == MVT::i32 || VT == MVT::f32)
19601 return std::make_pair(0U, &X86::GR32RegClass);
19602 if (VT == MVT::i16)
19603 return std::make_pair(0U, &X86::GR16RegClass);
19604 if (VT == MVT::i8 || VT == MVT::i1)
19605 return std::make_pair(0U, &X86::GR8RegClass);
19606 if (VT == MVT::i64 || VT == MVT::f64)
19607 return std::make_pair(0U, &X86::GR64RegClass);
19610 // 32-bit fallthrough
19611 case 'Q': // Q_REGS
19612 if (VT == MVT::i32 || VT == MVT::f32)
19613 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19614 if (VT == MVT::i16)
19615 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19616 if (VT == MVT::i8 || VT == MVT::i1)
19617 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19618 if (VT == MVT::i64)
19619 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19621 case 'r': // GENERAL_REGS
19622 case 'l': // INDEX_REGS
19623 if (VT == MVT::i8 || VT == MVT::i1)
19624 return std::make_pair(0U, &X86::GR8RegClass);
19625 if (VT == MVT::i16)
19626 return std::make_pair(0U, &X86::GR16RegClass);
19627 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19628 return std::make_pair(0U, &X86::GR32RegClass);
19629 return std::make_pair(0U, &X86::GR64RegClass);
19630 case 'R': // LEGACY_REGS
19631 if (VT == MVT::i8 || VT == MVT::i1)
19632 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19633 if (VT == MVT::i16)
19634 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19635 if (VT == MVT::i32 || !Subtarget->is64Bit())
19636 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19637 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19638 case 'f': // FP Stack registers.
19639 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19640 // value to the correct fpstack register class.
19641 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19642 return std::make_pair(0U, &X86::RFP32RegClass);
19643 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19644 return std::make_pair(0U, &X86::RFP64RegClass);
19645 return std::make_pair(0U, &X86::RFP80RegClass);
19646 case 'y': // MMX_REGS if MMX allowed.
19647 if (!Subtarget->hasMMX()) break;
19648 return std::make_pair(0U, &X86::VR64RegClass);
19649 case 'Y': // SSE_REGS if SSE2 allowed
19650 if (!Subtarget->hasSSE2()) break;
19652 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19653 if (!Subtarget->hasSSE1()) break;
19655 switch (VT.SimpleTy) {
19657 // Scalar SSE types.
19660 return std::make_pair(0U, &X86::FR32RegClass);
19663 return std::make_pair(0U, &X86::FR64RegClass);
19671 return std::make_pair(0U, &X86::VR128RegClass);
19679 return std::make_pair(0U, &X86::VR256RegClass);
19684 return std::make_pair(0U, &X86::VR512RegClass);
19690 // Use the default implementation in TargetLowering to convert the register
19691 // constraint into a member of a register class.
19692 std::pair<unsigned, const TargetRegisterClass*> Res;
19693 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19695 // Not found as a standard register?
19696 if (Res.second == 0) {
19697 // Map st(0) -> st(7) -> ST0
19698 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19699 tolower(Constraint[1]) == 's' &&
19700 tolower(Constraint[2]) == 't' &&
19701 Constraint[3] == '(' &&
19702 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19703 Constraint[5] == ')' &&
19704 Constraint[6] == '}') {
19706 Res.first = X86::ST0+Constraint[4]-'0';
19707 Res.second = &X86::RFP80RegClass;
19711 // GCC allows "st(0)" to be called just plain "st".
19712 if (StringRef("{st}").equals_lower(Constraint)) {
19713 Res.first = X86::ST0;
19714 Res.second = &X86::RFP80RegClass;
19719 if (StringRef("{flags}").equals_lower(Constraint)) {
19720 Res.first = X86::EFLAGS;
19721 Res.second = &X86::CCRRegClass;
19725 // 'A' means EAX + EDX.
19726 if (Constraint == "A") {
19727 Res.first = X86::EAX;
19728 Res.second = &X86::GR32_ADRegClass;
19734 // Otherwise, check to see if this is a register class of the wrong value
19735 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19736 // turn into {ax},{dx}.
19737 if (Res.second->hasType(VT))
19738 return Res; // Correct type already, nothing to do.
19740 // All of the single-register GCC register classes map their values onto
19741 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19742 // really want an 8-bit or 32-bit register, map to the appropriate register
19743 // class and return the appropriate register.
19744 if (Res.second == &X86::GR16RegClass) {
19745 if (VT == MVT::i8 || VT == MVT::i1) {
19746 unsigned DestReg = 0;
19747 switch (Res.first) {
19749 case X86::AX: DestReg = X86::AL; break;
19750 case X86::DX: DestReg = X86::DL; break;
19751 case X86::CX: DestReg = X86::CL; break;
19752 case X86::BX: DestReg = X86::BL; break;
19755 Res.first = DestReg;
19756 Res.second = &X86::GR8RegClass;
19758 } else if (VT == MVT::i32 || VT == MVT::f32) {
19759 unsigned DestReg = 0;
19760 switch (Res.first) {
19762 case X86::AX: DestReg = X86::EAX; break;
19763 case X86::DX: DestReg = X86::EDX; break;
19764 case X86::CX: DestReg = X86::ECX; break;
19765 case X86::BX: DestReg = X86::EBX; break;
19766 case X86::SI: DestReg = X86::ESI; break;
19767 case X86::DI: DestReg = X86::EDI; break;
19768 case X86::BP: DestReg = X86::EBP; break;
19769 case X86::SP: DestReg = X86::ESP; break;
19772 Res.first = DestReg;
19773 Res.second = &X86::GR32RegClass;
19775 } else if (VT == MVT::i64 || VT == MVT::f64) {
19776 unsigned DestReg = 0;
19777 switch (Res.first) {
19779 case X86::AX: DestReg = X86::RAX; break;
19780 case X86::DX: DestReg = X86::RDX; break;
19781 case X86::CX: DestReg = X86::RCX; break;
19782 case X86::BX: DestReg = X86::RBX; break;
19783 case X86::SI: DestReg = X86::RSI; break;
19784 case X86::DI: DestReg = X86::RDI; break;
19785 case X86::BP: DestReg = X86::RBP; break;
19786 case X86::SP: DestReg = X86::RSP; break;
19789 Res.first = DestReg;
19790 Res.second = &X86::GR64RegClass;
19793 } else if (Res.second == &X86::FR32RegClass ||
19794 Res.second == &X86::FR64RegClass ||
19795 Res.second == &X86::VR128RegClass ||
19796 Res.second == &X86::VR256RegClass ||
19797 Res.second == &X86::FR32XRegClass ||
19798 Res.second == &X86::FR64XRegClass ||
19799 Res.second == &X86::VR128XRegClass ||
19800 Res.second == &X86::VR256XRegClass ||
19801 Res.second == &X86::VR512RegClass) {
19802 // Handle references to XMM physical registers that got mapped into the
19803 // wrong class. This can happen with constraints like {xmm0} where the
19804 // target independent register mapper will just pick the first match it can
19805 // find, ignoring the required type.
19807 if (VT == MVT::f32 || VT == MVT::i32)
19808 Res.second = &X86::FR32RegClass;
19809 else if (VT == MVT::f64 || VT == MVT::i64)
19810 Res.second = &X86::FR64RegClass;
19811 else if (X86::VR128RegClass.hasType(VT))
19812 Res.second = &X86::VR128RegClass;
19813 else if (X86::VR256RegClass.hasType(VT))
19814 Res.second = &X86::VR256RegClass;
19815 else if (X86::VR512RegClass.hasType(VT))
19816 Res.second = &X86::VR512RegClass;