1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Constants.h"
35 #include "llvm/DerivedTypes.h"
36 #include "llvm/Function.h"
37 #include "llvm/GlobalAlias.h"
38 #include "llvm/GlobalVariable.h"
39 #include "llvm/Instructions.h"
40 #include "llvm/Intrinsics.h"
41 #include "llvm/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
162 RegInfo = TM.getRegisterInfo();
163 TD = getDataLayout();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
184 // Bypass i32 with i8 on Atom when compiling with O2
185 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default)
186 addBypassSlowDiv(32, 8);
188 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
189 // Setup Windows compiler runtime calls.
190 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
191 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
192 setLibcallName(RTLIB::SREM_I64, "_allrem");
193 setLibcallName(RTLIB::UREM_I64, "_aullrem");
194 setLibcallName(RTLIB::MUL_I64, "_allmul");
195 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
197 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
198 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
199 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
201 // The _ftol2 runtime function has an unusual calling conv, which
202 // is modeled by a special pseudo-instruction.
203 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
204 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
205 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
206 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
209 if (Subtarget->isTargetDarwin()) {
210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
211 setUseUnderscoreSetJmp(false);
212 setUseUnderscoreLongJmp(false);
213 } else if (Subtarget->isTargetMingw()) {
214 // MS runtime is weird: it exports _setjmp, but longjmp!
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(false);
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(true);
222 // Set up the register classes.
223 addRegisterClass(MVT::i8, &X86::GR8RegClass);
224 addRegisterClass(MVT::i16, &X86::GR16RegClass);
225 addRegisterClass(MVT::i32, &X86::GR32RegClass);
226 if (Subtarget->is64Bit())
227 addRegisterClass(MVT::i64, &X86::GR64RegClass);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 // We don't accept any truncstore of integer registers.
232 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
233 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
235 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
239 // SETOEQ and SETUNE require checking two conditions.
240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 } else if (!TM.Options.UseSoftFloat) {
257 // We have an algorithm for SSE2->double, and we turn this into a
258 // 64-bit FILD followed by conditional FADD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
260 // We have an algorithm for SSE2, and we turn this into a 64-bit
261 // FILD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
270 if (!TM.Options.UseSoftFloat) {
271 // SSE has no i16 to fp conversion, only i32
272 if (X86ScalarSSEf32) {
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 // f32 and f64 cases are Legal, f80 case is not
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
286 // are Legal, f80 is custom lowered.
287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
295 if (X86ScalarSSEf32) {
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
297 // f32 and f64 cases are Legal, f80 case is not
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 // Handle FP_TO_UINT by promoting the destination to a larger signed
306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
310 if (Subtarget->is64Bit()) {
311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
313 } else if (!TM.Options.UseSoftFloat) {
314 // Since AVX is a superset of SSE3, only check for SSE here.
315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 if (isTargetFTOL()) {
327 // Use the _ftol2 runtime function, which has a pseudo-instruction
328 // to handle its weird calling convention.
329 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
332 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
333 if (!X86ScalarSSEf64) {
334 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
335 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
338 // Without SSE, i64->f64 goes through memory.
339 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
343 // Scalar integer divide and remainder are lowered to use operations that
344 // produce two results, to match the available instructions. This exposes
345 // the two-result form to trivial CSE, which is able to combine x/y and x%y
346 // into a single instruction.
348 // Scalar integer multiply-high is also lowered to use two-result
349 // operations, to match the available instructions. However, plain multiply
350 // (low) operations are left as Legal, as there are single-result
351 // instructions for this in x86. Using the two-result multiply instructions
352 // when both high and low results are needed must be arranged by dagcombine.
353 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
355 setOperationAction(ISD::MULHS, VT, Expand);
356 setOperationAction(ISD::MULHU, VT, Expand);
357 setOperationAction(ISD::SDIV, VT, Expand);
358 setOperationAction(ISD::UDIV, VT, Expand);
359 setOperationAction(ISD::SREM, VT, Expand);
360 setOperationAction(ISD::UREM, VT, Expand);
362 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
363 setOperationAction(ISD::ADDC, VT, Custom);
364 setOperationAction(ISD::ADDE, VT, Custom);
365 setOperationAction(ISD::SUBC, VT, Custom);
366 setOperationAction(ISD::SUBE, VT, Custom);
369 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
370 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
371 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
372 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
373 if (Subtarget->is64Bit())
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
378 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
379 setOperationAction(ISD::FREM , MVT::f32 , Expand);
380 setOperationAction(ISD::FREM , MVT::f64 , Expand);
381 setOperationAction(ISD::FREM , MVT::f80 , Expand);
382 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
384 // Promote the i8 variants and force them on up to i32 which has a shorter
386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
387 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
389 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
390 if (Subtarget->hasBMI()) {
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
396 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
397 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
402 if (Subtarget->hasLZCNT()) {
403 // When promoting the i8 variants, force them to i32 for a shorter
405 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
406 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
408 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
411 if (Subtarget->is64Bit())
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
414 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
426 if (Subtarget->hasPOPCNT()) {
427 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
429 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
430 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
431 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
436 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
437 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
439 // These should be promoted to a larger select which is supported.
440 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
441 // X86 wants to expand cmov itself.
442 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
443 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
444 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
445 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
447 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
448 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
451 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
454 if (Subtarget->is64Bit()) {
455 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
456 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
458 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
459 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support
460 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
461 // support continuation, user-level threading, and etc.. As a result, no
462 // other SjLj exception interfaces are implemented and please don't build
463 // your own exception handling based on them.
464 // LLVM/Clang supports zero-cost DWARF exception handling.
465 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
466 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
469 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
470 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
471 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
472 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
475 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
476 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
479 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
480 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
481 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
482 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
484 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
485 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
486 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
487 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
488 if (Subtarget->is64Bit()) {
489 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
490 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
491 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
494 if (Subtarget->hasSSE1())
495 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
497 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
498 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
500 // On X86 and X86-64, atomic operations are lowered to locked instructions.
501 // Locked instructions, in turn, have implicit fence semantics (all memory
502 // operations are flushed before issuing the locked instruction, and they
503 // are not buffered), so we can fold away the common pattern of
504 // fence-atomic-fence.
505 setShouldFoldAtomicFences(true);
507 // Expand certain atomics
508 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
512 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
515 if (!Subtarget->is64Bit()) {
516 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
517 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
518 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
519 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
520 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
521 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
522 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
523 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
524 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
525 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
526 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
527 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
530 if (Subtarget->hasCmpxchg16b()) {
531 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
534 // FIXME - use subtarget debug flags
535 if (!Subtarget->isTargetDarwin() &&
536 !Subtarget->isTargetELF() &&
537 !Subtarget->isTargetCygMing()) {
538 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
541 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
542 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
543 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
544 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
545 if (Subtarget->is64Bit()) {
546 setExceptionPointerRegister(X86::RAX);
547 setExceptionSelectorRegister(X86::RDX);
549 setExceptionPointerRegister(X86::EAX);
550 setExceptionSelectorRegister(X86::EDX);
552 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
553 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
555 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
556 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
558 setOperationAction(ISD::TRAP, MVT::Other, Legal);
559 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
561 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
562 setOperationAction(ISD::VASTART , MVT::Other, Custom);
563 setOperationAction(ISD::VAEND , MVT::Other, Expand);
564 if (Subtarget->is64Bit()) {
565 setOperationAction(ISD::VAARG , MVT::Other, Custom);
566 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
568 setOperationAction(ISD::VAARG , MVT::Other, Expand);
569 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
572 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
573 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
575 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
576 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
577 MVT::i64 : MVT::i32, Custom);
578 else if (TM.Options.EnableSegmentedStacks)
579 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
580 MVT::i64 : MVT::i32, Custom);
582 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
583 MVT::i64 : MVT::i32, Expand);
585 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
586 // f32 and f64 use SSE.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f32, &X86::FR32RegClass);
589 addRegisterClass(MVT::f64, &X86::FR64RegClass);
591 // Use ANDPD to simulate FABS.
592 setOperationAction(ISD::FABS , MVT::f64, Custom);
593 setOperationAction(ISD::FABS , MVT::f32, Custom);
595 // Use XORP to simulate FNEG.
596 setOperationAction(ISD::FNEG , MVT::f64, Custom);
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 // Use ANDPD and ORPD to simulate FCOPYSIGN.
600 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
601 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
603 // Lower this to FGETSIGNx86 plus an AND.
604 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
605 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
607 // We don't support sin/cos/fmod
608 setOperationAction(ISD::FSIN , MVT::f64, Expand);
609 setOperationAction(ISD::FCOS , MVT::f64, Expand);
610 setOperationAction(ISD::FSIN , MVT::f32, Expand);
611 setOperationAction(ISD::FCOS , MVT::f32, Expand);
613 // Expand FP immediates into loads from the stack, except for the special
615 addLegalFPImmediate(APFloat(+0.0)); // xorpd
616 addLegalFPImmediate(APFloat(+0.0f)); // xorps
617 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
618 // Use SSE for f32, x87 for f64.
619 // Set up the FP register classes.
620 addRegisterClass(MVT::f32, &X86::FR32RegClass);
621 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
623 // Use ANDPS to simulate FABS.
624 setOperationAction(ISD::FABS , MVT::f32, Custom);
626 // Use XORP to simulate FNEG.
627 setOperationAction(ISD::FNEG , MVT::f32, Custom);
629 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
631 // Use ANDPS and ORPS to simulate FCOPYSIGN.
632 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
633 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
635 // We don't support sin/cos/fmod
636 setOperationAction(ISD::FSIN , MVT::f32, Expand);
637 setOperationAction(ISD::FCOS , MVT::f32, Expand);
639 // Special cases we handle for FP constants.
640 addLegalFPImmediate(APFloat(+0.0f)); // xorps
641 addLegalFPImmediate(APFloat(+0.0)); // FLD0
642 addLegalFPImmediate(APFloat(+1.0)); // FLD1
643 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
644 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
646 if (!TM.Options.UnsafeFPMath) {
647 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
648 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
650 } else if (!TM.Options.UseSoftFloat) {
651 // f32 and f64 in x87.
652 // Set up the FP register classes.
653 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
654 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
656 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
657 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
658 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
659 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
661 if (!TM.Options.UnsafeFPMath) {
662 setOperationAction(ISD::FSIN , MVT::f32 , Expand);
663 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
664 setOperationAction(ISD::FCOS , MVT::f32 , Expand);
665 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
667 addLegalFPImmediate(APFloat(+0.0)); // FLD0
668 addLegalFPImmediate(APFloat(+1.0)); // FLD1
669 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
670 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
671 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
672 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
673 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
674 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
677 // We don't support FMA.
678 setOperationAction(ISD::FMA, MVT::f64, Expand);
679 setOperationAction(ISD::FMA, MVT::f32, Expand);
681 // Long double always uses X87.
682 if (!TM.Options.UseSoftFloat) {
683 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
684 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
685 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
687 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
688 addLegalFPImmediate(TmpFlt); // FLD0
690 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
693 APFloat TmpFlt2(+1.0);
694 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
696 addLegalFPImmediate(TmpFlt2); // FLD1
697 TmpFlt2.changeSign();
698 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
701 if (!TM.Options.UnsafeFPMath) {
702 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
703 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
706 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
707 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
708 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
709 setOperationAction(ISD::FRINT, MVT::f80, Expand);
710 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
711 setOperationAction(ISD::FMA, MVT::f80, Expand);
714 // Always use a library call for pow.
715 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
716 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
717 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
719 setOperationAction(ISD::FLOG, MVT::f80, Expand);
720 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
721 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
722 setOperationAction(ISD::FEXP, MVT::f80, Expand);
723 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
725 // First set operation action for all vector types to either promote
726 // (for widening) or expand (for scalarization). Then we will selectively
727 // turn on ones that can be effectively codegen'd.
728 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
729 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
730 MVT VT = (MVT::SimpleValueType)i;
731 setOperationAction(ISD::ADD , VT, Expand);
732 setOperationAction(ISD::SUB , VT, Expand);
733 setOperationAction(ISD::FADD, VT, Expand);
734 setOperationAction(ISD::FNEG, VT, Expand);
735 setOperationAction(ISD::FSUB, VT, Expand);
736 setOperationAction(ISD::MUL , VT, Expand);
737 setOperationAction(ISD::FMUL, VT, Expand);
738 setOperationAction(ISD::SDIV, VT, Expand);
739 setOperationAction(ISD::UDIV, VT, Expand);
740 setOperationAction(ISD::FDIV, VT, Expand);
741 setOperationAction(ISD::SREM, VT, Expand);
742 setOperationAction(ISD::UREM, VT, Expand);
743 setOperationAction(ISD::LOAD, VT, Expand);
744 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
746 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
747 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
748 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
749 setOperationAction(ISD::FABS, VT, Expand);
750 setOperationAction(ISD::FSIN, VT, Expand);
751 setOperationAction(ISD::FCOS, VT, Expand);
752 setOperationAction(ISD::FREM, VT, Expand);
753 setOperationAction(ISD::FMA, VT, Expand);
754 setOperationAction(ISD::FPOWI, VT, Expand);
755 setOperationAction(ISD::FSQRT, VT, Expand);
756 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
757 setOperationAction(ISD::FFLOOR, VT, Expand);
758 setOperationAction(ISD::FCEIL, VT, Expand);
759 setOperationAction(ISD::FTRUNC, VT, Expand);
760 setOperationAction(ISD::FRINT, VT, Expand);
761 setOperationAction(ISD::FNEARBYINT, VT, Expand);
762 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
763 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
764 setOperationAction(ISD::SDIVREM, VT, Expand);
765 setOperationAction(ISD::UDIVREM, VT, Expand);
766 setOperationAction(ISD::FPOW, VT, Expand);
767 setOperationAction(ISD::CTPOP, VT, Expand);
768 setOperationAction(ISD::CTTZ, VT, Expand);
769 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
770 setOperationAction(ISD::CTLZ, VT, Expand);
771 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
772 setOperationAction(ISD::SHL, VT, Expand);
773 setOperationAction(ISD::SRA, VT, Expand);
774 setOperationAction(ISD::SRL, VT, Expand);
775 setOperationAction(ISD::ROTL, VT, Expand);
776 setOperationAction(ISD::ROTR, VT, Expand);
777 setOperationAction(ISD::BSWAP, VT, Expand);
778 setOperationAction(ISD::SETCC, VT, Expand);
779 setOperationAction(ISD::FLOG, VT, Expand);
780 setOperationAction(ISD::FLOG2, VT, Expand);
781 setOperationAction(ISD::FLOG10, VT, Expand);
782 setOperationAction(ISD::FEXP, VT, Expand);
783 setOperationAction(ISD::FEXP2, VT, Expand);
784 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
785 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
786 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
787 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
788 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
789 setOperationAction(ISD::TRUNCATE, VT, Expand);
790 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
791 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
792 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
793 setOperationAction(ISD::VSELECT, VT, Expand);
794 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
795 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
796 setTruncStoreAction(VT,
797 (MVT::SimpleValueType)InnerVT, Expand);
798 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
799 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
800 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
803 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
804 // with -msoft-float, disable use of MMX as well.
805 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
806 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
807 // No operations on x86mmx supported, everything uses intrinsics.
810 // MMX-sized vectors (other than x86mmx) are expected to be expanded
811 // into smaller operations.
812 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
813 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
814 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
815 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
816 setOperationAction(ISD::AND, MVT::v8i8, Expand);
817 setOperationAction(ISD::AND, MVT::v4i16, Expand);
818 setOperationAction(ISD::AND, MVT::v2i32, Expand);
819 setOperationAction(ISD::AND, MVT::v1i64, Expand);
820 setOperationAction(ISD::OR, MVT::v8i8, Expand);
821 setOperationAction(ISD::OR, MVT::v4i16, Expand);
822 setOperationAction(ISD::OR, MVT::v2i32, Expand);
823 setOperationAction(ISD::OR, MVT::v1i64, Expand);
824 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
825 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
826 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
827 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
828 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
831 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
833 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
834 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
835 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
836 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
837 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
838 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
839 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
840 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
842 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
843 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
845 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
846 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
847 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
848 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
849 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
850 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
851 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
852 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
853 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
856 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
859 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
860 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
862 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
863 // registers cannot be used even for integer operations.
864 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
865 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
866 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
867 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
869 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
870 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
871 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
872 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
873 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
874 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
875 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
876 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
877 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
878 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
879 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
880 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
881 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
882 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
883 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
884 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
885 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
887 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
888 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
889 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
890 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
892 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
895 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
898 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
901 // Do not attempt to custom lower non-power-of-2 vectors
902 if (!isPowerOf2_32(VT.getVectorNumElements()))
904 // Do not attempt to custom lower non-128-bit vectors
905 if (!VT.is128BitVector())
907 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
908 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
909 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
912 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
913 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
914 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
915 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
916 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
919 if (Subtarget->is64Bit()) {
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
924 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
925 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
926 MVT VT = (MVT::SimpleValueType)i;
928 // Do not attempt to promote non-128-bit vectors
929 if (!VT.is128BitVector())
932 setOperationAction(ISD::AND, VT, Promote);
933 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
934 setOperationAction(ISD::OR, VT, Promote);
935 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
936 setOperationAction(ISD::XOR, VT, Promote);
937 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
938 setOperationAction(ISD::LOAD, VT, Promote);
939 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
940 setOperationAction(ISD::SELECT, VT, Promote);
941 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
944 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
946 // Custom lower v2i64 and v2f64 selects.
947 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
948 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
949 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
950 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
952 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
953 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
955 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
956 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
957 // As there is no 64-bit GPR available, we need build a special custom
958 // sequence to convert from v2i32 to v2f32.
959 if (!Subtarget->is64Bit())
960 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
962 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
963 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
965 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
968 if (Subtarget->hasSSE41()) {
969 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
970 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
971 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
972 setOperationAction(ISD::FRINT, MVT::f32, Legal);
973 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
974 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
975 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
976 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
977 setOperationAction(ISD::FRINT, MVT::f64, Legal);
978 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
980 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
981 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
982 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
983 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
984 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
985 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
986 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
988 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
991 // FIXME: Do we need to handle scalar-to-vector here?
992 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
994 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
995 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
996 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
997 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
998 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1000 // i8 and i16 vectors are custom , because the source register and source
1001 // source memory operand types are not the same width. f32 vectors are
1002 // custom since the immediate controlling the insert encodes additional
1004 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1005 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1007 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1014 // FIXME: these should be Legal but thats only for the case where
1015 // the index is constant. For now custom expand to deal with that.
1016 if (Subtarget->is64Bit()) {
1017 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1018 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1022 if (Subtarget->hasSSE2()) {
1023 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1029 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1030 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1032 if (Subtarget->hasInt256()) {
1033 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1034 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1036 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1037 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1039 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1041 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1042 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1044 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1045 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1047 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1051 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1052 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1053 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1059 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1060 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1063 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1064 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1074 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1077 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1087 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1089 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1091 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1094 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1095 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1097 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1098 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1099 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1101 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1103 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1104 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1106 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1117 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1118 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1121 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1122 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1123 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1124 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1126 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1127 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1129 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1130 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1131 setOperationAction(ISD::FMA, MVT::f32, Legal);
1132 setOperationAction(ISD::FMA, MVT::f64, Legal);
1135 if (Subtarget->hasInt256()) {
1136 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1137 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1138 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1139 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1141 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1142 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1143 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1144 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1146 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1147 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1148 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1149 // Don't lower v32i8 because there is no 128-bit byte mul
1151 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1153 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1154 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1156 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1157 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1161 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1174 // Don't lower v32i8 because there is no 128-bit byte mul
1176 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1177 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1179 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1180 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1182 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1185 // Custom lower several nodes for 256-bit types.
1186 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1187 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1188 MVT VT = (MVT::SimpleValueType)i;
1190 // Extract subvector is special because the value type
1191 // (result) is 128-bit but the source is 256-bit wide.
1192 if (VT.is128BitVector())
1193 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1195 // Do not attempt to custom lower other non-256-bit vectors
1196 if (!VT.is256BitVector())
1199 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1200 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1201 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1202 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1203 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1204 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1205 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1208 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1209 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1210 MVT VT = (MVT::SimpleValueType)i;
1212 // Do not attempt to promote non-256-bit vectors
1213 if (!VT.is256BitVector())
1216 setOperationAction(ISD::AND, VT, Promote);
1217 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1218 setOperationAction(ISD::OR, VT, Promote);
1219 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1220 setOperationAction(ISD::XOR, VT, Promote);
1221 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1222 setOperationAction(ISD::LOAD, VT, Promote);
1223 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1224 setOperationAction(ISD::SELECT, VT, Promote);
1225 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1229 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1230 // of this type with custom code.
1231 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1232 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1233 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1237 // We want to custom lower some of our intrinsics.
1238 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1239 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1242 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1243 // handle type legalization for these operations here.
1245 // FIXME: We really should do custom legalization for addition and
1246 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1247 // than generic legalization for 64-bit multiplication-with-overflow, though.
1248 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1249 // Add/Sub/Mul with overflow operations are custom lowered.
1251 setOperationAction(ISD::SADDO, VT, Custom);
1252 setOperationAction(ISD::UADDO, VT, Custom);
1253 setOperationAction(ISD::SSUBO, VT, Custom);
1254 setOperationAction(ISD::USUBO, VT, Custom);
1255 setOperationAction(ISD::SMULO, VT, Custom);
1256 setOperationAction(ISD::UMULO, VT, Custom);
1259 // There are no 8-bit 3-address imul/mul instructions
1260 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1261 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1263 if (!Subtarget->is64Bit()) {
1264 // These libcalls are not available in 32-bit.
1265 setLibcallName(RTLIB::SHL_I128, 0);
1266 setLibcallName(RTLIB::SRL_I128, 0);
1267 setLibcallName(RTLIB::SRA_I128, 0);
1270 // We have target-specific dag combine patterns for the following nodes:
1271 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1272 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1273 setTargetDAGCombine(ISD::VSELECT);
1274 setTargetDAGCombine(ISD::SELECT);
1275 setTargetDAGCombine(ISD::SHL);
1276 setTargetDAGCombine(ISD::SRA);
1277 setTargetDAGCombine(ISD::SRL);
1278 setTargetDAGCombine(ISD::OR);
1279 setTargetDAGCombine(ISD::AND);
1280 setTargetDAGCombine(ISD::ADD);
1281 setTargetDAGCombine(ISD::FADD);
1282 setTargetDAGCombine(ISD::FSUB);
1283 setTargetDAGCombine(ISD::FMA);
1284 setTargetDAGCombine(ISD::SUB);
1285 setTargetDAGCombine(ISD::LOAD);
1286 setTargetDAGCombine(ISD::STORE);
1287 setTargetDAGCombine(ISD::ZERO_EXTEND);
1288 setTargetDAGCombine(ISD::ANY_EXTEND);
1289 setTargetDAGCombine(ISD::SIGN_EXTEND);
1290 setTargetDAGCombine(ISD::TRUNCATE);
1291 setTargetDAGCombine(ISD::SINT_TO_FP);
1292 setTargetDAGCombine(ISD::SETCC);
1293 if (Subtarget->is64Bit())
1294 setTargetDAGCombine(ISD::MUL);
1295 setTargetDAGCombine(ISD::XOR);
1297 computeRegisterProperties();
1299 // On Darwin, -Os means optimize for size without hurting performance,
1300 // do not reduce the limit.
1301 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1302 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1303 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1304 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1305 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1306 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1307 setPrefLoopAlignment(4); // 2^4 bytes.
1308 benefitFromCodePlacementOpt = true;
1310 // Predictable cmov don't hurt on atom because it's in-order.
1311 predictableSelectIsExpensive = !Subtarget->isAtom();
1313 setPrefFunctionAlignment(4); // 2^4 bytes.
1317 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1318 if (!VT.isVector()) return MVT::i8;
1319 return VT.changeVectorElementTypeToInteger();
1323 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1324 /// the desired ByVal argument alignment.
1325 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1328 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1329 if (VTy->getBitWidth() == 128)
1331 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1332 unsigned EltAlign = 0;
1333 getMaxByValAlign(ATy->getElementType(), EltAlign);
1334 if (EltAlign > MaxAlign)
1335 MaxAlign = EltAlign;
1336 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1337 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1338 unsigned EltAlign = 0;
1339 getMaxByValAlign(STy->getElementType(i), EltAlign);
1340 if (EltAlign > MaxAlign)
1341 MaxAlign = EltAlign;
1348 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1349 /// function arguments in the caller parameter area. For X86, aggregates
1350 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1351 /// are at 4-byte boundaries.
1352 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1353 if (Subtarget->is64Bit()) {
1354 // Max of 8 and alignment of type.
1355 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1362 if (Subtarget->hasSSE1())
1363 getMaxByValAlign(Ty, Align);
1367 /// getOptimalMemOpType - Returns the target specific optimal type for load
1368 /// and store operations as a result of memset, memcpy, and memmove
1369 /// lowering. If DstAlign is zero that means it's safe to destination
1370 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1371 /// means there isn't a need to check it against alignment requirement,
1372 /// probably because the source does not need to be loaded. If 'IsMemset' is
1373 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1374 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1375 /// source is constant so it does not need to be loaded.
1376 /// It returns EVT::Other if the type should be determined using generic
1377 /// target-independent logic.
1379 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1380 unsigned DstAlign, unsigned SrcAlign,
1381 bool IsMemset, bool ZeroMemset,
1383 MachineFunction &MF) const {
1384 const Function *F = MF.getFunction();
1385 if ((!IsMemset || ZeroMemset) &&
1386 !F->getFnAttributes().hasAttribute(Attribute::NoImplicitFloat)) {
1388 (Subtarget->isUnalignedMemAccessFast() ||
1389 ((DstAlign == 0 || DstAlign >= 16) &&
1390 (SrcAlign == 0 || SrcAlign >= 16)))) {
1392 if (Subtarget->hasInt256())
1394 if (Subtarget->hasFp256())
1397 if (Subtarget->hasSSE2())
1399 if (Subtarget->hasSSE1())
1401 } else if (!MemcpyStrSrc && Size >= 8 &&
1402 !Subtarget->is64Bit() &&
1403 Subtarget->hasSSE2()) {
1404 // Do not use f64 to lower memcpy if source is string constant. It's
1405 // better to use i32 to avoid the loads.
1409 if (Subtarget->is64Bit() && Size >= 8)
1414 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1416 return X86ScalarSSEf32;
1417 else if (VT == MVT::f64)
1418 return X86ScalarSSEf64;
1423 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1425 *Fast = Subtarget->isUnalignedMemAccessFast();
1429 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1430 /// current function. The returned value is a member of the
1431 /// MachineJumpTableInfo::JTEntryKind enum.
1432 unsigned X86TargetLowering::getJumpTableEncoding() const {
1433 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1435 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1436 Subtarget->isPICStyleGOT())
1437 return MachineJumpTableInfo::EK_Custom32;
1439 // Otherwise, use the normal jump table encoding heuristics.
1440 return TargetLowering::getJumpTableEncoding();
1444 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1445 const MachineBasicBlock *MBB,
1446 unsigned uid,MCContext &Ctx) const{
1447 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1448 Subtarget->isPICStyleGOT());
1449 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1451 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1452 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1455 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1457 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1458 SelectionDAG &DAG) const {
1459 if (!Subtarget->is64Bit())
1460 // This doesn't have DebugLoc associated with it, but is not really the
1461 // same as a Register.
1462 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1466 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1467 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1469 const MCExpr *X86TargetLowering::
1470 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1471 MCContext &Ctx) const {
1472 // X86-64 uses RIP relative addressing based on the jump table label.
1473 if (Subtarget->isPICStyleRIPRel())
1474 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1476 // Otherwise, the reference is relative to the PIC base.
1477 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1480 // FIXME: Why this routine is here? Move to RegInfo!
1481 std::pair<const TargetRegisterClass*, uint8_t>
1482 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1483 const TargetRegisterClass *RRC = 0;
1485 switch (VT.getSimpleVT().SimpleTy) {
1487 return TargetLowering::findRepresentativeClass(VT);
1488 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1489 RRC = Subtarget->is64Bit() ?
1490 (const TargetRegisterClass*)&X86::GR64RegClass :
1491 (const TargetRegisterClass*)&X86::GR32RegClass;
1494 RRC = &X86::VR64RegClass;
1496 case MVT::f32: case MVT::f64:
1497 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1498 case MVT::v4f32: case MVT::v2f64:
1499 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1501 RRC = &X86::VR128RegClass;
1504 return std::make_pair(RRC, Cost);
1507 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1508 unsigned &Offset) const {
1509 if (!Subtarget->isTargetLinux())
1512 if (Subtarget->is64Bit()) {
1513 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1515 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1528 //===----------------------------------------------------------------------===//
1529 // Return Value Calling Convention Implementation
1530 //===----------------------------------------------------------------------===//
1532 #include "X86GenCallingConv.inc"
1535 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1536 MachineFunction &MF, bool isVarArg,
1537 const SmallVectorImpl<ISD::OutputArg> &Outs,
1538 LLVMContext &Context) const {
1539 SmallVector<CCValAssign, 16> RVLocs;
1540 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1542 return CCInfo.CheckReturn(Outs, RetCC_X86);
1546 X86TargetLowering::LowerReturn(SDValue Chain,
1547 CallingConv::ID CallConv, bool isVarArg,
1548 const SmallVectorImpl<ISD::OutputArg> &Outs,
1549 const SmallVectorImpl<SDValue> &OutVals,
1550 DebugLoc dl, SelectionDAG &DAG) const {
1551 MachineFunction &MF = DAG.getMachineFunction();
1552 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1554 SmallVector<CCValAssign, 16> RVLocs;
1555 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1556 RVLocs, *DAG.getContext());
1557 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1559 // Add the regs to the liveout set for the function.
1560 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1561 for (unsigned i = 0; i != RVLocs.size(); ++i)
1562 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1563 MRI.addLiveOut(RVLocs[i].getLocReg());
1567 SmallVector<SDValue, 6> RetOps;
1568 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1569 // Operand #1 = Bytes To Pop
1570 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1573 // Copy the result values into the output registers.
1574 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1575 CCValAssign &VA = RVLocs[i];
1576 assert(VA.isRegLoc() && "Can only return in registers!");
1577 SDValue ValToCopy = OutVals[i];
1578 EVT ValVT = ValToCopy.getValueType();
1580 // Promote values to the appropriate types
1581 if (VA.getLocInfo() == CCValAssign::SExt)
1582 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1583 else if (VA.getLocInfo() == CCValAssign::ZExt)
1584 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1585 else if (VA.getLocInfo() == CCValAssign::AExt)
1586 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1587 else if (VA.getLocInfo() == CCValAssign::BCvt)
1588 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1590 // If this is x86-64, and we disabled SSE, we can't return FP values,
1591 // or SSE or MMX vectors.
1592 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1593 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1594 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1595 report_fatal_error("SSE register return with SSE disabled");
1597 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1598 // llvm-gcc has never done it right and no one has noticed, so this
1599 // should be OK for now.
1600 if (ValVT == MVT::f64 &&
1601 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1602 report_fatal_error("SSE2 register return with SSE2 disabled");
1604 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1605 // the RET instruction and handled by the FP Stackifier.
1606 if (VA.getLocReg() == X86::ST0 ||
1607 VA.getLocReg() == X86::ST1) {
1608 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1609 // change the value to the FP stack register class.
1610 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1611 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1612 RetOps.push_back(ValToCopy);
1613 // Don't emit a copytoreg.
1617 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1618 // which is returned in RAX / RDX.
1619 if (Subtarget->is64Bit()) {
1620 if (ValVT == MVT::x86mmx) {
1621 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1622 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1623 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1625 // If we don't have SSE2 available, convert to v4f32 so the generated
1626 // register is legal.
1627 if (!Subtarget->hasSSE2())
1628 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1633 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1634 Flag = Chain.getValue(1);
1637 // The x86-64 ABI for returning structs by value requires that we copy
1638 // the sret argument into %rax for the return. We saved the argument into
1639 // a virtual register in the entry block, so now we copy the value out
1641 if (Subtarget->is64Bit() &&
1642 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1643 MachineFunction &MF = DAG.getMachineFunction();
1644 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1645 unsigned Reg = FuncInfo->getSRetReturnReg();
1647 "SRetReturnReg should have been set in LowerFormalArguments().");
1648 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1650 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1651 Flag = Chain.getValue(1);
1653 // RAX now acts like a return value.
1654 MRI.addLiveOut(X86::RAX);
1657 RetOps[0] = Chain; // Update chain.
1659 // Add the flag if we have it.
1661 RetOps.push_back(Flag);
1663 return DAG.getNode(X86ISD::RET_FLAG, dl,
1664 MVT::Other, &RetOps[0], RetOps.size());
1667 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1668 if (N->getNumValues() != 1)
1670 if (!N->hasNUsesOfValue(1, 0))
1673 SDValue TCChain = Chain;
1674 SDNode *Copy = *N->use_begin();
1675 if (Copy->getOpcode() == ISD::CopyToReg) {
1676 // If the copy has a glue operand, we conservatively assume it isn't safe to
1677 // perform a tail call.
1678 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1680 TCChain = Copy->getOperand(0);
1681 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1684 bool HasRet = false;
1685 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1687 if (UI->getOpcode() != X86ISD::RET_FLAG)
1700 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1701 ISD::NodeType ExtendKind) const {
1703 // TODO: Is this also valid on 32-bit?
1704 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1705 ReturnMVT = MVT::i8;
1707 ReturnMVT = MVT::i32;
1709 EVT MinVT = getRegisterType(Context, ReturnMVT);
1710 return VT.bitsLT(MinVT) ? MinVT : VT;
1713 /// LowerCallResult - Lower the result values of a call into the
1714 /// appropriate copies out of appropriate physical registers.
1717 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1718 CallingConv::ID CallConv, bool isVarArg,
1719 const SmallVectorImpl<ISD::InputArg> &Ins,
1720 DebugLoc dl, SelectionDAG &DAG,
1721 SmallVectorImpl<SDValue> &InVals) const {
1723 // Assign locations to each value returned by this call.
1724 SmallVector<CCValAssign, 16> RVLocs;
1725 bool Is64Bit = Subtarget->is64Bit();
1726 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1727 getTargetMachine(), RVLocs, *DAG.getContext());
1728 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1730 // Copy all of the result registers out of their specified physreg.
1731 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1732 CCValAssign &VA = RVLocs[i];
1733 EVT CopyVT = VA.getValVT();
1735 // If this is x86-64, and we disabled SSE, we can't return FP values
1736 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1737 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1738 report_fatal_error("SSE register return with SSE disabled");
1743 // If this is a call to a function that returns an fp value on the floating
1744 // point stack, we must guarantee the value is popped from the stack, so
1745 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1746 // if the return value is not used. We use the FpPOP_RETVAL instruction
1748 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1749 // If we prefer to use the value in xmm registers, copy it out as f80 and
1750 // use a truncate to move it from fp stack reg to xmm reg.
1751 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1752 SDValue Ops[] = { Chain, InFlag };
1753 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1754 MVT::Other, MVT::Glue, Ops, 2), 1);
1755 Val = Chain.getValue(0);
1757 // Round the f80 to the right size, which also moves it to the appropriate
1759 if (CopyVT != VA.getValVT())
1760 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1761 // This truncation won't change the value.
1762 DAG.getIntPtrConstant(1));
1764 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1765 CopyVT, InFlag).getValue(1);
1766 Val = Chain.getValue(0);
1768 InFlag = Chain.getValue(2);
1769 InVals.push_back(Val);
1776 //===----------------------------------------------------------------------===//
1777 // C & StdCall & Fast Calling Convention implementation
1778 //===----------------------------------------------------------------------===//
1779 // StdCall calling convention seems to be standard for many Windows' API
1780 // routines and around. It differs from C calling convention just a little:
1781 // callee should clean up the stack, not caller. Symbols should be also
1782 // decorated in some fancy way :) It doesn't support any vector arguments.
1783 // For info on fast calling convention see Fast Calling Convention (tail call)
1784 // implementation LowerX86_32FastCCCallTo.
1786 /// CallIsStructReturn - Determines whether a call uses struct return
1788 enum StructReturnType {
1793 static StructReturnType
1794 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1796 return NotStructReturn;
1798 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1799 if (!Flags.isSRet())
1800 return NotStructReturn;
1801 if (Flags.isInReg())
1802 return RegStructReturn;
1803 return StackStructReturn;
1806 /// ArgsAreStructReturn - Determines whether a function uses struct
1807 /// return semantics.
1808 static StructReturnType
1809 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1811 return NotStructReturn;
1813 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1814 if (!Flags.isSRet())
1815 return NotStructReturn;
1816 if (Flags.isInReg())
1817 return RegStructReturn;
1818 return StackStructReturn;
1821 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1822 /// by "Src" to address "Dst" with size and alignment information specified by
1823 /// the specific parameter attribute. The copy will be passed as a byval
1824 /// function parameter.
1826 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1827 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1829 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1831 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1832 /*isVolatile*/false, /*AlwaysInline=*/true,
1833 MachinePointerInfo(), MachinePointerInfo());
1836 /// IsTailCallConvention - Return true if the calling convention is one that
1837 /// supports tail call optimization.
1838 static bool IsTailCallConvention(CallingConv::ID CC) {
1839 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1840 CC == CallingConv::HiPE);
1843 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1844 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1848 CallingConv::ID CalleeCC = CS.getCallingConv();
1849 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1855 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1856 /// a tailcall target by changing its ABI.
1857 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1858 bool GuaranteedTailCallOpt) {
1859 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1863 X86TargetLowering::LowerMemArgument(SDValue Chain,
1864 CallingConv::ID CallConv,
1865 const SmallVectorImpl<ISD::InputArg> &Ins,
1866 DebugLoc dl, SelectionDAG &DAG,
1867 const CCValAssign &VA,
1868 MachineFrameInfo *MFI,
1870 // Create the nodes corresponding to a load from this parameter slot.
1871 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1872 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1873 getTargetMachine().Options.GuaranteedTailCallOpt);
1874 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1877 // If value is passed by pointer we have address passed instead of the value
1879 if (VA.getLocInfo() == CCValAssign::Indirect)
1880 ValVT = VA.getLocVT();
1882 ValVT = VA.getValVT();
1884 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1885 // changed with more analysis.
1886 // In case of tail call optimization mark all arguments mutable. Since they
1887 // could be overwritten by lowering of arguments in case of a tail call.
1888 if (Flags.isByVal()) {
1889 unsigned Bytes = Flags.getByValSize();
1890 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1891 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1892 return DAG.getFrameIndex(FI, getPointerTy());
1894 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1895 VA.getLocMemOffset(), isImmutable);
1896 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1897 return DAG.getLoad(ValVT, dl, Chain, FIN,
1898 MachinePointerInfo::getFixedStack(FI),
1899 false, false, false, 0);
1904 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1905 CallingConv::ID CallConv,
1907 const SmallVectorImpl<ISD::InputArg> &Ins,
1910 SmallVectorImpl<SDValue> &InVals)
1912 MachineFunction &MF = DAG.getMachineFunction();
1913 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1915 const Function* Fn = MF.getFunction();
1916 if (Fn->hasExternalLinkage() &&
1917 Subtarget->isTargetCygMing() &&
1918 Fn->getName() == "main")
1919 FuncInfo->setForceFramePointer(true);
1921 MachineFrameInfo *MFI = MF.getFrameInfo();
1922 bool Is64Bit = Subtarget->is64Bit();
1923 bool IsWindows = Subtarget->isTargetWindows();
1924 bool IsWin64 = Subtarget->isTargetWin64();
1926 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1927 "Var args not supported with calling convention fastcc, ghc or hipe");
1929 // Assign locations to all of the incoming arguments.
1930 SmallVector<CCValAssign, 16> ArgLocs;
1931 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1932 ArgLocs, *DAG.getContext());
1934 // Allocate shadow area for Win64
1936 CCInfo.AllocateStack(32, 8);
1939 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1941 unsigned LastVal = ~0U;
1943 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1944 CCValAssign &VA = ArgLocs[i];
1945 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1947 assert(VA.getValNo() != LastVal &&
1948 "Don't support value assigned to multiple locs yet");
1950 LastVal = VA.getValNo();
1952 if (VA.isRegLoc()) {
1953 EVT RegVT = VA.getLocVT();
1954 const TargetRegisterClass *RC;
1955 if (RegVT == MVT::i32)
1956 RC = &X86::GR32RegClass;
1957 else if (Is64Bit && RegVT == MVT::i64)
1958 RC = &X86::GR64RegClass;
1959 else if (RegVT == MVT::f32)
1960 RC = &X86::FR32RegClass;
1961 else if (RegVT == MVT::f64)
1962 RC = &X86::FR64RegClass;
1963 else if (RegVT.is256BitVector())
1964 RC = &X86::VR256RegClass;
1965 else if (RegVT.is128BitVector())
1966 RC = &X86::VR128RegClass;
1967 else if (RegVT == MVT::x86mmx)
1968 RC = &X86::VR64RegClass;
1970 llvm_unreachable("Unknown argument type!");
1972 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1973 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1975 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1976 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1978 if (VA.getLocInfo() == CCValAssign::SExt)
1979 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1980 DAG.getValueType(VA.getValVT()));
1981 else if (VA.getLocInfo() == CCValAssign::ZExt)
1982 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1983 DAG.getValueType(VA.getValVT()));
1984 else if (VA.getLocInfo() == CCValAssign::BCvt)
1985 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1987 if (VA.isExtInLoc()) {
1988 // Handle MMX values passed in XMM regs.
1989 if (RegVT.isVector()) {
1990 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1993 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1996 assert(VA.isMemLoc());
1997 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2000 // If value is passed via pointer - do a load.
2001 if (VA.getLocInfo() == CCValAssign::Indirect)
2002 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2003 MachinePointerInfo(), false, false, false, 0);
2005 InVals.push_back(ArgValue);
2008 // The x86-64 ABI for returning structs by value requires that we copy
2009 // the sret argument into %rax for the return. Save the argument into
2010 // a virtual register so that we can access it from the return points.
2011 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
2012 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2013 unsigned Reg = FuncInfo->getSRetReturnReg();
2015 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
2016 FuncInfo->setSRetReturnReg(Reg);
2018 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2019 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2022 unsigned StackSize = CCInfo.getNextStackOffset();
2023 // Align stack specially for tail calls.
2024 if (FuncIsMadeTailCallSafe(CallConv,
2025 MF.getTarget().Options.GuaranteedTailCallOpt))
2026 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2028 // If the function takes variable number of arguments, make a frame index for
2029 // the start of the first vararg value... for expansion of llvm.va_start.
2031 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2032 CallConv != CallingConv::X86_ThisCall)) {
2033 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2036 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2038 // FIXME: We should really autogenerate these arrays
2039 static const uint16_t GPR64ArgRegsWin64[] = {
2040 X86::RCX, X86::RDX, X86::R8, X86::R9
2042 static const uint16_t GPR64ArgRegs64Bit[] = {
2043 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2045 static const uint16_t XMMArgRegs64Bit[] = {
2046 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2047 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2049 const uint16_t *GPR64ArgRegs;
2050 unsigned NumXMMRegs = 0;
2053 // The XMM registers which might contain var arg parameters are shadowed
2054 // in their paired GPR. So we only need to save the GPR to their home
2056 TotalNumIntRegs = 4;
2057 GPR64ArgRegs = GPR64ArgRegsWin64;
2059 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2060 GPR64ArgRegs = GPR64ArgRegs64Bit;
2062 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2065 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2068 bool NoImplicitFloatOps = Fn->getFnAttributes().
2069 hasAttribute(Attribute::NoImplicitFloat);
2070 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2071 "SSE register cannot be used when SSE is disabled!");
2072 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2073 NoImplicitFloatOps) &&
2074 "SSE register cannot be used when SSE is disabled!");
2075 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2076 !Subtarget->hasSSE1())
2077 // Kernel mode asks for SSE to be disabled, so don't push them
2079 TotalNumXMMRegs = 0;
2082 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2083 // Get to the caller-allocated home save location. Add 8 to account
2084 // for the return address.
2085 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2086 FuncInfo->setRegSaveFrameIndex(
2087 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2088 // Fixup to set vararg frame on shadow area (4 x i64).
2090 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2092 // For X86-64, if there are vararg parameters that are passed via
2093 // registers, then we must store them to their spots on the stack so
2094 // they may be loaded by deferencing the result of va_next.
2095 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2096 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2097 FuncInfo->setRegSaveFrameIndex(
2098 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2102 // Store the integer parameter registers.
2103 SmallVector<SDValue, 8> MemOps;
2104 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2106 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2107 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2108 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2109 DAG.getIntPtrConstant(Offset));
2110 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2111 &X86::GR64RegClass);
2112 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2114 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2115 MachinePointerInfo::getFixedStack(
2116 FuncInfo->getRegSaveFrameIndex(), Offset),
2118 MemOps.push_back(Store);
2122 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2123 // Now store the XMM (fp + vector) parameter registers.
2124 SmallVector<SDValue, 11> SaveXMMOps;
2125 SaveXMMOps.push_back(Chain);
2127 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2128 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2129 SaveXMMOps.push_back(ALVal);
2131 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2132 FuncInfo->getRegSaveFrameIndex()));
2133 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2134 FuncInfo->getVarArgsFPOffset()));
2136 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2137 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2138 &X86::VR128RegClass);
2139 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2140 SaveXMMOps.push_back(Val);
2142 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2144 &SaveXMMOps[0], SaveXMMOps.size()));
2147 if (!MemOps.empty())
2148 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2149 &MemOps[0], MemOps.size());
2153 // Some CCs need callee pop.
2154 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2155 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2156 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2158 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2159 // If this is an sret function, the return should pop the hidden pointer.
2160 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2161 argsAreStructReturn(Ins) == StackStructReturn)
2162 FuncInfo->setBytesToPopOnReturn(4);
2166 // RegSaveFrameIndex is X86-64 only.
2167 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2168 if (CallConv == CallingConv::X86_FastCall ||
2169 CallConv == CallingConv::X86_ThisCall)
2170 // fastcc functions can't have varargs.
2171 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2174 FuncInfo->setArgumentStackSize(StackSize);
2180 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2181 SDValue StackPtr, SDValue Arg,
2182 DebugLoc dl, SelectionDAG &DAG,
2183 const CCValAssign &VA,
2184 ISD::ArgFlagsTy Flags) const {
2185 unsigned LocMemOffset = VA.getLocMemOffset();
2186 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2187 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2188 if (Flags.isByVal())
2189 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2191 return DAG.getStore(Chain, dl, Arg, PtrOff,
2192 MachinePointerInfo::getStack(LocMemOffset),
2196 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2197 /// optimization is performed and it is required.
2199 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2200 SDValue &OutRetAddr, SDValue Chain,
2201 bool IsTailCall, bool Is64Bit,
2202 int FPDiff, DebugLoc dl) const {
2203 // Adjust the Return address stack slot.
2204 EVT VT = getPointerTy();
2205 OutRetAddr = getReturnAddressFrameIndex(DAG);
2207 // Load the "old" Return address.
2208 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2209 false, false, false, 0);
2210 return SDValue(OutRetAddr.getNode(), 1);
2213 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2214 /// optimization is performed and it is required (FPDiff!=0).
2216 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2217 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2218 unsigned SlotSize, int FPDiff, DebugLoc dl) {
2219 // Store the return address to the appropriate stack slot.
2220 if (!FPDiff) return Chain;
2221 // Calculate the new stack slot for the return address.
2222 int NewReturnAddrFI =
2223 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2224 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2225 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2226 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2232 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2233 SmallVectorImpl<SDValue> &InVals) const {
2234 SelectionDAG &DAG = CLI.DAG;
2235 DebugLoc &dl = CLI.DL;
2236 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2237 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2238 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2239 SDValue Chain = CLI.Chain;
2240 SDValue Callee = CLI.Callee;
2241 CallingConv::ID CallConv = CLI.CallConv;
2242 bool &isTailCall = CLI.IsTailCall;
2243 bool isVarArg = CLI.IsVarArg;
2245 MachineFunction &MF = DAG.getMachineFunction();
2246 bool Is64Bit = Subtarget->is64Bit();
2247 bool IsWin64 = Subtarget->isTargetWin64();
2248 bool IsWindows = Subtarget->isTargetWindows();
2249 StructReturnType SR = callIsStructReturn(Outs);
2250 bool IsSibcall = false;
2252 if (MF.getTarget().Options.DisableTailCalls)
2256 // Check if it's really possible to do a tail call.
2257 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2258 isVarArg, SR != NotStructReturn,
2259 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2260 Outs, OutVals, Ins, DAG);
2262 // Sibcalls are automatically detected tailcalls which do not require
2264 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2271 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2272 "Var args not supported with calling convention fastcc, ghc or hipe");
2274 // Analyze operands of the call, assigning locations to each operand.
2275 SmallVector<CCValAssign, 16> ArgLocs;
2276 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2277 ArgLocs, *DAG.getContext());
2279 // Allocate shadow area for Win64
2281 CCInfo.AllocateStack(32, 8);
2284 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2286 // Get a count of how many bytes are to be pushed on the stack.
2287 unsigned NumBytes = CCInfo.getNextStackOffset();
2289 // This is a sibcall. The memory operands are available in caller's
2290 // own caller's stack.
2292 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2293 IsTailCallConvention(CallConv))
2294 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2297 if (isTailCall && !IsSibcall) {
2298 // Lower arguments at fp - stackoffset + fpdiff.
2299 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2300 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2302 FPDiff = NumBytesCallerPushed - NumBytes;
2304 // Set the delta of movement of the returnaddr stackslot.
2305 // But only set if delta is greater than previous delta.
2306 if (FPDiff < X86Info->getTCReturnAddrDelta())
2307 X86Info->setTCReturnAddrDelta(FPDiff);
2311 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2313 SDValue RetAddrFrIdx;
2314 // Load return address for tail calls.
2315 if (isTailCall && FPDiff)
2316 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2317 Is64Bit, FPDiff, dl);
2319 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2320 SmallVector<SDValue, 8> MemOpChains;
2323 // Walk the register/memloc assignments, inserting copies/loads. In the case
2324 // of tail call optimization arguments are handle later.
2325 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2326 CCValAssign &VA = ArgLocs[i];
2327 EVT RegVT = VA.getLocVT();
2328 SDValue Arg = OutVals[i];
2329 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2330 bool isByVal = Flags.isByVal();
2332 // Promote the value if needed.
2333 switch (VA.getLocInfo()) {
2334 default: llvm_unreachable("Unknown loc info!");
2335 case CCValAssign::Full: break;
2336 case CCValAssign::SExt:
2337 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2339 case CCValAssign::ZExt:
2340 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2342 case CCValAssign::AExt:
2343 if (RegVT.is128BitVector()) {
2344 // Special case: passing MMX values in XMM registers.
2345 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2346 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2347 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2349 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2351 case CCValAssign::BCvt:
2352 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2354 case CCValAssign::Indirect: {
2355 // Store the argument.
2356 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2357 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2358 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2359 MachinePointerInfo::getFixedStack(FI),
2366 if (VA.isRegLoc()) {
2367 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2368 if (isVarArg && IsWin64) {
2369 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2370 // shadow reg if callee is a varargs function.
2371 unsigned ShadowReg = 0;
2372 switch (VA.getLocReg()) {
2373 case X86::XMM0: ShadowReg = X86::RCX; break;
2374 case X86::XMM1: ShadowReg = X86::RDX; break;
2375 case X86::XMM2: ShadowReg = X86::R8; break;
2376 case X86::XMM3: ShadowReg = X86::R9; break;
2379 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2381 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2382 assert(VA.isMemLoc());
2383 if (StackPtr.getNode() == 0)
2384 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2386 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2387 dl, DAG, VA, Flags));
2391 if (!MemOpChains.empty())
2392 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2393 &MemOpChains[0], MemOpChains.size());
2395 if (Subtarget->isPICStyleGOT()) {
2396 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2399 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2400 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2402 // If we are tail calling and generating PIC/GOT style code load the
2403 // address of the callee into ECX. The value in ecx is used as target of
2404 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2405 // for tail calls on PIC/GOT architectures. Normally we would just put the
2406 // address of GOT into ebx and then call target@PLT. But for tail calls
2407 // ebx would be restored (since ebx is callee saved) before jumping to the
2410 // Note: The actual moving to ECX is done further down.
2411 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2412 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2413 !G->getGlobal()->hasProtectedVisibility())
2414 Callee = LowerGlobalAddress(Callee, DAG);
2415 else if (isa<ExternalSymbolSDNode>(Callee))
2416 Callee = LowerExternalSymbol(Callee, DAG);
2420 if (Is64Bit && isVarArg && !IsWin64) {
2421 // From AMD64 ABI document:
2422 // For calls that may call functions that use varargs or stdargs
2423 // (prototype-less calls or calls to functions containing ellipsis (...) in
2424 // the declaration) %al is used as hidden argument to specify the number
2425 // of SSE registers used. The contents of %al do not need to match exactly
2426 // the number of registers, but must be an ubound on the number of SSE
2427 // registers used and is in the range 0 - 8 inclusive.
2429 // Count the number of XMM registers allocated.
2430 static const uint16_t XMMArgRegs[] = {
2431 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2432 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2434 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2435 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2436 && "SSE registers cannot be used when SSE is disabled");
2438 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2439 DAG.getConstant(NumXMMRegs, MVT::i8)));
2442 // For tail calls lower the arguments to the 'real' stack slot.
2444 // Force all the incoming stack arguments to be loaded from the stack
2445 // before any new outgoing arguments are stored to the stack, because the
2446 // outgoing stack slots may alias the incoming argument stack slots, and
2447 // the alias isn't otherwise explicit. This is slightly more conservative
2448 // than necessary, because it means that each store effectively depends
2449 // on every argument instead of just those arguments it would clobber.
2450 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2452 SmallVector<SDValue, 8> MemOpChains2;
2455 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2456 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2457 CCValAssign &VA = ArgLocs[i];
2460 assert(VA.isMemLoc());
2461 SDValue Arg = OutVals[i];
2462 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2463 // Create frame index.
2464 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2465 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2466 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2467 FIN = DAG.getFrameIndex(FI, getPointerTy());
2469 if (Flags.isByVal()) {
2470 // Copy relative to framepointer.
2471 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2472 if (StackPtr.getNode() == 0)
2473 StackPtr = DAG.getCopyFromReg(Chain, dl,
2474 RegInfo->getStackRegister(),
2476 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2478 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2482 // Store relative to framepointer.
2483 MemOpChains2.push_back(
2484 DAG.getStore(ArgChain, dl, Arg, FIN,
2485 MachinePointerInfo::getFixedStack(FI),
2491 if (!MemOpChains2.empty())
2492 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2493 &MemOpChains2[0], MemOpChains2.size());
2495 // Store the return address to the appropriate stack slot.
2496 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2497 getPointerTy(), RegInfo->getSlotSize(),
2501 // Build a sequence of copy-to-reg nodes chained together with token chain
2502 // and flag operands which copy the outgoing args into registers.
2504 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2505 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2506 RegsToPass[i].second, InFlag);
2507 InFlag = Chain.getValue(1);
2510 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2511 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2512 // In the 64-bit large code model, we have to make all calls
2513 // through a register, since the call instruction's 32-bit
2514 // pc-relative offset may not be large enough to hold the whole
2516 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2517 // If the callee is a GlobalAddress node (quite common, every direct call
2518 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2521 // We should use extra load for direct calls to dllimported functions in
2523 const GlobalValue *GV = G->getGlobal();
2524 if (!GV->hasDLLImportLinkage()) {
2525 unsigned char OpFlags = 0;
2526 bool ExtraLoad = false;
2527 unsigned WrapperKind = ISD::DELETED_NODE;
2529 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2530 // external symbols most go through the PLT in PIC mode. If the symbol
2531 // has hidden or protected visibility, or if it is static or local, then
2532 // we don't need to use the PLT - we can directly call it.
2533 if (Subtarget->isTargetELF() &&
2534 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2535 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2536 OpFlags = X86II::MO_PLT;
2537 } else if (Subtarget->isPICStyleStubAny() &&
2538 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2539 (!Subtarget->getTargetTriple().isMacOSX() ||
2540 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2541 // PC-relative references to external symbols should go through $stub,
2542 // unless we're building with the leopard linker or later, which
2543 // automatically synthesizes these stubs.
2544 OpFlags = X86II::MO_DARWIN_STUB;
2545 } else if (Subtarget->isPICStyleRIPRel() &&
2546 isa<Function>(GV) &&
2547 cast<Function>(GV)->getFnAttributes().
2548 hasAttribute(Attribute::NonLazyBind)) {
2549 // If the function is marked as non-lazy, generate an indirect call
2550 // which loads from the GOT directly. This avoids runtime overhead
2551 // at the cost of eager binding (and one extra byte of encoding).
2552 OpFlags = X86II::MO_GOTPCREL;
2553 WrapperKind = X86ISD::WrapperRIP;
2557 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2558 G->getOffset(), OpFlags);
2560 // Add a wrapper if needed.
2561 if (WrapperKind != ISD::DELETED_NODE)
2562 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2563 // Add extra indirection if needed.
2565 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2566 MachinePointerInfo::getGOT(),
2567 false, false, false, 0);
2569 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2570 unsigned char OpFlags = 0;
2572 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2573 // external symbols should go through the PLT.
2574 if (Subtarget->isTargetELF() &&
2575 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2576 OpFlags = X86II::MO_PLT;
2577 } else if (Subtarget->isPICStyleStubAny() &&
2578 (!Subtarget->getTargetTriple().isMacOSX() ||
2579 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2580 // PC-relative references to external symbols should go through $stub,
2581 // unless we're building with the leopard linker or later, which
2582 // automatically synthesizes these stubs.
2583 OpFlags = X86II::MO_DARWIN_STUB;
2586 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2590 // Returns a chain & a flag for retval copy to use.
2591 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2592 SmallVector<SDValue, 8> Ops;
2594 if (!IsSibcall && isTailCall) {
2595 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2596 DAG.getIntPtrConstant(0, true), InFlag);
2597 InFlag = Chain.getValue(1);
2600 Ops.push_back(Chain);
2601 Ops.push_back(Callee);
2604 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2606 // Add argument registers to the end of the list so that they are known live
2608 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2609 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2610 RegsToPass[i].second.getValueType()));
2612 // Add a register mask operand representing the call-preserved registers.
2613 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2614 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2615 assert(Mask && "Missing call preserved mask for calling convention");
2616 Ops.push_back(DAG.getRegisterMask(Mask));
2618 if (InFlag.getNode())
2619 Ops.push_back(InFlag);
2623 //// If this is the first return lowered for this function, add the regs
2624 //// to the liveout set for the function.
2625 // This isn't right, although it's probably harmless on x86; liveouts
2626 // should be computed from returns not tail calls. Consider a void
2627 // function making a tail call to a function returning int.
2628 return DAG.getNode(X86ISD::TC_RETURN, dl,
2629 NodeTys, &Ops[0], Ops.size());
2632 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2633 InFlag = Chain.getValue(1);
2635 // Create the CALLSEQ_END node.
2636 unsigned NumBytesForCalleeToPush;
2637 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2638 getTargetMachine().Options.GuaranteedTailCallOpt))
2639 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2640 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2641 SR == StackStructReturn)
2642 // If this is a call to a struct-return function, the callee
2643 // pops the hidden struct pointer, so we have to push it back.
2644 // This is common for Darwin/X86, Linux & Mingw32 targets.
2645 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2646 NumBytesForCalleeToPush = 4;
2648 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2650 // Returns a flag for retval copy to use.
2652 Chain = DAG.getCALLSEQ_END(Chain,
2653 DAG.getIntPtrConstant(NumBytes, true),
2654 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2657 InFlag = Chain.getValue(1);
2660 // Handle result values, copying them out of physregs into vregs that we
2662 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2663 Ins, dl, DAG, InVals);
2667 //===----------------------------------------------------------------------===//
2668 // Fast Calling Convention (tail call) implementation
2669 //===----------------------------------------------------------------------===//
2671 // Like std call, callee cleans arguments, convention except that ECX is
2672 // reserved for storing the tail called function address. Only 2 registers are
2673 // free for argument passing (inreg). Tail call optimization is performed
2675 // * tailcallopt is enabled
2676 // * caller/callee are fastcc
2677 // On X86_64 architecture with GOT-style position independent code only local
2678 // (within module) calls are supported at the moment.
2679 // To keep the stack aligned according to platform abi the function
2680 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2681 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2682 // If a tail called function callee has more arguments than the caller the
2683 // caller needs to make sure that there is room to move the RETADDR to. This is
2684 // achieved by reserving an area the size of the argument delta right after the
2685 // original REtADDR, but before the saved framepointer or the spilled registers
2686 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2698 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2699 /// for a 16 byte align requirement.
2701 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2702 SelectionDAG& DAG) const {
2703 MachineFunction &MF = DAG.getMachineFunction();
2704 const TargetMachine &TM = MF.getTarget();
2705 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2706 unsigned StackAlignment = TFI.getStackAlignment();
2707 uint64_t AlignMask = StackAlignment - 1;
2708 int64_t Offset = StackSize;
2709 unsigned SlotSize = RegInfo->getSlotSize();
2710 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2711 // Number smaller than 12 so just add the difference.
2712 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2714 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2715 Offset = ((~AlignMask) & Offset) + StackAlignment +
2716 (StackAlignment-SlotSize);
2721 /// MatchingStackOffset - Return true if the given stack call argument is
2722 /// already available in the same position (relatively) of the caller's
2723 /// incoming argument stack.
2725 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2726 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2727 const X86InstrInfo *TII) {
2728 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2730 if (Arg.getOpcode() == ISD::CopyFromReg) {
2731 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2732 if (!TargetRegisterInfo::isVirtualRegister(VR))
2734 MachineInstr *Def = MRI->getVRegDef(VR);
2737 if (!Flags.isByVal()) {
2738 if (!TII->isLoadFromStackSlot(Def, FI))
2741 unsigned Opcode = Def->getOpcode();
2742 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2743 Def->getOperand(1).isFI()) {
2744 FI = Def->getOperand(1).getIndex();
2745 Bytes = Flags.getByValSize();
2749 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2750 if (Flags.isByVal())
2751 // ByVal argument is passed in as a pointer but it's now being
2752 // dereferenced. e.g.
2753 // define @foo(%struct.X* %A) {
2754 // tail call @bar(%struct.X* byval %A)
2757 SDValue Ptr = Ld->getBasePtr();
2758 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2761 FI = FINode->getIndex();
2762 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2763 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2764 FI = FINode->getIndex();
2765 Bytes = Flags.getByValSize();
2769 assert(FI != INT_MAX);
2770 if (!MFI->isFixedObjectIndex(FI))
2772 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2775 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2776 /// for tail call optimization. Targets which want to do tail call
2777 /// optimization should implement this function.
2779 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2780 CallingConv::ID CalleeCC,
2782 bool isCalleeStructRet,
2783 bool isCallerStructRet,
2785 const SmallVectorImpl<ISD::OutputArg> &Outs,
2786 const SmallVectorImpl<SDValue> &OutVals,
2787 const SmallVectorImpl<ISD::InputArg> &Ins,
2788 SelectionDAG& DAG) const {
2789 if (!IsTailCallConvention(CalleeCC) &&
2790 CalleeCC != CallingConv::C)
2793 // If -tailcallopt is specified, make fastcc functions tail-callable.
2794 const MachineFunction &MF = DAG.getMachineFunction();
2795 const Function *CallerF = DAG.getMachineFunction().getFunction();
2797 // If the function return type is x86_fp80 and the callee return type is not,
2798 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2799 // perform a tailcall optimization here.
2800 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
2803 CallingConv::ID CallerCC = CallerF->getCallingConv();
2804 bool CCMatch = CallerCC == CalleeCC;
2806 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2807 if (IsTailCallConvention(CalleeCC) && CCMatch)
2812 // Look for obvious safe cases to perform tail call optimization that do not
2813 // require ABI changes. This is what gcc calls sibcall.
2815 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2816 // emit a special epilogue.
2817 if (RegInfo->needsStackRealignment(MF))
2820 // Also avoid sibcall optimization if either caller or callee uses struct
2821 // return semantics.
2822 if (isCalleeStructRet || isCallerStructRet)
2825 // An stdcall caller is expected to clean up its arguments; the callee
2826 // isn't going to do that.
2827 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2830 // Do not sibcall optimize vararg calls unless all arguments are passed via
2832 if (isVarArg && !Outs.empty()) {
2834 // Optimizing for varargs on Win64 is unlikely to be safe without
2835 // additional testing.
2836 if (Subtarget->isTargetWin64())
2839 SmallVector<CCValAssign, 16> ArgLocs;
2840 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2841 getTargetMachine(), ArgLocs, *DAG.getContext());
2843 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2844 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2845 if (!ArgLocs[i].isRegLoc())
2849 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2850 // stack. Therefore, if it's not used by the call it is not safe to optimize
2851 // this into a sibcall.
2852 bool Unused = false;
2853 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2860 SmallVector<CCValAssign, 16> RVLocs;
2861 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2862 getTargetMachine(), RVLocs, *DAG.getContext());
2863 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2864 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2865 CCValAssign &VA = RVLocs[i];
2866 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2871 // If the calling conventions do not match, then we'd better make sure the
2872 // results are returned in the same way as what the caller expects.
2874 SmallVector<CCValAssign, 16> RVLocs1;
2875 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2876 getTargetMachine(), RVLocs1, *DAG.getContext());
2877 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2879 SmallVector<CCValAssign, 16> RVLocs2;
2880 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2881 getTargetMachine(), RVLocs2, *DAG.getContext());
2882 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2884 if (RVLocs1.size() != RVLocs2.size())
2886 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2887 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2889 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2891 if (RVLocs1[i].isRegLoc()) {
2892 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2895 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2901 // If the callee takes no arguments then go on to check the results of the
2903 if (!Outs.empty()) {
2904 // Check if stack adjustment is needed. For now, do not do this if any
2905 // argument is passed on the stack.
2906 SmallVector<CCValAssign, 16> ArgLocs;
2907 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2908 getTargetMachine(), ArgLocs, *DAG.getContext());
2910 // Allocate shadow area for Win64
2911 if (Subtarget->isTargetWin64()) {
2912 CCInfo.AllocateStack(32, 8);
2915 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2916 if (CCInfo.getNextStackOffset()) {
2917 MachineFunction &MF = DAG.getMachineFunction();
2918 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2921 // Check if the arguments are already laid out in the right way as
2922 // the caller's fixed stack objects.
2923 MachineFrameInfo *MFI = MF.getFrameInfo();
2924 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2925 const X86InstrInfo *TII =
2926 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
2927 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2928 CCValAssign &VA = ArgLocs[i];
2929 SDValue Arg = OutVals[i];
2930 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2931 if (VA.getLocInfo() == CCValAssign::Indirect)
2933 if (!VA.isRegLoc()) {
2934 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2941 // If the tailcall address may be in a register, then make sure it's
2942 // possible to register allocate for it. In 32-bit, the call address can
2943 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2944 // callee-saved registers are restored. These happen to be the same
2945 // registers used to pass 'inreg' arguments so watch out for those.
2946 if (!Subtarget->is64Bit() &&
2947 !isa<GlobalAddressSDNode>(Callee) &&
2948 !isa<ExternalSymbolSDNode>(Callee)) {
2949 unsigned NumInRegs = 0;
2950 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2951 CCValAssign &VA = ArgLocs[i];
2954 unsigned Reg = VA.getLocReg();
2957 case X86::EAX: case X86::EDX: case X86::ECX:
2958 if (++NumInRegs == 3)
2970 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2971 const TargetLibraryInfo *libInfo) const {
2972 return X86::createFastISel(funcInfo, libInfo);
2976 //===----------------------------------------------------------------------===//
2977 // Other Lowering Hooks
2978 //===----------------------------------------------------------------------===//
2980 static bool MayFoldLoad(SDValue Op) {
2981 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2984 static bool MayFoldIntoStore(SDValue Op) {
2985 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2988 static bool isTargetShuffle(unsigned Opcode) {
2990 default: return false;
2991 case X86ISD::PSHUFD:
2992 case X86ISD::PSHUFHW:
2993 case X86ISD::PSHUFLW:
2995 case X86ISD::PALIGN:
2996 case X86ISD::MOVLHPS:
2997 case X86ISD::MOVLHPD:
2998 case X86ISD::MOVHLPS:
2999 case X86ISD::MOVLPS:
3000 case X86ISD::MOVLPD:
3001 case X86ISD::MOVSHDUP:
3002 case X86ISD::MOVSLDUP:
3003 case X86ISD::MOVDDUP:
3006 case X86ISD::UNPCKL:
3007 case X86ISD::UNPCKH:
3008 case X86ISD::VPERMILP:
3009 case X86ISD::VPERM2X128:
3010 case X86ISD::VPERMI:
3015 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3016 SDValue V1, SelectionDAG &DAG) {
3018 default: llvm_unreachable("Unknown x86 shuffle node");
3019 case X86ISD::MOVSHDUP:
3020 case X86ISD::MOVSLDUP:
3021 case X86ISD::MOVDDUP:
3022 return DAG.getNode(Opc, dl, VT, V1);
3026 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3027 SDValue V1, unsigned TargetMask,
3028 SelectionDAG &DAG) {
3030 default: llvm_unreachable("Unknown x86 shuffle node");
3031 case X86ISD::PSHUFD:
3032 case X86ISD::PSHUFHW:
3033 case X86ISD::PSHUFLW:
3034 case X86ISD::VPERMILP:
3035 case X86ISD::VPERMI:
3036 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3040 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3041 SDValue V1, SDValue V2, unsigned TargetMask,
3042 SelectionDAG &DAG) {
3044 default: llvm_unreachable("Unknown x86 shuffle node");
3045 case X86ISD::PALIGN:
3047 case X86ISD::VPERM2X128:
3048 return DAG.getNode(Opc, dl, VT, V1, V2,
3049 DAG.getConstant(TargetMask, MVT::i8));
3053 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3054 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3056 default: llvm_unreachable("Unknown x86 shuffle node");
3057 case X86ISD::MOVLHPS:
3058 case X86ISD::MOVLHPD:
3059 case X86ISD::MOVHLPS:
3060 case X86ISD::MOVLPS:
3061 case X86ISD::MOVLPD:
3064 case X86ISD::UNPCKL:
3065 case X86ISD::UNPCKH:
3066 return DAG.getNode(Opc, dl, VT, V1, V2);
3070 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3071 MachineFunction &MF = DAG.getMachineFunction();
3072 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3073 int ReturnAddrIndex = FuncInfo->getRAIndex();
3075 if (ReturnAddrIndex == 0) {
3076 // Set up a frame object for the return address.
3077 unsigned SlotSize = RegInfo->getSlotSize();
3078 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3080 FuncInfo->setRAIndex(ReturnAddrIndex);
3083 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3087 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3088 bool hasSymbolicDisplacement) {
3089 // Offset should fit into 32 bit immediate field.
3090 if (!isInt<32>(Offset))
3093 // If we don't have a symbolic displacement - we don't have any extra
3095 if (!hasSymbolicDisplacement)
3098 // FIXME: Some tweaks might be needed for medium code model.
3099 if (M != CodeModel::Small && M != CodeModel::Kernel)
3102 // For small code model we assume that latest object is 16MB before end of 31
3103 // bits boundary. We may also accept pretty large negative constants knowing
3104 // that all objects are in the positive half of address space.
3105 if (M == CodeModel::Small && Offset < 16*1024*1024)
3108 // For kernel code model we know that all object resist in the negative half
3109 // of 32bits address space. We may not accept negative offsets, since they may
3110 // be just off and we may accept pretty large positive ones.
3111 if (M == CodeModel::Kernel && Offset > 0)
3117 /// isCalleePop - Determines whether the callee is required to pop its
3118 /// own arguments. Callee pop is necessary to support tail calls.
3119 bool X86::isCalleePop(CallingConv::ID CallingConv,
3120 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3124 switch (CallingConv) {
3127 case CallingConv::X86_StdCall:
3129 case CallingConv::X86_FastCall:
3131 case CallingConv::X86_ThisCall:
3133 case CallingConv::Fast:
3135 case CallingConv::GHC:
3137 case CallingConv::HiPE:
3142 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3143 /// specific condition code, returning the condition code and the LHS/RHS of the
3144 /// comparison to make.
3145 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3146 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3148 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3149 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3150 // X > -1 -> X == 0, jump !sign.
3151 RHS = DAG.getConstant(0, RHS.getValueType());
3152 return X86::COND_NS;
3154 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3155 // X < 0 -> X == 0, jump on sign.
3158 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3160 RHS = DAG.getConstant(0, RHS.getValueType());
3161 return X86::COND_LE;
3165 switch (SetCCOpcode) {
3166 default: llvm_unreachable("Invalid integer condition!");
3167 case ISD::SETEQ: return X86::COND_E;
3168 case ISD::SETGT: return X86::COND_G;
3169 case ISD::SETGE: return X86::COND_GE;
3170 case ISD::SETLT: return X86::COND_L;
3171 case ISD::SETLE: return X86::COND_LE;
3172 case ISD::SETNE: return X86::COND_NE;
3173 case ISD::SETULT: return X86::COND_B;
3174 case ISD::SETUGT: return X86::COND_A;
3175 case ISD::SETULE: return X86::COND_BE;
3176 case ISD::SETUGE: return X86::COND_AE;
3180 // First determine if it is required or is profitable to flip the operands.
3182 // If LHS is a foldable load, but RHS is not, flip the condition.
3183 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3184 !ISD::isNON_EXTLoad(RHS.getNode())) {
3185 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3186 std::swap(LHS, RHS);
3189 switch (SetCCOpcode) {
3195 std::swap(LHS, RHS);
3199 // On a floating point condition, the flags are set as follows:
3201 // 0 | 0 | 0 | X > Y
3202 // 0 | 0 | 1 | X < Y
3203 // 1 | 0 | 0 | X == Y
3204 // 1 | 1 | 1 | unordered
3205 switch (SetCCOpcode) {
3206 default: llvm_unreachable("Condcode should be pre-legalized away");
3208 case ISD::SETEQ: return X86::COND_E;
3209 case ISD::SETOLT: // flipped
3211 case ISD::SETGT: return X86::COND_A;
3212 case ISD::SETOLE: // flipped
3214 case ISD::SETGE: return X86::COND_AE;
3215 case ISD::SETUGT: // flipped
3217 case ISD::SETLT: return X86::COND_B;
3218 case ISD::SETUGE: // flipped
3220 case ISD::SETLE: return X86::COND_BE;
3222 case ISD::SETNE: return X86::COND_NE;
3223 case ISD::SETUO: return X86::COND_P;
3224 case ISD::SETO: return X86::COND_NP;
3226 case ISD::SETUNE: return X86::COND_INVALID;
3230 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3231 /// code. Current x86 isa includes the following FP cmov instructions:
3232 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3233 static bool hasFPCMov(unsigned X86CC) {
3249 /// isFPImmLegal - Returns true if the target can instruction select the
3250 /// specified FP immediate natively. If false, the legalizer will
3251 /// materialize the FP immediate as a load from a constant pool.
3252 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3253 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3254 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3260 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3261 /// the specified range (L, H].
3262 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3263 return (Val < 0) || (Val >= Low && Val < Hi);
3266 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3267 /// specified value.
3268 static bool isUndefOrEqual(int Val, int CmpVal) {
3269 return (Val < 0 || Val == CmpVal);
3272 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3273 /// from position Pos and ending in Pos+Size, falls within the specified
3274 /// sequential range (L, L+Pos]. or is undef.
3275 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3276 unsigned Pos, unsigned Size, int Low) {
3277 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3278 if (!isUndefOrEqual(Mask[i], Low))
3283 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3284 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3285 /// the second operand.
3286 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3287 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3288 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3289 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3290 return (Mask[0] < 2 && Mask[1] < 2);
3294 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3295 /// is suitable for input to PSHUFHW.
3296 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3297 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3300 // Lower quadword copied in order or undef.
3301 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3304 // Upper quadword shuffled.
3305 for (unsigned i = 4; i != 8; ++i)
3306 if (!isUndefOrInRange(Mask[i], 4, 8))
3309 if (VT == MVT::v16i16) {
3310 // Lower quadword copied in order or undef.
3311 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3314 // Upper quadword shuffled.
3315 for (unsigned i = 12; i != 16; ++i)
3316 if (!isUndefOrInRange(Mask[i], 12, 16))
3323 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3324 /// is suitable for input to PSHUFLW.
3325 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3326 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3329 // Upper quadword copied in order.
3330 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3333 // Lower quadword shuffled.
3334 for (unsigned i = 0; i != 4; ++i)
3335 if (!isUndefOrInRange(Mask[i], 0, 4))
3338 if (VT == MVT::v16i16) {
3339 // Upper quadword copied in order.
3340 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3343 // Lower quadword shuffled.
3344 for (unsigned i = 8; i != 12; ++i)
3345 if (!isUndefOrInRange(Mask[i], 8, 12))
3352 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3353 /// is suitable for input to PALIGNR.
3354 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3355 const X86Subtarget *Subtarget) {
3356 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3357 (VT.getSizeInBits() == 256 && !Subtarget->hasInt256()))
3360 unsigned NumElts = VT.getVectorNumElements();
3361 unsigned NumLanes = VT.getSizeInBits()/128;
3362 unsigned NumLaneElts = NumElts/NumLanes;
3364 // Do not handle 64-bit element shuffles with palignr.
3365 if (NumLaneElts == 2)
3368 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3370 for (i = 0; i != NumLaneElts; ++i) {
3375 // Lane is all undef, go to next lane
3376 if (i == NumLaneElts)
3379 int Start = Mask[i+l];
3381 // Make sure its in this lane in one of the sources
3382 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3383 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3386 // If not lane 0, then we must match lane 0
3387 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3390 // Correct second source to be contiguous with first source
3391 if (Start >= (int)NumElts)
3392 Start -= NumElts - NumLaneElts;
3394 // Make sure we're shifting in the right direction.
3395 if (Start <= (int)(i+l))
3400 // Check the rest of the elements to see if they are consecutive.
3401 for (++i; i != NumLaneElts; ++i) {
3402 int Idx = Mask[i+l];
3404 // Make sure its in this lane
3405 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3406 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3409 // If not lane 0, then we must match lane 0
3410 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3413 if (Idx >= (int)NumElts)
3414 Idx -= NumElts - NumLaneElts;
3416 if (!isUndefOrEqual(Idx, Start+i))
3425 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3426 /// the two vector operands have swapped position.
3427 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3428 unsigned NumElems) {
3429 for (unsigned i = 0; i != NumElems; ++i) {
3433 else if (idx < (int)NumElems)
3434 Mask[i] = idx + NumElems;
3436 Mask[i] = idx - NumElems;
3440 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3441 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3442 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3443 /// reverse of what x86 shuffles want.
3444 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3445 bool Commuted = false) {
3446 if (!HasFp256 && VT.getSizeInBits() == 256)
3449 unsigned NumElems = VT.getVectorNumElements();
3450 unsigned NumLanes = VT.getSizeInBits()/128;
3451 unsigned NumLaneElems = NumElems/NumLanes;
3453 if (NumLaneElems != 2 && NumLaneElems != 4)
3456 // VSHUFPSY divides the resulting vector into 4 chunks.
3457 // The sources are also splitted into 4 chunks, and each destination
3458 // chunk must come from a different source chunk.
3460 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3461 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3463 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3464 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3466 // VSHUFPDY divides the resulting vector into 4 chunks.
3467 // The sources are also splitted into 4 chunks, and each destination
3468 // chunk must come from a different source chunk.
3470 // SRC1 => X3 X2 X1 X0
3471 // SRC2 => Y3 Y2 Y1 Y0
3473 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3475 unsigned HalfLaneElems = NumLaneElems/2;
3476 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3477 for (unsigned i = 0; i != NumLaneElems; ++i) {
3478 int Idx = Mask[i+l];
3479 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3480 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3482 // For VSHUFPSY, the mask of the second half must be the same as the
3483 // first but with the appropriate offsets. This works in the same way as
3484 // VPERMILPS works with masks.
3485 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3487 if (!isUndefOrEqual(Idx, Mask[i]+l))
3495 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3496 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3497 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3498 if (!VT.is128BitVector())
3501 unsigned NumElems = VT.getVectorNumElements();
3506 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3507 return isUndefOrEqual(Mask[0], 6) &&
3508 isUndefOrEqual(Mask[1], 7) &&
3509 isUndefOrEqual(Mask[2], 2) &&
3510 isUndefOrEqual(Mask[3], 3);
3513 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3514 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3516 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3517 if (!VT.is128BitVector())
3520 unsigned NumElems = VT.getVectorNumElements();
3525 return isUndefOrEqual(Mask[0], 2) &&
3526 isUndefOrEqual(Mask[1], 3) &&
3527 isUndefOrEqual(Mask[2], 2) &&
3528 isUndefOrEqual(Mask[3], 3);
3531 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3532 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3533 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3534 if (!VT.is128BitVector())
3537 unsigned NumElems = VT.getVectorNumElements();
3539 if (NumElems != 2 && NumElems != 4)
3542 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3543 if (!isUndefOrEqual(Mask[i], i + NumElems))
3546 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3547 if (!isUndefOrEqual(Mask[i], i))
3553 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3554 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3555 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3556 if (!VT.is128BitVector())
3559 unsigned NumElems = VT.getVectorNumElements();
3561 if (NumElems != 2 && NumElems != 4)
3564 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3565 if (!isUndefOrEqual(Mask[i], i))
3568 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3569 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3576 // Some special combinations that can be optimized.
3579 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3580 SelectionDAG &DAG) {
3581 EVT VT = SVOp->getValueType(0);
3582 DebugLoc dl = SVOp->getDebugLoc();
3584 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3587 ArrayRef<int> Mask = SVOp->getMask();
3589 // These are the special masks that may be optimized.
3590 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3591 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3592 bool MatchEvenMask = true;
3593 bool MatchOddMask = true;
3594 for (int i=0; i<8; ++i) {
3595 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3596 MatchEvenMask = false;
3597 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3598 MatchOddMask = false;
3601 if (!MatchEvenMask && !MatchOddMask)
3604 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3606 SDValue Op0 = SVOp->getOperand(0);
3607 SDValue Op1 = SVOp->getOperand(1);
3609 if (MatchEvenMask) {
3610 // Shift the second operand right to 32 bits.
3611 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3612 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3614 // Shift the first operand left to 32 bits.
3615 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3616 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3618 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3619 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3622 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3623 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3624 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3625 bool HasInt256, bool V2IsSplat = false) {
3626 unsigned NumElts = VT.getVectorNumElements();
3628 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3629 "Unsupported vector type for unpckh");
3631 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3632 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3635 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3636 // independently on 128-bit lanes.
3637 unsigned NumLanes = VT.getSizeInBits()/128;
3638 unsigned NumLaneElts = NumElts/NumLanes;
3640 for (unsigned l = 0; l != NumLanes; ++l) {
3641 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3642 i != (l+1)*NumLaneElts;
3645 int BitI1 = Mask[i+1];
3646 if (!isUndefOrEqual(BitI, j))
3649 if (!isUndefOrEqual(BitI1, NumElts))
3652 if (!isUndefOrEqual(BitI1, j + NumElts))
3661 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3662 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3663 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3664 bool HasInt256, bool V2IsSplat = false) {
3665 unsigned NumElts = VT.getVectorNumElements();
3667 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3668 "Unsupported vector type for unpckh");
3670 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3671 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3674 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3675 // independently on 128-bit lanes.
3676 unsigned NumLanes = VT.getSizeInBits()/128;
3677 unsigned NumLaneElts = NumElts/NumLanes;
3679 for (unsigned l = 0; l != NumLanes; ++l) {
3680 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3681 i != (l+1)*NumLaneElts; i += 2, ++j) {
3683 int BitI1 = Mask[i+1];
3684 if (!isUndefOrEqual(BitI, j))
3687 if (isUndefOrEqual(BitI1, NumElts))
3690 if (!isUndefOrEqual(BitI1, j+NumElts))
3698 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3699 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3701 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3703 unsigned NumElts = VT.getVectorNumElements();
3705 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3706 "Unsupported vector type for unpckh");
3708 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3709 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3712 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3713 // FIXME: Need a better way to get rid of this, there's no latency difference
3714 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3715 // the former later. We should also remove the "_undef" special mask.
3716 if (NumElts == 4 && VT.getSizeInBits() == 256)
3719 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3720 // independently on 128-bit lanes.
3721 unsigned NumLanes = VT.getSizeInBits()/128;
3722 unsigned NumLaneElts = NumElts/NumLanes;
3724 for (unsigned l = 0; l != NumLanes; ++l) {
3725 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3726 i != (l+1)*NumLaneElts;
3729 int BitI1 = Mask[i+1];
3731 if (!isUndefOrEqual(BitI, j))
3733 if (!isUndefOrEqual(BitI1, j))
3741 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3742 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3744 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3745 unsigned NumElts = VT.getVectorNumElements();
3747 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3748 "Unsupported vector type for unpckh");
3750 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3751 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3754 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3755 // independently on 128-bit lanes.
3756 unsigned NumLanes = VT.getSizeInBits()/128;
3757 unsigned NumLaneElts = NumElts/NumLanes;
3759 for (unsigned l = 0; l != NumLanes; ++l) {
3760 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3761 i != (l+1)*NumLaneElts; i += 2, ++j) {
3763 int BitI1 = Mask[i+1];
3764 if (!isUndefOrEqual(BitI, j))
3766 if (!isUndefOrEqual(BitI1, j))
3773 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3774 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3775 /// MOVSD, and MOVD, i.e. setting the lowest element.
3776 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3777 if (VT.getVectorElementType().getSizeInBits() < 32)
3779 if (!VT.is128BitVector())
3782 unsigned NumElts = VT.getVectorNumElements();
3784 if (!isUndefOrEqual(Mask[0], NumElts))
3787 for (unsigned i = 1; i != NumElts; ++i)
3788 if (!isUndefOrEqual(Mask[i], i))
3794 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3795 /// as permutations between 128-bit chunks or halves. As an example: this
3797 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3798 /// The first half comes from the second half of V1 and the second half from the
3799 /// the second half of V2.
3800 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3801 if (!HasFp256 || !VT.is256BitVector())
3804 // The shuffle result is divided into half A and half B. In total the two
3805 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3806 // B must come from C, D, E or F.
3807 unsigned HalfSize = VT.getVectorNumElements()/2;
3808 bool MatchA = false, MatchB = false;
3810 // Check if A comes from one of C, D, E, F.
3811 for (unsigned Half = 0; Half != 4; ++Half) {
3812 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3818 // Check if B comes from one of C, D, E, F.
3819 for (unsigned Half = 0; Half != 4; ++Half) {
3820 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3826 return MatchA && MatchB;
3829 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3830 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3831 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3832 EVT VT = SVOp->getValueType(0);
3834 unsigned HalfSize = VT.getVectorNumElements()/2;
3836 unsigned FstHalf = 0, SndHalf = 0;
3837 for (unsigned i = 0; i < HalfSize; ++i) {
3838 if (SVOp->getMaskElt(i) > 0) {
3839 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3843 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3844 if (SVOp->getMaskElt(i) > 0) {
3845 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3850 return (FstHalf | (SndHalf << 4));
3853 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3854 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3855 /// Note that VPERMIL mask matching is different depending whether theunderlying
3856 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3857 /// to the same elements of the low, but to the higher half of the source.
3858 /// In VPERMILPD the two lanes could be shuffled independently of each other
3859 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3860 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3864 unsigned NumElts = VT.getVectorNumElements();
3865 // Only match 256-bit with 32/64-bit types
3866 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3869 unsigned NumLanes = VT.getSizeInBits()/128;
3870 unsigned LaneSize = NumElts/NumLanes;
3871 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3872 for (unsigned i = 0; i != LaneSize; ++i) {
3873 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3875 if (NumElts != 8 || l == 0)
3877 // VPERMILPS handling
3880 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3888 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3889 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3890 /// element of vector 2 and the other elements to come from vector 1 in order.
3891 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3892 bool V2IsSplat = false, bool V2IsUndef = false) {
3893 if (!VT.is128BitVector())
3896 unsigned NumOps = VT.getVectorNumElements();
3897 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3900 if (!isUndefOrEqual(Mask[0], 0))
3903 for (unsigned i = 1; i != NumOps; ++i)
3904 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3905 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3906 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3912 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3913 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3914 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3915 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3916 const X86Subtarget *Subtarget) {
3917 if (!Subtarget->hasSSE3())
3920 unsigned NumElems = VT.getVectorNumElements();
3922 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3923 (VT.getSizeInBits() == 256 && NumElems != 8))
3926 // "i+1" is the value the indexed mask element must have
3927 for (unsigned i = 0; i != NumElems; i += 2)
3928 if (!isUndefOrEqual(Mask[i], i+1) ||
3929 !isUndefOrEqual(Mask[i+1], i+1))
3935 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3936 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3937 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3938 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3939 const X86Subtarget *Subtarget) {
3940 if (!Subtarget->hasSSE3())
3943 unsigned NumElems = VT.getVectorNumElements();
3945 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3946 (VT.getSizeInBits() == 256 && NumElems != 8))
3949 // "i" is the value the indexed mask element must have
3950 for (unsigned i = 0; i != NumElems; i += 2)
3951 if (!isUndefOrEqual(Mask[i], i) ||
3952 !isUndefOrEqual(Mask[i+1], i))
3958 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3959 /// specifies a shuffle of elements that is suitable for input to 256-bit
3960 /// version of MOVDDUP.
3961 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3962 if (!HasFp256 || !VT.is256BitVector())
3965 unsigned NumElts = VT.getVectorNumElements();
3969 for (unsigned i = 0; i != NumElts/2; ++i)
3970 if (!isUndefOrEqual(Mask[i], 0))
3972 for (unsigned i = NumElts/2; i != NumElts; ++i)
3973 if (!isUndefOrEqual(Mask[i], NumElts/2))
3978 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3979 /// specifies a shuffle of elements that is suitable for input to 128-bit
3980 /// version of MOVDDUP.
3981 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3982 if (!VT.is128BitVector())
3985 unsigned e = VT.getVectorNumElements() / 2;
3986 for (unsigned i = 0; i != e; ++i)
3987 if (!isUndefOrEqual(Mask[i], i))
3989 for (unsigned i = 0; i != e; ++i)
3990 if (!isUndefOrEqual(Mask[e+i], i))
3995 /// isVEXTRACTF128Index - Return true if the specified
3996 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3997 /// suitable for input to VEXTRACTF128.
3998 bool X86::isVEXTRACTF128Index(SDNode *N) {
3999 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4002 // The index should be aligned on a 128-bit boundary.
4004 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4006 unsigned VL = N->getValueType(0).getVectorNumElements();
4007 unsigned VBits = N->getValueType(0).getSizeInBits();
4008 unsigned ElSize = VBits / VL;
4009 bool Result = (Index * ElSize) % 128 == 0;
4014 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4015 /// operand specifies a subvector insert that is suitable for input to
4017 bool X86::isVINSERTF128Index(SDNode *N) {
4018 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4021 // The index should be aligned on a 128-bit boundary.
4023 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4025 unsigned VL = N->getValueType(0).getVectorNumElements();
4026 unsigned VBits = N->getValueType(0).getSizeInBits();
4027 unsigned ElSize = VBits / VL;
4028 bool Result = (Index * ElSize) % 128 == 0;
4033 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4034 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4035 /// Handles 128-bit and 256-bit.
4036 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4037 EVT VT = N->getValueType(0);
4039 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4040 "Unsupported vector type for PSHUF/SHUFP");
4042 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4043 // independently on 128-bit lanes.
4044 unsigned NumElts = VT.getVectorNumElements();
4045 unsigned NumLanes = VT.getSizeInBits()/128;
4046 unsigned NumLaneElts = NumElts/NumLanes;
4048 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4049 "Only supports 2 or 4 elements per lane");
4051 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4053 for (unsigned i = 0; i != NumElts; ++i) {
4054 int Elt = N->getMaskElt(i);
4055 if (Elt < 0) continue;
4056 Elt &= NumLaneElts - 1;
4057 unsigned ShAmt = (i << Shift) % 8;
4058 Mask |= Elt << ShAmt;
4064 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4065 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4066 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4067 EVT VT = N->getValueType(0);
4069 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4070 "Unsupported vector type for PSHUFHW");
4072 unsigned NumElts = VT.getVectorNumElements();
4075 for (unsigned l = 0; l != NumElts; l += 8) {
4076 // 8 nodes per lane, but we only care about the last 4.
4077 for (unsigned i = 0; i < 4; ++i) {
4078 int Elt = N->getMaskElt(l+i+4);
4079 if (Elt < 0) continue;
4080 Elt &= 0x3; // only 2-bits.
4081 Mask |= Elt << (i * 2);
4088 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4089 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4090 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4091 EVT VT = N->getValueType(0);
4093 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4094 "Unsupported vector type for PSHUFHW");
4096 unsigned NumElts = VT.getVectorNumElements();
4099 for (unsigned l = 0; l != NumElts; l += 8) {
4100 // 8 nodes per lane, but we only care about the first 4.
4101 for (unsigned i = 0; i < 4; ++i) {
4102 int Elt = N->getMaskElt(l+i);
4103 if (Elt < 0) continue;
4104 Elt &= 0x3; // only 2-bits
4105 Mask |= Elt << (i * 2);
4112 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4113 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4114 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4115 EVT VT = SVOp->getValueType(0);
4116 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4118 unsigned NumElts = VT.getVectorNumElements();
4119 unsigned NumLanes = VT.getSizeInBits()/128;
4120 unsigned NumLaneElts = NumElts/NumLanes;
4124 for (i = 0; i != NumElts; ++i) {
4125 Val = SVOp->getMaskElt(i);
4129 if (Val >= (int)NumElts)
4130 Val -= NumElts - NumLaneElts;
4132 assert(Val - i > 0 && "PALIGNR imm should be positive");
4133 return (Val - i) * EltSize;
4136 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4137 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4139 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4140 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4141 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4144 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4146 EVT VecVT = N->getOperand(0).getValueType();
4147 EVT ElVT = VecVT.getVectorElementType();
4149 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4150 return Index / NumElemsPerChunk;
4153 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4154 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4156 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4157 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4158 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4161 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4163 EVT VecVT = N->getValueType(0);
4164 EVT ElVT = VecVT.getVectorElementType();
4166 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4167 return Index / NumElemsPerChunk;
4170 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4171 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4172 /// Handles 256-bit.
4173 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4174 EVT VT = N->getValueType(0);
4176 unsigned NumElts = VT.getVectorNumElements();
4178 assert((VT.is256BitVector() && NumElts == 4) &&
4179 "Unsupported vector type for VPERMQ/VPERMPD");
4182 for (unsigned i = 0; i != NumElts; ++i) {
4183 int Elt = N->getMaskElt(i);
4186 Mask |= Elt << (i*2);
4191 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4193 bool X86::isZeroNode(SDValue Elt) {
4194 return ((isa<ConstantSDNode>(Elt) &&
4195 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4196 (isa<ConstantFPSDNode>(Elt) &&
4197 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4200 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4201 /// their permute mask.
4202 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4203 SelectionDAG &DAG) {
4204 EVT VT = SVOp->getValueType(0);
4205 unsigned NumElems = VT.getVectorNumElements();
4206 SmallVector<int, 8> MaskVec;
4208 for (unsigned i = 0; i != NumElems; ++i) {
4209 int Idx = SVOp->getMaskElt(i);
4211 if (Idx < (int)NumElems)
4216 MaskVec.push_back(Idx);
4218 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4219 SVOp->getOperand(0), &MaskVec[0]);
4222 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4223 /// match movhlps. The lower half elements should come from upper half of
4224 /// V1 (and in order), and the upper half elements should come from the upper
4225 /// half of V2 (and in order).
4226 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4227 if (!VT.is128BitVector())
4229 if (VT.getVectorNumElements() != 4)
4231 for (unsigned i = 0, e = 2; i != e; ++i)
4232 if (!isUndefOrEqual(Mask[i], i+2))
4234 for (unsigned i = 2; i != 4; ++i)
4235 if (!isUndefOrEqual(Mask[i], i+4))
4240 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4241 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4243 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4244 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4246 N = N->getOperand(0).getNode();
4247 if (!ISD::isNON_EXTLoad(N))
4250 *LD = cast<LoadSDNode>(N);
4254 // Test whether the given value is a vector value which will be legalized
4256 static bool WillBeConstantPoolLoad(SDNode *N) {
4257 if (N->getOpcode() != ISD::BUILD_VECTOR)
4260 // Check for any non-constant elements.
4261 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4262 switch (N->getOperand(i).getNode()->getOpcode()) {
4264 case ISD::ConstantFP:
4271 // Vectors of all-zeros and all-ones are materialized with special
4272 // instructions rather than being loaded.
4273 return !ISD::isBuildVectorAllZeros(N) &&
4274 !ISD::isBuildVectorAllOnes(N);
4277 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4278 /// match movlp{s|d}. The lower half elements should come from lower half of
4279 /// V1 (and in order), and the upper half elements should come from the upper
4280 /// half of V2 (and in order). And since V1 will become the source of the
4281 /// MOVLP, it must be either a vector load or a scalar load to vector.
4282 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4283 ArrayRef<int> Mask, EVT VT) {
4284 if (!VT.is128BitVector())
4287 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4289 // Is V2 is a vector load, don't do this transformation. We will try to use
4290 // load folding shufps op.
4291 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4294 unsigned NumElems = VT.getVectorNumElements();
4296 if (NumElems != 2 && NumElems != 4)
4298 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4299 if (!isUndefOrEqual(Mask[i], i))
4301 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4302 if (!isUndefOrEqual(Mask[i], i+NumElems))
4307 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4309 static bool isSplatVector(SDNode *N) {
4310 if (N->getOpcode() != ISD::BUILD_VECTOR)
4313 SDValue SplatValue = N->getOperand(0);
4314 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4315 if (N->getOperand(i) != SplatValue)
4320 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4321 /// to an zero vector.
4322 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4323 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4324 SDValue V1 = N->getOperand(0);
4325 SDValue V2 = N->getOperand(1);
4326 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4327 for (unsigned i = 0; i != NumElems; ++i) {
4328 int Idx = N->getMaskElt(i);
4329 if (Idx >= (int)NumElems) {
4330 unsigned Opc = V2.getOpcode();
4331 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4333 if (Opc != ISD::BUILD_VECTOR ||
4334 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4336 } else if (Idx >= 0) {
4337 unsigned Opc = V1.getOpcode();
4338 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4340 if (Opc != ISD::BUILD_VECTOR ||
4341 !X86::isZeroNode(V1.getOperand(Idx)))
4348 /// getZeroVector - Returns a vector of specified type with all zero elements.
4350 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4351 SelectionDAG &DAG, DebugLoc dl) {
4352 assert(VT.isVector() && "Expected a vector type");
4353 unsigned Size = VT.getSizeInBits();
4355 // Always build SSE zero vectors as <4 x i32> bitcasted
4356 // to their dest type. This ensures they get CSE'd.
4358 if (Size == 128) { // SSE
4359 if (Subtarget->hasSSE2()) { // SSE2
4360 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4361 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4363 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4364 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4366 } else if (Size == 256) { // AVX
4367 if (Subtarget->hasInt256()) { // AVX2
4368 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4369 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4370 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4372 // 256-bit logic and arithmetic instructions in AVX are all
4373 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4374 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4375 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4376 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4379 llvm_unreachable("Unexpected vector type");
4381 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4384 /// getOnesVector - Returns a vector of specified type with all bits set.
4385 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4386 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4387 /// Then bitcast to their original type, ensuring they get CSE'd.
4388 static SDValue getOnesVector(EVT VT, bool HasInt256, SelectionDAG &DAG,
4390 assert(VT.isVector() && "Expected a vector type");
4391 unsigned Size = VT.getSizeInBits();
4393 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4396 if (HasInt256) { // AVX2
4397 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4398 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4400 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4401 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4403 } else if (Size == 128) {
4404 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4406 llvm_unreachable("Unexpected vector type");
4408 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4411 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4412 /// that point to V2 points to its first element.
4413 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4414 for (unsigned i = 0; i != NumElems; ++i) {
4415 if (Mask[i] > (int)NumElems) {
4421 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4422 /// operation of specified width.
4423 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4425 unsigned NumElems = VT.getVectorNumElements();
4426 SmallVector<int, 8> Mask;
4427 Mask.push_back(NumElems);
4428 for (unsigned i = 1; i != NumElems; ++i)
4430 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4433 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4434 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4436 unsigned NumElems = VT.getVectorNumElements();
4437 SmallVector<int, 8> Mask;
4438 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4440 Mask.push_back(i + NumElems);
4442 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4445 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4446 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4448 unsigned NumElems = VT.getVectorNumElements();
4449 SmallVector<int, 8> Mask;
4450 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4451 Mask.push_back(i + Half);
4452 Mask.push_back(i + NumElems + Half);
4454 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4457 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4458 // a generic shuffle instruction because the target has no such instructions.
4459 // Generate shuffles which repeat i16 and i8 several times until they can be
4460 // represented by v4f32 and then be manipulated by target suported shuffles.
4461 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4462 EVT VT = V.getValueType();
4463 int NumElems = VT.getVectorNumElements();
4464 DebugLoc dl = V.getDebugLoc();
4466 while (NumElems > 4) {
4467 if (EltNo < NumElems/2) {
4468 V = getUnpackl(DAG, dl, VT, V, V);
4470 V = getUnpackh(DAG, dl, VT, V, V);
4471 EltNo -= NumElems/2;
4478 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4479 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4480 EVT VT = V.getValueType();
4481 DebugLoc dl = V.getDebugLoc();
4482 unsigned Size = VT.getSizeInBits();
4485 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4486 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4487 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4489 } else if (Size == 256) {
4490 // To use VPERMILPS to splat scalars, the second half of indicies must
4491 // refer to the higher part, which is a duplication of the lower one,
4492 // because VPERMILPS can only handle in-lane permutations.
4493 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4494 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4496 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4497 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4500 llvm_unreachable("Vector size not supported");
4502 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4505 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4506 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4507 EVT SrcVT = SV->getValueType(0);
4508 SDValue V1 = SV->getOperand(0);
4509 DebugLoc dl = SV->getDebugLoc();
4511 int EltNo = SV->getSplatIndex();
4512 int NumElems = SrcVT.getVectorNumElements();
4513 unsigned Size = SrcVT.getSizeInBits();
4515 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4516 "Unknown how to promote splat for type");
4518 // Extract the 128-bit part containing the splat element and update
4519 // the splat element index when it refers to the higher register.
4521 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4522 if (EltNo >= NumElems/2)
4523 EltNo -= NumElems/2;
4526 // All i16 and i8 vector types can't be used directly by a generic shuffle
4527 // instruction because the target has no such instruction. Generate shuffles
4528 // which repeat i16 and i8 several times until they fit in i32, and then can
4529 // be manipulated by target suported shuffles.
4530 EVT EltVT = SrcVT.getVectorElementType();
4531 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4532 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4534 // Recreate the 256-bit vector and place the same 128-bit vector
4535 // into the low and high part. This is necessary because we want
4536 // to use VPERM* to shuffle the vectors
4538 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4541 return getLegalSplat(DAG, V1, EltNo);
4544 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4545 /// vector of zero or undef vector. This produces a shuffle where the low
4546 /// element of V2 is swizzled into the zero/undef vector, landing at element
4547 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4548 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4550 const X86Subtarget *Subtarget,
4551 SelectionDAG &DAG) {
4552 EVT VT = V2.getValueType();
4554 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4555 unsigned NumElems = VT.getVectorNumElements();
4556 SmallVector<int, 16> MaskVec;
4557 for (unsigned i = 0; i != NumElems; ++i)
4558 // If this is the insertion idx, put the low elt of V2 here.
4559 MaskVec.push_back(i == Idx ? NumElems : i);
4560 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4563 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4564 /// target specific opcode. Returns true if the Mask could be calculated.
4565 /// Sets IsUnary to true if only uses one source.
4566 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4567 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4568 unsigned NumElems = VT.getVectorNumElements();
4572 switch(N->getOpcode()) {
4574 ImmN = N->getOperand(N->getNumOperands()-1);
4575 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4577 case X86ISD::UNPCKH:
4578 DecodeUNPCKHMask(VT, Mask);
4580 case X86ISD::UNPCKL:
4581 DecodeUNPCKLMask(VT, Mask);
4583 case X86ISD::MOVHLPS:
4584 DecodeMOVHLPSMask(NumElems, Mask);
4586 case X86ISD::MOVLHPS:
4587 DecodeMOVLHPSMask(NumElems, Mask);
4589 case X86ISD::PSHUFD:
4590 case X86ISD::VPERMILP:
4591 ImmN = N->getOperand(N->getNumOperands()-1);
4592 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4595 case X86ISD::PSHUFHW:
4596 ImmN = N->getOperand(N->getNumOperands()-1);
4597 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4600 case X86ISD::PSHUFLW:
4601 ImmN = N->getOperand(N->getNumOperands()-1);
4602 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4605 case X86ISD::VPERMI:
4606 ImmN = N->getOperand(N->getNumOperands()-1);
4607 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4611 case X86ISD::MOVSD: {
4612 // The index 0 always comes from the first element of the second source,
4613 // this is why MOVSS and MOVSD are used in the first place. The other
4614 // elements come from the other positions of the first source vector
4615 Mask.push_back(NumElems);
4616 for (unsigned i = 1; i != NumElems; ++i) {
4621 case X86ISD::VPERM2X128:
4622 ImmN = N->getOperand(N->getNumOperands()-1);
4623 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4624 if (Mask.empty()) return false;
4626 case X86ISD::MOVDDUP:
4627 case X86ISD::MOVLHPD:
4628 case X86ISD::MOVLPD:
4629 case X86ISD::MOVLPS:
4630 case X86ISD::MOVSHDUP:
4631 case X86ISD::MOVSLDUP:
4632 case X86ISD::PALIGN:
4633 // Not yet implemented
4635 default: llvm_unreachable("unknown target shuffle node");
4641 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4642 /// element of the result of the vector shuffle.
4643 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4646 return SDValue(); // Limit search depth.
4648 SDValue V = SDValue(N, 0);
4649 EVT VT = V.getValueType();
4650 unsigned Opcode = V.getOpcode();
4652 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4653 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4654 int Elt = SV->getMaskElt(Index);
4657 return DAG.getUNDEF(VT.getVectorElementType());
4659 unsigned NumElems = VT.getVectorNumElements();
4660 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4661 : SV->getOperand(1);
4662 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4665 // Recurse into target specific vector shuffles to find scalars.
4666 if (isTargetShuffle(Opcode)) {
4667 MVT ShufVT = V.getValueType().getSimpleVT();
4668 unsigned NumElems = ShufVT.getVectorNumElements();
4669 SmallVector<int, 16> ShuffleMask;
4672 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4675 int Elt = ShuffleMask[Index];
4677 return DAG.getUNDEF(ShufVT.getVectorElementType());
4679 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4681 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4685 // Actual nodes that may contain scalar elements
4686 if (Opcode == ISD::BITCAST) {
4687 V = V.getOperand(0);
4688 EVT SrcVT = V.getValueType();
4689 unsigned NumElems = VT.getVectorNumElements();
4691 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4695 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4696 return (Index == 0) ? V.getOperand(0)
4697 : DAG.getUNDEF(VT.getVectorElementType());
4699 if (V.getOpcode() == ISD::BUILD_VECTOR)
4700 return V.getOperand(Index);
4705 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4706 /// shuffle operation which come from a consecutively from a zero. The
4707 /// search can start in two different directions, from left or right.
4709 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4710 bool ZerosFromLeft, SelectionDAG &DAG) {
4712 for (i = 0; i != NumElems; ++i) {
4713 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4714 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4715 if (!(Elt.getNode() &&
4716 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4723 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4724 /// correspond consecutively to elements from one of the vector operands,
4725 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4727 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4728 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4729 unsigned NumElems, unsigned &OpNum) {
4730 bool SeenV1 = false;
4731 bool SeenV2 = false;
4733 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4734 int Idx = SVOp->getMaskElt(i);
4735 // Ignore undef indicies
4739 if (Idx < (int)NumElems)
4744 // Only accept consecutive elements from the same vector
4745 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4749 OpNum = SeenV1 ? 0 : 1;
4753 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4754 /// logical left shift of a vector.
4755 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4756 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4757 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4758 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4759 false /* check zeros from right */, DAG);
4765 // Considering the elements in the mask that are not consecutive zeros,
4766 // check if they consecutively come from only one of the source vectors.
4768 // V1 = {X, A, B, C} 0
4770 // vector_shuffle V1, V2 <1, 2, 3, X>
4772 if (!isShuffleMaskConsecutive(SVOp,
4773 0, // Mask Start Index
4774 NumElems-NumZeros, // Mask End Index(exclusive)
4775 NumZeros, // Where to start looking in the src vector
4776 NumElems, // Number of elements in vector
4777 OpSrc)) // Which source operand ?
4782 ShVal = SVOp->getOperand(OpSrc);
4786 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4787 /// logical left shift of a vector.
4788 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4789 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4790 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4791 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4792 true /* check zeros from left */, DAG);
4798 // Considering the elements in the mask that are not consecutive zeros,
4799 // check if they consecutively come from only one of the source vectors.
4801 // 0 { A, B, X, X } = V2
4803 // vector_shuffle V1, V2 <X, X, 4, 5>
4805 if (!isShuffleMaskConsecutive(SVOp,
4806 NumZeros, // Mask Start Index
4807 NumElems, // Mask End Index(exclusive)
4808 0, // Where to start looking in the src vector
4809 NumElems, // Number of elements in vector
4810 OpSrc)) // Which source operand ?
4815 ShVal = SVOp->getOperand(OpSrc);
4819 /// isVectorShift - Returns true if the shuffle can be implemented as a
4820 /// logical left or right shift of a vector.
4821 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4822 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4823 // Although the logic below support any bitwidth size, there are no
4824 // shift instructions which handle more than 128-bit vectors.
4825 if (!SVOp->getValueType(0).is128BitVector())
4828 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4829 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4835 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4837 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4838 unsigned NumNonZero, unsigned NumZero,
4840 const X86Subtarget* Subtarget,
4841 const TargetLowering &TLI) {
4845 DebugLoc dl = Op.getDebugLoc();
4848 for (unsigned i = 0; i < 16; ++i) {
4849 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4850 if (ThisIsNonZero && First) {
4852 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4854 V = DAG.getUNDEF(MVT::v8i16);
4859 SDValue ThisElt(0, 0), LastElt(0, 0);
4860 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4861 if (LastIsNonZero) {
4862 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4863 MVT::i16, Op.getOperand(i-1));
4865 if (ThisIsNonZero) {
4866 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4867 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4868 ThisElt, DAG.getConstant(8, MVT::i8));
4870 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4874 if (ThisElt.getNode())
4875 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4876 DAG.getIntPtrConstant(i/2));
4880 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4883 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4885 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4886 unsigned NumNonZero, unsigned NumZero,
4888 const X86Subtarget* Subtarget,
4889 const TargetLowering &TLI) {
4893 DebugLoc dl = Op.getDebugLoc();
4896 for (unsigned i = 0; i < 8; ++i) {
4897 bool isNonZero = (NonZeros & (1 << i)) != 0;
4901 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4903 V = DAG.getUNDEF(MVT::v8i16);
4906 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4907 MVT::v8i16, V, Op.getOperand(i),
4908 DAG.getIntPtrConstant(i));
4915 /// getVShift - Return a vector logical shift node.
4917 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4918 unsigned NumBits, SelectionDAG &DAG,
4919 const TargetLowering &TLI, DebugLoc dl) {
4920 assert(VT.is128BitVector() && "Unknown type for VShift");
4921 EVT ShVT = MVT::v2i64;
4922 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4923 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4924 return DAG.getNode(ISD::BITCAST, dl, VT,
4925 DAG.getNode(Opc, dl, ShVT, SrcOp,
4926 DAG.getConstant(NumBits,
4927 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4931 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4932 SelectionDAG &DAG) const {
4934 // Check if the scalar load can be widened into a vector load. And if
4935 // the address is "base + cst" see if the cst can be "absorbed" into
4936 // the shuffle mask.
4937 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4938 SDValue Ptr = LD->getBasePtr();
4939 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4941 EVT PVT = LD->getValueType(0);
4942 if (PVT != MVT::i32 && PVT != MVT::f32)
4947 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4948 FI = FINode->getIndex();
4950 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4951 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4952 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4953 Offset = Ptr.getConstantOperandVal(1);
4954 Ptr = Ptr.getOperand(0);
4959 // FIXME: 256-bit vector instructions don't require a strict alignment,
4960 // improve this code to support it better.
4961 unsigned RequiredAlign = VT.getSizeInBits()/8;
4962 SDValue Chain = LD->getChain();
4963 // Make sure the stack object alignment is at least 16 or 32.
4964 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4965 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4966 if (MFI->isFixedObjectIndex(FI)) {
4967 // Can't change the alignment. FIXME: It's possible to compute
4968 // the exact stack offset and reference FI + adjust offset instead.
4969 // If someone *really* cares about this. That's the way to implement it.
4972 MFI->setObjectAlignment(FI, RequiredAlign);
4976 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4977 // Ptr + (Offset & ~15).
4980 if ((Offset % RequiredAlign) & 3)
4982 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4984 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4985 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4987 int EltNo = (Offset - StartOffset) >> 2;
4988 unsigned NumElems = VT.getVectorNumElements();
4990 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4991 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4992 LD->getPointerInfo().getWithOffset(StartOffset),
4993 false, false, false, 0);
4995 SmallVector<int, 8> Mask;
4996 for (unsigned i = 0; i != NumElems; ++i)
4997 Mask.push_back(EltNo);
4999 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5005 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5006 /// vector of type 'VT', see if the elements can be replaced by a single large
5007 /// load which has the same value as a build_vector whose operands are 'elts'.
5009 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5011 /// FIXME: we'd also like to handle the case where the last elements are zero
5012 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5013 /// There's even a handy isZeroNode for that purpose.
5014 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5015 DebugLoc &DL, SelectionDAG &DAG) {
5016 EVT EltVT = VT.getVectorElementType();
5017 unsigned NumElems = Elts.size();
5019 LoadSDNode *LDBase = NULL;
5020 unsigned LastLoadedElt = -1U;
5022 // For each element in the initializer, see if we've found a load or an undef.
5023 // If we don't find an initial load element, or later load elements are
5024 // non-consecutive, bail out.
5025 for (unsigned i = 0; i < NumElems; ++i) {
5026 SDValue Elt = Elts[i];
5028 if (!Elt.getNode() ||
5029 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5032 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5034 LDBase = cast<LoadSDNode>(Elt.getNode());
5038 if (Elt.getOpcode() == ISD::UNDEF)
5041 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5042 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5047 // If we have found an entire vector of loads and undefs, then return a large
5048 // load of the entire vector width starting at the base pointer. If we found
5049 // consecutive loads for the low half, generate a vzext_load node.
5050 if (LastLoadedElt == NumElems - 1) {
5051 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5052 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5053 LDBase->getPointerInfo(),
5054 LDBase->isVolatile(), LDBase->isNonTemporal(),
5055 LDBase->isInvariant(), 0);
5056 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5057 LDBase->getPointerInfo(),
5058 LDBase->isVolatile(), LDBase->isNonTemporal(),
5059 LDBase->isInvariant(), LDBase->getAlignment());
5061 if (NumElems == 4 && LastLoadedElt == 1 &&
5062 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5063 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5064 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5066 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5067 LDBase->getPointerInfo(),
5068 LDBase->getAlignment(),
5069 false/*isVolatile*/, true/*ReadMem*/,
5072 // Make sure the newly-created LOAD is in the same position as LDBase in
5073 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5074 // update uses of LDBase's output chain to use the TokenFactor.
5075 if (LDBase->hasAnyUseOfValue(1)) {
5076 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5077 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5078 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5079 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5080 SDValue(ResNode.getNode(), 1));
5083 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5088 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5089 /// to generate a splat value for the following cases:
5090 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5091 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5092 /// a scalar load, or a constant.
5093 /// The VBROADCAST node is returned when a pattern is found,
5094 /// or SDValue() otherwise.
5096 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5097 if (!Subtarget->hasFp256())
5100 EVT VT = Op.getValueType();
5101 DebugLoc dl = Op.getDebugLoc();
5103 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5104 "Unsupported vector type for broadcast.");
5109 switch (Op.getOpcode()) {
5111 // Unknown pattern found.
5114 case ISD::BUILD_VECTOR: {
5115 // The BUILD_VECTOR node must be a splat.
5116 if (!isSplatVector(Op.getNode()))
5119 Ld = Op.getOperand(0);
5120 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5121 Ld.getOpcode() == ISD::ConstantFP);
5123 // The suspected load node has several users. Make sure that all
5124 // of its users are from the BUILD_VECTOR node.
5125 // Constants may have multiple users.
5126 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5131 case ISD::VECTOR_SHUFFLE: {
5132 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5134 // Shuffles must have a splat mask where the first element is
5136 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5139 SDValue Sc = Op.getOperand(0);
5140 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5141 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5143 if (!Subtarget->hasInt256())
5146 // Use the register form of the broadcast instruction available on AVX2.
5147 if (VT.is256BitVector())
5148 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5152 Ld = Sc.getOperand(0);
5153 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5154 Ld.getOpcode() == ISD::ConstantFP);
5156 // The scalar_to_vector node and the suspected
5157 // load node must have exactly one user.
5158 // Constants may have multiple users.
5159 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5165 bool Is256 = VT.is256BitVector();
5167 // Handle the broadcasting a single constant scalar from the constant pool
5168 // into a vector. On Sandybridge it is still better to load a constant vector
5169 // from the constant pool and not to broadcast it from a scalar.
5170 if (ConstSplatVal && Subtarget->hasInt256()) {
5171 EVT CVT = Ld.getValueType();
5172 assert(!CVT.isVector() && "Must not broadcast a vector type");
5173 unsigned ScalarSize = CVT.getSizeInBits();
5175 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5176 const Constant *C = 0;
5177 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5178 C = CI->getConstantIntValue();
5179 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5180 C = CF->getConstantFPValue();
5182 assert(C && "Invalid constant type");
5184 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5185 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5186 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5187 MachinePointerInfo::getConstantPool(),
5188 false, false, false, Alignment);
5190 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5194 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5195 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5197 // Handle AVX2 in-register broadcasts.
5198 if (!IsLoad && Subtarget->hasInt256() &&
5199 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5200 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5202 // The scalar source must be a normal load.
5206 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5207 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5209 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5210 // double since there is no vbroadcastsd xmm
5211 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5212 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5213 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5216 // Unsupported broadcast.
5221 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5222 EVT VT = Op.getValueType();
5224 // Skip if insert_vec_elt is not supported.
5225 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5228 DebugLoc DL = Op.getDebugLoc();
5229 unsigned NumElems = Op.getNumOperands();
5233 SmallVector<unsigned, 4> InsertIndices;
5234 SmallVector<int, 8> Mask(NumElems, -1);
5236 for (unsigned i = 0; i != NumElems; ++i) {
5237 unsigned Opc = Op.getOperand(i).getOpcode();
5239 if (Opc == ISD::UNDEF)
5242 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5243 // Quit if more than 1 elements need inserting.
5244 if (InsertIndices.size() > 1)
5247 InsertIndices.push_back(i);
5251 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5252 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5254 // Quit if extracted from vector of different type.
5255 if (ExtractedFromVec.getValueType() != VT)
5258 // Quit if non-constant index.
5259 if (!isa<ConstantSDNode>(ExtIdx))
5262 if (VecIn1.getNode() == 0)
5263 VecIn1 = ExtractedFromVec;
5264 else if (VecIn1 != ExtractedFromVec) {
5265 if (VecIn2.getNode() == 0)
5266 VecIn2 = ExtractedFromVec;
5267 else if (VecIn2 != ExtractedFromVec)
5268 // Quit if more than 2 vectors to shuffle
5272 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5274 if (ExtractedFromVec == VecIn1)
5276 else if (ExtractedFromVec == VecIn2)
5277 Mask[i] = Idx + NumElems;
5280 if (VecIn1.getNode() == 0)
5283 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5284 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5285 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5286 unsigned Idx = InsertIndices[i];
5287 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5288 DAG.getIntPtrConstant(Idx));
5295 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5296 DebugLoc dl = Op.getDebugLoc();
5298 EVT VT = Op.getValueType();
5299 EVT ExtVT = VT.getVectorElementType();
5300 unsigned NumElems = Op.getNumOperands();
5302 // Vectors containing all zeros can be matched by pxor and xorps later
5303 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5304 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5305 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5306 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5309 return getZeroVector(VT, Subtarget, DAG, dl);
5312 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5313 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5314 // vpcmpeqd on 256-bit vectors.
5315 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5316 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5319 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5322 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5323 if (Broadcast.getNode())
5326 unsigned EVTBits = ExtVT.getSizeInBits();
5328 unsigned NumZero = 0;
5329 unsigned NumNonZero = 0;
5330 unsigned NonZeros = 0;
5331 bool IsAllConstants = true;
5332 SmallSet<SDValue, 8> Values;
5333 for (unsigned i = 0; i < NumElems; ++i) {
5334 SDValue Elt = Op.getOperand(i);
5335 if (Elt.getOpcode() == ISD::UNDEF)
5338 if (Elt.getOpcode() != ISD::Constant &&
5339 Elt.getOpcode() != ISD::ConstantFP)
5340 IsAllConstants = false;
5341 if (X86::isZeroNode(Elt))
5344 NonZeros |= (1 << i);
5349 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5350 if (NumNonZero == 0)
5351 return DAG.getUNDEF(VT);
5353 // Special case for single non-zero, non-undef, element.
5354 if (NumNonZero == 1) {
5355 unsigned Idx = CountTrailingZeros_32(NonZeros);
5356 SDValue Item = Op.getOperand(Idx);
5358 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5359 // the value are obviously zero, truncate the value to i32 and do the
5360 // insertion that way. Only do this if the value is non-constant or if the
5361 // value is a constant being inserted into element 0. It is cheaper to do
5362 // a constant pool load than it is to do a movd + shuffle.
5363 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5364 (!IsAllConstants || Idx == 0)) {
5365 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5367 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5368 EVT VecVT = MVT::v4i32;
5369 unsigned VecElts = 4;
5371 // Truncate the value (which may itself be a constant) to i32, and
5372 // convert it to a vector with movd (S2V+shuffle to zero extend).
5373 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5374 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5375 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5377 // Now we have our 32-bit value zero extended in the low element of
5378 // a vector. If Idx != 0, swizzle it into place.
5380 SmallVector<int, 4> Mask;
5381 Mask.push_back(Idx);
5382 for (unsigned i = 1; i != VecElts; ++i)
5384 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5387 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5391 // If we have a constant or non-constant insertion into the low element of
5392 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5393 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5394 // depending on what the source datatype is.
5397 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5399 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5400 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5401 if (VT.is256BitVector()) {
5402 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5403 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5404 Item, DAG.getIntPtrConstant(0));
5406 assert(VT.is128BitVector() && "Expected an SSE value type!");
5407 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5408 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5409 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5412 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5413 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5414 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5415 if (VT.is256BitVector()) {
5416 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5417 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5419 assert(VT.is128BitVector() && "Expected an SSE value type!");
5420 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5422 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5426 // Is it a vector logical left shift?
5427 if (NumElems == 2 && Idx == 1 &&
5428 X86::isZeroNode(Op.getOperand(0)) &&
5429 !X86::isZeroNode(Op.getOperand(1))) {
5430 unsigned NumBits = VT.getSizeInBits();
5431 return getVShift(true, VT,
5432 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5433 VT, Op.getOperand(1)),
5434 NumBits/2, DAG, *this, dl);
5437 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5440 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5441 // is a non-constant being inserted into an element other than the low one,
5442 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5443 // movd/movss) to move this into the low element, then shuffle it into
5445 if (EVTBits == 32) {
5446 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5448 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5449 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5450 SmallVector<int, 8> MaskVec;
5451 for (unsigned i = 0; i != NumElems; ++i)
5452 MaskVec.push_back(i == Idx ? 0 : 1);
5453 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5457 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5458 if (Values.size() == 1) {
5459 if (EVTBits == 32) {
5460 // Instead of a shuffle like this:
5461 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5462 // Check if it's possible to issue this instead.
5463 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5464 unsigned Idx = CountTrailingZeros_32(NonZeros);
5465 SDValue Item = Op.getOperand(Idx);
5466 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5467 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5472 // A vector full of immediates; various special cases are already
5473 // handled, so this is best done with a single constant-pool load.
5477 // For AVX-length vectors, build the individual 128-bit pieces and use
5478 // shuffles to put them in place.
5479 if (VT.is256BitVector()) {
5480 SmallVector<SDValue, 32> V;
5481 for (unsigned i = 0; i != NumElems; ++i)
5482 V.push_back(Op.getOperand(i));
5484 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5486 // Build both the lower and upper subvector.
5487 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5488 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5491 // Recreate the wider vector with the lower and upper part.
5492 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5495 // Let legalizer expand 2-wide build_vectors.
5496 if (EVTBits == 64) {
5497 if (NumNonZero == 1) {
5498 // One half is zero or undef.
5499 unsigned Idx = CountTrailingZeros_32(NonZeros);
5500 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5501 Op.getOperand(Idx));
5502 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5507 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5508 if (EVTBits == 8 && NumElems == 16) {
5509 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5511 if (V.getNode()) return V;
5514 if (EVTBits == 16 && NumElems == 8) {
5515 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5517 if (V.getNode()) return V;
5520 // If element VT is == 32 bits, turn it into a number of shuffles.
5521 SmallVector<SDValue, 8> V(NumElems);
5522 if (NumElems == 4 && NumZero > 0) {
5523 for (unsigned i = 0; i < 4; ++i) {
5524 bool isZero = !(NonZeros & (1 << i));
5526 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5528 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5531 for (unsigned i = 0; i < 2; ++i) {
5532 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5535 V[i] = V[i*2]; // Must be a zero vector.
5538 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5541 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5544 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5549 bool Reverse1 = (NonZeros & 0x3) == 2;
5550 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5554 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5555 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5557 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5560 if (Values.size() > 1 && VT.is128BitVector()) {
5561 // Check for a build vector of consecutive loads.
5562 for (unsigned i = 0; i < NumElems; ++i)
5563 V[i] = Op.getOperand(i);
5565 // Check for elements which are consecutive loads.
5566 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5570 // Check for a build vector from mostly shuffle plus few inserting.
5571 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5575 // For SSE 4.1, use insertps to put the high elements into the low element.
5576 if (getSubtarget()->hasSSE41()) {
5578 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5579 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5581 Result = DAG.getUNDEF(VT);
5583 for (unsigned i = 1; i < NumElems; ++i) {
5584 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5585 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5586 Op.getOperand(i), DAG.getIntPtrConstant(i));
5591 // Otherwise, expand into a number of unpckl*, start by extending each of
5592 // our (non-undef) elements to the full vector width with the element in the
5593 // bottom slot of the vector (which generates no code for SSE).
5594 for (unsigned i = 0; i < NumElems; ++i) {
5595 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5596 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5598 V[i] = DAG.getUNDEF(VT);
5601 // Next, we iteratively mix elements, e.g. for v4f32:
5602 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5603 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5604 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5605 unsigned EltStride = NumElems >> 1;
5606 while (EltStride != 0) {
5607 for (unsigned i = 0; i < EltStride; ++i) {
5608 // If V[i+EltStride] is undef and this is the first round of mixing,
5609 // then it is safe to just drop this shuffle: V[i] is already in the
5610 // right place, the one element (since it's the first round) being
5611 // inserted as undef can be dropped. This isn't safe for successive
5612 // rounds because they will permute elements within both vectors.
5613 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5614 EltStride == NumElems/2)
5617 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5626 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5627 // to create 256-bit vectors from two other 128-bit ones.
5628 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5629 DebugLoc dl = Op.getDebugLoc();
5630 EVT ResVT = Op.getValueType();
5632 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5634 SDValue V1 = Op.getOperand(0);
5635 SDValue V2 = Op.getOperand(1);
5636 unsigned NumElems = ResVT.getVectorNumElements();
5638 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5641 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5642 assert(Op.getNumOperands() == 2);
5644 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5645 // from two other 128-bit ones.
5646 return LowerAVXCONCAT_VECTORS(Op, DAG);
5649 // Try to lower a shuffle node into a simple blend instruction.
5651 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5652 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5653 SDValue V1 = SVOp->getOperand(0);
5654 SDValue V2 = SVOp->getOperand(1);
5655 DebugLoc dl = SVOp->getDebugLoc();
5656 EVT VT = SVOp->getValueType(0);
5657 EVT EltVT = VT.getVectorElementType();
5658 unsigned NumElems = VT.getVectorNumElements();
5660 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5662 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5665 // Check the mask for BLEND and build the value.
5666 unsigned MaskValue = 0;
5667 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5668 unsigned NumLanes = (NumElems-1)/8 + 1;
5669 unsigned NumElemsInLane = NumElems / NumLanes;
5671 // Blend for v16i16 should be symetric for the both lanes.
5672 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5674 int SndLaneEltIdx = (NumLanes == 2) ?
5675 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5676 int EltIdx = SVOp->getMaskElt(i);
5678 if ((EltIdx == -1 || EltIdx == (int)i) &&
5679 (SndLaneEltIdx == -1 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5682 if (((unsigned)EltIdx == (i + NumElems)) &&
5683 (SndLaneEltIdx == -1 ||
5684 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
5685 MaskValue |= (1<<i);
5690 // Convert i32 vectors to floating point if it is not AVX2.
5691 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
5693 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
5694 BlendVT = EVT::getVectorVT(*DAG.getContext(),
5695 EVT::getFloatingPointVT(EltVT.getSizeInBits()),
5697 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5698 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5701 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
5702 DAG.getConstant(MaskValue, MVT::i32));
5703 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5706 // v8i16 shuffles - Prefer shuffles in the following order:
5707 // 1. [all] pshuflw, pshufhw, optional move
5708 // 2. [ssse3] 1 x pshufb
5709 // 3. [ssse3] 2 x pshufb + 1 x por
5710 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5712 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
5713 SelectionDAG &DAG) {
5714 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5715 SDValue V1 = SVOp->getOperand(0);
5716 SDValue V2 = SVOp->getOperand(1);
5717 DebugLoc dl = SVOp->getDebugLoc();
5718 SmallVector<int, 8> MaskVals;
5720 // Determine if more than 1 of the words in each of the low and high quadwords
5721 // of the result come from the same quadword of one of the two inputs. Undef
5722 // mask values count as coming from any quadword, for better codegen.
5723 unsigned LoQuad[] = { 0, 0, 0, 0 };
5724 unsigned HiQuad[] = { 0, 0, 0, 0 };
5725 std::bitset<4> InputQuads;
5726 for (unsigned i = 0; i < 8; ++i) {
5727 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5728 int EltIdx = SVOp->getMaskElt(i);
5729 MaskVals.push_back(EltIdx);
5738 InputQuads.set(EltIdx / 4);
5741 int BestLoQuad = -1;
5742 unsigned MaxQuad = 1;
5743 for (unsigned i = 0; i < 4; ++i) {
5744 if (LoQuad[i] > MaxQuad) {
5746 MaxQuad = LoQuad[i];
5750 int BestHiQuad = -1;
5752 for (unsigned i = 0; i < 4; ++i) {
5753 if (HiQuad[i] > MaxQuad) {
5755 MaxQuad = HiQuad[i];
5759 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5760 // of the two input vectors, shuffle them into one input vector so only a
5761 // single pshufb instruction is necessary. If There are more than 2 input
5762 // quads, disable the next transformation since it does not help SSSE3.
5763 bool V1Used = InputQuads[0] || InputQuads[1];
5764 bool V2Used = InputQuads[2] || InputQuads[3];
5765 if (Subtarget->hasSSSE3()) {
5766 if (InputQuads.count() == 2 && V1Used && V2Used) {
5767 BestLoQuad = InputQuads[0] ? 0 : 1;
5768 BestHiQuad = InputQuads[2] ? 2 : 3;
5770 if (InputQuads.count() > 2) {
5776 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5777 // the shuffle mask. If a quad is scored as -1, that means that it contains
5778 // words from all 4 input quadwords.
5780 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5782 BestLoQuad < 0 ? 0 : BestLoQuad,
5783 BestHiQuad < 0 ? 1 : BestHiQuad
5785 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5786 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5787 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5788 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5790 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5791 // source words for the shuffle, to aid later transformations.
5792 bool AllWordsInNewV = true;
5793 bool InOrder[2] = { true, true };
5794 for (unsigned i = 0; i != 8; ++i) {
5795 int idx = MaskVals[i];
5797 InOrder[i/4] = false;
5798 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5800 AllWordsInNewV = false;
5804 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5805 if (AllWordsInNewV) {
5806 for (int i = 0; i != 8; ++i) {
5807 int idx = MaskVals[i];
5810 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5811 if ((idx != i) && idx < 4)
5813 if ((idx != i) && idx > 3)
5822 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5823 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5824 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5825 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5826 unsigned TargetMask = 0;
5827 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5828 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5830 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5831 getShufflePSHUFLWImmediate(SVOp);
5832 V1 = NewV.getOperand(0);
5833 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5837 // If we have SSSE3, and all words of the result are from 1 input vector,
5838 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5839 // is present, fall back to case 4.
5840 if (Subtarget->hasSSSE3()) {
5841 SmallVector<SDValue,16> pshufbMask;
5843 // If we have elements from both input vectors, set the high bit of the
5844 // shuffle mask element to zero out elements that come from V2 in the V1
5845 // mask, and elements that come from V1 in the V2 mask, so that the two
5846 // results can be OR'd together.
5847 bool TwoInputs = V1Used && V2Used;
5848 for (unsigned i = 0; i != 8; ++i) {
5849 int EltIdx = MaskVals[i] * 2;
5850 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5851 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5852 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5853 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5855 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5856 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5857 DAG.getNode(ISD::BUILD_VECTOR, dl,
5858 MVT::v16i8, &pshufbMask[0], 16));
5860 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5862 // Calculate the shuffle mask for the second input, shuffle it, and
5863 // OR it with the first shuffled input.
5865 for (unsigned i = 0; i != 8; ++i) {
5866 int EltIdx = MaskVals[i] * 2;
5867 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5868 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5869 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5870 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5872 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5873 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5874 DAG.getNode(ISD::BUILD_VECTOR, dl,
5875 MVT::v16i8, &pshufbMask[0], 16));
5876 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5877 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5880 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5881 // and update MaskVals with new element order.
5882 std::bitset<8> InOrder;
5883 if (BestLoQuad >= 0) {
5884 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5885 for (int i = 0; i != 4; ++i) {
5886 int idx = MaskVals[i];
5889 } else if ((idx / 4) == BestLoQuad) {
5894 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5897 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5898 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5899 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5901 getShufflePSHUFLWImmediate(SVOp), DAG);
5905 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5906 // and update MaskVals with the new element order.
5907 if (BestHiQuad >= 0) {
5908 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5909 for (unsigned i = 4; i != 8; ++i) {
5910 int idx = MaskVals[i];
5913 } else if ((idx / 4) == BestHiQuad) {
5914 MaskV[i] = (idx & 3) + 4;
5918 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5921 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5923 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5925 getShufflePSHUFHWImmediate(SVOp), DAG);
5929 // In case BestHi & BestLo were both -1, which means each quadword has a word
5930 // from each of the four input quadwords, calculate the InOrder bitvector now
5931 // before falling through to the insert/extract cleanup.
5932 if (BestLoQuad == -1 && BestHiQuad == -1) {
5934 for (int i = 0; i != 8; ++i)
5935 if (MaskVals[i] < 0 || MaskVals[i] == i)
5939 // The other elements are put in the right place using pextrw and pinsrw.
5940 for (unsigned i = 0; i != 8; ++i) {
5943 int EltIdx = MaskVals[i];
5946 SDValue ExtOp = (EltIdx < 8) ?
5947 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5948 DAG.getIntPtrConstant(EltIdx)) :
5949 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5950 DAG.getIntPtrConstant(EltIdx - 8));
5951 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5952 DAG.getIntPtrConstant(i));
5957 // v16i8 shuffles - Prefer shuffles in the following order:
5958 // 1. [ssse3] 1 x pshufb
5959 // 2. [ssse3] 2 x pshufb + 1 x por
5960 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5962 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5964 const X86TargetLowering &TLI) {
5965 SDValue V1 = SVOp->getOperand(0);
5966 SDValue V2 = SVOp->getOperand(1);
5967 DebugLoc dl = SVOp->getDebugLoc();
5968 ArrayRef<int> MaskVals = SVOp->getMask();
5970 // If we have SSSE3, case 1 is generated when all result bytes come from
5971 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5972 // present, fall back to case 3.
5974 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5975 if (TLI.getSubtarget()->hasSSSE3()) {
5976 SmallVector<SDValue,16> pshufbMask;
5978 // If all result elements are from one input vector, then only translate
5979 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5981 // Otherwise, we have elements from both input vectors, and must zero out
5982 // elements that come from V2 in the first mask, and V1 in the second mask
5983 // so that we can OR them together.
5984 for (unsigned i = 0; i != 16; ++i) {
5985 int EltIdx = MaskVals[i];
5986 if (EltIdx < 0 || EltIdx >= 16)
5988 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5990 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5991 DAG.getNode(ISD::BUILD_VECTOR, dl,
5992 MVT::v16i8, &pshufbMask[0], 16));
5994 // As PSHUFB will zero elements with negative indices, it's safe to ignore
5995 // the 2nd operand if it's undefined or zero.
5996 if (V2.getOpcode() == ISD::UNDEF ||
5997 ISD::isBuildVectorAllZeros(V2.getNode()))
6000 // Calculate the shuffle mask for the second input, shuffle it, and
6001 // OR it with the first shuffled input.
6003 for (unsigned i = 0; i != 16; ++i) {
6004 int EltIdx = MaskVals[i];
6005 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6006 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6008 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6009 DAG.getNode(ISD::BUILD_VECTOR, dl,
6010 MVT::v16i8, &pshufbMask[0], 16));
6011 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6014 // No SSSE3 - Calculate in place words and then fix all out of place words
6015 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6016 // the 16 different words that comprise the two doublequadword input vectors.
6017 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6018 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6020 for (int i = 0; i != 8; ++i) {
6021 int Elt0 = MaskVals[i*2];
6022 int Elt1 = MaskVals[i*2+1];
6024 // This word of the result is all undef, skip it.
6025 if (Elt0 < 0 && Elt1 < 0)
6028 // This word of the result is already in the correct place, skip it.
6029 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6032 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6033 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6036 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6037 // using a single extract together, load it and store it.
6038 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6039 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6040 DAG.getIntPtrConstant(Elt1 / 2));
6041 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6042 DAG.getIntPtrConstant(i));
6046 // If Elt1 is defined, extract it from the appropriate source. If the
6047 // source byte is not also odd, shift the extracted word left 8 bits
6048 // otherwise clear the bottom 8 bits if we need to do an or.
6050 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6051 DAG.getIntPtrConstant(Elt1 / 2));
6052 if ((Elt1 & 1) == 0)
6053 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6055 TLI.getShiftAmountTy(InsElt.getValueType())));
6057 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6058 DAG.getConstant(0xFF00, MVT::i16));
6060 // If Elt0 is defined, extract it from the appropriate source. If the
6061 // source byte is not also even, shift the extracted word right 8 bits. If
6062 // Elt1 was also defined, OR the extracted values together before
6063 // inserting them in the result.
6065 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6066 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6067 if ((Elt0 & 1) != 0)
6068 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6070 TLI.getShiftAmountTy(InsElt0.getValueType())));
6072 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6073 DAG.getConstant(0x00FF, MVT::i16));
6074 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6077 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6078 DAG.getIntPtrConstant(i));
6080 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6083 // v32i8 shuffles - Translate to VPSHUFB if possible.
6085 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6086 const X86Subtarget *Subtarget,
6087 SelectionDAG &DAG) {
6088 EVT VT = SVOp->getValueType(0);
6089 SDValue V1 = SVOp->getOperand(0);
6090 SDValue V2 = SVOp->getOperand(1);
6091 DebugLoc dl = SVOp->getDebugLoc();
6092 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6094 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6095 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6096 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6098 // VPSHUFB may be generated if
6099 // (1) one of input vector is undefined or zeroinitializer.
6100 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6101 // And (2) the mask indexes don't cross the 128-bit lane.
6102 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6103 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6106 if (V1IsAllZero && !V2IsAllZero) {
6107 CommuteVectorShuffleMask(MaskVals, 32);
6110 SmallVector<SDValue, 32> pshufbMask;
6111 for (unsigned i = 0; i != 32; i++) {
6112 int EltIdx = MaskVals[i];
6113 if (EltIdx < 0 || EltIdx >= 32)
6116 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6117 // Cross lane is not allowed.
6121 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6123 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6124 DAG.getNode(ISD::BUILD_VECTOR, dl,
6125 MVT::v32i8, &pshufbMask[0], 32));
6128 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6129 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6130 /// done when every pair / quad of shuffle mask elements point to elements in
6131 /// the right sequence. e.g.
6132 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6134 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6135 SelectionDAG &DAG, DebugLoc dl) {
6136 MVT VT = SVOp->getValueType(0).getSimpleVT();
6137 unsigned NumElems = VT.getVectorNumElements();
6140 switch (VT.SimpleTy) {
6141 default: llvm_unreachable("Unexpected!");
6142 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6143 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6144 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6145 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6146 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6147 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6150 SmallVector<int, 8> MaskVec;
6151 for (unsigned i = 0; i != NumElems; i += Scale) {
6153 for (unsigned j = 0; j != Scale; ++j) {
6154 int EltIdx = SVOp->getMaskElt(i+j);
6158 StartIdx = (EltIdx / Scale);
6159 if (EltIdx != (int)(StartIdx*Scale + j))
6162 MaskVec.push_back(StartIdx);
6165 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6166 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6167 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6170 /// getVZextMovL - Return a zero-extending vector move low node.
6172 static SDValue getVZextMovL(EVT VT, EVT OpVT,
6173 SDValue SrcOp, SelectionDAG &DAG,
6174 const X86Subtarget *Subtarget, DebugLoc dl) {
6175 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6176 LoadSDNode *LD = NULL;
6177 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6178 LD = dyn_cast<LoadSDNode>(SrcOp);
6180 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6182 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6183 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6184 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6185 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6186 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6188 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6189 return DAG.getNode(ISD::BITCAST, dl, VT,
6190 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6191 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6199 return DAG.getNode(ISD::BITCAST, dl, VT,
6200 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6201 DAG.getNode(ISD::BITCAST, dl,
6205 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6206 /// which could not be matched by any known target speficic shuffle
6208 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6210 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6211 if (NewOp.getNode())
6214 EVT VT = SVOp->getValueType(0);
6216 unsigned NumElems = VT.getVectorNumElements();
6217 unsigned NumLaneElems = NumElems / 2;
6219 DebugLoc dl = SVOp->getDebugLoc();
6220 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6221 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6224 SmallVector<int, 16> Mask;
6225 for (unsigned l = 0; l < 2; ++l) {
6226 // Build a shuffle mask for the output, discovering on the fly which
6227 // input vectors to use as shuffle operands (recorded in InputUsed).
6228 // If building a suitable shuffle vector proves too hard, then bail
6229 // out with UseBuildVector set.
6230 bool UseBuildVector = false;
6231 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6232 unsigned LaneStart = l * NumLaneElems;
6233 for (unsigned i = 0; i != NumLaneElems; ++i) {
6234 // The mask element. This indexes into the input.
6235 int Idx = SVOp->getMaskElt(i+LaneStart);
6237 // the mask element does not index into any input vector.
6242 // The input vector this mask element indexes into.
6243 int Input = Idx / NumLaneElems;
6245 // Turn the index into an offset from the start of the input vector.
6246 Idx -= Input * NumLaneElems;
6248 // Find or create a shuffle vector operand to hold this input.
6250 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6251 if (InputUsed[OpNo] == Input)
6252 // This input vector is already an operand.
6254 if (InputUsed[OpNo] < 0) {
6255 // Create a new operand for this input vector.
6256 InputUsed[OpNo] = Input;
6261 if (OpNo >= array_lengthof(InputUsed)) {
6262 // More than two input vectors used! Give up on trying to create a
6263 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6264 UseBuildVector = true;
6268 // Add the mask index for the new shuffle vector.
6269 Mask.push_back(Idx + OpNo * NumLaneElems);
6272 if (UseBuildVector) {
6273 SmallVector<SDValue, 16> SVOps;
6274 for (unsigned i = 0; i != NumLaneElems; ++i) {
6275 // The mask element. This indexes into the input.
6276 int Idx = SVOp->getMaskElt(i+LaneStart);
6278 SVOps.push_back(DAG.getUNDEF(EltVT));
6282 // The input vector this mask element indexes into.
6283 int Input = Idx / NumElems;
6285 // Turn the index into an offset from the start of the input vector.
6286 Idx -= Input * NumElems;
6288 // Extract the vector element by hand.
6289 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6290 SVOp->getOperand(Input),
6291 DAG.getIntPtrConstant(Idx)));
6294 // Construct the output using a BUILD_VECTOR.
6295 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6297 } else if (InputUsed[0] < 0) {
6298 // No input vectors were used! The result is undefined.
6299 Output[l] = DAG.getUNDEF(NVT);
6301 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6302 (InputUsed[0] % 2) * NumLaneElems,
6304 // If only one input was used, use an undefined vector for the other.
6305 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6306 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6307 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6308 // At least one input vector was used. Create a new shuffle vector.
6309 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6315 // Concatenate the result back
6316 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6319 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6320 /// 4 elements, and match them with several different shuffle types.
6322 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6323 SDValue V1 = SVOp->getOperand(0);
6324 SDValue V2 = SVOp->getOperand(1);
6325 DebugLoc dl = SVOp->getDebugLoc();
6326 EVT VT = SVOp->getValueType(0);
6328 assert(VT.is128BitVector() && "Unsupported vector size");
6330 std::pair<int, int> Locs[4];
6331 int Mask1[] = { -1, -1, -1, -1 };
6332 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6336 for (unsigned i = 0; i != 4; ++i) {
6337 int Idx = PermMask[i];
6339 Locs[i] = std::make_pair(-1, -1);
6341 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6343 Locs[i] = std::make_pair(0, NumLo);
6347 Locs[i] = std::make_pair(1, NumHi);
6349 Mask1[2+NumHi] = Idx;
6355 if (NumLo <= 2 && NumHi <= 2) {
6356 // If no more than two elements come from either vector. This can be
6357 // implemented with two shuffles. First shuffle gather the elements.
6358 // The second shuffle, which takes the first shuffle as both of its
6359 // vector operands, put the elements into the right order.
6360 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6362 int Mask2[] = { -1, -1, -1, -1 };
6364 for (unsigned i = 0; i != 4; ++i)
6365 if (Locs[i].first != -1) {
6366 unsigned Idx = (i < 2) ? 0 : 4;
6367 Idx += Locs[i].first * 2 + Locs[i].second;
6371 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6374 if (NumLo == 3 || NumHi == 3) {
6375 // Otherwise, we must have three elements from one vector, call it X, and
6376 // one element from the other, call it Y. First, use a shufps to build an
6377 // intermediate vector with the one element from Y and the element from X
6378 // that will be in the same half in the final destination (the indexes don't
6379 // matter). Then, use a shufps to build the final vector, taking the half
6380 // containing the element from Y from the intermediate, and the other half
6383 // Normalize it so the 3 elements come from V1.
6384 CommuteVectorShuffleMask(PermMask, 4);
6388 // Find the element from V2.
6390 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6391 int Val = PermMask[HiIndex];
6398 Mask1[0] = PermMask[HiIndex];
6400 Mask1[2] = PermMask[HiIndex^1];
6402 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6405 Mask1[0] = PermMask[0];
6406 Mask1[1] = PermMask[1];
6407 Mask1[2] = HiIndex & 1 ? 6 : 4;
6408 Mask1[3] = HiIndex & 1 ? 4 : 6;
6409 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6412 Mask1[0] = HiIndex & 1 ? 2 : 0;
6413 Mask1[1] = HiIndex & 1 ? 0 : 2;
6414 Mask1[2] = PermMask[2];
6415 Mask1[3] = PermMask[3];
6420 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6423 // Break it into (shuffle shuffle_hi, shuffle_lo).
6424 int LoMask[] = { -1, -1, -1, -1 };
6425 int HiMask[] = { -1, -1, -1, -1 };
6427 int *MaskPtr = LoMask;
6428 unsigned MaskIdx = 0;
6431 for (unsigned i = 0; i != 4; ++i) {
6438 int Idx = PermMask[i];
6440 Locs[i] = std::make_pair(-1, -1);
6441 } else if (Idx < 4) {
6442 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6443 MaskPtr[LoIdx] = Idx;
6446 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6447 MaskPtr[HiIdx] = Idx;
6452 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6453 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6454 int MaskOps[] = { -1, -1, -1, -1 };
6455 for (unsigned i = 0; i != 4; ++i)
6456 if (Locs[i].first != -1)
6457 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6458 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6461 static bool MayFoldVectorLoad(SDValue V) {
6462 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6463 V = V.getOperand(0);
6465 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6466 V = V.getOperand(0);
6467 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6468 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6469 // BUILD_VECTOR (load), undef
6470 V = V.getOperand(0);
6472 return MayFoldLoad(V);
6476 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6477 EVT VT = Op.getValueType();
6479 // Canonizalize to v2f64.
6480 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6481 return DAG.getNode(ISD::BITCAST, dl, VT,
6482 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6487 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6489 SDValue V1 = Op.getOperand(0);
6490 SDValue V2 = Op.getOperand(1);
6491 EVT VT = Op.getValueType();
6493 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6495 if (HasSSE2 && VT == MVT::v2f64)
6496 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6498 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6499 return DAG.getNode(ISD::BITCAST, dl, VT,
6500 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6501 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6502 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6506 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6507 SDValue V1 = Op.getOperand(0);
6508 SDValue V2 = Op.getOperand(1);
6509 EVT VT = Op.getValueType();
6511 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6512 "unsupported shuffle type");
6514 if (V2.getOpcode() == ISD::UNDEF)
6518 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6522 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6523 SDValue V1 = Op.getOperand(0);
6524 SDValue V2 = Op.getOperand(1);
6525 EVT VT = Op.getValueType();
6526 unsigned NumElems = VT.getVectorNumElements();
6528 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6529 // operand of these instructions is only memory, so check if there's a
6530 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6532 bool CanFoldLoad = false;
6534 // Trivial case, when V2 comes from a load.
6535 if (MayFoldVectorLoad(V2))
6538 // When V1 is a load, it can be folded later into a store in isel, example:
6539 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6541 // (MOVLPSmr addr:$src1, VR128:$src2)
6542 // So, recognize this potential and also use MOVLPS or MOVLPD
6543 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6546 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6548 if (HasSSE2 && NumElems == 2)
6549 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6552 // If we don't care about the second element, proceed to use movss.
6553 if (SVOp->getMaskElt(1) != -1)
6554 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6557 // movl and movlp will both match v2i64, but v2i64 is never matched by
6558 // movl earlier because we make it strict to avoid messing with the movlp load
6559 // folding logic (see the code above getMOVLP call). Match it here then,
6560 // this is horrible, but will stay like this until we move all shuffle
6561 // matching to x86 specific nodes. Note that for the 1st condition all
6562 // types are matched with movsd.
6564 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6565 // as to remove this logic from here, as much as possible
6566 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6567 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6568 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6571 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6573 // Invert the operand order and use SHUFPS to match it.
6574 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6575 getShuffleSHUFImmediate(SVOp), DAG);
6578 // Reduce a vector shuffle to zext.
6580 X86TargetLowering::lowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6581 // PMOVZX is only available from SSE41.
6582 if (!Subtarget->hasSSE41())
6585 EVT VT = Op.getValueType();
6587 // Only AVX2 support 256-bit vector integer extending.
6588 if (!Subtarget->hasInt256() && VT.is256BitVector())
6591 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6592 DebugLoc DL = Op.getDebugLoc();
6593 SDValue V1 = Op.getOperand(0);
6594 SDValue V2 = Op.getOperand(1);
6595 unsigned NumElems = VT.getVectorNumElements();
6597 // Extending is an unary operation and the element type of the source vector
6598 // won't be equal to or larger than i64.
6599 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6600 VT.getVectorElementType() == MVT::i64)
6603 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6604 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6605 while ((1U << Shift) < NumElems) {
6606 if (SVOp->getMaskElt(1U << Shift) == 1)
6609 // The maximal ratio is 8, i.e. from i8 to i64.
6614 // Check the shuffle mask.
6615 unsigned Mask = (1U << Shift) - 1;
6616 for (unsigned i = 0; i != NumElems; ++i) {
6617 int EltIdx = SVOp->getMaskElt(i);
6618 if ((i & Mask) != 0 && EltIdx != -1)
6620 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6624 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6625 EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits);
6626 EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> Shift);
6628 if (!isTypeLegal(NVT))
6631 // Simplify the operand as it's prepared to be fed into shuffle.
6632 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6633 if (V1.getOpcode() == ISD::BITCAST &&
6634 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6635 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6637 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6638 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6639 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6640 ConstantSDNode *CIdx =
6641 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6642 // If it's foldable, i.e. normal load with single use, we will let code
6643 // selection to fold it. Otherwise, we will short the conversion sequence.
6644 if (CIdx && CIdx->getZExtValue() == 0 &&
6645 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse()))
6646 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6649 return DAG.getNode(ISD::BITCAST, DL, VT,
6650 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6654 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6655 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6656 EVT VT = Op.getValueType();
6657 DebugLoc dl = Op.getDebugLoc();
6658 SDValue V1 = Op.getOperand(0);
6659 SDValue V2 = Op.getOperand(1);
6661 if (isZeroShuffle(SVOp))
6662 return getZeroVector(VT, Subtarget, DAG, dl);
6664 // Handle splat operations
6665 if (SVOp->isSplat()) {
6666 unsigned NumElem = VT.getVectorNumElements();
6667 int Size = VT.getSizeInBits();
6669 // Use vbroadcast whenever the splat comes from a foldable load
6670 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6671 if (Broadcast.getNode())
6674 // Handle splats by matching through known shuffle masks
6675 if ((Size == 128 && NumElem <= 4) ||
6676 (Size == 256 && NumElem <= 8))
6679 // All remaning splats are promoted to target supported vector shuffles.
6680 return PromoteSplat(SVOp, DAG);
6683 // Check integer expanding shuffles.
6684 SDValue NewOp = lowerVectorIntExtend(Op, DAG);
6685 if (NewOp.getNode())
6688 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6690 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6691 VT == MVT::v16i16 || VT == MVT::v32i8) {
6692 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6693 if (NewOp.getNode())
6694 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6695 } else if ((VT == MVT::v4i32 ||
6696 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6697 // FIXME: Figure out a cleaner way to do this.
6698 // Try to make use of movq to zero out the top part.
6699 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6700 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6701 if (NewOp.getNode()) {
6702 EVT NewVT = NewOp.getValueType();
6703 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6704 NewVT, true, false))
6705 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6706 DAG, Subtarget, dl);
6708 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6709 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6710 if (NewOp.getNode()) {
6711 EVT NewVT = NewOp.getValueType();
6712 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6713 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6714 DAG, Subtarget, dl);
6722 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6723 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6724 SDValue V1 = Op.getOperand(0);
6725 SDValue V2 = Op.getOperand(1);
6726 EVT VT = Op.getValueType();
6727 DebugLoc dl = Op.getDebugLoc();
6728 unsigned NumElems = VT.getVectorNumElements();
6729 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6730 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6731 bool V1IsSplat = false;
6732 bool V2IsSplat = false;
6733 bool HasSSE2 = Subtarget->hasSSE2();
6734 bool HasFp256 = Subtarget->hasFp256();
6735 bool HasInt256 = Subtarget->hasInt256();
6736 MachineFunction &MF = DAG.getMachineFunction();
6737 bool OptForSize = MF.getFunction()->getFnAttributes().
6738 hasAttribute(Attribute::OptimizeForSize);
6740 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6742 if (V1IsUndef && V2IsUndef)
6743 return DAG.getUNDEF(VT);
6745 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6747 // Vector shuffle lowering takes 3 steps:
6749 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6750 // narrowing and commutation of operands should be handled.
6751 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6753 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6754 // so the shuffle can be broken into other shuffles and the legalizer can
6755 // try the lowering again.
6757 // The general idea is that no vector_shuffle operation should be left to
6758 // be matched during isel, all of them must be converted to a target specific
6761 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6762 // narrowing and commutation of operands should be handled. The actual code
6763 // doesn't include all of those, work in progress...
6764 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6765 if (NewOp.getNode())
6768 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6770 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6771 // unpckh_undef). Only use pshufd if speed is more important than size.
6772 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6773 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6774 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6775 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6777 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6778 V2IsUndef && MayFoldVectorLoad(V1))
6779 return getMOVDDup(Op, dl, V1, DAG);
6781 if (isMOVHLPS_v_undef_Mask(M, VT))
6782 return getMOVHighToLow(Op, dl, DAG);
6784 // Use to match splats
6785 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
6786 (VT == MVT::v2f64 || VT == MVT::v2i64))
6787 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6789 if (isPSHUFDMask(M, VT)) {
6790 // The actual implementation will match the mask in the if above and then
6791 // during isel it can match several different instructions, not only pshufd
6792 // as its name says, sad but true, emulate the behavior for now...
6793 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6794 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6796 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6798 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6799 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6801 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6802 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
6805 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6809 // Check if this can be converted into a logical shift.
6810 bool isLeft = false;
6813 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6814 if (isShift && ShVal.hasOneUse()) {
6815 // If the shifted value has multiple uses, it may be cheaper to use
6816 // v_set0 + movlhps or movhlps, etc.
6817 EVT EltVT = VT.getVectorElementType();
6818 ShAmt *= EltVT.getSizeInBits();
6819 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6822 if (isMOVLMask(M, VT)) {
6823 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6824 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6825 if (!isMOVLPMask(M, VT)) {
6826 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6827 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6829 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6830 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6834 // FIXME: fold these into legal mask.
6835 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
6836 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6838 if (isMOVHLPSMask(M, VT))
6839 return getMOVHighToLow(Op, dl, DAG);
6841 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6842 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6844 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6845 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6847 if (isMOVLPMask(M, VT))
6848 return getMOVLP(Op, dl, DAG, HasSSE2);
6850 if (ShouldXformToMOVHLPS(M, VT) ||
6851 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6852 return CommuteVectorShuffle(SVOp, DAG);
6855 // No better options. Use a vshldq / vsrldq.
6856 EVT EltVT = VT.getVectorElementType();
6857 ShAmt *= EltVT.getSizeInBits();
6858 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6861 bool Commuted = false;
6862 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6863 // 1,1,1,1 -> v8i16 though.
6864 V1IsSplat = isSplatVector(V1.getNode());
6865 V2IsSplat = isSplatVector(V2.getNode());
6867 // Canonicalize the splat or undef, if present, to be on the RHS.
6868 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6869 CommuteVectorShuffleMask(M, NumElems);
6871 std::swap(V1IsSplat, V2IsSplat);
6875 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6876 // Shuffling low element of v1 into undef, just return v1.
6879 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6880 // the instruction selector will not match, so get a canonical MOVL with
6881 // swapped operands to undo the commute.
6882 return getMOVL(DAG, dl, VT, V2, V1);
6885 if (isUNPCKLMask(M, VT, HasInt256))
6886 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6888 if (isUNPCKHMask(M, VT, HasInt256))
6889 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6892 // Normalize mask so all entries that point to V2 points to its first
6893 // element then try to match unpck{h|l} again. If match, return a
6894 // new vector_shuffle with the corrected mask.p
6895 SmallVector<int, 8> NewMask(M.begin(), M.end());
6896 NormalizeMask(NewMask, NumElems);
6897 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
6898 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6899 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
6900 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6904 // Commute is back and try unpck* again.
6905 // FIXME: this seems wrong.
6906 CommuteVectorShuffleMask(M, NumElems);
6908 std::swap(V1IsSplat, V2IsSplat);
6911 if (isUNPCKLMask(M, VT, HasInt256))
6912 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6914 if (isUNPCKHMask(M, VT, HasInt256))
6915 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6918 // Normalize the node to match x86 shuffle ops if needed
6919 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
6920 return CommuteVectorShuffle(SVOp, DAG);
6922 // The checks below are all present in isShuffleMaskLegal, but they are
6923 // inlined here right now to enable us to directly emit target specific
6924 // nodes, and remove one by one until they don't return Op anymore.
6926 if (isPALIGNRMask(M, VT, Subtarget))
6927 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6928 getShufflePALIGNRImmediate(SVOp),
6931 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6932 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6933 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6934 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6937 if (isPSHUFHWMask(M, VT, HasInt256))
6938 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6939 getShufflePSHUFHWImmediate(SVOp),
6942 if (isPSHUFLWMask(M, VT, HasInt256))
6943 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6944 getShufflePSHUFLWImmediate(SVOp),
6947 if (isSHUFPMask(M, VT, HasFp256))
6948 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6949 getShuffleSHUFImmediate(SVOp), DAG);
6951 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6952 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6953 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6954 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6956 //===--------------------------------------------------------------------===//
6957 // Generate target specific nodes for 128 or 256-bit shuffles only
6958 // supported in the AVX instruction set.
6961 // Handle VMOVDDUPY permutations
6962 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
6963 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6965 // Handle VPERMILPS/D* permutations
6966 if (isVPERMILPMask(M, VT, HasFp256)) {
6967 if (HasInt256 && VT == MVT::v8i32)
6968 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6969 getShuffleSHUFImmediate(SVOp), DAG);
6970 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6971 getShuffleSHUFImmediate(SVOp), DAG);
6974 // Handle VPERM2F128/VPERM2I128 permutations
6975 if (isVPERM2X128Mask(M, VT, HasFp256))
6976 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6977 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6979 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6980 if (BlendOp.getNode())
6983 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6984 SmallVector<SDValue, 8> permclMask;
6985 for (unsigned i = 0; i != 8; ++i) {
6986 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6988 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6990 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6991 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6992 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6995 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6996 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6997 getShuffleCLImmediate(SVOp), DAG);
7000 //===--------------------------------------------------------------------===//
7001 // Since no target specific shuffle was selected for this generic one,
7002 // lower it into other known shuffles. FIXME: this isn't true yet, but
7003 // this is the plan.
7006 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7007 if (VT == MVT::v8i16) {
7008 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7009 if (NewOp.getNode())
7013 if (VT == MVT::v16i8) {
7014 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7015 if (NewOp.getNode())
7019 if (VT == MVT::v32i8) {
7020 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7021 if (NewOp.getNode())
7025 // Handle all 128-bit wide vectors with 4 elements, and match them with
7026 // several different shuffle types.
7027 if (NumElems == 4 && VT.is128BitVector())
7028 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7030 // Handle general 256-bit shuffles
7031 if (VT.is256BitVector())
7032 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7038 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
7039 SelectionDAG &DAG) const {
7040 EVT VT = Op.getValueType();
7041 DebugLoc dl = Op.getDebugLoc();
7043 if (!Op.getOperand(0).getValueType().is128BitVector())
7046 if (VT.getSizeInBits() == 8) {
7047 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7048 Op.getOperand(0), Op.getOperand(1));
7049 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7050 DAG.getValueType(VT));
7051 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7054 if (VT.getSizeInBits() == 16) {
7055 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7056 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7058 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7059 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7060 DAG.getNode(ISD::BITCAST, dl,
7064 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7065 Op.getOperand(0), Op.getOperand(1));
7066 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7067 DAG.getValueType(VT));
7068 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7071 if (VT == MVT::f32) {
7072 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7073 // the result back to FR32 register. It's only worth matching if the
7074 // result has a single use which is a store or a bitcast to i32. And in
7075 // the case of a store, it's not worth it if the index is a constant 0,
7076 // because a MOVSSmr can be used instead, which is smaller and faster.
7077 if (!Op.hasOneUse())
7079 SDNode *User = *Op.getNode()->use_begin();
7080 if ((User->getOpcode() != ISD::STORE ||
7081 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7082 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7083 (User->getOpcode() != ISD::BITCAST ||
7084 User->getValueType(0) != MVT::i32))
7086 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7087 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7090 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7093 if (VT == MVT::i32 || VT == MVT::i64) {
7094 // ExtractPS/pextrq works with constant index.
7095 if (isa<ConstantSDNode>(Op.getOperand(1)))
7103 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7104 SelectionDAG &DAG) const {
7105 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7108 SDValue Vec = Op.getOperand(0);
7109 EVT VecVT = Vec.getValueType();
7111 // If this is a 256-bit vector result, first extract the 128-bit vector and
7112 // then extract the element from the 128-bit vector.
7113 if (VecVT.is256BitVector()) {
7114 DebugLoc dl = Op.getNode()->getDebugLoc();
7115 unsigned NumElems = VecVT.getVectorNumElements();
7116 SDValue Idx = Op.getOperand(1);
7117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7119 // Get the 128-bit vector.
7120 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7122 if (IdxVal >= NumElems/2)
7123 IdxVal -= NumElems/2;
7124 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7125 DAG.getConstant(IdxVal, MVT::i32));
7128 assert(VecVT.is128BitVector() && "Unexpected vector length");
7130 if (Subtarget->hasSSE41()) {
7131 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7136 EVT VT = Op.getValueType();
7137 DebugLoc dl = Op.getDebugLoc();
7138 // TODO: handle v16i8.
7139 if (VT.getSizeInBits() == 16) {
7140 SDValue Vec = Op.getOperand(0);
7141 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7143 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7144 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7145 DAG.getNode(ISD::BITCAST, dl,
7148 // Transform it so it match pextrw which produces a 32-bit result.
7149 EVT EltVT = MVT::i32;
7150 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7151 Op.getOperand(0), Op.getOperand(1));
7152 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7153 DAG.getValueType(VT));
7154 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7157 if (VT.getSizeInBits() == 32) {
7158 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7162 // SHUFPS the element to the lowest double word, then movss.
7163 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7164 EVT VVT = Op.getOperand(0).getValueType();
7165 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7166 DAG.getUNDEF(VVT), Mask);
7167 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7168 DAG.getIntPtrConstant(0));
7171 if (VT.getSizeInBits() == 64) {
7172 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7173 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7174 // to match extract_elt for f64.
7175 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7179 // UNPCKHPD the element to the lowest double word, then movsd.
7180 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7181 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7182 int Mask[2] = { 1, -1 };
7183 EVT VVT = Op.getOperand(0).getValueType();
7184 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7185 DAG.getUNDEF(VVT), Mask);
7186 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7187 DAG.getIntPtrConstant(0));
7194 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
7195 SelectionDAG &DAG) const {
7196 EVT VT = Op.getValueType();
7197 EVT EltVT = VT.getVectorElementType();
7198 DebugLoc dl = Op.getDebugLoc();
7200 SDValue N0 = Op.getOperand(0);
7201 SDValue N1 = Op.getOperand(1);
7202 SDValue N2 = Op.getOperand(2);
7204 if (!VT.is128BitVector())
7207 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7208 isa<ConstantSDNode>(N2)) {
7210 if (VT == MVT::v8i16)
7211 Opc = X86ISD::PINSRW;
7212 else if (VT == MVT::v16i8)
7213 Opc = X86ISD::PINSRB;
7215 Opc = X86ISD::PINSRB;
7217 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7219 if (N1.getValueType() != MVT::i32)
7220 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7221 if (N2.getValueType() != MVT::i32)
7222 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7223 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7226 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7227 // Bits [7:6] of the constant are the source select. This will always be
7228 // zero here. The DAG Combiner may combine an extract_elt index into these
7229 // bits. For example (insert (extract, 3), 2) could be matched by putting
7230 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7231 // Bits [5:4] of the constant are the destination select. This is the
7232 // value of the incoming immediate.
7233 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7234 // combine either bitwise AND or insert of float 0.0 to set these bits.
7235 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7236 // Create this as a scalar to vector..
7237 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7238 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7241 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7242 // PINSR* works with constant index.
7249 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7250 EVT VT = Op.getValueType();
7251 EVT EltVT = VT.getVectorElementType();
7253 DebugLoc dl = Op.getDebugLoc();
7254 SDValue N0 = Op.getOperand(0);
7255 SDValue N1 = Op.getOperand(1);
7256 SDValue N2 = Op.getOperand(2);
7258 // If this is a 256-bit vector result, first extract the 128-bit vector,
7259 // insert the element into the extracted half and then place it back.
7260 if (VT.is256BitVector()) {
7261 if (!isa<ConstantSDNode>(N2))
7264 // Get the desired 128-bit vector half.
7265 unsigned NumElems = VT.getVectorNumElements();
7266 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7267 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7269 // Insert the element into the desired half.
7270 bool Upper = IdxVal >= NumElems/2;
7271 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7272 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7274 // Insert the changed part back to the 256-bit vector
7275 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7278 if (Subtarget->hasSSE41())
7279 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7281 if (EltVT == MVT::i8)
7284 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7285 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7286 // as its second argument.
7287 if (N1.getValueType() != MVT::i32)
7288 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7289 if (N2.getValueType() != MVT::i32)
7290 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7291 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7296 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7297 LLVMContext *Context = DAG.getContext();
7298 DebugLoc dl = Op.getDebugLoc();
7299 EVT OpVT = Op.getValueType();
7301 // If this is a 256-bit vector result, first insert into a 128-bit
7302 // vector and then insert into the 256-bit vector.
7303 if (!OpVT.is128BitVector()) {
7304 // Insert into a 128-bit vector.
7305 EVT VT128 = EVT::getVectorVT(*Context,
7306 OpVT.getVectorElementType(),
7307 OpVT.getVectorNumElements() / 2);
7309 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7311 // Insert the 128-bit vector.
7312 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7315 if (OpVT == MVT::v1i64 &&
7316 Op.getOperand(0).getValueType() == MVT::i64)
7317 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7319 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7320 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7321 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7322 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7325 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7326 // a simple subregister reference or explicit instructions to grab
7327 // upper bits of a vector.
7328 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7329 SelectionDAG &DAG) {
7330 if (Subtarget->hasFp256()) {
7331 DebugLoc dl = Op.getNode()->getDebugLoc();
7332 SDValue Vec = Op.getNode()->getOperand(0);
7333 SDValue Idx = Op.getNode()->getOperand(1);
7335 if (Op.getNode()->getValueType(0).is128BitVector() &&
7336 Vec.getNode()->getValueType(0).is256BitVector() &&
7337 isa<ConstantSDNode>(Idx)) {
7338 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7339 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7345 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7346 // simple superregister reference or explicit instructions to insert
7347 // the upper bits of a vector.
7348 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7349 SelectionDAG &DAG) {
7350 if (Subtarget->hasFp256()) {
7351 DebugLoc dl = Op.getNode()->getDebugLoc();
7352 SDValue Vec = Op.getNode()->getOperand(0);
7353 SDValue SubVec = Op.getNode()->getOperand(1);
7354 SDValue Idx = Op.getNode()->getOperand(2);
7356 if (Op.getNode()->getValueType(0).is256BitVector() &&
7357 SubVec.getNode()->getValueType(0).is128BitVector() &&
7358 isa<ConstantSDNode>(Idx)) {
7359 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7360 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7366 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7367 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7368 // one of the above mentioned nodes. It has to be wrapped because otherwise
7369 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7370 // be used to form addressing mode. These wrapped nodes will be selected
7373 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7374 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7376 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7378 unsigned char OpFlag = 0;
7379 unsigned WrapperKind = X86ISD::Wrapper;
7380 CodeModel::Model M = getTargetMachine().getCodeModel();
7382 if (Subtarget->isPICStyleRIPRel() &&
7383 (M == CodeModel::Small || M == CodeModel::Kernel))
7384 WrapperKind = X86ISD::WrapperRIP;
7385 else if (Subtarget->isPICStyleGOT())
7386 OpFlag = X86II::MO_GOTOFF;
7387 else if (Subtarget->isPICStyleStubPIC())
7388 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7390 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7392 CP->getOffset(), OpFlag);
7393 DebugLoc DL = CP->getDebugLoc();
7394 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7395 // With PIC, the address is actually $g + Offset.
7397 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7398 DAG.getNode(X86ISD::GlobalBaseReg,
7399 DebugLoc(), getPointerTy()),
7406 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7407 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7409 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7411 unsigned char OpFlag = 0;
7412 unsigned WrapperKind = X86ISD::Wrapper;
7413 CodeModel::Model M = getTargetMachine().getCodeModel();
7415 if (Subtarget->isPICStyleRIPRel() &&
7416 (M == CodeModel::Small || M == CodeModel::Kernel))
7417 WrapperKind = X86ISD::WrapperRIP;
7418 else if (Subtarget->isPICStyleGOT())
7419 OpFlag = X86II::MO_GOTOFF;
7420 else if (Subtarget->isPICStyleStubPIC())
7421 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7423 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7425 DebugLoc DL = JT->getDebugLoc();
7426 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7428 // With PIC, the address is actually $g + Offset.
7430 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7431 DAG.getNode(X86ISD::GlobalBaseReg,
7432 DebugLoc(), getPointerTy()),
7439 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7440 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7442 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7444 unsigned char OpFlag = 0;
7445 unsigned WrapperKind = X86ISD::Wrapper;
7446 CodeModel::Model M = getTargetMachine().getCodeModel();
7448 if (Subtarget->isPICStyleRIPRel() &&
7449 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7450 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7451 OpFlag = X86II::MO_GOTPCREL;
7452 WrapperKind = X86ISD::WrapperRIP;
7453 } else if (Subtarget->isPICStyleGOT()) {
7454 OpFlag = X86II::MO_GOT;
7455 } else if (Subtarget->isPICStyleStubPIC()) {
7456 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7457 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7458 OpFlag = X86II::MO_DARWIN_NONLAZY;
7461 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7463 DebugLoc DL = Op.getDebugLoc();
7464 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7467 // With PIC, the address is actually $g + Offset.
7468 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7469 !Subtarget->is64Bit()) {
7470 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7471 DAG.getNode(X86ISD::GlobalBaseReg,
7472 DebugLoc(), getPointerTy()),
7476 // For symbols that require a load from a stub to get the address, emit the
7478 if (isGlobalStubReference(OpFlag))
7479 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7480 MachinePointerInfo::getGOT(), false, false, false, 0);
7486 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7487 // Create the TargetBlockAddressAddress node.
7488 unsigned char OpFlags =
7489 Subtarget->ClassifyBlockAddressReference();
7490 CodeModel::Model M = getTargetMachine().getCodeModel();
7491 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7492 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7493 DebugLoc dl = Op.getDebugLoc();
7494 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7497 if (Subtarget->isPICStyleRIPRel() &&
7498 (M == CodeModel::Small || M == CodeModel::Kernel))
7499 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7501 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7503 // With PIC, the address is actually $g + Offset.
7504 if (isGlobalRelativeToPICBase(OpFlags)) {
7505 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7506 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7514 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7516 SelectionDAG &DAG) const {
7517 // Create the TargetGlobalAddress node, folding in the constant
7518 // offset if it is legal.
7519 unsigned char OpFlags =
7520 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7521 CodeModel::Model M = getTargetMachine().getCodeModel();
7523 if (OpFlags == X86II::MO_NO_FLAG &&
7524 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7525 // A direct static reference to a global.
7526 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7529 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7532 if (Subtarget->isPICStyleRIPRel() &&
7533 (M == CodeModel::Small || M == CodeModel::Kernel))
7534 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7536 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7538 // With PIC, the address is actually $g + Offset.
7539 if (isGlobalRelativeToPICBase(OpFlags)) {
7540 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7541 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7545 // For globals that require a load from a stub to get the address, emit the
7547 if (isGlobalStubReference(OpFlags))
7548 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7549 MachinePointerInfo::getGOT(), false, false, false, 0);
7551 // If there was a non-zero offset that we didn't fold, create an explicit
7554 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7555 DAG.getConstant(Offset, getPointerTy()));
7561 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7562 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7563 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7564 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7568 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7569 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7570 unsigned char OperandFlags, bool LocalDynamic = false) {
7571 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7572 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7573 DebugLoc dl = GA->getDebugLoc();
7574 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7575 GA->getValueType(0),
7579 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7583 SDValue Ops[] = { Chain, TGA, *InFlag };
7584 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7586 SDValue Ops[] = { Chain, TGA };
7587 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7590 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7591 MFI->setAdjustsStack(true);
7593 SDValue Flag = Chain.getValue(1);
7594 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7597 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7599 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7602 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7603 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7604 DAG.getNode(X86ISD::GlobalBaseReg,
7605 DebugLoc(), PtrVT), InFlag);
7606 InFlag = Chain.getValue(1);
7608 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7611 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7613 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7615 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7616 X86::RAX, X86II::MO_TLSGD);
7619 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7623 DebugLoc dl = GA->getDebugLoc();
7625 // Get the start address of the TLS block for this module.
7626 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7627 .getInfo<X86MachineFunctionInfo>();
7628 MFI->incNumLocalDynamicTLSAccesses();
7632 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7633 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7636 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7637 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7638 InFlag = Chain.getValue(1);
7639 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7640 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7643 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7647 unsigned char OperandFlags = X86II::MO_DTPOFF;
7648 unsigned WrapperKind = X86ISD::Wrapper;
7649 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7650 GA->getValueType(0),
7651 GA->getOffset(), OperandFlags);
7652 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7654 // Add x@dtpoff with the base.
7655 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7658 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7659 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7660 const EVT PtrVT, TLSModel::Model model,
7661 bool is64Bit, bool isPIC) {
7662 DebugLoc dl = GA->getDebugLoc();
7664 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7665 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7666 is64Bit ? 257 : 256));
7668 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7669 DAG.getIntPtrConstant(0),
7670 MachinePointerInfo(Ptr),
7671 false, false, false, 0);
7673 unsigned char OperandFlags = 0;
7674 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7676 unsigned WrapperKind = X86ISD::Wrapper;
7677 if (model == TLSModel::LocalExec) {
7678 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7679 } else if (model == TLSModel::InitialExec) {
7681 OperandFlags = X86II::MO_GOTTPOFF;
7682 WrapperKind = X86ISD::WrapperRIP;
7684 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7687 llvm_unreachable("Unexpected model");
7690 // emit "addl x@ntpoff,%eax" (local exec)
7691 // or "addl x@indntpoff,%eax" (initial exec)
7692 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7693 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7694 GA->getValueType(0),
7695 GA->getOffset(), OperandFlags);
7696 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7698 if (model == TLSModel::InitialExec) {
7699 if (isPIC && !is64Bit) {
7700 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7701 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7705 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7706 MachinePointerInfo::getGOT(), false, false, false,
7710 // The address of the thread local variable is the add of the thread
7711 // pointer with the offset of the variable.
7712 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7716 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7718 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7719 const GlobalValue *GV = GA->getGlobal();
7721 if (Subtarget->isTargetELF()) {
7722 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7725 case TLSModel::GeneralDynamic:
7726 if (Subtarget->is64Bit())
7727 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7728 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7729 case TLSModel::LocalDynamic:
7730 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7731 Subtarget->is64Bit());
7732 case TLSModel::InitialExec:
7733 case TLSModel::LocalExec:
7734 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7735 Subtarget->is64Bit(),
7736 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7738 llvm_unreachable("Unknown TLS model.");
7741 if (Subtarget->isTargetDarwin()) {
7742 // Darwin only has one model of TLS. Lower to that.
7743 unsigned char OpFlag = 0;
7744 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7745 X86ISD::WrapperRIP : X86ISD::Wrapper;
7747 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7749 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7750 !Subtarget->is64Bit();
7752 OpFlag = X86II::MO_TLVP_PIC_BASE;
7754 OpFlag = X86II::MO_TLVP;
7755 DebugLoc DL = Op.getDebugLoc();
7756 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7757 GA->getValueType(0),
7758 GA->getOffset(), OpFlag);
7759 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7761 // With PIC32, the address is actually $g + Offset.
7763 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7764 DAG.getNode(X86ISD::GlobalBaseReg,
7765 DebugLoc(), getPointerTy()),
7768 // Lowering the machine isd will make sure everything is in the right
7770 SDValue Chain = DAG.getEntryNode();
7771 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7772 SDValue Args[] = { Chain, Offset };
7773 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7775 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7776 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7777 MFI->setAdjustsStack(true);
7779 // And our return value (tls address) is in the standard call return value
7781 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7782 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7786 if (Subtarget->isTargetWindows()) {
7787 // Just use the implicit TLS architecture
7788 // Need to generate someting similar to:
7789 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7791 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7792 // mov rcx, qword [rdx+rcx*8]
7793 // mov eax, .tls$:tlsvar
7794 // [rax+rcx] contains the address
7795 // Windows 64bit: gs:0x58
7796 // Windows 32bit: fs:__tls_array
7798 // If GV is an alias then use the aliasee for determining
7799 // thread-localness.
7800 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7801 GV = GA->resolveAliasedGlobal(false);
7802 DebugLoc dl = GA->getDebugLoc();
7803 SDValue Chain = DAG.getEntryNode();
7805 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7806 // %gs:0x58 (64-bit).
7807 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7808 ? Type::getInt8PtrTy(*DAG.getContext(),
7810 : Type::getInt32PtrTy(*DAG.getContext(),
7813 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7814 Subtarget->is64Bit()
7815 ? DAG.getIntPtrConstant(0x58)
7816 : DAG.getExternalSymbol("_tls_array",
7818 MachinePointerInfo(Ptr),
7819 false, false, false, 0);
7821 // Load the _tls_index variable
7822 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7823 if (Subtarget->is64Bit())
7824 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7825 IDX, MachinePointerInfo(), MVT::i32,
7828 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7829 false, false, false, 0);
7831 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7833 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7835 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7836 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7837 false, false, false, 0);
7839 // Get the offset of start of .tls section
7840 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7841 GA->getValueType(0),
7842 GA->getOffset(), X86II::MO_SECREL);
7843 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7845 // The address of the thread local variable is the add of the thread
7846 // pointer with the offset of the variable.
7847 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7850 llvm_unreachable("TLS not implemented for this target.");
7854 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7855 /// and take a 2 x i32 value to shift plus a shift amount.
7856 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7857 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7858 EVT VT = Op.getValueType();
7859 unsigned VTBits = VT.getSizeInBits();
7860 DebugLoc dl = Op.getDebugLoc();
7861 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7862 SDValue ShOpLo = Op.getOperand(0);
7863 SDValue ShOpHi = Op.getOperand(1);
7864 SDValue ShAmt = Op.getOperand(2);
7865 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7866 DAG.getConstant(VTBits - 1, MVT::i8))
7867 : DAG.getConstant(0, VT);
7870 if (Op.getOpcode() == ISD::SHL_PARTS) {
7871 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7872 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7874 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7875 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7878 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7879 DAG.getConstant(VTBits, MVT::i8));
7880 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7881 AndNode, DAG.getConstant(0, MVT::i8));
7884 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7885 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7886 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7888 if (Op.getOpcode() == ISD::SHL_PARTS) {
7889 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7890 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7892 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7893 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7896 SDValue Ops[2] = { Lo, Hi };
7897 return DAG.getMergeValues(Ops, 2, dl);
7900 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7901 SelectionDAG &DAG) const {
7902 EVT SrcVT = Op.getOperand(0).getValueType();
7904 if (SrcVT.isVector())
7907 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7908 "Unknown SINT_TO_FP to lower!");
7910 // These are really Legal; return the operand so the caller accepts it as
7912 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7914 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7915 Subtarget->is64Bit()) {
7919 DebugLoc dl = Op.getDebugLoc();
7920 unsigned Size = SrcVT.getSizeInBits()/8;
7921 MachineFunction &MF = DAG.getMachineFunction();
7922 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7923 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7924 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7926 MachinePointerInfo::getFixedStack(SSFI),
7928 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7931 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7933 SelectionDAG &DAG) const {
7935 DebugLoc DL = Op.getDebugLoc();
7937 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7939 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7941 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7943 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7945 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7946 MachineMemOperand *MMO;
7948 int SSFI = FI->getIndex();
7950 DAG.getMachineFunction()
7951 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7952 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7954 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7955 StackSlot = StackSlot.getOperand(1);
7957 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7958 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7960 Tys, Ops, array_lengthof(Ops),
7964 Chain = Result.getValue(1);
7965 SDValue InFlag = Result.getValue(2);
7967 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7968 // shouldn't be necessary except that RFP cannot be live across
7969 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7970 MachineFunction &MF = DAG.getMachineFunction();
7971 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7972 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7973 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7974 Tys = DAG.getVTList(MVT::Other);
7976 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7978 MachineMemOperand *MMO =
7979 DAG.getMachineFunction()
7980 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7981 MachineMemOperand::MOStore, SSFISize, SSFISize);
7983 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7984 Ops, array_lengthof(Ops),
7985 Op.getValueType(), MMO);
7986 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7987 MachinePointerInfo::getFixedStack(SSFI),
7988 false, false, false, 0);
7994 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7995 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7996 SelectionDAG &DAG) const {
7997 // This algorithm is not obvious. Here it is what we're trying to output:
8000 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8001 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8005 pshufd $0x4e, %xmm0, %xmm1
8010 DebugLoc dl = Op.getDebugLoc();
8011 LLVMContext *Context = DAG.getContext();
8013 // Build some magic constants.
8014 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8015 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8016 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8018 SmallVector<Constant*,2> CV1;
8020 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
8022 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
8023 Constant *C1 = ConstantVector::get(CV1);
8024 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8026 // Load the 64-bit value into an XMM register.
8027 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8029 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8030 MachinePointerInfo::getConstantPool(),
8031 false, false, false, 16);
8032 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8033 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8036 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8037 MachinePointerInfo::getConstantPool(),
8038 false, false, false, 16);
8039 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8040 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8043 if (Subtarget->hasSSE3()) {
8044 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8045 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8047 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8048 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8050 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8051 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8055 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8056 DAG.getIntPtrConstant(0));
8059 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8060 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8061 SelectionDAG &DAG) const {
8062 DebugLoc dl = Op.getDebugLoc();
8063 // FP constant to bias correct the final result.
8064 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8067 // Load the 32-bit value into an XMM register.
8068 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8071 // Zero out the upper parts of the register.
8072 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8074 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8075 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8076 DAG.getIntPtrConstant(0));
8078 // Or the load with the bias.
8079 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8080 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8081 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8083 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8084 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8085 MVT::v2f64, Bias)));
8086 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8087 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8088 DAG.getIntPtrConstant(0));
8090 // Subtract the bias.
8091 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8093 // Handle final rounding.
8094 EVT DestVT = Op.getValueType();
8096 if (DestVT.bitsLT(MVT::f64))
8097 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8098 DAG.getIntPtrConstant(0));
8099 if (DestVT.bitsGT(MVT::f64))
8100 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8102 // Handle final rounding.
8106 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8107 SelectionDAG &DAG) const {
8108 SDValue N0 = Op.getOperand(0);
8109 EVT SVT = N0.getValueType();
8110 DebugLoc dl = Op.getDebugLoc();
8112 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8113 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8114 "Custom UINT_TO_FP is not supported!");
8116 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, SVT.getVectorNumElements());
8117 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8118 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8121 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8122 SelectionDAG &DAG) const {
8123 SDValue N0 = Op.getOperand(0);
8124 DebugLoc dl = Op.getDebugLoc();
8126 if (Op.getValueType().isVector())
8127 return lowerUINT_TO_FP_vec(Op, DAG);
8129 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8130 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8131 // the optimization here.
8132 if (DAG.SignBitIsZero(N0))
8133 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8135 EVT SrcVT = N0.getValueType();
8136 EVT DstVT = Op.getValueType();
8137 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8138 return LowerUINT_TO_FP_i64(Op, DAG);
8139 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8140 return LowerUINT_TO_FP_i32(Op, DAG);
8141 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8144 // Make a 64-bit buffer, and use it to build an FILD.
8145 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8146 if (SrcVT == MVT::i32) {
8147 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8148 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8149 getPointerTy(), StackSlot, WordOff);
8150 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8151 StackSlot, MachinePointerInfo(),
8153 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8154 OffsetSlot, MachinePointerInfo(),
8156 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8160 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8161 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8162 StackSlot, MachinePointerInfo(),
8164 // For i64 source, we need to add the appropriate power of 2 if the input
8165 // was negative. This is the same as the optimization in
8166 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8167 // we must be careful to do the computation in x87 extended precision, not
8168 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8169 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8170 MachineMemOperand *MMO =
8171 DAG.getMachineFunction()
8172 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8173 MachineMemOperand::MOLoad, 8, 8);
8175 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8176 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8177 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
8180 APInt FF(32, 0x5F800000ULL);
8182 // Check whether the sign bit is set.
8183 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
8184 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8187 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8188 SDValue FudgePtr = DAG.getConstantPool(
8189 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8192 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8193 SDValue Zero = DAG.getIntPtrConstant(0);
8194 SDValue Four = DAG.getIntPtrConstant(4);
8195 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8197 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8199 // Load the value out, extending it from f32 to f80.
8200 // FIXME: Avoid the extend by constructing the right constant pool?
8201 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8202 FudgePtr, MachinePointerInfo::getConstantPool(),
8203 MVT::f32, false, false, 4);
8204 // Extend everything to 80 bits to force it to be done on x87.
8205 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8206 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8209 std::pair<SDValue,SDValue> X86TargetLowering::
8210 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
8211 DebugLoc DL = Op.getDebugLoc();
8213 EVT DstTy = Op.getValueType();
8215 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8216 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8220 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8221 DstTy.getSimpleVT() >= MVT::i16 &&
8222 "Unknown FP_TO_INT to lower!");
8224 // These are really Legal.
8225 if (DstTy == MVT::i32 &&
8226 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8227 return std::make_pair(SDValue(), SDValue());
8228 if (Subtarget->is64Bit() &&
8229 DstTy == MVT::i64 &&
8230 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8231 return std::make_pair(SDValue(), SDValue());
8233 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8234 // stack slot, or into the FTOL runtime function.
8235 MachineFunction &MF = DAG.getMachineFunction();
8236 unsigned MemSize = DstTy.getSizeInBits()/8;
8237 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8238 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8241 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8242 Opc = X86ISD::WIN_FTOL;
8244 switch (DstTy.getSimpleVT().SimpleTy) {
8245 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8246 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8247 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8248 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8251 SDValue Chain = DAG.getEntryNode();
8252 SDValue Value = Op.getOperand(0);
8253 EVT TheVT = Op.getOperand(0).getValueType();
8254 // FIXME This causes a redundant load/store if the SSE-class value is already
8255 // in memory, such as if it is on the callstack.
8256 if (isScalarFPTypeInSSEReg(TheVT)) {
8257 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8258 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8259 MachinePointerInfo::getFixedStack(SSFI),
8261 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8263 Chain, StackSlot, DAG.getValueType(TheVT)
8266 MachineMemOperand *MMO =
8267 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8268 MachineMemOperand::MOLoad, MemSize, MemSize);
8269 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8271 Chain = Value.getValue(1);
8272 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8273 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8276 MachineMemOperand *MMO =
8277 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8278 MachineMemOperand::MOStore, MemSize, MemSize);
8280 if (Opc != X86ISD::WIN_FTOL) {
8281 // Build the FP_TO_INT*_IN_MEM
8282 SDValue Ops[] = { Chain, Value, StackSlot };
8283 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8284 Ops, 3, DstTy, MMO);
8285 return std::make_pair(FIST, StackSlot);
8287 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8288 DAG.getVTList(MVT::Other, MVT::Glue),
8290 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8291 MVT::i32, ftol.getValue(1));
8292 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8293 MVT::i32, eax.getValue(2));
8294 SDValue Ops[] = { eax, edx };
8295 SDValue pair = IsReplace
8296 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8297 : DAG.getMergeValues(Ops, 2, DL);
8298 return std::make_pair(pair, SDValue());
8302 SDValue X86TargetLowering::lowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const {
8303 DebugLoc DL = Op.getDebugLoc();
8304 EVT VT = Op.getValueType();
8305 SDValue In = Op.getOperand(0);
8306 EVT SVT = In.getValueType();
8308 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8309 VT.getVectorNumElements() != SVT.getVectorNumElements())
8312 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8314 // AVX2 has better support of integer extending.
8315 if (Subtarget->hasInt256())
8316 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8318 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8319 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8320 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8321 DAG.getVectorShuffle(MVT::v8i16, DL, In, DAG.getUNDEF(MVT::v8i16), &Mask[0]));
8323 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8326 SDValue X86TargetLowering::lowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8327 DebugLoc DL = Op.getDebugLoc();
8328 EVT VT = Op.getValueType();
8329 EVT SVT = Op.getOperand(0).getValueType();
8331 if (!VT.is128BitVector() || !SVT.is256BitVector() ||
8332 VT.getVectorNumElements() != SVT.getVectorNumElements())
8335 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8337 unsigned NumElems = VT.getVectorNumElements();
8338 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8341 SDValue In = Op.getOperand(0);
8342 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8343 // Prepare truncation shuffle mask
8344 for (unsigned i = 0; i != NumElems; ++i)
8346 SDValue V = DAG.getVectorShuffle(NVT, DL,
8347 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8348 DAG.getUNDEF(NVT), &MaskVec[0]);
8349 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8350 DAG.getIntPtrConstant(0));
8353 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8354 SelectionDAG &DAG) const {
8355 if (Op.getValueType().isVector()) {
8356 if (Op.getValueType() == MVT::v8i16)
8357 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), Op.getValueType(),
8358 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8359 MVT::v8i32, Op.getOperand(0)));
8363 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8364 /*IsSigned=*/ true, /*IsReplace=*/ false);
8365 SDValue FIST = Vals.first, StackSlot = Vals.second;
8366 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8367 if (FIST.getNode() == 0) return Op;
8369 if (StackSlot.getNode())
8371 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8372 FIST, StackSlot, MachinePointerInfo(),
8373 false, false, false, 0);
8375 // The node is the result.
8379 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8380 SelectionDAG &DAG) const {
8381 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8382 /*IsSigned=*/ false, /*IsReplace=*/ false);
8383 SDValue FIST = Vals.first, StackSlot = Vals.second;
8384 assert(FIST.getNode() && "Unexpected failure");
8386 if (StackSlot.getNode())
8388 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8389 FIST, StackSlot, MachinePointerInfo(),
8390 false, false, false, 0);
8392 // The node is the result.
8396 SDValue X86TargetLowering::lowerFP_EXTEND(SDValue Op,
8397 SelectionDAG &DAG) const {
8398 DebugLoc DL = Op.getDebugLoc();
8399 EVT VT = Op.getValueType();
8400 SDValue In = Op.getOperand(0);
8401 EVT SVT = In.getValueType();
8403 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8405 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8406 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8407 In, DAG.getUNDEF(SVT)));
8410 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8411 LLVMContext *Context = DAG.getContext();
8412 DebugLoc dl = Op.getDebugLoc();
8413 EVT VT = Op.getValueType();
8415 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8416 if (VT.isVector()) {
8417 EltVT = VT.getVectorElementType();
8418 NumElts = VT.getVectorNumElements();
8421 if (EltVT == MVT::f64)
8422 C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
8424 C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
8425 C = ConstantVector::getSplat(NumElts, C);
8426 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8427 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8428 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8429 MachinePointerInfo::getConstantPool(),
8430 false, false, false, Alignment);
8431 if (VT.isVector()) {
8432 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8433 return DAG.getNode(ISD::BITCAST, dl, VT,
8434 DAG.getNode(ISD::AND, dl, ANDVT,
8435 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8437 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8439 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8442 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8443 LLVMContext *Context = DAG.getContext();
8444 DebugLoc dl = Op.getDebugLoc();
8445 EVT VT = Op.getValueType();
8447 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8448 if (VT.isVector()) {
8449 EltVT = VT.getVectorElementType();
8450 NumElts = VT.getVectorNumElements();
8453 if (EltVT == MVT::f64)
8454 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8456 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8457 C = ConstantVector::getSplat(NumElts, C);
8458 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8459 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8460 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8461 MachinePointerInfo::getConstantPool(),
8462 false, false, false, Alignment);
8463 if (VT.isVector()) {
8464 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8465 return DAG.getNode(ISD::BITCAST, dl, VT,
8466 DAG.getNode(ISD::XOR, dl, XORVT,
8467 DAG.getNode(ISD::BITCAST, dl, XORVT,
8469 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8472 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8475 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8476 LLVMContext *Context = DAG.getContext();
8477 SDValue Op0 = Op.getOperand(0);
8478 SDValue Op1 = Op.getOperand(1);
8479 DebugLoc dl = Op.getDebugLoc();
8480 EVT VT = Op.getValueType();
8481 EVT SrcVT = Op1.getValueType();
8483 // If second operand is smaller, extend it first.
8484 if (SrcVT.bitsLT(VT)) {
8485 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8488 // And if it is bigger, shrink it first.
8489 if (SrcVT.bitsGT(VT)) {
8490 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8494 // At this point the operands and the result should have the same
8495 // type, and that won't be f80 since that is not custom lowered.
8497 // First get the sign bit of second operand.
8498 SmallVector<Constant*,4> CV;
8499 if (SrcVT == MVT::f64) {
8500 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8501 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8503 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8504 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8505 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8506 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8508 Constant *C = ConstantVector::get(CV);
8509 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8510 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8511 MachinePointerInfo::getConstantPool(),
8512 false, false, false, 16);
8513 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8515 // Shift sign bit right or left if the two operands have different types.
8516 if (SrcVT.bitsGT(VT)) {
8517 // Op0 is MVT::f32, Op1 is MVT::f64.
8518 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8519 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8520 DAG.getConstant(32, MVT::i32));
8521 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8522 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8523 DAG.getIntPtrConstant(0));
8526 // Clear first operand sign bit.
8528 if (VT == MVT::f64) {
8529 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8530 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8532 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8533 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8534 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8535 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8537 C = ConstantVector::get(CV);
8538 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8539 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8540 MachinePointerInfo::getConstantPool(),
8541 false, false, false, 16);
8542 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8544 // Or the value with the sign bit.
8545 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8548 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
8549 SDValue N0 = Op.getOperand(0);
8550 DebugLoc dl = Op.getDebugLoc();
8551 EVT VT = Op.getValueType();
8553 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8554 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8555 DAG.getConstant(1, VT));
8556 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8559 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
8561 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const {
8562 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8564 if (!Subtarget->hasSSE41())
8567 if (!Op->hasOneUse())
8570 SDNode *N = Op.getNode();
8571 DebugLoc DL = N->getDebugLoc();
8573 SmallVector<SDValue, 8> Opnds;
8574 DenseMap<SDValue, unsigned> VecInMap;
8575 EVT VT = MVT::Other;
8577 // Recognize a special case where a vector is casted into wide integer to
8579 Opnds.push_back(N->getOperand(0));
8580 Opnds.push_back(N->getOperand(1));
8582 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
8583 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot;
8584 // BFS traverse all OR'd operands.
8585 if (I->getOpcode() == ISD::OR) {
8586 Opnds.push_back(I->getOperand(0));
8587 Opnds.push_back(I->getOperand(1));
8588 // Re-evaluate the number of nodes to be traversed.
8589 e += 2; // 2 more nodes (LHS and RHS) are pushed.
8593 // Quit if a non-EXTRACT_VECTOR_ELT
8594 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8597 // Quit if without a constant index.
8598 SDValue Idx = I->getOperand(1);
8599 if (!isa<ConstantSDNode>(Idx))
8602 SDValue ExtractedFromVec = I->getOperand(0);
8603 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
8604 if (M == VecInMap.end()) {
8605 VT = ExtractedFromVec.getValueType();
8606 // Quit if not 128/256-bit vector.
8607 if (!VT.is128BitVector() && !VT.is256BitVector())
8609 // Quit if not the same type.
8610 if (VecInMap.begin() != VecInMap.end() &&
8611 VT != VecInMap.begin()->first.getValueType())
8613 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
8615 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
8618 assert((VT.is128BitVector() || VT.is256BitVector()) &&
8619 "Not extracted from 128-/256-bit vector.");
8621 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
8622 SmallVector<SDValue, 8> VecIns;
8624 for (DenseMap<SDValue, unsigned>::const_iterator
8625 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
8626 // Quit if not all elements are used.
8627 if (I->second != FullMask)
8629 VecIns.push_back(I->first);
8632 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8634 // Cast all vectors into TestVT for PTEST.
8635 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
8636 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8638 // If more than one full vectors are evaluated, OR them first before PTEST.
8639 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
8640 // Each iteration will OR 2 nodes and append the result until there is only
8641 // 1 node left, i.e. the final OR'd value of all vectors.
8642 SDValue LHS = VecIns[Slot];
8643 SDValue RHS = VecIns[Slot + 1];
8644 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8647 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
8648 VecIns.back(), VecIns.back());
8651 /// Emit nodes that will be selected as "test Op0,Op0", or something
8653 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8654 SelectionDAG &DAG) const {
8655 DebugLoc dl = Op.getDebugLoc();
8657 // CF and OF aren't always set the way we want. Determine which
8658 // of these we need.
8659 bool NeedCF = false;
8660 bool NeedOF = false;
8663 case X86::COND_A: case X86::COND_AE:
8664 case X86::COND_B: case X86::COND_BE:
8667 case X86::COND_G: case X86::COND_GE:
8668 case X86::COND_L: case X86::COND_LE:
8669 case X86::COND_O: case X86::COND_NO:
8674 // See if we can use the EFLAGS value from the operand instead of
8675 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8676 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8677 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8678 // Emit a CMP with 0, which is the TEST pattern.
8679 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8680 DAG.getConstant(0, Op.getValueType()));
8682 unsigned Opcode = 0;
8683 unsigned NumOperands = 0;
8685 // Truncate operations may prevent the merge of the SETCC instruction
8686 // and the arithmetic intruction before it. Attempt to truncate the operands
8687 // of the arithmetic instruction and use a reduced bit-width instruction.
8688 bool NeedTruncation = false;
8689 SDValue ArithOp = Op;
8690 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8691 SDValue Arith = Op->getOperand(0);
8692 // Both the trunc and the arithmetic op need to have one user each.
8693 if (Arith->hasOneUse())
8694 switch (Arith.getOpcode()) {
8701 NeedTruncation = true;
8707 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8708 // which may be the result of a CAST. We use the variable 'Op', which is the
8709 // non-casted variable when we check for possible users.
8710 switch (ArithOp.getOpcode()) {
8712 // Due to an isel shortcoming, be conservative if this add is likely to be
8713 // selected as part of a load-modify-store instruction. When the root node
8714 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8715 // uses of other nodes in the match, such as the ADD in this case. This
8716 // leads to the ADD being left around and reselected, with the result being
8717 // two adds in the output. Alas, even if none our users are stores, that
8718 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8719 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8720 // climbing the DAG back to the root, and it doesn't seem to be worth the
8722 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8723 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8724 if (UI->getOpcode() != ISD::CopyToReg &&
8725 UI->getOpcode() != ISD::SETCC &&
8726 UI->getOpcode() != ISD::STORE)
8729 if (ConstantSDNode *C =
8730 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8731 // An add of one will be selected as an INC.
8732 if (C->getAPIntValue() == 1) {
8733 Opcode = X86ISD::INC;
8738 // An add of negative one (subtract of one) will be selected as a DEC.
8739 if (C->getAPIntValue().isAllOnesValue()) {
8740 Opcode = X86ISD::DEC;
8746 // Otherwise use a regular EFLAGS-setting add.
8747 Opcode = X86ISD::ADD;
8751 // If the primary and result isn't used, don't bother using X86ISD::AND,
8752 // because a TEST instruction will be better.
8753 bool NonFlagUse = false;
8754 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8755 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8757 unsigned UOpNo = UI.getOperandNo();
8758 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8759 // Look pass truncate.
8760 UOpNo = User->use_begin().getOperandNo();
8761 User = *User->use_begin();
8764 if (User->getOpcode() != ISD::BRCOND &&
8765 User->getOpcode() != ISD::SETCC &&
8766 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8779 // Due to the ISEL shortcoming noted above, be conservative if this op is
8780 // likely to be selected as part of a load-modify-store instruction.
8781 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8782 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8783 if (UI->getOpcode() == ISD::STORE)
8786 // Otherwise use a regular EFLAGS-setting instruction.
8787 switch (ArithOp.getOpcode()) {
8788 default: llvm_unreachable("unexpected operator!");
8789 case ISD::SUB: Opcode = X86ISD::SUB; break;
8790 case ISD::XOR: Opcode = X86ISD::XOR; break;
8791 case ISD::AND: Opcode = X86ISD::AND; break;
8793 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
8794 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
8795 if (EFLAGS.getNode())
8798 Opcode = X86ISD::OR;
8812 return SDValue(Op.getNode(), 1);
8818 // If we found that truncation is beneficial, perform the truncation and
8820 if (NeedTruncation) {
8821 EVT VT = Op.getValueType();
8822 SDValue WideVal = Op->getOperand(0);
8823 EVT WideVT = WideVal.getValueType();
8824 unsigned ConvertedOp = 0;
8825 // Use a target machine opcode to prevent further DAGCombine
8826 // optimizations that may separate the arithmetic operations
8827 // from the setcc node.
8828 switch (WideVal.getOpcode()) {
8830 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
8831 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
8832 case ISD::AND: ConvertedOp = X86ISD::AND; break;
8833 case ISD::OR: ConvertedOp = X86ISD::OR; break;
8834 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
8838 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8839 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
8840 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
8841 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
8842 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
8848 // Emit a CMP with 0, which is the TEST pattern.
8849 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8850 DAG.getConstant(0, Op.getValueType()));
8852 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8853 SmallVector<SDValue, 4> Ops;
8854 for (unsigned i = 0; i != NumOperands; ++i)
8855 Ops.push_back(Op.getOperand(i));
8857 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8858 DAG.ReplaceAllUsesWith(Op, New);
8859 return SDValue(New.getNode(), 1);
8862 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8864 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8865 SelectionDAG &DAG) const {
8866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8867 if (C->getAPIntValue() == 0)
8868 return EmitTest(Op0, X86CC, DAG);
8870 DebugLoc dl = Op0.getDebugLoc();
8871 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
8872 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
8873 // Use SUB instead of CMP to enable CSE between SUB and CMP.
8874 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
8875 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
8877 return SDValue(Sub.getNode(), 1);
8879 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8882 /// Convert a comparison if required by the subtarget.
8883 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8884 SelectionDAG &DAG) const {
8885 // If the subtarget does not support the FUCOMI instruction, floating-point
8886 // comparisons have to be converted.
8887 if (Subtarget->hasCMov() ||
8888 Cmp.getOpcode() != X86ISD::CMP ||
8889 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8890 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8893 // The instruction selector will select an FUCOM instruction instead of
8894 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8895 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8896 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8897 DebugLoc dl = Cmp.getDebugLoc();
8898 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8899 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8900 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8901 DAG.getConstant(8, MVT::i8));
8902 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8903 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8906 static bool isAllOnes(SDValue V) {
8907 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8908 return C && C->isAllOnesValue();
8911 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8912 /// if it's possible.
8913 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8914 DebugLoc dl, SelectionDAG &DAG) const {
8915 SDValue Op0 = And.getOperand(0);
8916 SDValue Op1 = And.getOperand(1);
8917 if (Op0.getOpcode() == ISD::TRUNCATE)
8918 Op0 = Op0.getOperand(0);
8919 if (Op1.getOpcode() == ISD::TRUNCATE)
8920 Op1 = Op1.getOperand(0);
8923 if (Op1.getOpcode() == ISD::SHL)
8924 std::swap(Op0, Op1);
8925 if (Op0.getOpcode() == ISD::SHL) {
8926 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8927 if (And00C->getZExtValue() == 1) {
8928 // If we looked past a truncate, check that it's only truncating away
8930 unsigned BitWidth = Op0.getValueSizeInBits();
8931 unsigned AndBitWidth = And.getValueSizeInBits();
8932 if (BitWidth > AndBitWidth) {
8934 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8935 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8939 RHS = Op0.getOperand(1);
8941 } else if (Op1.getOpcode() == ISD::Constant) {
8942 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8943 uint64_t AndRHSVal = AndRHS->getZExtValue();
8944 SDValue AndLHS = Op0;
8946 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8947 LHS = AndLHS.getOperand(0);
8948 RHS = AndLHS.getOperand(1);
8951 // Use BT if the immediate can't be encoded in a TEST instruction.
8952 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8954 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8958 if (LHS.getNode()) {
8959 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip
8960 // the condition code later.
8961 bool Invert = false;
8962 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
8964 LHS = LHS.getOperand(0);
8967 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8968 // instruction. Since the shift amount is in-range-or-undefined, we know
8969 // that doing a bittest on the i32 value is ok. We extend to i32 because
8970 // the encoding for the i16 version is larger than the i32 version.
8971 // Also promote i16 to i32 for performance / code size reason.
8972 if (LHS.getValueType() == MVT::i8 ||
8973 LHS.getValueType() == MVT::i16)
8974 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8976 // If the operand types disagree, extend the shift amount to match. Since
8977 // BT ignores high bits (like shifts) we can use anyextend.
8978 if (LHS.getValueType() != RHS.getValueType())
8979 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8981 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8982 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8983 // Flip the condition if the LHS was a not instruction
8985 Cond = X86::GetOppositeBranchCondition(Cond);
8986 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8987 DAG.getConstant(Cond, MVT::i8), BT);
8993 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8995 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8997 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8998 SDValue Op0 = Op.getOperand(0);
8999 SDValue Op1 = Op.getOperand(1);
9000 DebugLoc dl = Op.getDebugLoc();
9001 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9003 // Optimize to BT if possible.
9004 // Lower (X & (1 << N)) == 0 to BT(X, N).
9005 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9006 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9007 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9008 Op1.getOpcode() == ISD::Constant &&
9009 cast<ConstantSDNode>(Op1)->isNullValue() &&
9010 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9011 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9012 if (NewSetCC.getNode())
9016 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9018 if (Op1.getOpcode() == ISD::Constant &&
9019 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9020 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9021 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9023 // If the input is a setcc, then reuse the input setcc or use a new one with
9024 // the inverted condition.
9025 if (Op0.getOpcode() == X86ISD::SETCC) {
9026 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9027 bool Invert = (CC == ISD::SETNE) ^
9028 cast<ConstantSDNode>(Op1)->isNullValue();
9029 if (!Invert) return Op0;
9031 CCode = X86::GetOppositeBranchCondition(CCode);
9032 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9033 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9037 bool isFP = Op1.getValueType().isFloatingPoint();
9038 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9039 if (X86CC == X86::COND_INVALID)
9042 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9043 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9044 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9045 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9048 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9049 // ones, and then concatenate the result back.
9050 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9051 EVT VT = Op.getValueType();
9053 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9054 "Unsupported value type for operation");
9056 unsigned NumElems = VT.getVectorNumElements();
9057 DebugLoc dl = Op.getDebugLoc();
9058 SDValue CC = Op.getOperand(2);
9060 // Extract the LHS vectors
9061 SDValue LHS = Op.getOperand(0);
9062 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9063 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9065 // Extract the RHS vectors
9066 SDValue RHS = Op.getOperand(1);
9067 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9068 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9070 // Issue the operation on the smaller types and concatenate the result back
9071 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9072 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9073 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9074 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9075 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9079 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
9081 SDValue Op0 = Op.getOperand(0);
9082 SDValue Op1 = Op.getOperand(1);
9083 SDValue CC = Op.getOperand(2);
9084 EVT VT = Op.getValueType();
9085 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9086 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
9087 DebugLoc dl = Op.getDebugLoc();
9091 EVT EltVT = Op0.getValueType().getVectorElementType();
9092 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9098 // SSE Condition code mapping:
9107 switch (SetCCOpcode) {
9108 default: llvm_unreachable("Unexpected SETCC condition");
9110 case ISD::SETEQ: SSECC = 0; break;
9112 case ISD::SETGT: Swap = true; // Fallthrough
9114 case ISD::SETOLT: SSECC = 1; break;
9116 case ISD::SETGE: Swap = true; // Fallthrough
9118 case ISD::SETOLE: SSECC = 2; break;
9119 case ISD::SETUO: SSECC = 3; break;
9121 case ISD::SETNE: SSECC = 4; break;
9122 case ISD::SETULE: Swap = true; // Fallthrough
9123 case ISD::SETUGE: SSECC = 5; break;
9124 case ISD::SETULT: Swap = true; // Fallthrough
9125 case ISD::SETUGT: SSECC = 6; break;
9126 case ISD::SETO: SSECC = 7; break;
9128 case ISD::SETONE: SSECC = 8; break;
9131 std::swap(Op0, Op1);
9133 // In the two special cases we can't handle, emit two comparisons.
9136 unsigned CombineOpc;
9137 if (SetCCOpcode == ISD::SETUEQ) {
9138 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9140 assert(SetCCOpcode == ISD::SETONE);
9141 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9144 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9145 DAG.getConstant(CC0, MVT::i8));
9146 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9147 DAG.getConstant(CC1, MVT::i8));
9148 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9150 // Handle all other FP comparisons here.
9151 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9152 DAG.getConstant(SSECC, MVT::i8));
9155 // Break 256-bit integer vector compare into smaller ones.
9156 if (VT.is256BitVector() && !Subtarget->hasInt256())
9157 return Lower256IntVSETCC(Op, DAG);
9159 // We are handling one of the integer comparisons here. Since SSE only has
9160 // GT and EQ comparisons for integer, swapping operands and multiple
9161 // operations may be required for some comparisons.
9163 bool Swap = false, Invert = false, FlipSigns = false;
9165 switch (SetCCOpcode) {
9166 default: llvm_unreachable("Unexpected SETCC condition");
9167 case ISD::SETNE: Invert = true;
9168 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9169 case ISD::SETLT: Swap = true;
9170 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9171 case ISD::SETGE: Swap = true;
9172 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9173 case ISD::SETULT: Swap = true;
9174 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9175 case ISD::SETUGE: Swap = true;
9176 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9179 std::swap(Op0, Op1);
9181 // Check that the operation in question is available (most are plain SSE2,
9182 // but PCMPGTQ and PCMPEQQ have different requirements).
9183 if (VT == MVT::v2i64) {
9184 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
9186 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41())
9190 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9191 // bits of the inputs before performing those operations.
9193 EVT EltVT = VT.getVectorElementType();
9194 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
9196 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
9197 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9199 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9200 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9203 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9205 // If the logical-not of the result is required, perform that now.
9207 Result = DAG.getNOT(dl, Result, VT);
9212 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9213 static bool isX86LogicalCmp(SDValue Op) {
9214 unsigned Opc = Op.getNode()->getOpcode();
9215 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9216 Opc == X86ISD::SAHF)
9218 if (Op.getResNo() == 1 &&
9219 (Opc == X86ISD::ADD ||
9220 Opc == X86ISD::SUB ||
9221 Opc == X86ISD::ADC ||
9222 Opc == X86ISD::SBB ||
9223 Opc == X86ISD::SMUL ||
9224 Opc == X86ISD::UMUL ||
9225 Opc == X86ISD::INC ||
9226 Opc == X86ISD::DEC ||
9227 Opc == X86ISD::OR ||
9228 Opc == X86ISD::XOR ||
9229 Opc == X86ISD::AND))
9232 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9238 static bool isZero(SDValue V) {
9239 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9240 return C && C->isNullValue();
9243 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9244 if (V.getOpcode() != ISD::TRUNCATE)
9247 SDValue VOp0 = V.getOperand(0);
9248 unsigned InBits = VOp0.getValueSizeInBits();
9249 unsigned Bits = V.getValueSizeInBits();
9250 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9253 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9254 bool addTest = true;
9255 SDValue Cond = Op.getOperand(0);
9256 SDValue Op1 = Op.getOperand(1);
9257 SDValue Op2 = Op.getOperand(2);
9258 DebugLoc DL = Op.getDebugLoc();
9261 if (Cond.getOpcode() == ISD::SETCC) {
9262 SDValue NewCond = LowerSETCC(Cond, DAG);
9263 if (NewCond.getNode())
9267 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9268 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9269 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9270 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9271 if (Cond.getOpcode() == X86ISD::SETCC &&
9272 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9273 isZero(Cond.getOperand(1).getOperand(1))) {
9274 SDValue Cmp = Cond.getOperand(1);
9276 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9278 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9279 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9280 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9282 SDValue CmpOp0 = Cmp.getOperand(0);
9283 // Apply further optimizations for special cases
9284 // (select (x != 0), -1, 0) -> neg & sbb
9285 // (select (x == 0), 0, -1) -> neg & sbb
9286 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9287 if (YC->isNullValue() &&
9288 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9289 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9290 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9291 DAG.getConstant(0, CmpOp0.getValueType()),
9293 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9294 DAG.getConstant(X86::COND_B, MVT::i8),
9295 SDValue(Neg.getNode(), 1));
9299 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9300 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9301 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9303 SDValue Res = // Res = 0 or -1.
9304 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9305 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9307 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9308 Res = DAG.getNOT(DL, Res, Res.getValueType());
9310 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9311 if (N2C == 0 || !N2C->isNullValue())
9312 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9317 // Look past (and (setcc_carry (cmp ...)), 1).
9318 if (Cond.getOpcode() == ISD::AND &&
9319 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9320 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9321 if (C && C->getAPIntValue() == 1)
9322 Cond = Cond.getOperand(0);
9325 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9326 // setting operand in place of the X86ISD::SETCC.
9327 unsigned CondOpcode = Cond.getOpcode();
9328 if (CondOpcode == X86ISD::SETCC ||
9329 CondOpcode == X86ISD::SETCC_CARRY) {
9330 CC = Cond.getOperand(0);
9332 SDValue Cmp = Cond.getOperand(1);
9333 unsigned Opc = Cmp.getOpcode();
9334 EVT VT = Op.getValueType();
9336 bool IllegalFPCMov = false;
9337 if (VT.isFloatingPoint() && !VT.isVector() &&
9338 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9339 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9341 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9342 Opc == X86ISD::BT) { // FIXME
9346 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9347 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9348 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9349 Cond.getOperand(0).getValueType() != MVT::i8)) {
9350 SDValue LHS = Cond.getOperand(0);
9351 SDValue RHS = Cond.getOperand(1);
9355 switch (CondOpcode) {
9356 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9357 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9358 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9359 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9360 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9361 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9362 default: llvm_unreachable("unexpected overflowing operator");
9364 if (CondOpcode == ISD::UMULO)
9365 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9368 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9370 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9372 if (CondOpcode == ISD::UMULO)
9373 Cond = X86Op.getValue(2);
9375 Cond = X86Op.getValue(1);
9377 CC = DAG.getConstant(X86Cond, MVT::i8);
9382 // Look pass the truncate if the high bits are known zero.
9383 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9384 Cond = Cond.getOperand(0);
9386 // We know the result of AND is compared against zero. Try to match
9388 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9389 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9390 if (NewSetCC.getNode()) {
9391 CC = NewSetCC.getOperand(0);
9392 Cond = NewSetCC.getOperand(1);
9399 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9400 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9403 // a < b ? -1 : 0 -> RES = ~setcc_carry
9404 // a < b ? 0 : -1 -> RES = setcc_carry
9405 // a >= b ? -1 : 0 -> RES = setcc_carry
9406 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9407 if (Cond.getOpcode() == X86ISD::SUB) {
9408 Cond = ConvertCmpIfNecessary(Cond, DAG);
9409 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9411 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9412 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9413 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9414 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9415 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9416 return DAG.getNOT(DL, Res, Res.getValueType());
9421 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9422 // widen the cmov and push the truncate through. This avoids introducing a new
9423 // branch during isel and doesn't add any extensions.
9424 if (Op.getValueType() == MVT::i8 &&
9425 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9426 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
9427 if (T1.getValueType() == T2.getValueType() &&
9428 // Blacklist CopyFromReg to avoid partial register stalls.
9429 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9430 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
9431 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
9432 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9436 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9437 // condition is true.
9438 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9439 SDValue Ops[] = { Op2, Op1, CC, Cond };
9440 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9443 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9444 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9445 // from the AND / OR.
9446 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9447 Opc = Op.getOpcode();
9448 if (Opc != ISD::OR && Opc != ISD::AND)
9450 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9451 Op.getOperand(0).hasOneUse() &&
9452 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9453 Op.getOperand(1).hasOneUse());
9456 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9457 // 1 and that the SETCC node has a single use.
9458 static bool isXor1OfSetCC(SDValue Op) {
9459 if (Op.getOpcode() != ISD::XOR)
9461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9462 if (N1C && N1C->getAPIntValue() == 1) {
9463 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9464 Op.getOperand(0).hasOneUse();
9469 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9470 bool addTest = true;
9471 SDValue Chain = Op.getOperand(0);
9472 SDValue Cond = Op.getOperand(1);
9473 SDValue Dest = Op.getOperand(2);
9474 DebugLoc dl = Op.getDebugLoc();
9476 bool Inverted = false;
9478 if (Cond.getOpcode() == ISD::SETCC) {
9479 // Check for setcc([su]{add,sub,mul}o == 0).
9480 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9481 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9482 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9483 Cond.getOperand(0).getResNo() == 1 &&
9484 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9485 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9486 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9487 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9488 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9489 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9491 Cond = Cond.getOperand(0);
9493 SDValue NewCond = LowerSETCC(Cond, DAG);
9494 if (NewCond.getNode())
9499 // FIXME: LowerXALUO doesn't handle these!!
9500 else if (Cond.getOpcode() == X86ISD::ADD ||
9501 Cond.getOpcode() == X86ISD::SUB ||
9502 Cond.getOpcode() == X86ISD::SMUL ||
9503 Cond.getOpcode() == X86ISD::UMUL)
9504 Cond = LowerXALUO(Cond, DAG);
9507 // Look pass (and (setcc_carry (cmp ...)), 1).
9508 if (Cond.getOpcode() == ISD::AND &&
9509 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9510 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9511 if (C && C->getAPIntValue() == 1)
9512 Cond = Cond.getOperand(0);
9515 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9516 // setting operand in place of the X86ISD::SETCC.
9517 unsigned CondOpcode = Cond.getOpcode();
9518 if (CondOpcode == X86ISD::SETCC ||
9519 CondOpcode == X86ISD::SETCC_CARRY) {
9520 CC = Cond.getOperand(0);
9522 SDValue Cmp = Cond.getOperand(1);
9523 unsigned Opc = Cmp.getOpcode();
9524 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9525 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9529 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9533 // These can only come from an arithmetic instruction with overflow,
9534 // e.g. SADDO, UADDO.
9535 Cond = Cond.getNode()->getOperand(1);
9541 CondOpcode = Cond.getOpcode();
9542 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9543 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9544 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9545 Cond.getOperand(0).getValueType() != MVT::i8)) {
9546 SDValue LHS = Cond.getOperand(0);
9547 SDValue RHS = Cond.getOperand(1);
9551 switch (CondOpcode) {
9552 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9553 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9554 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9555 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9556 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9557 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9558 default: llvm_unreachable("unexpected overflowing operator");
9561 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9562 if (CondOpcode == ISD::UMULO)
9563 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9566 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9568 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9570 if (CondOpcode == ISD::UMULO)
9571 Cond = X86Op.getValue(2);
9573 Cond = X86Op.getValue(1);
9575 CC = DAG.getConstant(X86Cond, MVT::i8);
9579 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9580 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9581 if (CondOpc == ISD::OR) {
9582 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9583 // two branches instead of an explicit OR instruction with a
9585 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9586 isX86LogicalCmp(Cmp)) {
9587 CC = Cond.getOperand(0).getOperand(0);
9588 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9589 Chain, Dest, CC, Cmp);
9590 CC = Cond.getOperand(1).getOperand(0);
9594 } else { // ISD::AND
9595 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9596 // two branches instead of an explicit AND instruction with a
9597 // separate test. However, we only do this if this block doesn't
9598 // have a fall-through edge, because this requires an explicit
9599 // jmp when the condition is false.
9600 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9601 isX86LogicalCmp(Cmp) &&
9602 Op.getNode()->hasOneUse()) {
9603 X86::CondCode CCode =
9604 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9605 CCode = X86::GetOppositeBranchCondition(CCode);
9606 CC = DAG.getConstant(CCode, MVT::i8);
9607 SDNode *User = *Op.getNode()->use_begin();
9608 // Look for an unconditional branch following this conditional branch.
9609 // We need this because we need to reverse the successors in order
9610 // to implement FCMP_OEQ.
9611 if (User->getOpcode() == ISD::BR) {
9612 SDValue FalseBB = User->getOperand(1);
9614 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9615 assert(NewBR == User);
9619 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9620 Chain, Dest, CC, Cmp);
9621 X86::CondCode CCode =
9622 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9623 CCode = X86::GetOppositeBranchCondition(CCode);
9624 CC = DAG.getConstant(CCode, MVT::i8);
9630 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9631 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9632 // It should be transformed during dag combiner except when the condition
9633 // is set by a arithmetics with overflow node.
9634 X86::CondCode CCode =
9635 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9636 CCode = X86::GetOppositeBranchCondition(CCode);
9637 CC = DAG.getConstant(CCode, MVT::i8);
9638 Cond = Cond.getOperand(0).getOperand(1);
9640 } else if (Cond.getOpcode() == ISD::SETCC &&
9641 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9642 // For FCMP_OEQ, we can emit
9643 // two branches instead of an explicit AND instruction with a
9644 // separate test. However, we only do this if this block doesn't
9645 // have a fall-through edge, because this requires an explicit
9646 // jmp when the condition is false.
9647 if (Op.getNode()->hasOneUse()) {
9648 SDNode *User = *Op.getNode()->use_begin();
9649 // Look for an unconditional branch following this conditional branch.
9650 // We need this because we need to reverse the successors in order
9651 // to implement FCMP_OEQ.
9652 if (User->getOpcode() == ISD::BR) {
9653 SDValue FalseBB = User->getOperand(1);
9655 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9656 assert(NewBR == User);
9660 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9661 Cond.getOperand(0), Cond.getOperand(1));
9662 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9663 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9664 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9665 Chain, Dest, CC, Cmp);
9666 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9671 } else if (Cond.getOpcode() == ISD::SETCC &&
9672 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9673 // For FCMP_UNE, we can emit
9674 // two branches instead of an explicit AND instruction with a
9675 // separate test. However, we only do this if this block doesn't
9676 // have a fall-through edge, because this requires an explicit
9677 // jmp when the condition is false.
9678 if (Op.getNode()->hasOneUse()) {
9679 SDNode *User = *Op.getNode()->use_begin();
9680 // Look for an unconditional branch following this conditional branch.
9681 // We need this because we need to reverse the successors in order
9682 // to implement FCMP_UNE.
9683 if (User->getOpcode() == ISD::BR) {
9684 SDValue FalseBB = User->getOperand(1);
9686 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9687 assert(NewBR == User);
9690 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9691 Cond.getOperand(0), Cond.getOperand(1));
9692 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9693 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9694 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9695 Chain, Dest, CC, Cmp);
9696 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9706 // Look pass the truncate if the high bits are known zero.
9707 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9708 Cond = Cond.getOperand(0);
9710 // We know the result of AND is compared against zero. Try to match
9712 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9713 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9714 if (NewSetCC.getNode()) {
9715 CC = NewSetCC.getOperand(0);
9716 Cond = NewSetCC.getOperand(1);
9723 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9724 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9726 Cond = ConvertCmpIfNecessary(Cond, DAG);
9727 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9728 Chain, Dest, CC, Cond);
9732 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9733 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9734 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9735 // that the guard pages used by the OS virtual memory manager are allocated in
9736 // correct sequence.
9738 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9739 SelectionDAG &DAG) const {
9740 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9741 getTargetMachine().Options.EnableSegmentedStacks) &&
9742 "This should be used only on Windows targets or when segmented stacks "
9744 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9745 DebugLoc dl = Op.getDebugLoc();
9748 SDValue Chain = Op.getOperand(0);
9749 SDValue Size = Op.getOperand(1);
9750 // FIXME: Ensure alignment here
9752 bool Is64Bit = Subtarget->is64Bit();
9753 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9755 if (getTargetMachine().Options.EnableSegmentedStacks) {
9756 MachineFunction &MF = DAG.getMachineFunction();
9757 MachineRegisterInfo &MRI = MF.getRegInfo();
9760 // The 64 bit implementation of segmented stacks needs to clobber both r10
9761 // r11. This makes it impossible to use it along with nested parameters.
9762 const Function *F = MF.getFunction();
9764 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9766 if (I->hasNestAttr())
9767 report_fatal_error("Cannot use segmented stacks with functions that "
9768 "have nested arguments.");
9771 const TargetRegisterClass *AddrRegClass =
9772 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9773 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9774 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9775 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9776 DAG.getRegister(Vreg, SPTy));
9777 SDValue Ops1[2] = { Value, Chain };
9778 return DAG.getMergeValues(Ops1, 2, dl);
9781 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9783 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9784 Flag = Chain.getValue(1);
9785 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9787 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9788 Flag = Chain.getValue(1);
9790 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
9793 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9794 return DAG.getMergeValues(Ops1, 2, dl);
9798 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9799 MachineFunction &MF = DAG.getMachineFunction();
9800 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9802 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9803 DebugLoc DL = Op.getDebugLoc();
9805 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9806 // vastart just stores the address of the VarArgsFrameIndex slot into the
9807 // memory location argument.
9808 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9810 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9811 MachinePointerInfo(SV), false, false, 0);
9815 // gp_offset (0 - 6 * 8)
9816 // fp_offset (48 - 48 + 8 * 16)
9817 // overflow_arg_area (point to parameters coming in memory).
9819 SmallVector<SDValue, 8> MemOps;
9820 SDValue FIN = Op.getOperand(1);
9822 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9823 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9825 FIN, MachinePointerInfo(SV), false, false, 0);
9826 MemOps.push_back(Store);
9829 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9830 FIN, DAG.getIntPtrConstant(4));
9831 Store = DAG.getStore(Op.getOperand(0), DL,
9832 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9834 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9835 MemOps.push_back(Store);
9837 // Store ptr to overflow_arg_area
9838 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9839 FIN, DAG.getIntPtrConstant(4));
9840 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9842 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9843 MachinePointerInfo(SV, 8),
9845 MemOps.push_back(Store);
9847 // Store ptr to reg_save_area.
9848 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9849 FIN, DAG.getIntPtrConstant(8));
9850 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9852 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9853 MachinePointerInfo(SV, 16), false, false, 0);
9854 MemOps.push_back(Store);
9855 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9856 &MemOps[0], MemOps.size());
9859 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9860 assert(Subtarget->is64Bit() &&
9861 "LowerVAARG only handles 64-bit va_arg!");
9862 assert((Subtarget->isTargetLinux() ||
9863 Subtarget->isTargetDarwin()) &&
9864 "Unhandled target in LowerVAARG");
9865 assert(Op.getNode()->getNumOperands() == 4);
9866 SDValue Chain = Op.getOperand(0);
9867 SDValue SrcPtr = Op.getOperand(1);
9868 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9869 unsigned Align = Op.getConstantOperandVal(3);
9870 DebugLoc dl = Op.getDebugLoc();
9872 EVT ArgVT = Op.getNode()->getValueType(0);
9873 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9874 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
9877 // Decide which area this value should be read from.
9878 // TODO: Implement the AMD64 ABI in its entirety. This simple
9879 // selection mechanism works only for the basic types.
9880 if (ArgVT == MVT::f80) {
9881 llvm_unreachable("va_arg for f80 not yet implemented");
9882 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9883 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9884 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9885 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9887 llvm_unreachable("Unhandled argument type in LowerVAARG");
9891 // Sanity Check: Make sure using fp_offset makes sense.
9892 assert(!getTargetMachine().Options.UseSoftFloat &&
9893 !(DAG.getMachineFunction()
9894 .getFunction()->getFnAttributes()
9895 .hasAttribute(Attribute::NoImplicitFloat)) &&
9896 Subtarget->hasSSE1());
9899 // Insert VAARG_64 node into the DAG
9900 // VAARG_64 returns two values: Variable Argument Address, Chain
9901 SmallVector<SDValue, 11> InstOps;
9902 InstOps.push_back(Chain);
9903 InstOps.push_back(SrcPtr);
9904 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9905 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9906 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9907 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9908 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9909 VTs, &InstOps[0], InstOps.size(),
9911 MachinePointerInfo(SV),
9916 Chain = VAARG.getValue(1);
9918 // Load the next argument and return it
9919 return DAG.getLoad(ArgVT, dl,
9922 MachinePointerInfo(),
9923 false, false, false, 0);
9926 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
9927 SelectionDAG &DAG) {
9928 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9929 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9930 SDValue Chain = Op.getOperand(0);
9931 SDValue DstPtr = Op.getOperand(1);
9932 SDValue SrcPtr = Op.getOperand(2);
9933 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9934 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9935 DebugLoc DL = Op.getDebugLoc();
9937 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9938 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9940 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9943 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9944 // may or may not be a constant. Takes immediate version of shift as input.
9945 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9946 SDValue SrcOp, SDValue ShAmt,
9947 SelectionDAG &DAG) {
9948 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9950 if (isa<ConstantSDNode>(ShAmt)) {
9951 // Constant may be a TargetConstant. Use a regular constant.
9952 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
9954 default: llvm_unreachable("Unknown target vector shift node");
9958 return DAG.getNode(Opc, dl, VT, SrcOp,
9959 DAG.getConstant(ShiftAmt, MVT::i32));
9963 // Change opcode to non-immediate version
9965 default: llvm_unreachable("Unknown target vector shift node");
9966 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9967 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9968 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9971 // Need to build a vector containing shift amount
9972 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9975 ShOps[1] = DAG.getConstant(0, MVT::i32);
9976 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
9977 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9979 // The return type has to be a 128-bit type with the same element
9980 // type as the input type.
9981 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9982 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
9984 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
9985 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9988 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
9989 DebugLoc dl = Op.getDebugLoc();
9990 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9992 default: return SDValue(); // Don't custom lower most intrinsics.
9993 // Comparison intrinsics.
9994 case Intrinsic::x86_sse_comieq_ss:
9995 case Intrinsic::x86_sse_comilt_ss:
9996 case Intrinsic::x86_sse_comile_ss:
9997 case Intrinsic::x86_sse_comigt_ss:
9998 case Intrinsic::x86_sse_comige_ss:
9999 case Intrinsic::x86_sse_comineq_ss:
10000 case Intrinsic::x86_sse_ucomieq_ss:
10001 case Intrinsic::x86_sse_ucomilt_ss:
10002 case Intrinsic::x86_sse_ucomile_ss:
10003 case Intrinsic::x86_sse_ucomigt_ss:
10004 case Intrinsic::x86_sse_ucomige_ss:
10005 case Intrinsic::x86_sse_ucomineq_ss:
10006 case Intrinsic::x86_sse2_comieq_sd:
10007 case Intrinsic::x86_sse2_comilt_sd:
10008 case Intrinsic::x86_sse2_comile_sd:
10009 case Intrinsic::x86_sse2_comigt_sd:
10010 case Intrinsic::x86_sse2_comige_sd:
10011 case Intrinsic::x86_sse2_comineq_sd:
10012 case Intrinsic::x86_sse2_ucomieq_sd:
10013 case Intrinsic::x86_sse2_ucomilt_sd:
10014 case Intrinsic::x86_sse2_ucomile_sd:
10015 case Intrinsic::x86_sse2_ucomigt_sd:
10016 case Intrinsic::x86_sse2_ucomige_sd:
10017 case Intrinsic::x86_sse2_ucomineq_sd: {
10021 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10022 case Intrinsic::x86_sse_comieq_ss:
10023 case Intrinsic::x86_sse2_comieq_sd:
10024 Opc = X86ISD::COMI;
10027 case Intrinsic::x86_sse_comilt_ss:
10028 case Intrinsic::x86_sse2_comilt_sd:
10029 Opc = X86ISD::COMI;
10032 case Intrinsic::x86_sse_comile_ss:
10033 case Intrinsic::x86_sse2_comile_sd:
10034 Opc = X86ISD::COMI;
10037 case Intrinsic::x86_sse_comigt_ss:
10038 case Intrinsic::x86_sse2_comigt_sd:
10039 Opc = X86ISD::COMI;
10042 case Intrinsic::x86_sse_comige_ss:
10043 case Intrinsic::x86_sse2_comige_sd:
10044 Opc = X86ISD::COMI;
10047 case Intrinsic::x86_sse_comineq_ss:
10048 case Intrinsic::x86_sse2_comineq_sd:
10049 Opc = X86ISD::COMI;
10052 case Intrinsic::x86_sse_ucomieq_ss:
10053 case Intrinsic::x86_sse2_ucomieq_sd:
10054 Opc = X86ISD::UCOMI;
10057 case Intrinsic::x86_sse_ucomilt_ss:
10058 case Intrinsic::x86_sse2_ucomilt_sd:
10059 Opc = X86ISD::UCOMI;
10062 case Intrinsic::x86_sse_ucomile_ss:
10063 case Intrinsic::x86_sse2_ucomile_sd:
10064 Opc = X86ISD::UCOMI;
10067 case Intrinsic::x86_sse_ucomigt_ss:
10068 case Intrinsic::x86_sse2_ucomigt_sd:
10069 Opc = X86ISD::UCOMI;
10072 case Intrinsic::x86_sse_ucomige_ss:
10073 case Intrinsic::x86_sse2_ucomige_sd:
10074 Opc = X86ISD::UCOMI;
10077 case Intrinsic::x86_sse_ucomineq_ss:
10078 case Intrinsic::x86_sse2_ucomineq_sd:
10079 Opc = X86ISD::UCOMI;
10084 SDValue LHS = Op.getOperand(1);
10085 SDValue RHS = Op.getOperand(2);
10086 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10087 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10088 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10089 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10090 DAG.getConstant(X86CC, MVT::i8), Cond);
10091 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10094 // Arithmetic intrinsics.
10095 case Intrinsic::x86_sse2_pmulu_dq:
10096 case Intrinsic::x86_avx2_pmulu_dq:
10097 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10098 Op.getOperand(1), Op.getOperand(2));
10100 // SSE2/AVX2 sub with unsigned saturation intrinsics
10101 case Intrinsic::x86_sse2_psubus_b:
10102 case Intrinsic::x86_sse2_psubus_w:
10103 case Intrinsic::x86_avx2_psubus_b:
10104 case Intrinsic::x86_avx2_psubus_w:
10105 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10106 Op.getOperand(1), Op.getOperand(2));
10108 // SSE3/AVX horizontal add/sub intrinsics
10109 case Intrinsic::x86_sse3_hadd_ps:
10110 case Intrinsic::x86_sse3_hadd_pd:
10111 case Intrinsic::x86_avx_hadd_ps_256:
10112 case Intrinsic::x86_avx_hadd_pd_256:
10113 case Intrinsic::x86_sse3_hsub_ps:
10114 case Intrinsic::x86_sse3_hsub_pd:
10115 case Intrinsic::x86_avx_hsub_ps_256:
10116 case Intrinsic::x86_avx_hsub_pd_256:
10117 case Intrinsic::x86_ssse3_phadd_w_128:
10118 case Intrinsic::x86_ssse3_phadd_d_128:
10119 case Intrinsic::x86_avx2_phadd_w:
10120 case Intrinsic::x86_avx2_phadd_d:
10121 case Intrinsic::x86_ssse3_phsub_w_128:
10122 case Intrinsic::x86_ssse3_phsub_d_128:
10123 case Intrinsic::x86_avx2_phsub_w:
10124 case Intrinsic::x86_avx2_phsub_d: {
10127 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10128 case Intrinsic::x86_sse3_hadd_ps:
10129 case Intrinsic::x86_sse3_hadd_pd:
10130 case Intrinsic::x86_avx_hadd_ps_256:
10131 case Intrinsic::x86_avx_hadd_pd_256:
10132 Opcode = X86ISD::FHADD;
10134 case Intrinsic::x86_sse3_hsub_ps:
10135 case Intrinsic::x86_sse3_hsub_pd:
10136 case Intrinsic::x86_avx_hsub_ps_256:
10137 case Intrinsic::x86_avx_hsub_pd_256:
10138 Opcode = X86ISD::FHSUB;
10140 case Intrinsic::x86_ssse3_phadd_w_128:
10141 case Intrinsic::x86_ssse3_phadd_d_128:
10142 case Intrinsic::x86_avx2_phadd_w:
10143 case Intrinsic::x86_avx2_phadd_d:
10144 Opcode = X86ISD::HADD;
10146 case Intrinsic::x86_ssse3_phsub_w_128:
10147 case Intrinsic::x86_ssse3_phsub_d_128:
10148 case Intrinsic::x86_avx2_phsub_w:
10149 case Intrinsic::x86_avx2_phsub_d:
10150 Opcode = X86ISD::HSUB;
10153 return DAG.getNode(Opcode, dl, Op.getValueType(),
10154 Op.getOperand(1), Op.getOperand(2));
10157 // AVX2 variable shift intrinsics
10158 case Intrinsic::x86_avx2_psllv_d:
10159 case Intrinsic::x86_avx2_psllv_q:
10160 case Intrinsic::x86_avx2_psllv_d_256:
10161 case Intrinsic::x86_avx2_psllv_q_256:
10162 case Intrinsic::x86_avx2_psrlv_d:
10163 case Intrinsic::x86_avx2_psrlv_q:
10164 case Intrinsic::x86_avx2_psrlv_d_256:
10165 case Intrinsic::x86_avx2_psrlv_q_256:
10166 case Intrinsic::x86_avx2_psrav_d:
10167 case Intrinsic::x86_avx2_psrav_d_256: {
10170 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10171 case Intrinsic::x86_avx2_psllv_d:
10172 case Intrinsic::x86_avx2_psllv_q:
10173 case Intrinsic::x86_avx2_psllv_d_256:
10174 case Intrinsic::x86_avx2_psllv_q_256:
10177 case Intrinsic::x86_avx2_psrlv_d:
10178 case Intrinsic::x86_avx2_psrlv_q:
10179 case Intrinsic::x86_avx2_psrlv_d_256:
10180 case Intrinsic::x86_avx2_psrlv_q_256:
10183 case Intrinsic::x86_avx2_psrav_d:
10184 case Intrinsic::x86_avx2_psrav_d_256:
10188 return DAG.getNode(Opcode, dl, Op.getValueType(),
10189 Op.getOperand(1), Op.getOperand(2));
10192 case Intrinsic::x86_ssse3_pshuf_b_128:
10193 case Intrinsic::x86_avx2_pshuf_b:
10194 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10195 Op.getOperand(1), Op.getOperand(2));
10197 case Intrinsic::x86_ssse3_psign_b_128:
10198 case Intrinsic::x86_ssse3_psign_w_128:
10199 case Intrinsic::x86_ssse3_psign_d_128:
10200 case Intrinsic::x86_avx2_psign_b:
10201 case Intrinsic::x86_avx2_psign_w:
10202 case Intrinsic::x86_avx2_psign_d:
10203 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10204 Op.getOperand(1), Op.getOperand(2));
10206 case Intrinsic::x86_sse41_insertps:
10207 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10208 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10210 case Intrinsic::x86_avx_vperm2f128_ps_256:
10211 case Intrinsic::x86_avx_vperm2f128_pd_256:
10212 case Intrinsic::x86_avx_vperm2f128_si_256:
10213 case Intrinsic::x86_avx2_vperm2i128:
10214 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10215 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10217 case Intrinsic::x86_avx2_permd:
10218 case Intrinsic::x86_avx2_permps:
10219 // Operands intentionally swapped. Mask is last operand to intrinsic,
10220 // but second operand for node/intruction.
10221 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10222 Op.getOperand(2), Op.getOperand(1));
10224 // ptest and testp intrinsics. The intrinsic these come from are designed to
10225 // return an integer value, not just an instruction so lower it to the ptest
10226 // or testp pattern and a setcc for the result.
10227 case Intrinsic::x86_sse41_ptestz:
10228 case Intrinsic::x86_sse41_ptestc:
10229 case Intrinsic::x86_sse41_ptestnzc:
10230 case Intrinsic::x86_avx_ptestz_256:
10231 case Intrinsic::x86_avx_ptestc_256:
10232 case Intrinsic::x86_avx_ptestnzc_256:
10233 case Intrinsic::x86_avx_vtestz_ps:
10234 case Intrinsic::x86_avx_vtestc_ps:
10235 case Intrinsic::x86_avx_vtestnzc_ps:
10236 case Intrinsic::x86_avx_vtestz_pd:
10237 case Intrinsic::x86_avx_vtestc_pd:
10238 case Intrinsic::x86_avx_vtestnzc_pd:
10239 case Intrinsic::x86_avx_vtestz_ps_256:
10240 case Intrinsic::x86_avx_vtestc_ps_256:
10241 case Intrinsic::x86_avx_vtestnzc_ps_256:
10242 case Intrinsic::x86_avx_vtestz_pd_256:
10243 case Intrinsic::x86_avx_vtestc_pd_256:
10244 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10245 bool IsTestPacked = false;
10248 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10249 case Intrinsic::x86_avx_vtestz_ps:
10250 case Intrinsic::x86_avx_vtestz_pd:
10251 case Intrinsic::x86_avx_vtestz_ps_256:
10252 case Intrinsic::x86_avx_vtestz_pd_256:
10253 IsTestPacked = true; // Fallthrough
10254 case Intrinsic::x86_sse41_ptestz:
10255 case Intrinsic::x86_avx_ptestz_256:
10257 X86CC = X86::COND_E;
10259 case Intrinsic::x86_avx_vtestc_ps:
10260 case Intrinsic::x86_avx_vtestc_pd:
10261 case Intrinsic::x86_avx_vtestc_ps_256:
10262 case Intrinsic::x86_avx_vtestc_pd_256:
10263 IsTestPacked = true; // Fallthrough
10264 case Intrinsic::x86_sse41_ptestc:
10265 case Intrinsic::x86_avx_ptestc_256:
10267 X86CC = X86::COND_B;
10269 case Intrinsic::x86_avx_vtestnzc_ps:
10270 case Intrinsic::x86_avx_vtestnzc_pd:
10271 case Intrinsic::x86_avx_vtestnzc_ps_256:
10272 case Intrinsic::x86_avx_vtestnzc_pd_256:
10273 IsTestPacked = true; // Fallthrough
10274 case Intrinsic::x86_sse41_ptestnzc:
10275 case Intrinsic::x86_avx_ptestnzc_256:
10277 X86CC = X86::COND_A;
10281 SDValue LHS = Op.getOperand(1);
10282 SDValue RHS = Op.getOperand(2);
10283 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
10284 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
10285 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
10286 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10287 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10290 // SSE/AVX shift intrinsics
10291 case Intrinsic::x86_sse2_psll_w:
10292 case Intrinsic::x86_sse2_psll_d:
10293 case Intrinsic::x86_sse2_psll_q:
10294 case Intrinsic::x86_avx2_psll_w:
10295 case Intrinsic::x86_avx2_psll_d:
10296 case Intrinsic::x86_avx2_psll_q:
10297 case Intrinsic::x86_sse2_psrl_w:
10298 case Intrinsic::x86_sse2_psrl_d:
10299 case Intrinsic::x86_sse2_psrl_q:
10300 case Intrinsic::x86_avx2_psrl_w:
10301 case Intrinsic::x86_avx2_psrl_d:
10302 case Intrinsic::x86_avx2_psrl_q:
10303 case Intrinsic::x86_sse2_psra_w:
10304 case Intrinsic::x86_sse2_psra_d:
10305 case Intrinsic::x86_avx2_psra_w:
10306 case Intrinsic::x86_avx2_psra_d: {
10309 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10310 case Intrinsic::x86_sse2_psll_w:
10311 case Intrinsic::x86_sse2_psll_d:
10312 case Intrinsic::x86_sse2_psll_q:
10313 case Intrinsic::x86_avx2_psll_w:
10314 case Intrinsic::x86_avx2_psll_d:
10315 case Intrinsic::x86_avx2_psll_q:
10316 Opcode = X86ISD::VSHL;
10318 case Intrinsic::x86_sse2_psrl_w:
10319 case Intrinsic::x86_sse2_psrl_d:
10320 case Intrinsic::x86_sse2_psrl_q:
10321 case Intrinsic::x86_avx2_psrl_w:
10322 case Intrinsic::x86_avx2_psrl_d:
10323 case Intrinsic::x86_avx2_psrl_q:
10324 Opcode = X86ISD::VSRL;
10326 case Intrinsic::x86_sse2_psra_w:
10327 case Intrinsic::x86_sse2_psra_d:
10328 case Intrinsic::x86_avx2_psra_w:
10329 case Intrinsic::x86_avx2_psra_d:
10330 Opcode = X86ISD::VSRA;
10333 return DAG.getNode(Opcode, dl, Op.getValueType(),
10334 Op.getOperand(1), Op.getOperand(2));
10337 // SSE/AVX immediate shift intrinsics
10338 case Intrinsic::x86_sse2_pslli_w:
10339 case Intrinsic::x86_sse2_pslli_d:
10340 case Intrinsic::x86_sse2_pslli_q:
10341 case Intrinsic::x86_avx2_pslli_w:
10342 case Intrinsic::x86_avx2_pslli_d:
10343 case Intrinsic::x86_avx2_pslli_q:
10344 case Intrinsic::x86_sse2_psrli_w:
10345 case Intrinsic::x86_sse2_psrli_d:
10346 case Intrinsic::x86_sse2_psrli_q:
10347 case Intrinsic::x86_avx2_psrli_w:
10348 case Intrinsic::x86_avx2_psrli_d:
10349 case Intrinsic::x86_avx2_psrli_q:
10350 case Intrinsic::x86_sse2_psrai_w:
10351 case Intrinsic::x86_sse2_psrai_d:
10352 case Intrinsic::x86_avx2_psrai_w:
10353 case Intrinsic::x86_avx2_psrai_d: {
10356 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10357 case Intrinsic::x86_sse2_pslli_w:
10358 case Intrinsic::x86_sse2_pslli_d:
10359 case Intrinsic::x86_sse2_pslli_q:
10360 case Intrinsic::x86_avx2_pslli_w:
10361 case Intrinsic::x86_avx2_pslli_d:
10362 case Intrinsic::x86_avx2_pslli_q:
10363 Opcode = X86ISD::VSHLI;
10365 case Intrinsic::x86_sse2_psrli_w:
10366 case Intrinsic::x86_sse2_psrli_d:
10367 case Intrinsic::x86_sse2_psrli_q:
10368 case Intrinsic::x86_avx2_psrli_w:
10369 case Intrinsic::x86_avx2_psrli_d:
10370 case Intrinsic::x86_avx2_psrli_q:
10371 Opcode = X86ISD::VSRLI;
10373 case Intrinsic::x86_sse2_psrai_w:
10374 case Intrinsic::x86_sse2_psrai_d:
10375 case Intrinsic::x86_avx2_psrai_w:
10376 case Intrinsic::x86_avx2_psrai_d:
10377 Opcode = X86ISD::VSRAI;
10380 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
10381 Op.getOperand(1), Op.getOperand(2), DAG);
10384 case Intrinsic::x86_sse42_pcmpistria128:
10385 case Intrinsic::x86_sse42_pcmpestria128:
10386 case Intrinsic::x86_sse42_pcmpistric128:
10387 case Intrinsic::x86_sse42_pcmpestric128:
10388 case Intrinsic::x86_sse42_pcmpistrio128:
10389 case Intrinsic::x86_sse42_pcmpestrio128:
10390 case Intrinsic::x86_sse42_pcmpistris128:
10391 case Intrinsic::x86_sse42_pcmpestris128:
10392 case Intrinsic::x86_sse42_pcmpistriz128:
10393 case Intrinsic::x86_sse42_pcmpestriz128: {
10397 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10398 case Intrinsic::x86_sse42_pcmpistria128:
10399 Opcode = X86ISD::PCMPISTRI;
10400 X86CC = X86::COND_A;
10402 case Intrinsic::x86_sse42_pcmpestria128:
10403 Opcode = X86ISD::PCMPESTRI;
10404 X86CC = X86::COND_A;
10406 case Intrinsic::x86_sse42_pcmpistric128:
10407 Opcode = X86ISD::PCMPISTRI;
10408 X86CC = X86::COND_B;
10410 case Intrinsic::x86_sse42_pcmpestric128:
10411 Opcode = X86ISD::PCMPESTRI;
10412 X86CC = X86::COND_B;
10414 case Intrinsic::x86_sse42_pcmpistrio128:
10415 Opcode = X86ISD::PCMPISTRI;
10416 X86CC = X86::COND_O;
10418 case Intrinsic::x86_sse42_pcmpestrio128:
10419 Opcode = X86ISD::PCMPESTRI;
10420 X86CC = X86::COND_O;
10422 case Intrinsic::x86_sse42_pcmpistris128:
10423 Opcode = X86ISD::PCMPISTRI;
10424 X86CC = X86::COND_S;
10426 case Intrinsic::x86_sse42_pcmpestris128:
10427 Opcode = X86ISD::PCMPESTRI;
10428 X86CC = X86::COND_S;
10430 case Intrinsic::x86_sse42_pcmpistriz128:
10431 Opcode = X86ISD::PCMPISTRI;
10432 X86CC = X86::COND_E;
10434 case Intrinsic::x86_sse42_pcmpestriz128:
10435 Opcode = X86ISD::PCMPESTRI;
10436 X86CC = X86::COND_E;
10439 SmallVector<SDValue, 5> NewOps;
10440 NewOps.append(Op->op_begin()+1, Op->op_end());
10441 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10442 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10443 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10444 DAG.getConstant(X86CC, MVT::i8),
10445 SDValue(PCMP.getNode(), 1));
10446 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10449 case Intrinsic::x86_sse42_pcmpistri128:
10450 case Intrinsic::x86_sse42_pcmpestri128: {
10452 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10453 Opcode = X86ISD::PCMPISTRI;
10455 Opcode = X86ISD::PCMPESTRI;
10457 SmallVector<SDValue, 5> NewOps;
10458 NewOps.append(Op->op_begin()+1, Op->op_end());
10459 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10460 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10462 case Intrinsic::x86_fma_vfmadd_ps:
10463 case Intrinsic::x86_fma_vfmadd_pd:
10464 case Intrinsic::x86_fma_vfmsub_ps:
10465 case Intrinsic::x86_fma_vfmsub_pd:
10466 case Intrinsic::x86_fma_vfnmadd_ps:
10467 case Intrinsic::x86_fma_vfnmadd_pd:
10468 case Intrinsic::x86_fma_vfnmsub_ps:
10469 case Intrinsic::x86_fma_vfnmsub_pd:
10470 case Intrinsic::x86_fma_vfmaddsub_ps:
10471 case Intrinsic::x86_fma_vfmaddsub_pd:
10472 case Intrinsic::x86_fma_vfmsubadd_ps:
10473 case Intrinsic::x86_fma_vfmsubadd_pd:
10474 case Intrinsic::x86_fma_vfmadd_ps_256:
10475 case Intrinsic::x86_fma_vfmadd_pd_256:
10476 case Intrinsic::x86_fma_vfmsub_ps_256:
10477 case Intrinsic::x86_fma_vfmsub_pd_256:
10478 case Intrinsic::x86_fma_vfnmadd_ps_256:
10479 case Intrinsic::x86_fma_vfnmadd_pd_256:
10480 case Intrinsic::x86_fma_vfnmsub_ps_256:
10481 case Intrinsic::x86_fma_vfnmsub_pd_256:
10482 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10483 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10484 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10485 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10488 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10489 case Intrinsic::x86_fma_vfmadd_ps:
10490 case Intrinsic::x86_fma_vfmadd_pd:
10491 case Intrinsic::x86_fma_vfmadd_ps_256:
10492 case Intrinsic::x86_fma_vfmadd_pd_256:
10493 Opc = X86ISD::FMADD;
10495 case Intrinsic::x86_fma_vfmsub_ps:
10496 case Intrinsic::x86_fma_vfmsub_pd:
10497 case Intrinsic::x86_fma_vfmsub_ps_256:
10498 case Intrinsic::x86_fma_vfmsub_pd_256:
10499 Opc = X86ISD::FMSUB;
10501 case Intrinsic::x86_fma_vfnmadd_ps:
10502 case Intrinsic::x86_fma_vfnmadd_pd:
10503 case Intrinsic::x86_fma_vfnmadd_ps_256:
10504 case Intrinsic::x86_fma_vfnmadd_pd_256:
10505 Opc = X86ISD::FNMADD;
10507 case Intrinsic::x86_fma_vfnmsub_ps:
10508 case Intrinsic::x86_fma_vfnmsub_pd:
10509 case Intrinsic::x86_fma_vfnmsub_ps_256:
10510 case Intrinsic::x86_fma_vfnmsub_pd_256:
10511 Opc = X86ISD::FNMSUB;
10513 case Intrinsic::x86_fma_vfmaddsub_ps:
10514 case Intrinsic::x86_fma_vfmaddsub_pd:
10515 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10516 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10517 Opc = X86ISD::FMADDSUB;
10519 case Intrinsic::x86_fma_vfmsubadd_ps:
10520 case Intrinsic::x86_fma_vfmsubadd_pd:
10521 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10522 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10523 Opc = X86ISD::FMSUBADD;
10527 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10528 Op.getOperand(2), Op.getOperand(3));
10533 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
10534 DebugLoc dl = Op.getDebugLoc();
10535 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10537 default: return SDValue(); // Don't custom lower most intrinsics.
10539 // RDRAND intrinsics.
10540 case Intrinsic::x86_rdrand_16:
10541 case Intrinsic::x86_rdrand_32:
10542 case Intrinsic::x86_rdrand_64: {
10543 // Emit the node with the right value type.
10544 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10545 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10547 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
10548 // return the value from Rand, which is always 0, casted to i32.
10549 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10550 DAG.getConstant(1, Op->getValueType(1)),
10551 DAG.getConstant(X86::COND_B, MVT::i32),
10552 SDValue(Result.getNode(), 1) };
10553 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10554 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10557 // Return { result, isValid, chain }.
10558 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10559 SDValue(Result.getNode(), 2));
10564 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
10565 SelectionDAG &DAG) const {
10566 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10567 MFI->setReturnAddressIsTaken(true);
10569 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10570 DebugLoc dl = Op.getDebugLoc();
10571 EVT PtrVT = getPointerTy();
10574 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10576 DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
10577 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10578 DAG.getNode(ISD::ADD, dl, PtrVT,
10579 FrameAddr, Offset),
10580 MachinePointerInfo(), false, false, false, 0);
10583 // Just load the return address.
10584 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
10585 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10586 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10589 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
10590 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10591 MFI->setFrameAddressIsTaken(true);
10593 EVT VT = Op.getValueType();
10594 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
10595 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10596 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
10597 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
10599 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
10600 MachinePointerInfo(),
10601 false, false, false, 0);
10605 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
10606 SelectionDAG &DAG) const {
10607 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
10610 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
10611 SDValue Chain = Op.getOperand(0);
10612 SDValue Offset = Op.getOperand(1);
10613 SDValue Handler = Op.getOperand(2);
10614 DebugLoc dl = Op.getDebugLoc();
10616 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
10617 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
10619 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
10621 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
10622 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
10623 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
10624 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
10626 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
10628 return DAG.getNode(X86ISD::EH_RETURN, dl,
10630 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
10633 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
10634 SelectionDAG &DAG) const {
10635 DebugLoc DL = Op.getDebugLoc();
10636 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
10637 DAG.getVTList(MVT::i32, MVT::Other),
10638 Op.getOperand(0), Op.getOperand(1));
10641 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
10642 SelectionDAG &DAG) const {
10643 DebugLoc DL = Op.getDebugLoc();
10644 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
10645 Op.getOperand(0), Op.getOperand(1));
10648 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
10649 return Op.getOperand(0);
10652 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
10653 SelectionDAG &DAG) const {
10654 SDValue Root = Op.getOperand(0);
10655 SDValue Trmp = Op.getOperand(1); // trampoline
10656 SDValue FPtr = Op.getOperand(2); // nested function
10657 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
10658 DebugLoc dl = Op.getDebugLoc();
10660 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10661 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
10663 if (Subtarget->is64Bit()) {
10664 SDValue OutChains[6];
10666 // Large code-model.
10667 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
10668 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
10670 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
10671 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
10673 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
10675 // Load the pointer to the nested function into R11.
10676 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
10677 SDValue Addr = Trmp;
10678 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10679 Addr, MachinePointerInfo(TrmpAddr),
10682 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10683 DAG.getConstant(2, MVT::i64));
10684 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
10685 MachinePointerInfo(TrmpAddr, 2),
10688 // Load the 'nest' parameter value into R10.
10689 // R10 is specified in X86CallingConv.td
10690 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
10691 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10692 DAG.getConstant(10, MVT::i64));
10693 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10694 Addr, MachinePointerInfo(TrmpAddr, 10),
10697 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10698 DAG.getConstant(12, MVT::i64));
10699 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
10700 MachinePointerInfo(TrmpAddr, 12),
10703 // Jump to the nested function.
10704 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
10705 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10706 DAG.getConstant(20, MVT::i64));
10707 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10708 Addr, MachinePointerInfo(TrmpAddr, 20),
10711 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
10712 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10713 DAG.getConstant(22, MVT::i64));
10714 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
10715 MachinePointerInfo(TrmpAddr, 22),
10718 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
10720 const Function *Func =
10721 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10722 CallingConv::ID CC = Func->getCallingConv();
10727 llvm_unreachable("Unsupported calling convention");
10728 case CallingConv::C:
10729 case CallingConv::X86_StdCall: {
10730 // Pass 'nest' parameter in ECX.
10731 // Must be kept in sync with X86CallingConv.td
10732 NestReg = X86::ECX;
10734 // Check that ECX wasn't needed by an 'inreg' parameter.
10735 FunctionType *FTy = Func->getFunctionType();
10736 const AttributeSet &Attrs = Func->getAttributes();
10738 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10739 unsigned InRegCount = 0;
10742 for (FunctionType::param_iterator I = FTy->param_begin(),
10743 E = FTy->param_end(); I != E; ++I, ++Idx)
10744 if (Attrs.getParamAttributes(Idx).hasAttribute(Attribute::InReg))
10745 // FIXME: should only count parameters that are lowered to integers.
10746 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10748 if (InRegCount > 2) {
10749 report_fatal_error("Nest register in use - reduce number of inreg"
10755 case CallingConv::X86_FastCall:
10756 case CallingConv::X86_ThisCall:
10757 case CallingConv::Fast:
10758 // Pass 'nest' parameter in EAX.
10759 // Must be kept in sync with X86CallingConv.td
10760 NestReg = X86::EAX;
10764 SDValue OutChains[4];
10765 SDValue Addr, Disp;
10767 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10768 DAG.getConstant(10, MVT::i32));
10769 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10771 // This is storing the opcode for MOV32ri.
10772 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10773 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
10774 OutChains[0] = DAG.getStore(Root, dl,
10775 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10776 Trmp, MachinePointerInfo(TrmpAddr),
10779 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10780 DAG.getConstant(1, MVT::i32));
10781 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10782 MachinePointerInfo(TrmpAddr, 1),
10785 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10786 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10787 DAG.getConstant(5, MVT::i32));
10788 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10789 MachinePointerInfo(TrmpAddr, 5),
10792 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10793 DAG.getConstant(6, MVT::i32));
10794 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10795 MachinePointerInfo(TrmpAddr, 6),
10798 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10802 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10803 SelectionDAG &DAG) const {
10805 The rounding mode is in bits 11:10 of FPSR, and has the following
10807 00 Round to nearest
10812 FLT_ROUNDS, on the other hand, expects the following:
10819 To perform the conversion, we do:
10820 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10823 MachineFunction &MF = DAG.getMachineFunction();
10824 const TargetMachine &TM = MF.getTarget();
10825 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10826 unsigned StackAlignment = TFI.getStackAlignment();
10827 EVT VT = Op.getValueType();
10828 DebugLoc DL = Op.getDebugLoc();
10830 // Save FP Control Word to stack slot
10831 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10832 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10835 MachineMemOperand *MMO =
10836 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10837 MachineMemOperand::MOStore, 2, 2);
10839 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10840 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10841 DAG.getVTList(MVT::Other),
10842 Ops, 2, MVT::i16, MMO);
10844 // Load FP Control Word from stack slot
10845 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10846 MachinePointerInfo(), false, false, false, 0);
10848 // Transform as necessary
10850 DAG.getNode(ISD::SRL, DL, MVT::i16,
10851 DAG.getNode(ISD::AND, DL, MVT::i16,
10852 CWD, DAG.getConstant(0x800, MVT::i16)),
10853 DAG.getConstant(11, MVT::i8));
10855 DAG.getNode(ISD::SRL, DL, MVT::i16,
10856 DAG.getNode(ISD::AND, DL, MVT::i16,
10857 CWD, DAG.getConstant(0x400, MVT::i16)),
10858 DAG.getConstant(9, MVT::i8));
10861 DAG.getNode(ISD::AND, DL, MVT::i16,
10862 DAG.getNode(ISD::ADD, DL, MVT::i16,
10863 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10864 DAG.getConstant(1, MVT::i16)),
10865 DAG.getConstant(3, MVT::i16));
10868 return DAG.getNode((VT.getSizeInBits() < 16 ?
10869 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10872 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
10873 EVT VT = Op.getValueType();
10875 unsigned NumBits = VT.getSizeInBits();
10876 DebugLoc dl = Op.getDebugLoc();
10878 Op = Op.getOperand(0);
10879 if (VT == MVT::i8) {
10880 // Zero extend to i32 since there is not an i8 bsr.
10882 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10885 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10886 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10887 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10889 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10892 DAG.getConstant(NumBits+NumBits-1, OpVT),
10893 DAG.getConstant(X86::COND_E, MVT::i8),
10896 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10898 // Finally xor with NumBits-1.
10899 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10902 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10906 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
10907 EVT VT = Op.getValueType();
10909 unsigned NumBits = VT.getSizeInBits();
10910 DebugLoc dl = Op.getDebugLoc();
10912 Op = Op.getOperand(0);
10913 if (VT == MVT::i8) {
10914 // Zero extend to i32 since there is not an i8 bsr.
10916 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10919 // Issue a bsr (scan bits in reverse).
10920 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10921 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10923 // And xor with NumBits-1.
10924 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10927 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10931 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
10932 EVT VT = Op.getValueType();
10933 unsigned NumBits = VT.getSizeInBits();
10934 DebugLoc dl = Op.getDebugLoc();
10935 Op = Op.getOperand(0);
10937 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10938 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10939 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10941 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10944 DAG.getConstant(NumBits, VT),
10945 DAG.getConstant(X86::COND_E, MVT::i8),
10948 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10951 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10952 // ones, and then concatenate the result back.
10953 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10954 EVT VT = Op.getValueType();
10956 assert(VT.is256BitVector() && VT.isInteger() &&
10957 "Unsupported value type for operation");
10959 unsigned NumElems = VT.getVectorNumElements();
10960 DebugLoc dl = Op.getDebugLoc();
10962 // Extract the LHS vectors
10963 SDValue LHS = Op.getOperand(0);
10964 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10965 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10967 // Extract the RHS vectors
10968 SDValue RHS = Op.getOperand(1);
10969 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10970 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10972 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10973 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10975 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10976 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10977 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10980 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
10981 assert(Op.getValueType().is256BitVector() &&
10982 Op.getValueType().isInteger() &&
10983 "Only handle AVX 256-bit vector integer operation");
10984 return Lower256IntArith(Op, DAG);
10987 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
10988 assert(Op.getValueType().is256BitVector() &&
10989 Op.getValueType().isInteger() &&
10990 "Only handle AVX 256-bit vector integer operation");
10991 return Lower256IntArith(Op, DAG);
10994 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
10995 SelectionDAG &DAG) {
10996 EVT VT = Op.getValueType();
10998 // Decompose 256-bit ops into smaller 128-bit ops.
10999 if (VT.is256BitVector() && !Subtarget->hasInt256())
11000 return Lower256IntArith(Op, DAG);
11002 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11003 "Only know how to lower V2I64/V4I64 multiply");
11005 DebugLoc dl = Op.getDebugLoc();
11007 // Ahi = psrlqi(a, 32);
11008 // Bhi = psrlqi(b, 32);
11010 // AloBlo = pmuludq(a, b);
11011 // AloBhi = pmuludq(a, Bhi);
11012 // AhiBlo = pmuludq(Ahi, b);
11014 // AloBhi = psllqi(AloBhi, 32);
11015 // AhiBlo = psllqi(AhiBlo, 32);
11016 // return AloBlo + AloBhi + AhiBlo;
11018 SDValue A = Op.getOperand(0);
11019 SDValue B = Op.getOperand(1);
11021 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11023 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11024 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11026 // Bit cast to 32-bit vectors for MULUDQ
11027 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11028 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11029 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11030 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11031 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11033 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11034 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11035 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11037 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11038 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11040 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11041 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11044 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
11046 EVT VT = Op.getValueType();
11047 DebugLoc dl = Op.getDebugLoc();
11048 SDValue R = Op.getOperand(0);
11049 SDValue Amt = Op.getOperand(1);
11050 LLVMContext *Context = DAG.getContext();
11052 if (!Subtarget->hasSSE2())
11055 // Optimize shl/srl/sra with constant shift amount.
11056 if (isSplatVector(Amt.getNode())) {
11057 SDValue SclrAmt = Amt->getOperand(0);
11058 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11059 uint64_t ShiftAmt = C->getZExtValue();
11061 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11062 (Subtarget->hasInt256() &&
11063 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11064 if (Op.getOpcode() == ISD::SHL)
11065 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11066 DAG.getConstant(ShiftAmt, MVT::i32));
11067 if (Op.getOpcode() == ISD::SRL)
11068 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11069 DAG.getConstant(ShiftAmt, MVT::i32));
11070 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11071 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11072 DAG.getConstant(ShiftAmt, MVT::i32));
11075 if (VT == MVT::v16i8) {
11076 if (Op.getOpcode() == ISD::SHL) {
11077 // Make a large shift.
11078 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11079 DAG.getConstant(ShiftAmt, MVT::i32));
11080 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11081 // Zero out the rightmost bits.
11082 SmallVector<SDValue, 16> V(16,
11083 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11085 return DAG.getNode(ISD::AND, dl, VT, SHL,
11086 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11088 if (Op.getOpcode() == ISD::SRL) {
11089 // Make a large shift.
11090 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11091 DAG.getConstant(ShiftAmt, MVT::i32));
11092 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11093 // Zero out the leftmost bits.
11094 SmallVector<SDValue, 16> V(16,
11095 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11097 return DAG.getNode(ISD::AND, dl, VT, SRL,
11098 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11100 if (Op.getOpcode() == ISD::SRA) {
11101 if (ShiftAmt == 7) {
11102 // R s>> 7 === R s< 0
11103 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11104 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11107 // R s>> a === ((R u>> a) ^ m) - m
11108 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11109 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11111 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11112 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11113 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11116 llvm_unreachable("Unknown shift opcode.");
11119 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11120 if (Op.getOpcode() == ISD::SHL) {
11121 // Make a large shift.
11122 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11123 DAG.getConstant(ShiftAmt, MVT::i32));
11124 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11125 // Zero out the rightmost bits.
11126 SmallVector<SDValue, 32> V(32,
11127 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11129 return DAG.getNode(ISD::AND, dl, VT, SHL,
11130 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11132 if (Op.getOpcode() == ISD::SRL) {
11133 // Make a large shift.
11134 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11135 DAG.getConstant(ShiftAmt, MVT::i32));
11136 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11137 // Zero out the leftmost bits.
11138 SmallVector<SDValue, 32> V(32,
11139 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11141 return DAG.getNode(ISD::AND, dl, VT, SRL,
11142 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11144 if (Op.getOpcode() == ISD::SRA) {
11145 if (ShiftAmt == 7) {
11146 // R s>> 7 === R s< 0
11147 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11148 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11151 // R s>> a === ((R u>> a) ^ m) - m
11152 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11153 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11155 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11156 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11157 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11160 llvm_unreachable("Unknown shift opcode.");
11165 // Lower SHL with variable shift amount.
11166 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11167 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
11168 DAG.getConstant(23, MVT::i32));
11170 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
11171 Constant *C = ConstantDataVector::get(*Context, CV);
11172 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
11173 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11174 MachinePointerInfo::getConstantPool(),
11175 false, false, false, 16);
11177 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
11178 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11179 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11180 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11182 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11183 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
11186 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
11187 DAG.getConstant(5, MVT::i32));
11188 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11190 // Turn 'a' into a mask suitable for VSELECT
11191 SDValue VSelM = DAG.getConstant(0x80, VT);
11192 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11193 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11195 SDValue CM1 = DAG.getConstant(0x0f, VT);
11196 SDValue CM2 = DAG.getConstant(0x3f, VT);
11198 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
11199 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11200 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11201 DAG.getConstant(4, MVT::i32), DAG);
11202 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11203 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11206 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11207 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11208 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11210 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
11211 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11212 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11213 DAG.getConstant(2, MVT::i32), DAG);
11214 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11215 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11218 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11219 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11220 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11222 // return VSELECT(r, r+r, a);
11223 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11224 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11228 // Decompose 256-bit shifts into smaller 128-bit shifts.
11229 if (VT.is256BitVector()) {
11230 unsigned NumElems = VT.getVectorNumElements();
11231 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11232 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11234 // Extract the two vectors
11235 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
11236 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
11238 // Recreate the shift amount vectors
11239 SDValue Amt1, Amt2;
11240 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11241 // Constant shift amount
11242 SmallVector<SDValue, 4> Amt1Csts;
11243 SmallVector<SDValue, 4> Amt2Csts;
11244 for (unsigned i = 0; i != NumElems/2; ++i)
11245 Amt1Csts.push_back(Amt->getOperand(i));
11246 for (unsigned i = NumElems/2; i != NumElems; ++i)
11247 Amt2Csts.push_back(Amt->getOperand(i));
11249 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11250 &Amt1Csts[0], NumElems/2);
11251 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11252 &Amt2Csts[0], NumElems/2);
11254 // Variable shift amount
11255 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11256 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
11259 // Issue new vector shifts for the smaller types
11260 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11261 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11263 // Concatenate the result back
11264 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11270 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
11271 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
11272 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
11273 // looks for this combo and may remove the "setcc" instruction if the "setcc"
11274 // has only one use.
11275 SDNode *N = Op.getNode();
11276 SDValue LHS = N->getOperand(0);
11277 SDValue RHS = N->getOperand(1);
11278 unsigned BaseOp = 0;
11280 DebugLoc DL = Op.getDebugLoc();
11281 switch (Op.getOpcode()) {
11282 default: llvm_unreachable("Unknown ovf instruction!");
11284 // A subtract of one will be selected as a INC. Note that INC doesn't
11285 // set CF, so we can't do this for UADDO.
11286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11288 BaseOp = X86ISD::INC;
11289 Cond = X86::COND_O;
11292 BaseOp = X86ISD::ADD;
11293 Cond = X86::COND_O;
11296 BaseOp = X86ISD::ADD;
11297 Cond = X86::COND_B;
11300 // A subtract of one will be selected as a DEC. Note that DEC doesn't
11301 // set CF, so we can't do this for USUBO.
11302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11304 BaseOp = X86ISD::DEC;
11305 Cond = X86::COND_O;
11308 BaseOp = X86ISD::SUB;
11309 Cond = X86::COND_O;
11312 BaseOp = X86ISD::SUB;
11313 Cond = X86::COND_B;
11316 BaseOp = X86ISD::SMUL;
11317 Cond = X86::COND_O;
11319 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
11320 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
11322 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
11325 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11326 DAG.getConstant(X86::COND_O, MVT::i32),
11327 SDValue(Sum.getNode(), 2));
11329 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11333 // Also sets EFLAGS.
11334 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
11335 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
11338 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
11339 DAG.getConstant(Cond, MVT::i32),
11340 SDValue(Sum.getNode(), 1));
11342 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11345 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
11346 SelectionDAG &DAG) const {
11347 DebugLoc dl = Op.getDebugLoc();
11348 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
11349 EVT VT = Op.getValueType();
11351 if (!Subtarget->hasSSE2() || !VT.isVector())
11354 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
11355 ExtraVT.getScalarType().getSizeInBits();
11356 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
11358 switch (VT.getSimpleVT().SimpleTy) {
11359 default: return SDValue();
11362 if (!Subtarget->hasFp256())
11364 if (!Subtarget->hasInt256()) {
11365 // needs to be split
11366 unsigned NumElems = VT.getVectorNumElements();
11368 // Extract the LHS vectors
11369 SDValue LHS = Op.getOperand(0);
11370 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11371 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11373 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11374 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11376 EVT ExtraEltVT = ExtraVT.getVectorElementType();
11377 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
11378 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
11380 SDValue Extra = DAG.getValueType(ExtraVT);
11382 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
11383 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
11385 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
11390 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
11391 Op.getOperand(0), ShAmt, DAG);
11392 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
11398 static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
11399 SelectionDAG &DAG) {
11400 DebugLoc dl = Op.getDebugLoc();
11402 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
11403 // There isn't any reason to disable it if the target processor supports it.
11404 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
11405 SDValue Chain = Op.getOperand(0);
11406 SDValue Zero = DAG.getConstant(0, MVT::i32);
11408 DAG.getRegister(X86::ESP, MVT::i32), // Base
11409 DAG.getTargetConstant(1, MVT::i8), // Scale
11410 DAG.getRegister(0, MVT::i32), // Index
11411 DAG.getTargetConstant(0, MVT::i32), // Disp
11412 DAG.getRegister(0, MVT::i32), // Segment.
11417 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11418 array_lengthof(Ops));
11419 return SDValue(Res, 0);
11422 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
11424 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11426 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11427 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11428 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
11429 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
11431 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
11432 if (!Op1 && !Op2 && !Op3 && Op4)
11433 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
11435 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
11436 if (Op1 && !Op2 && !Op3 && !Op4)
11437 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
11439 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
11441 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11444 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
11445 SelectionDAG &DAG) {
11446 DebugLoc dl = Op.getDebugLoc();
11447 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
11448 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
11449 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
11450 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
11452 // The only fence that needs an instruction is a sequentially-consistent
11453 // cross-thread fence.
11454 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
11455 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
11456 // no-sse2). There isn't any reason to disable it if the target processor
11458 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
11459 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11461 SDValue Chain = Op.getOperand(0);
11462 SDValue Zero = DAG.getConstant(0, MVT::i32);
11464 DAG.getRegister(X86::ESP, MVT::i32), // Base
11465 DAG.getTargetConstant(1, MVT::i8), // Scale
11466 DAG.getRegister(0, MVT::i32), // Index
11467 DAG.getTargetConstant(0, MVT::i32), // Disp
11468 DAG.getRegister(0, MVT::i32), // Segment.
11473 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11474 array_lengthof(Ops));
11475 return SDValue(Res, 0);
11478 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
11479 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11483 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
11484 SelectionDAG &DAG) {
11485 EVT T = Op.getValueType();
11486 DebugLoc DL = Op.getDebugLoc();
11489 switch(T.getSimpleVT().SimpleTy) {
11490 default: llvm_unreachable("Invalid value type!");
11491 case MVT::i8: Reg = X86::AL; size = 1; break;
11492 case MVT::i16: Reg = X86::AX; size = 2; break;
11493 case MVT::i32: Reg = X86::EAX; size = 4; break;
11495 assert(Subtarget->is64Bit() && "Node not type legal!");
11496 Reg = X86::RAX; size = 8;
11499 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
11500 Op.getOperand(2), SDValue());
11501 SDValue Ops[] = { cpIn.getValue(0),
11504 DAG.getTargetConstant(size, MVT::i8),
11505 cpIn.getValue(1) };
11506 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11507 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
11508 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11511 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11515 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
11516 SelectionDAG &DAG) {
11517 assert(Subtarget->is64Bit() && "Result not type legalized?");
11518 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11519 SDValue TheChain = Op.getOperand(0);
11520 DebugLoc dl = Op.getDebugLoc();
11521 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11522 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
11523 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
11525 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11526 DAG.getConstant(32, MVT::i8));
11528 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11531 return DAG.getMergeValues(Ops, 2, dl);
11534 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
11535 EVT SrcVT = Op.getOperand(0).getValueType();
11536 EVT DstVT = Op.getValueType();
11537 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
11538 Subtarget->hasMMX() && "Unexpected custom BITCAST");
11539 assert((DstVT == MVT::i64 ||
11540 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
11541 "Unexpected custom BITCAST");
11542 // i64 <=> MMX conversions are Legal.
11543 if (SrcVT==MVT::i64 && DstVT.isVector())
11545 if (DstVT==MVT::i64 && SrcVT.isVector())
11547 // MMX <=> MMX conversions are Legal.
11548 if (SrcVT.isVector() && DstVT.isVector())
11550 // All other conversions need to be expanded.
11554 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
11555 SDNode *Node = Op.getNode();
11556 DebugLoc dl = Node->getDebugLoc();
11557 EVT T = Node->getValueType(0);
11558 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11559 DAG.getConstant(0, T), Node->getOperand(2));
11560 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
11561 cast<AtomicSDNode>(Node)->getMemoryVT(),
11562 Node->getOperand(0),
11563 Node->getOperand(1), negOp,
11564 cast<AtomicSDNode>(Node)->getSrcValue(),
11565 cast<AtomicSDNode>(Node)->getAlignment(),
11566 cast<AtomicSDNode>(Node)->getOrdering(),
11567 cast<AtomicSDNode>(Node)->getSynchScope());
11570 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
11571 SDNode *Node = Op.getNode();
11572 DebugLoc dl = Node->getDebugLoc();
11573 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11575 // Convert seq_cst store -> xchg
11576 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
11577 // FIXME: On 32-bit, store -> fist or movq would be more efficient
11578 // (The only way to get a 16-byte store is cmpxchg16b)
11579 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
11580 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
11581 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
11582 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
11583 cast<AtomicSDNode>(Node)->getMemoryVT(),
11584 Node->getOperand(0),
11585 Node->getOperand(1), Node->getOperand(2),
11586 cast<AtomicSDNode>(Node)->getMemOperand(),
11587 cast<AtomicSDNode>(Node)->getOrdering(),
11588 cast<AtomicSDNode>(Node)->getSynchScope());
11589 return Swap.getValue(1);
11591 // Other atomic stores have a simple pattern.
11595 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
11596 EVT VT = Op.getNode()->getValueType(0);
11598 // Let legalize expand this if it isn't a legal type yet.
11599 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
11602 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11605 bool ExtraOp = false;
11606 switch (Op.getOpcode()) {
11607 default: llvm_unreachable("Invalid code");
11608 case ISD::ADDC: Opc = X86ISD::ADD; break;
11609 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
11610 case ISD::SUBC: Opc = X86ISD::SUB; break;
11611 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
11615 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11617 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11618 Op.getOperand(1), Op.getOperand(2));
11621 /// LowerOperation - Provide custom lowering hooks for some operations.
11623 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
11624 switch (Op.getOpcode()) {
11625 default: llvm_unreachable("Should not custom lower this!");
11626 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
11627 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
11628 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
11629 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
11630 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
11631 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
11632 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
11633 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
11634 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
11635 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
11636 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
11637 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
11638 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
11639 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
11640 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
11641 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
11642 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
11643 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
11644 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
11645 case ISD::SHL_PARTS:
11646 case ISD::SRA_PARTS:
11647 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
11648 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
11649 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
11650 case ISD::TRUNCATE: return lowerTRUNCATE(Op, DAG);
11651 case ISD::ZERO_EXTEND: return lowerZERO_EXTEND(Op, DAG);
11652 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
11653 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
11654 case ISD::FP_EXTEND: return lowerFP_EXTEND(Op, DAG);
11655 case ISD::FABS: return LowerFABS(Op, DAG);
11656 case ISD::FNEG: return LowerFNEG(Op, DAG);
11657 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
11658 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
11659 case ISD::SETCC: return LowerSETCC(Op, DAG);
11660 case ISD::SELECT: return LowerSELECT(Op, DAG);
11661 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
11662 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
11663 case ISD::VASTART: return LowerVASTART(Op, DAG);
11664 case ISD::VAARG: return LowerVAARG(Op, DAG);
11665 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
11666 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
11667 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
11668 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
11669 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
11670 case ISD::FRAME_TO_ARGS_OFFSET:
11671 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
11672 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
11673 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
11674 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
11675 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
11676 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
11677 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
11678 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
11679 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
11680 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
11681 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
11682 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
11685 case ISD::SHL: return LowerShift(Op, DAG);
11691 case ISD::UMULO: return LowerXALUO(Op, DAG);
11692 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
11693 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
11697 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
11698 case ISD::ADD: return LowerADD(Op, DAG);
11699 case ISD::SUB: return LowerSUB(Op, DAG);
11703 static void ReplaceATOMIC_LOAD(SDNode *Node,
11704 SmallVectorImpl<SDValue> &Results,
11705 SelectionDAG &DAG) {
11706 DebugLoc dl = Node->getDebugLoc();
11707 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11709 // Convert wide load -> cmpxchg8b/cmpxchg16b
11710 // FIXME: On 32-bit, load -> fild or movq would be more efficient
11711 // (The only way to get a 16-byte load is cmpxchg16b)
11712 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
11713 SDValue Zero = DAG.getConstant(0, VT);
11714 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
11715 Node->getOperand(0),
11716 Node->getOperand(1), Zero, Zero,
11717 cast<AtomicSDNode>(Node)->getMemOperand(),
11718 cast<AtomicSDNode>(Node)->getOrdering(),
11719 cast<AtomicSDNode>(Node)->getSynchScope());
11720 Results.push_back(Swap.getValue(0));
11721 Results.push_back(Swap.getValue(1));
11725 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
11726 SelectionDAG &DAG, unsigned NewOp) {
11727 DebugLoc dl = Node->getDebugLoc();
11728 assert (Node->getValueType(0) == MVT::i64 &&
11729 "Only know how to expand i64 atomics");
11731 SDValue Chain = Node->getOperand(0);
11732 SDValue In1 = Node->getOperand(1);
11733 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11734 Node->getOperand(2), DAG.getIntPtrConstant(0));
11735 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11736 Node->getOperand(2), DAG.getIntPtrConstant(1));
11737 SDValue Ops[] = { Chain, In1, In2L, In2H };
11738 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11740 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11741 cast<MemSDNode>(Node)->getMemOperand());
11742 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11743 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11744 Results.push_back(Result.getValue(2));
11747 /// ReplaceNodeResults - Replace a node with an illegal result type
11748 /// with a new node built out of custom code.
11749 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11750 SmallVectorImpl<SDValue>&Results,
11751 SelectionDAG &DAG) const {
11752 DebugLoc dl = N->getDebugLoc();
11753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11754 switch (N->getOpcode()) {
11756 llvm_unreachable("Do not know how to custom type legalize this operation!");
11757 case ISD::SIGN_EXTEND_INREG:
11762 // We don't want to expand or promote these.
11764 case ISD::FP_TO_SINT:
11765 case ISD::FP_TO_UINT: {
11766 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11768 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11771 std::pair<SDValue,SDValue> Vals =
11772 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11773 SDValue FIST = Vals.first, StackSlot = Vals.second;
11774 if (FIST.getNode() != 0) {
11775 EVT VT = N->getValueType(0);
11776 // Return a load from the stack slot.
11777 if (StackSlot.getNode() != 0)
11778 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11779 MachinePointerInfo(),
11780 false, false, false, 0));
11782 Results.push_back(FIST);
11786 case ISD::UINT_TO_FP: {
11787 if (N->getOperand(0).getValueType() != MVT::v2i32 &&
11788 N->getValueType(0) != MVT::v2f32)
11790 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
11792 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11794 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
11795 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
11796 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
11797 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
11798 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
11799 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
11802 case ISD::FP_ROUND: {
11803 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
11805 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
11806 Results.push_back(V);
11809 case ISD::READCYCLECOUNTER: {
11810 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11811 SDValue TheChain = N->getOperand(0);
11812 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11813 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11815 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11817 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11818 SDValue Ops[] = { eax, edx };
11819 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11820 Results.push_back(edx.getValue(1));
11823 case ISD::ATOMIC_CMP_SWAP: {
11824 EVT T = N->getValueType(0);
11825 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11826 bool Regs64bit = T == MVT::i128;
11827 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11828 SDValue cpInL, cpInH;
11829 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11830 DAG.getConstant(0, HalfT));
11831 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11832 DAG.getConstant(1, HalfT));
11833 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11834 Regs64bit ? X86::RAX : X86::EAX,
11836 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11837 Regs64bit ? X86::RDX : X86::EDX,
11838 cpInH, cpInL.getValue(1));
11839 SDValue swapInL, swapInH;
11840 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11841 DAG.getConstant(0, HalfT));
11842 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11843 DAG.getConstant(1, HalfT));
11844 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11845 Regs64bit ? X86::RBX : X86::EBX,
11846 swapInL, cpInH.getValue(1));
11847 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11848 Regs64bit ? X86::RCX : X86::ECX,
11849 swapInH, swapInL.getValue(1));
11850 SDValue Ops[] = { swapInH.getValue(0),
11852 swapInH.getValue(1) };
11853 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11854 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11855 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11856 X86ISD::LCMPXCHG8_DAG;
11857 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11859 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11860 Regs64bit ? X86::RAX : X86::EAX,
11861 HalfT, Result.getValue(1));
11862 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11863 Regs64bit ? X86::RDX : X86::EDX,
11864 HalfT, cpOutL.getValue(2));
11865 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11866 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11867 Results.push_back(cpOutH.getValue(1));
11870 case ISD::ATOMIC_LOAD_ADD:
11871 case ISD::ATOMIC_LOAD_AND:
11872 case ISD::ATOMIC_LOAD_NAND:
11873 case ISD::ATOMIC_LOAD_OR:
11874 case ISD::ATOMIC_LOAD_SUB:
11875 case ISD::ATOMIC_LOAD_XOR:
11876 case ISD::ATOMIC_LOAD_MAX:
11877 case ISD::ATOMIC_LOAD_MIN:
11878 case ISD::ATOMIC_LOAD_UMAX:
11879 case ISD::ATOMIC_LOAD_UMIN:
11880 case ISD::ATOMIC_SWAP: {
11882 switch (N->getOpcode()) {
11883 default: llvm_unreachable("Unexpected opcode");
11884 case ISD::ATOMIC_LOAD_ADD:
11885 Opc = X86ISD::ATOMADD64_DAG;
11887 case ISD::ATOMIC_LOAD_AND:
11888 Opc = X86ISD::ATOMAND64_DAG;
11890 case ISD::ATOMIC_LOAD_NAND:
11891 Opc = X86ISD::ATOMNAND64_DAG;
11893 case ISD::ATOMIC_LOAD_OR:
11894 Opc = X86ISD::ATOMOR64_DAG;
11896 case ISD::ATOMIC_LOAD_SUB:
11897 Opc = X86ISD::ATOMSUB64_DAG;
11899 case ISD::ATOMIC_LOAD_XOR:
11900 Opc = X86ISD::ATOMXOR64_DAG;
11902 case ISD::ATOMIC_LOAD_MAX:
11903 Opc = X86ISD::ATOMMAX64_DAG;
11905 case ISD::ATOMIC_LOAD_MIN:
11906 Opc = X86ISD::ATOMMIN64_DAG;
11908 case ISD::ATOMIC_LOAD_UMAX:
11909 Opc = X86ISD::ATOMUMAX64_DAG;
11911 case ISD::ATOMIC_LOAD_UMIN:
11912 Opc = X86ISD::ATOMUMIN64_DAG;
11914 case ISD::ATOMIC_SWAP:
11915 Opc = X86ISD::ATOMSWAP64_DAG;
11918 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
11921 case ISD::ATOMIC_LOAD:
11922 ReplaceATOMIC_LOAD(N, Results, DAG);
11926 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11928 default: return NULL;
11929 case X86ISD::BSF: return "X86ISD::BSF";
11930 case X86ISD::BSR: return "X86ISD::BSR";
11931 case X86ISD::SHLD: return "X86ISD::SHLD";
11932 case X86ISD::SHRD: return "X86ISD::SHRD";
11933 case X86ISD::FAND: return "X86ISD::FAND";
11934 case X86ISD::FOR: return "X86ISD::FOR";
11935 case X86ISD::FXOR: return "X86ISD::FXOR";
11936 case X86ISD::FSRL: return "X86ISD::FSRL";
11937 case X86ISD::FILD: return "X86ISD::FILD";
11938 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11939 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11940 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11941 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11942 case X86ISD::FLD: return "X86ISD::FLD";
11943 case X86ISD::FST: return "X86ISD::FST";
11944 case X86ISD::CALL: return "X86ISD::CALL";
11945 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11946 case X86ISD::BT: return "X86ISD::BT";
11947 case X86ISD::CMP: return "X86ISD::CMP";
11948 case X86ISD::COMI: return "X86ISD::COMI";
11949 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11950 case X86ISD::SETCC: return "X86ISD::SETCC";
11951 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11952 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11953 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11954 case X86ISD::CMOV: return "X86ISD::CMOV";
11955 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11956 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11957 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11958 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11959 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11960 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11961 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11962 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11963 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11964 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11965 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11966 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11967 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11968 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11969 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11970 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11971 case X86ISD::BLENDI: return "X86ISD::BLENDI";
11972 case X86ISD::SUBUS: return "X86ISD::SUBUS";
11973 case X86ISD::HADD: return "X86ISD::HADD";
11974 case X86ISD::HSUB: return "X86ISD::HSUB";
11975 case X86ISD::FHADD: return "X86ISD::FHADD";
11976 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11977 case X86ISD::FMAX: return "X86ISD::FMAX";
11978 case X86ISD::FMIN: return "X86ISD::FMIN";
11979 case X86ISD::FMAXC: return "X86ISD::FMAXC";
11980 case X86ISD::FMINC: return "X86ISD::FMINC";
11981 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11982 case X86ISD::FRCP: return "X86ISD::FRCP";
11983 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11984 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11985 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11986 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
11987 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
11988 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11989 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11990 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11991 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11992 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11993 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11994 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11995 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11996 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11997 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11998 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11999 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
12000 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
12001 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
12002 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
12003 case X86ISD::VZEXT: return "X86ISD::VZEXT";
12004 case X86ISD::VSEXT: return "X86ISD::VSEXT";
12005 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
12006 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
12007 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
12008 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
12009 case X86ISD::VSHL: return "X86ISD::VSHL";
12010 case X86ISD::VSRL: return "X86ISD::VSRL";
12011 case X86ISD::VSRA: return "X86ISD::VSRA";
12012 case X86ISD::VSHLI: return "X86ISD::VSHLI";
12013 case X86ISD::VSRLI: return "X86ISD::VSRLI";
12014 case X86ISD::VSRAI: return "X86ISD::VSRAI";
12015 case X86ISD::CMPP: return "X86ISD::CMPP";
12016 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
12017 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
12018 case X86ISD::ADD: return "X86ISD::ADD";
12019 case X86ISD::SUB: return "X86ISD::SUB";
12020 case X86ISD::ADC: return "X86ISD::ADC";
12021 case X86ISD::SBB: return "X86ISD::SBB";
12022 case X86ISD::SMUL: return "X86ISD::SMUL";
12023 case X86ISD::UMUL: return "X86ISD::UMUL";
12024 case X86ISD::INC: return "X86ISD::INC";
12025 case X86ISD::DEC: return "X86ISD::DEC";
12026 case X86ISD::OR: return "X86ISD::OR";
12027 case X86ISD::XOR: return "X86ISD::XOR";
12028 case X86ISD::AND: return "X86ISD::AND";
12029 case X86ISD::BLSI: return "X86ISD::BLSI";
12030 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
12031 case X86ISD::BLSR: return "X86ISD::BLSR";
12032 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
12033 case X86ISD::PTEST: return "X86ISD::PTEST";
12034 case X86ISD::TESTP: return "X86ISD::TESTP";
12035 case X86ISD::PALIGN: return "X86ISD::PALIGN";
12036 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
12037 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
12038 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
12039 case X86ISD::SHUFP: return "X86ISD::SHUFP";
12040 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
12041 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
12042 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
12043 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
12044 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
12045 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
12046 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
12047 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
12048 case X86ISD::MOVSD: return "X86ISD::MOVSD";
12049 case X86ISD::MOVSS: return "X86ISD::MOVSS";
12050 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
12051 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
12052 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
12053 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
12054 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
12055 case X86ISD::VPERMV: return "X86ISD::VPERMV";
12056 case X86ISD::VPERMI: return "X86ISD::VPERMI";
12057 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
12058 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
12059 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
12060 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
12061 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
12062 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
12063 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
12064 case X86ISD::SAHF: return "X86ISD::SAHF";
12065 case X86ISD::RDRAND: return "X86ISD::RDRAND";
12066 case X86ISD::FMADD: return "X86ISD::FMADD";
12067 case X86ISD::FMSUB: return "X86ISD::FMSUB";
12068 case X86ISD::FNMADD: return "X86ISD::FNMADD";
12069 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
12070 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
12071 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
12072 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
12073 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12077 // isLegalAddressingMode - Return true if the addressing mode represented
12078 // by AM is legal for this target, for a load/store of the specified type.
12079 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
12081 // X86 supports extremely general addressing modes.
12082 CodeModel::Model M = getTargetMachine().getCodeModel();
12083 Reloc::Model R = getTargetMachine().getRelocationModel();
12085 // X86 allows a sign-extended 32-bit immediate field as a displacement.
12086 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
12091 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
12093 // If a reference to this global requires an extra load, we can't fold it.
12094 if (isGlobalStubReference(GVFlags))
12097 // If BaseGV requires a register for the PIC base, we cannot also have a
12098 // BaseReg specified.
12099 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
12102 // If lower 4G is not available, then we must use rip-relative addressing.
12103 if ((M != CodeModel::Small || R != Reloc::Static) &&
12104 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
12108 switch (AM.Scale) {
12114 // These scales always work.
12119 // These scales are formed with basereg+scalereg. Only accept if there is
12124 default: // Other stuff never works.
12132 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12133 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12135 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12136 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12137 if (NumBits1 <= NumBits2)
12142 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12143 return Imm == (int32_t)Imm;
12146 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
12147 // Can also use sub to handle negated immediates.
12148 return Imm == (int32_t)Imm;
12151 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12152 if (!VT1.isInteger() || !VT2.isInteger())
12154 unsigned NumBits1 = VT1.getSizeInBits();
12155 unsigned NumBits2 = VT2.getSizeInBits();
12156 if (NumBits1 <= NumBits2)
12161 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
12162 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12163 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
12166 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
12167 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12168 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
12171 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12172 EVT VT1 = Val.getValueType();
12173 if (isZExtFree(VT1, VT2))
12176 if (Val.getOpcode() != ISD::LOAD)
12179 if (!VT1.isSimple() || !VT1.isInteger() ||
12180 !VT2.isSimple() || !VT2.isInteger())
12183 switch (VT1.getSimpleVT().SimpleTy) {
12188 // X86 has 8, 16, and 32-bit zero-extending loads.
12195 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
12196 // i16 instructions are longer (0x66 prefix) and potentially slower.
12197 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
12200 /// isShuffleMaskLegal - Targets can use this to indicate that they only
12201 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
12202 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12203 /// are assumed to be legal.
12205 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
12207 // Very little shuffling can be done for 64-bit vectors right now.
12208 if (VT.getSizeInBits() == 64)
12211 // FIXME: pshufb, blends, shifts.
12212 return (VT.getVectorNumElements() == 2 ||
12213 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
12214 isMOVLMask(M, VT) ||
12215 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
12216 isPSHUFDMask(M, VT) ||
12217 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
12218 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
12219 isPALIGNRMask(M, VT, Subtarget) ||
12220 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
12221 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
12222 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
12223 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
12227 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
12229 unsigned NumElts = VT.getVectorNumElements();
12230 // FIXME: This collection of masks seems suspect.
12233 if (NumElts == 4 && VT.is128BitVector()) {
12234 return (isMOVLMask(Mask, VT) ||
12235 isCommutedMOVLMask(Mask, VT, true) ||
12236 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
12237 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
12242 //===----------------------------------------------------------------------===//
12243 // X86 Scheduler Hooks
12244 //===----------------------------------------------------------------------===//
12246 /// Utility function to emit xbegin specifying the start of an RTM region.
12247 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
12248 const TargetInstrInfo *TII) {
12249 DebugLoc DL = MI->getDebugLoc();
12251 const BasicBlock *BB = MBB->getBasicBlock();
12252 MachineFunction::iterator I = MBB;
12255 // For the v = xbegin(), we generate
12266 MachineBasicBlock *thisMBB = MBB;
12267 MachineFunction *MF = MBB->getParent();
12268 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12269 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12270 MF->insert(I, mainMBB);
12271 MF->insert(I, sinkMBB);
12273 // Transfer the remainder of BB and its successor edges to sinkMBB.
12274 sinkMBB->splice(sinkMBB->begin(), MBB,
12275 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12276 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12280 // # fallthrough to mainMBB
12281 // # abortion to sinkMBB
12282 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
12283 thisMBB->addSuccessor(mainMBB);
12284 thisMBB->addSuccessor(sinkMBB);
12288 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12289 mainMBB->addSuccessor(sinkMBB);
12292 // EAX is live into the sinkMBB
12293 sinkMBB->addLiveIn(X86::EAX);
12294 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12295 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12298 MI->eraseFromParent();
12302 // Get CMPXCHG opcode for the specified data type.
12303 static unsigned getCmpXChgOpcode(EVT VT) {
12304 switch (VT.getSimpleVT().SimpleTy) {
12305 case MVT::i8: return X86::LCMPXCHG8;
12306 case MVT::i16: return X86::LCMPXCHG16;
12307 case MVT::i32: return X86::LCMPXCHG32;
12308 case MVT::i64: return X86::LCMPXCHG64;
12312 llvm_unreachable("Invalid operand size!");
12315 // Get LOAD opcode for the specified data type.
12316 static unsigned getLoadOpcode(EVT VT) {
12317 switch (VT.getSimpleVT().SimpleTy) {
12318 case MVT::i8: return X86::MOV8rm;
12319 case MVT::i16: return X86::MOV16rm;
12320 case MVT::i32: return X86::MOV32rm;
12321 case MVT::i64: return X86::MOV64rm;
12325 llvm_unreachable("Invalid operand size!");
12328 // Get opcode of the non-atomic one from the specified atomic instruction.
12329 static unsigned getNonAtomicOpcode(unsigned Opc) {
12331 case X86::ATOMAND8: return X86::AND8rr;
12332 case X86::ATOMAND16: return X86::AND16rr;
12333 case X86::ATOMAND32: return X86::AND32rr;
12334 case X86::ATOMAND64: return X86::AND64rr;
12335 case X86::ATOMOR8: return X86::OR8rr;
12336 case X86::ATOMOR16: return X86::OR16rr;
12337 case X86::ATOMOR32: return X86::OR32rr;
12338 case X86::ATOMOR64: return X86::OR64rr;
12339 case X86::ATOMXOR8: return X86::XOR8rr;
12340 case X86::ATOMXOR16: return X86::XOR16rr;
12341 case X86::ATOMXOR32: return X86::XOR32rr;
12342 case X86::ATOMXOR64: return X86::XOR64rr;
12344 llvm_unreachable("Unhandled atomic-load-op opcode!");
12347 // Get opcode of the non-atomic one from the specified atomic instruction with
12349 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
12350 unsigned &ExtraOpc) {
12352 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
12353 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
12354 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
12355 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
12356 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
12357 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
12358 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
12359 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
12360 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
12361 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
12362 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
12363 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
12364 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
12365 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
12366 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
12367 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
12368 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
12369 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
12370 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
12371 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
12373 llvm_unreachable("Unhandled atomic-load-op opcode!");
12376 // Get opcode of the non-atomic one from the specified atomic instruction for
12377 // 64-bit data type on 32-bit target.
12378 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
12380 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
12381 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
12382 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
12383 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
12384 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
12385 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
12386 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
12387 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
12388 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
12389 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
12391 llvm_unreachable("Unhandled atomic-load-op opcode!");
12394 // Get opcode of the non-atomic one from the specified atomic instruction for
12395 // 64-bit data type on 32-bit target with extra opcode.
12396 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
12398 unsigned &ExtraOpc) {
12400 case X86::ATOMNAND6432:
12401 ExtraOpc = X86::NOT32r;
12402 HiOpc = X86::AND32rr;
12403 return X86::AND32rr;
12405 llvm_unreachable("Unhandled atomic-load-op opcode!");
12408 // Get pseudo CMOV opcode from the specified data type.
12409 static unsigned getPseudoCMOVOpc(EVT VT) {
12410 switch (VT.getSimpleVT().SimpleTy) {
12411 case MVT::i8: return X86::CMOV_GR8;
12412 case MVT::i16: return X86::CMOV_GR16;
12413 case MVT::i32: return X86::CMOV_GR32;
12417 llvm_unreachable("Unknown CMOV opcode!");
12420 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
12421 // They will be translated into a spin-loop or compare-exchange loop from
12424 // dst = atomic-fetch-op MI.addr, MI.val
12430 // EAX = LOAD MI.addr
12432 // t1 = OP MI.val, EAX
12433 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12438 MachineBasicBlock *
12439 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
12440 MachineBasicBlock *MBB) const {
12441 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12442 DebugLoc DL = MI->getDebugLoc();
12444 MachineFunction *MF = MBB->getParent();
12445 MachineRegisterInfo &MRI = MF->getRegInfo();
12447 const BasicBlock *BB = MBB->getBasicBlock();
12448 MachineFunction::iterator I = MBB;
12451 assert(MI->getNumOperands() <= X86::AddrNumOperands + 2 &&
12452 "Unexpected number of operands");
12454 assert(MI->hasOneMemOperand() &&
12455 "Expected atomic-load-op to have one memoperand");
12457 // Memory Reference
12458 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12459 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12461 unsigned DstReg, SrcReg;
12462 unsigned MemOpndSlot;
12464 unsigned CurOp = 0;
12466 DstReg = MI->getOperand(CurOp++).getReg();
12467 MemOpndSlot = CurOp;
12468 CurOp += X86::AddrNumOperands;
12469 SrcReg = MI->getOperand(CurOp++).getReg();
12471 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
12472 MVT::SimpleValueType VT = *RC->vt_begin();
12473 unsigned AccPhyReg = getX86SubSuperRegister(X86::EAX, VT);
12475 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
12476 unsigned LOADOpc = getLoadOpcode(VT);
12478 // For the atomic load-arith operator, we generate
12481 // EAX = LOAD [MI.addr]
12483 // t1 = OP MI.val, EAX
12484 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12488 MachineBasicBlock *thisMBB = MBB;
12489 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12490 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12491 MF->insert(I, mainMBB);
12492 MF->insert(I, sinkMBB);
12494 MachineInstrBuilder MIB;
12496 // Transfer the remainder of BB and its successor edges to sinkMBB.
12497 sinkMBB->splice(sinkMBB->begin(), MBB,
12498 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12499 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12502 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), AccPhyReg);
12503 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12504 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12505 MIB.setMemRefs(MMOBegin, MMOEnd);
12507 thisMBB->addSuccessor(mainMBB);
12510 MachineBasicBlock *origMainMBB = mainMBB;
12511 mainMBB->addLiveIn(AccPhyReg);
12513 // Copy AccPhyReg as it is used more than once.
12514 unsigned AccReg = MRI.createVirtualRegister(RC);
12515 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccReg)
12516 .addReg(AccPhyReg);
12518 unsigned t1 = MRI.createVirtualRegister(RC);
12519 unsigned Opc = MI->getOpcode();
12522 llvm_unreachable("Unhandled atomic-load-op opcode!");
12523 case X86::ATOMAND8:
12524 case X86::ATOMAND16:
12525 case X86::ATOMAND32:
12526 case X86::ATOMAND64:
12528 case X86::ATOMOR16:
12529 case X86::ATOMOR32:
12530 case X86::ATOMOR64:
12531 case X86::ATOMXOR8:
12532 case X86::ATOMXOR16:
12533 case X86::ATOMXOR32:
12534 case X86::ATOMXOR64: {
12535 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
12536 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t1).addReg(SrcReg)
12540 case X86::ATOMNAND8:
12541 case X86::ATOMNAND16:
12542 case X86::ATOMNAND32:
12543 case X86::ATOMNAND64: {
12544 unsigned t2 = MRI.createVirtualRegister(RC);
12546 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
12547 BuildMI(mainMBB, DL, TII->get(ANDOpc), t2).addReg(SrcReg)
12549 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2);
12552 case X86::ATOMMAX8:
12553 case X86::ATOMMAX16:
12554 case X86::ATOMMAX32:
12555 case X86::ATOMMAX64:
12556 case X86::ATOMMIN8:
12557 case X86::ATOMMIN16:
12558 case X86::ATOMMIN32:
12559 case X86::ATOMMIN64:
12560 case X86::ATOMUMAX8:
12561 case X86::ATOMUMAX16:
12562 case X86::ATOMUMAX32:
12563 case X86::ATOMUMAX64:
12564 case X86::ATOMUMIN8:
12565 case X86::ATOMUMIN16:
12566 case X86::ATOMUMIN32:
12567 case X86::ATOMUMIN64: {
12569 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
12571 BuildMI(mainMBB, DL, TII->get(CMPOpc))
12575 if (Subtarget->hasCMov()) {
12576 if (VT != MVT::i8) {
12578 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t1)
12582 // Promote i8 to i32 to use CMOV32
12583 const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32);
12584 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
12585 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
12586 unsigned t2 = MRI.createVirtualRegister(RC32);
12588 unsigned Undef = MRI.createVirtualRegister(RC32);
12589 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
12591 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
12594 .addImm(X86::sub_8bit);
12595 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
12598 .addImm(X86::sub_8bit);
12600 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
12604 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t1)
12605 .addReg(t2, 0, X86::sub_8bit);
12608 // Use pseudo select and lower them.
12609 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
12610 "Invalid atomic-load-op transformation!");
12611 unsigned SelOpc = getPseudoCMOVOpc(VT);
12612 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
12613 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
12614 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t1)
12615 .addReg(SrcReg).addReg(AccReg)
12617 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12623 // Copy AccPhyReg back from virtual register.
12624 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccPhyReg)
12627 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
12628 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12629 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12631 MIB.setMemRefs(MMOBegin, MMOEnd);
12633 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
12635 mainMBB->addSuccessor(origMainMBB);
12636 mainMBB->addSuccessor(sinkMBB);
12639 sinkMBB->addLiveIn(AccPhyReg);
12641 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12642 TII->get(TargetOpcode::COPY), DstReg)
12643 .addReg(AccPhyReg);
12645 MI->eraseFromParent();
12649 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
12650 // instructions. They will be translated into a spin-loop or compare-exchange
12654 // dst = atomic-fetch-op MI.addr, MI.val
12660 // EAX = LOAD [MI.addr + 0]
12661 // EDX = LOAD [MI.addr + 4]
12663 // EBX = OP MI.val.lo, EAX
12664 // ECX = OP MI.val.hi, EDX
12665 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
12670 MachineBasicBlock *
12671 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
12672 MachineBasicBlock *MBB) const {
12673 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12674 DebugLoc DL = MI->getDebugLoc();
12676 MachineFunction *MF = MBB->getParent();
12677 MachineRegisterInfo &MRI = MF->getRegInfo();
12679 const BasicBlock *BB = MBB->getBasicBlock();
12680 MachineFunction::iterator I = MBB;
12683 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
12684 "Unexpected number of operands");
12686 assert(MI->hasOneMemOperand() &&
12687 "Expected atomic-load-op32 to have one memoperand");
12689 // Memory Reference
12690 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12691 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12693 unsigned DstLoReg, DstHiReg;
12694 unsigned SrcLoReg, SrcHiReg;
12695 unsigned MemOpndSlot;
12697 unsigned CurOp = 0;
12699 DstLoReg = MI->getOperand(CurOp++).getReg();
12700 DstHiReg = MI->getOperand(CurOp++).getReg();
12701 MemOpndSlot = CurOp;
12702 CurOp += X86::AddrNumOperands;
12703 SrcLoReg = MI->getOperand(CurOp++).getReg();
12704 SrcHiReg = MI->getOperand(CurOp++).getReg();
12706 const TargetRegisterClass *RC = &X86::GR32RegClass;
12707 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
12709 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
12710 unsigned LOADOpc = X86::MOV32rm;
12712 // For the atomic load-arith operator, we generate
12715 // EAX = LOAD [MI.addr + 0]
12716 // EDX = LOAD [MI.addr + 4]
12718 // EBX = OP MI.vallo, EAX
12719 // ECX = OP MI.valhi, EDX
12720 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
12724 MachineBasicBlock *thisMBB = MBB;
12725 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12726 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12727 MF->insert(I, mainMBB);
12728 MF->insert(I, sinkMBB);
12730 MachineInstrBuilder MIB;
12732 // Transfer the remainder of BB and its successor edges to sinkMBB.
12733 sinkMBB->splice(sinkMBB->begin(), MBB,
12734 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12735 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12739 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EAX);
12740 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12741 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12742 MIB.setMemRefs(MMOBegin, MMOEnd);
12744 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX);
12745 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
12746 if (i == X86::AddrDisp)
12747 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
12749 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12751 MIB.setMemRefs(MMOBegin, MMOEnd);
12753 thisMBB->addSuccessor(mainMBB);
12756 MachineBasicBlock *origMainMBB = mainMBB;
12757 mainMBB->addLiveIn(X86::EAX);
12758 mainMBB->addLiveIn(X86::EDX);
12760 // Copy EDX:EAX as they are used more than once.
12761 unsigned LoReg = MRI.createVirtualRegister(RC);
12762 unsigned HiReg = MRI.createVirtualRegister(RC);
12763 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), LoReg).addReg(X86::EAX);
12764 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), HiReg).addReg(X86::EDX);
12766 unsigned t1L = MRI.createVirtualRegister(RC);
12767 unsigned t1H = MRI.createVirtualRegister(RC);
12769 unsigned Opc = MI->getOpcode();
12772 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
12773 case X86::ATOMAND6432:
12774 case X86::ATOMOR6432:
12775 case X86::ATOMXOR6432:
12776 case X86::ATOMADD6432:
12777 case X86::ATOMSUB6432: {
12779 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
12780 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
12781 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
12784 case X86::ATOMNAND6432: {
12785 unsigned HiOpc, NOTOpc;
12786 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
12787 unsigned t2L = MRI.createVirtualRegister(RC);
12788 unsigned t2H = MRI.createVirtualRegister(RC);
12789 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg).addReg(LoReg);
12790 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg).addReg(HiReg);
12791 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1L).addReg(t2L);
12792 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1H).addReg(t2H);
12795 case X86::ATOMMAX6432:
12796 case X86::ATOMMIN6432:
12797 case X86::ATOMUMAX6432:
12798 case X86::ATOMUMIN6432: {
12800 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
12801 unsigned cL = MRI.createVirtualRegister(RC8);
12802 unsigned cH = MRI.createVirtualRegister(RC8);
12803 unsigned cL32 = MRI.createVirtualRegister(RC);
12804 unsigned cH32 = MRI.createVirtualRegister(RC);
12805 unsigned cc = MRI.createVirtualRegister(RC);
12806 // cl := cmp src_lo, lo
12807 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
12808 .addReg(SrcLoReg).addReg(LoReg);
12809 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
12810 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
12811 // ch := cmp src_hi, hi
12812 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
12813 .addReg(SrcHiReg).addReg(HiReg);
12814 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
12815 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
12816 // cc := if (src_hi == hi) ? cl : ch;
12817 if (Subtarget->hasCMov()) {
12818 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
12819 .addReg(cH32).addReg(cL32);
12821 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
12822 .addReg(cH32).addReg(cL32)
12823 .addImm(X86::COND_E);
12824 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12826 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
12827 if (Subtarget->hasCMov()) {
12828 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1L)
12829 .addReg(SrcLoReg).addReg(LoReg);
12830 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1H)
12831 .addReg(SrcHiReg).addReg(HiReg);
12833 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1L)
12834 .addReg(SrcLoReg).addReg(LoReg)
12835 .addImm(X86::COND_NE);
12836 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12837 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1H)
12838 .addReg(SrcHiReg).addReg(HiReg)
12839 .addImm(X86::COND_NE);
12840 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12844 case X86::ATOMSWAP6432: {
12846 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
12847 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg);
12848 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg);
12853 // Copy EDX:EAX back from HiReg:LoReg
12854 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(LoReg);
12855 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(HiReg);
12856 // Copy ECX:EBX from t1H:t1L
12857 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t1L);
12858 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t1H);
12860 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
12861 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12862 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12863 MIB.setMemRefs(MMOBegin, MMOEnd);
12865 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
12867 mainMBB->addSuccessor(origMainMBB);
12868 mainMBB->addSuccessor(sinkMBB);
12871 sinkMBB->addLiveIn(X86::EAX);
12872 sinkMBB->addLiveIn(X86::EDX);
12874 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12875 TII->get(TargetOpcode::COPY), DstLoReg)
12877 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12878 TII->get(TargetOpcode::COPY), DstHiReg)
12881 MI->eraseFromParent();
12885 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
12886 // or XMM0_V32I8 in AVX all of this code can be replaced with that
12887 // in the .td file.
12888 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
12889 const TargetInstrInfo *TII) {
12891 switch (MI->getOpcode()) {
12892 default: llvm_unreachable("illegal opcode!");
12893 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
12894 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
12895 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
12896 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
12897 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
12898 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
12899 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
12900 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
12903 DebugLoc dl = MI->getDebugLoc();
12904 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12906 unsigned NumArgs = MI->getNumOperands();
12907 for (unsigned i = 1; i < NumArgs; ++i) {
12908 MachineOperand &Op = MI->getOperand(i);
12909 if (!(Op.isReg() && Op.isImplicit()))
12910 MIB.addOperand(Op);
12912 if (MI->hasOneMemOperand())
12913 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
12915 BuildMI(*BB, MI, dl,
12916 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12917 .addReg(X86::XMM0);
12919 MI->eraseFromParent();
12923 // FIXME: Custom handling because TableGen doesn't support multiple implicit
12924 // defs in an instruction pattern
12925 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
12926 const TargetInstrInfo *TII) {
12928 switch (MI->getOpcode()) {
12929 default: llvm_unreachable("illegal opcode!");
12930 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
12931 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
12932 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
12933 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
12934 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
12935 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
12936 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
12937 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
12940 DebugLoc dl = MI->getDebugLoc();
12941 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12943 unsigned NumArgs = MI->getNumOperands(); // remove the results
12944 for (unsigned i = 1; i < NumArgs; ++i) {
12945 MachineOperand &Op = MI->getOperand(i);
12946 if (!(Op.isReg() && Op.isImplicit()))
12947 MIB.addOperand(Op);
12949 if (MI->hasOneMemOperand())
12950 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
12952 BuildMI(*BB, MI, dl,
12953 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12956 MI->eraseFromParent();
12960 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
12961 const TargetInstrInfo *TII,
12962 const X86Subtarget* Subtarget) {
12963 DebugLoc dl = MI->getDebugLoc();
12965 // Address into RAX/EAX, other two args into ECX, EDX.
12966 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
12967 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12968 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
12969 for (int i = 0; i < X86::AddrNumOperands; ++i)
12970 MIB.addOperand(MI->getOperand(i));
12972 unsigned ValOps = X86::AddrNumOperands;
12973 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
12974 .addReg(MI->getOperand(ValOps).getReg());
12975 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
12976 .addReg(MI->getOperand(ValOps+1).getReg());
12978 // The instruction doesn't actually take any operands though.
12979 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
12981 MI->eraseFromParent(); // The pseudo is gone now.
12985 MachineBasicBlock *
12986 X86TargetLowering::EmitVAARG64WithCustomInserter(
12988 MachineBasicBlock *MBB) const {
12989 // Emit va_arg instruction on X86-64.
12991 // Operands to this pseudo-instruction:
12992 // 0 ) Output : destination address (reg)
12993 // 1-5) Input : va_list address (addr, i64mem)
12994 // 6 ) ArgSize : Size (in bytes) of vararg type
12995 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
12996 // 8 ) Align : Alignment of type
12997 // 9 ) EFLAGS (implicit-def)
12999 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
13000 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
13002 unsigned DestReg = MI->getOperand(0).getReg();
13003 MachineOperand &Base = MI->getOperand(1);
13004 MachineOperand &Scale = MI->getOperand(2);
13005 MachineOperand &Index = MI->getOperand(3);
13006 MachineOperand &Disp = MI->getOperand(4);
13007 MachineOperand &Segment = MI->getOperand(5);
13008 unsigned ArgSize = MI->getOperand(6).getImm();
13009 unsigned ArgMode = MI->getOperand(7).getImm();
13010 unsigned Align = MI->getOperand(8).getImm();
13012 // Memory Reference
13013 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
13014 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13015 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13017 // Machine Information
13018 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13019 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
13020 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
13021 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
13022 DebugLoc DL = MI->getDebugLoc();
13024 // struct va_list {
13027 // i64 overflow_area (address)
13028 // i64 reg_save_area (address)
13030 // sizeof(va_list) = 24
13031 // alignment(va_list) = 8
13033 unsigned TotalNumIntRegs = 6;
13034 unsigned TotalNumXMMRegs = 8;
13035 bool UseGPOffset = (ArgMode == 1);
13036 bool UseFPOffset = (ArgMode == 2);
13037 unsigned MaxOffset = TotalNumIntRegs * 8 +
13038 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
13040 /* Align ArgSize to a multiple of 8 */
13041 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
13042 bool NeedsAlign = (Align > 8);
13044 MachineBasicBlock *thisMBB = MBB;
13045 MachineBasicBlock *overflowMBB;
13046 MachineBasicBlock *offsetMBB;
13047 MachineBasicBlock *endMBB;
13049 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
13050 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
13051 unsigned OffsetReg = 0;
13053 if (!UseGPOffset && !UseFPOffset) {
13054 // If we only pull from the overflow region, we don't create a branch.
13055 // We don't need to alter control flow.
13056 OffsetDestReg = 0; // unused
13057 OverflowDestReg = DestReg;
13060 overflowMBB = thisMBB;
13063 // First emit code to check if gp_offset (or fp_offset) is below the bound.
13064 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
13065 // If not, pull from overflow_area. (branch to overflowMBB)
13070 // offsetMBB overflowMBB
13075 // Registers for the PHI in endMBB
13076 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
13077 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
13079 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13080 MachineFunction *MF = MBB->getParent();
13081 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13082 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13083 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13085 MachineFunction::iterator MBBIter = MBB;
13088 // Insert the new basic blocks
13089 MF->insert(MBBIter, offsetMBB);
13090 MF->insert(MBBIter, overflowMBB);
13091 MF->insert(MBBIter, endMBB);
13093 // Transfer the remainder of MBB and its successor edges to endMBB.
13094 endMBB->splice(endMBB->begin(), thisMBB,
13095 llvm::next(MachineBasicBlock::iterator(MI)),
13097 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
13099 // Make offsetMBB and overflowMBB successors of thisMBB
13100 thisMBB->addSuccessor(offsetMBB);
13101 thisMBB->addSuccessor(overflowMBB);
13103 // endMBB is a successor of both offsetMBB and overflowMBB
13104 offsetMBB->addSuccessor(endMBB);
13105 overflowMBB->addSuccessor(endMBB);
13107 // Load the offset value into a register
13108 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13109 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13113 .addDisp(Disp, UseFPOffset ? 4 : 0)
13114 .addOperand(Segment)
13115 .setMemRefs(MMOBegin, MMOEnd);
13117 // Check if there is enough room left to pull this argument.
13118 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13120 .addImm(MaxOffset + 8 - ArgSizeA8);
13122 // Branch to "overflowMBB" if offset >= max
13123 // Fall through to "offsetMBB" otherwise
13124 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13125 .addMBB(overflowMBB);
13128 // In offsetMBB, emit code to use the reg_save_area.
13130 assert(OffsetReg != 0);
13132 // Read the reg_save_area address.
13133 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
13134 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13139 .addOperand(Segment)
13140 .setMemRefs(MMOBegin, MMOEnd);
13142 // Zero-extend the offset
13143 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
13144 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13147 .addImm(X86::sub_32bit);
13149 // Add the offset to the reg_save_area to get the final address.
13150 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13151 .addReg(OffsetReg64)
13152 .addReg(RegSaveReg);
13154 // Compute the offset for the next argument
13155 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13156 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13158 .addImm(UseFPOffset ? 16 : 8);
13160 // Store it back into the va_list.
13161 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13165 .addDisp(Disp, UseFPOffset ? 4 : 0)
13166 .addOperand(Segment)
13167 .addReg(NextOffsetReg)
13168 .setMemRefs(MMOBegin, MMOEnd);
13171 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
13176 // Emit code to use overflow area
13179 // Load the overflow_area address into a register.
13180 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
13181 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
13186 .addOperand(Segment)
13187 .setMemRefs(MMOBegin, MMOEnd);
13189 // If we need to align it, do so. Otherwise, just copy the address
13190 // to OverflowDestReg.
13192 // Align the overflow address
13193 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
13194 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
13196 // aligned_addr = (addr + (align-1)) & ~(align-1)
13197 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
13198 .addReg(OverflowAddrReg)
13201 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
13203 .addImm(~(uint64_t)(Align-1));
13205 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
13206 .addReg(OverflowAddrReg);
13209 // Compute the next overflow address after this argument.
13210 // (the overflow address should be kept 8-byte aligned)
13211 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
13212 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
13213 .addReg(OverflowDestReg)
13214 .addImm(ArgSizeA8);
13216 // Store the new overflow address.
13217 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
13222 .addOperand(Segment)
13223 .addReg(NextAddrReg)
13224 .setMemRefs(MMOBegin, MMOEnd);
13226 // If we branched, emit the PHI to the front of endMBB.
13228 BuildMI(*endMBB, endMBB->begin(), DL,
13229 TII->get(X86::PHI), DestReg)
13230 .addReg(OffsetDestReg).addMBB(offsetMBB)
13231 .addReg(OverflowDestReg).addMBB(overflowMBB);
13234 // Erase the pseudo instruction
13235 MI->eraseFromParent();
13240 MachineBasicBlock *
13241 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
13243 MachineBasicBlock *MBB) const {
13244 // Emit code to save XMM registers to the stack. The ABI says that the
13245 // number of registers to save is given in %al, so it's theoretically
13246 // possible to do an indirect jump trick to avoid saving all of them,
13247 // however this code takes a simpler approach and just executes all
13248 // of the stores if %al is non-zero. It's less code, and it's probably
13249 // easier on the hardware branch predictor, and stores aren't all that
13250 // expensive anyway.
13252 // Create the new basic blocks. One block contains all the XMM stores,
13253 // and one block is the final destination regardless of whether any
13254 // stores were performed.
13255 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13256 MachineFunction *F = MBB->getParent();
13257 MachineFunction::iterator MBBIter = MBB;
13259 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
13260 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
13261 F->insert(MBBIter, XMMSaveMBB);
13262 F->insert(MBBIter, EndMBB);
13264 // Transfer the remainder of MBB and its successor edges to EndMBB.
13265 EndMBB->splice(EndMBB->begin(), MBB,
13266 llvm::next(MachineBasicBlock::iterator(MI)),
13268 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
13270 // The original block will now fall through to the XMM save block.
13271 MBB->addSuccessor(XMMSaveMBB);
13272 // The XMMSaveMBB will fall through to the end block.
13273 XMMSaveMBB->addSuccessor(EndMBB);
13275 // Now add the instructions.
13276 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13277 DebugLoc DL = MI->getDebugLoc();
13279 unsigned CountReg = MI->getOperand(0).getReg();
13280 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
13281 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
13283 if (!Subtarget->isTargetWin64()) {
13284 // If %al is 0, branch around the XMM save block.
13285 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
13286 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
13287 MBB->addSuccessor(EndMBB);
13290 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
13291 // In the XMM save block, save all the XMM argument registers.
13292 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
13293 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
13294 MachineMemOperand *MMO =
13295 F->getMachineMemOperand(
13296 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
13297 MachineMemOperand::MOStore,
13298 /*Size=*/16, /*Align=*/16);
13299 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
13300 .addFrameIndex(RegSaveFrameIndex)
13301 .addImm(/*Scale=*/1)
13302 .addReg(/*IndexReg=*/0)
13303 .addImm(/*Disp=*/Offset)
13304 .addReg(/*Segment=*/0)
13305 .addReg(MI->getOperand(i).getReg())
13306 .addMemOperand(MMO);
13309 MI->eraseFromParent(); // The pseudo instruction is gone now.
13314 // The EFLAGS operand of SelectItr might be missing a kill marker
13315 // because there were multiple uses of EFLAGS, and ISel didn't know
13316 // which to mark. Figure out whether SelectItr should have had a
13317 // kill marker, and set it if it should. Returns the correct kill
13319 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
13320 MachineBasicBlock* BB,
13321 const TargetRegisterInfo* TRI) {
13322 // Scan forward through BB for a use/def of EFLAGS.
13323 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
13324 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
13325 const MachineInstr& mi = *miI;
13326 if (mi.readsRegister(X86::EFLAGS))
13328 if (mi.definesRegister(X86::EFLAGS))
13329 break; // Should have kill-flag - update below.
13332 // If we hit the end of the block, check whether EFLAGS is live into a
13334 if (miI == BB->end()) {
13335 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
13336 sEnd = BB->succ_end();
13337 sItr != sEnd; ++sItr) {
13338 MachineBasicBlock* succ = *sItr;
13339 if (succ->isLiveIn(X86::EFLAGS))
13344 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
13345 // out. SelectMI should have a kill flag on EFLAGS.
13346 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
13350 MachineBasicBlock *
13351 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
13352 MachineBasicBlock *BB) const {
13353 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13354 DebugLoc DL = MI->getDebugLoc();
13356 // To "insert" a SELECT_CC instruction, we actually have to insert the
13357 // diamond control-flow pattern. The incoming instruction knows the
13358 // destination vreg to set, the condition code register to branch on, the
13359 // true/false values to select between, and a branch opcode to use.
13360 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13361 MachineFunction::iterator It = BB;
13367 // cmpTY ccX, r1, r2
13369 // fallthrough --> copy0MBB
13370 MachineBasicBlock *thisMBB = BB;
13371 MachineFunction *F = BB->getParent();
13372 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
13373 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
13374 F->insert(It, copy0MBB);
13375 F->insert(It, sinkMBB);
13377 // If the EFLAGS register isn't dead in the terminator, then claim that it's
13378 // live into the sink and copy blocks.
13379 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13380 if (!MI->killsRegister(X86::EFLAGS) &&
13381 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
13382 copy0MBB->addLiveIn(X86::EFLAGS);
13383 sinkMBB->addLiveIn(X86::EFLAGS);
13386 // Transfer the remainder of BB and its successor edges to sinkMBB.
13387 sinkMBB->splice(sinkMBB->begin(), BB,
13388 llvm::next(MachineBasicBlock::iterator(MI)),
13390 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
13392 // Add the true and fallthrough blocks as its successors.
13393 BB->addSuccessor(copy0MBB);
13394 BB->addSuccessor(sinkMBB);
13396 // Create the conditional branch instruction.
13398 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
13399 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
13402 // %FalseValue = ...
13403 // # fallthrough to sinkMBB
13404 copy0MBB->addSuccessor(sinkMBB);
13407 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
13409 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13410 TII->get(X86::PHI), MI->getOperand(0).getReg())
13411 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
13412 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
13414 MI->eraseFromParent(); // The pseudo instruction is gone now.
13418 MachineBasicBlock *
13419 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
13420 bool Is64Bit) const {
13421 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13422 DebugLoc DL = MI->getDebugLoc();
13423 MachineFunction *MF = BB->getParent();
13424 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13426 assert(getTargetMachine().Options.EnableSegmentedStacks);
13428 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
13429 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
13432 // ... [Till the alloca]
13433 // If stacklet is not large enough, jump to mallocMBB
13436 // Allocate by subtracting from RSP
13437 // Jump to continueMBB
13440 // Allocate by call to runtime
13444 // [rest of original BB]
13447 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13448 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13449 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13451 MachineRegisterInfo &MRI = MF->getRegInfo();
13452 const TargetRegisterClass *AddrRegClass =
13453 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
13455 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13456 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13457 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
13458 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
13459 sizeVReg = MI->getOperand(1).getReg(),
13460 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
13462 MachineFunction::iterator MBBIter = BB;
13465 MF->insert(MBBIter, bumpMBB);
13466 MF->insert(MBBIter, mallocMBB);
13467 MF->insert(MBBIter, continueMBB);
13469 continueMBB->splice(continueMBB->begin(), BB, llvm::next
13470 (MachineBasicBlock::iterator(MI)), BB->end());
13471 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
13473 // Add code to the main basic block to check if the stack limit has been hit,
13474 // and if so, jump to mallocMBB otherwise to bumpMBB.
13475 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
13476 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
13477 .addReg(tmpSPVReg).addReg(sizeVReg);
13478 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
13479 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
13480 .addReg(SPLimitVReg);
13481 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
13483 // bumpMBB simply decreases the stack pointer, since we know the current
13484 // stacklet has enough space.
13485 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
13486 .addReg(SPLimitVReg);
13487 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
13488 .addReg(SPLimitVReg);
13489 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13491 // Calls into a routine in libgcc to allocate more space from the heap.
13492 const uint32_t *RegMask =
13493 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13495 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
13497 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
13498 .addExternalSymbol("__morestack_allocate_stack_space")
13499 .addRegMask(RegMask)
13500 .addReg(X86::RDI, RegState::Implicit)
13501 .addReg(X86::RAX, RegState::ImplicitDefine);
13503 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
13505 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
13506 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
13507 .addExternalSymbol("__morestack_allocate_stack_space")
13508 .addRegMask(RegMask)
13509 .addReg(X86::EAX, RegState::ImplicitDefine);
13513 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
13516 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
13517 .addReg(Is64Bit ? X86::RAX : X86::EAX);
13518 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13520 // Set up the CFG correctly.
13521 BB->addSuccessor(bumpMBB);
13522 BB->addSuccessor(mallocMBB);
13523 mallocMBB->addSuccessor(continueMBB);
13524 bumpMBB->addSuccessor(continueMBB);
13526 // Take care of the PHI nodes.
13527 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
13528 MI->getOperand(0).getReg())
13529 .addReg(mallocPtrVReg).addMBB(mallocMBB)
13530 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
13532 // Delete the original pseudo instruction.
13533 MI->eraseFromParent();
13536 return continueMBB;
13539 MachineBasicBlock *
13540 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
13541 MachineBasicBlock *BB) const {
13542 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13543 DebugLoc DL = MI->getDebugLoc();
13545 assert(!Subtarget->isTargetEnvMacho());
13547 // The lowering is pretty easy: we're just emitting the call to _alloca. The
13548 // non-trivial part is impdef of ESP.
13550 if (Subtarget->isTargetWin64()) {
13551 if (Subtarget->isTargetCygMing()) {
13552 // ___chkstk(Mingw64):
13553 // Clobbers R10, R11, RAX and EFLAGS.
13555 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13556 .addExternalSymbol("___chkstk")
13557 .addReg(X86::RAX, RegState::Implicit)
13558 .addReg(X86::RSP, RegState::Implicit)
13559 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
13560 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
13561 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13563 // __chkstk(MSVCRT): does not update stack pointer.
13564 // Clobbers R10, R11 and EFLAGS.
13565 // FIXME: RAX(allocated size) might be reused and not killed.
13566 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13567 .addExternalSymbol("__chkstk")
13568 .addReg(X86::RAX, RegState::Implicit)
13569 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13570 // RAX has the offset to subtracted from RSP.
13571 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
13576 const char *StackProbeSymbol =
13577 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
13579 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
13580 .addExternalSymbol(StackProbeSymbol)
13581 .addReg(X86::EAX, RegState::Implicit)
13582 .addReg(X86::ESP, RegState::Implicit)
13583 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
13584 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
13585 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13588 MI->eraseFromParent(); // The pseudo instruction is gone now.
13592 MachineBasicBlock *
13593 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
13594 MachineBasicBlock *BB) const {
13595 // This is pretty easy. We're taking the value that we received from
13596 // our load from the relocation, sticking it in either RDI (x86-64)
13597 // or EAX and doing an indirect call. The return value will then
13598 // be in the normal return register.
13599 const X86InstrInfo *TII
13600 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
13601 DebugLoc DL = MI->getDebugLoc();
13602 MachineFunction *F = BB->getParent();
13604 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
13605 assert(MI->getOperand(3).isGlobal() && "This should be a global");
13607 // Get a register mask for the lowered call.
13608 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
13609 // proper register mask.
13610 const uint32_t *RegMask =
13611 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13612 if (Subtarget->is64Bit()) {
13613 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13614 TII->get(X86::MOV64rm), X86::RDI)
13616 .addImm(0).addReg(0)
13617 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13618 MI->getOperand(3).getTargetFlags())
13620 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
13621 addDirectMem(MIB, X86::RDI);
13622 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
13623 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
13624 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13625 TII->get(X86::MOV32rm), X86::EAX)
13627 .addImm(0).addReg(0)
13628 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13629 MI->getOperand(3).getTargetFlags())
13631 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
13632 addDirectMem(MIB, X86::EAX);
13633 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
13635 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13636 TII->get(X86::MOV32rm), X86::EAX)
13637 .addReg(TII->getGlobalBaseReg(F))
13638 .addImm(0).addReg(0)
13639 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13640 MI->getOperand(3).getTargetFlags())
13642 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
13643 addDirectMem(MIB, X86::EAX);
13644 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
13647 MI->eraseFromParent(); // The pseudo instruction is gone now.
13651 MachineBasicBlock *
13652 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
13653 MachineBasicBlock *MBB) const {
13654 DebugLoc DL = MI->getDebugLoc();
13655 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13657 MachineFunction *MF = MBB->getParent();
13658 MachineRegisterInfo &MRI = MF->getRegInfo();
13660 const BasicBlock *BB = MBB->getBasicBlock();
13661 MachineFunction::iterator I = MBB;
13664 // Memory Reference
13665 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13666 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13669 unsigned MemOpndSlot = 0;
13671 unsigned CurOp = 0;
13673 DstReg = MI->getOperand(CurOp++).getReg();
13674 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
13675 assert(RC->hasType(MVT::i32) && "Invalid destination!");
13676 unsigned mainDstReg = MRI.createVirtualRegister(RC);
13677 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
13679 MemOpndSlot = CurOp;
13681 MVT PVT = getPointerTy();
13682 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
13683 "Invalid Pointer Size!");
13685 // For v = setjmp(buf), we generate
13688 // buf[LabelOffset] = restoreMBB
13689 // SjLjSetup restoreMBB
13695 // v = phi(main, restore)
13700 MachineBasicBlock *thisMBB = MBB;
13701 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13702 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13703 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
13704 MF->insert(I, mainMBB);
13705 MF->insert(I, sinkMBB);
13706 MF->push_back(restoreMBB);
13708 MachineInstrBuilder MIB;
13710 // Transfer the remainder of BB and its successor edges to sinkMBB.
13711 sinkMBB->splice(sinkMBB->begin(), MBB,
13712 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13713 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13716 unsigned PtrStoreOpc = 0;
13717 unsigned LabelReg = 0;
13718 const int64_t LabelOffset = 1 * PVT.getStoreSize();
13719 Reloc::Model RM = getTargetMachine().getRelocationModel();
13720 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
13721 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
13723 // Prepare IP either in reg or imm.
13724 if (!UseImmLabel) {
13725 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
13726 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
13727 LabelReg = MRI.createVirtualRegister(PtrRC);
13728 if (Subtarget->is64Bit()) {
13729 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
13733 .addMBB(restoreMBB)
13736 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
13737 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
13738 .addReg(XII->getGlobalBaseReg(MF))
13741 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
13745 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
13747 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
13748 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13749 if (i == X86::AddrDisp)
13750 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
13752 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13755 MIB.addReg(LabelReg);
13757 MIB.addMBB(restoreMBB);
13758 MIB.setMemRefs(MMOBegin, MMOEnd);
13760 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
13761 .addMBB(restoreMBB);
13762 MIB.addRegMask(RegInfo->getNoPreservedMask());
13763 thisMBB->addSuccessor(mainMBB);
13764 thisMBB->addSuccessor(restoreMBB);
13768 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
13769 mainMBB->addSuccessor(sinkMBB);
13772 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13773 TII->get(X86::PHI), DstReg)
13774 .addReg(mainDstReg).addMBB(mainMBB)
13775 .addReg(restoreDstReg).addMBB(restoreMBB);
13778 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
13779 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
13780 restoreMBB->addSuccessor(sinkMBB);
13782 MI->eraseFromParent();
13786 MachineBasicBlock *
13787 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
13788 MachineBasicBlock *MBB) const {
13789 DebugLoc DL = MI->getDebugLoc();
13790 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13792 MachineFunction *MF = MBB->getParent();
13793 MachineRegisterInfo &MRI = MF->getRegInfo();
13795 // Memory Reference
13796 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13797 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13799 MVT PVT = getPointerTy();
13800 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
13801 "Invalid Pointer Size!");
13803 const TargetRegisterClass *RC =
13804 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
13805 unsigned Tmp = MRI.createVirtualRegister(RC);
13806 // Since FP is only updated here but NOT referenced, it's treated as GPR.
13807 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
13808 unsigned SP = RegInfo->getStackRegister();
13810 MachineInstrBuilder MIB;
13812 const int64_t LabelOffset = 1 * PVT.getStoreSize();
13813 const int64_t SPOffset = 2 * PVT.getStoreSize();
13815 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
13816 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
13819 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
13820 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13821 MIB.addOperand(MI->getOperand(i));
13822 MIB.setMemRefs(MMOBegin, MMOEnd);
13824 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
13825 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13826 if (i == X86::AddrDisp)
13827 MIB.addDisp(MI->getOperand(i), LabelOffset);
13829 MIB.addOperand(MI->getOperand(i));
13831 MIB.setMemRefs(MMOBegin, MMOEnd);
13833 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
13834 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13835 if (i == X86::AddrDisp)
13836 MIB.addDisp(MI->getOperand(i), SPOffset);
13838 MIB.addOperand(MI->getOperand(i));
13840 MIB.setMemRefs(MMOBegin, MMOEnd);
13842 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
13844 MI->eraseFromParent();
13848 MachineBasicBlock *
13849 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
13850 MachineBasicBlock *BB) const {
13851 switch (MI->getOpcode()) {
13852 default: llvm_unreachable("Unexpected instr type to insert");
13853 case X86::TAILJMPd64:
13854 case X86::TAILJMPr64:
13855 case X86::TAILJMPm64:
13856 llvm_unreachable("TAILJMP64 would not be touched here.");
13857 case X86::TCRETURNdi64:
13858 case X86::TCRETURNri64:
13859 case X86::TCRETURNmi64:
13861 case X86::WIN_ALLOCA:
13862 return EmitLoweredWinAlloca(MI, BB);
13863 case X86::SEG_ALLOCA_32:
13864 return EmitLoweredSegAlloca(MI, BB, false);
13865 case X86::SEG_ALLOCA_64:
13866 return EmitLoweredSegAlloca(MI, BB, true);
13867 case X86::TLSCall_32:
13868 case X86::TLSCall_64:
13869 return EmitLoweredTLSCall(MI, BB);
13870 case X86::CMOV_GR8:
13871 case X86::CMOV_FR32:
13872 case X86::CMOV_FR64:
13873 case X86::CMOV_V4F32:
13874 case X86::CMOV_V2F64:
13875 case X86::CMOV_V2I64:
13876 case X86::CMOV_V8F32:
13877 case X86::CMOV_V4F64:
13878 case X86::CMOV_V4I64:
13879 case X86::CMOV_GR16:
13880 case X86::CMOV_GR32:
13881 case X86::CMOV_RFP32:
13882 case X86::CMOV_RFP64:
13883 case X86::CMOV_RFP80:
13884 return EmitLoweredSelect(MI, BB);
13886 case X86::FP32_TO_INT16_IN_MEM:
13887 case X86::FP32_TO_INT32_IN_MEM:
13888 case X86::FP32_TO_INT64_IN_MEM:
13889 case X86::FP64_TO_INT16_IN_MEM:
13890 case X86::FP64_TO_INT32_IN_MEM:
13891 case X86::FP64_TO_INT64_IN_MEM:
13892 case X86::FP80_TO_INT16_IN_MEM:
13893 case X86::FP80_TO_INT32_IN_MEM:
13894 case X86::FP80_TO_INT64_IN_MEM: {
13895 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13896 DebugLoc DL = MI->getDebugLoc();
13898 // Change the floating point control register to use "round towards zero"
13899 // mode when truncating to an integer value.
13900 MachineFunction *F = BB->getParent();
13901 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
13902 addFrameReference(BuildMI(*BB, MI, DL,
13903 TII->get(X86::FNSTCW16m)), CWFrameIdx);
13905 // Load the old value of the high byte of the control word...
13907 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
13908 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
13911 // Set the high part to be round to zero...
13912 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
13915 // Reload the modified control word now...
13916 addFrameReference(BuildMI(*BB, MI, DL,
13917 TII->get(X86::FLDCW16m)), CWFrameIdx);
13919 // Restore the memory image of control word to original value
13920 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
13923 // Get the X86 opcode to use.
13925 switch (MI->getOpcode()) {
13926 default: llvm_unreachable("illegal opcode!");
13927 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
13928 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
13929 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
13930 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
13931 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
13932 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
13933 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
13934 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
13935 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
13939 MachineOperand &Op = MI->getOperand(0);
13941 AM.BaseType = X86AddressMode::RegBase;
13942 AM.Base.Reg = Op.getReg();
13944 AM.BaseType = X86AddressMode::FrameIndexBase;
13945 AM.Base.FrameIndex = Op.getIndex();
13947 Op = MI->getOperand(1);
13949 AM.Scale = Op.getImm();
13950 Op = MI->getOperand(2);
13952 AM.IndexReg = Op.getImm();
13953 Op = MI->getOperand(3);
13954 if (Op.isGlobal()) {
13955 AM.GV = Op.getGlobal();
13957 AM.Disp = Op.getImm();
13959 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
13960 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
13962 // Reload the original control word now.
13963 addFrameReference(BuildMI(*BB, MI, DL,
13964 TII->get(X86::FLDCW16m)), CWFrameIdx);
13966 MI->eraseFromParent(); // The pseudo instruction is gone now.
13969 // String/text processing lowering.
13970 case X86::PCMPISTRM128REG:
13971 case X86::VPCMPISTRM128REG:
13972 case X86::PCMPISTRM128MEM:
13973 case X86::VPCMPISTRM128MEM:
13974 case X86::PCMPESTRM128REG:
13975 case X86::VPCMPESTRM128REG:
13976 case X86::PCMPESTRM128MEM:
13977 case X86::VPCMPESTRM128MEM:
13978 assert(Subtarget->hasSSE42() &&
13979 "Target must have SSE4.2 or AVX features enabled");
13980 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
13982 // String/text processing lowering.
13983 case X86::PCMPISTRIREG:
13984 case X86::VPCMPISTRIREG:
13985 case X86::PCMPISTRIMEM:
13986 case X86::VPCMPISTRIMEM:
13987 case X86::PCMPESTRIREG:
13988 case X86::VPCMPESTRIREG:
13989 case X86::PCMPESTRIMEM:
13990 case X86::VPCMPESTRIMEM:
13991 assert(Subtarget->hasSSE42() &&
13992 "Target must have SSE4.2 or AVX features enabled");
13993 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
13995 // Thread synchronization.
13997 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
14001 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
14003 // Atomic Lowering.
14004 case X86::ATOMAND8:
14005 case X86::ATOMAND16:
14006 case X86::ATOMAND32:
14007 case X86::ATOMAND64:
14010 case X86::ATOMOR16:
14011 case X86::ATOMOR32:
14012 case X86::ATOMOR64:
14014 case X86::ATOMXOR16:
14015 case X86::ATOMXOR8:
14016 case X86::ATOMXOR32:
14017 case X86::ATOMXOR64:
14019 case X86::ATOMNAND8:
14020 case X86::ATOMNAND16:
14021 case X86::ATOMNAND32:
14022 case X86::ATOMNAND64:
14024 case X86::ATOMMAX8:
14025 case X86::ATOMMAX16:
14026 case X86::ATOMMAX32:
14027 case X86::ATOMMAX64:
14029 case X86::ATOMMIN8:
14030 case X86::ATOMMIN16:
14031 case X86::ATOMMIN32:
14032 case X86::ATOMMIN64:
14034 case X86::ATOMUMAX8:
14035 case X86::ATOMUMAX16:
14036 case X86::ATOMUMAX32:
14037 case X86::ATOMUMAX64:
14039 case X86::ATOMUMIN8:
14040 case X86::ATOMUMIN16:
14041 case X86::ATOMUMIN32:
14042 case X86::ATOMUMIN64:
14043 return EmitAtomicLoadArith(MI, BB);
14045 // This group does 64-bit operations on a 32-bit host.
14046 case X86::ATOMAND6432:
14047 case X86::ATOMOR6432:
14048 case X86::ATOMXOR6432:
14049 case X86::ATOMNAND6432:
14050 case X86::ATOMADD6432:
14051 case X86::ATOMSUB6432:
14052 case X86::ATOMMAX6432:
14053 case X86::ATOMMIN6432:
14054 case X86::ATOMUMAX6432:
14055 case X86::ATOMUMIN6432:
14056 case X86::ATOMSWAP6432:
14057 return EmitAtomicLoadArith6432(MI, BB);
14059 case X86::VASTART_SAVE_XMM_REGS:
14060 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
14062 case X86::VAARG_64:
14063 return EmitVAARG64WithCustomInserter(MI, BB);
14065 case X86::EH_SjLj_SetJmp32:
14066 case X86::EH_SjLj_SetJmp64:
14067 return emitEHSjLjSetJmp(MI, BB);
14069 case X86::EH_SjLj_LongJmp32:
14070 case X86::EH_SjLj_LongJmp64:
14071 return emitEHSjLjLongJmp(MI, BB);
14075 //===----------------------------------------------------------------------===//
14076 // X86 Optimization Hooks
14077 //===----------------------------------------------------------------------===//
14079 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
14082 const SelectionDAG &DAG,
14083 unsigned Depth) const {
14084 unsigned BitWidth = KnownZero.getBitWidth();
14085 unsigned Opc = Op.getOpcode();
14086 assert((Opc >= ISD::BUILTIN_OP_END ||
14087 Opc == ISD::INTRINSIC_WO_CHAIN ||
14088 Opc == ISD::INTRINSIC_W_CHAIN ||
14089 Opc == ISD::INTRINSIC_VOID) &&
14090 "Should use MaskedValueIsZero if you don't know whether Op"
14091 " is a target node!");
14093 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
14107 // These nodes' second result is a boolean.
14108 if (Op.getResNo() == 0)
14111 case X86ISD::SETCC:
14112 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
14114 case ISD::INTRINSIC_WO_CHAIN: {
14115 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14116 unsigned NumLoBits = 0;
14119 case Intrinsic::x86_sse_movmsk_ps:
14120 case Intrinsic::x86_avx_movmsk_ps_256:
14121 case Intrinsic::x86_sse2_movmsk_pd:
14122 case Intrinsic::x86_avx_movmsk_pd_256:
14123 case Intrinsic::x86_mmx_pmovmskb:
14124 case Intrinsic::x86_sse2_pmovmskb_128:
14125 case Intrinsic::x86_avx2_pmovmskb: {
14126 // High bits of movmskp{s|d}, pmovmskb are known zero.
14128 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14129 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
14130 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
14131 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
14132 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
14133 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
14134 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
14135 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
14137 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
14146 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
14147 unsigned Depth) const {
14148 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
14149 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14150 return Op.getValueType().getScalarType().getSizeInBits();
14156 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
14157 /// node is a GlobalAddress + offset.
14158 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
14159 const GlobalValue* &GA,
14160 int64_t &Offset) const {
14161 if (N->getOpcode() == X86ISD::Wrapper) {
14162 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
14163 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
14164 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
14168 return TargetLowering::isGAPlusOffset(N, GA, Offset);
14171 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
14172 /// same as extracting the high 128-bit part of 256-bit vector and then
14173 /// inserting the result into the low part of a new 256-bit vector
14174 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
14175 EVT VT = SVOp->getValueType(0);
14176 unsigned NumElems = VT.getVectorNumElements();
14178 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14179 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
14180 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14181 SVOp->getMaskElt(j) >= 0)
14187 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
14188 /// same as extracting the low 128-bit part of 256-bit vector and then
14189 /// inserting the result into the high part of a new 256-bit vector
14190 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
14191 EVT VT = SVOp->getValueType(0);
14192 unsigned NumElems = VT.getVectorNumElements();
14194 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14195 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
14196 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14197 SVOp->getMaskElt(j) >= 0)
14203 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
14204 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
14205 TargetLowering::DAGCombinerInfo &DCI,
14206 const X86Subtarget* Subtarget) {
14207 DebugLoc dl = N->getDebugLoc();
14208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
14209 SDValue V1 = SVOp->getOperand(0);
14210 SDValue V2 = SVOp->getOperand(1);
14211 EVT VT = SVOp->getValueType(0);
14212 unsigned NumElems = VT.getVectorNumElements();
14214 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
14215 V2.getOpcode() == ISD::CONCAT_VECTORS) {
14219 // V UNDEF BUILD_VECTOR UNDEF
14221 // CONCAT_VECTOR CONCAT_VECTOR
14224 // RESULT: V + zero extended
14226 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
14227 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
14228 V1.getOperand(1).getOpcode() != ISD::UNDEF)
14231 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
14234 // To match the shuffle mask, the first half of the mask should
14235 // be exactly the first vector, and all the rest a splat with the
14236 // first element of the second one.
14237 for (unsigned i = 0; i != NumElems/2; ++i)
14238 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
14239 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
14242 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
14243 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
14244 if (Ld->hasNUsesOfValue(1, 0)) {
14245 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
14246 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
14248 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
14250 Ld->getPointerInfo(),
14251 Ld->getAlignment(),
14252 false/*isVolatile*/, true/*ReadMem*/,
14253 false/*WriteMem*/);
14255 // Make sure the newly-created LOAD is in the same position as Ld in
14256 // terms of dependency. We create a TokenFactor for Ld and ResNode,
14257 // and update uses of Ld's output chain to use the TokenFactor.
14258 if (Ld->hasAnyUseOfValue(1)) {
14259 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
14260 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
14261 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
14262 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
14263 SDValue(ResNode.getNode(), 1));
14266 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
14270 // Emit a zeroed vector and insert the desired subvector on its
14272 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
14273 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
14274 return DCI.CombineTo(N, InsV);
14277 //===--------------------------------------------------------------------===//
14278 // Combine some shuffles into subvector extracts and inserts:
14281 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14282 if (isShuffleHigh128VectorInsertLow(SVOp)) {
14283 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
14284 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
14285 return DCI.CombineTo(N, InsV);
14288 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14289 if (isShuffleLow128VectorInsertHigh(SVOp)) {
14290 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
14291 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
14292 return DCI.CombineTo(N, InsV);
14298 /// PerformShuffleCombine - Performs several different shuffle combines.
14299 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
14300 TargetLowering::DAGCombinerInfo &DCI,
14301 const X86Subtarget *Subtarget) {
14302 DebugLoc dl = N->getDebugLoc();
14303 EVT VT = N->getValueType(0);
14305 // Don't create instructions with illegal types after legalize types has run.
14306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14307 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
14310 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
14311 if (Subtarget->hasFp256() && VT.is256BitVector() &&
14312 N->getOpcode() == ISD::VECTOR_SHUFFLE)
14313 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
14315 // Only handle 128 wide vector from here on.
14316 if (!VT.is128BitVector())
14319 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
14320 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
14321 // consecutive, non-overlapping, and in the right order.
14322 SmallVector<SDValue, 16> Elts;
14323 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
14324 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
14326 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
14330 /// PerformTruncateCombine - Converts truncate operation to
14331 /// a sequence of vector shuffle operations.
14332 /// It is possible when we truncate 256-bit vector to 128-bit vector
14333 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
14334 TargetLowering::DAGCombinerInfo &DCI,
14335 const X86Subtarget *Subtarget) {
14336 if (!DCI.isBeforeLegalizeOps())
14339 if (!Subtarget->hasFp256())
14342 EVT VT = N->getValueType(0);
14343 SDValue Op = N->getOperand(0);
14344 EVT OpVT = Op.getValueType();
14345 DebugLoc dl = N->getDebugLoc();
14347 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
14349 if (Subtarget->hasInt256()) {
14350 // AVX2: v4i64 -> v4i32
14353 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14355 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
14356 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
14359 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
14360 DAG.getIntPtrConstant(0));
14363 // AVX: v4i64 -> v4i32
14364 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
14365 DAG.getIntPtrConstant(0));
14367 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
14368 DAG.getIntPtrConstant(2));
14370 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
14371 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
14374 static const int ShufMask1[] = {0, 2, 0, 0};
14376 SDValue Undef = DAG.getUNDEF(VT);
14377 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, Undef, ShufMask1);
14378 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, Undef, ShufMask1);
14381 static const int ShufMask2[] = {0, 1, 4, 5};
14383 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
14386 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
14388 if (Subtarget->hasInt256()) {
14389 // AVX2: v8i32 -> v8i16
14391 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
14394 SmallVector<SDValue,32> pshufbMask;
14395 for (unsigned i = 0; i < 2; ++i) {
14396 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14397 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14398 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14399 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14400 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14401 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14402 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14403 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14404 for (unsigned j = 0; j < 8; ++j)
14405 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14407 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
14408 &pshufbMask[0], 32);
14409 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
14411 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
14413 static const int ShufMask[] = {0, 2, -1, -1};
14414 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
14417 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
14418 DAG.getIntPtrConstant(0));
14420 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
14423 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
14424 DAG.getIntPtrConstant(0));
14426 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
14427 DAG.getIntPtrConstant(4));
14429 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
14430 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
14433 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14434 -1, -1, -1, -1, -1, -1, -1, -1};
14436 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14437 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, Undef, ShufMask1);
14438 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, Undef, ShufMask1);
14440 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
14441 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
14444 static const int ShufMask2[] = {0, 1, 4, 5};
14446 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
14447 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
14453 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
14454 /// specific shuffle of a load can be folded into a single element load.
14455 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
14456 /// shuffles have been customed lowered so we need to handle those here.
14457 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
14458 TargetLowering::DAGCombinerInfo &DCI) {
14459 if (DCI.isBeforeLegalizeOps())
14462 SDValue InVec = N->getOperand(0);
14463 SDValue EltNo = N->getOperand(1);
14465 if (!isa<ConstantSDNode>(EltNo))
14468 EVT VT = InVec.getValueType();
14470 bool HasShuffleIntoBitcast = false;
14471 if (InVec.getOpcode() == ISD::BITCAST) {
14472 // Don't duplicate a load with other uses.
14473 if (!InVec.hasOneUse())
14475 EVT BCVT = InVec.getOperand(0).getValueType();
14476 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
14478 InVec = InVec.getOperand(0);
14479 HasShuffleIntoBitcast = true;
14482 if (!isTargetShuffle(InVec.getOpcode()))
14485 // Don't duplicate a load with other uses.
14486 if (!InVec.hasOneUse())
14489 SmallVector<int, 16> ShuffleMask;
14491 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
14495 // Select the input vector, guarding against out of range extract vector.
14496 unsigned NumElems = VT.getVectorNumElements();
14497 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
14498 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
14499 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
14500 : InVec.getOperand(1);
14502 // If inputs to shuffle are the same for both ops, then allow 2 uses
14503 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
14505 if (LdNode.getOpcode() == ISD::BITCAST) {
14506 // Don't duplicate a load with other uses.
14507 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
14510 AllowedUses = 1; // only allow 1 load use if we have a bitcast
14511 LdNode = LdNode.getOperand(0);
14514 if (!ISD::isNormalLoad(LdNode.getNode()))
14517 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
14519 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
14522 if (HasShuffleIntoBitcast) {
14523 // If there's a bitcast before the shuffle, check if the load type and
14524 // alignment is valid.
14525 unsigned Align = LN0->getAlignment();
14526 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14527 unsigned NewAlign = TLI.getDataLayout()->
14528 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
14530 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
14534 // All checks match so transform back to vector_shuffle so that DAG combiner
14535 // can finish the job
14536 DebugLoc dl = N->getDebugLoc();
14538 // Create shuffle node taking into account the case that its a unary shuffle
14539 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
14540 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
14541 InVec.getOperand(0), Shuffle,
14543 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
14544 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
14548 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
14549 /// generation and convert it from being a bunch of shuffles and extracts
14550 /// to a simple store and scalar loads to extract the elements.
14551 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
14552 TargetLowering::DAGCombinerInfo &DCI) {
14553 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
14554 if (NewOp.getNode())
14557 SDValue InputVector = N->getOperand(0);
14558 // Detect whether we are trying to convert from mmx to i32 and the bitcast
14559 // from mmx to v2i32 has a single usage.
14560 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
14561 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
14562 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
14563 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(),
14564 N->getValueType(0),
14565 InputVector.getNode()->getOperand(0));
14567 // Only operate on vectors of 4 elements, where the alternative shuffling
14568 // gets to be more expensive.
14569 if (InputVector.getValueType() != MVT::v4i32)
14572 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
14573 // single use which is a sign-extend or zero-extend, and all elements are
14575 SmallVector<SDNode *, 4> Uses;
14576 unsigned ExtractedElements = 0;
14577 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
14578 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
14579 if (UI.getUse().getResNo() != InputVector.getResNo())
14582 SDNode *Extract = *UI;
14583 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14586 if (Extract->getValueType(0) != MVT::i32)
14588 if (!Extract->hasOneUse())
14590 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
14591 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
14593 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
14596 // Record which element was extracted.
14597 ExtractedElements |=
14598 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
14600 Uses.push_back(Extract);
14603 // If not all the elements were used, this may not be worthwhile.
14604 if (ExtractedElements != 15)
14607 // Ok, we've now decided to do the transformation.
14608 DebugLoc dl = InputVector.getDebugLoc();
14610 // Store the value to a temporary stack slot.
14611 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
14612 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
14613 MachinePointerInfo(), false, false, 0);
14615 // Replace each use (extract) with a load of the appropriate element.
14616 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
14617 UE = Uses.end(); UI != UE; ++UI) {
14618 SDNode *Extract = *UI;
14620 // cOMpute the element's address.
14621 SDValue Idx = Extract->getOperand(1);
14623 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
14624 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
14625 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14626 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
14628 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
14629 StackPtr, OffsetVal);
14631 // Load the scalar.
14632 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
14633 ScalarAddr, MachinePointerInfo(),
14634 false, false, false, 0);
14636 // Replace the exact with the load.
14637 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
14640 // The replacement was made in place; don't return anything.
14644 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
14646 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
14647 TargetLowering::DAGCombinerInfo &DCI,
14648 const X86Subtarget *Subtarget) {
14649 DebugLoc DL = N->getDebugLoc();
14650 SDValue Cond = N->getOperand(0);
14651 // Get the LHS/RHS of the select.
14652 SDValue LHS = N->getOperand(1);
14653 SDValue RHS = N->getOperand(2);
14654 EVT VT = LHS.getValueType();
14656 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
14657 // instructions match the semantics of the common C idiom x<y?x:y but not
14658 // x<=y?x:y, because of how they handle negative zero (which can be
14659 // ignored in unsafe-math mode).
14660 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
14661 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
14662 (Subtarget->hasSSE2() ||
14663 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
14664 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14666 unsigned Opcode = 0;
14667 // Check for x CC y ? x : y.
14668 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
14669 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
14673 // Converting this to a min would handle NaNs incorrectly, and swapping
14674 // the operands would cause it to handle comparisons between positive
14675 // and negative zero incorrectly.
14676 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
14677 if (!DAG.getTarget().Options.UnsafeFPMath &&
14678 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
14680 std::swap(LHS, RHS);
14682 Opcode = X86ISD::FMIN;
14685 // Converting this to a min would handle comparisons between positive
14686 // and negative zero incorrectly.
14687 if (!DAG.getTarget().Options.UnsafeFPMath &&
14688 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
14690 Opcode = X86ISD::FMIN;
14693 // Converting this to a min would handle both negative zeros and NaNs
14694 // incorrectly, but we can swap the operands to fix both.
14695 std::swap(LHS, RHS);
14699 Opcode = X86ISD::FMIN;
14703 // Converting this to a max would handle comparisons between positive
14704 // and negative zero incorrectly.
14705 if (!DAG.getTarget().Options.UnsafeFPMath &&
14706 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
14708 Opcode = X86ISD::FMAX;
14711 // Converting this to a max would handle NaNs incorrectly, and swapping
14712 // the operands would cause it to handle comparisons between positive
14713 // and negative zero incorrectly.
14714 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
14715 if (!DAG.getTarget().Options.UnsafeFPMath &&
14716 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
14718 std::swap(LHS, RHS);
14720 Opcode = X86ISD::FMAX;
14723 // Converting this to a max would handle both negative zeros and NaNs
14724 // incorrectly, but we can swap the operands to fix both.
14725 std::swap(LHS, RHS);
14729 Opcode = X86ISD::FMAX;
14732 // Check for x CC y ? y : x -- a min/max with reversed arms.
14733 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
14734 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
14738 // Converting this to a min would handle comparisons between positive
14739 // and negative zero incorrectly, and swapping the operands would
14740 // cause it to handle NaNs incorrectly.
14741 if (!DAG.getTarget().Options.UnsafeFPMath &&
14742 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
14743 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
14745 std::swap(LHS, RHS);
14747 Opcode = X86ISD::FMIN;
14750 // Converting this to a min would handle NaNs incorrectly.
14751 if (!DAG.getTarget().Options.UnsafeFPMath &&
14752 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
14754 Opcode = X86ISD::FMIN;
14757 // Converting this to a min would handle both negative zeros and NaNs
14758 // incorrectly, but we can swap the operands to fix both.
14759 std::swap(LHS, RHS);
14763 Opcode = X86ISD::FMIN;
14767 // Converting this to a max would handle NaNs incorrectly.
14768 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
14770 Opcode = X86ISD::FMAX;
14773 // Converting this to a max would handle comparisons between positive
14774 // and negative zero incorrectly, and swapping the operands would
14775 // cause it to handle NaNs incorrectly.
14776 if (!DAG.getTarget().Options.UnsafeFPMath &&
14777 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
14778 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
14780 std::swap(LHS, RHS);
14782 Opcode = X86ISD::FMAX;
14785 // Converting this to a max would handle both negative zeros and NaNs
14786 // incorrectly, but we can swap the operands to fix both.
14787 std::swap(LHS, RHS);
14791 Opcode = X86ISD::FMAX;
14797 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
14800 // If this is a select between two integer constants, try to do some
14802 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
14803 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
14804 // Don't do this for crazy integer types.
14805 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
14806 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
14807 // so that TrueC (the true value) is larger than FalseC.
14808 bool NeedsCondInvert = false;
14810 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
14811 // Efficiently invertible.
14812 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
14813 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
14814 isa<ConstantSDNode>(Cond.getOperand(1))))) {
14815 NeedsCondInvert = true;
14816 std::swap(TrueC, FalseC);
14819 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
14820 if (FalseC->getAPIntValue() == 0 &&
14821 TrueC->getAPIntValue().isPowerOf2()) {
14822 if (NeedsCondInvert) // Invert the condition if needed.
14823 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
14824 DAG.getConstant(1, Cond.getValueType()));
14826 // Zero extend the condition if needed.
14827 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
14829 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
14830 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
14831 DAG.getConstant(ShAmt, MVT::i8));
14834 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
14835 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
14836 if (NeedsCondInvert) // Invert the condition if needed.
14837 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
14838 DAG.getConstant(1, Cond.getValueType()));
14840 // Zero extend the condition if needed.
14841 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
14842 FalseC->getValueType(0), Cond);
14843 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14844 SDValue(FalseC, 0));
14847 // Optimize cases that will turn into an LEA instruction. This requires
14848 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
14849 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
14850 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
14851 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
14853 bool isFastMultiplier = false;
14855 switch ((unsigned char)Diff) {
14857 case 1: // result = add base, cond
14858 case 2: // result = lea base( , cond*2)
14859 case 3: // result = lea base(cond, cond*2)
14860 case 4: // result = lea base( , cond*4)
14861 case 5: // result = lea base(cond, cond*4)
14862 case 8: // result = lea base( , cond*8)
14863 case 9: // result = lea base(cond, cond*8)
14864 isFastMultiplier = true;
14869 if (isFastMultiplier) {
14870 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
14871 if (NeedsCondInvert) // Invert the condition if needed.
14872 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
14873 DAG.getConstant(1, Cond.getValueType()));
14875 // Zero extend the condition if needed.
14876 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
14878 // Scale the condition by the difference.
14880 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
14881 DAG.getConstant(Diff, Cond.getValueType()));
14883 // Add the base if non-zero.
14884 if (FalseC->getAPIntValue() != 0)
14885 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14886 SDValue(FalseC, 0));
14893 // Canonicalize max and min:
14894 // (x > y) ? x : y -> (x >= y) ? x : y
14895 // (x < y) ? x : y -> (x <= y) ? x : y
14896 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
14897 // the need for an extra compare
14898 // against zero. e.g.
14899 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
14901 // testl %edi, %edi
14903 // cmovgl %edi, %eax
14907 // cmovsl %eax, %edi
14908 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
14909 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
14910 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
14911 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14916 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
14917 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
14918 Cond.getOperand(0), Cond.getOperand(1), NewCC);
14919 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
14924 // Match VSELECTs into subs with unsigned saturation.
14925 if (!DCI.isBeforeLegalize() &&
14926 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
14927 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
14928 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
14929 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
14930 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14932 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
14933 // left side invert the predicate to simplify logic below.
14935 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
14937 CC = ISD::getSetCCInverse(CC, true);
14938 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
14942 if (Other.getNode() && Other->getNumOperands() == 2 &&
14943 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
14944 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
14945 SDValue CondRHS = Cond->getOperand(1);
14947 // Look for a general sub with unsigned saturation first.
14948 // x >= y ? x-y : 0 --> subus x, y
14949 // x > y ? x-y : 0 --> subus x, y
14950 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
14951 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
14952 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
14954 // If the RHS is a constant we have to reverse the const canonicalization.
14955 // x > C-1 ? x+-C : 0 --> subus x, C
14956 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
14957 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
14958 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
14959 if (CondRHS.getConstantOperandVal(0) == -A-1) {
14960 SmallVector<SDValue, 32> V(VT.getVectorNumElements(),
14961 DAG.getConstant(-A, VT.getScalarType()));
14962 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
14963 DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
14964 V.data(), V.size()));
14968 // Another special case: If C was a sign bit, the sub has been
14969 // canonicalized into a xor.
14970 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
14971 // it's safe to decanonicalize the xor?
14972 // x s< 0 ? x^C : 0 --> subus x, C
14973 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
14974 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
14975 isSplatVector(OpRHS.getNode())) {
14976 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
14978 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
14983 // If we know that this node is legal then we know that it is going to be
14984 // matched by one of the SSE/AVX BLEND instructions. These instructions only
14985 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
14986 // to simplify previous instructions.
14987 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14988 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
14989 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
14990 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
14992 // Don't optimize vector selects that map to mask-registers.
14996 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
14997 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
14999 APInt KnownZero, KnownOne;
15000 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
15001 DCI.isBeforeLegalizeOps());
15002 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
15003 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
15004 DCI.CommitTargetLoweringOpt(TLO);
15010 // Check whether a boolean test is testing a boolean value generated by
15011 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
15014 // Simplify the following patterns:
15015 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
15016 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
15017 // to (Op EFLAGS Cond)
15019 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
15020 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
15021 // to (Op EFLAGS !Cond)
15023 // where Op could be BRCOND or CMOV.
15025 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
15026 // Quit if not CMP and SUB with its value result used.
15027 if (Cmp.getOpcode() != X86ISD::CMP &&
15028 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
15031 // Quit if not used as a boolean value.
15032 if (CC != X86::COND_E && CC != X86::COND_NE)
15035 // Check CMP operands. One of them should be 0 or 1 and the other should be
15036 // an SetCC or extended from it.
15037 SDValue Op1 = Cmp.getOperand(0);
15038 SDValue Op2 = Cmp.getOperand(1);
15041 const ConstantSDNode* C = 0;
15042 bool needOppositeCond = (CC == X86::COND_E);
15044 if ((C = dyn_cast<ConstantSDNode>(Op1)))
15046 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
15048 else // Quit if all operands are not constants.
15051 if (C->getZExtValue() == 1)
15052 needOppositeCond = !needOppositeCond;
15053 else if (C->getZExtValue() != 0)
15054 // Quit if the constant is neither 0 or 1.
15057 // Skip 'zext' node.
15058 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
15059 SetCC = SetCC.getOperand(0);
15061 switch (SetCC.getOpcode()) {
15062 case X86ISD::SETCC:
15063 // Set the condition code or opposite one if necessary.
15064 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
15065 if (needOppositeCond)
15066 CC = X86::GetOppositeBranchCondition(CC);
15067 return SetCC.getOperand(1);
15068 case X86ISD::CMOV: {
15069 // Check whether false/true value has canonical one, i.e. 0 or 1.
15070 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
15071 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
15072 // Quit if true value is not a constant.
15075 // Quit if false value is not a constant.
15077 // A special case for rdrand, where 0 is set if false cond is found.
15078 SDValue Op = SetCC.getOperand(0);
15079 if (Op.getOpcode() != X86ISD::RDRAND)
15082 // Quit if false value is not the constant 0 or 1.
15083 bool FValIsFalse = true;
15084 if (FVal && FVal->getZExtValue() != 0) {
15085 if (FVal->getZExtValue() != 1)
15087 // If FVal is 1, opposite cond is needed.
15088 needOppositeCond = !needOppositeCond;
15089 FValIsFalse = false;
15091 // Quit if TVal is not the constant opposite of FVal.
15092 if (FValIsFalse && TVal->getZExtValue() != 1)
15094 if (!FValIsFalse && TVal->getZExtValue() != 0)
15096 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
15097 if (needOppositeCond)
15098 CC = X86::GetOppositeBranchCondition(CC);
15099 return SetCC.getOperand(3);
15106 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
15107 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
15108 TargetLowering::DAGCombinerInfo &DCI,
15109 const X86Subtarget *Subtarget) {
15110 DebugLoc DL = N->getDebugLoc();
15112 // If the flag operand isn't dead, don't touch this CMOV.
15113 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
15116 SDValue FalseOp = N->getOperand(0);
15117 SDValue TrueOp = N->getOperand(1);
15118 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
15119 SDValue Cond = N->getOperand(3);
15121 if (CC == X86::COND_E || CC == X86::COND_NE) {
15122 switch (Cond.getOpcode()) {
15126 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
15127 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
15128 return (CC == X86::COND_E) ? FalseOp : TrueOp;
15134 Flags = checkBoolTestSetCCCombine(Cond, CC);
15135 if (Flags.getNode() &&
15136 // Extra check as FCMOV only supports a subset of X86 cond.
15137 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
15138 SDValue Ops[] = { FalseOp, TrueOp,
15139 DAG.getConstant(CC, MVT::i8), Flags };
15140 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
15141 Ops, array_lengthof(Ops));
15144 // If this is a select between two integer constants, try to do some
15145 // optimizations. Note that the operands are ordered the opposite of SELECT
15147 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
15148 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
15149 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
15150 // larger than FalseC (the false value).
15151 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
15152 CC = X86::GetOppositeBranchCondition(CC);
15153 std::swap(TrueC, FalseC);
15154 std::swap(TrueOp, FalseOp);
15157 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
15158 // This is efficient for any integer data type (including i8/i16) and
15160 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
15161 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15162 DAG.getConstant(CC, MVT::i8), Cond);
15164 // Zero extend the condition if needed.
15165 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
15167 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15168 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
15169 DAG.getConstant(ShAmt, MVT::i8));
15170 if (N->getNumValues() == 2) // Dead flag value?
15171 return DCI.CombineTo(N, Cond, SDValue());
15175 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
15176 // for any integer data type, including i8/i16.
15177 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15178 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15179 DAG.getConstant(CC, MVT::i8), Cond);
15181 // Zero extend the condition if needed.
15182 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15183 FalseC->getValueType(0), Cond);
15184 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15185 SDValue(FalseC, 0));
15187 if (N->getNumValues() == 2) // Dead flag value?
15188 return DCI.CombineTo(N, Cond, SDValue());
15192 // Optimize cases that will turn into an LEA instruction. This requires
15193 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15194 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15195 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15196 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15198 bool isFastMultiplier = false;
15200 switch ((unsigned char)Diff) {
15202 case 1: // result = add base, cond
15203 case 2: // result = lea base( , cond*2)
15204 case 3: // result = lea base(cond, cond*2)
15205 case 4: // result = lea base( , cond*4)
15206 case 5: // result = lea base(cond, cond*4)
15207 case 8: // result = lea base( , cond*8)
15208 case 9: // result = lea base(cond, cond*8)
15209 isFastMultiplier = true;
15214 if (isFastMultiplier) {
15215 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15216 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15217 DAG.getConstant(CC, MVT::i8), Cond);
15218 // Zero extend the condition if needed.
15219 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15221 // Scale the condition by the difference.
15223 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15224 DAG.getConstant(Diff, Cond.getValueType()));
15226 // Add the base if non-zero.
15227 if (FalseC->getAPIntValue() != 0)
15228 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15229 SDValue(FalseC, 0));
15230 if (N->getNumValues() == 2) // Dead flag value?
15231 return DCI.CombineTo(N, Cond, SDValue());
15238 // Handle these cases:
15239 // (select (x != c), e, c) -> select (x != c), e, x),
15240 // (select (x == c), c, e) -> select (x == c), x, e)
15241 // where the c is an integer constant, and the "select" is the combination
15242 // of CMOV and CMP.
15244 // The rationale for this change is that the conditional-move from a constant
15245 // needs two instructions, however, conditional-move from a register needs
15246 // only one instruction.
15248 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
15249 // some instruction-combining opportunities. This opt needs to be
15250 // postponed as late as possible.
15252 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
15253 // the DCI.xxxx conditions are provided to postpone the optimization as
15254 // late as possible.
15256 ConstantSDNode *CmpAgainst = 0;
15257 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
15258 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
15259 dyn_cast<ConstantSDNode>(Cond.getOperand(0)) == 0) {
15261 if (CC == X86::COND_NE &&
15262 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
15263 CC = X86::GetOppositeBranchCondition(CC);
15264 std::swap(TrueOp, FalseOp);
15267 if (CC == X86::COND_E &&
15268 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
15269 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
15270 DAG.getConstant(CC, MVT::i8), Cond };
15271 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
15272 array_lengthof(Ops));
15281 /// PerformMulCombine - Optimize a single multiply with constant into two
15282 /// in order to implement it with two cheaper instructions, e.g.
15283 /// LEA + SHL, LEA + LEA.
15284 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
15285 TargetLowering::DAGCombinerInfo &DCI) {
15286 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15289 EVT VT = N->getValueType(0);
15290 if (VT != MVT::i64)
15293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
15296 uint64_t MulAmt = C->getZExtValue();
15297 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
15300 uint64_t MulAmt1 = 0;
15301 uint64_t MulAmt2 = 0;
15302 if ((MulAmt % 9) == 0) {
15304 MulAmt2 = MulAmt / 9;
15305 } else if ((MulAmt % 5) == 0) {
15307 MulAmt2 = MulAmt / 5;
15308 } else if ((MulAmt % 3) == 0) {
15310 MulAmt2 = MulAmt / 3;
15313 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
15314 DebugLoc DL = N->getDebugLoc();
15316 if (isPowerOf2_64(MulAmt2) &&
15317 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
15318 // If second multiplifer is pow2, issue it first. We want the multiply by
15319 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
15321 std::swap(MulAmt1, MulAmt2);
15324 if (isPowerOf2_64(MulAmt1))
15325 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15326 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
15328 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
15329 DAG.getConstant(MulAmt1, VT));
15331 if (isPowerOf2_64(MulAmt2))
15332 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
15333 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
15335 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
15336 DAG.getConstant(MulAmt2, VT));
15338 // Do not add new nodes to DAG combiner worklist.
15339 DCI.CombineTo(N, NewMul, false);
15344 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
15345 SDValue N0 = N->getOperand(0);
15346 SDValue N1 = N->getOperand(1);
15347 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
15348 EVT VT = N0.getValueType();
15350 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
15351 // since the result of setcc_c is all zero's or all ones.
15352 if (VT.isInteger() && !VT.isVector() &&
15353 N1C && N0.getOpcode() == ISD::AND &&
15354 N0.getOperand(1).getOpcode() == ISD::Constant) {
15355 SDValue N00 = N0.getOperand(0);
15356 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
15357 ((N00.getOpcode() == ISD::ANY_EXTEND ||
15358 N00.getOpcode() == ISD::ZERO_EXTEND) &&
15359 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
15360 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
15361 APInt ShAmt = N1C->getAPIntValue();
15362 Mask = Mask.shl(ShAmt);
15364 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
15365 N00, DAG.getConstant(Mask, VT));
15370 // Hardware support for vector shifts is sparse which makes us scalarize the
15371 // vector operations in many cases. Also, on sandybridge ADD is faster than
15373 // (shl V, 1) -> add V,V
15374 if (isSplatVector(N1.getNode())) {
15375 assert(N0.getValueType().isVector() && "Invalid vector shift type");
15376 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
15377 // We shift all of the values by one. In many cases we do not have
15378 // hardware support for this operation. This is better expressed as an ADD
15380 if (N1C && (1 == N1C->getZExtValue())) {
15381 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
15388 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
15390 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
15391 TargetLowering::DAGCombinerInfo &DCI,
15392 const X86Subtarget *Subtarget) {
15393 EVT VT = N->getValueType(0);
15394 if (N->getOpcode() == ISD::SHL) {
15395 SDValue V = PerformSHLCombine(N, DAG);
15396 if (V.getNode()) return V;
15399 // On X86 with SSE2 support, we can transform this to a vector shift if
15400 // all elements are shifted by the same amount. We can't do this in legalize
15401 // because the a constant vector is typically transformed to a constant pool
15402 // so we have no knowledge of the shift amount.
15403 if (!Subtarget->hasSSE2())
15406 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
15407 (!Subtarget->hasInt256() ||
15408 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
15411 SDValue ShAmtOp = N->getOperand(1);
15412 EVT EltVT = VT.getVectorElementType();
15413 DebugLoc DL = N->getDebugLoc();
15414 SDValue BaseShAmt = SDValue();
15415 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
15416 unsigned NumElts = VT.getVectorNumElements();
15418 for (; i != NumElts; ++i) {
15419 SDValue Arg = ShAmtOp.getOperand(i);
15420 if (Arg.getOpcode() == ISD::UNDEF) continue;
15424 // Handle the case where the build_vector is all undef
15425 // FIXME: Should DAG allow this?
15429 for (; i != NumElts; ++i) {
15430 SDValue Arg = ShAmtOp.getOperand(i);
15431 if (Arg.getOpcode() == ISD::UNDEF) continue;
15432 if (Arg != BaseShAmt) {
15436 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
15437 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
15438 SDValue InVec = ShAmtOp.getOperand(0);
15439 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15440 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15442 for (; i != NumElts; ++i) {
15443 SDValue Arg = InVec.getOperand(i);
15444 if (Arg.getOpcode() == ISD::UNDEF) continue;
15448 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15449 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15450 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
15451 if (C->getZExtValue() == SplatIdx)
15452 BaseShAmt = InVec.getOperand(1);
15455 if (BaseShAmt.getNode() == 0) {
15456 // Don't create instructions with illegal types after legalize
15458 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
15459 !DCI.isBeforeLegalize())
15462 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
15463 DAG.getIntPtrConstant(0));
15468 // The shift amount is an i32.
15469 if (EltVT.bitsGT(MVT::i32))
15470 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
15471 else if (EltVT.bitsLT(MVT::i32))
15472 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
15474 // The shift amount is identical so we can do a vector shift.
15475 SDValue ValOp = N->getOperand(0);
15476 switch (N->getOpcode()) {
15478 llvm_unreachable("Unknown shift opcode!");
15480 switch (VT.getSimpleVT().SimpleTy) {
15481 default: return SDValue();
15488 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
15491 switch (VT.getSimpleVT().SimpleTy) {
15492 default: return SDValue();
15497 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
15500 switch (VT.getSimpleVT().SimpleTy) {
15501 default: return SDValue();
15508 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
15514 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
15515 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
15516 // and friends. Likewise for OR -> CMPNEQSS.
15517 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
15518 TargetLowering::DAGCombinerInfo &DCI,
15519 const X86Subtarget *Subtarget) {
15522 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
15523 // we're requiring SSE2 for both.
15524 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
15525 SDValue N0 = N->getOperand(0);
15526 SDValue N1 = N->getOperand(1);
15527 SDValue CMP0 = N0->getOperand(1);
15528 SDValue CMP1 = N1->getOperand(1);
15529 DebugLoc DL = N->getDebugLoc();
15531 // The SETCCs should both refer to the same CMP.
15532 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
15535 SDValue CMP00 = CMP0->getOperand(0);
15536 SDValue CMP01 = CMP0->getOperand(1);
15537 EVT VT = CMP00.getValueType();
15539 if (VT == MVT::f32 || VT == MVT::f64) {
15540 bool ExpectingFlags = false;
15541 // Check for any users that want flags:
15542 for (SDNode::use_iterator UI = N->use_begin(),
15544 !ExpectingFlags && UI != UE; ++UI)
15545 switch (UI->getOpcode()) {
15550 ExpectingFlags = true;
15552 case ISD::CopyToReg:
15553 case ISD::SIGN_EXTEND:
15554 case ISD::ZERO_EXTEND:
15555 case ISD::ANY_EXTEND:
15559 if (!ExpectingFlags) {
15560 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
15561 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
15563 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
15564 X86::CondCode tmp = cc0;
15569 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
15570 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
15571 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
15572 X86ISD::NodeType NTOperator = is64BitFP ?
15573 X86ISD::FSETCCsd : X86ISD::FSETCCss;
15574 // FIXME: need symbolic constants for these magic numbers.
15575 // See X86ATTInstPrinter.cpp:printSSECC().
15576 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
15577 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
15578 DAG.getConstant(x86cc, MVT::i8));
15579 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
15581 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
15582 DAG.getConstant(1, MVT::i32));
15583 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
15584 return OneBitOfTruth;
15592 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
15593 /// so it can be folded inside ANDNP.
15594 static bool CanFoldXORWithAllOnes(const SDNode *N) {
15595 EVT VT = N->getValueType(0);
15597 // Match direct AllOnes for 128 and 256-bit vectors
15598 if (ISD::isBuildVectorAllOnes(N))
15601 // Look through a bit convert.
15602 if (N->getOpcode() == ISD::BITCAST)
15603 N = N->getOperand(0).getNode();
15605 // Sometimes the operand may come from a insert_subvector building a 256-bit
15607 if (VT.is256BitVector() &&
15608 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
15609 SDValue V1 = N->getOperand(0);
15610 SDValue V2 = N->getOperand(1);
15612 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
15613 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
15614 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
15615 ISD::isBuildVectorAllOnes(V2.getNode()))
15622 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
15623 TargetLowering::DAGCombinerInfo &DCI,
15624 const X86Subtarget *Subtarget) {
15625 if (DCI.isBeforeLegalizeOps())
15628 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
15632 EVT VT = N->getValueType(0);
15634 // Create BLSI, and BLSR instructions
15635 // BLSI is X & (-X)
15636 // BLSR is X & (X-1)
15637 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
15638 SDValue N0 = N->getOperand(0);
15639 SDValue N1 = N->getOperand(1);
15640 DebugLoc DL = N->getDebugLoc();
15642 // Check LHS for neg
15643 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
15644 isZero(N0.getOperand(0)))
15645 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
15647 // Check RHS for neg
15648 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
15649 isZero(N1.getOperand(0)))
15650 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
15652 // Check LHS for X-1
15653 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
15654 isAllOnes(N0.getOperand(1)))
15655 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
15657 // Check RHS for X-1
15658 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
15659 isAllOnes(N1.getOperand(1)))
15660 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
15665 // Want to form ANDNP nodes:
15666 // 1) In the hopes of then easily combining them with OR and AND nodes
15667 // to form PBLEND/PSIGN.
15668 // 2) To match ANDN packed intrinsics
15669 if (VT != MVT::v2i64 && VT != MVT::v4i64)
15672 SDValue N0 = N->getOperand(0);
15673 SDValue N1 = N->getOperand(1);
15674 DebugLoc DL = N->getDebugLoc();
15676 // Check LHS for vnot
15677 if (N0.getOpcode() == ISD::XOR &&
15678 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
15679 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
15680 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
15682 // Check RHS for vnot
15683 if (N1.getOpcode() == ISD::XOR &&
15684 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
15685 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
15686 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
15691 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
15692 TargetLowering::DAGCombinerInfo &DCI,
15693 const X86Subtarget *Subtarget) {
15694 if (DCI.isBeforeLegalizeOps())
15697 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
15701 EVT VT = N->getValueType(0);
15703 SDValue N0 = N->getOperand(0);
15704 SDValue N1 = N->getOperand(1);
15706 // look for psign/blend
15707 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
15708 if (!Subtarget->hasSSSE3() ||
15709 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
15712 // Canonicalize pandn to RHS
15713 if (N0.getOpcode() == X86ISD::ANDNP)
15715 // or (and (m, y), (pandn m, x))
15716 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
15717 SDValue Mask = N1.getOperand(0);
15718 SDValue X = N1.getOperand(1);
15720 if (N0.getOperand(0) == Mask)
15721 Y = N0.getOperand(1);
15722 if (N0.getOperand(1) == Mask)
15723 Y = N0.getOperand(0);
15725 // Check to see if the mask appeared in both the AND and ANDNP and
15729 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
15730 // Look through mask bitcast.
15731 if (Mask.getOpcode() == ISD::BITCAST)
15732 Mask = Mask.getOperand(0);
15733 if (X.getOpcode() == ISD::BITCAST)
15734 X = X.getOperand(0);
15735 if (Y.getOpcode() == ISD::BITCAST)
15736 Y = Y.getOperand(0);
15738 EVT MaskVT = Mask.getValueType();
15740 // Validate that the Mask operand is a vector sra node.
15741 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
15742 // there is no psrai.b
15743 if (Mask.getOpcode() != X86ISD::VSRAI)
15746 // Check that the SRA is all signbits.
15747 SDValue SraC = Mask.getOperand(1);
15748 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
15749 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
15750 if ((SraAmt + 1) != EltBits)
15753 DebugLoc DL = N->getDebugLoc();
15755 // We are going to replace the AND, OR, NAND with either BLEND
15756 // or PSIGN, which only look at the MSB. The VSRAI instruction
15757 // does not affect the highest bit, so we can get rid of it.
15758 Mask = Mask.getOperand(0);
15760 // Now we know we at least have a plendvb with the mask val. See if
15761 // we can form a psignb/w/d.
15762 // psign = x.type == y.type == mask.type && y = sub(0, x);
15763 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
15764 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
15765 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
15766 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
15767 "Unsupported VT for PSIGN");
15768 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask);
15769 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
15771 // PBLENDVB only available on SSE 4.1
15772 if (!Subtarget->hasSSE41())
15775 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
15777 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
15778 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
15779 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
15780 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
15781 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
15785 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
15788 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
15789 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
15791 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
15793 if (!N0.hasOneUse() || !N1.hasOneUse())
15796 SDValue ShAmt0 = N0.getOperand(1);
15797 if (ShAmt0.getValueType() != MVT::i8)
15799 SDValue ShAmt1 = N1.getOperand(1);
15800 if (ShAmt1.getValueType() != MVT::i8)
15802 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
15803 ShAmt0 = ShAmt0.getOperand(0);
15804 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
15805 ShAmt1 = ShAmt1.getOperand(0);
15807 DebugLoc DL = N->getDebugLoc();
15808 unsigned Opc = X86ISD::SHLD;
15809 SDValue Op0 = N0.getOperand(0);
15810 SDValue Op1 = N1.getOperand(0);
15811 if (ShAmt0.getOpcode() == ISD::SUB) {
15812 Opc = X86ISD::SHRD;
15813 std::swap(Op0, Op1);
15814 std::swap(ShAmt0, ShAmt1);
15817 unsigned Bits = VT.getSizeInBits();
15818 if (ShAmt1.getOpcode() == ISD::SUB) {
15819 SDValue Sum = ShAmt1.getOperand(0);
15820 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
15821 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
15822 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
15823 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
15824 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
15825 return DAG.getNode(Opc, DL, VT,
15827 DAG.getNode(ISD::TRUNCATE, DL,
15830 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
15831 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
15833 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
15834 return DAG.getNode(Opc, DL, VT,
15835 N0.getOperand(0), N1.getOperand(0),
15836 DAG.getNode(ISD::TRUNCATE, DL,
15843 // Generate NEG and CMOV for integer abs.
15844 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
15845 EVT VT = N->getValueType(0);
15847 // Since X86 does not have CMOV for 8-bit integer, we don't convert
15848 // 8-bit integer abs to NEG and CMOV.
15849 if (VT.isInteger() && VT.getSizeInBits() == 8)
15852 SDValue N0 = N->getOperand(0);
15853 SDValue N1 = N->getOperand(1);
15854 DebugLoc DL = N->getDebugLoc();
15856 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
15857 // and change it to SUB and CMOV.
15858 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
15859 N0.getOpcode() == ISD::ADD &&
15860 N0.getOperand(1) == N1 &&
15861 N1.getOpcode() == ISD::SRA &&
15862 N1.getOperand(0) == N0.getOperand(0))
15863 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
15864 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
15865 // Generate SUB & CMOV.
15866 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
15867 DAG.getConstant(0, VT), N0.getOperand(0));
15869 SDValue Ops[] = { N0.getOperand(0), Neg,
15870 DAG.getConstant(X86::COND_GE, MVT::i8),
15871 SDValue(Neg.getNode(), 1) };
15872 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
15873 Ops, array_lengthof(Ops));
15878 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
15879 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
15880 TargetLowering::DAGCombinerInfo &DCI,
15881 const X86Subtarget *Subtarget) {
15882 if (DCI.isBeforeLegalizeOps())
15885 if (Subtarget->hasCMov()) {
15886 SDValue RV = performIntegerAbsCombine(N, DAG);
15891 // Try forming BMI if it is available.
15892 if (!Subtarget->hasBMI())
15895 EVT VT = N->getValueType(0);
15897 if (VT != MVT::i32 && VT != MVT::i64)
15900 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
15902 // Create BLSMSK instructions by finding X ^ (X-1)
15903 SDValue N0 = N->getOperand(0);
15904 SDValue N1 = N->getOperand(1);
15905 DebugLoc DL = N->getDebugLoc();
15907 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
15908 isAllOnes(N0.getOperand(1)))
15909 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
15911 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
15912 isAllOnes(N1.getOperand(1)))
15913 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
15918 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
15919 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
15920 TargetLowering::DAGCombinerInfo &DCI,
15921 const X86Subtarget *Subtarget) {
15922 LoadSDNode *Ld = cast<LoadSDNode>(N);
15923 EVT RegVT = Ld->getValueType(0);
15924 EVT MemVT = Ld->getMemoryVT();
15925 DebugLoc dl = Ld->getDebugLoc();
15926 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15928 ISD::LoadExtType Ext = Ld->getExtensionType();
15930 // If this is a vector EXT Load then attempt to optimize it using a
15931 // shuffle. We need SSSE3 shuffles.
15932 // SEXT loads are suppoted starting SSE41.
15933 // We generate X86ISD::VSEXT for them.
15934 // TODO: It is possible to support ZExt by zeroing the undef values
15935 // during the shuffle phase or after the shuffle.
15936 if (RegVT.isVector() && RegVT.isInteger() &&
15937 (Ext == ISD::EXTLOAD && Subtarget->hasSSSE3() ||
15938 Ext == ISD::SEXTLOAD && Subtarget->hasSSE41())){
15939 assert(MemVT != RegVT && "Cannot extend to the same type");
15940 assert(MemVT.isVector() && "Must load a vector from memory");
15942 unsigned NumElems = RegVT.getVectorNumElements();
15943 unsigned RegSz = RegVT.getSizeInBits();
15944 unsigned MemSz = MemVT.getSizeInBits();
15945 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15947 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
15950 // All sizes must be a power of two.
15951 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
15954 // Attempt to load the original value using scalar loads.
15955 // Find the largest scalar type that divides the total loaded size.
15956 MVT SclrLoadTy = MVT::i8;
15957 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15958 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15959 MVT Tp = (MVT::SimpleValueType)tp;
15960 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15965 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15966 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15968 SclrLoadTy = MVT::f64;
15970 // Calculate the number of scalar loads that we need to perform
15971 // in order to load our vector from memory.
15972 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15973 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
15976 unsigned loadRegZize = RegSz;
15977 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15980 // Represent our vector as a sequence of elements which are the
15981 // largest scalar that we can load.
15982 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
15983 loadRegZize/SclrLoadTy.getSizeInBits());
15985 // Represent the data using the same element type that is stored in
15986 // memory. In practice, we ''widen'' MemVT.
15988 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15989 loadRegZize/MemVT.getScalarType().getSizeInBits());
15991 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15992 "Invalid vector type");
15994 // We can't shuffle using an illegal type.
15995 if (!TLI.isTypeLegal(WideVecVT))
15998 SmallVector<SDValue, 8> Chains;
15999 SDValue Ptr = Ld->getBasePtr();
16000 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
16001 TLI.getPointerTy());
16002 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16004 for (unsigned i = 0; i < NumLoads; ++i) {
16005 // Perform a single load.
16006 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
16007 Ptr, Ld->getPointerInfo(),
16008 Ld->isVolatile(), Ld->isNonTemporal(),
16009 Ld->isInvariant(), Ld->getAlignment());
16010 Chains.push_back(ScalarLoad.getValue(1));
16011 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16012 // another round of DAGCombining.
16014 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16016 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16017 ScalarLoad, DAG.getIntPtrConstant(i));
16019 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16022 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16025 // Bitcast the loaded value to a vector of the original element type, in
16026 // the size of the target vector type.
16027 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16028 unsigned SizeRatio = RegSz/MemSz;
16030 if (Ext == ISD::SEXTLOAD) {
16031 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16032 return DCI.CombineTo(N, Sext, TF, true);
16034 // Redistribute the loaded elements into the different locations.
16035 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16036 for (unsigned i = 0; i != NumElems; ++i)
16037 ShuffleVec[i*SizeRatio] = i;
16039 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16040 DAG.getUNDEF(WideVecVT),
16043 // Bitcast to the requested type.
16044 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16045 // Replace the original load with the new sequence
16046 // and return the new chain.
16047 return DCI.CombineTo(N, Shuff, TF, true);
16053 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
16054 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
16055 const X86Subtarget *Subtarget) {
16056 StoreSDNode *St = cast<StoreSDNode>(N);
16057 EVT VT = St->getValue().getValueType();
16058 EVT StVT = St->getMemoryVT();
16059 DebugLoc dl = St->getDebugLoc();
16060 SDValue StoredVal = St->getOperand(1);
16061 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16063 // If we are saving a concatenation of two XMM registers, perform two stores.
16064 // On Sandy Bridge, 256-bit memory operations are executed by two
16065 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
16066 // memory operation.
16067 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
16068 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
16069 StoredVal.getNumOperands() == 2) {
16070 SDValue Value0 = StoredVal.getOperand(0);
16071 SDValue Value1 = StoredVal.getOperand(1);
16073 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
16074 SDValue Ptr0 = St->getBasePtr();
16075 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
16077 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
16078 St->getPointerInfo(), St->isVolatile(),
16079 St->isNonTemporal(), St->getAlignment());
16080 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
16081 St->getPointerInfo(), St->isVolatile(),
16082 St->isNonTemporal(), St->getAlignment());
16083 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16086 // Optimize trunc store (of multiple scalars) to shuffle and store.
16087 // First, pack all of the elements in one place. Next, store to memory
16088 // in fewer chunks.
16089 if (St->isTruncatingStore() && VT.isVector()) {
16090 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16091 unsigned NumElems = VT.getVectorNumElements();
16092 assert(StVT != VT && "Cannot truncate to the same type");
16093 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
16094 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
16096 // From, To sizes and ElemCount must be pow of two
16097 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
16098 // We are going to use the original vector elt for storing.
16099 // Accumulated smaller vector elements must be a multiple of the store size.
16100 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
16102 unsigned SizeRatio = FromSz / ToSz;
16104 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
16106 // Create a type on which we perform the shuffle
16107 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
16108 StVT.getScalarType(), NumElems*SizeRatio);
16110 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
16112 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
16113 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16114 for (unsigned i = 0; i != NumElems; ++i)
16115 ShuffleVec[i] = i * SizeRatio;
16117 // Can't shuffle using an illegal type.
16118 if (!TLI.isTypeLegal(WideVecVT))
16121 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
16122 DAG.getUNDEF(WideVecVT),
16124 // At this point all of the data is stored at the bottom of the
16125 // register. We now need to save it to mem.
16127 // Find the largest store unit
16128 MVT StoreType = MVT::i8;
16129 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16130 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16131 MVT Tp = (MVT::SimpleValueType)tp;
16132 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
16136 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16137 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
16138 (64 <= NumElems * ToSz))
16139 StoreType = MVT::f64;
16141 // Bitcast the original vector into a vector of store-size units
16142 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
16143 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
16144 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
16145 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
16146 SmallVector<SDValue, 8> Chains;
16147 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
16148 TLI.getPointerTy());
16149 SDValue Ptr = St->getBasePtr();
16151 // Perform one or more big stores into memory.
16152 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
16153 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16154 StoreType, ShuffWide,
16155 DAG.getIntPtrConstant(i));
16156 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
16157 St->getPointerInfo(), St->isVolatile(),
16158 St->isNonTemporal(), St->getAlignment());
16159 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16160 Chains.push_back(Ch);
16163 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16168 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
16169 // the FP state in cases where an emms may be missing.
16170 // A preferable solution to the general problem is to figure out the right
16171 // places to insert EMMS. This qualifies as a quick hack.
16173 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
16174 if (VT.getSizeInBits() != 64)
16177 const Function *F = DAG.getMachineFunction().getFunction();
16178 bool NoImplicitFloatOps = F->getFnAttributes().
16179 hasAttribute(Attribute::NoImplicitFloat);
16180 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
16181 && Subtarget->hasSSE2();
16182 if ((VT.isVector() ||
16183 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
16184 isa<LoadSDNode>(St->getValue()) &&
16185 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
16186 St->getChain().hasOneUse() && !St->isVolatile()) {
16187 SDNode* LdVal = St->getValue().getNode();
16188 LoadSDNode *Ld = 0;
16189 int TokenFactorIndex = -1;
16190 SmallVector<SDValue, 8> Ops;
16191 SDNode* ChainVal = St->getChain().getNode();
16192 // Must be a store of a load. We currently handle two cases: the load
16193 // is a direct child, and it's under an intervening TokenFactor. It is
16194 // possible to dig deeper under nested TokenFactors.
16195 if (ChainVal == LdVal)
16196 Ld = cast<LoadSDNode>(St->getChain());
16197 else if (St->getValue().hasOneUse() &&
16198 ChainVal->getOpcode() == ISD::TokenFactor) {
16199 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
16200 if (ChainVal->getOperand(i).getNode() == LdVal) {
16201 TokenFactorIndex = i;
16202 Ld = cast<LoadSDNode>(St->getValue());
16204 Ops.push_back(ChainVal->getOperand(i));
16208 if (!Ld || !ISD::isNormalLoad(Ld))
16211 // If this is not the MMX case, i.e. we are just turning i64 load/store
16212 // into f64 load/store, avoid the transformation if there are multiple
16213 // uses of the loaded value.
16214 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
16217 DebugLoc LdDL = Ld->getDebugLoc();
16218 DebugLoc StDL = N->getDebugLoc();
16219 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
16220 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
16222 if (Subtarget->is64Bit() || F64IsLegal) {
16223 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
16224 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
16225 Ld->getPointerInfo(), Ld->isVolatile(),
16226 Ld->isNonTemporal(), Ld->isInvariant(),
16227 Ld->getAlignment());
16228 SDValue NewChain = NewLd.getValue(1);
16229 if (TokenFactorIndex != -1) {
16230 Ops.push_back(NewChain);
16231 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16234 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
16235 St->getPointerInfo(),
16236 St->isVolatile(), St->isNonTemporal(),
16237 St->getAlignment());
16240 // Otherwise, lower to two pairs of 32-bit loads / stores.
16241 SDValue LoAddr = Ld->getBasePtr();
16242 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
16243 DAG.getConstant(4, MVT::i32));
16245 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
16246 Ld->getPointerInfo(),
16247 Ld->isVolatile(), Ld->isNonTemporal(),
16248 Ld->isInvariant(), Ld->getAlignment());
16249 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
16250 Ld->getPointerInfo().getWithOffset(4),
16251 Ld->isVolatile(), Ld->isNonTemporal(),
16253 MinAlign(Ld->getAlignment(), 4));
16255 SDValue NewChain = LoLd.getValue(1);
16256 if (TokenFactorIndex != -1) {
16257 Ops.push_back(LoLd);
16258 Ops.push_back(HiLd);
16259 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16263 LoAddr = St->getBasePtr();
16264 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
16265 DAG.getConstant(4, MVT::i32));
16267 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
16268 St->getPointerInfo(),
16269 St->isVolatile(), St->isNonTemporal(),
16270 St->getAlignment());
16271 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
16272 St->getPointerInfo().getWithOffset(4),
16274 St->isNonTemporal(),
16275 MinAlign(St->getAlignment(), 4));
16276 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
16281 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
16282 /// and return the operands for the horizontal operation in LHS and RHS. A
16283 /// horizontal operation performs the binary operation on successive elements
16284 /// of its first operand, then on successive elements of its second operand,
16285 /// returning the resulting values in a vector. For example, if
16286 /// A = < float a0, float a1, float a2, float a3 >
16288 /// B = < float b0, float b1, float b2, float b3 >
16289 /// then the result of doing a horizontal operation on A and B is
16290 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
16291 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
16292 /// A horizontal-op B, for some already available A and B, and if so then LHS is
16293 /// set to A, RHS to B, and the routine returns 'true'.
16294 /// Note that the binary operation should have the property that if one of the
16295 /// operands is UNDEF then the result is UNDEF.
16296 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
16297 // Look for the following pattern: if
16298 // A = < float a0, float a1, float a2, float a3 >
16299 // B = < float b0, float b1, float b2, float b3 >
16301 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
16302 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
16303 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
16304 // which is A horizontal-op B.
16306 // At least one of the operands should be a vector shuffle.
16307 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
16308 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
16311 EVT VT = LHS.getValueType();
16313 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16314 "Unsupported vector type for horizontal add/sub");
16316 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
16317 // operate independently on 128-bit lanes.
16318 unsigned NumElts = VT.getVectorNumElements();
16319 unsigned NumLanes = VT.getSizeInBits()/128;
16320 unsigned NumLaneElts = NumElts / NumLanes;
16321 assert((NumLaneElts % 2 == 0) &&
16322 "Vector type should have an even number of elements in each lane");
16323 unsigned HalfLaneElts = NumLaneElts/2;
16325 // View LHS in the form
16326 // LHS = VECTOR_SHUFFLE A, B, LMask
16327 // If LHS is not a shuffle then pretend it is the shuffle
16328 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
16329 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
16332 SmallVector<int, 16> LMask(NumElts);
16333 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16334 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
16335 A = LHS.getOperand(0);
16336 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
16337 B = LHS.getOperand(1);
16338 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
16339 std::copy(Mask.begin(), Mask.end(), LMask.begin());
16341 if (LHS.getOpcode() != ISD::UNDEF)
16343 for (unsigned i = 0; i != NumElts; ++i)
16347 // Likewise, view RHS in the form
16348 // RHS = VECTOR_SHUFFLE C, D, RMask
16350 SmallVector<int, 16> RMask(NumElts);
16351 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16352 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
16353 C = RHS.getOperand(0);
16354 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
16355 D = RHS.getOperand(1);
16356 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
16357 std::copy(Mask.begin(), Mask.end(), RMask.begin());
16359 if (RHS.getOpcode() != ISD::UNDEF)
16361 for (unsigned i = 0; i != NumElts; ++i)
16365 // Check that the shuffles are both shuffling the same vectors.
16366 if (!(A == C && B == D) && !(A == D && B == C))
16369 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
16370 if (!A.getNode() && !B.getNode())
16373 // If A and B occur in reverse order in RHS, then "swap" them (which means
16374 // rewriting the mask).
16376 CommuteVectorShuffleMask(RMask, NumElts);
16378 // At this point LHS and RHS are equivalent to
16379 // LHS = VECTOR_SHUFFLE A, B, LMask
16380 // RHS = VECTOR_SHUFFLE A, B, RMask
16381 // Check that the masks correspond to performing a horizontal operation.
16382 for (unsigned i = 0; i != NumElts; ++i) {
16383 int LIdx = LMask[i], RIdx = RMask[i];
16385 // Ignore any UNDEF components.
16386 if (LIdx < 0 || RIdx < 0 ||
16387 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
16388 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
16391 // Check that successive elements are being operated on. If not, this is
16392 // not a horizontal operation.
16393 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
16394 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
16395 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
16396 if (!(LIdx == Index && RIdx == Index + 1) &&
16397 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
16401 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
16402 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
16406 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
16407 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
16408 const X86Subtarget *Subtarget) {
16409 EVT VT = N->getValueType(0);
16410 SDValue LHS = N->getOperand(0);
16411 SDValue RHS = N->getOperand(1);
16413 // Try to synthesize horizontal adds from adds of shuffles.
16414 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16415 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16416 isHorizontalBinOp(LHS, RHS, true))
16417 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
16421 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
16422 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
16423 const X86Subtarget *Subtarget) {
16424 EVT VT = N->getValueType(0);
16425 SDValue LHS = N->getOperand(0);
16426 SDValue RHS = N->getOperand(1);
16428 // Try to synthesize horizontal subs from subs of shuffles.
16429 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16430 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16431 isHorizontalBinOp(LHS, RHS, false))
16432 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
16436 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
16437 /// X86ISD::FXOR nodes.
16438 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
16439 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
16440 // F[X]OR(0.0, x) -> x
16441 // F[X]OR(x, 0.0) -> x
16442 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16443 if (C->getValueAPF().isPosZero())
16444 return N->getOperand(1);
16445 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16446 if (C->getValueAPF().isPosZero())
16447 return N->getOperand(0);
16451 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
16452 /// X86ISD::FMAX nodes.
16453 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
16454 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
16456 // Only perform optimizations if UnsafeMath is used.
16457 if (!DAG.getTarget().Options.UnsafeFPMath)
16460 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
16461 // into FMINC and FMAXC, which are Commutative operations.
16462 unsigned NewOp = 0;
16463 switch (N->getOpcode()) {
16464 default: llvm_unreachable("unknown opcode");
16465 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
16466 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
16469 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
16470 N->getOperand(0), N->getOperand(1));
16474 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
16475 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
16476 // FAND(0.0, x) -> 0.0
16477 // FAND(x, 0.0) -> 0.0
16478 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16479 if (C->getValueAPF().isPosZero())
16480 return N->getOperand(0);
16481 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16482 if (C->getValueAPF().isPosZero())
16483 return N->getOperand(1);
16487 static SDValue PerformBTCombine(SDNode *N,
16489 TargetLowering::DAGCombinerInfo &DCI) {
16490 // BT ignores high bits in the bit index operand.
16491 SDValue Op1 = N->getOperand(1);
16492 if (Op1.hasOneUse()) {
16493 unsigned BitWidth = Op1.getValueSizeInBits();
16494 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
16495 APInt KnownZero, KnownOne;
16496 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
16497 !DCI.isBeforeLegalizeOps());
16498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16499 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
16500 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
16501 DCI.CommitTargetLoweringOpt(TLO);
16506 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
16507 SDValue Op = N->getOperand(0);
16508 if (Op.getOpcode() == ISD::BITCAST)
16509 Op = Op.getOperand(0);
16510 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
16511 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
16512 VT.getVectorElementType().getSizeInBits() ==
16513 OpVT.getVectorElementType().getSizeInBits()) {
16514 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
16519 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
16520 TargetLowering::DAGCombinerInfo &DCI,
16521 const X86Subtarget *Subtarget) {
16522 if (!DCI.isBeforeLegalizeOps())
16525 if (!Subtarget->hasFp256())
16528 EVT VT = N->getValueType(0);
16529 SDValue Op = N->getOperand(0);
16530 EVT OpVT = Op.getValueType();
16531 DebugLoc dl = N->getDebugLoc();
16533 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
16534 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
16536 if (Subtarget->hasInt256())
16537 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
16539 // Optimize vectors in AVX mode
16540 // Sign extend v8i16 to v8i32 and
16543 // Divide input vector into two parts
16544 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
16545 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
16546 // concat the vectors to original VT
16548 unsigned NumElems = OpVT.getVectorNumElements();
16549 SDValue Undef = DAG.getUNDEF(OpVT);
16551 SmallVector<int,8> ShufMask1(NumElems, -1);
16552 for (unsigned i = 0; i != NumElems/2; ++i)
16555 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask1[0]);
16557 SmallVector<int,8> ShufMask2(NumElems, -1);
16558 for (unsigned i = 0; i != NumElems/2; ++i)
16559 ShufMask2[i] = i + NumElems/2;
16561 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask2[0]);
16563 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
16564 VT.getVectorNumElements()/2);
16566 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
16567 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
16569 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
16574 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
16575 const X86Subtarget* Subtarget) {
16576 DebugLoc dl = N->getDebugLoc();
16577 EVT VT = N->getValueType(0);
16579 // Let legalize expand this if it isn't a legal type yet.
16580 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16583 EVT ScalarVT = VT.getScalarType();
16584 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
16585 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
16588 SDValue A = N->getOperand(0);
16589 SDValue B = N->getOperand(1);
16590 SDValue C = N->getOperand(2);
16592 bool NegA = (A.getOpcode() == ISD::FNEG);
16593 bool NegB = (B.getOpcode() == ISD::FNEG);
16594 bool NegC = (C.getOpcode() == ISD::FNEG);
16596 // Negative multiplication when NegA xor NegB
16597 bool NegMul = (NegA != NegB);
16599 A = A.getOperand(0);
16601 B = B.getOperand(0);
16603 C = C.getOperand(0);
16607 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
16609 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
16611 return DAG.getNode(Opcode, dl, VT, A, B, C);
16614 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
16615 TargetLowering::DAGCombinerInfo &DCI,
16616 const X86Subtarget *Subtarget) {
16617 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
16618 // (and (i32 x86isd::setcc_carry), 1)
16619 // This eliminates the zext. This transformation is necessary because
16620 // ISD::SETCC is always legalized to i8.
16621 DebugLoc dl = N->getDebugLoc();
16622 SDValue N0 = N->getOperand(0);
16623 EVT VT = N->getValueType(0);
16624 EVT OpVT = N0.getValueType();
16626 if (N0.getOpcode() == ISD::AND &&
16628 N0.getOperand(0).hasOneUse()) {
16629 SDValue N00 = N0.getOperand(0);
16630 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
16632 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
16633 if (!C || C->getZExtValue() != 1)
16635 return DAG.getNode(ISD::AND, dl, VT,
16636 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
16637 N00.getOperand(0), N00.getOperand(1)),
16638 DAG.getConstant(1, VT));
16641 // Optimize vectors in AVX mode:
16644 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
16645 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
16646 // Concat upper and lower parts.
16649 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
16650 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
16651 // Concat upper and lower parts.
16653 if (!DCI.isBeforeLegalizeOps())
16656 if (!Subtarget->hasFp256())
16659 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
16660 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
16662 if (Subtarget->hasInt256())
16663 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
16665 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
16666 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
16667 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
16669 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
16670 VT.getVectorNumElements()/2);
16672 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
16673 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
16675 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
16681 // Optimize x == -y --> x+y == 0
16682 // x != -y --> x+y != 0
16683 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
16684 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
16685 SDValue LHS = N->getOperand(0);
16686 SDValue RHS = N->getOperand(1);
16688 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
16689 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
16690 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
16691 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
16692 LHS.getValueType(), RHS, LHS.getOperand(1));
16693 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
16694 addV, DAG.getConstant(0, addV.getValueType()), CC);
16696 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
16697 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
16698 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
16699 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
16700 RHS.getValueType(), LHS, RHS.getOperand(1));
16701 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
16702 addV, DAG.getConstant(0, addV.getValueType()), CC);
16707 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
16708 // as "sbb reg,reg", since it can be extended without zext and produces
16709 // an all-ones bit which is more useful than 0/1 in some cases.
16710 static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
16711 return DAG.getNode(ISD::AND, DL, MVT::i8,
16712 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
16713 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
16714 DAG.getConstant(1, MVT::i8));
16717 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
16718 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
16719 TargetLowering::DAGCombinerInfo &DCI,
16720 const X86Subtarget *Subtarget) {
16721 DebugLoc DL = N->getDebugLoc();
16722 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
16723 SDValue EFLAGS = N->getOperand(1);
16725 if (CC == X86::COND_A) {
16726 // Try to convert COND_A into COND_B in an attempt to facilitate
16727 // materializing "setb reg".
16729 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
16730 // cannot take an immediate as its first operand.
16732 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
16733 EFLAGS.getValueType().isInteger() &&
16734 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
16735 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(),
16736 EFLAGS.getNode()->getVTList(),
16737 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
16738 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
16739 return MaterializeSETB(DL, NewEFLAGS, DAG);
16743 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
16744 // a zext and produces an all-ones bit which is more useful than 0/1 in some
16746 if (CC == X86::COND_B)
16747 return MaterializeSETB(DL, EFLAGS, DAG);
16751 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
16752 if (Flags.getNode()) {
16753 SDValue Cond = DAG.getConstant(CC, MVT::i8);
16754 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
16760 // Optimize branch condition evaluation.
16762 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
16763 TargetLowering::DAGCombinerInfo &DCI,
16764 const X86Subtarget *Subtarget) {
16765 DebugLoc DL = N->getDebugLoc();
16766 SDValue Chain = N->getOperand(0);
16767 SDValue Dest = N->getOperand(1);
16768 SDValue EFLAGS = N->getOperand(3);
16769 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
16773 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
16774 if (Flags.getNode()) {
16775 SDValue Cond = DAG.getConstant(CC, MVT::i8);
16776 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
16783 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
16784 const X86TargetLowering *XTLI) {
16785 SDValue Op0 = N->getOperand(0);
16786 EVT InVT = Op0->getValueType(0);
16788 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
16789 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
16790 DebugLoc dl = N->getDebugLoc();
16791 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
16792 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
16793 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
16796 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
16797 // a 32-bit target where SSE doesn't support i64->FP operations.
16798 if (Op0.getOpcode() == ISD::LOAD) {
16799 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
16800 EVT VT = Ld->getValueType(0);
16801 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
16802 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
16803 !XTLI->getSubtarget()->is64Bit() &&
16804 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16805 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
16806 Ld->getChain(), Op0, DAG);
16807 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
16814 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
16815 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
16816 X86TargetLowering::DAGCombinerInfo &DCI) {
16817 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
16818 // the result is either zero or one (depending on the input carry bit).
16819 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
16820 if (X86::isZeroNode(N->getOperand(0)) &&
16821 X86::isZeroNode(N->getOperand(1)) &&
16822 // We don't have a good way to replace an EFLAGS use, so only do this when
16824 SDValue(N, 1).use_empty()) {
16825 DebugLoc DL = N->getDebugLoc();
16826 EVT VT = N->getValueType(0);
16827 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
16828 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
16829 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
16830 DAG.getConstant(X86::COND_B,MVT::i8),
16832 DAG.getConstant(1, VT));
16833 return DCI.CombineTo(N, Res1, CarryOut);
16839 // fold (add Y, (sete X, 0)) -> adc 0, Y
16840 // (add Y, (setne X, 0)) -> sbb -1, Y
16841 // (sub (sete X, 0), Y) -> sbb 0, Y
16842 // (sub (setne X, 0), Y) -> adc -1, Y
16843 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
16844 DebugLoc DL = N->getDebugLoc();
16846 // Look through ZExts.
16847 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
16848 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
16851 SDValue SetCC = Ext.getOperand(0);
16852 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
16855 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
16856 if (CC != X86::COND_E && CC != X86::COND_NE)
16859 SDValue Cmp = SetCC.getOperand(1);
16860 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
16861 !X86::isZeroNode(Cmp.getOperand(1)) ||
16862 !Cmp.getOperand(0).getValueType().isInteger())
16865 SDValue CmpOp0 = Cmp.getOperand(0);
16866 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
16867 DAG.getConstant(1, CmpOp0.getValueType()));
16869 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
16870 if (CC == X86::COND_NE)
16871 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
16872 DL, OtherVal.getValueType(), OtherVal,
16873 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
16874 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
16875 DL, OtherVal.getValueType(), OtherVal,
16876 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
16879 /// PerformADDCombine - Do target-specific dag combines on integer adds.
16880 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
16881 const X86Subtarget *Subtarget) {
16882 EVT VT = N->getValueType(0);
16883 SDValue Op0 = N->getOperand(0);
16884 SDValue Op1 = N->getOperand(1);
16886 // Try to synthesize horizontal adds from adds of shuffles.
16887 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
16888 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
16889 isHorizontalBinOp(Op0, Op1, true))
16890 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
16892 return OptimizeConditionalInDecrement(N, DAG);
16895 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
16896 const X86Subtarget *Subtarget) {
16897 SDValue Op0 = N->getOperand(0);
16898 SDValue Op1 = N->getOperand(1);
16900 // X86 can't encode an immediate LHS of a sub. See if we can push the
16901 // negation into a preceding instruction.
16902 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
16903 // If the RHS of the sub is a XOR with one use and a constant, invert the
16904 // immediate. Then add one to the LHS of the sub so we can turn
16905 // X-Y -> X+~Y+1, saving one register.
16906 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
16907 isa<ConstantSDNode>(Op1.getOperand(1))) {
16908 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
16909 EVT VT = Op0.getValueType();
16910 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
16912 DAG.getConstant(~XorC, VT));
16913 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
16914 DAG.getConstant(C->getAPIntValue()+1, VT));
16918 // Try to synthesize horizontal adds from adds of shuffles.
16919 EVT VT = N->getValueType(0);
16920 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
16921 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
16922 isHorizontalBinOp(Op0, Op1, true))
16923 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
16925 return OptimizeConditionalInDecrement(N, DAG);
16928 /// performVZEXTCombine - Performs build vector combines
16929 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
16930 TargetLowering::DAGCombinerInfo &DCI,
16931 const X86Subtarget *Subtarget) {
16932 // (vzext (bitcast (vzext (x)) -> (vzext x)
16933 SDValue In = N->getOperand(0);
16934 while (In.getOpcode() == ISD::BITCAST)
16935 In = In.getOperand(0);
16937 if (In.getOpcode() != X86ISD::VZEXT)
16940 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0), In.getOperand(0));
16943 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
16944 DAGCombinerInfo &DCI) const {
16945 SelectionDAG &DAG = DCI.DAG;
16946 switch (N->getOpcode()) {
16948 case ISD::EXTRACT_VECTOR_ELT:
16949 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
16951 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
16952 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
16953 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
16954 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
16955 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
16956 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
16959 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
16960 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
16961 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
16962 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
16963 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
16964 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
16965 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
16966 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
16967 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
16969 case X86ISD::FOR: return PerformFORCombine(N, DAG);
16971 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
16972 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
16973 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
16974 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
16975 case ISD::ANY_EXTEND:
16976 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
16977 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
16978 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
16979 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
16980 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
16981 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
16982 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
16983 case X86ISD::SHUFP: // Handle all target specific shuffles
16984 case X86ISD::PALIGN:
16985 case X86ISD::UNPCKH:
16986 case X86ISD::UNPCKL:
16987 case X86ISD::MOVHLPS:
16988 case X86ISD::MOVLHPS:
16989 case X86ISD::PSHUFD:
16990 case X86ISD::PSHUFHW:
16991 case X86ISD::PSHUFLW:
16992 case X86ISD::MOVSS:
16993 case X86ISD::MOVSD:
16994 case X86ISD::VPERMILP:
16995 case X86ISD::VPERM2X128:
16996 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
16997 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
17003 /// isTypeDesirableForOp - Return true if the target has native support for
17004 /// the specified value type and it is 'desirable' to use the type for the
17005 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
17006 /// instruction encodings are longer and some i16 instructions are slow.
17007 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
17008 if (!isTypeLegal(VT))
17010 if (VT != MVT::i16)
17017 case ISD::SIGN_EXTEND:
17018 case ISD::ZERO_EXTEND:
17019 case ISD::ANY_EXTEND:
17032 /// IsDesirableToPromoteOp - This method query the target whether it is
17033 /// beneficial for dag combiner to promote the specified node. If true, it
17034 /// should return the desired promotion type by reference.
17035 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
17036 EVT VT = Op.getValueType();
17037 if (VT != MVT::i16)
17040 bool Promote = false;
17041 bool Commute = false;
17042 switch (Op.getOpcode()) {
17045 LoadSDNode *LD = cast<LoadSDNode>(Op);
17046 // If the non-extending load has a single use and it's not live out, then it
17047 // might be folded.
17048 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
17049 Op.hasOneUse()*/) {
17050 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
17051 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
17052 // The only case where we'd want to promote LOAD (rather then it being
17053 // promoted as an operand is when it's only use is liveout.
17054 if (UI->getOpcode() != ISD::CopyToReg)
17061 case ISD::SIGN_EXTEND:
17062 case ISD::ZERO_EXTEND:
17063 case ISD::ANY_EXTEND:
17068 SDValue N0 = Op.getOperand(0);
17069 // Look out for (store (shl (load), x)).
17070 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
17083 SDValue N0 = Op.getOperand(0);
17084 SDValue N1 = Op.getOperand(1);
17085 if (!Commute && MayFoldLoad(N1))
17087 // Avoid disabling potential load folding opportunities.
17088 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
17090 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
17100 //===----------------------------------------------------------------------===//
17101 // X86 Inline Assembly Support
17102 //===----------------------------------------------------------------------===//
17105 // Helper to match a string separated by whitespace.
17106 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
17107 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
17109 for (unsigned i = 0, e = args.size(); i != e; ++i) {
17110 StringRef piece(*args[i]);
17111 if (!s.startswith(piece)) // Check if the piece matches.
17114 s = s.substr(piece.size());
17115 StringRef::size_type pos = s.find_first_not_of(" \t");
17116 if (pos == 0) // We matched a prefix.
17124 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
17127 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
17128 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
17130 std::string AsmStr = IA->getAsmString();
17132 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
17133 if (!Ty || Ty->getBitWidth() % 16 != 0)
17136 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
17137 SmallVector<StringRef, 4> AsmPieces;
17138 SplitString(AsmStr, AsmPieces, ";\n");
17140 switch (AsmPieces.size()) {
17141 default: return false;
17143 // FIXME: this should verify that we are targeting a 486 or better. If not,
17144 // we will turn this bswap into something that will be lowered to logical
17145 // ops instead of emitting the bswap asm. For now, we don't support 486 or
17146 // lower so don't worry about this.
17148 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
17149 matchAsm(AsmPieces[0], "bswapl", "$0") ||
17150 matchAsm(AsmPieces[0], "bswapq", "$0") ||
17151 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
17152 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
17153 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
17154 // No need to check constraints, nothing other than the equivalent of
17155 // "=r,0" would be valid here.
17156 return IntrinsicLowering::LowerToByteSwap(CI);
17159 // rorw $$8, ${0:w} --> llvm.bswap.i16
17160 if (CI->getType()->isIntegerTy(16) &&
17161 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17162 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
17163 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
17165 const std::string &ConstraintsStr = IA->getConstraintString();
17166 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17167 std::sort(AsmPieces.begin(), AsmPieces.end());
17168 if (AsmPieces.size() == 4 &&
17169 AsmPieces[0] == "~{cc}" &&
17170 AsmPieces[1] == "~{dirflag}" &&
17171 AsmPieces[2] == "~{flags}" &&
17172 AsmPieces[3] == "~{fpsr}")
17173 return IntrinsicLowering::LowerToByteSwap(CI);
17177 if (CI->getType()->isIntegerTy(32) &&
17178 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17179 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
17180 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
17181 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
17183 const std::string &ConstraintsStr = IA->getConstraintString();
17184 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17185 std::sort(AsmPieces.begin(), AsmPieces.end());
17186 if (AsmPieces.size() == 4 &&
17187 AsmPieces[0] == "~{cc}" &&
17188 AsmPieces[1] == "~{dirflag}" &&
17189 AsmPieces[2] == "~{flags}" &&
17190 AsmPieces[3] == "~{fpsr}")
17191 return IntrinsicLowering::LowerToByteSwap(CI);
17194 if (CI->getType()->isIntegerTy(64)) {
17195 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
17196 if (Constraints.size() >= 2 &&
17197 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
17198 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
17199 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
17200 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
17201 matchAsm(AsmPieces[1], "bswap", "%edx") &&
17202 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
17203 return IntrinsicLowering::LowerToByteSwap(CI);
17213 /// getConstraintType - Given a constraint letter, return the type of
17214 /// constraint it is for this target.
17215 X86TargetLowering::ConstraintType
17216 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
17217 if (Constraint.size() == 1) {
17218 switch (Constraint[0]) {
17229 return C_RegisterClass;
17253 return TargetLowering::getConstraintType(Constraint);
17256 /// Examine constraint type and operand type and determine a weight value.
17257 /// This object must already have been set up with the operand type
17258 /// and the current alternative constraint selected.
17259 TargetLowering::ConstraintWeight
17260 X86TargetLowering::getSingleConstraintMatchWeight(
17261 AsmOperandInfo &info, const char *constraint) const {
17262 ConstraintWeight weight = CW_Invalid;
17263 Value *CallOperandVal = info.CallOperandVal;
17264 // If we don't have a value, we can't do a match,
17265 // but allow it at the lowest weight.
17266 if (CallOperandVal == NULL)
17268 Type *type = CallOperandVal->getType();
17269 // Look at the constraint type.
17270 switch (*constraint) {
17272 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
17283 if (CallOperandVal->getType()->isIntegerTy())
17284 weight = CW_SpecificReg;
17289 if (type->isFloatingPointTy())
17290 weight = CW_SpecificReg;
17293 if (type->isX86_MMXTy() && Subtarget->hasMMX())
17294 weight = CW_SpecificReg;
17298 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
17299 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
17300 weight = CW_Register;
17303 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
17304 if (C->getZExtValue() <= 31)
17305 weight = CW_Constant;
17309 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17310 if (C->getZExtValue() <= 63)
17311 weight = CW_Constant;
17315 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17316 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
17317 weight = CW_Constant;
17321 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17322 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
17323 weight = CW_Constant;
17327 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17328 if (C->getZExtValue() <= 3)
17329 weight = CW_Constant;
17333 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17334 if (C->getZExtValue() <= 0xff)
17335 weight = CW_Constant;
17340 if (dyn_cast<ConstantFP>(CallOperandVal)) {
17341 weight = CW_Constant;
17345 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17346 if ((C->getSExtValue() >= -0x80000000LL) &&
17347 (C->getSExtValue() <= 0x7fffffffLL))
17348 weight = CW_Constant;
17352 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17353 if (C->getZExtValue() <= 0xffffffff)
17354 weight = CW_Constant;
17361 /// LowerXConstraint - try to replace an X constraint, which matches anything,
17362 /// with another that has more specific requirements based on the type of the
17363 /// corresponding operand.
17364 const char *X86TargetLowering::
17365 LowerXConstraint(EVT ConstraintVT) const {
17366 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
17367 // 'f' like normal targets.
17368 if (ConstraintVT.isFloatingPoint()) {
17369 if (Subtarget->hasSSE2())
17371 if (Subtarget->hasSSE1())
17375 return TargetLowering::LowerXConstraint(ConstraintVT);
17378 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
17379 /// vector. If it is invalid, don't add anything to Ops.
17380 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
17381 std::string &Constraint,
17382 std::vector<SDValue>&Ops,
17383 SelectionDAG &DAG) const {
17384 SDValue Result(0, 0);
17386 // Only support length 1 constraints for now.
17387 if (Constraint.length() > 1) return;
17389 char ConstraintLetter = Constraint[0];
17390 switch (ConstraintLetter) {
17393 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17394 if (C->getZExtValue() <= 31) {
17395 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17402 if (C->getZExtValue() <= 63) {
17403 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17409 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17410 if (isInt<8>(C->getSExtValue())) {
17411 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17417 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17418 if (C->getZExtValue() <= 255) {
17419 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17425 // 32-bit signed value
17426 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17427 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17428 C->getSExtValue())) {
17429 // Widen to 64 bits here to get it sign extended.
17430 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
17433 // FIXME gcc accepts some relocatable values here too, but only in certain
17434 // memory models; it's complicated.
17439 // 32-bit unsigned value
17440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17441 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17442 C->getZExtValue())) {
17443 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17447 // FIXME gcc accepts some relocatable values here too, but only in certain
17448 // memory models; it's complicated.
17452 // Literal immediates are always ok.
17453 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
17454 // Widen to 64 bits here to get it sign extended.
17455 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
17459 // In any sort of PIC mode addresses need to be computed at runtime by
17460 // adding in a register or some sort of table lookup. These can't
17461 // be used as immediates.
17462 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
17465 // If we are in non-pic codegen mode, we allow the address of a global (with
17466 // an optional displacement) to be used with 'i'.
17467 GlobalAddressSDNode *GA = 0;
17468 int64_t Offset = 0;
17470 // Match either (GA), (GA+C), (GA+C1+C2), etc.
17472 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
17473 Offset += GA->getOffset();
17475 } else if (Op.getOpcode() == ISD::ADD) {
17476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17477 Offset += C->getZExtValue();
17478 Op = Op.getOperand(0);
17481 } else if (Op.getOpcode() == ISD::SUB) {
17482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17483 Offset += -C->getZExtValue();
17484 Op = Op.getOperand(0);
17489 // Otherwise, this isn't something we can handle, reject it.
17493 const GlobalValue *GV = GA->getGlobal();
17494 // If we require an extra load to get this address, as in PIC mode, we
17495 // can't accept it.
17496 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
17497 getTargetMachine())))
17500 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
17501 GA->getValueType(0), Offset);
17506 if (Result.getNode()) {
17507 Ops.push_back(Result);
17510 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
17513 std::pair<unsigned, const TargetRegisterClass*>
17514 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
17516 // First, see if this is a constraint that directly corresponds to an LLVM
17518 if (Constraint.size() == 1) {
17519 // GCC Constraint Letters
17520 switch (Constraint[0]) {
17522 // TODO: Slight differences here in allocation order and leaving
17523 // RIP in the class. Do they matter any more here than they do
17524 // in the normal allocation?
17525 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
17526 if (Subtarget->is64Bit()) {
17527 if (VT == MVT::i32 || VT == MVT::f32)
17528 return std::make_pair(0U, &X86::GR32RegClass);
17529 if (VT == MVT::i16)
17530 return std::make_pair(0U, &X86::GR16RegClass);
17531 if (VT == MVT::i8 || VT == MVT::i1)
17532 return std::make_pair(0U, &X86::GR8RegClass);
17533 if (VT == MVT::i64 || VT == MVT::f64)
17534 return std::make_pair(0U, &X86::GR64RegClass);
17537 // 32-bit fallthrough
17538 case 'Q': // Q_REGS
17539 if (VT == MVT::i32 || VT == MVT::f32)
17540 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
17541 if (VT == MVT::i16)
17542 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
17543 if (VT == MVT::i8 || VT == MVT::i1)
17544 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
17545 if (VT == MVT::i64)
17546 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
17548 case 'r': // GENERAL_REGS
17549 case 'l': // INDEX_REGS
17550 if (VT == MVT::i8 || VT == MVT::i1)
17551 return std::make_pair(0U, &X86::GR8RegClass);
17552 if (VT == MVT::i16)
17553 return std::make_pair(0U, &X86::GR16RegClass);
17554 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
17555 return std::make_pair(0U, &X86::GR32RegClass);
17556 return std::make_pair(0U, &X86::GR64RegClass);
17557 case 'R': // LEGACY_REGS
17558 if (VT == MVT::i8 || VT == MVT::i1)
17559 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
17560 if (VT == MVT::i16)
17561 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
17562 if (VT == MVT::i32 || !Subtarget->is64Bit())
17563 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
17564 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
17565 case 'f': // FP Stack registers.
17566 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
17567 // value to the correct fpstack register class.
17568 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
17569 return std::make_pair(0U, &X86::RFP32RegClass);
17570 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
17571 return std::make_pair(0U, &X86::RFP64RegClass);
17572 return std::make_pair(0U, &X86::RFP80RegClass);
17573 case 'y': // MMX_REGS if MMX allowed.
17574 if (!Subtarget->hasMMX()) break;
17575 return std::make_pair(0U, &X86::VR64RegClass);
17576 case 'Y': // SSE_REGS if SSE2 allowed
17577 if (!Subtarget->hasSSE2()) break;
17579 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
17580 if (!Subtarget->hasSSE1()) break;
17582 switch (VT.getSimpleVT().SimpleTy) {
17584 // Scalar SSE types.
17587 return std::make_pair(0U, &X86::FR32RegClass);
17590 return std::make_pair(0U, &X86::FR64RegClass);
17598 return std::make_pair(0U, &X86::VR128RegClass);
17606 return std::make_pair(0U, &X86::VR256RegClass);
17612 // Use the default implementation in TargetLowering to convert the register
17613 // constraint into a member of a register class.
17614 std::pair<unsigned, const TargetRegisterClass*> Res;
17615 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
17617 // Not found as a standard register?
17618 if (Res.second == 0) {
17619 // Map st(0) -> st(7) -> ST0
17620 if (Constraint.size() == 7 && Constraint[0] == '{' &&
17621 tolower(Constraint[1]) == 's' &&
17622 tolower(Constraint[2]) == 't' &&
17623 Constraint[3] == '(' &&
17624 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
17625 Constraint[5] == ')' &&
17626 Constraint[6] == '}') {
17628 Res.first = X86::ST0+Constraint[4]-'0';
17629 Res.second = &X86::RFP80RegClass;
17633 // GCC allows "st(0)" to be called just plain "st".
17634 if (StringRef("{st}").equals_lower(Constraint)) {
17635 Res.first = X86::ST0;
17636 Res.second = &X86::RFP80RegClass;
17641 if (StringRef("{flags}").equals_lower(Constraint)) {
17642 Res.first = X86::EFLAGS;
17643 Res.second = &X86::CCRRegClass;
17647 // 'A' means EAX + EDX.
17648 if (Constraint == "A") {
17649 Res.first = X86::EAX;
17650 Res.second = &X86::GR32_ADRegClass;
17656 // Otherwise, check to see if this is a register class of the wrong value
17657 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
17658 // turn into {ax},{dx}.
17659 if (Res.second->hasType(VT))
17660 return Res; // Correct type already, nothing to do.
17662 // All of the single-register GCC register classes map their values onto
17663 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
17664 // really want an 8-bit or 32-bit register, map to the appropriate register
17665 // class and return the appropriate register.
17666 if (Res.second == &X86::GR16RegClass) {
17667 if (VT == MVT::i8) {
17668 unsigned DestReg = 0;
17669 switch (Res.first) {
17671 case X86::AX: DestReg = X86::AL; break;
17672 case X86::DX: DestReg = X86::DL; break;
17673 case X86::CX: DestReg = X86::CL; break;
17674 case X86::BX: DestReg = X86::BL; break;
17677 Res.first = DestReg;
17678 Res.second = &X86::GR8RegClass;
17680 } else if (VT == MVT::i32) {
17681 unsigned DestReg = 0;
17682 switch (Res.first) {
17684 case X86::AX: DestReg = X86::EAX; break;
17685 case X86::DX: DestReg = X86::EDX; break;
17686 case X86::CX: DestReg = X86::ECX; break;
17687 case X86::BX: DestReg = X86::EBX; break;
17688 case X86::SI: DestReg = X86::ESI; break;
17689 case X86::DI: DestReg = X86::EDI; break;
17690 case X86::BP: DestReg = X86::EBP; break;
17691 case X86::SP: DestReg = X86::ESP; break;
17694 Res.first = DestReg;
17695 Res.second = &X86::GR32RegClass;
17697 } else if (VT == MVT::i64) {
17698 unsigned DestReg = 0;
17699 switch (Res.first) {
17701 case X86::AX: DestReg = X86::RAX; break;
17702 case X86::DX: DestReg = X86::RDX; break;
17703 case X86::CX: DestReg = X86::RCX; break;
17704 case X86::BX: DestReg = X86::RBX; break;
17705 case X86::SI: DestReg = X86::RSI; break;
17706 case X86::DI: DestReg = X86::RDI; break;
17707 case X86::BP: DestReg = X86::RBP; break;
17708 case X86::SP: DestReg = X86::RSP; break;
17711 Res.first = DestReg;
17712 Res.second = &X86::GR64RegClass;
17715 } else if (Res.second == &X86::FR32RegClass ||
17716 Res.second == &X86::FR64RegClass ||
17717 Res.second == &X86::VR128RegClass) {
17718 // Handle references to XMM physical registers that got mapped into the
17719 // wrong class. This can happen with constraints like {xmm0} where the
17720 // target independent register mapper will just pick the first match it can
17721 // find, ignoring the required type.
17723 if (VT == MVT::f32 || VT == MVT::i32)
17724 Res.second = &X86::FR32RegClass;
17725 else if (VT == MVT::f64 || VT == MVT::i64)
17726 Res.second = &X86::FR64RegClass;
17727 else if (X86::VR128RegClass.hasType(VT))
17728 Res.second = &X86::VR128RegClass;
17729 else if (X86::VR256RegClass.hasType(VT))
17730 Res.second = &X86::VR256RegClass;
17736 //===----------------------------------------------------------------------===//
17740 //===----------------------------------------------------------------------===//
17742 struct X86CostTblEntry {
17749 FindInTable(const X86CostTblEntry *Tbl, unsigned len, int ISD, MVT Ty) {
17750 for (unsigned int i = 0; i < len; ++i)
17751 if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)
17754 // Could not find an entry.
17758 struct X86TypeConversionCostTblEntry {
17766 FindInConvertTable(const X86TypeConversionCostTblEntry *Tbl, unsigned len,
17767 int ISD, MVT Dst, MVT Src) {
17768 for (unsigned int i = 0; i < len; ++i)
17769 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
17772 // Could not find an entry.
17776 ScalarTargetTransformInfo::PopcntHwSupport
17777 X86ScalarTargetTransformImpl::getPopcntHwSupport(unsigned TyWidth) const {
17778 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
17779 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
17781 // TODO: Currently the __builtin_popcount() implementation using SSE3
17782 // instructions is inefficient. Once the problem is fixed, we should
17783 // call ST.hasSSE3() instead of ST.hasSSE4().
17784 return ST.hasSSE41() ? Fast : None;
17788 X86VectorTargetTransformInfo::getArithmeticInstrCost(unsigned Opcode,
17790 // Legalize the type.
17791 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(Ty);
17793 int ISD = InstructionOpcodeToISD(Opcode);
17794 assert(ISD && "Invalid opcode");
17796 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
17798 static const X86CostTblEntry AVX1CostTable[] = {
17799 // We don't have to scalarize unsupported ops. We can issue two half-sized
17800 // operations and we only need to extract the upper YMM half.
17801 // Two ops + 1 extract + 1 insert = 4.
17802 { ISD::MUL, MVT::v8i32, 4 },
17803 { ISD::SUB, MVT::v8i32, 4 },
17804 { ISD::ADD, MVT::v8i32, 4 },
17805 { ISD::MUL, MVT::v4i64, 4 },
17806 { ISD::SUB, MVT::v4i64, 4 },
17807 { ISD::ADD, MVT::v4i64, 4 },
17810 // Look for AVX1 lowering tricks.
17812 int Idx = FindInTable(AVX1CostTable, array_lengthof(AVX1CostTable), ISD,
17815 return LT.first * AVX1CostTable[Idx].Cost;
17817 // Fallback to the default implementation.
17818 return VectorTargetTransformImpl::getArithmeticInstrCost(Opcode, Ty);
17822 X86VectorTargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
17823 unsigned Index) const {
17824 assert(Val->isVectorTy() && "This must be a vector type");
17826 if (Index != -1U) {
17827 // Legalize the type.
17828 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(Val);
17830 // This type is legalized to a scalar type.
17831 if (!LT.second.isVector())
17834 // The type may be split. Normalize the index to the new type.
17835 unsigned Width = LT.second.getVectorNumElements();
17836 Index = Index % Width;
17838 // Floating point scalars are already located in index #0.
17839 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
17843 return VectorTargetTransformImpl::getVectorInstrCost(Opcode, Val, Index);
17846 unsigned X86VectorTargetTransformInfo::getCmpSelInstrCost(unsigned Opcode,
17848 Type *CondTy) const {
17849 // Legalize the type.
17850 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(ValTy);
17852 MVT MTy = LT.second;
17854 int ISD = InstructionOpcodeToISD(Opcode);
17855 assert(ISD && "Invalid opcode");
17857 const X86Subtarget &ST =
17858 TLI->getTargetMachine().getSubtarget<X86Subtarget>();
17860 static const X86CostTblEntry SSE42CostTbl[] = {
17861 { ISD::SETCC, MVT::v2f64, 1 },
17862 { ISD::SETCC, MVT::v4f32, 1 },
17863 { ISD::SETCC, MVT::v2i64, 1 },
17864 { ISD::SETCC, MVT::v4i32, 1 },
17865 { ISD::SETCC, MVT::v8i16, 1 },
17866 { ISD::SETCC, MVT::v16i8, 1 },
17869 static const X86CostTblEntry AVX1CostTbl[] = {
17870 { ISD::SETCC, MVT::v4f64, 1 },
17871 { ISD::SETCC, MVT::v8f32, 1 },
17872 // AVX1 does not support 8-wide integer compare.
17873 { ISD::SETCC, MVT::v4i64, 4 },
17874 { ISD::SETCC, MVT::v8i32, 4 },
17875 { ISD::SETCC, MVT::v16i16, 4 },
17876 { ISD::SETCC, MVT::v32i8, 4 },
17879 static const X86CostTblEntry AVX2CostTbl[] = {
17880 { ISD::SETCC, MVT::v4i64, 1 },
17881 { ISD::SETCC, MVT::v8i32, 1 },
17882 { ISD::SETCC, MVT::v16i16, 1 },
17883 { ISD::SETCC, MVT::v32i8, 1 },
17886 if (ST.hasAVX2()) {
17887 int Idx = FindInTable(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
17889 return LT.first * AVX2CostTbl[Idx].Cost;
17893 int Idx = FindInTable(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
17895 return LT.first * AVX1CostTbl[Idx].Cost;
17898 if (ST.hasSSE42()) {
17899 int Idx = FindInTable(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
17901 return LT.first * SSE42CostTbl[Idx].Cost;
17904 return VectorTargetTransformImpl::getCmpSelInstrCost(Opcode, ValTy, CondTy);
17907 unsigned X86VectorTargetTransformInfo::getCastInstrCost(unsigned Opcode,
17910 int ISD = InstructionOpcodeToISD(Opcode);
17911 assert(ISD && "Invalid opcode");
17913 EVT SrcTy = TLI->getValueType(Src);
17914 EVT DstTy = TLI->getValueType(Dst);
17916 if (!SrcTy.isSimple() || !DstTy.isSimple())
17917 return VectorTargetTransformImpl::getCastInstrCost(Opcode, Dst, Src);
17919 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
17921 static const X86TypeConversionCostTblEntry AVXConversionTbl[] = {
17922 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
17923 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
17924 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
17925 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
17926 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
17927 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
17928 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
17929 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
17930 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
17931 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
17932 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
17933 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
17934 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
17935 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
17936 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
17940 int Idx = FindInConvertTable(AVXConversionTbl,
17941 array_lengthof(AVXConversionTbl),
17942 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
17944 return AVXConversionTbl[Idx].Cost;
17947 return VectorTargetTransformImpl::getCastInstrCost(Opcode, Dst, Src);