1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i16, Expand);
526 if (Subtarget->hasPOPCNT()) {
527 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
529 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
531 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
532 if (Subtarget->is64Bit())
533 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
536 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
538 if (!Subtarget->hasMOVBE())
539 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
541 // These should be promoted to a larger select which is supported.
542 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
543 // X86 wants to expand cmov itself.
544 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
546 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
556 if (Subtarget->is64Bit()) {
557 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
560 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
561 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
562 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
563 // support continuation, user-level threading, and etc.. As a result, no
564 // other SjLj exception interfaces are implemented and please don't build
565 // your own exception handling based on them.
566 // LLVM/Clang supports zero-cost DWARF exception handling.
567 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
568 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
571 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
572 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
574 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
575 if (Subtarget->is64Bit())
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
577 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
578 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
579 if (Subtarget->is64Bit()) {
580 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
581 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
582 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
583 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
584 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
586 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
587 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
589 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
596 if (Subtarget->hasSSE1())
597 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
599 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
601 // Expand certain atomics
602 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
604 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
605 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
606 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
609 if (Subtarget->hasCmpxchg16b()) {
610 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
613 // FIXME - use subtarget debug flags
614 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
615 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
616 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
619 if (Subtarget->is64Bit()) {
620 setExceptionPointerRegister(X86::RAX);
621 setExceptionSelectorRegister(X86::RDX);
623 setExceptionPointerRegister(X86::EAX);
624 setExceptionSelectorRegister(X86::EDX);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
627 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
629 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
630 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::TRAP, MVT::Other, Legal);
633 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
635 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
636 setOperationAction(ISD::VASTART , MVT::Other, Custom);
637 setOperationAction(ISD::VAEND , MVT::Other, Expand);
638 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
639 // TargetInfo::X86_64ABIBuiltinVaList
640 setOperationAction(ISD::VAARG , MVT::Other, Custom);
641 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
643 // TargetInfo::CharPtrBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Expand);
645 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
648 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
649 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
651 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
652 MVT::i64 : MVT::i32, Custom);
654 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
655 // f32 and f64 use SSE.
656 // Set up the FP register classes.
657 addRegisterClass(MVT::f32, &X86::FR32RegClass);
658 addRegisterClass(MVT::f64, &X86::FR64RegClass);
660 // Use ANDPD to simulate FABS.
661 setOperationAction(ISD::FABS , MVT::f64, Custom);
662 setOperationAction(ISD::FABS , MVT::f32, Custom);
664 // Use XORP to simulate FNEG.
665 setOperationAction(ISD::FNEG , MVT::f64, Custom);
666 setOperationAction(ISD::FNEG , MVT::f32, Custom);
668 // Use ANDPD and ORPD to simulate FCOPYSIGN.
669 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
670 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
672 // Lower this to FGETSIGNx86 plus an AND.
673 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
674 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
676 // We don't support sin/cos/fmod
677 setOperationAction(ISD::FSIN , MVT::f64, Expand);
678 setOperationAction(ISD::FCOS , MVT::f64, Expand);
679 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
680 setOperationAction(ISD::FSIN , MVT::f32, Expand);
681 setOperationAction(ISD::FCOS , MVT::f32, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
684 // Expand FP immediates into loads from the stack, except for the special
686 addLegalFPImmediate(APFloat(+0.0)); // xorpd
687 addLegalFPImmediate(APFloat(+0.0f)); // xorps
688 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
689 // Use SSE for f32, x87 for f64.
690 // Set up the FP register classes.
691 addRegisterClass(MVT::f32, &X86::FR32RegClass);
692 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
694 // Use ANDPS to simulate FABS.
695 setOperationAction(ISD::FABS , MVT::f32, Custom);
697 // Use XORP to simulate FNEG.
698 setOperationAction(ISD::FNEG , MVT::f32, Custom);
700 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
702 // Use ANDPS and ORPS to simulate FCOPYSIGN.
703 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
704 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
706 // We don't support sin/cos/fmod
707 setOperationAction(ISD::FSIN , MVT::f32, Expand);
708 setOperationAction(ISD::FCOS , MVT::f32, Expand);
709 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
711 // Special cases we handle for FP constants.
712 addLegalFPImmediate(APFloat(+0.0f)); // xorps
713 addLegalFPImmediate(APFloat(+0.0)); // FLD0
714 addLegalFPImmediate(APFloat(+1.0)); // FLD1
715 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
716 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
718 if (!TM.Options.UnsafeFPMath) {
719 setOperationAction(ISD::FSIN , MVT::f64, Expand);
720 setOperationAction(ISD::FCOS , MVT::f64, Expand);
721 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
723 } else if (!TM.Options.UseSoftFloat) {
724 // f32 and f64 in x87.
725 // Set up the FP register classes.
726 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
727 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
729 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
730 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
731 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
734 if (!TM.Options.UnsafeFPMath) {
735 setOperationAction(ISD::FSIN , MVT::f64, Expand);
736 setOperationAction(ISD::FSIN , MVT::f32, Expand);
737 setOperationAction(ISD::FCOS , MVT::f64, Expand);
738 setOperationAction(ISD::FCOS , MVT::f32, Expand);
739 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
742 addLegalFPImmediate(APFloat(+0.0)); // FLD0
743 addLegalFPImmediate(APFloat(+1.0)); // FLD1
744 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
745 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
746 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
747 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
748 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
749 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
752 // We don't support FMA.
753 setOperationAction(ISD::FMA, MVT::f64, Expand);
754 setOperationAction(ISD::FMA, MVT::f32, Expand);
756 // Long double always uses X87.
757 if (!TM.Options.UseSoftFloat) {
758 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
759 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
760 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
762 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
763 addLegalFPImmediate(TmpFlt); // FLD0
765 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
768 APFloat TmpFlt2(+1.0);
769 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
771 addLegalFPImmediate(TmpFlt2); // FLD1
772 TmpFlt2.changeSign();
773 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
776 if (!TM.Options.UnsafeFPMath) {
777 setOperationAction(ISD::FSIN , MVT::f80, Expand);
778 setOperationAction(ISD::FCOS , MVT::f80, Expand);
779 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
782 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
783 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
784 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
785 setOperationAction(ISD::FRINT, MVT::f80, Expand);
786 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
787 setOperationAction(ISD::FMA, MVT::f80, Expand);
790 // Always use a library call for pow.
791 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
792 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
795 setOperationAction(ISD::FLOG, MVT::f80, Expand);
796 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
798 setOperationAction(ISD::FEXP, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
881 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
884 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
885 // with -msoft-float, disable use of MMX as well.
886 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
887 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
888 // No operations on x86mmx supported, everything uses intrinsics.
891 // MMX-sized vectors (other than x86mmx) are expected to be expanded
892 // into smaller operations.
893 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
894 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
895 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
896 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
897 setOperationAction(ISD::AND, MVT::v8i8, Expand);
898 setOperationAction(ISD::AND, MVT::v4i16, Expand);
899 setOperationAction(ISD::AND, MVT::v2i32, Expand);
900 setOperationAction(ISD::AND, MVT::v1i64, Expand);
901 setOperationAction(ISD::OR, MVT::v8i8, Expand);
902 setOperationAction(ISD::OR, MVT::v4i16, Expand);
903 setOperationAction(ISD::OR, MVT::v2i32, Expand);
904 setOperationAction(ISD::OR, MVT::v1i64, Expand);
905 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
906 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
907 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
908 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
909 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
910 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
911 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
912 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
913 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
914 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
915 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
916 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
917 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
918 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
919 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
920 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
921 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
923 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
924 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
926 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
927 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
928 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
929 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
930 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
931 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
932 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
933 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
934 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
935 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
937 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
940 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
941 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
943 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
944 // registers cannot be used even for integer operations.
945 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
946 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
947 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
948 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
950 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
951 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
952 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
953 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
954 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
955 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
956 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
957 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
958 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
959 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
960 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
961 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
962 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
963 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
964 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
965 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
966 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
967 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
968 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
969 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
970 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
971 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
973 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
974 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
975 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
976 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
978 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
979 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
984 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
985 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
986 MVT VT = (MVT::SimpleValueType)i;
987 // Do not attempt to custom lower non-power-of-2 vectors
988 if (!isPowerOf2_32(VT.getVectorNumElements()))
990 // Do not attempt to custom lower non-128-bit vectors
991 if (!VT.is128BitVector())
993 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
994 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
998 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
999 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1000 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1001 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1002 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1005 if (Subtarget->is64Bit()) {
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1010 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1011 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1012 MVT VT = (MVT::SimpleValueType)i;
1014 // Do not attempt to promote non-128-bit vectors
1015 if (!VT.is128BitVector())
1018 setOperationAction(ISD::AND, VT, Promote);
1019 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1020 setOperationAction(ISD::OR, VT, Promote);
1021 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1022 setOperationAction(ISD::XOR, VT, Promote);
1023 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1024 setOperationAction(ISD::LOAD, VT, Promote);
1025 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1026 setOperationAction(ISD::SELECT, VT, Promote);
1027 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1030 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1032 // Custom lower v2i64 and v2f64 selects.
1033 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1034 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1035 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1041 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1042 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1043 // As there is no 64-bit GPR available, we need build a special custom
1044 // sequence to convert from v2i32 to v2f32.
1045 if (!Subtarget->is64Bit())
1046 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1048 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1049 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1051 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1053 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1054 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1055 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1058 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1059 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1060 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1061 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1062 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1063 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1064 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1065 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1066 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1067 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1068 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1075 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1076 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1077 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1078 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1079 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1081 // FIXME: Do we need to handle scalar-to-vector here?
1082 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1084 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1085 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1086 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1087 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1088 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1089 // There is no BLENDI for byte vectors. We don't need to custom lower
1090 // some vselects for now.
1091 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1093 // i8 and i16 vectors are custom , because the source register and source
1094 // source memory operand types are not the same width. f32 vectors are
1095 // custom since the immediate controlling the insert encodes additional
1097 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1098 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1099 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1100 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1103 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1105 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1107 // FIXME: these should be Legal but thats only for the case where
1108 // the index is constant. For now custom expand to deal with that.
1109 if (Subtarget->is64Bit()) {
1110 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1115 if (Subtarget->hasSSE2()) {
1116 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1117 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1120 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1122 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1123 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1125 // In the customized shift lowering, the legal cases in AVX2 will be
1127 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1128 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1130 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1131 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1133 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1136 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1137 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1138 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1139 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1140 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1141 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1142 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1144 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1145 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1146 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1148 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1149 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1150 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1151 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1152 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1155 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1156 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1157 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1158 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1159 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1161 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1162 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1163 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1164 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1165 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1166 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1167 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1168 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1169 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1170 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1171 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1172 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1174 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1175 // even though v8i16 is a legal type.
1176 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1177 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1178 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1180 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1181 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1182 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1184 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1185 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1187 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1189 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1190 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1192 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1193 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1195 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1196 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1198 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1199 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1200 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1201 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1203 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1204 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1205 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1207 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1208 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1209 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1210 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1212 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1213 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1215 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1216 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1218 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1219 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1221 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1222 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1223 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1225 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1226 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1227 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1228 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1229 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1230 setOperationAction(ISD::FMA, MVT::f32, Legal);
1231 setOperationAction(ISD::FMA, MVT::f64, Legal);
1234 if (Subtarget->hasInt256()) {
1235 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1236 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1237 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1238 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1240 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1241 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1242 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1243 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1245 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1247 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1248 // Don't lower v32i8 because there is no 128-bit byte mul
1250 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1252 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1253 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1255 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1256 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1258 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1259 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1260 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1261 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1263 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1264 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1265 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1266 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1268 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1269 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1270 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1271 // Don't lower v32i8 because there is no 128-bit byte mul
1274 // In the customized shift lowering, the legal cases in AVX2 will be
1276 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1277 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1279 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1280 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1282 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1284 // Custom lower several nodes for 256-bit types.
1285 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1286 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1287 MVT VT = (MVT::SimpleValueType)i;
1289 // Extract subvector is special because the value type
1290 // (result) is 128-bit but the source is 256-bit wide.
1291 if (VT.is128BitVector())
1292 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1294 // Do not attempt to custom lower other non-256-bit vectors
1295 if (!VT.is256BitVector())
1298 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1299 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1300 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1301 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1302 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1303 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1304 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1307 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1308 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1309 MVT VT = (MVT::SimpleValueType)i;
1311 // Do not attempt to promote non-256-bit vectors
1312 if (!VT.is256BitVector())
1315 setOperationAction(ISD::AND, VT, Promote);
1316 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1317 setOperationAction(ISD::OR, VT, Promote);
1318 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1319 setOperationAction(ISD::XOR, VT, Promote);
1320 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1321 setOperationAction(ISD::LOAD, VT, Promote);
1322 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1323 setOperationAction(ISD::SELECT, VT, Promote);
1324 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1328 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1329 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1330 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1331 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1332 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1334 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1335 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1336 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1338 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1339 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1340 setOperationAction(ISD::XOR, MVT::i1, Legal);
1341 setOperationAction(ISD::OR, MVT::i1, Legal);
1342 setOperationAction(ISD::AND, MVT::i1, Legal);
1343 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1344 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1346 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1347 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1348 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1350 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1357 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1358 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1363 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1364 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1366 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1368 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1370 if (Subtarget->is64Bit()) {
1371 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1373 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1374 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1376 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1377 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1378 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1379 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1380 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1381 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1382 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1383 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1384 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1385 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1387 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1388 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1391 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1392 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1393 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1394 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1395 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1398 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1399 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1401 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1402 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1403 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1404 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1405 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1406 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1408 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1409 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1411 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1413 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1414 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1415 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1416 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1417 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1418 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1419 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1420 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1421 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1423 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1424 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1426 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1427 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1429 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1431 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1434 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1437 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1438 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1440 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1441 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1442 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1443 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1444 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1445 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1447 if (Subtarget->hasCDI()) {
1448 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1449 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1452 // Custom lower several nodes.
1453 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1454 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1455 MVT VT = (MVT::SimpleValueType)i;
1457 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1458 // Extract subvector is special because the value type
1459 // (result) is 256/128-bit but the source is 512-bit wide.
1460 if (VT.is128BitVector() || VT.is256BitVector())
1461 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1463 if (VT.getVectorElementType() == MVT::i1)
1464 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1466 // Do not attempt to custom lower other non-512-bit vectors
1467 if (!VT.is512BitVector())
1470 if ( EltSize >= 32) {
1471 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1472 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1473 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1474 setOperationAction(ISD::VSELECT, VT, Legal);
1475 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1476 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1477 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1480 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1481 MVT VT = (MVT::SimpleValueType)i;
1483 // Do not attempt to promote non-256-bit vectors
1484 if (!VT.is512BitVector())
1487 setOperationAction(ISD::SELECT, VT, Promote);
1488 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1492 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1493 // of this type with custom code.
1494 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1495 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1496 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1500 // We want to custom lower some of our intrinsics.
1501 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1502 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1503 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1504 if (!Subtarget->is64Bit())
1505 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1507 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1508 // handle type legalization for these operations here.
1510 // FIXME: We really should do custom legalization for addition and
1511 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1512 // than generic legalization for 64-bit multiplication-with-overflow, though.
1513 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1514 // Add/Sub/Mul with overflow operations are custom lowered.
1516 setOperationAction(ISD::SADDO, VT, Custom);
1517 setOperationAction(ISD::UADDO, VT, Custom);
1518 setOperationAction(ISD::SSUBO, VT, Custom);
1519 setOperationAction(ISD::USUBO, VT, Custom);
1520 setOperationAction(ISD::SMULO, VT, Custom);
1521 setOperationAction(ISD::UMULO, VT, Custom);
1524 // There are no 8-bit 3-address imul/mul instructions
1525 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1526 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1528 if (!Subtarget->is64Bit()) {
1529 // These libcalls are not available in 32-bit.
1530 setLibcallName(RTLIB::SHL_I128, nullptr);
1531 setLibcallName(RTLIB::SRL_I128, nullptr);
1532 setLibcallName(RTLIB::SRA_I128, nullptr);
1535 // Combine sin / cos into one node or libcall if possible.
1536 if (Subtarget->hasSinCos()) {
1537 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1538 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1539 if (Subtarget->isTargetDarwin()) {
1540 // For MacOSX, we don't want to the normal expansion of a libcall to
1541 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1543 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1544 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1548 if (Subtarget->isTargetWin64()) {
1549 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1550 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1551 setOperationAction(ISD::SREM, MVT::i128, Custom);
1552 setOperationAction(ISD::UREM, MVT::i128, Custom);
1553 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1554 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1557 // We have target-specific dag combine patterns for the following nodes:
1558 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1559 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1560 setTargetDAGCombine(ISD::VSELECT);
1561 setTargetDAGCombine(ISD::SELECT);
1562 setTargetDAGCombine(ISD::SHL);
1563 setTargetDAGCombine(ISD::SRA);
1564 setTargetDAGCombine(ISD::SRL);
1565 setTargetDAGCombine(ISD::OR);
1566 setTargetDAGCombine(ISD::AND);
1567 setTargetDAGCombine(ISD::ADD);
1568 setTargetDAGCombine(ISD::FADD);
1569 setTargetDAGCombine(ISD::FSUB);
1570 setTargetDAGCombine(ISD::FMA);
1571 setTargetDAGCombine(ISD::SUB);
1572 setTargetDAGCombine(ISD::LOAD);
1573 setTargetDAGCombine(ISD::STORE);
1574 setTargetDAGCombine(ISD::ZERO_EXTEND);
1575 setTargetDAGCombine(ISD::ANY_EXTEND);
1576 setTargetDAGCombine(ISD::SIGN_EXTEND);
1577 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1578 setTargetDAGCombine(ISD::TRUNCATE);
1579 setTargetDAGCombine(ISD::SINT_TO_FP);
1580 setTargetDAGCombine(ISD::SETCC);
1581 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1582 setTargetDAGCombine(ISD::BUILD_VECTOR);
1583 if (Subtarget->is64Bit())
1584 setTargetDAGCombine(ISD::MUL);
1585 setTargetDAGCombine(ISD::XOR);
1587 computeRegisterProperties();
1589 // On Darwin, -Os means optimize for size without hurting performance,
1590 // do not reduce the limit.
1591 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1592 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1593 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1594 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1595 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1596 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1597 setPrefLoopAlignment(4); // 2^4 bytes.
1599 // Predictable cmov don't hurt on atom because it's in-order.
1600 PredictableSelectIsExpensive = !Subtarget->isAtom();
1602 setPrefFunctionAlignment(4); // 2^4 bytes.
1605 TargetLoweringBase::LegalizeTypeAction
1606 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1607 if (ExperimentalVectorWideningLegalization &&
1608 VT.getVectorNumElements() != 1 &&
1609 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1610 return TypeWidenVector;
1612 return TargetLoweringBase::getPreferredVectorAction(VT);
1615 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1617 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1619 if (Subtarget->hasAVX512())
1620 switch(VT.getVectorNumElements()) {
1621 case 8: return MVT::v8i1;
1622 case 16: return MVT::v16i1;
1625 return VT.changeVectorElementTypeToInteger();
1628 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1629 /// the desired ByVal argument alignment.
1630 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1633 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1634 if (VTy->getBitWidth() == 128)
1636 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1637 unsigned EltAlign = 0;
1638 getMaxByValAlign(ATy->getElementType(), EltAlign);
1639 if (EltAlign > MaxAlign)
1640 MaxAlign = EltAlign;
1641 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1642 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1643 unsigned EltAlign = 0;
1644 getMaxByValAlign(STy->getElementType(i), EltAlign);
1645 if (EltAlign > MaxAlign)
1646 MaxAlign = EltAlign;
1653 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1654 /// function arguments in the caller parameter area. For X86, aggregates
1655 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1656 /// are at 4-byte boundaries.
1657 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1658 if (Subtarget->is64Bit()) {
1659 // Max of 8 and alignment of type.
1660 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1667 if (Subtarget->hasSSE1())
1668 getMaxByValAlign(Ty, Align);
1672 /// getOptimalMemOpType - Returns the target specific optimal type for load
1673 /// and store operations as a result of memset, memcpy, and memmove
1674 /// lowering. If DstAlign is zero that means it's safe to destination
1675 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1676 /// means there isn't a need to check it against alignment requirement,
1677 /// probably because the source does not need to be loaded. If 'IsMemset' is
1678 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1679 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1680 /// source is constant so it does not need to be loaded.
1681 /// It returns EVT::Other if the type should be determined using generic
1682 /// target-independent logic.
1684 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1685 unsigned DstAlign, unsigned SrcAlign,
1686 bool IsMemset, bool ZeroMemset,
1688 MachineFunction &MF) const {
1689 const Function *F = MF.getFunction();
1690 if ((!IsMemset || ZeroMemset) &&
1691 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1692 Attribute::NoImplicitFloat)) {
1694 (Subtarget->isUnalignedMemAccessFast() ||
1695 ((DstAlign == 0 || DstAlign >= 16) &&
1696 (SrcAlign == 0 || SrcAlign >= 16)))) {
1698 if (Subtarget->hasInt256())
1700 if (Subtarget->hasFp256())
1703 if (Subtarget->hasSSE2())
1705 if (Subtarget->hasSSE1())
1707 } else if (!MemcpyStrSrc && Size >= 8 &&
1708 !Subtarget->is64Bit() &&
1709 Subtarget->hasSSE2()) {
1710 // Do not use f64 to lower memcpy if source is string constant. It's
1711 // better to use i32 to avoid the loads.
1715 if (Subtarget->is64Bit() && Size >= 8)
1720 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1722 return X86ScalarSSEf32;
1723 else if (VT == MVT::f64)
1724 return X86ScalarSSEf64;
1729 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1733 *Fast = Subtarget->isUnalignedMemAccessFast();
1737 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1738 /// current function. The returned value is a member of the
1739 /// MachineJumpTableInfo::JTEntryKind enum.
1740 unsigned X86TargetLowering::getJumpTableEncoding() const {
1741 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1743 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1744 Subtarget->isPICStyleGOT())
1745 return MachineJumpTableInfo::EK_Custom32;
1747 // Otherwise, use the normal jump table encoding heuristics.
1748 return TargetLowering::getJumpTableEncoding();
1752 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1753 const MachineBasicBlock *MBB,
1754 unsigned uid,MCContext &Ctx) const{
1755 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1756 Subtarget->isPICStyleGOT());
1757 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1759 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1760 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1763 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1765 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1766 SelectionDAG &DAG) const {
1767 if (!Subtarget->is64Bit())
1768 // This doesn't have SDLoc associated with it, but is not really the
1769 // same as a Register.
1770 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1774 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1775 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1777 const MCExpr *X86TargetLowering::
1778 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1779 MCContext &Ctx) const {
1780 // X86-64 uses RIP relative addressing based on the jump table label.
1781 if (Subtarget->isPICStyleRIPRel())
1782 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1784 // Otherwise, the reference is relative to the PIC base.
1785 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1788 // FIXME: Why this routine is here? Move to RegInfo!
1789 std::pair<const TargetRegisterClass*, uint8_t>
1790 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1791 const TargetRegisterClass *RRC = nullptr;
1793 switch (VT.SimpleTy) {
1795 return TargetLowering::findRepresentativeClass(VT);
1796 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1797 RRC = Subtarget->is64Bit() ?
1798 (const TargetRegisterClass*)&X86::GR64RegClass :
1799 (const TargetRegisterClass*)&X86::GR32RegClass;
1802 RRC = &X86::VR64RegClass;
1804 case MVT::f32: case MVT::f64:
1805 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1806 case MVT::v4f32: case MVT::v2f64:
1807 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1809 RRC = &X86::VR128RegClass;
1812 return std::make_pair(RRC, Cost);
1815 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1816 unsigned &Offset) const {
1817 if (!Subtarget->isTargetLinux())
1820 if (Subtarget->is64Bit()) {
1821 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1823 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1835 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1836 unsigned DestAS) const {
1837 assert(SrcAS != DestAS && "Expected different address spaces!");
1839 return SrcAS < 256 && DestAS < 256;
1842 //===----------------------------------------------------------------------===//
1843 // Return Value Calling Convention Implementation
1844 //===----------------------------------------------------------------------===//
1846 #include "X86GenCallingConv.inc"
1849 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1850 MachineFunction &MF, bool isVarArg,
1851 const SmallVectorImpl<ISD::OutputArg> &Outs,
1852 LLVMContext &Context) const {
1853 SmallVector<CCValAssign, 16> RVLocs;
1854 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
1856 return CCInfo.CheckReturn(Outs, RetCC_X86);
1859 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1860 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1865 X86TargetLowering::LowerReturn(SDValue Chain,
1866 CallingConv::ID CallConv, bool isVarArg,
1867 const SmallVectorImpl<ISD::OutputArg> &Outs,
1868 const SmallVectorImpl<SDValue> &OutVals,
1869 SDLoc dl, SelectionDAG &DAG) const {
1870 MachineFunction &MF = DAG.getMachineFunction();
1871 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1873 SmallVector<CCValAssign, 16> RVLocs;
1874 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
1875 RVLocs, *DAG.getContext());
1876 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1879 SmallVector<SDValue, 6> RetOps;
1880 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1881 // Operand #1 = Bytes To Pop
1882 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1885 // Copy the result values into the output registers.
1886 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1887 CCValAssign &VA = RVLocs[i];
1888 assert(VA.isRegLoc() && "Can only return in registers!");
1889 SDValue ValToCopy = OutVals[i];
1890 EVT ValVT = ValToCopy.getValueType();
1892 // Promote values to the appropriate types
1893 if (VA.getLocInfo() == CCValAssign::SExt)
1894 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1895 else if (VA.getLocInfo() == CCValAssign::ZExt)
1896 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1897 else if (VA.getLocInfo() == CCValAssign::AExt)
1898 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1899 else if (VA.getLocInfo() == CCValAssign::BCvt)
1900 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1902 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1903 "Unexpected FP-extend for return value.");
1905 // If this is x86-64, and we disabled SSE, we can't return FP values,
1906 // or SSE or MMX vectors.
1907 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1908 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1909 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1910 report_fatal_error("SSE register return with SSE disabled");
1912 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1913 // llvm-gcc has never done it right and no one has noticed, so this
1914 // should be OK for now.
1915 if (ValVT == MVT::f64 &&
1916 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1917 report_fatal_error("SSE2 register return with SSE2 disabled");
1919 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1920 // the RET instruction and handled by the FP Stackifier.
1921 if (VA.getLocReg() == X86::ST0 ||
1922 VA.getLocReg() == X86::ST1) {
1923 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1924 // change the value to the FP stack register class.
1925 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1926 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1927 RetOps.push_back(ValToCopy);
1928 // Don't emit a copytoreg.
1932 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1933 // which is returned in RAX / RDX.
1934 if (Subtarget->is64Bit()) {
1935 if (ValVT == MVT::x86mmx) {
1936 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1937 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1938 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1940 // If we don't have SSE2 available, convert to v4f32 so the generated
1941 // register is legal.
1942 if (!Subtarget->hasSSE2())
1943 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1948 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1949 Flag = Chain.getValue(1);
1950 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1953 // The x86-64 ABIs require that for returning structs by value we copy
1954 // the sret argument into %rax/%eax (depending on ABI) for the return.
1955 // Win32 requires us to put the sret argument to %eax as well.
1956 // We saved the argument into a virtual register in the entry block,
1957 // so now we copy the value out and into %rax/%eax.
1958 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1959 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1960 MachineFunction &MF = DAG.getMachineFunction();
1961 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1962 unsigned Reg = FuncInfo->getSRetReturnReg();
1964 "SRetReturnReg should have been set in LowerFormalArguments().");
1965 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1968 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1969 X86::RAX : X86::EAX;
1970 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1971 Flag = Chain.getValue(1);
1973 // RAX/EAX now acts like a return value.
1974 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1977 RetOps[0] = Chain; // Update chain.
1979 // Add the flag if we have it.
1981 RetOps.push_back(Flag);
1983 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1986 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1987 if (N->getNumValues() != 1)
1989 if (!N->hasNUsesOfValue(1, 0))
1992 SDValue TCChain = Chain;
1993 SDNode *Copy = *N->use_begin();
1994 if (Copy->getOpcode() == ISD::CopyToReg) {
1995 // If the copy has a glue operand, we conservatively assume it isn't safe to
1996 // perform a tail call.
1997 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1999 TCChain = Copy->getOperand(0);
2000 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2003 bool HasRet = false;
2004 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2006 if (UI->getOpcode() != X86ISD::RET_FLAG)
2019 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
2020 ISD::NodeType ExtendKind) const {
2022 // TODO: Is this also valid on 32-bit?
2023 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2024 ReturnMVT = MVT::i8;
2026 ReturnMVT = MVT::i32;
2028 MVT MinVT = getRegisterType(ReturnMVT);
2029 return VT.bitsLT(MinVT) ? MinVT : VT;
2032 /// LowerCallResult - Lower the result values of a call into the
2033 /// appropriate copies out of appropriate physical registers.
2036 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2037 CallingConv::ID CallConv, bool isVarArg,
2038 const SmallVectorImpl<ISD::InputArg> &Ins,
2039 SDLoc dl, SelectionDAG &DAG,
2040 SmallVectorImpl<SDValue> &InVals) const {
2042 // Assign locations to each value returned by this call.
2043 SmallVector<CCValAssign, 16> RVLocs;
2044 bool Is64Bit = Subtarget->is64Bit();
2045 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2046 DAG.getTarget(), RVLocs, *DAG.getContext());
2047 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2049 // Copy all of the result registers out of their specified physreg.
2050 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2051 CCValAssign &VA = RVLocs[i];
2052 EVT CopyVT = VA.getValVT();
2054 // If this is x86-64, and we disabled SSE, we can't return FP values
2055 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2056 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2057 report_fatal_error("SSE register return with SSE disabled");
2062 // If this is a call to a function that returns an fp value on the floating
2063 // point stack, we must guarantee the value is popped from the stack, so
2064 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2065 // if the return value is not used. We use the FpPOP_RETVAL instruction
2067 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2068 // If we prefer to use the value in xmm registers, copy it out as f80 and
2069 // use a truncate to move it from fp stack reg to xmm reg.
2070 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2071 SDValue Ops[] = { Chain, InFlag };
2072 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2073 MVT::Other, MVT::Glue, Ops), 1);
2074 Val = Chain.getValue(0);
2076 // Round the f80 to the right size, which also moves it to the appropriate
2078 if (CopyVT != VA.getValVT())
2079 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2080 // This truncation won't change the value.
2081 DAG.getIntPtrConstant(1));
2083 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2084 CopyVT, InFlag).getValue(1);
2085 Val = Chain.getValue(0);
2087 InFlag = Chain.getValue(2);
2088 InVals.push_back(Val);
2094 //===----------------------------------------------------------------------===//
2095 // C & StdCall & Fast Calling Convention implementation
2096 //===----------------------------------------------------------------------===//
2097 // StdCall calling convention seems to be standard for many Windows' API
2098 // routines and around. It differs from C calling convention just a little:
2099 // callee should clean up the stack, not caller. Symbols should be also
2100 // decorated in some fancy way :) It doesn't support any vector arguments.
2101 // For info on fast calling convention see Fast Calling Convention (tail call)
2102 // implementation LowerX86_32FastCCCallTo.
2104 /// CallIsStructReturn - Determines whether a call uses struct return
2106 enum StructReturnType {
2111 static StructReturnType
2112 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2114 return NotStructReturn;
2116 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2117 if (!Flags.isSRet())
2118 return NotStructReturn;
2119 if (Flags.isInReg())
2120 return RegStructReturn;
2121 return StackStructReturn;
2124 /// ArgsAreStructReturn - Determines whether a function uses struct
2125 /// return semantics.
2126 static StructReturnType
2127 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2129 return NotStructReturn;
2131 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2132 if (!Flags.isSRet())
2133 return NotStructReturn;
2134 if (Flags.isInReg())
2135 return RegStructReturn;
2136 return StackStructReturn;
2139 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2140 /// by "Src" to address "Dst" with size and alignment information specified by
2141 /// the specific parameter attribute. The copy will be passed as a byval
2142 /// function parameter.
2144 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2145 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2147 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2149 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2150 /*isVolatile*/false, /*AlwaysInline=*/true,
2151 MachinePointerInfo(), MachinePointerInfo());
2154 /// IsTailCallConvention - Return true if the calling convention is one that
2155 /// supports tail call optimization.
2156 static bool IsTailCallConvention(CallingConv::ID CC) {
2157 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2158 CC == CallingConv::HiPE);
2161 /// \brief Return true if the calling convention is a C calling convention.
2162 static bool IsCCallConvention(CallingConv::ID CC) {
2163 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2164 CC == CallingConv::X86_64_SysV);
2167 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2168 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2172 CallingConv::ID CalleeCC = CS.getCallingConv();
2173 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2179 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2180 /// a tailcall target by changing its ABI.
2181 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2182 bool GuaranteedTailCallOpt) {
2183 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2187 X86TargetLowering::LowerMemArgument(SDValue Chain,
2188 CallingConv::ID CallConv,
2189 const SmallVectorImpl<ISD::InputArg> &Ins,
2190 SDLoc dl, SelectionDAG &DAG,
2191 const CCValAssign &VA,
2192 MachineFrameInfo *MFI,
2194 // Create the nodes corresponding to a load from this parameter slot.
2195 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2196 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2197 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2198 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2201 // If value is passed by pointer we have address passed instead of the value
2203 if (VA.getLocInfo() == CCValAssign::Indirect)
2204 ValVT = VA.getLocVT();
2206 ValVT = VA.getValVT();
2208 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2209 // changed with more analysis.
2210 // In case of tail call optimization mark all arguments mutable. Since they
2211 // could be overwritten by lowering of arguments in case of a tail call.
2212 if (Flags.isByVal()) {
2213 unsigned Bytes = Flags.getByValSize();
2214 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2215 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2216 return DAG.getFrameIndex(FI, getPointerTy());
2218 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2219 VA.getLocMemOffset(), isImmutable);
2220 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2221 return DAG.getLoad(ValVT, dl, Chain, FIN,
2222 MachinePointerInfo::getFixedStack(FI),
2223 false, false, false, 0);
2228 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2229 CallingConv::ID CallConv,
2231 const SmallVectorImpl<ISD::InputArg> &Ins,
2234 SmallVectorImpl<SDValue> &InVals)
2236 MachineFunction &MF = DAG.getMachineFunction();
2237 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2239 const Function* Fn = MF.getFunction();
2240 if (Fn->hasExternalLinkage() &&
2241 Subtarget->isTargetCygMing() &&
2242 Fn->getName() == "main")
2243 FuncInfo->setForceFramePointer(true);
2245 MachineFrameInfo *MFI = MF.getFrameInfo();
2246 bool Is64Bit = Subtarget->is64Bit();
2247 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2249 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2250 "Var args not supported with calling convention fastcc, ghc or hipe");
2252 // Assign locations to all of the incoming arguments.
2253 SmallVector<CCValAssign, 16> ArgLocs;
2254 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
2255 ArgLocs, *DAG.getContext());
2257 // Allocate shadow area for Win64
2259 CCInfo.AllocateStack(32, 8);
2261 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2263 unsigned LastVal = ~0U;
2265 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2266 CCValAssign &VA = ArgLocs[i];
2267 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2269 assert(VA.getValNo() != LastVal &&
2270 "Don't support value assigned to multiple locs yet");
2272 LastVal = VA.getValNo();
2274 if (VA.isRegLoc()) {
2275 EVT RegVT = VA.getLocVT();
2276 const TargetRegisterClass *RC;
2277 if (RegVT == MVT::i32)
2278 RC = &X86::GR32RegClass;
2279 else if (Is64Bit && RegVT == MVT::i64)
2280 RC = &X86::GR64RegClass;
2281 else if (RegVT == MVT::f32)
2282 RC = &X86::FR32RegClass;
2283 else if (RegVT == MVT::f64)
2284 RC = &X86::FR64RegClass;
2285 else if (RegVT.is512BitVector())
2286 RC = &X86::VR512RegClass;
2287 else if (RegVT.is256BitVector())
2288 RC = &X86::VR256RegClass;
2289 else if (RegVT.is128BitVector())
2290 RC = &X86::VR128RegClass;
2291 else if (RegVT == MVT::x86mmx)
2292 RC = &X86::VR64RegClass;
2293 else if (RegVT == MVT::i1)
2294 RC = &X86::VK1RegClass;
2295 else if (RegVT == MVT::v8i1)
2296 RC = &X86::VK8RegClass;
2297 else if (RegVT == MVT::v16i1)
2298 RC = &X86::VK16RegClass;
2300 llvm_unreachable("Unknown argument type!");
2302 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2303 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2305 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2306 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2308 if (VA.getLocInfo() == CCValAssign::SExt)
2309 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2310 DAG.getValueType(VA.getValVT()));
2311 else if (VA.getLocInfo() == CCValAssign::ZExt)
2312 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2313 DAG.getValueType(VA.getValVT()));
2314 else if (VA.getLocInfo() == CCValAssign::BCvt)
2315 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2317 if (VA.isExtInLoc()) {
2318 // Handle MMX values passed in XMM regs.
2319 if (RegVT.isVector())
2320 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2322 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2325 assert(VA.isMemLoc());
2326 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2329 // If value is passed via pointer - do a load.
2330 if (VA.getLocInfo() == CCValAssign::Indirect)
2331 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2332 MachinePointerInfo(), false, false, false, 0);
2334 InVals.push_back(ArgValue);
2337 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2338 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2339 // The x86-64 ABIs require that for returning structs by value we copy
2340 // the sret argument into %rax/%eax (depending on ABI) for the return.
2341 // Win32 requires us to put the sret argument to %eax as well.
2342 // Save the argument into a virtual register so that we can access it
2343 // from the return points.
2344 if (Ins[i].Flags.isSRet()) {
2345 unsigned Reg = FuncInfo->getSRetReturnReg();
2347 MVT PtrTy = getPointerTy();
2348 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2349 FuncInfo->setSRetReturnReg(Reg);
2351 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2352 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2358 unsigned StackSize = CCInfo.getNextStackOffset();
2359 // Align stack specially for tail calls.
2360 if (FuncIsMadeTailCallSafe(CallConv,
2361 MF.getTarget().Options.GuaranteedTailCallOpt))
2362 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2364 // If the function takes variable number of arguments, make a frame index for
2365 // the start of the first vararg value... for expansion of llvm.va_start.
2367 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2368 CallConv != CallingConv::X86_ThisCall)) {
2369 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2372 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2374 // FIXME: We should really autogenerate these arrays
2375 static const MCPhysReg GPR64ArgRegsWin64[] = {
2376 X86::RCX, X86::RDX, X86::R8, X86::R9
2378 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2379 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2381 static const MCPhysReg XMMArgRegs64Bit[] = {
2382 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2383 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2385 const MCPhysReg *GPR64ArgRegs;
2386 unsigned NumXMMRegs = 0;
2389 // The XMM registers which might contain var arg parameters are shadowed
2390 // in their paired GPR. So we only need to save the GPR to their home
2392 TotalNumIntRegs = 4;
2393 GPR64ArgRegs = GPR64ArgRegsWin64;
2395 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2396 GPR64ArgRegs = GPR64ArgRegs64Bit;
2398 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2401 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2404 bool NoImplicitFloatOps = Fn->getAttributes().
2405 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2406 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2407 "SSE register cannot be used when SSE is disabled!");
2408 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2409 NoImplicitFloatOps) &&
2410 "SSE register cannot be used when SSE is disabled!");
2411 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2412 !Subtarget->hasSSE1())
2413 // Kernel mode asks for SSE to be disabled, so don't push them
2415 TotalNumXMMRegs = 0;
2418 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
2419 // Get to the caller-allocated home save location. Add 8 to account
2420 // for the return address.
2421 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2422 FuncInfo->setRegSaveFrameIndex(
2423 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2424 // Fixup to set vararg frame on shadow area (4 x i64).
2426 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2428 // For X86-64, if there are vararg parameters that are passed via
2429 // registers, then we must store them to their spots on the stack so
2430 // they may be loaded by deferencing the result of va_next.
2431 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2432 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2433 FuncInfo->setRegSaveFrameIndex(
2434 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2438 // Store the integer parameter registers.
2439 SmallVector<SDValue, 8> MemOps;
2440 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2442 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2443 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2444 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2445 DAG.getIntPtrConstant(Offset));
2446 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2447 &X86::GR64RegClass);
2448 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2450 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2451 MachinePointerInfo::getFixedStack(
2452 FuncInfo->getRegSaveFrameIndex(), Offset),
2454 MemOps.push_back(Store);
2458 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2459 // Now store the XMM (fp + vector) parameter registers.
2460 SmallVector<SDValue, 11> SaveXMMOps;
2461 SaveXMMOps.push_back(Chain);
2463 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2464 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2465 SaveXMMOps.push_back(ALVal);
2467 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2468 FuncInfo->getRegSaveFrameIndex()));
2469 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2470 FuncInfo->getVarArgsFPOffset()));
2472 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2473 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2474 &X86::VR128RegClass);
2475 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2476 SaveXMMOps.push_back(Val);
2478 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2479 MVT::Other, SaveXMMOps));
2482 if (!MemOps.empty())
2483 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2487 // Some CCs need callee pop.
2488 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2489 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2490 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2492 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2493 // If this is an sret function, the return should pop the hidden pointer.
2494 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2495 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2496 argsAreStructReturn(Ins) == StackStructReturn)
2497 FuncInfo->setBytesToPopOnReturn(4);
2501 // RegSaveFrameIndex is X86-64 only.
2502 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2503 if (CallConv == CallingConv::X86_FastCall ||
2504 CallConv == CallingConv::X86_ThisCall)
2505 // fastcc functions can't have varargs.
2506 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2509 FuncInfo->setArgumentStackSize(StackSize);
2515 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2516 SDValue StackPtr, SDValue Arg,
2517 SDLoc dl, SelectionDAG &DAG,
2518 const CCValAssign &VA,
2519 ISD::ArgFlagsTy Flags) const {
2520 unsigned LocMemOffset = VA.getLocMemOffset();
2521 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2522 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2523 if (Flags.isByVal())
2524 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2526 return DAG.getStore(Chain, dl, Arg, PtrOff,
2527 MachinePointerInfo::getStack(LocMemOffset),
2531 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2532 /// optimization is performed and it is required.
2534 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2535 SDValue &OutRetAddr, SDValue Chain,
2536 bool IsTailCall, bool Is64Bit,
2537 int FPDiff, SDLoc dl) const {
2538 // Adjust the Return address stack slot.
2539 EVT VT = getPointerTy();
2540 OutRetAddr = getReturnAddressFrameIndex(DAG);
2542 // Load the "old" Return address.
2543 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2544 false, false, false, 0);
2545 return SDValue(OutRetAddr.getNode(), 1);
2548 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2549 /// optimization is performed and it is required (FPDiff!=0).
2550 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2551 SDValue Chain, SDValue RetAddrFrIdx,
2552 EVT PtrVT, unsigned SlotSize,
2553 int FPDiff, SDLoc dl) {
2554 // Store the return address to the appropriate stack slot.
2555 if (!FPDiff) return Chain;
2556 // Calculate the new stack slot for the return address.
2557 int NewReturnAddrFI =
2558 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2560 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2561 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2562 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2568 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2569 SmallVectorImpl<SDValue> &InVals) const {
2570 SelectionDAG &DAG = CLI.DAG;
2572 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2573 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2574 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2575 SDValue Chain = CLI.Chain;
2576 SDValue Callee = CLI.Callee;
2577 CallingConv::ID CallConv = CLI.CallConv;
2578 bool &isTailCall = CLI.IsTailCall;
2579 bool isVarArg = CLI.IsVarArg;
2581 MachineFunction &MF = DAG.getMachineFunction();
2582 bool Is64Bit = Subtarget->is64Bit();
2583 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2584 StructReturnType SR = callIsStructReturn(Outs);
2585 bool IsSibcall = false;
2587 if (MF.getTarget().Options.DisableTailCalls)
2590 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2592 // Force this to be a tail call. The verifier rules are enough to ensure
2593 // that we can lower this successfully without moving the return address
2596 } else if (isTailCall) {
2597 // Check if it's really possible to do a tail call.
2598 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2599 isVarArg, SR != NotStructReturn,
2600 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2601 Outs, OutVals, Ins, DAG);
2603 // Sibcalls are automatically detected tailcalls which do not require
2605 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2612 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2613 "Var args not supported with calling convention fastcc, ghc or hipe");
2615 // Analyze operands of the call, assigning locations to each operand.
2616 SmallVector<CCValAssign, 16> ArgLocs;
2617 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
2618 ArgLocs, *DAG.getContext());
2620 // Allocate shadow area for Win64
2622 CCInfo.AllocateStack(32, 8);
2624 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2626 // Get a count of how many bytes are to be pushed on the stack.
2627 unsigned NumBytes = CCInfo.getNextStackOffset();
2629 // This is a sibcall. The memory operands are available in caller's
2630 // own caller's stack.
2632 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2633 IsTailCallConvention(CallConv))
2634 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2637 if (isTailCall && !IsSibcall && !IsMustTail) {
2638 // Lower arguments at fp - stackoffset + fpdiff.
2639 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2640 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2642 FPDiff = NumBytesCallerPushed - NumBytes;
2644 // Set the delta of movement of the returnaddr stackslot.
2645 // But only set if delta is greater than previous delta.
2646 if (FPDiff < X86Info->getTCReturnAddrDelta())
2647 X86Info->setTCReturnAddrDelta(FPDiff);
2650 unsigned NumBytesToPush = NumBytes;
2651 unsigned NumBytesToPop = NumBytes;
2653 // If we have an inalloca argument, all stack space has already been allocated
2654 // for us and be right at the top of the stack. We don't support multiple
2655 // arguments passed in memory when using inalloca.
2656 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2658 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2659 "an inalloca argument must be the only memory argument");
2663 Chain = DAG.getCALLSEQ_START(
2664 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2666 SDValue RetAddrFrIdx;
2667 // Load return address for tail calls.
2668 if (isTailCall && FPDiff)
2669 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2670 Is64Bit, FPDiff, dl);
2672 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2673 SmallVector<SDValue, 8> MemOpChains;
2676 // Walk the register/memloc assignments, inserting copies/loads. In the case
2677 // of tail call optimization arguments are handle later.
2678 const X86RegisterInfo *RegInfo =
2679 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
2680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2681 // Skip inalloca arguments, they have already been written.
2682 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2683 if (Flags.isInAlloca())
2686 CCValAssign &VA = ArgLocs[i];
2687 EVT RegVT = VA.getLocVT();
2688 SDValue Arg = OutVals[i];
2689 bool isByVal = Flags.isByVal();
2691 // Promote the value if needed.
2692 switch (VA.getLocInfo()) {
2693 default: llvm_unreachable("Unknown loc info!");
2694 case CCValAssign::Full: break;
2695 case CCValAssign::SExt:
2696 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2698 case CCValAssign::ZExt:
2699 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2701 case CCValAssign::AExt:
2702 if (RegVT.is128BitVector()) {
2703 // Special case: passing MMX values in XMM registers.
2704 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2705 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2706 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2708 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2710 case CCValAssign::BCvt:
2711 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2713 case CCValAssign::Indirect: {
2714 // Store the argument.
2715 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2716 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2717 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2718 MachinePointerInfo::getFixedStack(FI),
2725 if (VA.isRegLoc()) {
2726 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2727 if (isVarArg && IsWin64) {
2728 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2729 // shadow reg if callee is a varargs function.
2730 unsigned ShadowReg = 0;
2731 switch (VA.getLocReg()) {
2732 case X86::XMM0: ShadowReg = X86::RCX; break;
2733 case X86::XMM1: ShadowReg = X86::RDX; break;
2734 case X86::XMM2: ShadowReg = X86::R8; break;
2735 case X86::XMM3: ShadowReg = X86::R9; break;
2738 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2740 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2741 assert(VA.isMemLoc());
2742 if (!StackPtr.getNode())
2743 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2745 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2746 dl, DAG, VA, Flags));
2750 if (!MemOpChains.empty())
2751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2753 if (Subtarget->isPICStyleGOT()) {
2754 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2757 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2758 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2760 // If we are tail calling and generating PIC/GOT style code load the
2761 // address of the callee into ECX. The value in ecx is used as target of
2762 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2763 // for tail calls on PIC/GOT architectures. Normally we would just put the
2764 // address of GOT into ebx and then call target@PLT. But for tail calls
2765 // ebx would be restored (since ebx is callee saved) before jumping to the
2768 // Note: The actual moving to ECX is done further down.
2769 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2770 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2771 !G->getGlobal()->hasProtectedVisibility())
2772 Callee = LowerGlobalAddress(Callee, DAG);
2773 else if (isa<ExternalSymbolSDNode>(Callee))
2774 Callee = LowerExternalSymbol(Callee, DAG);
2778 if (Is64Bit && isVarArg && !IsWin64) {
2779 // From AMD64 ABI document:
2780 // For calls that may call functions that use varargs or stdargs
2781 // (prototype-less calls or calls to functions containing ellipsis (...) in
2782 // the declaration) %al is used as hidden argument to specify the number
2783 // of SSE registers used. The contents of %al do not need to match exactly
2784 // the number of registers, but must be an ubound on the number of SSE
2785 // registers used and is in the range 0 - 8 inclusive.
2787 // Count the number of XMM registers allocated.
2788 static const MCPhysReg XMMArgRegs[] = {
2789 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2790 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2792 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2793 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2794 && "SSE registers cannot be used when SSE is disabled");
2796 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2797 DAG.getConstant(NumXMMRegs, MVT::i8)));
2800 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2801 // don't need this because the eligibility check rejects calls that require
2802 // shuffling arguments passed in memory.
2803 if (!IsSibcall && isTailCall) {
2804 // Force all the incoming stack arguments to be loaded from the stack
2805 // before any new outgoing arguments are stored to the stack, because the
2806 // outgoing stack slots may alias the incoming argument stack slots, and
2807 // the alias isn't otherwise explicit. This is slightly more conservative
2808 // than necessary, because it means that each store effectively depends
2809 // on every argument instead of just those arguments it would clobber.
2810 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2812 SmallVector<SDValue, 8> MemOpChains2;
2815 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2816 CCValAssign &VA = ArgLocs[i];
2819 assert(VA.isMemLoc());
2820 SDValue Arg = OutVals[i];
2821 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2822 // Skip inalloca arguments. They don't require any work.
2823 if (Flags.isInAlloca())
2825 // Create frame index.
2826 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2827 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2828 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2829 FIN = DAG.getFrameIndex(FI, getPointerTy());
2831 if (Flags.isByVal()) {
2832 // Copy relative to framepointer.
2833 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2834 if (!StackPtr.getNode())
2835 StackPtr = DAG.getCopyFromReg(Chain, dl,
2836 RegInfo->getStackRegister(),
2838 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2840 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2844 // Store relative to framepointer.
2845 MemOpChains2.push_back(
2846 DAG.getStore(ArgChain, dl, Arg, FIN,
2847 MachinePointerInfo::getFixedStack(FI),
2852 if (!MemOpChains2.empty())
2853 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2855 // Store the return address to the appropriate stack slot.
2856 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2857 getPointerTy(), RegInfo->getSlotSize(),
2861 // Build a sequence of copy-to-reg nodes chained together with token chain
2862 // and flag operands which copy the outgoing args into registers.
2864 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2865 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2866 RegsToPass[i].second, InFlag);
2867 InFlag = Chain.getValue(1);
2870 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2871 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2872 // In the 64-bit large code model, we have to make all calls
2873 // through a register, since the call instruction's 32-bit
2874 // pc-relative offset may not be large enough to hold the whole
2876 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2877 // If the callee is a GlobalAddress node (quite common, every direct call
2878 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2881 // We should use extra load for direct calls to dllimported functions in
2883 const GlobalValue *GV = G->getGlobal();
2884 if (!GV->hasDLLImportStorageClass()) {
2885 unsigned char OpFlags = 0;
2886 bool ExtraLoad = false;
2887 unsigned WrapperKind = ISD::DELETED_NODE;
2889 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2890 // external symbols most go through the PLT in PIC mode. If the symbol
2891 // has hidden or protected visibility, or if it is static or local, then
2892 // we don't need to use the PLT - we can directly call it.
2893 if (Subtarget->isTargetELF() &&
2894 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2895 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2896 OpFlags = X86II::MO_PLT;
2897 } else if (Subtarget->isPICStyleStubAny() &&
2898 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2899 (!Subtarget->getTargetTriple().isMacOSX() ||
2900 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2901 // PC-relative references to external symbols should go through $stub,
2902 // unless we're building with the leopard linker or later, which
2903 // automatically synthesizes these stubs.
2904 OpFlags = X86II::MO_DARWIN_STUB;
2905 } else if (Subtarget->isPICStyleRIPRel() &&
2906 isa<Function>(GV) &&
2907 cast<Function>(GV)->getAttributes().
2908 hasAttribute(AttributeSet::FunctionIndex,
2909 Attribute::NonLazyBind)) {
2910 // If the function is marked as non-lazy, generate an indirect call
2911 // which loads from the GOT directly. This avoids runtime overhead
2912 // at the cost of eager binding (and one extra byte of encoding).
2913 OpFlags = X86II::MO_GOTPCREL;
2914 WrapperKind = X86ISD::WrapperRIP;
2918 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2919 G->getOffset(), OpFlags);
2921 // Add a wrapper if needed.
2922 if (WrapperKind != ISD::DELETED_NODE)
2923 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2924 // Add extra indirection if needed.
2926 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2927 MachinePointerInfo::getGOT(),
2928 false, false, false, 0);
2930 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2931 unsigned char OpFlags = 0;
2933 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2934 // external symbols should go through the PLT.
2935 if (Subtarget->isTargetELF() &&
2936 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2937 OpFlags = X86II::MO_PLT;
2938 } else if (Subtarget->isPICStyleStubAny() &&
2939 (!Subtarget->getTargetTriple().isMacOSX() ||
2940 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2941 // PC-relative references to external symbols should go through $stub,
2942 // unless we're building with the leopard linker or later, which
2943 // automatically synthesizes these stubs.
2944 OpFlags = X86II::MO_DARWIN_STUB;
2947 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2951 // Returns a chain & a flag for retval copy to use.
2952 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2953 SmallVector<SDValue, 8> Ops;
2955 if (!IsSibcall && isTailCall) {
2956 Chain = DAG.getCALLSEQ_END(Chain,
2957 DAG.getIntPtrConstant(NumBytesToPop, true),
2958 DAG.getIntPtrConstant(0, true), InFlag, dl);
2959 InFlag = Chain.getValue(1);
2962 Ops.push_back(Chain);
2963 Ops.push_back(Callee);
2966 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2968 // Add argument registers to the end of the list so that they are known live
2970 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2971 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2972 RegsToPass[i].second.getValueType()));
2974 // Add a register mask operand representing the call-preserved registers.
2975 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
2976 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2977 assert(Mask && "Missing call preserved mask for calling convention");
2978 Ops.push_back(DAG.getRegisterMask(Mask));
2980 if (InFlag.getNode())
2981 Ops.push_back(InFlag);
2985 //// If this is the first return lowered for this function, add the regs
2986 //// to the liveout set for the function.
2987 // This isn't right, although it's probably harmless on x86; liveouts
2988 // should be computed from returns not tail calls. Consider a void
2989 // function making a tail call to a function returning int.
2990 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
2993 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
2994 InFlag = Chain.getValue(1);
2996 // Create the CALLSEQ_END node.
2997 unsigned NumBytesForCalleeToPop;
2998 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2999 DAG.getTarget().Options.GuaranteedTailCallOpt))
3000 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3001 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3002 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3003 SR == StackStructReturn)
3004 // If this is a call to a struct-return function, the callee
3005 // pops the hidden struct pointer, so we have to push it back.
3006 // This is common for Darwin/X86, Linux & Mingw32 targets.
3007 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3008 NumBytesForCalleeToPop = 4;
3010 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3012 // Returns a flag for retval copy to use.
3014 Chain = DAG.getCALLSEQ_END(Chain,
3015 DAG.getIntPtrConstant(NumBytesToPop, true),
3016 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3019 InFlag = Chain.getValue(1);
3022 // Handle result values, copying them out of physregs into vregs that we
3024 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3025 Ins, dl, DAG, InVals);
3028 //===----------------------------------------------------------------------===//
3029 // Fast Calling Convention (tail call) implementation
3030 //===----------------------------------------------------------------------===//
3032 // Like std call, callee cleans arguments, convention except that ECX is
3033 // reserved for storing the tail called function address. Only 2 registers are
3034 // free for argument passing (inreg). Tail call optimization is performed
3036 // * tailcallopt is enabled
3037 // * caller/callee are fastcc
3038 // On X86_64 architecture with GOT-style position independent code only local
3039 // (within module) calls are supported at the moment.
3040 // To keep the stack aligned according to platform abi the function
3041 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3042 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3043 // If a tail called function callee has more arguments than the caller the
3044 // caller needs to make sure that there is room to move the RETADDR to. This is
3045 // achieved by reserving an area the size of the argument delta right after the
3046 // original REtADDR, but before the saved framepointer or the spilled registers
3047 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3059 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3060 /// for a 16 byte align requirement.
3062 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3063 SelectionDAG& DAG) const {
3064 MachineFunction &MF = DAG.getMachineFunction();
3065 const TargetMachine &TM = MF.getTarget();
3066 const X86RegisterInfo *RegInfo =
3067 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3068 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3069 unsigned StackAlignment = TFI.getStackAlignment();
3070 uint64_t AlignMask = StackAlignment - 1;
3071 int64_t Offset = StackSize;
3072 unsigned SlotSize = RegInfo->getSlotSize();
3073 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3074 // Number smaller than 12 so just add the difference.
3075 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3077 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3078 Offset = ((~AlignMask) & Offset) + StackAlignment +
3079 (StackAlignment-SlotSize);
3084 /// MatchingStackOffset - Return true if the given stack call argument is
3085 /// already available in the same position (relatively) of the caller's
3086 /// incoming argument stack.
3088 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3089 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3090 const X86InstrInfo *TII) {
3091 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3093 if (Arg.getOpcode() == ISD::CopyFromReg) {
3094 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3095 if (!TargetRegisterInfo::isVirtualRegister(VR))
3097 MachineInstr *Def = MRI->getVRegDef(VR);
3100 if (!Flags.isByVal()) {
3101 if (!TII->isLoadFromStackSlot(Def, FI))
3104 unsigned Opcode = Def->getOpcode();
3105 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3106 Def->getOperand(1).isFI()) {
3107 FI = Def->getOperand(1).getIndex();
3108 Bytes = Flags.getByValSize();
3112 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3113 if (Flags.isByVal())
3114 // ByVal argument is passed in as a pointer but it's now being
3115 // dereferenced. e.g.
3116 // define @foo(%struct.X* %A) {
3117 // tail call @bar(%struct.X* byval %A)
3120 SDValue Ptr = Ld->getBasePtr();
3121 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3124 FI = FINode->getIndex();
3125 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3126 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3127 FI = FINode->getIndex();
3128 Bytes = Flags.getByValSize();
3132 assert(FI != INT_MAX);
3133 if (!MFI->isFixedObjectIndex(FI))
3135 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3138 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3139 /// for tail call optimization. Targets which want to do tail call
3140 /// optimization should implement this function.
3142 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3143 CallingConv::ID CalleeCC,
3145 bool isCalleeStructRet,
3146 bool isCallerStructRet,
3148 const SmallVectorImpl<ISD::OutputArg> &Outs,
3149 const SmallVectorImpl<SDValue> &OutVals,
3150 const SmallVectorImpl<ISD::InputArg> &Ins,
3151 SelectionDAG &DAG) const {
3152 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3155 // If -tailcallopt is specified, make fastcc functions tail-callable.
3156 const MachineFunction &MF = DAG.getMachineFunction();
3157 const Function *CallerF = MF.getFunction();
3159 // If the function return type is x86_fp80 and the callee return type is not,
3160 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3161 // perform a tailcall optimization here.
3162 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3165 CallingConv::ID CallerCC = CallerF->getCallingConv();
3166 bool CCMatch = CallerCC == CalleeCC;
3167 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3168 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3170 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3171 if (IsTailCallConvention(CalleeCC) && CCMatch)
3176 // Look for obvious safe cases to perform tail call optimization that do not
3177 // require ABI changes. This is what gcc calls sibcall.
3179 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3180 // emit a special epilogue.
3181 const X86RegisterInfo *RegInfo =
3182 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3183 if (RegInfo->needsStackRealignment(MF))
3186 // Also avoid sibcall optimization if either caller or callee uses struct
3187 // return semantics.
3188 if (isCalleeStructRet || isCallerStructRet)
3191 // An stdcall/thiscall caller is expected to clean up its arguments; the
3192 // callee isn't going to do that.
3193 // FIXME: this is more restrictive than needed. We could produce a tailcall
3194 // when the stack adjustment matches. For example, with a thiscall that takes
3195 // only one argument.
3196 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3197 CallerCC == CallingConv::X86_ThisCall))
3200 // Do not sibcall optimize vararg calls unless all arguments are passed via
3202 if (isVarArg && !Outs.empty()) {
3204 // Optimizing for varargs on Win64 is unlikely to be safe without
3205 // additional testing.
3206 if (IsCalleeWin64 || IsCallerWin64)
3209 SmallVector<CCValAssign, 16> ArgLocs;
3210 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3211 DAG.getTarget(), ArgLocs, *DAG.getContext());
3213 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3214 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3215 if (!ArgLocs[i].isRegLoc())
3219 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3220 // stack. Therefore, if it's not used by the call it is not safe to optimize
3221 // this into a sibcall.
3222 bool Unused = false;
3223 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3230 SmallVector<CCValAssign, 16> RVLocs;
3231 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3232 DAG.getTarget(), RVLocs, *DAG.getContext());
3233 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3234 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3235 CCValAssign &VA = RVLocs[i];
3236 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3241 // If the calling conventions do not match, then we'd better make sure the
3242 // results are returned in the same way as what the caller expects.
3244 SmallVector<CCValAssign, 16> RVLocs1;
3245 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3246 DAG.getTarget(), RVLocs1, *DAG.getContext());
3247 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3249 SmallVector<CCValAssign, 16> RVLocs2;
3250 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3251 DAG.getTarget(), RVLocs2, *DAG.getContext());
3252 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3254 if (RVLocs1.size() != RVLocs2.size())
3256 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3257 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3259 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3261 if (RVLocs1[i].isRegLoc()) {
3262 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3265 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3271 // If the callee takes no arguments then go on to check the results of the
3273 if (!Outs.empty()) {
3274 // Check if stack adjustment is needed. For now, do not do this if any
3275 // argument is passed on the stack.
3276 SmallVector<CCValAssign, 16> ArgLocs;
3277 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3278 DAG.getTarget(), ArgLocs, *DAG.getContext());
3280 // Allocate shadow area for Win64
3282 CCInfo.AllocateStack(32, 8);
3284 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3285 if (CCInfo.getNextStackOffset()) {
3286 MachineFunction &MF = DAG.getMachineFunction();
3287 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3290 // Check if the arguments are already laid out in the right way as
3291 // the caller's fixed stack objects.
3292 MachineFrameInfo *MFI = MF.getFrameInfo();
3293 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3294 const X86InstrInfo *TII =
3295 static_cast<const X86InstrInfo *>(DAG.getTarget().getInstrInfo());
3296 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3297 CCValAssign &VA = ArgLocs[i];
3298 SDValue Arg = OutVals[i];
3299 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3300 if (VA.getLocInfo() == CCValAssign::Indirect)
3302 if (!VA.isRegLoc()) {
3303 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3310 // If the tailcall address may be in a register, then make sure it's
3311 // possible to register allocate for it. In 32-bit, the call address can
3312 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3313 // callee-saved registers are restored. These happen to be the same
3314 // registers used to pass 'inreg' arguments so watch out for those.
3315 if (!Subtarget->is64Bit() &&
3316 ((!isa<GlobalAddressSDNode>(Callee) &&
3317 !isa<ExternalSymbolSDNode>(Callee)) ||
3318 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3319 unsigned NumInRegs = 0;
3320 // In PIC we need an extra register to formulate the address computation
3322 unsigned MaxInRegs =
3323 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3325 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3326 CCValAssign &VA = ArgLocs[i];
3329 unsigned Reg = VA.getLocReg();
3332 case X86::EAX: case X86::EDX: case X86::ECX:
3333 if (++NumInRegs == MaxInRegs)
3345 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3346 const TargetLibraryInfo *libInfo) const {
3347 return X86::createFastISel(funcInfo, libInfo);
3350 //===----------------------------------------------------------------------===//
3351 // Other Lowering Hooks
3352 //===----------------------------------------------------------------------===//
3354 static bool MayFoldLoad(SDValue Op) {
3355 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3358 static bool MayFoldIntoStore(SDValue Op) {
3359 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3362 static bool isTargetShuffle(unsigned Opcode) {
3364 default: return false;
3365 case X86ISD::PSHUFD:
3366 case X86ISD::PSHUFHW:
3367 case X86ISD::PSHUFLW:
3369 case X86ISD::PALIGNR:
3370 case X86ISD::MOVLHPS:
3371 case X86ISD::MOVLHPD:
3372 case X86ISD::MOVHLPS:
3373 case X86ISD::MOVLPS:
3374 case X86ISD::MOVLPD:
3375 case X86ISD::MOVSHDUP:
3376 case X86ISD::MOVSLDUP:
3377 case X86ISD::MOVDDUP:
3380 case X86ISD::UNPCKL:
3381 case X86ISD::UNPCKH:
3382 case X86ISD::VPERMILP:
3383 case X86ISD::VPERM2X128:
3384 case X86ISD::VPERMI:
3389 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3390 SDValue V1, SelectionDAG &DAG) {
3392 default: llvm_unreachable("Unknown x86 shuffle node");
3393 case X86ISD::MOVSHDUP:
3394 case X86ISD::MOVSLDUP:
3395 case X86ISD::MOVDDUP:
3396 return DAG.getNode(Opc, dl, VT, V1);
3400 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3401 SDValue V1, unsigned TargetMask,
3402 SelectionDAG &DAG) {
3404 default: llvm_unreachable("Unknown x86 shuffle node");
3405 case X86ISD::PSHUFD:
3406 case X86ISD::PSHUFHW:
3407 case X86ISD::PSHUFLW:
3408 case X86ISD::VPERMILP:
3409 case X86ISD::VPERMI:
3410 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3414 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3415 SDValue V1, SDValue V2, unsigned TargetMask,
3416 SelectionDAG &DAG) {
3418 default: llvm_unreachable("Unknown x86 shuffle node");
3419 case X86ISD::PALIGNR:
3421 case X86ISD::VPERM2X128:
3422 return DAG.getNode(Opc, dl, VT, V1, V2,
3423 DAG.getConstant(TargetMask, MVT::i8));
3427 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3428 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3430 default: llvm_unreachable("Unknown x86 shuffle node");
3431 case X86ISD::MOVLHPS:
3432 case X86ISD::MOVLHPD:
3433 case X86ISD::MOVHLPS:
3434 case X86ISD::MOVLPS:
3435 case X86ISD::MOVLPD:
3438 case X86ISD::UNPCKL:
3439 case X86ISD::UNPCKH:
3440 return DAG.getNode(Opc, dl, VT, V1, V2);
3444 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3445 MachineFunction &MF = DAG.getMachineFunction();
3446 const X86RegisterInfo *RegInfo =
3447 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3448 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3449 int ReturnAddrIndex = FuncInfo->getRAIndex();
3451 if (ReturnAddrIndex == 0) {
3452 // Set up a frame object for the return address.
3453 unsigned SlotSize = RegInfo->getSlotSize();
3454 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3457 FuncInfo->setRAIndex(ReturnAddrIndex);
3460 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3463 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3464 bool hasSymbolicDisplacement) {
3465 // Offset should fit into 32 bit immediate field.
3466 if (!isInt<32>(Offset))
3469 // If we don't have a symbolic displacement - we don't have any extra
3471 if (!hasSymbolicDisplacement)
3474 // FIXME: Some tweaks might be needed for medium code model.
3475 if (M != CodeModel::Small && M != CodeModel::Kernel)
3478 // For small code model we assume that latest object is 16MB before end of 31
3479 // bits boundary. We may also accept pretty large negative constants knowing
3480 // that all objects are in the positive half of address space.
3481 if (M == CodeModel::Small && Offset < 16*1024*1024)
3484 // For kernel code model we know that all object resist in the negative half
3485 // of 32bits address space. We may not accept negative offsets, since they may
3486 // be just off and we may accept pretty large positive ones.
3487 if (M == CodeModel::Kernel && Offset > 0)
3493 /// isCalleePop - Determines whether the callee is required to pop its
3494 /// own arguments. Callee pop is necessary to support tail calls.
3495 bool X86::isCalleePop(CallingConv::ID CallingConv,
3496 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3500 switch (CallingConv) {
3503 case CallingConv::X86_StdCall:
3505 case CallingConv::X86_FastCall:
3507 case CallingConv::X86_ThisCall:
3509 case CallingConv::Fast:
3511 case CallingConv::GHC:
3513 case CallingConv::HiPE:
3518 /// \brief Return true if the condition is an unsigned comparison operation.
3519 static bool isX86CCUnsigned(unsigned X86CC) {
3521 default: llvm_unreachable("Invalid integer condition!");
3522 case X86::COND_E: return true;
3523 case X86::COND_G: return false;
3524 case X86::COND_GE: return false;
3525 case X86::COND_L: return false;
3526 case X86::COND_LE: return false;
3527 case X86::COND_NE: return true;
3528 case X86::COND_B: return true;
3529 case X86::COND_A: return true;
3530 case X86::COND_BE: return true;
3531 case X86::COND_AE: return true;
3533 llvm_unreachable("covered switch fell through?!");
3536 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3537 /// specific condition code, returning the condition code and the LHS/RHS of the
3538 /// comparison to make.
3539 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3540 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3542 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3543 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3544 // X > -1 -> X == 0, jump !sign.
3545 RHS = DAG.getConstant(0, RHS.getValueType());
3546 return X86::COND_NS;
3548 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3549 // X < 0 -> X == 0, jump on sign.
3552 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3554 RHS = DAG.getConstant(0, RHS.getValueType());
3555 return X86::COND_LE;
3559 switch (SetCCOpcode) {
3560 default: llvm_unreachable("Invalid integer condition!");
3561 case ISD::SETEQ: return X86::COND_E;
3562 case ISD::SETGT: return X86::COND_G;
3563 case ISD::SETGE: return X86::COND_GE;
3564 case ISD::SETLT: return X86::COND_L;
3565 case ISD::SETLE: return X86::COND_LE;
3566 case ISD::SETNE: return X86::COND_NE;
3567 case ISD::SETULT: return X86::COND_B;
3568 case ISD::SETUGT: return X86::COND_A;
3569 case ISD::SETULE: return X86::COND_BE;
3570 case ISD::SETUGE: return X86::COND_AE;
3574 // First determine if it is required or is profitable to flip the operands.
3576 // If LHS is a foldable load, but RHS is not, flip the condition.
3577 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3578 !ISD::isNON_EXTLoad(RHS.getNode())) {
3579 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3580 std::swap(LHS, RHS);
3583 switch (SetCCOpcode) {
3589 std::swap(LHS, RHS);
3593 // On a floating point condition, the flags are set as follows:
3595 // 0 | 0 | 0 | X > Y
3596 // 0 | 0 | 1 | X < Y
3597 // 1 | 0 | 0 | X == Y
3598 // 1 | 1 | 1 | unordered
3599 switch (SetCCOpcode) {
3600 default: llvm_unreachable("Condcode should be pre-legalized away");
3602 case ISD::SETEQ: return X86::COND_E;
3603 case ISD::SETOLT: // flipped
3605 case ISD::SETGT: return X86::COND_A;
3606 case ISD::SETOLE: // flipped
3608 case ISD::SETGE: return X86::COND_AE;
3609 case ISD::SETUGT: // flipped
3611 case ISD::SETLT: return X86::COND_B;
3612 case ISD::SETUGE: // flipped
3614 case ISD::SETLE: return X86::COND_BE;
3616 case ISD::SETNE: return X86::COND_NE;
3617 case ISD::SETUO: return X86::COND_P;
3618 case ISD::SETO: return X86::COND_NP;
3620 case ISD::SETUNE: return X86::COND_INVALID;
3624 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3625 /// code. Current x86 isa includes the following FP cmov instructions:
3626 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3627 static bool hasFPCMov(unsigned X86CC) {
3643 /// isFPImmLegal - Returns true if the target can instruction select the
3644 /// specified FP immediate natively. If false, the legalizer will
3645 /// materialize the FP immediate as a load from a constant pool.
3646 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3647 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3648 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3654 /// \brief Returns true if it is beneficial to convert a load of a constant
3655 /// to just the constant itself.
3656 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3658 assert(Ty->isIntegerTy());
3660 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3661 if (BitSize == 0 || BitSize > 64)
3666 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3667 /// the specified range (L, H].
3668 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3669 return (Val < 0) || (Val >= Low && Val < Hi);
3672 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3673 /// specified value.
3674 static bool isUndefOrEqual(int Val, int CmpVal) {
3675 return (Val < 0 || Val == CmpVal);
3678 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3679 /// from position Pos and ending in Pos+Size, falls within the specified
3680 /// sequential range (L, L+Pos]. or is undef.
3681 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3682 unsigned Pos, unsigned Size, int Low) {
3683 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3684 if (!isUndefOrEqual(Mask[i], Low))
3689 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3690 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3691 /// the second operand.
3692 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3693 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3694 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3695 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3696 return (Mask[0] < 2 && Mask[1] < 2);
3700 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3701 /// is suitable for input to PSHUFHW.
3702 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3703 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3706 // Lower quadword copied in order or undef.
3707 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3710 // Upper quadword shuffled.
3711 for (unsigned i = 4; i != 8; ++i)
3712 if (!isUndefOrInRange(Mask[i], 4, 8))
3715 if (VT == MVT::v16i16) {
3716 // Lower quadword copied in order or undef.
3717 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3720 // Upper quadword shuffled.
3721 for (unsigned i = 12; i != 16; ++i)
3722 if (!isUndefOrInRange(Mask[i], 12, 16))
3729 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3730 /// is suitable for input to PSHUFLW.
3731 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3732 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3735 // Upper quadword copied in order.
3736 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3739 // Lower quadword shuffled.
3740 for (unsigned i = 0; i != 4; ++i)
3741 if (!isUndefOrInRange(Mask[i], 0, 4))
3744 if (VT == MVT::v16i16) {
3745 // Upper quadword copied in order.
3746 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3749 // Lower quadword shuffled.
3750 for (unsigned i = 8; i != 12; ++i)
3751 if (!isUndefOrInRange(Mask[i], 8, 12))
3758 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3759 /// is suitable for input to PALIGNR.
3760 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3761 const X86Subtarget *Subtarget) {
3762 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3763 (VT.is256BitVector() && !Subtarget->hasInt256()))
3766 unsigned NumElts = VT.getVectorNumElements();
3767 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3768 unsigned NumLaneElts = NumElts/NumLanes;
3770 // Do not handle 64-bit element shuffles with palignr.
3771 if (NumLaneElts == 2)
3774 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3776 for (i = 0; i != NumLaneElts; ++i) {
3781 // Lane is all undef, go to next lane
3782 if (i == NumLaneElts)
3785 int Start = Mask[i+l];
3787 // Make sure its in this lane in one of the sources
3788 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3789 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3792 // If not lane 0, then we must match lane 0
3793 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3796 // Correct second source to be contiguous with first source
3797 if (Start >= (int)NumElts)
3798 Start -= NumElts - NumLaneElts;
3800 // Make sure we're shifting in the right direction.
3801 if (Start <= (int)(i+l))
3806 // Check the rest of the elements to see if they are consecutive.
3807 for (++i; i != NumLaneElts; ++i) {
3808 int Idx = Mask[i+l];
3810 // Make sure its in this lane
3811 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3812 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3815 // If not lane 0, then we must match lane 0
3816 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3819 if (Idx >= (int)NumElts)
3820 Idx -= NumElts - NumLaneElts;
3822 if (!isUndefOrEqual(Idx, Start+i))
3831 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3832 /// the two vector operands have swapped position.
3833 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3834 unsigned NumElems) {
3835 for (unsigned i = 0; i != NumElems; ++i) {
3839 else if (idx < (int)NumElems)
3840 Mask[i] = idx + NumElems;
3842 Mask[i] = idx - NumElems;
3846 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3847 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3848 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3849 /// reverse of what x86 shuffles want.
3850 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3852 unsigned NumElems = VT.getVectorNumElements();
3853 unsigned NumLanes = VT.getSizeInBits()/128;
3854 unsigned NumLaneElems = NumElems/NumLanes;
3856 if (NumLaneElems != 2 && NumLaneElems != 4)
3859 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3860 bool symetricMaskRequired =
3861 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3863 // VSHUFPSY divides the resulting vector into 4 chunks.
3864 // The sources are also splitted into 4 chunks, and each destination
3865 // chunk must come from a different source chunk.
3867 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3868 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3870 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3871 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3873 // VSHUFPDY divides the resulting vector into 4 chunks.
3874 // The sources are also splitted into 4 chunks, and each destination
3875 // chunk must come from a different source chunk.
3877 // SRC1 => X3 X2 X1 X0
3878 // SRC2 => Y3 Y2 Y1 Y0
3880 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3882 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3883 unsigned HalfLaneElems = NumLaneElems/2;
3884 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3885 for (unsigned i = 0; i != NumLaneElems; ++i) {
3886 int Idx = Mask[i+l];
3887 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3888 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3890 // For VSHUFPSY, the mask of the second half must be the same as the
3891 // first but with the appropriate offsets. This works in the same way as
3892 // VPERMILPS works with masks.
3893 if (!symetricMaskRequired || Idx < 0)
3895 if (MaskVal[i] < 0) {
3896 MaskVal[i] = Idx - l;
3899 if ((signed)(Idx - l) != MaskVal[i])
3907 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3908 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3909 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3910 if (!VT.is128BitVector())
3913 unsigned NumElems = VT.getVectorNumElements();
3918 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3919 return isUndefOrEqual(Mask[0], 6) &&
3920 isUndefOrEqual(Mask[1], 7) &&
3921 isUndefOrEqual(Mask[2], 2) &&
3922 isUndefOrEqual(Mask[3], 3);
3925 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3926 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3928 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3929 if (!VT.is128BitVector())
3932 unsigned NumElems = VT.getVectorNumElements();
3937 return isUndefOrEqual(Mask[0], 2) &&
3938 isUndefOrEqual(Mask[1], 3) &&
3939 isUndefOrEqual(Mask[2], 2) &&
3940 isUndefOrEqual(Mask[3], 3);
3943 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3944 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3945 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3946 if (!VT.is128BitVector())
3949 unsigned NumElems = VT.getVectorNumElements();
3951 if (NumElems != 2 && NumElems != 4)
3954 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3955 if (!isUndefOrEqual(Mask[i], i + NumElems))
3958 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3959 if (!isUndefOrEqual(Mask[i], i))
3965 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3966 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3967 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3968 if (!VT.is128BitVector())
3971 unsigned NumElems = VT.getVectorNumElements();
3973 if (NumElems != 2 && NumElems != 4)
3976 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3977 if (!isUndefOrEqual(Mask[i], i))
3980 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3981 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3987 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
3988 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
3989 /// i. e: If all but one element come from the same vector.
3990 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
3991 // TODO: Deal with AVX's VINSERTPS
3992 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
3995 unsigned CorrectPosV1 = 0;
3996 unsigned CorrectPosV2 = 0;
3997 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
3998 if (Mask[i] == -1) {
4006 else if (Mask[i] == i + 4)
4010 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4011 // We have 3 elements (undefs count as elements from any vector) from one
4012 // vector, and one from another.
4019 // Some special combinations that can be optimized.
4022 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4023 SelectionDAG &DAG) {
4024 MVT VT = SVOp->getSimpleValueType(0);
4027 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4030 ArrayRef<int> Mask = SVOp->getMask();
4032 // These are the special masks that may be optimized.
4033 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4034 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4035 bool MatchEvenMask = true;
4036 bool MatchOddMask = true;
4037 for (int i=0; i<8; ++i) {
4038 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4039 MatchEvenMask = false;
4040 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4041 MatchOddMask = false;
4044 if (!MatchEvenMask && !MatchOddMask)
4047 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4049 SDValue Op0 = SVOp->getOperand(0);
4050 SDValue Op1 = SVOp->getOperand(1);
4052 if (MatchEvenMask) {
4053 // Shift the second operand right to 32 bits.
4054 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4055 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4057 // Shift the first operand left to 32 bits.
4058 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4059 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4061 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4062 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4065 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4066 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4067 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4068 bool HasInt256, bool V2IsSplat = false) {
4070 assert(VT.getSizeInBits() >= 128 &&
4071 "Unsupported vector type for unpckl");
4073 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4075 unsigned NumOf256BitLanes;
4076 unsigned NumElts = VT.getVectorNumElements();
4077 if (VT.is256BitVector()) {
4078 if (NumElts != 4 && NumElts != 8 &&
4079 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4082 NumOf256BitLanes = 1;
4083 } else if (VT.is512BitVector()) {
4084 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4085 "Unsupported vector type for unpckh");
4087 NumOf256BitLanes = 2;
4090 NumOf256BitLanes = 1;
4093 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4094 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4096 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4097 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4098 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4099 int BitI = Mask[l256*NumEltsInStride+l+i];
4100 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4101 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4103 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4105 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4113 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4114 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4115 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4116 bool HasInt256, bool V2IsSplat = false) {
4117 assert(VT.getSizeInBits() >= 128 &&
4118 "Unsupported vector type for unpckh");
4120 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4122 unsigned NumOf256BitLanes;
4123 unsigned NumElts = VT.getVectorNumElements();
4124 if (VT.is256BitVector()) {
4125 if (NumElts != 4 && NumElts != 8 &&
4126 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4129 NumOf256BitLanes = 1;
4130 } else if (VT.is512BitVector()) {
4131 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4132 "Unsupported vector type for unpckh");
4134 NumOf256BitLanes = 2;
4137 NumOf256BitLanes = 1;
4140 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4141 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4143 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4144 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4145 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4146 int BitI = Mask[l256*NumEltsInStride+l+i];
4147 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4148 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4150 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4152 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4160 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4161 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4163 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4164 unsigned NumElts = VT.getVectorNumElements();
4165 bool Is256BitVec = VT.is256BitVector();
4167 if (VT.is512BitVector())
4169 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4170 "Unsupported vector type for unpckh");
4172 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4173 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4176 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4177 // FIXME: Need a better way to get rid of this, there's no latency difference
4178 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4179 // the former later. We should also remove the "_undef" special mask.
4180 if (NumElts == 4 && Is256BitVec)
4183 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4184 // independently on 128-bit lanes.
4185 unsigned NumLanes = VT.getSizeInBits()/128;
4186 unsigned NumLaneElts = NumElts/NumLanes;
4188 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4189 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4190 int BitI = Mask[l+i];
4191 int BitI1 = Mask[l+i+1];
4193 if (!isUndefOrEqual(BitI, j))
4195 if (!isUndefOrEqual(BitI1, j))
4203 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4204 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4206 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4207 unsigned NumElts = VT.getVectorNumElements();
4209 if (VT.is512BitVector())
4212 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4213 "Unsupported vector type for unpckh");
4215 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4216 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4219 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4220 // independently on 128-bit lanes.
4221 unsigned NumLanes = VT.getSizeInBits()/128;
4222 unsigned NumLaneElts = NumElts/NumLanes;
4224 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4225 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4226 int BitI = Mask[l+i];
4227 int BitI1 = Mask[l+i+1];
4228 if (!isUndefOrEqual(BitI, j))
4230 if (!isUndefOrEqual(BitI1, j))
4237 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4238 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4239 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4240 if (!VT.is512BitVector())
4243 unsigned NumElts = VT.getVectorNumElements();
4244 unsigned HalfSize = NumElts/2;
4245 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4246 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4251 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4252 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4260 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4262 /// MOVSD, and MOVD, i.e. setting the lowest element.
4263 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4264 if (VT.getVectorElementType().getSizeInBits() < 32)
4266 if (!VT.is128BitVector())
4269 unsigned NumElts = VT.getVectorNumElements();
4271 if (!isUndefOrEqual(Mask[0], NumElts))
4274 for (unsigned i = 1; i != NumElts; ++i)
4275 if (!isUndefOrEqual(Mask[i], i))
4281 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4282 /// as permutations between 128-bit chunks or halves. As an example: this
4284 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4285 /// The first half comes from the second half of V1 and the second half from the
4286 /// the second half of V2.
4287 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4288 if (!HasFp256 || !VT.is256BitVector())
4291 // The shuffle result is divided into half A and half B. In total the two
4292 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4293 // B must come from C, D, E or F.
4294 unsigned HalfSize = VT.getVectorNumElements()/2;
4295 bool MatchA = false, MatchB = false;
4297 // Check if A comes from one of C, D, E, F.
4298 for (unsigned Half = 0; Half != 4; ++Half) {
4299 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4305 // Check if B comes from one of C, D, E, F.
4306 for (unsigned Half = 0; Half != 4; ++Half) {
4307 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4313 return MatchA && MatchB;
4316 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4317 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4318 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4319 MVT VT = SVOp->getSimpleValueType(0);
4321 unsigned HalfSize = VT.getVectorNumElements()/2;
4323 unsigned FstHalf = 0, SndHalf = 0;
4324 for (unsigned i = 0; i < HalfSize; ++i) {
4325 if (SVOp->getMaskElt(i) > 0) {
4326 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4330 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4331 if (SVOp->getMaskElt(i) > 0) {
4332 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4337 return (FstHalf | (SndHalf << 4));
4340 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4341 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4342 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4346 unsigned NumElts = VT.getVectorNumElements();
4348 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4349 for (unsigned i = 0; i != NumElts; ++i) {
4352 Imm8 |= Mask[i] << (i*2);
4357 unsigned LaneSize = 4;
4358 SmallVector<int, 4> MaskVal(LaneSize, -1);
4360 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4361 for (unsigned i = 0; i != LaneSize; ++i) {
4362 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4366 if (MaskVal[i] < 0) {
4367 MaskVal[i] = Mask[i+l] - l;
4368 Imm8 |= MaskVal[i] << (i*2);
4371 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4378 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4379 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4380 /// Note that VPERMIL mask matching is different depending whether theunderlying
4381 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4382 /// to the same elements of the low, but to the higher half of the source.
4383 /// In VPERMILPD the two lanes could be shuffled independently of each other
4384 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4385 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4386 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4387 if (VT.getSizeInBits() < 256 || EltSize < 32)
4389 bool symetricMaskRequired = (EltSize == 32);
4390 unsigned NumElts = VT.getVectorNumElements();
4392 unsigned NumLanes = VT.getSizeInBits()/128;
4393 unsigned LaneSize = NumElts/NumLanes;
4394 // 2 or 4 elements in one lane
4396 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4397 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4398 for (unsigned i = 0; i != LaneSize; ++i) {
4399 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4401 if (symetricMaskRequired) {
4402 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4403 ExpectedMaskVal[i] = Mask[i+l] - l;
4406 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4414 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4415 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4416 /// element of vector 2 and the other elements to come from vector 1 in order.
4417 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4418 bool V2IsSplat = false, bool V2IsUndef = false) {
4419 if (!VT.is128BitVector())
4422 unsigned NumOps = VT.getVectorNumElements();
4423 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4426 if (!isUndefOrEqual(Mask[0], 0))
4429 for (unsigned i = 1; i != NumOps; ++i)
4430 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4431 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4432 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4438 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4439 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4440 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4441 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4442 const X86Subtarget *Subtarget) {
4443 if (!Subtarget->hasSSE3())
4446 unsigned NumElems = VT.getVectorNumElements();
4448 if ((VT.is128BitVector() && NumElems != 4) ||
4449 (VT.is256BitVector() && NumElems != 8) ||
4450 (VT.is512BitVector() && NumElems != 16))
4453 // "i+1" is the value the indexed mask element must have
4454 for (unsigned i = 0; i != NumElems; i += 2)
4455 if (!isUndefOrEqual(Mask[i], i+1) ||
4456 !isUndefOrEqual(Mask[i+1], i+1))
4462 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4463 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4464 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4465 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4466 const X86Subtarget *Subtarget) {
4467 if (!Subtarget->hasSSE3())
4470 unsigned NumElems = VT.getVectorNumElements();
4472 if ((VT.is128BitVector() && NumElems != 4) ||
4473 (VT.is256BitVector() && NumElems != 8) ||
4474 (VT.is512BitVector() && NumElems != 16))
4477 // "i" is the value the indexed mask element must have
4478 for (unsigned i = 0; i != NumElems; i += 2)
4479 if (!isUndefOrEqual(Mask[i], i) ||
4480 !isUndefOrEqual(Mask[i+1], i))
4486 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4487 /// specifies a shuffle of elements that is suitable for input to 256-bit
4488 /// version of MOVDDUP.
4489 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4490 if (!HasFp256 || !VT.is256BitVector())
4493 unsigned NumElts = VT.getVectorNumElements();
4497 for (unsigned i = 0; i != NumElts/2; ++i)
4498 if (!isUndefOrEqual(Mask[i], 0))
4500 for (unsigned i = NumElts/2; i != NumElts; ++i)
4501 if (!isUndefOrEqual(Mask[i], NumElts/2))
4506 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4507 /// specifies a shuffle of elements that is suitable for input to 128-bit
4508 /// version of MOVDDUP.
4509 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4510 if (!VT.is128BitVector())
4513 unsigned e = VT.getVectorNumElements() / 2;
4514 for (unsigned i = 0; i != e; ++i)
4515 if (!isUndefOrEqual(Mask[i], i))
4517 for (unsigned i = 0; i != e; ++i)
4518 if (!isUndefOrEqual(Mask[e+i], i))
4523 /// isVEXTRACTIndex - Return true if the specified
4524 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4525 /// suitable for instruction that extract 128 or 256 bit vectors
4526 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4527 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4528 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4531 // The index should be aligned on a vecWidth-bit boundary.
4533 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4535 MVT VT = N->getSimpleValueType(0);
4536 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4537 bool Result = (Index * ElSize) % vecWidth == 0;
4542 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4543 /// operand specifies a subvector insert that is suitable for input to
4544 /// insertion of 128 or 256-bit subvectors
4545 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4546 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4547 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4549 // The index should be aligned on a vecWidth-bit boundary.
4551 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4553 MVT VT = N->getSimpleValueType(0);
4554 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4555 bool Result = (Index * ElSize) % vecWidth == 0;
4560 bool X86::isVINSERT128Index(SDNode *N) {
4561 return isVINSERTIndex(N, 128);
4564 bool X86::isVINSERT256Index(SDNode *N) {
4565 return isVINSERTIndex(N, 256);
4568 bool X86::isVEXTRACT128Index(SDNode *N) {
4569 return isVEXTRACTIndex(N, 128);
4572 bool X86::isVEXTRACT256Index(SDNode *N) {
4573 return isVEXTRACTIndex(N, 256);
4576 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4577 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4578 /// Handles 128-bit and 256-bit.
4579 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4580 MVT VT = N->getSimpleValueType(0);
4582 assert((VT.getSizeInBits() >= 128) &&
4583 "Unsupported vector type for PSHUF/SHUFP");
4585 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4586 // independently on 128-bit lanes.
4587 unsigned NumElts = VT.getVectorNumElements();
4588 unsigned NumLanes = VT.getSizeInBits()/128;
4589 unsigned NumLaneElts = NumElts/NumLanes;
4591 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4592 "Only supports 2, 4 or 8 elements per lane");
4594 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4596 for (unsigned i = 0; i != NumElts; ++i) {
4597 int Elt = N->getMaskElt(i);
4598 if (Elt < 0) continue;
4599 Elt &= NumLaneElts - 1;
4600 unsigned ShAmt = (i << Shift) % 8;
4601 Mask |= Elt << ShAmt;
4607 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4608 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4609 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4610 MVT VT = N->getSimpleValueType(0);
4612 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4613 "Unsupported vector type for PSHUFHW");
4615 unsigned NumElts = VT.getVectorNumElements();
4618 for (unsigned l = 0; l != NumElts; l += 8) {
4619 // 8 nodes per lane, but we only care about the last 4.
4620 for (unsigned i = 0; i < 4; ++i) {
4621 int Elt = N->getMaskElt(l+i+4);
4622 if (Elt < 0) continue;
4623 Elt &= 0x3; // only 2-bits.
4624 Mask |= Elt << (i * 2);
4631 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4632 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4633 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4634 MVT VT = N->getSimpleValueType(0);
4636 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4637 "Unsupported vector type for PSHUFHW");
4639 unsigned NumElts = VT.getVectorNumElements();
4642 for (unsigned l = 0; l != NumElts; l += 8) {
4643 // 8 nodes per lane, but we only care about the first 4.
4644 for (unsigned i = 0; i < 4; ++i) {
4645 int Elt = N->getMaskElt(l+i);
4646 if (Elt < 0) continue;
4647 Elt &= 0x3; // only 2-bits
4648 Mask |= Elt << (i * 2);
4655 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4656 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4657 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4658 MVT VT = SVOp->getSimpleValueType(0);
4659 unsigned EltSize = VT.is512BitVector() ? 1 :
4660 VT.getVectorElementType().getSizeInBits() >> 3;
4662 unsigned NumElts = VT.getVectorNumElements();
4663 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4664 unsigned NumLaneElts = NumElts/NumLanes;
4668 for (i = 0; i != NumElts; ++i) {
4669 Val = SVOp->getMaskElt(i);
4673 if (Val >= (int)NumElts)
4674 Val -= NumElts - NumLaneElts;
4676 assert(Val - i > 0 && "PALIGNR imm should be positive");
4677 return (Val - i) * EltSize;
4680 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4681 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4682 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4683 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4686 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4688 MVT VecVT = N->getOperand(0).getSimpleValueType();
4689 MVT ElVT = VecVT.getVectorElementType();
4691 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4692 return Index / NumElemsPerChunk;
4695 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4696 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4697 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4698 llvm_unreachable("Illegal insert subvector for VINSERT");
4701 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4703 MVT VecVT = N->getSimpleValueType(0);
4704 MVT ElVT = VecVT.getVectorElementType();
4706 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4707 return Index / NumElemsPerChunk;
4710 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4711 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4712 /// and VINSERTI128 instructions.
4713 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4714 return getExtractVEXTRACTImmediate(N, 128);
4717 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4718 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4719 /// and VINSERTI64x4 instructions.
4720 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4721 return getExtractVEXTRACTImmediate(N, 256);
4724 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4725 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4726 /// and VINSERTI128 instructions.
4727 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4728 return getInsertVINSERTImmediate(N, 128);
4731 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4732 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4733 /// and VINSERTI64x4 instructions.
4734 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4735 return getInsertVINSERTImmediate(N, 256);
4738 /// isZero - Returns true if Elt is a constant integer zero
4739 static bool isZero(SDValue V) {
4740 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4741 return C && C->isNullValue();
4744 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4746 bool X86::isZeroNode(SDValue Elt) {
4749 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4750 return CFP->getValueAPF().isPosZero();
4754 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4755 /// their permute mask.
4756 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4757 SelectionDAG &DAG) {
4758 MVT VT = SVOp->getSimpleValueType(0);
4759 unsigned NumElems = VT.getVectorNumElements();
4760 SmallVector<int, 8> MaskVec;
4762 for (unsigned i = 0; i != NumElems; ++i) {
4763 int Idx = SVOp->getMaskElt(i);
4765 if (Idx < (int)NumElems)
4770 MaskVec.push_back(Idx);
4772 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4773 SVOp->getOperand(0), &MaskVec[0]);
4776 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4777 /// match movhlps. The lower half elements should come from upper half of
4778 /// V1 (and in order), and the upper half elements should come from the upper
4779 /// half of V2 (and in order).
4780 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4781 if (!VT.is128BitVector())
4783 if (VT.getVectorNumElements() != 4)
4785 for (unsigned i = 0, e = 2; i != e; ++i)
4786 if (!isUndefOrEqual(Mask[i], i+2))
4788 for (unsigned i = 2; i != 4; ++i)
4789 if (!isUndefOrEqual(Mask[i], i+4))
4794 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4795 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4797 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4798 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4800 N = N->getOperand(0).getNode();
4801 if (!ISD::isNON_EXTLoad(N))
4804 *LD = cast<LoadSDNode>(N);
4808 // Test whether the given value is a vector value which will be legalized
4810 static bool WillBeConstantPoolLoad(SDNode *N) {
4811 if (N->getOpcode() != ISD::BUILD_VECTOR)
4814 // Check for any non-constant elements.
4815 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4816 switch (N->getOperand(i).getNode()->getOpcode()) {
4818 case ISD::ConstantFP:
4825 // Vectors of all-zeros and all-ones are materialized with special
4826 // instructions rather than being loaded.
4827 return !ISD::isBuildVectorAllZeros(N) &&
4828 !ISD::isBuildVectorAllOnes(N);
4831 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4832 /// match movlp{s|d}. The lower half elements should come from lower half of
4833 /// V1 (and in order), and the upper half elements should come from the upper
4834 /// half of V2 (and in order). And since V1 will become the source of the
4835 /// MOVLP, it must be either a vector load or a scalar load to vector.
4836 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4837 ArrayRef<int> Mask, MVT VT) {
4838 if (!VT.is128BitVector())
4841 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4843 // Is V2 is a vector load, don't do this transformation. We will try to use
4844 // load folding shufps op.
4845 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4848 unsigned NumElems = VT.getVectorNumElements();
4850 if (NumElems != 2 && NumElems != 4)
4852 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4853 if (!isUndefOrEqual(Mask[i], i))
4855 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4856 if (!isUndefOrEqual(Mask[i], i+NumElems))
4861 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4862 /// to an zero vector.
4863 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4864 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4865 SDValue V1 = N->getOperand(0);
4866 SDValue V2 = N->getOperand(1);
4867 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4868 for (unsigned i = 0; i != NumElems; ++i) {
4869 int Idx = N->getMaskElt(i);
4870 if (Idx >= (int)NumElems) {
4871 unsigned Opc = V2.getOpcode();
4872 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4874 if (Opc != ISD::BUILD_VECTOR ||
4875 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4877 } else if (Idx >= 0) {
4878 unsigned Opc = V1.getOpcode();
4879 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4881 if (Opc != ISD::BUILD_VECTOR ||
4882 !X86::isZeroNode(V1.getOperand(Idx)))
4889 /// getZeroVector - Returns a vector of specified type with all zero elements.
4891 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4892 SelectionDAG &DAG, SDLoc dl) {
4893 assert(VT.isVector() && "Expected a vector type");
4895 // Always build SSE zero vectors as <4 x i32> bitcasted
4896 // to their dest type. This ensures they get CSE'd.
4898 if (VT.is128BitVector()) { // SSE
4899 if (Subtarget->hasSSE2()) { // SSE2
4900 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4901 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4903 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4904 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4906 } else if (VT.is256BitVector()) { // AVX
4907 if (Subtarget->hasInt256()) { // AVX2
4908 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4909 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4910 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4912 // 256-bit logic and arithmetic instructions in AVX are all
4913 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4914 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4915 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4916 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4918 } else if (VT.is512BitVector()) { // AVX-512
4919 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4920 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4921 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4922 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4923 } else if (VT.getScalarType() == MVT::i1) {
4924 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4925 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4926 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4927 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4929 llvm_unreachable("Unexpected vector type");
4931 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4934 /// getOnesVector - Returns a vector of specified type with all bits set.
4935 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4936 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4937 /// Then bitcast to their original type, ensuring they get CSE'd.
4938 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4940 assert(VT.isVector() && "Expected a vector type");
4942 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4944 if (VT.is256BitVector()) {
4945 if (HasInt256) { // AVX2
4946 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4947 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4949 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4950 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4952 } else if (VT.is128BitVector()) {
4953 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4955 llvm_unreachable("Unexpected vector type");
4957 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4960 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4961 /// that point to V2 points to its first element.
4962 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4963 for (unsigned i = 0; i != NumElems; ++i) {
4964 if (Mask[i] > (int)NumElems) {
4970 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4971 /// operation of specified width.
4972 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4974 unsigned NumElems = VT.getVectorNumElements();
4975 SmallVector<int, 8> Mask;
4976 Mask.push_back(NumElems);
4977 for (unsigned i = 1; i != NumElems; ++i)
4979 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4982 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4983 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4985 unsigned NumElems = VT.getVectorNumElements();
4986 SmallVector<int, 8> Mask;
4987 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4989 Mask.push_back(i + NumElems);
4991 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4994 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4995 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4997 unsigned NumElems = VT.getVectorNumElements();
4998 SmallVector<int, 8> Mask;
4999 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5000 Mask.push_back(i + Half);
5001 Mask.push_back(i + NumElems + Half);
5003 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5006 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5007 // a generic shuffle instruction because the target has no such instructions.
5008 // Generate shuffles which repeat i16 and i8 several times until they can be
5009 // represented by v4f32 and then be manipulated by target suported shuffles.
5010 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5011 MVT VT = V.getSimpleValueType();
5012 int NumElems = VT.getVectorNumElements();
5015 while (NumElems > 4) {
5016 if (EltNo < NumElems/2) {
5017 V = getUnpackl(DAG, dl, VT, V, V);
5019 V = getUnpackh(DAG, dl, VT, V, V);
5020 EltNo -= NumElems/2;
5027 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5028 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5029 MVT VT = V.getSimpleValueType();
5032 if (VT.is128BitVector()) {
5033 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5034 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5035 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5037 } else if (VT.is256BitVector()) {
5038 // To use VPERMILPS to splat scalars, the second half of indicies must
5039 // refer to the higher part, which is a duplication of the lower one,
5040 // because VPERMILPS can only handle in-lane permutations.
5041 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5042 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5044 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5045 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5048 llvm_unreachable("Vector size not supported");
5050 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5053 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5054 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5055 MVT SrcVT = SV->getSimpleValueType(0);
5056 SDValue V1 = SV->getOperand(0);
5059 int EltNo = SV->getSplatIndex();
5060 int NumElems = SrcVT.getVectorNumElements();
5061 bool Is256BitVec = SrcVT.is256BitVector();
5063 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5064 "Unknown how to promote splat for type");
5066 // Extract the 128-bit part containing the splat element and update
5067 // the splat element index when it refers to the higher register.
5069 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5070 if (EltNo >= NumElems/2)
5071 EltNo -= NumElems/2;
5074 // All i16 and i8 vector types can't be used directly by a generic shuffle
5075 // instruction because the target has no such instruction. Generate shuffles
5076 // which repeat i16 and i8 several times until they fit in i32, and then can
5077 // be manipulated by target suported shuffles.
5078 MVT EltVT = SrcVT.getVectorElementType();
5079 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5080 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5082 // Recreate the 256-bit vector and place the same 128-bit vector
5083 // into the low and high part. This is necessary because we want
5084 // to use VPERM* to shuffle the vectors
5086 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5089 return getLegalSplat(DAG, V1, EltNo);
5092 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5093 /// vector of zero or undef vector. This produces a shuffle where the low
5094 /// element of V2 is swizzled into the zero/undef vector, landing at element
5095 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5096 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5098 const X86Subtarget *Subtarget,
5099 SelectionDAG &DAG) {
5100 MVT VT = V2.getSimpleValueType();
5102 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5103 unsigned NumElems = VT.getVectorNumElements();
5104 SmallVector<int, 16> MaskVec;
5105 for (unsigned i = 0; i != NumElems; ++i)
5106 // If this is the insertion idx, put the low elt of V2 here.
5107 MaskVec.push_back(i == Idx ? NumElems : i);
5108 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5111 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5112 /// target specific opcode. Returns true if the Mask could be calculated.
5113 /// Sets IsUnary to true if only uses one source.
5114 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5115 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5116 unsigned NumElems = VT.getVectorNumElements();
5120 switch(N->getOpcode()) {
5122 ImmN = N->getOperand(N->getNumOperands()-1);
5123 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5125 case X86ISD::UNPCKH:
5126 DecodeUNPCKHMask(VT, Mask);
5128 case X86ISD::UNPCKL:
5129 DecodeUNPCKLMask(VT, Mask);
5131 case X86ISD::MOVHLPS:
5132 DecodeMOVHLPSMask(NumElems, Mask);
5134 case X86ISD::MOVLHPS:
5135 DecodeMOVLHPSMask(NumElems, Mask);
5137 case X86ISD::PALIGNR:
5138 ImmN = N->getOperand(N->getNumOperands()-1);
5139 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5141 case X86ISD::PSHUFD:
5142 case X86ISD::VPERMILP:
5143 ImmN = N->getOperand(N->getNumOperands()-1);
5144 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5147 case X86ISD::PSHUFHW:
5148 ImmN = N->getOperand(N->getNumOperands()-1);
5149 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5152 case X86ISD::PSHUFLW:
5153 ImmN = N->getOperand(N->getNumOperands()-1);
5154 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5157 case X86ISD::VPERMI:
5158 ImmN = N->getOperand(N->getNumOperands()-1);
5159 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5163 case X86ISD::MOVSD: {
5164 // The index 0 always comes from the first element of the second source,
5165 // this is why MOVSS and MOVSD are used in the first place. The other
5166 // elements come from the other positions of the first source vector
5167 Mask.push_back(NumElems);
5168 for (unsigned i = 1; i != NumElems; ++i) {
5173 case X86ISD::VPERM2X128:
5174 ImmN = N->getOperand(N->getNumOperands()-1);
5175 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5176 if (Mask.empty()) return false;
5178 case X86ISD::MOVDDUP:
5179 case X86ISD::MOVLHPD:
5180 case X86ISD::MOVLPD:
5181 case X86ISD::MOVLPS:
5182 case X86ISD::MOVSHDUP:
5183 case X86ISD::MOVSLDUP:
5184 // Not yet implemented
5186 default: llvm_unreachable("unknown target shuffle node");
5192 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5193 /// element of the result of the vector shuffle.
5194 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5197 return SDValue(); // Limit search depth.
5199 SDValue V = SDValue(N, 0);
5200 EVT VT = V.getValueType();
5201 unsigned Opcode = V.getOpcode();
5203 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5204 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5205 int Elt = SV->getMaskElt(Index);
5208 return DAG.getUNDEF(VT.getVectorElementType());
5210 unsigned NumElems = VT.getVectorNumElements();
5211 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5212 : SV->getOperand(1);
5213 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5216 // Recurse into target specific vector shuffles to find scalars.
5217 if (isTargetShuffle(Opcode)) {
5218 MVT ShufVT = V.getSimpleValueType();
5219 unsigned NumElems = ShufVT.getVectorNumElements();
5220 SmallVector<int, 16> ShuffleMask;
5223 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5226 int Elt = ShuffleMask[Index];
5228 return DAG.getUNDEF(ShufVT.getVectorElementType());
5230 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5232 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5236 // Actual nodes that may contain scalar elements
5237 if (Opcode == ISD::BITCAST) {
5238 V = V.getOperand(0);
5239 EVT SrcVT = V.getValueType();
5240 unsigned NumElems = VT.getVectorNumElements();
5242 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5246 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5247 return (Index == 0) ? V.getOperand(0)
5248 : DAG.getUNDEF(VT.getVectorElementType());
5250 if (V.getOpcode() == ISD::BUILD_VECTOR)
5251 return V.getOperand(Index);
5256 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5257 /// shuffle operation which come from a consecutively from a zero. The
5258 /// search can start in two different directions, from left or right.
5259 /// We count undefs as zeros until PreferredNum is reached.
5260 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5261 unsigned NumElems, bool ZerosFromLeft,
5263 unsigned PreferredNum = -1U) {
5264 unsigned NumZeros = 0;
5265 for (unsigned i = 0; i != NumElems; ++i) {
5266 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5267 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5271 if (X86::isZeroNode(Elt))
5273 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5274 NumZeros = std::min(NumZeros + 1, PreferredNum);
5282 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5283 /// correspond consecutively to elements from one of the vector operands,
5284 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5286 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5287 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5288 unsigned NumElems, unsigned &OpNum) {
5289 bool SeenV1 = false;
5290 bool SeenV2 = false;
5292 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5293 int Idx = SVOp->getMaskElt(i);
5294 // Ignore undef indicies
5298 if (Idx < (int)NumElems)
5303 // Only accept consecutive elements from the same vector
5304 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5308 OpNum = SeenV1 ? 0 : 1;
5312 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5313 /// logical left shift of a vector.
5314 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5315 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5317 SVOp->getSimpleValueType(0).getVectorNumElements();
5318 unsigned NumZeros = getNumOfConsecutiveZeros(
5319 SVOp, NumElems, false /* check zeros from right */, DAG,
5320 SVOp->getMaskElt(0));
5326 // Considering the elements in the mask that are not consecutive zeros,
5327 // check if they consecutively come from only one of the source vectors.
5329 // V1 = {X, A, B, C} 0
5331 // vector_shuffle V1, V2 <1, 2, 3, X>
5333 if (!isShuffleMaskConsecutive(SVOp,
5334 0, // Mask Start Index
5335 NumElems-NumZeros, // Mask End Index(exclusive)
5336 NumZeros, // Where to start looking in the src vector
5337 NumElems, // Number of elements in vector
5338 OpSrc)) // Which source operand ?
5343 ShVal = SVOp->getOperand(OpSrc);
5347 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5348 /// logical left shift of a vector.
5349 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5350 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5352 SVOp->getSimpleValueType(0).getVectorNumElements();
5353 unsigned NumZeros = getNumOfConsecutiveZeros(
5354 SVOp, NumElems, true /* check zeros from left */, DAG,
5355 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5361 // Considering the elements in the mask that are not consecutive zeros,
5362 // check if they consecutively come from only one of the source vectors.
5364 // 0 { A, B, X, X } = V2
5366 // vector_shuffle V1, V2 <X, X, 4, 5>
5368 if (!isShuffleMaskConsecutive(SVOp,
5369 NumZeros, // Mask Start Index
5370 NumElems, // Mask End Index(exclusive)
5371 0, // Where to start looking in the src vector
5372 NumElems, // Number of elements in vector
5373 OpSrc)) // Which source operand ?
5378 ShVal = SVOp->getOperand(OpSrc);
5382 /// isVectorShift - Returns true if the shuffle can be implemented as a
5383 /// logical left or right shift of a vector.
5384 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5385 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5386 // Although the logic below support any bitwidth size, there are no
5387 // shift instructions which handle more than 128-bit vectors.
5388 if (!SVOp->getSimpleValueType(0).is128BitVector())
5391 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5392 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5398 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5400 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5401 unsigned NumNonZero, unsigned NumZero,
5403 const X86Subtarget* Subtarget,
5404 const TargetLowering &TLI) {
5411 for (unsigned i = 0; i < 16; ++i) {
5412 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5413 if (ThisIsNonZero && First) {
5415 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5417 V = DAG.getUNDEF(MVT::v8i16);
5422 SDValue ThisElt, LastElt;
5423 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5424 if (LastIsNonZero) {
5425 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5426 MVT::i16, Op.getOperand(i-1));
5428 if (ThisIsNonZero) {
5429 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5430 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5431 ThisElt, DAG.getConstant(8, MVT::i8));
5433 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5437 if (ThisElt.getNode())
5438 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5439 DAG.getIntPtrConstant(i/2));
5443 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5446 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5448 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5449 unsigned NumNonZero, unsigned NumZero,
5451 const X86Subtarget* Subtarget,
5452 const TargetLowering &TLI) {
5459 for (unsigned i = 0; i < 8; ++i) {
5460 bool isNonZero = (NonZeros & (1 << i)) != 0;
5464 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5466 V = DAG.getUNDEF(MVT::v8i16);
5469 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5470 MVT::v8i16, V, Op.getOperand(i),
5471 DAG.getIntPtrConstant(i));
5478 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5479 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5480 unsigned NonZeros, unsigned NumNonZero,
5481 unsigned NumZero, SelectionDAG &DAG,
5482 const X86Subtarget *Subtarget,
5483 const TargetLowering &TLI) {
5484 // We know there's at least one non-zero element
5485 unsigned FirstNonZeroIdx = 0;
5486 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5487 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5488 X86::isZeroNode(FirstNonZero)) {
5490 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5493 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5494 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5497 SDValue V = FirstNonZero.getOperand(0);
5498 MVT VVT = V.getSimpleValueType();
5499 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5502 unsigned FirstNonZeroDst =
5503 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5504 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5505 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5506 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5508 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5509 SDValue Elem = Op.getOperand(Idx);
5510 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5513 // TODO: What else can be here? Deal with it.
5514 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5517 // TODO: Some optimizations are still possible here
5518 // ex: Getting one element from a vector, and the rest from another.
5519 if (Elem.getOperand(0) != V)
5522 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5525 else if (IncorrectIdx == -1U) {
5529 // There was already one element with an incorrect index.
5530 // We can't optimize this case to an insertps.
5534 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5536 EVT VT = Op.getSimpleValueType();
5537 unsigned ElementMoveMask = 0;
5538 if (IncorrectIdx == -1U)
5539 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5541 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5543 SDValue InsertpsMask =
5544 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5545 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5551 /// getVShift - Return a vector logical shift node.
5553 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5554 unsigned NumBits, SelectionDAG &DAG,
5555 const TargetLowering &TLI, SDLoc dl) {
5556 assert(VT.is128BitVector() && "Unknown type for VShift");
5557 EVT ShVT = MVT::v2i64;
5558 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5559 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5560 return DAG.getNode(ISD::BITCAST, dl, VT,
5561 DAG.getNode(Opc, dl, ShVT, SrcOp,
5562 DAG.getConstant(NumBits,
5563 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5567 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5569 // Check if the scalar load can be widened into a vector load. And if
5570 // the address is "base + cst" see if the cst can be "absorbed" into
5571 // the shuffle mask.
5572 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5573 SDValue Ptr = LD->getBasePtr();
5574 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5576 EVT PVT = LD->getValueType(0);
5577 if (PVT != MVT::i32 && PVT != MVT::f32)
5582 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5583 FI = FINode->getIndex();
5585 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5586 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5587 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5588 Offset = Ptr.getConstantOperandVal(1);
5589 Ptr = Ptr.getOperand(0);
5594 // FIXME: 256-bit vector instructions don't require a strict alignment,
5595 // improve this code to support it better.
5596 unsigned RequiredAlign = VT.getSizeInBits()/8;
5597 SDValue Chain = LD->getChain();
5598 // Make sure the stack object alignment is at least 16 or 32.
5599 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5600 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5601 if (MFI->isFixedObjectIndex(FI)) {
5602 // Can't change the alignment. FIXME: It's possible to compute
5603 // the exact stack offset and reference FI + adjust offset instead.
5604 // If someone *really* cares about this. That's the way to implement it.
5607 MFI->setObjectAlignment(FI, RequiredAlign);
5611 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5612 // Ptr + (Offset & ~15).
5615 if ((Offset % RequiredAlign) & 3)
5617 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5619 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5620 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5622 int EltNo = (Offset - StartOffset) >> 2;
5623 unsigned NumElems = VT.getVectorNumElements();
5625 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5626 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5627 LD->getPointerInfo().getWithOffset(StartOffset),
5628 false, false, false, 0);
5630 SmallVector<int, 8> Mask;
5631 for (unsigned i = 0; i != NumElems; ++i)
5632 Mask.push_back(EltNo);
5634 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5640 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5641 /// vector of type 'VT', see if the elements can be replaced by a single large
5642 /// load which has the same value as a build_vector whose operands are 'elts'.
5644 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5646 /// FIXME: we'd also like to handle the case where the last elements are zero
5647 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5648 /// There's even a handy isZeroNode for that purpose.
5649 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5650 SDLoc &DL, SelectionDAG &DAG,
5651 bool isAfterLegalize) {
5652 EVT EltVT = VT.getVectorElementType();
5653 unsigned NumElems = Elts.size();
5655 LoadSDNode *LDBase = nullptr;
5656 unsigned LastLoadedElt = -1U;
5658 // For each element in the initializer, see if we've found a load or an undef.
5659 // If we don't find an initial load element, or later load elements are
5660 // non-consecutive, bail out.
5661 for (unsigned i = 0; i < NumElems; ++i) {
5662 SDValue Elt = Elts[i];
5664 if (!Elt.getNode() ||
5665 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5668 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5670 LDBase = cast<LoadSDNode>(Elt.getNode());
5674 if (Elt.getOpcode() == ISD::UNDEF)
5677 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5678 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5683 // If we have found an entire vector of loads and undefs, then return a large
5684 // load of the entire vector width starting at the base pointer. If we found
5685 // consecutive loads for the low half, generate a vzext_load node.
5686 if (LastLoadedElt == NumElems - 1) {
5688 if (isAfterLegalize &&
5689 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5692 SDValue NewLd = SDValue();
5694 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5695 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5696 LDBase->getPointerInfo(),
5697 LDBase->isVolatile(), LDBase->isNonTemporal(),
5698 LDBase->isInvariant(), 0);
5699 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5700 LDBase->getPointerInfo(),
5701 LDBase->isVolatile(), LDBase->isNonTemporal(),
5702 LDBase->isInvariant(), LDBase->getAlignment());
5704 if (LDBase->hasAnyUseOfValue(1)) {
5705 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5707 SDValue(NewLd.getNode(), 1));
5708 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5709 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5710 SDValue(NewLd.getNode(), 1));
5715 if (NumElems == 4 && LastLoadedElt == 1 &&
5716 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5717 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5718 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5720 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5721 LDBase->getPointerInfo(),
5722 LDBase->getAlignment(),
5723 false/*isVolatile*/, true/*ReadMem*/,
5726 // Make sure the newly-created LOAD is in the same position as LDBase in
5727 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5728 // update uses of LDBase's output chain to use the TokenFactor.
5729 if (LDBase->hasAnyUseOfValue(1)) {
5730 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5731 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5732 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5733 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5734 SDValue(ResNode.getNode(), 1));
5737 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5742 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5743 /// to generate a splat value for the following cases:
5744 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5745 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5746 /// a scalar load, or a constant.
5747 /// The VBROADCAST node is returned when a pattern is found,
5748 /// or SDValue() otherwise.
5749 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5750 SelectionDAG &DAG) {
5751 if (!Subtarget->hasFp256())
5754 MVT VT = Op.getSimpleValueType();
5757 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5758 "Unsupported vector type for broadcast.");
5763 switch (Op.getOpcode()) {
5765 // Unknown pattern found.
5768 case ISD::BUILD_VECTOR: {
5769 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5770 BitVector UndefElements;
5771 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5773 // We need a splat of a single value to use broadcast, and it doesn't
5774 // make any sense if the value is only in one element of the vector.
5775 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5779 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5780 Ld.getOpcode() == ISD::ConstantFP);
5782 // Make sure that all of the users of a non-constant load are from the
5783 // BUILD_VECTOR node.
5784 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5789 case ISD::VECTOR_SHUFFLE: {
5790 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5792 // Shuffles must have a splat mask where the first element is
5794 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5797 SDValue Sc = Op.getOperand(0);
5798 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5799 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5801 if (!Subtarget->hasInt256())
5804 // Use the register form of the broadcast instruction available on AVX2.
5805 if (VT.getSizeInBits() >= 256)
5806 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5807 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5810 Ld = Sc.getOperand(0);
5811 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5812 Ld.getOpcode() == ISD::ConstantFP);
5814 // The scalar_to_vector node and the suspected
5815 // load node must have exactly one user.
5816 // Constants may have multiple users.
5818 // AVX-512 has register version of the broadcast
5819 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5820 Ld.getValueType().getSizeInBits() >= 32;
5821 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5828 bool IsGE256 = (VT.getSizeInBits() >= 256);
5830 // Handle the broadcasting a single constant scalar from the constant pool
5831 // into a vector. On Sandybridge it is still better to load a constant vector
5832 // from the constant pool and not to broadcast it from a scalar.
5833 if (ConstSplatVal && Subtarget->hasInt256()) {
5834 EVT CVT = Ld.getValueType();
5835 assert(!CVT.isVector() && "Must not broadcast a vector type");
5836 unsigned ScalarSize = CVT.getSizeInBits();
5838 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5839 const Constant *C = nullptr;
5840 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5841 C = CI->getConstantIntValue();
5842 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5843 C = CF->getConstantFPValue();
5845 assert(C && "Invalid constant type");
5847 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5848 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5849 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5850 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5851 MachinePointerInfo::getConstantPool(),
5852 false, false, false, Alignment);
5854 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5858 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5859 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5861 // Handle AVX2 in-register broadcasts.
5862 if (!IsLoad && Subtarget->hasInt256() &&
5863 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5864 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5866 // The scalar source must be a normal load.
5870 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5871 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5873 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5874 // double since there is no vbroadcastsd xmm
5875 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5876 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5877 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5880 // Unsupported broadcast.
5884 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5885 /// underlying vector and index.
5887 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5889 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5891 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5892 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5895 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5897 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5899 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5900 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5903 // In this case the vector is the extract_subvector expression and the index
5904 // is 2, as specified by the shuffle.
5905 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5906 SDValue ShuffleVec = SVOp->getOperand(0);
5907 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5908 assert(ShuffleVecVT.getVectorElementType() ==
5909 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5911 int ShuffleIdx = SVOp->getMaskElt(Idx);
5912 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5913 ExtractedFromVec = ShuffleVec;
5919 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5920 MVT VT = Op.getSimpleValueType();
5922 // Skip if insert_vec_elt is not supported.
5923 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5924 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5928 unsigned NumElems = Op.getNumOperands();
5932 SmallVector<unsigned, 4> InsertIndices;
5933 SmallVector<int, 8> Mask(NumElems, -1);
5935 for (unsigned i = 0; i != NumElems; ++i) {
5936 unsigned Opc = Op.getOperand(i).getOpcode();
5938 if (Opc == ISD::UNDEF)
5941 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5942 // Quit if more than 1 elements need inserting.
5943 if (InsertIndices.size() > 1)
5946 InsertIndices.push_back(i);
5950 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5951 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5952 // Quit if non-constant index.
5953 if (!isa<ConstantSDNode>(ExtIdx))
5955 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5957 // Quit if extracted from vector of different type.
5958 if (ExtractedFromVec.getValueType() != VT)
5961 if (!VecIn1.getNode())
5962 VecIn1 = ExtractedFromVec;
5963 else if (VecIn1 != ExtractedFromVec) {
5964 if (!VecIn2.getNode())
5965 VecIn2 = ExtractedFromVec;
5966 else if (VecIn2 != ExtractedFromVec)
5967 // Quit if more than 2 vectors to shuffle
5971 if (ExtractedFromVec == VecIn1)
5973 else if (ExtractedFromVec == VecIn2)
5974 Mask[i] = Idx + NumElems;
5977 if (!VecIn1.getNode())
5980 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5981 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5982 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5983 unsigned Idx = InsertIndices[i];
5984 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5985 DAG.getIntPtrConstant(Idx));
5991 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5993 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5995 MVT VT = Op.getSimpleValueType();
5996 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5997 "Unexpected type in LowerBUILD_VECTORvXi1!");
6000 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6001 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6002 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6003 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6006 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6007 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6008 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6009 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6012 bool AllContants = true;
6013 uint64_t Immediate = 0;
6014 int NonConstIdx = -1;
6015 bool IsSplat = true;
6016 unsigned NumNonConsts = 0;
6017 unsigned NumConsts = 0;
6018 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6019 SDValue In = Op.getOperand(idx);
6020 if (In.getOpcode() == ISD::UNDEF)
6022 if (!isa<ConstantSDNode>(In)) {
6023 AllContants = false;
6029 if (cast<ConstantSDNode>(In)->getZExtValue())
6030 Immediate |= (1ULL << idx);
6032 if (In != Op.getOperand(0))
6037 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6038 DAG.getConstant(Immediate, MVT::i16));
6039 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6040 DAG.getIntPtrConstant(0));
6043 if (NumNonConsts == 1 && NonConstIdx != 0) {
6046 SDValue VecAsImm = DAG.getConstant(Immediate,
6047 MVT::getIntegerVT(VT.getSizeInBits()));
6048 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6051 DstVec = DAG.getUNDEF(VT);
6052 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6053 Op.getOperand(NonConstIdx),
6054 DAG.getIntPtrConstant(NonConstIdx));
6056 if (!IsSplat && (NonConstIdx != 0))
6057 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6058 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6061 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6062 DAG.getConstant(-1, SelectVT),
6063 DAG.getConstant(0, SelectVT));
6065 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6066 DAG.getConstant((Immediate | 1), SelectVT),
6067 DAG.getConstant(Immediate, SelectVT));
6068 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6071 /// \brief Return true if \p N implements a horizontal binop and return the
6072 /// operands for the horizontal binop into V0 and V1.
6074 /// This is a helper function of PerformBUILD_VECTORCombine.
6075 /// This function checks that the build_vector \p N in input implements a
6076 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6077 /// operation to match.
6078 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6079 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6080 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6083 /// This function only analyzes elements of \p N whose indices are
6084 /// in range [BaseIdx, LastIdx).
6085 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6087 unsigned BaseIdx, unsigned LastIdx,
6088 SDValue &V0, SDValue &V1) {
6089 EVT VT = N->getValueType(0);
6091 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6092 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6093 "Invalid Vector in input!");
6095 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6096 bool CanFold = true;
6097 unsigned ExpectedVExtractIdx = BaseIdx;
6098 unsigned NumElts = LastIdx - BaseIdx;
6099 V0 = DAG.getUNDEF(VT);
6100 V1 = DAG.getUNDEF(VT);
6102 // Check if N implements a horizontal binop.
6103 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6104 SDValue Op = N->getOperand(i + BaseIdx);
6107 if (Op->getOpcode() == ISD::UNDEF) {
6108 // Update the expected vector extract index.
6109 if (i * 2 == NumElts)
6110 ExpectedVExtractIdx = BaseIdx;
6111 ExpectedVExtractIdx += 2;
6115 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6120 SDValue Op0 = Op.getOperand(0);
6121 SDValue Op1 = Op.getOperand(1);
6123 // Try to match the following pattern:
6124 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6125 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6126 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6127 Op0.getOperand(0) == Op1.getOperand(0) &&
6128 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6129 isa<ConstantSDNode>(Op1.getOperand(1)));
6133 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6134 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6136 if (i * 2 < NumElts) {
6137 if (V0.getOpcode() == ISD::UNDEF)
6138 V0 = Op0.getOperand(0);
6140 if (V1.getOpcode() == ISD::UNDEF)
6141 V1 = Op0.getOperand(0);
6142 if (i * 2 == NumElts)
6143 ExpectedVExtractIdx = BaseIdx;
6146 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6147 if (I0 == ExpectedVExtractIdx)
6148 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6149 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6150 // Try to match the following dag sequence:
6151 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6152 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6156 ExpectedVExtractIdx += 2;
6162 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6163 /// a concat_vector.
6165 /// This is a helper function of PerformBUILD_VECTORCombine.
6166 /// This function expects two 256-bit vectors called V0 and V1.
6167 /// At first, each vector is split into two separate 128-bit vectors.
6168 /// Then, the resulting 128-bit vectors are used to implement two
6169 /// horizontal binary operations.
6171 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6173 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6174 /// the two new horizontal binop.
6175 /// When Mode is set, the first horizontal binop dag node would take as input
6176 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6177 /// horizontal binop dag node would take as input the lower 128-bit of V1
6178 /// and the upper 128-bit of V1.
6180 /// HADD V0_LO, V0_HI
6181 /// HADD V1_LO, V1_HI
6183 /// Otherwise, the first horizontal binop dag node takes as input the lower
6184 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6185 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6187 /// HADD V0_LO, V1_LO
6188 /// HADD V0_HI, V1_HI
6190 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6191 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6192 /// the upper 128-bits of the result.
6193 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6194 SDLoc DL, SelectionDAG &DAG,
6195 unsigned X86Opcode, bool Mode,
6196 bool isUndefLO, bool isUndefHI) {
6197 EVT VT = V0.getValueType();
6198 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6199 "Invalid nodes in input!");
6201 unsigned NumElts = VT.getVectorNumElements();
6202 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6203 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6204 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6205 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6206 EVT NewVT = V0_LO.getValueType();
6208 SDValue LO = DAG.getUNDEF(NewVT);
6209 SDValue HI = DAG.getUNDEF(NewVT);
6212 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6213 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6214 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6215 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6216 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6218 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6219 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6220 V1_LO->getOpcode() != ISD::UNDEF))
6221 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6223 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6224 V1_HI->getOpcode() != ISD::UNDEF))
6225 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6228 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6231 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6232 /// sequence of 'vadd + vsub + blendi'.
6233 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6234 const X86Subtarget *Subtarget) {
6236 EVT VT = BV->getValueType(0);
6237 unsigned NumElts = VT.getVectorNumElements();
6238 SDValue InVec0 = DAG.getUNDEF(VT);
6239 SDValue InVec1 = DAG.getUNDEF(VT);
6241 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6242 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6244 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6246 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6249 // Odd-numbered elements in the input build vector are obtained from
6250 // adding two integer/float elements.
6251 // Even-numbered elements in the input build vector are obtained from
6252 // subtracting two integer/float elements.
6253 unsigned ExpectedOpcode = ISD::FSUB;
6254 unsigned NextExpectedOpcode = ISD::FADD;
6255 bool AddFound = false;
6256 bool SubFound = false;
6258 for (unsigned i = 0, e = NumElts; i != e; i++) {
6259 SDValue Op = BV->getOperand(i);
6261 // Skip 'undef' values.
6262 unsigned Opcode = Op.getOpcode();
6263 if (Opcode == ISD::UNDEF) {
6264 std::swap(ExpectedOpcode, NextExpectedOpcode);
6268 // Early exit if we found an unexpected opcode.
6269 if (Opcode != ExpectedOpcode)
6272 SDValue Op0 = Op.getOperand(0);
6273 SDValue Op1 = Op.getOperand(1);
6275 // Try to match the following pattern:
6276 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6277 // Early exit if we cannot match that sequence.
6278 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6279 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6280 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6281 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6282 Op0.getOperand(1) != Op1.getOperand(1))
6285 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6289 // We found a valid add/sub node. Update the information accordingly.
6295 // Update InVec0 and InVec1.
6296 if (InVec0.getOpcode() == ISD::UNDEF)
6297 InVec0 = Op0.getOperand(0);
6298 if (InVec1.getOpcode() == ISD::UNDEF)
6299 InVec1 = Op1.getOperand(0);
6301 // Make sure that operands in input to each add/sub node always
6302 // come from a same pair of vectors.
6303 if (InVec0 != Op0.getOperand(0)) {
6304 if (ExpectedOpcode == ISD::FSUB)
6307 // FADD is commutable. Try to commute the operands
6308 // and then test again.
6309 std::swap(Op0, Op1);
6310 if (InVec0 != Op0.getOperand(0))
6314 if (InVec1 != Op1.getOperand(0))
6317 // Update the pair of expected opcodes.
6318 std::swap(ExpectedOpcode, NextExpectedOpcode);
6321 // Don't try to fold this build_vector into a VSELECT if it has
6322 // too many UNDEF operands.
6323 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6324 InVec1.getOpcode() != ISD::UNDEF) {
6325 // Emit a sequence of vector add and sub followed by a VSELECT.
6326 // The new VSELECT will be lowered into a BLENDI.
6327 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6328 // and emit a single ADDSUB instruction.
6329 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6330 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6332 // Construct the VSELECT mask.
6333 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6334 EVT SVT = MaskVT.getVectorElementType();
6335 unsigned SVTBits = SVT.getSizeInBits();
6336 SmallVector<SDValue, 8> Ops;
6338 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6339 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6340 APInt::getAllOnesValue(SVTBits);
6341 SDValue Constant = DAG.getConstant(Value, SVT);
6342 Ops.push_back(Constant);
6345 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6346 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6352 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6353 const X86Subtarget *Subtarget) {
6355 EVT VT = N->getValueType(0);
6356 unsigned NumElts = VT.getVectorNumElements();
6357 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6358 SDValue InVec0, InVec1;
6360 // Try to match an ADDSUB.
6361 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6362 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6363 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6364 if (Value.getNode())
6368 // Try to match horizontal ADD/SUB.
6369 unsigned NumUndefsLO = 0;
6370 unsigned NumUndefsHI = 0;
6371 unsigned Half = NumElts/2;
6373 // Count the number of UNDEF operands in the build_vector in input.
6374 for (unsigned i = 0, e = Half; i != e; ++i)
6375 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6378 for (unsigned i = Half, e = NumElts; i != e; ++i)
6379 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6382 // Early exit if this is either a build_vector of all UNDEFs or all the
6383 // operands but one are UNDEF.
6384 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6387 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6388 // Try to match an SSE3 float HADD/HSUB.
6389 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6390 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6392 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6393 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6394 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6395 // Try to match an SSSE3 integer HADD/HSUB.
6396 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6397 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6399 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6400 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6403 if (!Subtarget->hasAVX())
6406 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6407 // Try to match an AVX horizontal add/sub of packed single/double
6408 // precision floating point values from 256-bit vectors.
6409 SDValue InVec2, InVec3;
6410 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6411 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6412 ((InVec0.getOpcode() == ISD::UNDEF ||
6413 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6414 ((InVec1.getOpcode() == ISD::UNDEF ||
6415 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6416 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6418 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6419 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6420 ((InVec0.getOpcode() == ISD::UNDEF ||
6421 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6422 ((InVec1.getOpcode() == ISD::UNDEF ||
6423 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6424 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6425 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6426 // Try to match an AVX2 horizontal add/sub of signed integers.
6427 SDValue InVec2, InVec3;
6429 bool CanFold = true;
6431 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6432 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6433 ((InVec0.getOpcode() == ISD::UNDEF ||
6434 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6435 ((InVec1.getOpcode() == ISD::UNDEF ||
6436 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6437 X86Opcode = X86ISD::HADD;
6438 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6439 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6440 ((InVec0.getOpcode() == ISD::UNDEF ||
6441 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6442 ((InVec1.getOpcode() == ISD::UNDEF ||
6443 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6444 X86Opcode = X86ISD::HSUB;
6449 // Fold this build_vector into a single horizontal add/sub.
6450 // Do this only if the target has AVX2.
6451 if (Subtarget->hasAVX2())
6452 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6454 // Do not try to expand this build_vector into a pair of horizontal
6455 // add/sub if we can emit a pair of scalar add/sub.
6456 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6459 // Convert this build_vector into a pair of horizontal binop followed by
6461 bool isUndefLO = NumUndefsLO == Half;
6462 bool isUndefHI = NumUndefsHI == Half;
6463 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6464 isUndefLO, isUndefHI);
6468 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6469 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6471 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6472 X86Opcode = X86ISD::HADD;
6473 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6474 X86Opcode = X86ISD::HSUB;
6475 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6476 X86Opcode = X86ISD::FHADD;
6477 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6478 X86Opcode = X86ISD::FHSUB;
6482 // Don't try to expand this build_vector into a pair of horizontal add/sub
6483 // if we can simply emit a pair of scalar add/sub.
6484 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6487 // Convert this build_vector into two horizontal add/sub followed by
6489 bool isUndefLO = NumUndefsLO == Half;
6490 bool isUndefHI = NumUndefsHI == Half;
6491 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6492 isUndefLO, isUndefHI);
6499 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6502 MVT VT = Op.getSimpleValueType();
6503 MVT ExtVT = VT.getVectorElementType();
6504 unsigned NumElems = Op.getNumOperands();
6506 // Generate vectors for predicate vectors.
6507 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6508 return LowerBUILD_VECTORvXi1(Op, DAG);
6510 // Vectors containing all zeros can be matched by pxor and xorps later
6511 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6512 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6513 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6514 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6517 return getZeroVector(VT, Subtarget, DAG, dl);
6520 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6521 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6522 // vpcmpeqd on 256-bit vectors.
6523 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6524 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6527 if (!VT.is512BitVector())
6528 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6531 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6532 if (Broadcast.getNode())
6535 unsigned EVTBits = ExtVT.getSizeInBits();
6537 unsigned NumZero = 0;
6538 unsigned NumNonZero = 0;
6539 unsigned NonZeros = 0;
6540 bool IsAllConstants = true;
6541 SmallSet<SDValue, 8> Values;
6542 for (unsigned i = 0; i < NumElems; ++i) {
6543 SDValue Elt = Op.getOperand(i);
6544 if (Elt.getOpcode() == ISD::UNDEF)
6547 if (Elt.getOpcode() != ISD::Constant &&
6548 Elt.getOpcode() != ISD::ConstantFP)
6549 IsAllConstants = false;
6550 if (X86::isZeroNode(Elt))
6553 NonZeros |= (1 << i);
6558 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6559 if (NumNonZero == 0)
6560 return DAG.getUNDEF(VT);
6562 // Special case for single non-zero, non-undef, element.
6563 if (NumNonZero == 1) {
6564 unsigned Idx = countTrailingZeros(NonZeros);
6565 SDValue Item = Op.getOperand(Idx);
6567 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6568 // the value are obviously zero, truncate the value to i32 and do the
6569 // insertion that way. Only do this if the value is non-constant or if the
6570 // value is a constant being inserted into element 0. It is cheaper to do
6571 // a constant pool load than it is to do a movd + shuffle.
6572 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6573 (!IsAllConstants || Idx == 0)) {
6574 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6576 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6577 EVT VecVT = MVT::v4i32;
6578 unsigned VecElts = 4;
6580 // Truncate the value (which may itself be a constant) to i32, and
6581 // convert it to a vector with movd (S2V+shuffle to zero extend).
6582 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6583 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6584 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6586 // Now we have our 32-bit value zero extended in the low element of
6587 // a vector. If Idx != 0, swizzle it into place.
6589 SmallVector<int, 4> Mask;
6590 Mask.push_back(Idx);
6591 for (unsigned i = 1; i != VecElts; ++i)
6593 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6596 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6600 // If we have a constant or non-constant insertion into the low element of
6601 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6602 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6603 // depending on what the source datatype is.
6606 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6608 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6609 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6610 if (VT.is256BitVector() || VT.is512BitVector()) {
6611 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6612 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6613 Item, DAG.getIntPtrConstant(0));
6615 assert(VT.is128BitVector() && "Expected an SSE value type!");
6616 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6617 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6618 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6621 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6622 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6623 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6624 if (VT.is256BitVector()) {
6625 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6626 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6628 assert(VT.is128BitVector() && "Expected an SSE value type!");
6629 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6631 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6635 // Is it a vector logical left shift?
6636 if (NumElems == 2 && Idx == 1 &&
6637 X86::isZeroNode(Op.getOperand(0)) &&
6638 !X86::isZeroNode(Op.getOperand(1))) {
6639 unsigned NumBits = VT.getSizeInBits();
6640 return getVShift(true, VT,
6641 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6642 VT, Op.getOperand(1)),
6643 NumBits/2, DAG, *this, dl);
6646 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6649 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6650 // is a non-constant being inserted into an element other than the low one,
6651 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6652 // movd/movss) to move this into the low element, then shuffle it into
6654 if (EVTBits == 32) {
6655 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6657 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6658 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6659 SmallVector<int, 8> MaskVec;
6660 for (unsigned i = 0; i != NumElems; ++i)
6661 MaskVec.push_back(i == Idx ? 0 : 1);
6662 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6666 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6667 if (Values.size() == 1) {
6668 if (EVTBits == 32) {
6669 // Instead of a shuffle like this:
6670 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6671 // Check if it's possible to issue this instead.
6672 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6673 unsigned Idx = countTrailingZeros(NonZeros);
6674 SDValue Item = Op.getOperand(Idx);
6675 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6676 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6681 // A vector full of immediates; various special cases are already
6682 // handled, so this is best done with a single constant-pool load.
6686 // For AVX-length vectors, build the individual 128-bit pieces and use
6687 // shuffles to put them in place.
6688 if (VT.is256BitVector() || VT.is512BitVector()) {
6689 SmallVector<SDValue, 64> V;
6690 for (unsigned i = 0; i != NumElems; ++i)
6691 V.push_back(Op.getOperand(i));
6693 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6695 // Build both the lower and upper subvector.
6696 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6697 makeArrayRef(&V[0], NumElems/2));
6698 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6699 makeArrayRef(&V[NumElems / 2], NumElems/2));
6701 // Recreate the wider vector with the lower and upper part.
6702 if (VT.is256BitVector())
6703 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6704 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6707 // Let legalizer expand 2-wide build_vectors.
6708 if (EVTBits == 64) {
6709 if (NumNonZero == 1) {
6710 // One half is zero or undef.
6711 unsigned Idx = countTrailingZeros(NonZeros);
6712 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6713 Op.getOperand(Idx));
6714 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6719 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6720 if (EVTBits == 8 && NumElems == 16) {
6721 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6723 if (V.getNode()) return V;
6726 if (EVTBits == 16 && NumElems == 8) {
6727 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6729 if (V.getNode()) return V;
6732 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6733 if (EVTBits == 32 && NumElems == 4) {
6734 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6735 NumZero, DAG, Subtarget, *this);
6740 // If element VT is == 32 bits, turn it into a number of shuffles.
6741 SmallVector<SDValue, 8> V(NumElems);
6742 if (NumElems == 4 && NumZero > 0) {
6743 for (unsigned i = 0; i < 4; ++i) {
6744 bool isZero = !(NonZeros & (1 << i));
6746 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6748 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6751 for (unsigned i = 0; i < 2; ++i) {
6752 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6755 V[i] = V[i*2]; // Must be a zero vector.
6758 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6761 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6764 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6769 bool Reverse1 = (NonZeros & 0x3) == 2;
6770 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6774 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6775 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6777 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6780 if (Values.size() > 1 && VT.is128BitVector()) {
6781 // Check for a build vector of consecutive loads.
6782 for (unsigned i = 0; i < NumElems; ++i)
6783 V[i] = Op.getOperand(i);
6785 // Check for elements which are consecutive loads.
6786 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6790 // Check for a build vector from mostly shuffle plus few inserting.
6791 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6795 // For SSE 4.1, use insertps to put the high elements into the low element.
6796 if (getSubtarget()->hasSSE41()) {
6798 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6799 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6801 Result = DAG.getUNDEF(VT);
6803 for (unsigned i = 1; i < NumElems; ++i) {
6804 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6805 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6806 Op.getOperand(i), DAG.getIntPtrConstant(i));
6811 // Otherwise, expand into a number of unpckl*, start by extending each of
6812 // our (non-undef) elements to the full vector width with the element in the
6813 // bottom slot of the vector (which generates no code for SSE).
6814 for (unsigned i = 0; i < NumElems; ++i) {
6815 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6816 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6818 V[i] = DAG.getUNDEF(VT);
6821 // Next, we iteratively mix elements, e.g. for v4f32:
6822 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6823 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6824 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6825 unsigned EltStride = NumElems >> 1;
6826 while (EltStride != 0) {
6827 for (unsigned i = 0; i < EltStride; ++i) {
6828 // If V[i+EltStride] is undef and this is the first round of mixing,
6829 // then it is safe to just drop this shuffle: V[i] is already in the
6830 // right place, the one element (since it's the first round) being
6831 // inserted as undef can be dropped. This isn't safe for successive
6832 // rounds because they will permute elements within both vectors.
6833 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6834 EltStride == NumElems/2)
6837 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6846 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6847 // to create 256-bit vectors from two other 128-bit ones.
6848 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6850 MVT ResVT = Op.getSimpleValueType();
6852 assert((ResVT.is256BitVector() ||
6853 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6855 SDValue V1 = Op.getOperand(0);
6856 SDValue V2 = Op.getOperand(1);
6857 unsigned NumElems = ResVT.getVectorNumElements();
6858 if(ResVT.is256BitVector())
6859 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6861 if (Op.getNumOperands() == 4) {
6862 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6863 ResVT.getVectorNumElements()/2);
6864 SDValue V3 = Op.getOperand(2);
6865 SDValue V4 = Op.getOperand(3);
6866 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6867 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6869 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6872 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6873 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6874 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6875 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6876 Op.getNumOperands() == 4)));
6878 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6879 // from two other 128-bit ones.
6881 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6882 return LowerAVXCONCAT_VECTORS(Op, DAG);
6886 //===----------------------------------------------------------------------===//
6887 // Vector shuffle lowering
6889 // This is an experimental code path for lowering vector shuffles on x86. It is
6890 // designed to handle arbitrary vector shuffles and blends, gracefully
6891 // degrading performance as necessary. It works hard to recognize idiomatic
6892 // shuffles and lower them to optimal instruction patterns without leaving
6893 // a framework that allows reasonably efficient handling of all vector shuffle
6895 //===----------------------------------------------------------------------===//
6897 /// \brief Tiny helper function to identify a no-op mask.
6899 /// This is a somewhat boring predicate function. It checks whether the mask
6900 /// array input, which is assumed to be a single-input shuffle mask of the kind
6901 /// used by the X86 shuffle instructions (not a fully general
6902 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6903 /// in-place shuffle are 'no-op's.
6904 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6905 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6906 if (Mask[i] != -1 && Mask[i] != i)
6911 /// \brief Helper function to classify a mask as a single-input mask.
6913 /// This isn't a generic single-input test because in the vector shuffle
6914 /// lowering we canonicalize single inputs to be the first input operand. This
6915 /// means we can more quickly test for a single input by only checking whether
6916 /// an input from the second operand exists. We also assume that the size of
6917 /// mask corresponds to the size of the input vectors which isn't true in the
6918 /// fully general case.
6919 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6921 if (M >= (int)Mask.size())
6926 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6928 /// This helper function produces an 8-bit shuffle immediate corresponding to
6929 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6930 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6933 /// NB: We rely heavily on "undef" masks preserving the input lane.
6934 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6935 SelectionDAG &DAG) {
6936 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6937 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6938 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6939 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6940 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6943 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6944 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6945 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6946 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6947 return DAG.getConstant(Imm, MVT::i8);
6950 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
6952 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
6953 /// support for floating point shuffles but not integer shuffles. These
6954 /// instructions will incur a domain crossing penalty on some chips though so
6955 /// it is better to avoid lowering through this for integer vectors where
6957 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6958 const X86Subtarget *Subtarget,
6959 SelectionDAG &DAG) {
6961 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
6962 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6963 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6964 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6965 ArrayRef<int> Mask = SVOp->getMask();
6966 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
6968 if (isSingleInputShuffleMask(Mask)) {
6969 // Straight shuffle of a single input vector. Simulate this by using the
6970 // single input as both of the "inputs" to this instruction..
6971 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
6972 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
6973 DAG.getConstant(SHUFPDMask, MVT::i8));
6975 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
6976 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
6978 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
6979 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
6980 DAG.getConstant(SHUFPDMask, MVT::i8));
6983 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
6985 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
6986 /// the integer unit to minimize domain crossing penalties. However, for blends
6987 /// it falls back to the floating point shuffle operation with appropriate bit
6989 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6990 const X86Subtarget *Subtarget,
6991 SelectionDAG &DAG) {
6993 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
6994 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6995 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6997 ArrayRef<int> Mask = SVOp->getMask();
6998 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7000 if (isSingleInputShuffleMask(Mask)) {
7001 // Straight shuffle of a single input vector. For everything from SSE2
7002 // onward this has a single fast instruction with no scary immediates.
7003 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7004 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7005 int WidenedMask[4] = {
7006 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7007 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7009 ISD::BITCAST, DL, MVT::v2i64,
7010 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7011 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7014 // We implement this with SHUFPD which is pretty lame because it will likely
7015 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7016 // However, all the alternatives are still more cycles and newer chips don't
7017 // have this problem. It would be really nice if x86 had better shuffles here.
7018 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7019 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7020 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7021 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7024 /// \brief Lower 4-lane 32-bit floating point shuffles.
7026 /// Uses instructions exclusively from the floating point unit to minimize
7027 /// domain crossing penalties, as these are sufficient to implement all v4f32
7029 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7030 const X86Subtarget *Subtarget,
7031 SelectionDAG &DAG) {
7033 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7034 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7035 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7037 ArrayRef<int> Mask = SVOp->getMask();
7038 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7040 SDValue LowV = V1, HighV = V2;
7041 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7044 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7046 if (NumV2Elements == 0)
7047 // Straight shuffle of a single input vector. We pass the input vector to
7048 // both operands to simulate this with a SHUFPS.
7049 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7050 getV4X86ShuffleImm8ForMask(Mask, DAG));
7052 if (NumV2Elements == 1) {
7054 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7056 // Compute the index adjacent to V2Index and in the same half by toggling
7058 int V2AdjIndex = V2Index ^ 1;
7060 if (Mask[V2AdjIndex] == -1) {
7061 // Handles all the cases where we have a single V2 element and an undef.
7062 // This will only ever happen in the high lanes because we commute the
7063 // vector otherwise.
7065 std::swap(LowV, HighV);
7066 NewMask[V2Index] -= 4;
7068 // Handle the case where the V2 element ends up adjacent to a V1 element.
7069 // To make this work, blend them together as the first step.
7070 int V1Index = V2AdjIndex;
7071 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7072 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7073 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7075 // Now proceed to reconstruct the final blend as we have the necessary
7076 // high or low half formed.
7083 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7084 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7086 } else if (NumV2Elements == 2) {
7087 if (Mask[0] < 4 && Mask[1] < 4) {
7088 // Handle the easy case where we have V1 in the low lanes and V2 in the
7089 // high lanes. We never see this reversed because we sort the shuffle.
7093 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7094 // trying to place elements directly, just blend them and set up the final
7095 // shuffle to place them.
7097 // The first two blend mask elements are for V1, the second two are for
7099 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7100 Mask[2] < 4 ? Mask[2] : Mask[3],
7101 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7102 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7103 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7104 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7106 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7109 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7110 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7111 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7112 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7115 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7116 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7119 /// \brief Lower 4-lane i32 vector shuffles.
7121 /// We try to handle these with integer-domain shuffles where we can, but for
7122 /// blends we use the floating point domain blend instructions.
7123 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7124 const X86Subtarget *Subtarget,
7125 SelectionDAG &DAG) {
7127 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7128 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7129 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7130 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7131 ArrayRef<int> Mask = SVOp->getMask();
7132 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7134 if (isSingleInputShuffleMask(Mask))
7135 // Straight shuffle of a single input vector. For everything from SSE2
7136 // onward this has a single fast instruction with no scary immediates.
7137 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7138 getV4X86ShuffleImm8ForMask(Mask, DAG));
7140 // We implement this with SHUFPS because it can blend from two vectors.
7141 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7142 // up the inputs, bypassing domain shift penalties that we would encur if we
7143 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7145 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7146 DAG.getVectorShuffle(
7148 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7149 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7152 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7153 /// shuffle lowering, and the most complex part.
7155 /// The lowering strategy is to try to form pairs of input lanes which are
7156 /// targeted at the same half of the final vector, and then use a dword shuffle
7157 /// to place them onto the right half, and finally unpack the paired lanes into
7158 /// their final position.
7160 /// The exact breakdown of how to form these dword pairs and align them on the
7161 /// correct sides is really tricky. See the comments within the function for
7162 /// more of the details.
7163 static SDValue lowerV8I16SingleInputVectorShuffle(
7164 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7165 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7166 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7167 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7168 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7170 SmallVector<int, 4> LoInputs;
7171 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7172 [](int M) { return M >= 0; });
7173 std::sort(LoInputs.begin(), LoInputs.end());
7174 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7175 SmallVector<int, 4> HiInputs;
7176 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7177 [](int M) { return M >= 0; });
7178 std::sort(HiInputs.begin(), HiInputs.end());
7179 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7181 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7182 int NumHToL = LoInputs.size() - NumLToL;
7184 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7185 int NumHToH = HiInputs.size() - NumLToH;
7186 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7187 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7188 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7189 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7191 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7192 // such inputs we can swap two of the dwords across the half mark and end up
7193 // with <=2 inputs to each half in each half. Once there, we can fall through
7194 // to the generic code below. For example:
7196 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7197 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7199 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7201 auto balanceSides = [&](ArrayRef<int> ThreeInputs, int OneInput,
7202 int ThreeInputHalfSum, int OneInputHalfOffset) {
7203 // Compute the index of dword with only one word among the three inputs in
7204 // a half by taking the sum of the half with three inputs and subtracting
7205 // the sum of the actual three inputs. The difference is the remaining
7207 int DWordA = (ThreeInputHalfSum -
7208 std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
7210 int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
7212 int PSHUFDMask[] = {0, 1, 2, 3};
7213 PSHUFDMask[DWordA] = DWordB;
7214 PSHUFDMask[DWordB] = DWordA;
7215 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7216 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7217 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7218 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7220 // Adjust the mask to match the new locations of A and B.
7222 if (M != -1 && M/2 == DWordA)
7223 M = 2 * DWordB + M % 2;
7224 else if (M != -1 && M/2 == DWordB)
7225 M = 2 * DWordA + M % 2;
7227 // Recurse back into this routine to re-compute state now that this isn't
7228 // a 3 and 1 problem.
7229 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7232 if (NumLToL == 3 && NumHToL == 1)
7233 return balanceSides(LToLInputs, HToLInputs[0], 0 + 1 + 2 + 3, 4);
7234 else if (NumLToL == 1 && NumHToL == 3)
7235 return balanceSides(HToLInputs, LToLInputs[0], 4 + 5 + 6 + 7, 0);
7236 else if (NumLToH == 1 && NumHToH == 3)
7237 return balanceSides(HToHInputs, LToHInputs[0], 4 + 5 + 6 + 7, 0);
7238 else if (NumLToH == 3 && NumHToH == 1)
7239 return balanceSides(LToHInputs, HToHInputs[0], 0 + 1 + 2 + 3, 4);
7241 // At this point there are at most two inputs to the low and high halves from
7242 // each half. That means the inputs can always be grouped into dwords and
7243 // those dwords can then be moved to the correct half with a dword shuffle.
7244 // We use at most one low and one high word shuffle to collect these paired
7245 // inputs into dwords, and finally a dword shuffle to place them.
7246 int PSHUFLMask[4] = {-1, -1, -1, -1};
7247 int PSHUFHMask[4] = {-1, -1, -1, -1};
7248 int PSHUFDMask[4] = {-1, -1, -1, -1};
7250 // First fix the masks for all the inputs that are staying in their
7251 // original halves. This will then dictate the targets of the cross-half
7253 auto fixInPlaceInputs = [&PSHUFDMask](
7254 ArrayRef<int> InPlaceInputs, MutableArrayRef<int> SourceHalfMask,
7255 MutableArrayRef<int> HalfMask, int HalfOffset) {
7256 if (InPlaceInputs.empty())
7258 if (InPlaceInputs.size() == 1) {
7259 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7260 InPlaceInputs[0] - HalfOffset;
7261 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7265 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7266 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7267 InPlaceInputs[0] - HalfOffset;
7268 // Put the second input next to the first so that they are packed into
7269 // a dword. We find the adjacent index by toggling the low bit.
7270 int AdjIndex = InPlaceInputs[0] ^ 1;
7271 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7272 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7273 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7275 if (!HToLInputs.empty())
7276 fixInPlaceInputs(LToLInputs, PSHUFLMask, LoMask, 0);
7277 if (!LToHInputs.empty())
7278 fixInPlaceInputs(HToHInputs, PSHUFHMask, HiMask, 4);
7280 // Now gather the cross-half inputs and place them into a free dword of
7281 // their target half.
7282 // FIXME: This operation could almost certainly be simplified dramatically to
7283 // look more like the 3-1 fixing operation.
7284 auto moveInputsToRightHalf = [&PSHUFDMask](
7285 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7286 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7287 int SourceOffset, int DestOffset) {
7288 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7289 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7291 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7293 int LowWord = Word & ~1;
7294 int HighWord = Word | 1;
7295 return isWordClobbered(SourceHalfMask, LowWord) ||
7296 isWordClobbered(SourceHalfMask, HighWord);
7299 if (IncomingInputs.empty())
7302 if (ExistingInputs.empty()) {
7303 // Map any dwords with inputs from them into the right half.
7304 for (int Input : IncomingInputs) {
7305 // If the source half mask maps over the inputs, turn those into
7306 // swaps and use the swapped lane.
7307 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7308 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7309 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7310 Input - SourceOffset;
7311 // We have to swap the uses in our half mask in one sweep.
7312 for (int &M : HalfMask)
7313 if (M == SourceHalfMask[Input - SourceOffset])
7315 else if (M == Input)
7316 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7318 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7319 Input - SourceOffset &&
7320 "Previous placement doesn't match!");
7322 // Note that this correctly re-maps both when we do a swap and when
7323 // we observe the other side of the swap above. We rely on that to
7324 // avoid swapping the members of the input list directly.
7325 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7328 // Map the input's dword into the correct half.
7329 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7330 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7332 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7334 "Previous placement doesn't match!");
7337 // And just directly shift any other-half mask elements to be same-half
7338 // as we will have mirrored the dword containing the element into the
7339 // same position within that half.
7340 for (int &M : HalfMask)
7341 if (M >= SourceOffset && M < SourceOffset + 4) {
7342 M = M - SourceOffset + DestOffset;
7343 assert(M >= 0 && "This should never wrap below zero!");
7348 // Ensure we have the input in a viable dword of its current half. This
7349 // is particularly tricky because the original position may be clobbered
7350 // by inputs being moved and *staying* in that half.
7351 if (IncomingInputs.size() == 1) {
7352 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7353 int InputFixed = std::find(std::begin(SourceHalfMask),
7354 std::end(SourceHalfMask), -1) -
7355 std::begin(SourceHalfMask) + SourceOffset;
7356 SourceHalfMask[InputFixed - SourceOffset] =
7357 IncomingInputs[0] - SourceOffset;
7358 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7360 IncomingInputs[0] = InputFixed;
7362 } else if (IncomingInputs.size() == 2) {
7363 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7364 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7365 int SourceDWordBase = !isDWordClobbered(SourceHalfMask, 0) ? 0 : 2;
7366 assert(!isDWordClobbered(SourceHalfMask, SourceDWordBase) &&
7367 "Not all dwords can be clobbered!");
7368 SourceHalfMask[SourceDWordBase] = IncomingInputs[0] - SourceOffset;
7369 SourceHalfMask[SourceDWordBase + 1] = IncomingInputs[1] - SourceOffset;
7370 for (int &M : HalfMask)
7371 if (M == IncomingInputs[0])
7372 M = SourceDWordBase + SourceOffset;
7373 else if (M == IncomingInputs[1])
7374 M = SourceDWordBase + 1 + SourceOffset;
7375 IncomingInputs[0] = SourceDWordBase + SourceOffset;
7376 IncomingInputs[1] = SourceDWordBase + 1 + SourceOffset;
7379 llvm_unreachable("Unhandled input size!");
7382 // Now hoist the DWord down to the right half.
7383 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7384 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7385 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7386 for (int Input : IncomingInputs)
7387 std::replace(HalfMask.begin(), HalfMask.end(), Input,
7388 FreeDWord * 2 + Input % 2);
7390 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask,
7391 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7392 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask,
7393 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7395 // Now enact all the shuffles we've computed to move the inputs into their
7397 if (!isNoopShuffleMask(PSHUFLMask))
7398 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7399 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7400 if (!isNoopShuffleMask(PSHUFHMask))
7401 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7402 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7403 if (!isNoopShuffleMask(PSHUFDMask))
7404 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7405 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7406 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7407 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7409 // At this point, each half should contain all its inputs, and we can then
7410 // just shuffle them into their final position.
7411 assert(std::count_if(LoMask.begin(), LoMask.end(),
7412 [](int M) { return M >= 4; }) == 0 &&
7413 "Failed to lift all the high half inputs to the low mask!");
7414 assert(std::count_if(HiMask.begin(), HiMask.end(),
7415 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7416 "Failed to lift all the low half inputs to the high mask!");
7418 // Do a half shuffle for the low mask.
7419 if (!isNoopShuffleMask(LoMask))
7420 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7421 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7423 // Do a half shuffle with the high mask after shifting its values down.
7424 for (int &M : HiMask)
7427 if (!isNoopShuffleMask(HiMask))
7428 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7429 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7434 /// \brief Detect whether the mask pattern should be lowered through
7437 /// This essentially tests whether viewing the mask as an interleaving of two
7438 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7439 /// lowering it through interleaving is a significantly better strategy.
7440 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7441 int NumEvenInputs[2] = {0, 0};
7442 int NumOddInputs[2] = {0, 0};
7443 int NumLoInputs[2] = {0, 0};
7444 int NumHiInputs[2] = {0, 0};
7445 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7449 int InputIdx = Mask[i] >= Size;
7452 ++NumLoInputs[InputIdx];
7454 ++NumHiInputs[InputIdx];
7457 ++NumEvenInputs[InputIdx];
7459 ++NumOddInputs[InputIdx];
7462 // The minimum number of cross-input results for both the interleaved and
7463 // split cases. If interleaving results in fewer cross-input results, return
7465 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7466 NumEvenInputs[0] + NumOddInputs[1]);
7467 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7468 NumLoInputs[0] + NumHiInputs[1]);
7469 return InterleavedCrosses < SplitCrosses;
7472 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7474 /// This strategy only works when the inputs from each vector fit into a single
7475 /// half of that vector, and generally there are not so many inputs as to leave
7476 /// the in-place shuffles required highly constrained (and thus expensive). It
7477 /// shifts all the inputs into a single side of both input vectors and then
7478 /// uses an unpack to interleave these inputs in a single vector. At that
7479 /// point, we will fall back on the generic single input shuffle lowering.
7480 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7482 MutableArrayRef<int> Mask,
7483 const X86Subtarget *Subtarget,
7484 SelectionDAG &DAG) {
7485 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7486 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7487 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7488 for (int i = 0; i < 8; ++i)
7489 if (Mask[i] >= 0 && Mask[i] < 4)
7490 LoV1Inputs.push_back(i);
7491 else if (Mask[i] >= 4 && Mask[i] < 8)
7492 HiV1Inputs.push_back(i);
7493 else if (Mask[i] >= 8 && Mask[i] < 12)
7494 LoV2Inputs.push_back(i);
7495 else if (Mask[i] >= 12)
7496 HiV2Inputs.push_back(i);
7498 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7499 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7502 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7503 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7504 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7506 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7507 HiV1Inputs.size() + HiV2Inputs.size();
7509 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7510 ArrayRef<int> HiInputs, bool MoveToLo,
7512 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7513 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7514 if (BadInputs.empty())
7517 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7518 int MoveOffset = MoveToLo ? 0 : 4;
7520 if (GoodInputs.empty()) {
7521 for (int BadInput : BadInputs) {
7522 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7523 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7526 if (GoodInputs.size() == 2) {
7527 // If the low inputs are spread across two dwords, pack them into
7529 MoveMask[Mask[GoodInputs[0]] % 2 + MoveOffset] =
7530 Mask[GoodInputs[0]] - MaskOffset;
7531 MoveMask[Mask[GoodInputs[1]] % 2 + MoveOffset] =
7532 Mask[GoodInputs[1]] - MaskOffset;
7533 Mask[GoodInputs[0]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7534 Mask[GoodInputs[1]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7536 // Otherwise pin the low inputs.
7537 for (int GoodInput : GoodInputs)
7538 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7542 std::find(std::begin(MoveMask) + MoveOffset, std::end(MoveMask), -1) -
7543 std::begin(MoveMask);
7544 assert(MoveMaskIdx >= MoveOffset && "Established above");
7546 if (BadInputs.size() == 2) {
7547 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7548 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7549 MoveMask[MoveMaskIdx + Mask[BadInputs[0]] % 2] =
7550 Mask[BadInputs[0]] - MaskOffset;
7551 MoveMask[MoveMaskIdx + Mask[BadInputs[1]] % 2] =
7552 Mask[BadInputs[1]] - MaskOffset;
7553 Mask[BadInputs[0]] = MoveMaskIdx + Mask[BadInputs[0]] % 2 + MaskOffset;
7554 Mask[BadInputs[1]] = MoveMaskIdx + Mask[BadInputs[1]] % 2 + MaskOffset;
7556 assert(BadInputs.size() == 1 && "All sizes handled");
7557 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7558 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7562 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7565 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7567 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7570 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7571 // cross-half traffic in the final shuffle.
7573 // Munge the mask to be a single-input mask after the unpack merges the
7577 M = 2 * (M % 4) + (M / 8);
7579 return DAG.getVectorShuffle(
7580 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7581 DL, MVT::v8i16, V1, V2),
7582 DAG.getUNDEF(MVT::v8i16), Mask);
7585 /// \brief Generic lowering of 8-lane i16 shuffles.
7587 /// This handles both single-input shuffles and combined shuffle/blends with
7588 /// two inputs. The single input shuffles are immediately delegated to
7589 /// a dedicated lowering routine.
7591 /// The blends are lowered in one of three fundamental ways. If there are few
7592 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7593 /// of the input is significantly cheaper when lowered as an interleaving of
7594 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7595 /// halves of the inputs separately (making them have relatively few inputs)
7596 /// and then concatenate them.
7597 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7598 const X86Subtarget *Subtarget,
7599 SelectionDAG &DAG) {
7601 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7602 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7603 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7604 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7605 ArrayRef<int> OrigMask = SVOp->getMask();
7606 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7607 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7608 MutableArrayRef<int> Mask(MaskStorage);
7610 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7612 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7613 auto isV2 = [](int M) { return M >= 8; };
7615 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7616 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7618 if (NumV2Inputs == 0)
7619 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7621 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7622 "to be V1-input shuffles.");
7624 if (NumV1Inputs + NumV2Inputs <= 4)
7625 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7627 // Check whether an interleaving lowering is likely to be more efficient.
7628 // This isn't perfect but it is a strong heuristic that tends to work well on
7629 // the kinds of shuffles that show up in practice.
7631 // FIXME: Handle 1x, 2x, and 4x interleaving.
7632 if (shouldLowerAsInterleaving(Mask)) {
7633 // FIXME: Figure out whether we should pack these into the low or high
7636 int EMask[8], OMask[8];
7637 for (int i = 0; i < 4; ++i) {
7638 EMask[i] = Mask[2*i];
7639 OMask[i] = Mask[2*i + 1];
7644 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7645 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7647 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7650 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7651 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7653 for (int i = 0; i < 4; ++i) {
7654 LoBlendMask[i] = Mask[i];
7655 HiBlendMask[i] = Mask[i + 4];
7658 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7659 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7660 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7661 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7663 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7664 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7667 /// \brief Generic lowering of v16i8 shuffles.
7669 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7670 /// detect any complexity reducing interleaving. If that doesn't help, it uses
7671 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
7672 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
7674 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7675 const X86Subtarget *Subtarget,
7676 SelectionDAG &DAG) {
7678 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7679 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7680 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7681 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7682 ArrayRef<int> OrigMask = SVOp->getMask();
7683 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
7684 int MaskStorage[16] = {
7685 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7686 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
7687 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
7688 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
7689 MutableArrayRef<int> Mask(MaskStorage);
7690 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
7691 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
7693 // For single-input shuffles, there are some nicer lowering tricks we can use.
7694 if (isSingleInputShuffleMask(Mask)) {
7695 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
7696 // Notably, this handles splat and partial-splat shuffles more efficiently.
7698 // FIXME: We should check for other patterns which can be widened into an
7699 // i16 shuffle as well.
7700 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
7701 for (int i = 0; i < 16; i += 2) {
7702 if (Mask[i] != Mask[i + 1])
7707 if (canWidenViaDuplication(Mask)) {
7708 SmallVector<int, 4> LoInputs;
7709 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
7710 [](int M) { return M >= 0 && M < 8; });
7711 std::sort(LoInputs.begin(), LoInputs.end());
7712 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
7714 SmallVector<int, 4> HiInputs;
7715 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
7716 [](int M) { return M >= 8; });
7717 std::sort(HiInputs.begin(), HiInputs.end());
7718 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
7721 bool TargetLo = LoInputs.size() >= HiInputs.size();
7722 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
7723 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
7726 SmallDenseMap<int, int, 8> LaneMap;
7727 for (int i = 0; i < 16; ++i)
7729 for (int I : InPlaceInputs) {
7733 int FreeByteIdx = 0;
7734 int TargetOffset = TargetLo ? 0 : 8;
7735 for (int I : MovingInputs) {
7736 // Walk the free index into the byte mask until we find an unoccupied
7737 // spot. We bound this to 8 steps to catch bugs, the pigeonhole
7738 // principle indicates that there *must* be a spot as we can only have
7739 // 8 duplicated inputs. We have to walk the index using modular
7740 // arithmetic to wrap around as necessary.
7741 // FIXME: We could do a much better job of picking an inexpensive slot
7742 // so this doesn't go through the worst case for the byte shuffle.
7743 for (int j = 0; j < 8 && ByteMask[FreeByteIdx + TargetOffset] != -1;
7744 ++j, FreeByteIdx = (FreeByteIdx + 1) % 8)
7746 assert(ByteMask[FreeByteIdx + TargetOffset] == -1 &&
7747 "Failed to find a free byte!");
7748 ByteMask[FreeByteIdx + TargetOffset] = I;
7749 LaneMap[I] = FreeByteIdx + TargetOffset;
7751 V1 = DAG.getVectorShuffle(MVT::v16i8, DL, V1, DAG.getUNDEF(MVT::v16i8),
7757 // Unpack the bytes to form the i16s that will be shuffled into place.
7758 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7759 MVT::v16i8, V1, V1);
7761 int I16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7762 for (int i = 0; i < 16; i += 2) {
7764 I16Shuffle[i / 2] = Mask[i] - (TargetLo ? 0 : 8);
7765 assert(I16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
7767 return DAG.getVectorShuffle(MVT::v8i16, DL,
7768 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7769 DAG.getUNDEF(MVT::v8i16), I16Shuffle);
7773 // Check whether an interleaving lowering is likely to be more efficient.
7774 // This isn't perfect but it is a strong heuristic that tends to work well on
7775 // the kinds of shuffles that show up in practice.
7777 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
7778 if (shouldLowerAsInterleaving(Mask)) {
7779 // FIXME: Figure out whether we should pack these into the low or high
7782 int EMask[16], OMask[16];
7783 for (int i = 0; i < 8; ++i) {
7784 EMask[i] = Mask[2*i];
7785 OMask[i] = Mask[2*i + 1];
7790 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
7791 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
7793 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
7795 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
7797 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7798 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, Zero));
7800 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7801 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, Zero));
7803 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7804 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V2, Zero));
7806 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7807 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V2, Zero));
7809 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7810 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7811 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7812 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7814 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
7815 MutableArrayRef<int> V1HalfBlendMask,
7816 MutableArrayRef<int> V2HalfBlendMask) {
7817 for (int i = 0; i < 8; ++i)
7818 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
7819 V1HalfBlendMask[i] = HalfMask[i];
7821 } else if (HalfMask[i] >= 16) {
7822 V2HalfBlendMask[i] = HalfMask[i] - 16;
7823 HalfMask[i] = i + 8;
7826 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
7827 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
7829 SDValue V1Lo = DAG.getVectorShuffle(MVT::v8i16, DL, LoV1, HiV1, V1LoBlendMask);
7830 SDValue V2Lo = DAG.getVectorShuffle(MVT::v8i16, DL, LoV2, HiV2, V2LoBlendMask);
7831 SDValue V1Hi = DAG.getVectorShuffle(MVT::v8i16, DL, LoV1, HiV1, V1HiBlendMask);
7832 SDValue V2Hi = DAG.getVectorShuffle(MVT::v8i16, DL, LoV2, HiV2, V2HiBlendMask);
7834 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
7835 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
7837 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
7840 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
7842 /// This routine breaks down the specific type of 128-bit shuffle and
7843 /// dispatches to the lowering routines accordingly.
7844 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7845 MVT VT, const X86Subtarget *Subtarget,
7846 SelectionDAG &DAG) {
7847 switch (VT.SimpleTy) {
7849 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7851 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7853 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7855 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7857 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
7859 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
7862 llvm_unreachable("Unimplemented!");
7866 /// \brief Tiny helper function to test whether adjacent masks are sequential.
7867 static bool areAdjacentMasksSequential(ArrayRef<int> Mask) {
7868 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7869 if (Mask[i] + 1 != Mask[i+1])
7875 /// \brief Top-level lowering for x86 vector shuffles.
7877 /// This handles decomposition, canonicalization, and lowering of all x86
7878 /// vector shuffles. Most of the specific lowering strategies are encapsulated
7879 /// above in helper routines. The canonicalization attempts to widen shuffles
7880 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
7881 /// s.t. only one of the two inputs needs to be tested, etc.
7882 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7883 SelectionDAG &DAG) {
7884 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7885 ArrayRef<int> Mask = SVOp->getMask();
7886 SDValue V1 = Op.getOperand(0);
7887 SDValue V2 = Op.getOperand(1);
7888 MVT VT = Op.getSimpleValueType();
7889 int NumElements = VT.getVectorNumElements();
7892 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7894 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7895 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7896 if (V1IsUndef && V2IsUndef)
7897 return DAG.getUNDEF(VT);
7899 // When we create a shuffle node we put the UNDEF node to second operand,
7900 // but in some cases the first operand may be transformed to UNDEF.
7901 // In this case we should just commute the node.
7903 return CommuteVectorShuffle(SVOp, DAG);
7905 // Check for non-undef masks pointing at an undef vector and make the masks
7906 // undef as well. This makes it easier to match the shuffle based solely on
7910 if (M >= NumElements) {
7911 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
7912 for (int &M : NewMask)
7913 if (M >= NumElements)
7915 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
7918 // For integer vector shuffles, try to collapse them into a shuffle of fewer
7919 // lanes but wider integers. We cap this to not form integers larger than i64
7920 // but it might be interesting to form i128 integers to handle flipping the
7921 // low and high halves of AVX 256-bit vectors.
7922 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
7923 areAdjacentMasksSequential(Mask)) {
7924 SmallVector<int, 8> NewMask;
7925 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7926 NewMask.push_back(Mask[i] / 2);
7928 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
7929 VT.getVectorNumElements() / 2);
7930 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
7931 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
7932 return DAG.getNode(ISD::BITCAST, dl, VT,
7933 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
7936 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
7937 for (int M : SVOp->getMask())
7940 else if (M < NumElements)
7945 // Commute the shuffle as needed such that more elements come from V1 than
7946 // V2. This allows us to match the shuffle pattern strictly on how many
7947 // elements come from V1 without handling the symmetric cases.
7948 if (NumV2Elements > NumV1Elements)
7949 return CommuteVectorShuffle(SVOp, DAG);
7951 // When the number of V1 and V2 elements are the same, try to minimize the
7952 // number of uses of V2 in the low half of the vector.
7953 if (NumV1Elements == NumV2Elements) {
7954 int LowV1Elements = 0, LowV2Elements = 0;
7955 for (int M : SVOp->getMask().slice(0, NumElements / 2))
7956 if (M >= NumElements)
7960 if (LowV2Elements > LowV1Elements)
7961 return CommuteVectorShuffle(SVOp, DAG);
7964 // For each vector width, delegate to a specialized lowering routine.
7965 if (VT.getSizeInBits() == 128)
7966 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
7968 llvm_unreachable("Unimplemented!");
7972 //===----------------------------------------------------------------------===//
7973 // Legacy vector shuffle lowering
7975 // This code is the legacy code handling vector shuffles until the above
7976 // replaces its functionality and performance.
7977 //===----------------------------------------------------------------------===//
7979 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
7980 bool hasInt256, unsigned *MaskOut = nullptr) {
7981 MVT EltVT = VT.getVectorElementType();
7983 // There is no blend with immediate in AVX-512.
7984 if (VT.is512BitVector())
7987 if (!hasSSE41 || EltVT == MVT::i8)
7989 if (!hasInt256 && VT == MVT::v16i16)
7992 unsigned MaskValue = 0;
7993 unsigned NumElems = VT.getVectorNumElements();
7994 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
7995 unsigned NumLanes = (NumElems - 1) / 8 + 1;
7996 unsigned NumElemsInLane = NumElems / NumLanes;
7998 // Blend for v16i16 should be symetric for the both lanes.
7999 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8001 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8002 int EltIdx = MaskVals[i];
8004 if ((EltIdx < 0 || EltIdx == (int)i) &&
8005 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8008 if (((unsigned)EltIdx == (i + NumElems)) &&
8009 (SndLaneEltIdx < 0 ||
8010 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8011 MaskValue |= (1 << i);
8017 *MaskOut = MaskValue;
8021 // Try to lower a shuffle node into a simple blend instruction.
8022 // This function assumes isBlendMask returns true for this
8023 // SuffleVectorSDNode
8024 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8026 const X86Subtarget *Subtarget,
8027 SelectionDAG &DAG) {
8028 MVT VT = SVOp->getSimpleValueType(0);
8029 MVT EltVT = VT.getVectorElementType();
8030 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8031 Subtarget->hasInt256() && "Trying to lower a "
8032 "VECTOR_SHUFFLE to a Blend but "
8033 "with the wrong mask"));
8034 SDValue V1 = SVOp->getOperand(0);
8035 SDValue V2 = SVOp->getOperand(1);
8037 unsigned NumElems = VT.getVectorNumElements();
8039 // Convert i32 vectors to floating point if it is not AVX2.
8040 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8042 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8043 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8045 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8046 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8049 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8050 DAG.getConstant(MaskValue, MVT::i32));
8051 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8054 /// In vector type \p VT, return true if the element at index \p InputIdx
8055 /// falls on a different 128-bit lane than \p OutputIdx.
8056 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8057 unsigned OutputIdx) {
8058 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8059 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8062 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8063 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8064 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8065 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8067 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8068 SelectionDAG &DAG) {
8069 MVT VT = V1.getSimpleValueType();
8070 assert(VT.is128BitVector() || VT.is256BitVector());
8072 MVT EltVT = VT.getVectorElementType();
8073 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8074 unsigned NumElts = VT.getVectorNumElements();
8076 SmallVector<SDValue, 32> PshufbMask;
8077 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8078 int InputIdx = MaskVals[OutputIdx];
8079 unsigned InputByteIdx;
8081 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8082 InputByteIdx = 0x80;
8084 // Cross lane is not allowed.
8085 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8087 InputByteIdx = InputIdx * EltSizeInBytes;
8088 // Index is an byte offset within the 128-bit lane.
8089 InputByteIdx &= 0xf;
8092 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8093 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8094 if (InputByteIdx != 0x80)
8099 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8101 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8102 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8103 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8106 // v8i16 shuffles - Prefer shuffles in the following order:
8107 // 1. [all] pshuflw, pshufhw, optional move
8108 // 2. [ssse3] 1 x pshufb
8109 // 3. [ssse3] 2 x pshufb + 1 x por
8110 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8112 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8113 SelectionDAG &DAG) {
8114 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8115 SDValue V1 = SVOp->getOperand(0);
8116 SDValue V2 = SVOp->getOperand(1);
8118 SmallVector<int, 8> MaskVals;
8120 // Determine if more than 1 of the words in each of the low and high quadwords
8121 // of the result come from the same quadword of one of the two inputs. Undef
8122 // mask values count as coming from any quadword, for better codegen.
8124 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8125 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8126 unsigned LoQuad[] = { 0, 0, 0, 0 };
8127 unsigned HiQuad[] = { 0, 0, 0, 0 };
8128 // Indices of quads used.
8129 std::bitset<4> InputQuads;
8130 for (unsigned i = 0; i < 8; ++i) {
8131 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8132 int EltIdx = SVOp->getMaskElt(i);
8133 MaskVals.push_back(EltIdx);
8142 InputQuads.set(EltIdx / 4);
8145 int BestLoQuad = -1;
8146 unsigned MaxQuad = 1;
8147 for (unsigned i = 0; i < 4; ++i) {
8148 if (LoQuad[i] > MaxQuad) {
8150 MaxQuad = LoQuad[i];
8154 int BestHiQuad = -1;
8156 for (unsigned i = 0; i < 4; ++i) {
8157 if (HiQuad[i] > MaxQuad) {
8159 MaxQuad = HiQuad[i];
8163 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8164 // of the two input vectors, shuffle them into one input vector so only a
8165 // single pshufb instruction is necessary. If there are more than 2 input
8166 // quads, disable the next transformation since it does not help SSSE3.
8167 bool V1Used = InputQuads[0] || InputQuads[1];
8168 bool V2Used = InputQuads[2] || InputQuads[3];
8169 if (Subtarget->hasSSSE3()) {
8170 if (InputQuads.count() == 2 && V1Used && V2Used) {
8171 BestLoQuad = InputQuads[0] ? 0 : 1;
8172 BestHiQuad = InputQuads[2] ? 2 : 3;
8174 if (InputQuads.count() > 2) {
8180 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8181 // the shuffle mask. If a quad is scored as -1, that means that it contains
8182 // words from all 4 input quadwords.
8184 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8186 BestLoQuad < 0 ? 0 : BestLoQuad,
8187 BestHiQuad < 0 ? 1 : BestHiQuad
8189 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8190 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8191 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8192 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8194 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8195 // source words for the shuffle, to aid later transformations.
8196 bool AllWordsInNewV = true;
8197 bool InOrder[2] = { true, true };
8198 for (unsigned i = 0; i != 8; ++i) {
8199 int idx = MaskVals[i];
8201 InOrder[i/4] = false;
8202 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8204 AllWordsInNewV = false;
8208 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8209 if (AllWordsInNewV) {
8210 for (int i = 0; i != 8; ++i) {
8211 int idx = MaskVals[i];
8214 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8215 if ((idx != i) && idx < 4)
8217 if ((idx != i) && idx > 3)
8226 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8227 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8228 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8229 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8230 unsigned TargetMask = 0;
8231 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8232 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8233 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8234 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8235 getShufflePSHUFLWImmediate(SVOp);
8236 V1 = NewV.getOperand(0);
8237 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8241 // Promote splats to a larger type which usually leads to more efficient code.
8242 // FIXME: Is this true if pshufb is available?
8243 if (SVOp->isSplat())
8244 return PromoteSplat(SVOp, DAG);
8246 // If we have SSSE3, and all words of the result are from 1 input vector,
8247 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8248 // is present, fall back to case 4.
8249 if (Subtarget->hasSSSE3()) {
8250 SmallVector<SDValue,16> pshufbMask;
8252 // If we have elements from both input vectors, set the high bit of the
8253 // shuffle mask element to zero out elements that come from V2 in the V1
8254 // mask, and elements that come from V1 in the V2 mask, so that the two
8255 // results can be OR'd together.
8256 bool TwoInputs = V1Used && V2Used;
8257 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8259 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8261 // Calculate the shuffle mask for the second input, shuffle it, and
8262 // OR it with the first shuffled input.
8263 CommuteVectorShuffleMask(MaskVals, 8);
8264 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8265 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8266 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8269 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8270 // and update MaskVals with new element order.
8271 std::bitset<8> InOrder;
8272 if (BestLoQuad >= 0) {
8273 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8274 for (int i = 0; i != 4; ++i) {
8275 int idx = MaskVals[i];
8278 } else if ((idx / 4) == BestLoQuad) {
8283 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8286 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8287 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8288 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8290 getShufflePSHUFLWImmediate(SVOp), DAG);
8294 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8295 // and update MaskVals with the new element order.
8296 if (BestHiQuad >= 0) {
8297 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8298 for (unsigned i = 4; i != 8; ++i) {
8299 int idx = MaskVals[i];
8302 } else if ((idx / 4) == BestHiQuad) {
8303 MaskV[i] = (idx & 3) + 4;
8307 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8310 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8312 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8314 getShufflePSHUFHWImmediate(SVOp), DAG);
8318 // In case BestHi & BestLo were both -1, which means each quadword has a word
8319 // from each of the four input quadwords, calculate the InOrder bitvector now
8320 // before falling through to the insert/extract cleanup.
8321 if (BestLoQuad == -1 && BestHiQuad == -1) {
8323 for (int i = 0; i != 8; ++i)
8324 if (MaskVals[i] < 0 || MaskVals[i] == i)
8328 // The other elements are put in the right place using pextrw and pinsrw.
8329 for (unsigned i = 0; i != 8; ++i) {
8332 int EltIdx = MaskVals[i];
8335 SDValue ExtOp = (EltIdx < 8) ?
8336 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8337 DAG.getIntPtrConstant(EltIdx)) :
8338 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8339 DAG.getIntPtrConstant(EltIdx - 8));
8340 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8341 DAG.getIntPtrConstant(i));
8346 /// \brief v16i16 shuffles
8348 /// FIXME: We only support generation of a single pshufb currently. We can
8349 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8350 /// well (e.g 2 x pshufb + 1 x por).
8352 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8354 SDValue V1 = SVOp->getOperand(0);
8355 SDValue V2 = SVOp->getOperand(1);
8358 if (V2.getOpcode() != ISD::UNDEF)
8361 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8362 return getPSHUFB(MaskVals, V1, dl, DAG);
8365 // v16i8 shuffles - Prefer shuffles in the following order:
8366 // 1. [ssse3] 1 x pshufb
8367 // 2. [ssse3] 2 x pshufb + 1 x por
8368 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8369 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8370 const X86Subtarget* Subtarget,
8371 SelectionDAG &DAG) {
8372 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8373 SDValue V1 = SVOp->getOperand(0);
8374 SDValue V2 = SVOp->getOperand(1);
8376 ArrayRef<int> MaskVals = SVOp->getMask();
8378 // Promote splats to a larger type which usually leads to more efficient code.
8379 // FIXME: Is this true if pshufb is available?
8380 if (SVOp->isSplat())
8381 return PromoteSplat(SVOp, DAG);
8383 // If we have SSSE3, case 1 is generated when all result bytes come from
8384 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8385 // present, fall back to case 3.
8387 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8388 if (Subtarget->hasSSSE3()) {
8389 SmallVector<SDValue,16> pshufbMask;
8391 // If all result elements are from one input vector, then only translate
8392 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8394 // Otherwise, we have elements from both input vectors, and must zero out
8395 // elements that come from V2 in the first mask, and V1 in the second mask
8396 // so that we can OR them together.
8397 for (unsigned i = 0; i != 16; ++i) {
8398 int EltIdx = MaskVals[i];
8399 if (EltIdx < 0 || EltIdx >= 16)
8401 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8403 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8404 DAG.getNode(ISD::BUILD_VECTOR, dl,
8405 MVT::v16i8, pshufbMask));
8407 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8408 // the 2nd operand if it's undefined or zero.
8409 if (V2.getOpcode() == ISD::UNDEF ||
8410 ISD::isBuildVectorAllZeros(V2.getNode()))
8413 // Calculate the shuffle mask for the second input, shuffle it, and
8414 // OR it with the first shuffled input.
8416 for (unsigned i = 0; i != 16; ++i) {
8417 int EltIdx = MaskVals[i];
8418 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8419 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8421 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8422 DAG.getNode(ISD::BUILD_VECTOR, dl,
8423 MVT::v16i8, pshufbMask));
8424 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8427 // No SSSE3 - Calculate in place words and then fix all out of place words
8428 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8429 // the 16 different words that comprise the two doublequadword input vectors.
8430 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8431 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8433 for (int i = 0; i != 8; ++i) {
8434 int Elt0 = MaskVals[i*2];
8435 int Elt1 = MaskVals[i*2+1];
8437 // This word of the result is all undef, skip it.
8438 if (Elt0 < 0 && Elt1 < 0)
8441 // This word of the result is already in the correct place, skip it.
8442 if ((Elt0 == i*2) && (Elt1 == i*2+1))
8445 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8446 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8449 // If Elt0 and Elt1 are defined, are consecutive, and can be load
8450 // using a single extract together, load it and store it.
8451 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
8452 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8453 DAG.getIntPtrConstant(Elt1 / 2));
8454 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8455 DAG.getIntPtrConstant(i));
8459 // If Elt1 is defined, extract it from the appropriate source. If the
8460 // source byte is not also odd, shift the extracted word left 8 bits
8461 // otherwise clear the bottom 8 bits if we need to do an or.
8463 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8464 DAG.getIntPtrConstant(Elt1 / 2));
8465 if ((Elt1 & 1) == 0)
8466 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
8468 TLI.getShiftAmountTy(InsElt.getValueType())));
8470 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
8471 DAG.getConstant(0xFF00, MVT::i16));
8473 // If Elt0 is defined, extract it from the appropriate source. If the
8474 // source byte is not also even, shift the extracted word right 8 bits. If
8475 // Elt1 was also defined, OR the extracted values together before
8476 // inserting them in the result.
8478 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
8479 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
8480 if ((Elt0 & 1) != 0)
8481 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8483 TLI.getShiftAmountTy(InsElt0.getValueType())));
8485 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
8486 DAG.getConstant(0x00FF, MVT::i16));
8487 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
8490 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8491 DAG.getIntPtrConstant(i));
8493 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8496 // v32i8 shuffles - Translate to VPSHUFB if possible.
8498 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
8499 const X86Subtarget *Subtarget,
8500 SelectionDAG &DAG) {
8501 MVT VT = SVOp->getSimpleValueType(0);
8502 SDValue V1 = SVOp->getOperand(0);
8503 SDValue V2 = SVOp->getOperand(1);
8505 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8507 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8508 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
8509 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8511 // VPSHUFB may be generated if
8512 // (1) one of input vector is undefined or zeroinitializer.
8513 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
8514 // And (2) the mask indexes don't cross the 128-bit lane.
8515 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
8516 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
8519 if (V1IsAllZero && !V2IsAllZero) {
8520 CommuteVectorShuffleMask(MaskVals, 32);
8523 return getPSHUFB(MaskVals, V1, dl, DAG);
8526 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8527 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8528 /// done when every pair / quad of shuffle mask elements point to elements in
8529 /// the right sequence. e.g.
8530 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
8532 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
8533 SelectionDAG &DAG) {
8534 MVT VT = SVOp->getSimpleValueType(0);
8536 unsigned NumElems = VT.getVectorNumElements();
8539 switch (VT.SimpleTy) {
8540 default: llvm_unreachable("Unexpected!");
8543 return SDValue(SVOp, 0);
8544 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
8545 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8546 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8547 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8548 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8549 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
8552 SmallVector<int, 8> MaskVec;
8553 for (unsigned i = 0; i != NumElems; i += Scale) {
8555 for (unsigned j = 0; j != Scale; ++j) {
8556 int EltIdx = SVOp->getMaskElt(i+j);
8560 StartIdx = (EltIdx / Scale);
8561 if (EltIdx != (int)(StartIdx*Scale + j))
8564 MaskVec.push_back(StartIdx);
8567 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
8568 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8569 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8572 /// getVZextMovL - Return a zero-extending vector move low node.
8574 static SDValue getVZextMovL(MVT VT, MVT OpVT,
8575 SDValue SrcOp, SelectionDAG &DAG,
8576 const X86Subtarget *Subtarget, SDLoc dl) {
8577 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
8578 LoadSDNode *LD = nullptr;
8579 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
8580 LD = dyn_cast<LoadSDNode>(SrcOp);
8582 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
8584 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
8585 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
8586 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8587 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
8588 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
8590 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8591 return DAG.getNode(ISD::BITCAST, dl, VT,
8592 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8593 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8601 return DAG.getNode(ISD::BITCAST, dl, VT,
8602 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8603 DAG.getNode(ISD::BITCAST, dl,
8607 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
8608 /// which could not be matched by any known target speficic shuffle
8610 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8612 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
8613 if (NewOp.getNode())
8616 MVT VT = SVOp->getSimpleValueType(0);
8618 unsigned NumElems = VT.getVectorNumElements();
8619 unsigned NumLaneElems = NumElems / 2;
8622 MVT EltVT = VT.getVectorElementType();
8623 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
8626 SmallVector<int, 16> Mask;
8627 for (unsigned l = 0; l < 2; ++l) {
8628 // Build a shuffle mask for the output, discovering on the fly which
8629 // input vectors to use as shuffle operands (recorded in InputUsed).
8630 // If building a suitable shuffle vector proves too hard, then bail
8631 // out with UseBuildVector set.
8632 bool UseBuildVector = false;
8633 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
8634 unsigned LaneStart = l * NumLaneElems;
8635 for (unsigned i = 0; i != NumLaneElems; ++i) {
8636 // The mask element. This indexes into the input.
8637 int Idx = SVOp->getMaskElt(i+LaneStart);
8639 // the mask element does not index into any input vector.
8644 // The input vector this mask element indexes into.
8645 int Input = Idx / NumLaneElems;
8647 // Turn the index into an offset from the start of the input vector.
8648 Idx -= Input * NumLaneElems;
8650 // Find or create a shuffle vector operand to hold this input.
8652 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
8653 if (InputUsed[OpNo] == Input)
8654 // This input vector is already an operand.
8656 if (InputUsed[OpNo] < 0) {
8657 // Create a new operand for this input vector.
8658 InputUsed[OpNo] = Input;
8663 if (OpNo >= array_lengthof(InputUsed)) {
8664 // More than two input vectors used! Give up on trying to create a
8665 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
8666 UseBuildVector = true;
8670 // Add the mask index for the new shuffle vector.
8671 Mask.push_back(Idx + OpNo * NumLaneElems);
8674 if (UseBuildVector) {
8675 SmallVector<SDValue, 16> SVOps;
8676 for (unsigned i = 0; i != NumLaneElems; ++i) {
8677 // The mask element. This indexes into the input.
8678 int Idx = SVOp->getMaskElt(i+LaneStart);
8680 SVOps.push_back(DAG.getUNDEF(EltVT));
8684 // The input vector this mask element indexes into.
8685 int Input = Idx / NumElems;
8687 // Turn the index into an offset from the start of the input vector.
8688 Idx -= Input * NumElems;
8690 // Extract the vector element by hand.
8691 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
8692 SVOp->getOperand(Input),
8693 DAG.getIntPtrConstant(Idx)));
8696 // Construct the output using a BUILD_VECTOR.
8697 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
8698 } else if (InputUsed[0] < 0) {
8699 // No input vectors were used! The result is undefined.
8700 Output[l] = DAG.getUNDEF(NVT);
8702 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
8703 (InputUsed[0] % 2) * NumLaneElems,
8705 // If only one input was used, use an undefined vector for the other.
8706 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
8707 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
8708 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
8709 // At least one input vector was used. Create a new shuffle vector.
8710 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
8716 // Concatenate the result back
8717 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
8720 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
8721 /// 4 elements, and match them with several different shuffle types.
8723 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8724 SDValue V1 = SVOp->getOperand(0);
8725 SDValue V2 = SVOp->getOperand(1);
8727 MVT VT = SVOp->getSimpleValueType(0);
8729 assert(VT.is128BitVector() && "Unsupported vector size");
8731 std::pair<int, int> Locs[4];
8732 int Mask1[] = { -1, -1, -1, -1 };
8733 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
8737 for (unsigned i = 0; i != 4; ++i) {
8738 int Idx = PermMask[i];
8740 Locs[i] = std::make_pair(-1, -1);
8742 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
8744 Locs[i] = std::make_pair(0, NumLo);
8748 Locs[i] = std::make_pair(1, NumHi);
8750 Mask1[2+NumHi] = Idx;
8756 if (NumLo <= 2 && NumHi <= 2) {
8757 // If no more than two elements come from either vector. This can be
8758 // implemented with two shuffles. First shuffle gather the elements.
8759 // The second shuffle, which takes the first shuffle as both of its
8760 // vector operands, put the elements into the right order.
8761 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8763 int Mask2[] = { -1, -1, -1, -1 };
8765 for (unsigned i = 0; i != 4; ++i)
8766 if (Locs[i].first != -1) {
8767 unsigned Idx = (i < 2) ? 0 : 4;
8768 Idx += Locs[i].first * 2 + Locs[i].second;
8772 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
8775 if (NumLo == 3 || NumHi == 3) {
8776 // Otherwise, we must have three elements from one vector, call it X, and
8777 // one element from the other, call it Y. First, use a shufps to build an
8778 // intermediate vector with the one element from Y and the element from X
8779 // that will be in the same half in the final destination (the indexes don't
8780 // matter). Then, use a shufps to build the final vector, taking the half
8781 // containing the element from Y from the intermediate, and the other half
8784 // Normalize it so the 3 elements come from V1.
8785 CommuteVectorShuffleMask(PermMask, 4);
8789 // Find the element from V2.
8791 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
8792 int Val = PermMask[HiIndex];
8799 Mask1[0] = PermMask[HiIndex];
8801 Mask1[2] = PermMask[HiIndex^1];
8803 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8806 Mask1[0] = PermMask[0];
8807 Mask1[1] = PermMask[1];
8808 Mask1[2] = HiIndex & 1 ? 6 : 4;
8809 Mask1[3] = HiIndex & 1 ? 4 : 6;
8810 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8813 Mask1[0] = HiIndex & 1 ? 2 : 0;
8814 Mask1[1] = HiIndex & 1 ? 0 : 2;
8815 Mask1[2] = PermMask[2];
8816 Mask1[3] = PermMask[3];
8821 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
8824 // Break it into (shuffle shuffle_hi, shuffle_lo).
8825 int LoMask[] = { -1, -1, -1, -1 };
8826 int HiMask[] = { -1, -1, -1, -1 };
8828 int *MaskPtr = LoMask;
8829 unsigned MaskIdx = 0;
8832 for (unsigned i = 0; i != 4; ++i) {
8839 int Idx = PermMask[i];
8841 Locs[i] = std::make_pair(-1, -1);
8842 } else if (Idx < 4) {
8843 Locs[i] = std::make_pair(MaskIdx, LoIdx);
8844 MaskPtr[LoIdx] = Idx;
8847 Locs[i] = std::make_pair(MaskIdx, HiIdx);
8848 MaskPtr[HiIdx] = Idx;
8853 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
8854 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
8855 int MaskOps[] = { -1, -1, -1, -1 };
8856 for (unsigned i = 0; i != 4; ++i)
8857 if (Locs[i].first != -1)
8858 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
8859 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
8862 static bool MayFoldVectorLoad(SDValue V) {
8863 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
8864 V = V.getOperand(0);
8866 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
8867 V = V.getOperand(0);
8868 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
8869 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
8870 // BUILD_VECTOR (load), undef
8871 V = V.getOperand(0);
8873 return MayFoldLoad(V);
8877 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
8878 MVT VT = Op.getSimpleValueType();
8880 // Canonizalize to v2f64.
8881 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
8882 return DAG.getNode(ISD::BITCAST, dl, VT,
8883 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
8888 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
8890 SDValue V1 = Op.getOperand(0);
8891 SDValue V2 = Op.getOperand(1);
8892 MVT VT = Op.getSimpleValueType();
8894 assert(VT != MVT::v2i64 && "unsupported shuffle type");
8896 if (HasSSE2 && VT == MVT::v2f64)
8897 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
8899 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
8900 return DAG.getNode(ISD::BITCAST, dl, VT,
8901 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
8902 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
8903 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
8907 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
8908 SDValue V1 = Op.getOperand(0);
8909 SDValue V2 = Op.getOperand(1);
8910 MVT VT = Op.getSimpleValueType();
8912 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
8913 "unsupported shuffle type");
8915 if (V2.getOpcode() == ISD::UNDEF)
8919 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
8923 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
8924 SDValue V1 = Op.getOperand(0);
8925 SDValue V2 = Op.getOperand(1);
8926 MVT VT = Op.getSimpleValueType();
8927 unsigned NumElems = VT.getVectorNumElements();
8929 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
8930 // operand of these instructions is only memory, so check if there's a
8931 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
8933 bool CanFoldLoad = false;
8935 // Trivial case, when V2 comes from a load.
8936 if (MayFoldVectorLoad(V2))
8939 // When V1 is a load, it can be folded later into a store in isel, example:
8940 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
8942 // (MOVLPSmr addr:$src1, VR128:$src2)
8943 // So, recognize this potential and also use MOVLPS or MOVLPD
8944 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
8947 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8949 if (HasSSE2 && NumElems == 2)
8950 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
8953 // If we don't care about the second element, proceed to use movss.
8954 if (SVOp->getMaskElt(1) != -1)
8955 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
8958 // movl and movlp will both match v2i64, but v2i64 is never matched by
8959 // movl earlier because we make it strict to avoid messing with the movlp load
8960 // folding logic (see the code above getMOVLP call). Match it here then,
8961 // this is horrible, but will stay like this until we move all shuffle
8962 // matching to x86 specific nodes. Note that for the 1st condition all
8963 // types are matched with movsd.
8965 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
8966 // as to remove this logic from here, as much as possible
8967 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
8968 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
8969 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
8972 assert(VT != MVT::v4i32 && "unsupported shuffle type");
8974 // Invert the operand order and use SHUFPS to match it.
8975 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
8976 getShuffleSHUFImmediate(SVOp), DAG);
8979 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
8980 SelectionDAG &DAG) {
8982 MVT VT = Load->getSimpleValueType(0);
8983 MVT EVT = VT.getVectorElementType();
8984 SDValue Addr = Load->getOperand(1);
8985 SDValue NewAddr = DAG.getNode(
8986 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
8987 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
8990 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
8991 DAG.getMachineFunction().getMachineMemOperand(
8992 Load->getMemOperand(), 0, EVT.getStoreSize()));
8996 // It is only safe to call this function if isINSERTPSMask is true for
8997 // this shufflevector mask.
8998 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
8999 SelectionDAG &DAG) {
9000 // Generate an insertps instruction when inserting an f32 from memory onto a
9001 // v4f32 or when copying a member from one v4f32 to another.
9002 // We also use it for transferring i32 from one register to another,
9003 // since it simply copies the same bits.
9004 // If we're transferring an i32 from memory to a specific element in a
9005 // register, we output a generic DAG that will match the PINSRD
9007 MVT VT = SVOp->getSimpleValueType(0);
9008 MVT EVT = VT.getVectorElementType();
9009 SDValue V1 = SVOp->getOperand(0);
9010 SDValue V2 = SVOp->getOperand(1);
9011 auto Mask = SVOp->getMask();
9012 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9013 "unsupported vector type for insertps/pinsrd");
9015 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9016 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9017 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9025 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9028 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9029 "More than one element from V1 and from V2, or no elements from one "
9030 "of the vectors. This case should not have returned true from "
9035 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9038 unsigned SrcIndex = Mask[DestIndex] % 4;
9039 if (MayFoldLoad(From)) {
9040 // Trivial case, when From comes from a load and is only used by the
9041 // shuffle. Make it use insertps from the vector that we need from that
9044 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9045 if (!NewLoad.getNode())
9048 if (EVT == MVT::f32) {
9049 // Create this as a scalar to vector to match the instruction pattern.
9050 SDValue LoadScalarToVector =
9051 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9052 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9053 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9055 } else { // EVT == MVT::i32
9056 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9057 // instruction, to match the PINSRD instruction, which loads an i32 to a
9058 // certain vector element.
9059 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9060 DAG.getConstant(DestIndex, MVT::i32));
9064 // Vector-element-to-vector
9065 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9066 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9069 // Reduce a vector shuffle to zext.
9070 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9071 SelectionDAG &DAG) {
9072 // PMOVZX is only available from SSE41.
9073 if (!Subtarget->hasSSE41())
9076 MVT VT = Op.getSimpleValueType();
9078 // Only AVX2 support 256-bit vector integer extending.
9079 if (!Subtarget->hasInt256() && VT.is256BitVector())
9082 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9084 SDValue V1 = Op.getOperand(0);
9085 SDValue V2 = Op.getOperand(1);
9086 unsigned NumElems = VT.getVectorNumElements();
9088 // Extending is an unary operation and the element type of the source vector
9089 // won't be equal to or larger than i64.
9090 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9091 VT.getVectorElementType() == MVT::i64)
9094 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9095 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9096 while ((1U << Shift) < NumElems) {
9097 if (SVOp->getMaskElt(1U << Shift) == 1)
9100 // The maximal ratio is 8, i.e. from i8 to i64.
9105 // Check the shuffle mask.
9106 unsigned Mask = (1U << Shift) - 1;
9107 for (unsigned i = 0; i != NumElems; ++i) {
9108 int EltIdx = SVOp->getMaskElt(i);
9109 if ((i & Mask) != 0 && EltIdx != -1)
9111 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9115 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9116 MVT NeVT = MVT::getIntegerVT(NBits);
9117 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9119 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9122 // Simplify the operand as it's prepared to be fed into shuffle.
9123 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9124 if (V1.getOpcode() == ISD::BITCAST &&
9125 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9126 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9127 V1.getOperand(0).getOperand(0)
9128 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9129 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9130 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9131 ConstantSDNode *CIdx =
9132 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9133 // If it's foldable, i.e. normal load with single use, we will let code
9134 // selection to fold it. Otherwise, we will short the conversion sequence.
9135 if (CIdx && CIdx->getZExtValue() == 0 &&
9136 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9137 MVT FullVT = V.getSimpleValueType();
9138 MVT V1VT = V1.getSimpleValueType();
9139 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9140 // The "ext_vec_elt" node is wider than the result node.
9141 // In this case we should extract subvector from V.
9142 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9143 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9144 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9145 FullVT.getVectorNumElements()/Ratio);
9146 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9147 DAG.getIntPtrConstant(0));
9149 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9153 return DAG.getNode(ISD::BITCAST, DL, VT,
9154 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9157 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9158 SelectionDAG &DAG) {
9159 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9160 MVT VT = Op.getSimpleValueType();
9162 SDValue V1 = Op.getOperand(0);
9163 SDValue V2 = Op.getOperand(1);
9165 if (isZeroShuffle(SVOp))
9166 return getZeroVector(VT, Subtarget, DAG, dl);
9168 // Handle splat operations
9169 if (SVOp->isSplat()) {
9170 // Use vbroadcast whenever the splat comes from a foldable load
9171 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9172 if (Broadcast.getNode())
9176 // Check integer expanding shuffles.
9177 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9178 if (NewOp.getNode())
9181 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9183 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9185 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9186 if (NewOp.getNode())
9187 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9188 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9189 // FIXME: Figure out a cleaner way to do this.
9190 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9191 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9192 if (NewOp.getNode()) {
9193 MVT NewVT = NewOp.getSimpleValueType();
9194 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9195 NewVT, true, false))
9196 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9199 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9200 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9201 if (NewOp.getNode()) {
9202 MVT NewVT = NewOp.getSimpleValueType();
9203 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9204 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9213 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9214 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9215 SDValue V1 = Op.getOperand(0);
9216 SDValue V2 = Op.getOperand(1);
9217 MVT VT = Op.getSimpleValueType();
9219 unsigned NumElems = VT.getVectorNumElements();
9220 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9221 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9222 bool V1IsSplat = false;
9223 bool V2IsSplat = false;
9224 bool HasSSE2 = Subtarget->hasSSE2();
9225 bool HasFp256 = Subtarget->hasFp256();
9226 bool HasInt256 = Subtarget->hasInt256();
9227 MachineFunction &MF = DAG.getMachineFunction();
9228 bool OptForSize = MF.getFunction()->getAttributes().
9229 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9231 // Check if we should use the experimental vector shuffle lowering. If so,
9232 // delegate completely to that code path.
9233 if (ExperimentalVectorShuffleLowering)
9234 return lowerVectorShuffle(Op, Subtarget, DAG);
9236 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9238 if (V1IsUndef && V2IsUndef)
9239 return DAG.getUNDEF(VT);
9241 // When we create a shuffle node we put the UNDEF node to second operand,
9242 // but in some cases the first operand may be transformed to UNDEF.
9243 // In this case we should just commute the node.
9245 return CommuteVectorShuffle(SVOp, DAG);
9247 // Vector shuffle lowering takes 3 steps:
9249 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9250 // narrowing and commutation of operands should be handled.
9251 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9253 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9254 // so the shuffle can be broken into other shuffles and the legalizer can
9255 // try the lowering again.
9257 // The general idea is that no vector_shuffle operation should be left to
9258 // be matched during isel, all of them must be converted to a target specific
9261 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9262 // narrowing and commutation of operands should be handled. The actual code
9263 // doesn't include all of those, work in progress...
9264 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9265 if (NewOp.getNode())
9268 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9270 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9271 // unpckh_undef). Only use pshufd if speed is more important than size.
9272 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9273 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9274 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9275 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9277 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9278 V2IsUndef && MayFoldVectorLoad(V1))
9279 return getMOVDDup(Op, dl, V1, DAG);
9281 if (isMOVHLPS_v_undef_Mask(M, VT))
9282 return getMOVHighToLow(Op, dl, DAG);
9284 // Use to match splats
9285 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9286 (VT == MVT::v2f64 || VT == MVT::v2i64))
9287 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9289 if (isPSHUFDMask(M, VT)) {
9290 // The actual implementation will match the mask in the if above and then
9291 // during isel it can match several different instructions, not only pshufd
9292 // as its name says, sad but true, emulate the behavior for now...
9293 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9294 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9296 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9298 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9299 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9301 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9302 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9305 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9309 if (isPALIGNRMask(M, VT, Subtarget))
9310 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9311 getShufflePALIGNRImmediate(SVOp),
9314 // Check if this can be converted into a logical shift.
9315 bool isLeft = false;
9318 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9319 if (isShift && ShVal.hasOneUse()) {
9320 // If the shifted value has multiple uses, it may be cheaper to use
9321 // v_set0 + movlhps or movhlps, etc.
9322 MVT EltVT = VT.getVectorElementType();
9323 ShAmt *= EltVT.getSizeInBits();
9324 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9327 if (isMOVLMask(M, VT)) {
9328 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9329 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9330 if (!isMOVLPMask(M, VT)) {
9331 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9332 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9334 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9335 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9339 // FIXME: fold these into legal mask.
9340 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9341 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9343 if (isMOVHLPSMask(M, VT))
9344 return getMOVHighToLow(Op, dl, DAG);
9346 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9347 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9349 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9350 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9352 if (isMOVLPMask(M, VT))
9353 return getMOVLP(Op, dl, DAG, HasSSE2);
9355 if (ShouldXformToMOVHLPS(M, VT) ||
9356 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9357 return CommuteVectorShuffle(SVOp, DAG);
9360 // No better options. Use a vshldq / vsrldq.
9361 MVT EltVT = VT.getVectorElementType();
9362 ShAmt *= EltVT.getSizeInBits();
9363 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9366 bool Commuted = false;
9367 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9368 // 1,1,1,1 -> v8i16 though.
9369 BitVector UndefElements;
9370 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9371 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9373 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9374 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9377 // Canonicalize the splat or undef, if present, to be on the RHS.
9378 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9379 CommuteVectorShuffleMask(M, NumElems);
9381 std::swap(V1IsSplat, V2IsSplat);
9385 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9386 // Shuffling low element of v1 into undef, just return v1.
9389 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9390 // the instruction selector will not match, so get a canonical MOVL with
9391 // swapped operands to undo the commute.
9392 return getMOVL(DAG, dl, VT, V2, V1);
9395 if (isUNPCKLMask(M, VT, HasInt256))
9396 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9398 if (isUNPCKHMask(M, VT, HasInt256))
9399 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9402 // Normalize mask so all entries that point to V2 points to its first
9403 // element then try to match unpck{h|l} again. If match, return a
9404 // new vector_shuffle with the corrected mask.p
9405 SmallVector<int, 8> NewMask(M.begin(), M.end());
9406 NormalizeMask(NewMask, NumElems);
9407 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9408 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9409 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9410 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9414 // Commute is back and try unpck* again.
9415 // FIXME: this seems wrong.
9416 CommuteVectorShuffleMask(M, NumElems);
9418 std::swap(V1IsSplat, V2IsSplat);
9420 if (isUNPCKLMask(M, VT, HasInt256))
9421 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9423 if (isUNPCKHMask(M, VT, HasInt256))
9424 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9427 // Normalize the node to match x86 shuffle ops if needed
9428 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9429 return CommuteVectorShuffle(SVOp, DAG);
9431 // The checks below are all present in isShuffleMaskLegal, but they are
9432 // inlined here right now to enable us to directly emit target specific
9433 // nodes, and remove one by one until they don't return Op anymore.
9435 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9436 SVOp->getSplatIndex() == 0 && V2IsUndef) {
9437 if (VT == MVT::v2f64 || VT == MVT::v2i64)
9438 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9441 if (isPSHUFHWMask(M, VT, HasInt256))
9442 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9443 getShufflePSHUFHWImmediate(SVOp),
9446 if (isPSHUFLWMask(M, VT, HasInt256))
9447 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9448 getShufflePSHUFLWImmediate(SVOp),
9452 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9454 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9456 if (isSHUFPMask(M, VT))
9457 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9458 getShuffleSHUFImmediate(SVOp), DAG);
9460 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9461 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9462 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9463 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9465 //===--------------------------------------------------------------------===//
9466 // Generate target specific nodes for 128 or 256-bit shuffles only
9467 // supported in the AVX instruction set.
9470 // Handle VMOVDDUPY permutations
9471 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9472 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9474 // Handle VPERMILPS/D* permutations
9475 if (isVPERMILPMask(M, VT)) {
9476 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9477 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9478 getShuffleSHUFImmediate(SVOp), DAG);
9479 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9480 getShuffleSHUFImmediate(SVOp), DAG);
9484 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9485 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9486 Idx*(NumElems/2), DAG, dl);
9488 // Handle VPERM2F128/VPERM2I128 permutations
9489 if (isVPERM2X128Mask(M, VT, HasFp256))
9490 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9491 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9493 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9494 return getINSERTPS(SVOp, dl, DAG);
9497 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9498 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9500 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9501 VT.is512BitVector()) {
9502 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9503 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9504 SmallVector<SDValue, 16> permclMask;
9505 for (unsigned i = 0; i != NumElems; ++i) {
9506 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9509 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9511 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9512 return DAG.getNode(X86ISD::VPERMV, dl, VT,
9513 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9514 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9515 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9518 //===--------------------------------------------------------------------===//
9519 // Since no target specific shuffle was selected for this generic one,
9520 // lower it into other known shuffles. FIXME: this isn't true yet, but
9521 // this is the plan.
9524 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9525 if (VT == MVT::v8i16) {
9526 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9527 if (NewOp.getNode())
9531 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9532 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9533 if (NewOp.getNode())
9537 if (VT == MVT::v16i8) {
9538 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9539 if (NewOp.getNode())
9543 if (VT == MVT::v32i8) {
9544 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9545 if (NewOp.getNode())
9549 // Handle all 128-bit wide vectors with 4 elements, and match them with
9550 // several different shuffle types.
9551 if (NumElems == 4 && VT.is128BitVector())
9552 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9554 // Handle general 256-bit shuffles
9555 if (VT.is256BitVector())
9556 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9561 // This function assumes its argument is a BUILD_VECTOR of constants or
9562 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
9564 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
9565 unsigned &MaskValue) {
9567 unsigned NumElems = BuildVector->getNumOperands();
9568 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9569 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9570 unsigned NumElemsInLane = NumElems / NumLanes;
9572 // Blend for v16i16 should be symetric for the both lanes.
9573 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9574 SDValue EltCond = BuildVector->getOperand(i);
9575 SDValue SndLaneEltCond =
9576 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
9578 int Lane1Cond = -1, Lane2Cond = -1;
9579 if (isa<ConstantSDNode>(EltCond))
9580 Lane1Cond = !isZero(EltCond);
9581 if (isa<ConstantSDNode>(SndLaneEltCond))
9582 Lane2Cond = !isZero(SndLaneEltCond);
9584 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
9585 // Lane1Cond != 0, means we want the first argument.
9586 // Lane1Cond == 0, means we want the second argument.
9587 // The encoding of this argument is 0 for the first argument, 1
9588 // for the second. Therefore, invert the condition.
9589 MaskValue |= !Lane1Cond << i;
9590 else if (Lane1Cond < 0)
9591 MaskValue |= !Lane2Cond << i;
9598 // Try to lower a vselect node into a simple blend instruction.
9599 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
9600 SelectionDAG &DAG) {
9601 SDValue Cond = Op.getOperand(0);
9602 SDValue LHS = Op.getOperand(1);
9603 SDValue RHS = Op.getOperand(2);
9605 MVT VT = Op.getSimpleValueType();
9606 MVT EltVT = VT.getVectorElementType();
9607 unsigned NumElems = VT.getVectorNumElements();
9609 // There is no blend with immediate in AVX-512.
9610 if (VT.is512BitVector())
9613 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
9615 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
9618 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
9621 // Check the mask for BLEND and build the value.
9622 unsigned MaskValue = 0;
9623 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
9626 // Convert i32 vectors to floating point if it is not AVX2.
9627 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9629 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9630 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9632 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
9633 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
9636 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
9637 DAG.getConstant(MaskValue, MVT::i32));
9638 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9641 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
9642 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
9643 if (BlendOp.getNode())
9646 // Some types for vselect were previously set to Expand, not Legal or
9647 // Custom. Return an empty SDValue so we fall-through to Expand, after
9648 // the Custom lowering phase.
9649 MVT VT = Op.getSimpleValueType();
9650 switch (VT.SimpleTy) {
9658 // We couldn't create a "Blend with immediate" node.
9659 // This node should still be legal, but we'll have to emit a blendv*
9664 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9665 MVT VT = Op.getSimpleValueType();
9668 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
9671 if (VT.getSizeInBits() == 8) {
9672 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
9673 Op.getOperand(0), Op.getOperand(1));
9674 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9675 DAG.getValueType(VT));
9676 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9679 if (VT.getSizeInBits() == 16) {
9680 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9681 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
9683 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9684 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9685 DAG.getNode(ISD::BITCAST, dl,
9689 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
9690 Op.getOperand(0), Op.getOperand(1));
9691 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9692 DAG.getValueType(VT));
9693 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9696 if (VT == MVT::f32) {
9697 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
9698 // the result back to FR32 register. It's only worth matching if the
9699 // result has a single use which is a store or a bitcast to i32. And in
9700 // the case of a store, it's not worth it if the index is a constant 0,
9701 // because a MOVSSmr can be used instead, which is smaller and faster.
9702 if (!Op.hasOneUse())
9704 SDNode *User = *Op.getNode()->use_begin();
9705 if ((User->getOpcode() != ISD::STORE ||
9706 (isa<ConstantSDNode>(Op.getOperand(1)) &&
9707 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
9708 (User->getOpcode() != ISD::BITCAST ||
9709 User->getValueType(0) != MVT::i32))
9711 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9712 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
9715 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
9718 if (VT == MVT::i32 || VT == MVT::i64) {
9719 // ExtractPS/pextrq works with constant index.
9720 if (isa<ConstantSDNode>(Op.getOperand(1)))
9726 /// Extract one bit from mask vector, like v16i1 or v8i1.
9727 /// AVX-512 feature.
9729 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
9730 SDValue Vec = Op.getOperand(0);
9732 MVT VecVT = Vec.getSimpleValueType();
9733 SDValue Idx = Op.getOperand(1);
9734 MVT EltVT = Op.getSimpleValueType();
9736 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
9738 // variable index can't be handled in mask registers,
9739 // extend vector to VR512
9740 if (!isa<ConstantSDNode>(Idx)) {
9741 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9742 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
9743 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
9744 ExtVT.getVectorElementType(), Ext, Idx);
9745 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
9748 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9749 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9750 unsigned MaxSift = rc->getSize()*8 - 1;
9751 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
9752 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9753 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
9754 DAG.getConstant(MaxSift, MVT::i8));
9755 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
9756 DAG.getIntPtrConstant(0));
9760 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
9761 SelectionDAG &DAG) const {
9763 SDValue Vec = Op.getOperand(0);
9764 MVT VecVT = Vec.getSimpleValueType();
9765 SDValue Idx = Op.getOperand(1);
9767 if (Op.getSimpleValueType() == MVT::i1)
9768 return ExtractBitFromMaskVector(Op, DAG);
9770 if (!isa<ConstantSDNode>(Idx)) {
9771 if (VecVT.is512BitVector() ||
9772 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
9773 VecVT.getVectorElementType().getSizeInBits() == 32)) {
9776 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
9777 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
9778 MaskEltVT.getSizeInBits());
9780 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
9781 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
9782 getZeroVector(MaskVT, Subtarget, DAG, dl),
9783 Idx, DAG.getConstant(0, getPointerTy()));
9784 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
9785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
9786 Perm, DAG.getConstant(0, getPointerTy()));
9791 // If this is a 256-bit vector result, first extract the 128-bit vector and
9792 // then extract the element from the 128-bit vector.
9793 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
9795 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9796 // Get the 128-bit vector.
9797 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
9798 MVT EltVT = VecVT.getVectorElementType();
9800 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
9802 //if (IdxVal >= NumElems/2)
9803 // IdxVal -= NumElems/2;
9804 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
9805 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
9806 DAG.getConstant(IdxVal, MVT::i32));
9809 assert(VecVT.is128BitVector() && "Unexpected vector length");
9811 if (Subtarget->hasSSE41()) {
9812 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
9817 MVT VT = Op.getSimpleValueType();
9818 // TODO: handle v16i8.
9819 if (VT.getSizeInBits() == 16) {
9820 SDValue Vec = Op.getOperand(0);
9821 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9823 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9824 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9825 DAG.getNode(ISD::BITCAST, dl,
9828 // Transform it so it match pextrw which produces a 32-bit result.
9829 MVT EltVT = MVT::i32;
9830 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
9831 Op.getOperand(0), Op.getOperand(1));
9832 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
9833 DAG.getValueType(VT));
9834 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9837 if (VT.getSizeInBits() == 32) {
9838 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9842 // SHUFPS the element to the lowest double word, then movss.
9843 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
9844 MVT VVT = Op.getOperand(0).getSimpleValueType();
9845 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9846 DAG.getUNDEF(VVT), Mask);
9847 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9848 DAG.getIntPtrConstant(0));
9851 if (VT.getSizeInBits() == 64) {
9852 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
9853 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
9854 // to match extract_elt for f64.
9855 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9859 // UNPCKHPD the element to the lowest double word, then movsd.
9860 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
9861 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
9862 int Mask[2] = { 1, -1 };
9863 MVT VVT = Op.getOperand(0).getSimpleValueType();
9864 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9865 DAG.getUNDEF(VVT), Mask);
9866 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9867 DAG.getIntPtrConstant(0));
9873 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9874 MVT VT = Op.getSimpleValueType();
9875 MVT EltVT = VT.getVectorElementType();
9878 SDValue N0 = Op.getOperand(0);
9879 SDValue N1 = Op.getOperand(1);
9880 SDValue N2 = Op.getOperand(2);
9882 if (!VT.is128BitVector())
9885 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
9886 isa<ConstantSDNode>(N2)) {
9888 if (VT == MVT::v8i16)
9889 Opc = X86ISD::PINSRW;
9890 else if (VT == MVT::v16i8)
9891 Opc = X86ISD::PINSRB;
9893 Opc = X86ISD::PINSRB;
9895 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
9897 if (N1.getValueType() != MVT::i32)
9898 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
9899 if (N2.getValueType() != MVT::i32)
9900 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
9901 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
9904 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
9905 // Bits [7:6] of the constant are the source select. This will always be
9906 // zero here. The DAG Combiner may combine an extract_elt index into these
9907 // bits. For example (insert (extract, 3), 2) could be matched by putting
9908 // the '3' into bits [7:6] of X86ISD::INSERTPS.
9909 // Bits [5:4] of the constant are the destination select. This is the
9910 // value of the incoming immediate.
9911 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
9912 // combine either bitwise AND or insert of float 0.0 to set these bits.
9913 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
9914 // Create this as a scalar to vector..
9915 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
9916 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
9919 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
9920 // PINSR* works with constant index.
9926 /// Insert one bit to mask vector, like v16i1 or v8i1.
9927 /// AVX-512 feature.
9929 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
9931 SDValue Vec = Op.getOperand(0);
9932 SDValue Elt = Op.getOperand(1);
9933 SDValue Idx = Op.getOperand(2);
9934 MVT VecVT = Vec.getSimpleValueType();
9936 if (!isa<ConstantSDNode>(Idx)) {
9937 // Non constant index. Extend source and destination,
9938 // insert element and then truncate the result.
9939 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9940 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
9941 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
9942 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
9943 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
9944 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
9947 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9948 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
9949 if (Vec.getOpcode() == ISD::UNDEF)
9950 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9951 DAG.getConstant(IdxVal, MVT::i8));
9952 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9953 unsigned MaxSift = rc->getSize()*8 - 1;
9954 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9955 DAG.getConstant(MaxSift, MVT::i8));
9956 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
9957 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9958 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
9961 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
9962 MVT VT = Op.getSimpleValueType();
9963 MVT EltVT = VT.getVectorElementType();
9965 if (EltVT == MVT::i1)
9966 return InsertBitToMaskVector(Op, DAG);
9969 SDValue N0 = Op.getOperand(0);
9970 SDValue N1 = Op.getOperand(1);
9971 SDValue N2 = Op.getOperand(2);
9973 // If this is a 256-bit vector result, first extract the 128-bit vector,
9974 // insert the element into the extracted half and then place it back.
9975 if (VT.is256BitVector() || VT.is512BitVector()) {
9976 if (!isa<ConstantSDNode>(N2))
9979 // Get the desired 128-bit vector half.
9980 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
9981 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
9983 // Insert the element into the desired half.
9984 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
9985 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
9987 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
9988 DAG.getConstant(IdxIn128, MVT::i32));
9990 // Insert the changed part back to the 256-bit vector
9991 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
9994 if (Subtarget->hasSSE41())
9995 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
9997 if (EltVT == MVT::i8)
10000 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10001 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10002 // as its second argument.
10003 if (N1.getValueType() != MVT::i32)
10004 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10005 if (N2.getValueType() != MVT::i32)
10006 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10007 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10012 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10014 MVT OpVT = Op.getSimpleValueType();
10016 // If this is a 256-bit vector result, first insert into a 128-bit
10017 // vector and then insert into the 256-bit vector.
10018 if (!OpVT.is128BitVector()) {
10019 // Insert into a 128-bit vector.
10020 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10021 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10022 OpVT.getVectorNumElements() / SizeFactor);
10024 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10026 // Insert the 128-bit vector.
10027 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10030 if (OpVT == MVT::v1i64 &&
10031 Op.getOperand(0).getValueType() == MVT::i64)
10032 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10034 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10035 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10036 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10037 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10040 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10041 // a simple subregister reference or explicit instructions to grab
10042 // upper bits of a vector.
10043 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10044 SelectionDAG &DAG) {
10046 SDValue In = Op.getOperand(0);
10047 SDValue Idx = Op.getOperand(1);
10048 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10049 MVT ResVT = Op.getSimpleValueType();
10050 MVT InVT = In.getSimpleValueType();
10052 if (Subtarget->hasFp256()) {
10053 if (ResVT.is128BitVector() &&
10054 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10055 isa<ConstantSDNode>(Idx)) {
10056 return Extract128BitVector(In, IdxVal, DAG, dl);
10058 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10059 isa<ConstantSDNode>(Idx)) {
10060 return Extract256BitVector(In, IdxVal, DAG, dl);
10066 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10067 // simple superregister reference or explicit instructions to insert
10068 // the upper bits of a vector.
10069 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10070 SelectionDAG &DAG) {
10071 if (Subtarget->hasFp256()) {
10072 SDLoc dl(Op.getNode());
10073 SDValue Vec = Op.getNode()->getOperand(0);
10074 SDValue SubVec = Op.getNode()->getOperand(1);
10075 SDValue Idx = Op.getNode()->getOperand(2);
10077 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10078 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10079 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10080 isa<ConstantSDNode>(Idx)) {
10081 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10082 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10085 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10086 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10087 isa<ConstantSDNode>(Idx)) {
10088 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10089 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10095 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10096 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10097 // one of the above mentioned nodes. It has to be wrapped because otherwise
10098 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10099 // be used to form addressing mode. These wrapped nodes will be selected
10102 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10103 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10105 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10106 // global base reg.
10107 unsigned char OpFlag = 0;
10108 unsigned WrapperKind = X86ISD::Wrapper;
10109 CodeModel::Model M = DAG.getTarget().getCodeModel();
10111 if (Subtarget->isPICStyleRIPRel() &&
10112 (M == CodeModel::Small || M == CodeModel::Kernel))
10113 WrapperKind = X86ISD::WrapperRIP;
10114 else if (Subtarget->isPICStyleGOT())
10115 OpFlag = X86II::MO_GOTOFF;
10116 else if (Subtarget->isPICStyleStubPIC())
10117 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10119 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10120 CP->getAlignment(),
10121 CP->getOffset(), OpFlag);
10123 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10124 // With PIC, the address is actually $g + Offset.
10126 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10127 DAG.getNode(X86ISD::GlobalBaseReg,
10128 SDLoc(), getPointerTy()),
10135 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10136 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10138 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10139 // global base reg.
10140 unsigned char OpFlag = 0;
10141 unsigned WrapperKind = X86ISD::Wrapper;
10142 CodeModel::Model M = DAG.getTarget().getCodeModel();
10144 if (Subtarget->isPICStyleRIPRel() &&
10145 (M == CodeModel::Small || M == CodeModel::Kernel))
10146 WrapperKind = X86ISD::WrapperRIP;
10147 else if (Subtarget->isPICStyleGOT())
10148 OpFlag = X86II::MO_GOTOFF;
10149 else if (Subtarget->isPICStyleStubPIC())
10150 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10152 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10155 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10157 // With PIC, the address is actually $g + Offset.
10159 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10160 DAG.getNode(X86ISD::GlobalBaseReg,
10161 SDLoc(), getPointerTy()),
10168 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10169 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10171 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10172 // global base reg.
10173 unsigned char OpFlag = 0;
10174 unsigned WrapperKind = X86ISD::Wrapper;
10175 CodeModel::Model M = DAG.getTarget().getCodeModel();
10177 if (Subtarget->isPICStyleRIPRel() &&
10178 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10179 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10180 OpFlag = X86II::MO_GOTPCREL;
10181 WrapperKind = X86ISD::WrapperRIP;
10182 } else if (Subtarget->isPICStyleGOT()) {
10183 OpFlag = X86II::MO_GOT;
10184 } else if (Subtarget->isPICStyleStubPIC()) {
10185 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10186 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10187 OpFlag = X86II::MO_DARWIN_NONLAZY;
10190 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10193 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10195 // With PIC, the address is actually $g + Offset.
10196 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10197 !Subtarget->is64Bit()) {
10198 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10199 DAG.getNode(X86ISD::GlobalBaseReg,
10200 SDLoc(), getPointerTy()),
10204 // For symbols that require a load from a stub to get the address, emit the
10206 if (isGlobalStubReference(OpFlag))
10207 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10208 MachinePointerInfo::getGOT(), false, false, false, 0);
10214 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10215 // Create the TargetBlockAddressAddress node.
10216 unsigned char OpFlags =
10217 Subtarget->ClassifyBlockAddressReference();
10218 CodeModel::Model M = DAG.getTarget().getCodeModel();
10219 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10220 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10222 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10225 if (Subtarget->isPICStyleRIPRel() &&
10226 (M == CodeModel::Small || M == CodeModel::Kernel))
10227 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10229 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10231 // With PIC, the address is actually $g + Offset.
10232 if (isGlobalRelativeToPICBase(OpFlags)) {
10233 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10234 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10242 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10243 int64_t Offset, SelectionDAG &DAG) const {
10244 // Create the TargetGlobalAddress node, folding in the constant
10245 // offset if it is legal.
10246 unsigned char OpFlags =
10247 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10248 CodeModel::Model M = DAG.getTarget().getCodeModel();
10250 if (OpFlags == X86II::MO_NO_FLAG &&
10251 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10252 // A direct static reference to a global.
10253 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10256 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10259 if (Subtarget->isPICStyleRIPRel() &&
10260 (M == CodeModel::Small || M == CodeModel::Kernel))
10261 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10263 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10265 // With PIC, the address is actually $g + Offset.
10266 if (isGlobalRelativeToPICBase(OpFlags)) {
10267 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10268 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10272 // For globals that require a load from a stub to get the address, emit the
10274 if (isGlobalStubReference(OpFlags))
10275 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10276 MachinePointerInfo::getGOT(), false, false, false, 0);
10278 // If there was a non-zero offset that we didn't fold, create an explicit
10279 // addition for it.
10281 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10282 DAG.getConstant(Offset, getPointerTy()));
10288 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10289 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10290 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10291 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10295 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10296 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10297 unsigned char OperandFlags, bool LocalDynamic = false) {
10298 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10299 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10301 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10302 GA->getValueType(0),
10306 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10310 SDValue Ops[] = { Chain, TGA, *InFlag };
10311 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10313 SDValue Ops[] = { Chain, TGA };
10314 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10317 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10318 MFI->setAdjustsStack(true);
10320 SDValue Flag = Chain.getValue(1);
10321 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10324 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10326 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10329 SDLoc dl(GA); // ? function entry point might be better
10330 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10331 DAG.getNode(X86ISD::GlobalBaseReg,
10332 SDLoc(), PtrVT), InFlag);
10333 InFlag = Chain.getValue(1);
10335 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10338 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10340 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10342 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10343 X86::RAX, X86II::MO_TLSGD);
10346 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10352 // Get the start address of the TLS block for this module.
10353 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10354 .getInfo<X86MachineFunctionInfo>();
10355 MFI->incNumLocalDynamicTLSAccesses();
10359 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10360 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10363 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10364 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10365 InFlag = Chain.getValue(1);
10366 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10367 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10370 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10374 unsigned char OperandFlags = X86II::MO_DTPOFF;
10375 unsigned WrapperKind = X86ISD::Wrapper;
10376 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10377 GA->getValueType(0),
10378 GA->getOffset(), OperandFlags);
10379 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10381 // Add x@dtpoff with the base.
10382 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10385 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10386 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10387 const EVT PtrVT, TLSModel::Model model,
10388 bool is64Bit, bool isPIC) {
10391 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10392 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10393 is64Bit ? 257 : 256));
10395 SDValue ThreadPointer =
10396 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10397 MachinePointerInfo(Ptr), false, false, false, 0);
10399 unsigned char OperandFlags = 0;
10400 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10402 unsigned WrapperKind = X86ISD::Wrapper;
10403 if (model == TLSModel::LocalExec) {
10404 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10405 } else if (model == TLSModel::InitialExec) {
10407 OperandFlags = X86II::MO_GOTTPOFF;
10408 WrapperKind = X86ISD::WrapperRIP;
10410 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10413 llvm_unreachable("Unexpected model");
10416 // emit "addl x@ntpoff,%eax" (local exec)
10417 // or "addl x@indntpoff,%eax" (initial exec)
10418 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10420 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10421 GA->getOffset(), OperandFlags);
10422 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10424 if (model == TLSModel::InitialExec) {
10425 if (isPIC && !is64Bit) {
10426 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10427 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10431 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10432 MachinePointerInfo::getGOT(), false, false, false, 0);
10435 // The address of the thread local variable is the add of the thread
10436 // pointer with the offset of the variable.
10437 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10441 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10443 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10444 const GlobalValue *GV = GA->getGlobal();
10446 if (Subtarget->isTargetELF()) {
10447 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10450 case TLSModel::GeneralDynamic:
10451 if (Subtarget->is64Bit())
10452 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10453 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10454 case TLSModel::LocalDynamic:
10455 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10456 Subtarget->is64Bit());
10457 case TLSModel::InitialExec:
10458 case TLSModel::LocalExec:
10459 return LowerToTLSExecModel(
10460 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10461 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10463 llvm_unreachable("Unknown TLS model.");
10466 if (Subtarget->isTargetDarwin()) {
10467 // Darwin only has one model of TLS. Lower to that.
10468 unsigned char OpFlag = 0;
10469 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10470 X86ISD::WrapperRIP : X86ISD::Wrapper;
10472 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10473 // global base reg.
10474 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10475 !Subtarget->is64Bit();
10477 OpFlag = X86II::MO_TLVP_PIC_BASE;
10479 OpFlag = X86II::MO_TLVP;
10481 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10482 GA->getValueType(0),
10483 GA->getOffset(), OpFlag);
10484 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10486 // With PIC32, the address is actually $g + Offset.
10488 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10489 DAG.getNode(X86ISD::GlobalBaseReg,
10490 SDLoc(), getPointerTy()),
10493 // Lowering the machine isd will make sure everything is in the right
10495 SDValue Chain = DAG.getEntryNode();
10496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10497 SDValue Args[] = { Chain, Offset };
10498 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10500 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10501 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10502 MFI->setAdjustsStack(true);
10504 // And our return value (tls address) is in the standard call return value
10506 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10507 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10508 Chain.getValue(1));
10511 if (Subtarget->isTargetKnownWindowsMSVC() ||
10512 Subtarget->isTargetWindowsGNU()) {
10513 // Just use the implicit TLS architecture
10514 // Need to generate someting similar to:
10515 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10517 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10518 // mov rcx, qword [rdx+rcx*8]
10519 // mov eax, .tls$:tlsvar
10520 // [rax+rcx] contains the address
10521 // Windows 64bit: gs:0x58
10522 // Windows 32bit: fs:__tls_array
10525 SDValue Chain = DAG.getEntryNode();
10527 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10528 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10529 // use its literal value of 0x2C.
10530 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10531 ? Type::getInt8PtrTy(*DAG.getContext(),
10533 : Type::getInt32PtrTy(*DAG.getContext(),
10537 Subtarget->is64Bit()
10538 ? DAG.getIntPtrConstant(0x58)
10539 : (Subtarget->isTargetWindowsGNU()
10540 ? DAG.getIntPtrConstant(0x2C)
10541 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10543 SDValue ThreadPointer =
10544 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10545 MachinePointerInfo(Ptr), false, false, false, 0);
10547 // Load the _tls_index variable
10548 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10549 if (Subtarget->is64Bit())
10550 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10551 IDX, MachinePointerInfo(), MVT::i32,
10554 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10555 false, false, false, 0);
10557 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10559 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10561 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10562 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10563 false, false, false, 0);
10565 // Get the offset of start of .tls section
10566 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10567 GA->getValueType(0),
10568 GA->getOffset(), X86II::MO_SECREL);
10569 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10571 // The address of the thread local variable is the add of the thread
10572 // pointer with the offset of the variable.
10573 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10576 llvm_unreachable("TLS not implemented for this target.");
10579 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
10580 /// and take a 2 x i32 value to shift plus a shift amount.
10581 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
10582 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
10583 MVT VT = Op.getSimpleValueType();
10584 unsigned VTBits = VT.getSizeInBits();
10586 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
10587 SDValue ShOpLo = Op.getOperand(0);
10588 SDValue ShOpHi = Op.getOperand(1);
10589 SDValue ShAmt = Op.getOperand(2);
10590 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
10591 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
10593 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10594 DAG.getConstant(VTBits - 1, MVT::i8));
10595 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
10596 DAG.getConstant(VTBits - 1, MVT::i8))
10597 : DAG.getConstant(0, VT);
10599 SDValue Tmp2, Tmp3;
10600 if (Op.getOpcode() == ISD::SHL_PARTS) {
10601 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
10602 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10604 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
10605 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
10608 // If the shift amount is larger or equal than the width of a part we can't
10609 // rely on the results of shld/shrd. Insert a test and select the appropriate
10610 // values for large shift amounts.
10611 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10612 DAG.getConstant(VTBits, MVT::i8));
10613 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10614 AndNode, DAG.getConstant(0, MVT::i8));
10617 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10618 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
10619 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
10621 if (Op.getOpcode() == ISD::SHL_PARTS) {
10622 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10623 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10625 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10626 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10629 SDValue Ops[2] = { Lo, Hi };
10630 return DAG.getMergeValues(Ops, dl);
10633 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
10634 SelectionDAG &DAG) const {
10635 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
10637 if (SrcVT.isVector())
10640 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
10641 "Unknown SINT_TO_FP to lower!");
10643 // These are really Legal; return the operand so the caller accepts it as
10645 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
10647 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
10648 Subtarget->is64Bit()) {
10653 unsigned Size = SrcVT.getSizeInBits()/8;
10654 MachineFunction &MF = DAG.getMachineFunction();
10655 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
10656 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10657 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10659 MachinePointerInfo::getFixedStack(SSFI),
10661 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
10664 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
10666 SelectionDAG &DAG) const {
10670 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
10672 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
10674 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
10676 unsigned ByteSize = SrcVT.getSizeInBits()/8;
10678 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
10679 MachineMemOperand *MMO;
10681 int SSFI = FI->getIndex();
10683 DAG.getMachineFunction()
10684 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10685 MachineMemOperand::MOLoad, ByteSize, ByteSize);
10687 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
10688 StackSlot = StackSlot.getOperand(1);
10690 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
10691 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
10693 Tys, Ops, SrcVT, MMO);
10696 Chain = Result.getValue(1);
10697 SDValue InFlag = Result.getValue(2);
10699 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
10700 // shouldn't be necessary except that RFP cannot be live across
10701 // multiple blocks. When stackifier is fixed, they can be uncoupled.
10702 MachineFunction &MF = DAG.getMachineFunction();
10703 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
10704 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
10705 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10706 Tys = DAG.getVTList(MVT::Other);
10708 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
10710 MachineMemOperand *MMO =
10711 DAG.getMachineFunction()
10712 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10713 MachineMemOperand::MOStore, SSFISize, SSFISize);
10715 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
10716 Ops, Op.getValueType(), MMO);
10717 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
10718 MachinePointerInfo::getFixedStack(SSFI),
10719 false, false, false, 0);
10725 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
10726 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
10727 SelectionDAG &DAG) const {
10728 // This algorithm is not obvious. Here it is what we're trying to output:
10731 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
10732 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
10734 haddpd %xmm0, %xmm0
10736 pshufd $0x4e, %xmm0, %xmm1
10742 LLVMContext *Context = DAG.getContext();
10744 // Build some magic constants.
10745 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
10746 Constant *C0 = ConstantDataVector::get(*Context, CV0);
10747 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
10749 SmallVector<Constant*,2> CV1;
10751 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10752 APInt(64, 0x4330000000000000ULL))));
10754 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10755 APInt(64, 0x4530000000000000ULL))));
10756 Constant *C1 = ConstantVector::get(CV1);
10757 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
10759 // Load the 64-bit value into an XMM register.
10760 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
10762 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
10763 MachinePointerInfo::getConstantPool(),
10764 false, false, false, 16);
10765 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
10766 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
10769 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
10770 MachinePointerInfo::getConstantPool(),
10771 false, false, false, 16);
10772 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
10773 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
10776 if (Subtarget->hasSSE3()) {
10777 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
10778 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
10780 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
10781 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
10783 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
10784 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
10788 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
10789 DAG.getIntPtrConstant(0));
10792 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
10793 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
10794 SelectionDAG &DAG) const {
10796 // FP constant to bias correct the final result.
10797 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
10800 // Load the 32-bit value into an XMM register.
10801 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
10804 // Zero out the upper parts of the register.
10805 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
10807 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10808 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
10809 DAG.getIntPtrConstant(0));
10811 // Or the load with the bias.
10812 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
10813 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10814 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10815 MVT::v2f64, Load)),
10816 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10817 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10818 MVT::v2f64, Bias)));
10819 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10820 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
10821 DAG.getIntPtrConstant(0));
10823 // Subtract the bias.
10824 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
10826 // Handle final rounding.
10827 EVT DestVT = Op.getValueType();
10829 if (DestVT.bitsLT(MVT::f64))
10830 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
10831 DAG.getIntPtrConstant(0));
10832 if (DestVT.bitsGT(MVT::f64))
10833 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
10835 // Handle final rounding.
10839 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
10840 SelectionDAG &DAG) const {
10841 SDValue N0 = Op.getOperand(0);
10842 MVT SVT = N0.getSimpleValueType();
10845 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
10846 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
10847 "Custom UINT_TO_FP is not supported!");
10849 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
10850 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
10851 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
10854 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
10855 SelectionDAG &DAG) const {
10856 SDValue N0 = Op.getOperand(0);
10859 if (Op.getValueType().isVector())
10860 return lowerUINT_TO_FP_vec(Op, DAG);
10862 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
10863 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
10864 // the optimization here.
10865 if (DAG.SignBitIsZero(N0))
10866 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
10868 MVT SrcVT = N0.getSimpleValueType();
10869 MVT DstVT = Op.getSimpleValueType();
10870 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
10871 return LowerUINT_TO_FP_i64(Op, DAG);
10872 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
10873 return LowerUINT_TO_FP_i32(Op, DAG);
10874 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
10877 // Make a 64-bit buffer, and use it to build an FILD.
10878 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
10879 if (SrcVT == MVT::i32) {
10880 SDValue WordOff = DAG.getConstant(4, getPointerTy());
10881 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
10882 getPointerTy(), StackSlot, WordOff);
10883 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10884 StackSlot, MachinePointerInfo(),
10886 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
10887 OffsetSlot, MachinePointerInfo(),
10889 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
10893 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
10894 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10895 StackSlot, MachinePointerInfo(),
10897 // For i64 source, we need to add the appropriate power of 2 if the input
10898 // was negative. This is the same as the optimization in
10899 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
10900 // we must be careful to do the computation in x87 extended precision, not
10901 // in SSE. (The generic code can't know it's OK to do this, or how to.)
10902 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
10903 MachineMemOperand *MMO =
10904 DAG.getMachineFunction()
10905 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10906 MachineMemOperand::MOLoad, 8, 8);
10908 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
10909 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
10910 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
10913 APInt FF(32, 0x5F800000ULL);
10915 // Check whether the sign bit is set.
10916 SDValue SignSet = DAG.getSetCC(dl,
10917 getSetCCResultType(*DAG.getContext(), MVT::i64),
10918 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
10921 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
10922 SDValue FudgePtr = DAG.getConstantPool(
10923 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
10926 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
10927 SDValue Zero = DAG.getIntPtrConstant(0);
10928 SDValue Four = DAG.getIntPtrConstant(4);
10929 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
10931 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
10933 // Load the value out, extending it from f32 to f80.
10934 // FIXME: Avoid the extend by constructing the right constant pool?
10935 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
10936 FudgePtr, MachinePointerInfo::getConstantPool(),
10937 MVT::f32, false, false, 4);
10938 // Extend everything to 80 bits to force it to be done on x87.
10939 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
10940 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
10943 std::pair<SDValue,SDValue>
10944 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
10945 bool IsSigned, bool IsReplace) const {
10948 EVT DstTy = Op.getValueType();
10950 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
10951 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
10955 assert(DstTy.getSimpleVT() <= MVT::i64 &&
10956 DstTy.getSimpleVT() >= MVT::i16 &&
10957 "Unknown FP_TO_INT to lower!");
10959 // These are really Legal.
10960 if (DstTy == MVT::i32 &&
10961 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
10962 return std::make_pair(SDValue(), SDValue());
10963 if (Subtarget->is64Bit() &&
10964 DstTy == MVT::i64 &&
10965 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
10966 return std::make_pair(SDValue(), SDValue());
10968 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
10969 // stack slot, or into the FTOL runtime function.
10970 MachineFunction &MF = DAG.getMachineFunction();
10971 unsigned MemSize = DstTy.getSizeInBits()/8;
10972 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
10973 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10976 if (!IsSigned && isIntegerTypeFTOL(DstTy))
10977 Opc = X86ISD::WIN_FTOL;
10979 switch (DstTy.getSimpleVT().SimpleTy) {
10980 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
10981 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
10982 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
10983 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
10986 SDValue Chain = DAG.getEntryNode();
10987 SDValue Value = Op.getOperand(0);
10988 EVT TheVT = Op.getOperand(0).getValueType();
10989 // FIXME This causes a redundant load/store if the SSE-class value is already
10990 // in memory, such as if it is on the callstack.
10991 if (isScalarFPTypeInSSEReg(TheVT)) {
10992 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
10993 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
10994 MachinePointerInfo::getFixedStack(SSFI),
10996 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
10998 Chain, StackSlot, DAG.getValueType(TheVT)
11001 MachineMemOperand *MMO =
11002 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11003 MachineMemOperand::MOLoad, MemSize, MemSize);
11004 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11005 Chain = Value.getValue(1);
11006 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11007 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11010 MachineMemOperand *MMO =
11011 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11012 MachineMemOperand::MOStore, MemSize, MemSize);
11014 if (Opc != X86ISD::WIN_FTOL) {
11015 // Build the FP_TO_INT*_IN_MEM
11016 SDValue Ops[] = { Chain, Value, StackSlot };
11017 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11019 return std::make_pair(FIST, StackSlot);
11021 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11022 DAG.getVTList(MVT::Other, MVT::Glue),
11024 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11025 MVT::i32, ftol.getValue(1));
11026 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11027 MVT::i32, eax.getValue(2));
11028 SDValue Ops[] = { eax, edx };
11029 SDValue pair = IsReplace
11030 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11031 : DAG.getMergeValues(Ops, DL);
11032 return std::make_pair(pair, SDValue());
11036 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11037 const X86Subtarget *Subtarget) {
11038 MVT VT = Op->getSimpleValueType(0);
11039 SDValue In = Op->getOperand(0);
11040 MVT InVT = In.getSimpleValueType();
11043 // Optimize vectors in AVX mode:
11046 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11047 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11048 // Concat upper and lower parts.
11051 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11052 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11053 // Concat upper and lower parts.
11056 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11057 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11058 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11061 if (Subtarget->hasInt256())
11062 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11064 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11065 SDValue Undef = DAG.getUNDEF(InVT);
11066 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11067 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11068 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11070 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11071 VT.getVectorNumElements()/2);
11073 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11074 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11076 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11079 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11080 SelectionDAG &DAG) {
11081 MVT VT = Op->getSimpleValueType(0);
11082 SDValue In = Op->getOperand(0);
11083 MVT InVT = In.getSimpleValueType();
11085 unsigned int NumElts = VT.getVectorNumElements();
11086 if (NumElts != 8 && NumElts != 16)
11089 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11090 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11092 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11094 // Now we have only mask extension
11095 assert(InVT.getVectorElementType() == MVT::i1);
11096 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11097 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11098 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11099 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11100 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11101 MachinePointerInfo::getConstantPool(),
11102 false, false, false, Alignment);
11104 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11105 if (VT.is512BitVector())
11107 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11110 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11111 SelectionDAG &DAG) {
11112 if (Subtarget->hasFp256()) {
11113 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11121 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11122 SelectionDAG &DAG) {
11124 MVT VT = Op.getSimpleValueType();
11125 SDValue In = Op.getOperand(0);
11126 MVT SVT = In.getSimpleValueType();
11128 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11129 return LowerZERO_EXTEND_AVX512(Op, DAG);
11131 if (Subtarget->hasFp256()) {
11132 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11137 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11138 VT.getVectorNumElements() != SVT.getVectorNumElements());
11142 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11144 MVT VT = Op.getSimpleValueType();
11145 SDValue In = Op.getOperand(0);
11146 MVT InVT = In.getSimpleValueType();
11148 if (VT == MVT::i1) {
11149 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11150 "Invalid scalar TRUNCATE operation");
11151 if (InVT == MVT::i32)
11153 if (InVT.getSizeInBits() == 64)
11154 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11155 else if (InVT.getSizeInBits() < 32)
11156 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11157 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11159 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11160 "Invalid TRUNCATE operation");
11162 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11163 if (VT.getVectorElementType().getSizeInBits() >=8)
11164 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11166 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11167 unsigned NumElts = InVT.getVectorNumElements();
11168 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11169 if (InVT.getSizeInBits() < 512) {
11170 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11171 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11175 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11176 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11177 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11178 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11179 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11180 MachinePointerInfo::getConstantPool(),
11181 false, false, false, Alignment);
11182 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11183 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11184 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11187 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11188 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11189 if (Subtarget->hasInt256()) {
11190 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11191 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11192 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11194 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11195 DAG.getIntPtrConstant(0));
11198 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11199 DAG.getIntPtrConstant(0));
11200 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11201 DAG.getIntPtrConstant(2));
11202 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11203 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11204 static const int ShufMask[] = {0, 2, 4, 6};
11205 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11208 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11209 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11210 if (Subtarget->hasInt256()) {
11211 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11213 SmallVector<SDValue,32> pshufbMask;
11214 for (unsigned i = 0; i < 2; ++i) {
11215 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11216 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11217 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11218 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11219 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11220 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11221 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11222 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11223 for (unsigned j = 0; j < 8; ++j)
11224 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11226 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11227 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11228 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11230 static const int ShufMask[] = {0, 2, -1, -1};
11231 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11233 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11234 DAG.getIntPtrConstant(0));
11235 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11238 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11239 DAG.getIntPtrConstant(0));
11241 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11242 DAG.getIntPtrConstant(4));
11244 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11245 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11247 // The PSHUFB mask:
11248 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11249 -1, -1, -1, -1, -1, -1, -1, -1};
11251 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11252 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11253 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11255 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11256 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11258 // The MOVLHPS Mask:
11259 static const int ShufMask2[] = {0, 1, 4, 5};
11260 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11261 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11264 // Handle truncation of V256 to V128 using shuffles.
11265 if (!VT.is128BitVector() || !InVT.is256BitVector())
11268 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11270 unsigned NumElems = VT.getVectorNumElements();
11271 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11273 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11274 // Prepare truncation shuffle mask
11275 for (unsigned i = 0; i != NumElems; ++i)
11276 MaskVec[i] = i * 2;
11277 SDValue V = DAG.getVectorShuffle(NVT, DL,
11278 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11279 DAG.getUNDEF(NVT), &MaskVec[0]);
11280 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11281 DAG.getIntPtrConstant(0));
11284 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11285 SelectionDAG &DAG) const {
11286 assert(!Op.getSimpleValueType().isVector());
11288 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11289 /*IsSigned=*/ true, /*IsReplace=*/ false);
11290 SDValue FIST = Vals.first, StackSlot = Vals.second;
11291 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11292 if (!FIST.getNode()) return Op;
11294 if (StackSlot.getNode())
11295 // Load the result.
11296 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11297 FIST, StackSlot, MachinePointerInfo(),
11298 false, false, false, 0);
11300 // The node is the result.
11304 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11305 SelectionDAG &DAG) const {
11306 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11307 /*IsSigned=*/ false, /*IsReplace=*/ false);
11308 SDValue FIST = Vals.first, StackSlot = Vals.second;
11309 assert(FIST.getNode() && "Unexpected failure");
11311 if (StackSlot.getNode())
11312 // Load the result.
11313 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11314 FIST, StackSlot, MachinePointerInfo(),
11315 false, false, false, 0);
11317 // The node is the result.
11321 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11323 MVT VT = Op.getSimpleValueType();
11324 SDValue In = Op.getOperand(0);
11325 MVT SVT = In.getSimpleValueType();
11327 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11329 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11330 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11331 In, DAG.getUNDEF(SVT)));
11334 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11335 LLVMContext *Context = DAG.getContext();
11337 MVT VT = Op.getSimpleValueType();
11339 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11340 if (VT.isVector()) {
11341 EltVT = VT.getVectorElementType();
11342 NumElts = VT.getVectorNumElements();
11345 if (EltVT == MVT::f64)
11346 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11347 APInt(64, ~(1ULL << 63))));
11349 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11350 APInt(32, ~(1U << 31))));
11351 C = ConstantVector::getSplat(NumElts, C);
11352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11353 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11354 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11355 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11356 MachinePointerInfo::getConstantPool(),
11357 false, false, false, Alignment);
11358 if (VT.isVector()) {
11359 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11360 return DAG.getNode(ISD::BITCAST, dl, VT,
11361 DAG.getNode(ISD::AND, dl, ANDVT,
11362 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11364 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11366 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11369 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11370 LLVMContext *Context = DAG.getContext();
11372 MVT VT = Op.getSimpleValueType();
11374 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11375 if (VT.isVector()) {
11376 EltVT = VT.getVectorElementType();
11377 NumElts = VT.getVectorNumElements();
11380 if (EltVT == MVT::f64)
11381 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11382 APInt(64, 1ULL << 63)));
11384 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11385 APInt(32, 1U << 31)));
11386 C = ConstantVector::getSplat(NumElts, C);
11387 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11388 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11389 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11390 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11391 MachinePointerInfo::getConstantPool(),
11392 false, false, false, Alignment);
11393 if (VT.isVector()) {
11394 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11395 return DAG.getNode(ISD::BITCAST, dl, VT,
11396 DAG.getNode(ISD::XOR, dl, XORVT,
11397 DAG.getNode(ISD::BITCAST, dl, XORVT,
11399 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11402 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11405 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11406 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11407 LLVMContext *Context = DAG.getContext();
11408 SDValue Op0 = Op.getOperand(0);
11409 SDValue Op1 = Op.getOperand(1);
11411 MVT VT = Op.getSimpleValueType();
11412 MVT SrcVT = Op1.getSimpleValueType();
11414 // If second operand is smaller, extend it first.
11415 if (SrcVT.bitsLT(VT)) {
11416 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
11419 // And if it is bigger, shrink it first.
11420 if (SrcVT.bitsGT(VT)) {
11421 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
11425 // At this point the operands and the result should have the same
11426 // type, and that won't be f80 since that is not custom lowered.
11428 // First get the sign bit of second operand.
11429 SmallVector<Constant*,4> CV;
11430 if (SrcVT == MVT::f64) {
11431 const fltSemantics &Sem = APFloat::IEEEdouble;
11432 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
11433 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11435 const fltSemantics &Sem = APFloat::IEEEsingle;
11436 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
11437 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11438 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11439 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11441 Constant *C = ConstantVector::get(CV);
11442 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11443 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
11444 MachinePointerInfo::getConstantPool(),
11445 false, false, false, 16);
11446 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
11448 // Shift sign bit right or left if the two operands have different types.
11449 if (SrcVT.bitsGT(VT)) {
11450 // Op0 is MVT::f32, Op1 is MVT::f64.
11451 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
11452 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
11453 DAG.getConstant(32, MVT::i32));
11454 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11455 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
11456 DAG.getIntPtrConstant(0));
11459 // Clear first operand sign bit.
11461 if (VT == MVT::f64) {
11462 const fltSemantics &Sem = APFloat::IEEEdouble;
11463 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11464 APInt(64, ~(1ULL << 63)))));
11465 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11467 const fltSemantics &Sem = APFloat::IEEEsingle;
11468 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11469 APInt(32, ~(1U << 31)))));
11470 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11471 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11472 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11474 C = ConstantVector::get(CV);
11475 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11476 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11477 MachinePointerInfo::getConstantPool(),
11478 false, false, false, 16);
11479 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
11481 // Or the value with the sign bit.
11482 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
11485 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
11486 SDValue N0 = Op.getOperand(0);
11488 MVT VT = Op.getSimpleValueType();
11490 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
11491 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
11492 DAG.getConstant(1, VT));
11493 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
11496 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
11498 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
11499 SelectionDAG &DAG) {
11500 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
11502 if (!Subtarget->hasSSE41())
11505 if (!Op->hasOneUse())
11508 SDNode *N = Op.getNode();
11511 SmallVector<SDValue, 8> Opnds;
11512 DenseMap<SDValue, unsigned> VecInMap;
11513 SmallVector<SDValue, 8> VecIns;
11514 EVT VT = MVT::Other;
11516 // Recognize a special case where a vector is casted into wide integer to
11518 Opnds.push_back(N->getOperand(0));
11519 Opnds.push_back(N->getOperand(1));
11521 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
11522 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
11523 // BFS traverse all OR'd operands.
11524 if (I->getOpcode() == ISD::OR) {
11525 Opnds.push_back(I->getOperand(0));
11526 Opnds.push_back(I->getOperand(1));
11527 // Re-evaluate the number of nodes to be traversed.
11528 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11532 // Quit if a non-EXTRACT_VECTOR_ELT
11533 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11536 // Quit if without a constant index.
11537 SDValue Idx = I->getOperand(1);
11538 if (!isa<ConstantSDNode>(Idx))
11541 SDValue ExtractedFromVec = I->getOperand(0);
11542 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
11543 if (M == VecInMap.end()) {
11544 VT = ExtractedFromVec.getValueType();
11545 // Quit if not 128/256-bit vector.
11546 if (!VT.is128BitVector() && !VT.is256BitVector())
11548 // Quit if not the same type.
11549 if (VecInMap.begin() != VecInMap.end() &&
11550 VT != VecInMap.begin()->first.getValueType())
11552 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
11553 VecIns.push_back(ExtractedFromVec);
11555 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
11558 assert((VT.is128BitVector() || VT.is256BitVector()) &&
11559 "Not extracted from 128-/256-bit vector.");
11561 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
11563 for (DenseMap<SDValue, unsigned>::const_iterator
11564 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
11565 // Quit if not all elements are used.
11566 if (I->second != FullMask)
11570 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11572 // Cast all vectors into TestVT for PTEST.
11573 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
11574 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
11576 // If more than one full vectors are evaluated, OR them first before PTEST.
11577 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
11578 // Each iteration will OR 2 nodes and append the result until there is only
11579 // 1 node left, i.e. the final OR'd value of all vectors.
11580 SDValue LHS = VecIns[Slot];
11581 SDValue RHS = VecIns[Slot + 1];
11582 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11585 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
11586 VecIns.back(), VecIns.back());
11589 /// \brief return true if \c Op has a use that doesn't just read flags.
11590 static bool hasNonFlagsUse(SDValue Op) {
11591 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
11593 SDNode *User = *UI;
11594 unsigned UOpNo = UI.getOperandNo();
11595 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
11596 // Look pass truncate.
11597 UOpNo = User->use_begin().getOperandNo();
11598 User = *User->use_begin();
11601 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11602 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
11608 /// Emit nodes that will be selected as "test Op0,Op0", or something
11610 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
11611 SelectionDAG &DAG) const {
11612 if (Op.getValueType() == MVT::i1)
11613 // KORTEST instruction should be selected
11614 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11615 DAG.getConstant(0, Op.getValueType()));
11617 // CF and OF aren't always set the way we want. Determine which
11618 // of these we need.
11619 bool NeedCF = false;
11620 bool NeedOF = false;
11623 case X86::COND_A: case X86::COND_AE:
11624 case X86::COND_B: case X86::COND_BE:
11627 case X86::COND_G: case X86::COND_GE:
11628 case X86::COND_L: case X86::COND_LE:
11629 case X86::COND_O: case X86::COND_NO: {
11630 // Check if we really need to set the
11631 // Overflow flag. If NoSignedWrap is present
11632 // that is not actually needed.
11633 switch (Op->getOpcode()) {
11638 const BinaryWithFlagsSDNode *BinNode =
11639 cast<BinaryWithFlagsSDNode>(Op.getNode());
11640 if (BinNode->hasNoSignedWrap())
11650 // See if we can use the EFLAGS value from the operand instead of
11651 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
11652 // we prove that the arithmetic won't overflow, we can't use OF or CF.
11653 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
11654 // Emit a CMP with 0, which is the TEST pattern.
11655 //if (Op.getValueType() == MVT::i1)
11656 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
11657 // DAG.getConstant(0, MVT::i1));
11658 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11659 DAG.getConstant(0, Op.getValueType()));
11661 unsigned Opcode = 0;
11662 unsigned NumOperands = 0;
11664 // Truncate operations may prevent the merge of the SETCC instruction
11665 // and the arithmetic instruction before it. Attempt to truncate the operands
11666 // of the arithmetic instruction and use a reduced bit-width instruction.
11667 bool NeedTruncation = false;
11668 SDValue ArithOp = Op;
11669 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
11670 SDValue Arith = Op->getOperand(0);
11671 // Both the trunc and the arithmetic op need to have one user each.
11672 if (Arith->hasOneUse())
11673 switch (Arith.getOpcode()) {
11680 NeedTruncation = true;
11686 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
11687 // which may be the result of a CAST. We use the variable 'Op', which is the
11688 // non-casted variable when we check for possible users.
11689 switch (ArithOp.getOpcode()) {
11691 // Due to an isel shortcoming, be conservative if this add is likely to be
11692 // selected as part of a load-modify-store instruction. When the root node
11693 // in a match is a store, isel doesn't know how to remap non-chain non-flag
11694 // uses of other nodes in the match, such as the ADD in this case. This
11695 // leads to the ADD being left around and reselected, with the result being
11696 // two adds in the output. Alas, even if none our users are stores, that
11697 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
11698 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
11699 // climbing the DAG back to the root, and it doesn't seem to be worth the
11701 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11702 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11703 if (UI->getOpcode() != ISD::CopyToReg &&
11704 UI->getOpcode() != ISD::SETCC &&
11705 UI->getOpcode() != ISD::STORE)
11708 if (ConstantSDNode *C =
11709 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
11710 // An add of one will be selected as an INC.
11711 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
11712 Opcode = X86ISD::INC;
11717 // An add of negative one (subtract of one) will be selected as a DEC.
11718 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
11719 Opcode = X86ISD::DEC;
11725 // Otherwise use a regular EFLAGS-setting add.
11726 Opcode = X86ISD::ADD;
11731 // If we have a constant logical shift that's only used in a comparison
11732 // against zero turn it into an equivalent AND. This allows turning it into
11733 // a TEST instruction later.
11734 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
11735 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
11736 EVT VT = Op.getValueType();
11737 unsigned BitWidth = VT.getSizeInBits();
11738 unsigned ShAmt = Op->getConstantOperandVal(1);
11739 if (ShAmt >= BitWidth) // Avoid undefined shifts.
11741 APInt Mask = ArithOp.getOpcode() == ISD::SRL
11742 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
11743 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
11744 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
11746 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
11747 DAG.getConstant(Mask, VT));
11748 DAG.ReplaceAllUsesWith(Op, New);
11754 // If the primary and result isn't used, don't bother using X86ISD::AND,
11755 // because a TEST instruction will be better.
11756 if (!hasNonFlagsUse(Op))
11762 // Due to the ISEL shortcoming noted above, be conservative if this op is
11763 // likely to be selected as part of a load-modify-store instruction.
11764 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11765 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11766 if (UI->getOpcode() == ISD::STORE)
11769 // Otherwise use a regular EFLAGS-setting instruction.
11770 switch (ArithOp.getOpcode()) {
11771 default: llvm_unreachable("unexpected operator!");
11772 case ISD::SUB: Opcode = X86ISD::SUB; break;
11773 case ISD::XOR: Opcode = X86ISD::XOR; break;
11774 case ISD::AND: Opcode = X86ISD::AND; break;
11776 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
11777 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
11778 if (EFLAGS.getNode())
11781 Opcode = X86ISD::OR;
11795 return SDValue(Op.getNode(), 1);
11801 // If we found that truncation is beneficial, perform the truncation and
11803 if (NeedTruncation) {
11804 EVT VT = Op.getValueType();
11805 SDValue WideVal = Op->getOperand(0);
11806 EVT WideVT = WideVal.getValueType();
11807 unsigned ConvertedOp = 0;
11808 // Use a target machine opcode to prevent further DAGCombine
11809 // optimizations that may separate the arithmetic operations
11810 // from the setcc node.
11811 switch (WideVal.getOpcode()) {
11813 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
11814 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
11815 case ISD::AND: ConvertedOp = X86ISD::AND; break;
11816 case ISD::OR: ConvertedOp = X86ISD::OR; break;
11817 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
11821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11822 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
11823 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
11824 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
11825 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
11831 // Emit a CMP with 0, which is the TEST pattern.
11832 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11833 DAG.getConstant(0, Op.getValueType()));
11835 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11836 SmallVector<SDValue, 4> Ops;
11837 for (unsigned i = 0; i != NumOperands; ++i)
11838 Ops.push_back(Op.getOperand(i));
11840 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
11841 DAG.ReplaceAllUsesWith(Op, New);
11842 return SDValue(New.getNode(), 1);
11845 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
11847 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
11848 SDLoc dl, SelectionDAG &DAG) const {
11849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
11850 if (C->getAPIntValue() == 0)
11851 return EmitTest(Op0, X86CC, dl, DAG);
11853 if (Op0.getValueType() == MVT::i1)
11854 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
11857 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
11858 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
11859 // Do the comparison at i32 if it's smaller, besides the Atom case.
11860 // This avoids subregister aliasing issues. Keep the smaller reference
11861 // if we're optimizing for size, however, as that'll allow better folding
11862 // of memory operations.
11863 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
11864 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
11865 AttributeSet::FunctionIndex, Attribute::MinSize) &&
11866 !Subtarget->isAtom()) {
11867 unsigned ExtendOp =
11868 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
11869 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
11870 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
11872 // Use SUB instead of CMP to enable CSE between SUB and CMP.
11873 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
11874 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
11876 return SDValue(Sub.getNode(), 1);
11878 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
11881 /// Convert a comparison if required by the subtarget.
11882 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
11883 SelectionDAG &DAG) const {
11884 // If the subtarget does not support the FUCOMI instruction, floating-point
11885 // comparisons have to be converted.
11886 if (Subtarget->hasCMov() ||
11887 Cmp.getOpcode() != X86ISD::CMP ||
11888 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
11889 !Cmp.getOperand(1).getValueType().isFloatingPoint())
11892 // The instruction selector will select an FUCOM instruction instead of
11893 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
11894 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
11895 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
11897 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
11898 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
11899 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
11900 DAG.getConstant(8, MVT::i8));
11901 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
11902 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
11905 static bool isAllOnes(SDValue V) {
11906 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
11907 return C && C->isAllOnesValue();
11910 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
11911 /// if it's possible.
11912 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
11913 SDLoc dl, SelectionDAG &DAG) const {
11914 SDValue Op0 = And.getOperand(0);
11915 SDValue Op1 = And.getOperand(1);
11916 if (Op0.getOpcode() == ISD::TRUNCATE)
11917 Op0 = Op0.getOperand(0);
11918 if (Op1.getOpcode() == ISD::TRUNCATE)
11919 Op1 = Op1.getOperand(0);
11922 if (Op1.getOpcode() == ISD::SHL)
11923 std::swap(Op0, Op1);
11924 if (Op0.getOpcode() == ISD::SHL) {
11925 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
11926 if (And00C->getZExtValue() == 1) {
11927 // If we looked past a truncate, check that it's only truncating away
11929 unsigned BitWidth = Op0.getValueSizeInBits();
11930 unsigned AndBitWidth = And.getValueSizeInBits();
11931 if (BitWidth > AndBitWidth) {
11933 DAG.computeKnownBits(Op0, Zeros, Ones);
11934 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
11938 RHS = Op0.getOperand(1);
11940 } else if (Op1.getOpcode() == ISD::Constant) {
11941 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
11942 uint64_t AndRHSVal = AndRHS->getZExtValue();
11943 SDValue AndLHS = Op0;
11945 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
11946 LHS = AndLHS.getOperand(0);
11947 RHS = AndLHS.getOperand(1);
11950 // Use BT if the immediate can't be encoded in a TEST instruction.
11951 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
11953 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
11957 if (LHS.getNode()) {
11958 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
11959 // instruction. Since the shift amount is in-range-or-undefined, we know
11960 // that doing a bittest on the i32 value is ok. We extend to i32 because
11961 // the encoding for the i16 version is larger than the i32 version.
11962 // Also promote i16 to i32 for performance / code size reason.
11963 if (LHS.getValueType() == MVT::i8 ||
11964 LHS.getValueType() == MVT::i16)
11965 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
11967 // If the operand types disagree, extend the shift amount to match. Since
11968 // BT ignores high bits (like shifts) we can use anyextend.
11969 if (LHS.getValueType() != RHS.getValueType())
11970 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
11972 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
11973 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
11974 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11975 DAG.getConstant(Cond, MVT::i8), BT);
11981 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
11983 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
11988 // SSE Condition code mapping:
11997 switch (SetCCOpcode) {
11998 default: llvm_unreachable("Unexpected SETCC condition");
12000 case ISD::SETEQ: SSECC = 0; break;
12002 case ISD::SETGT: Swap = true; // Fallthrough
12004 case ISD::SETOLT: SSECC = 1; break;
12006 case ISD::SETGE: Swap = true; // Fallthrough
12008 case ISD::SETOLE: SSECC = 2; break;
12009 case ISD::SETUO: SSECC = 3; break;
12011 case ISD::SETNE: SSECC = 4; break;
12012 case ISD::SETULE: Swap = true; // Fallthrough
12013 case ISD::SETUGE: SSECC = 5; break;
12014 case ISD::SETULT: Swap = true; // Fallthrough
12015 case ISD::SETUGT: SSECC = 6; break;
12016 case ISD::SETO: SSECC = 7; break;
12018 case ISD::SETONE: SSECC = 8; break;
12021 std::swap(Op0, Op1);
12026 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12027 // ones, and then concatenate the result back.
12028 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12029 MVT VT = Op.getSimpleValueType();
12031 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12032 "Unsupported value type for operation");
12034 unsigned NumElems = VT.getVectorNumElements();
12036 SDValue CC = Op.getOperand(2);
12038 // Extract the LHS vectors
12039 SDValue LHS = Op.getOperand(0);
12040 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12041 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12043 // Extract the RHS vectors
12044 SDValue RHS = Op.getOperand(1);
12045 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12046 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12048 // Issue the operation on the smaller types and concatenate the result back
12049 MVT EltVT = VT.getVectorElementType();
12050 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12051 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12052 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12053 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12056 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12057 const X86Subtarget *Subtarget) {
12058 SDValue Op0 = Op.getOperand(0);
12059 SDValue Op1 = Op.getOperand(1);
12060 SDValue CC = Op.getOperand(2);
12061 MVT VT = Op.getSimpleValueType();
12064 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12065 Op.getValueType().getScalarType() == MVT::i1 &&
12066 "Cannot set masked compare for this operation");
12068 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12070 bool Unsigned = false;
12073 switch (SetCCOpcode) {
12074 default: llvm_unreachable("Unexpected SETCC condition");
12075 case ISD::SETNE: SSECC = 4; break;
12076 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12077 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12078 case ISD::SETLT: Swap = true; //fall-through
12079 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12080 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12081 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12082 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12083 case ISD::SETULE: Unsigned = true; //fall-through
12084 case ISD::SETLE: SSECC = 2; break;
12088 std::swap(Op0, Op1);
12090 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12091 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12092 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12093 DAG.getConstant(SSECC, MVT::i8));
12096 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12097 /// operand \p Op1. If non-trivial (for example because it's not constant)
12098 /// return an empty value.
12099 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12101 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12105 MVT VT = Op1.getSimpleValueType();
12106 MVT EVT = VT.getVectorElementType();
12107 unsigned n = VT.getVectorNumElements();
12108 SmallVector<SDValue, 8> ULTOp1;
12110 for (unsigned i = 0; i < n; ++i) {
12111 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12112 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12115 // Avoid underflow.
12116 APInt Val = Elt->getAPIntValue();
12120 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12123 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12126 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12127 SelectionDAG &DAG) {
12128 SDValue Op0 = Op.getOperand(0);
12129 SDValue Op1 = Op.getOperand(1);
12130 SDValue CC = Op.getOperand(2);
12131 MVT VT = Op.getSimpleValueType();
12132 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12133 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12138 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12139 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12142 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12143 unsigned Opc = X86ISD::CMPP;
12144 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12145 assert(VT.getVectorNumElements() <= 16);
12146 Opc = X86ISD::CMPM;
12148 // In the two special cases we can't handle, emit two comparisons.
12151 unsigned CombineOpc;
12152 if (SetCCOpcode == ISD::SETUEQ) {
12153 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12155 assert(SetCCOpcode == ISD::SETONE);
12156 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12159 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12160 DAG.getConstant(CC0, MVT::i8));
12161 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12162 DAG.getConstant(CC1, MVT::i8));
12163 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12165 // Handle all other FP comparisons here.
12166 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12167 DAG.getConstant(SSECC, MVT::i8));
12170 // Break 256-bit integer vector compare into smaller ones.
12171 if (VT.is256BitVector() && !Subtarget->hasInt256())
12172 return Lower256IntVSETCC(Op, DAG);
12174 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12175 EVT OpVT = Op1.getValueType();
12176 if (Subtarget->hasAVX512()) {
12177 if (Op1.getValueType().is512BitVector() ||
12178 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12179 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12181 // In AVX-512 architecture setcc returns mask with i1 elements,
12182 // But there is no compare instruction for i8 and i16 elements.
12183 // We are not talking about 512-bit operands in this case, these
12184 // types are illegal.
12186 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12187 OpVT.getVectorElementType().getSizeInBits() >= 8))
12188 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12189 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12192 // We are handling one of the integer comparisons here. Since SSE only has
12193 // GT and EQ comparisons for integer, swapping operands and multiple
12194 // operations may be required for some comparisons.
12196 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12197 bool Subus = false;
12199 switch (SetCCOpcode) {
12200 default: llvm_unreachable("Unexpected SETCC condition");
12201 case ISD::SETNE: Invert = true;
12202 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12203 case ISD::SETLT: Swap = true;
12204 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12205 case ISD::SETGE: Swap = true;
12206 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12207 Invert = true; break;
12208 case ISD::SETULT: Swap = true;
12209 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12210 FlipSigns = true; break;
12211 case ISD::SETUGE: Swap = true;
12212 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12213 FlipSigns = true; Invert = true; break;
12216 // Special case: Use min/max operations for SETULE/SETUGE
12217 MVT VET = VT.getVectorElementType();
12219 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12220 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12223 switch (SetCCOpcode) {
12225 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12226 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12229 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12232 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12233 if (!MinMax && hasSubus) {
12234 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12236 // t = psubus Op0, Op1
12237 // pcmpeq t, <0..0>
12238 switch (SetCCOpcode) {
12240 case ISD::SETULT: {
12241 // If the comparison is against a constant we can turn this into a
12242 // setule. With psubus, setule does not require a swap. This is
12243 // beneficial because the constant in the register is no longer
12244 // destructed as the destination so it can be hoisted out of a loop.
12245 // Only do this pre-AVX since vpcmp* is no longer destructive.
12246 if (Subtarget->hasAVX())
12248 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12249 if (ULEOp1.getNode()) {
12251 Subus = true; Invert = false; Swap = false;
12255 // Psubus is better than flip-sign because it requires no inversion.
12256 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12257 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12261 Opc = X86ISD::SUBUS;
12267 std::swap(Op0, Op1);
12269 // Check that the operation in question is available (most are plain SSE2,
12270 // but PCMPGTQ and PCMPEQQ have different requirements).
12271 if (VT == MVT::v2i64) {
12272 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12273 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12275 // First cast everything to the right type.
12276 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12277 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12279 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12280 // bits of the inputs before performing those operations. The lower
12281 // compare is always unsigned.
12284 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12286 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12287 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12288 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12289 Sign, Zero, Sign, Zero);
12291 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12292 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12294 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12295 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12296 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12298 // Create masks for only the low parts/high parts of the 64 bit integers.
12299 static const int MaskHi[] = { 1, 1, 3, 3 };
12300 static const int MaskLo[] = { 0, 0, 2, 2 };
12301 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12302 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12303 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12305 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12306 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12309 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12311 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12314 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12315 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12316 // pcmpeqd + pshufd + pand.
12317 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12319 // First cast everything to the right type.
12320 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12321 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12324 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12326 // Make sure the lower and upper halves are both all-ones.
12327 static const int Mask[] = { 1, 0, 3, 2 };
12328 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12329 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12332 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12334 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12338 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12339 // bits of the inputs before performing those operations.
12341 EVT EltVT = VT.getVectorElementType();
12342 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12343 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12344 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12347 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12349 // If the logical-not of the result is required, perform that now.
12351 Result = DAG.getNOT(dl, Result, VT);
12354 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12357 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12358 getZeroVector(VT, Subtarget, DAG, dl));
12363 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12365 MVT VT = Op.getSimpleValueType();
12367 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12369 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12370 && "SetCC type must be 8-bit or 1-bit integer");
12371 SDValue Op0 = Op.getOperand(0);
12372 SDValue Op1 = Op.getOperand(1);
12374 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12376 // Optimize to BT if possible.
12377 // Lower (X & (1 << N)) == 0 to BT(X, N).
12378 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12379 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12380 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12381 Op1.getOpcode() == ISD::Constant &&
12382 cast<ConstantSDNode>(Op1)->isNullValue() &&
12383 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12384 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12385 if (NewSetCC.getNode())
12389 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12391 if (Op1.getOpcode() == ISD::Constant &&
12392 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12393 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12394 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12396 // If the input is a setcc, then reuse the input setcc or use a new one with
12397 // the inverted condition.
12398 if (Op0.getOpcode() == X86ISD::SETCC) {
12399 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12400 bool Invert = (CC == ISD::SETNE) ^
12401 cast<ConstantSDNode>(Op1)->isNullValue();
12405 CCode = X86::GetOppositeBranchCondition(CCode);
12406 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12407 DAG.getConstant(CCode, MVT::i8),
12408 Op0.getOperand(1));
12410 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12414 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12415 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12416 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12418 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12419 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12422 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12423 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12424 if (X86CC == X86::COND_INVALID)
12427 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12428 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12429 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12430 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12432 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12436 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
12437 static bool isX86LogicalCmp(SDValue Op) {
12438 unsigned Opc = Op.getNode()->getOpcode();
12439 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
12440 Opc == X86ISD::SAHF)
12442 if (Op.getResNo() == 1 &&
12443 (Opc == X86ISD::ADD ||
12444 Opc == X86ISD::SUB ||
12445 Opc == X86ISD::ADC ||
12446 Opc == X86ISD::SBB ||
12447 Opc == X86ISD::SMUL ||
12448 Opc == X86ISD::UMUL ||
12449 Opc == X86ISD::INC ||
12450 Opc == X86ISD::DEC ||
12451 Opc == X86ISD::OR ||
12452 Opc == X86ISD::XOR ||
12453 Opc == X86ISD::AND))
12456 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
12462 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
12463 if (V.getOpcode() != ISD::TRUNCATE)
12466 SDValue VOp0 = V.getOperand(0);
12467 unsigned InBits = VOp0.getValueSizeInBits();
12468 unsigned Bits = V.getValueSizeInBits();
12469 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
12472 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
12473 bool addTest = true;
12474 SDValue Cond = Op.getOperand(0);
12475 SDValue Op1 = Op.getOperand(1);
12476 SDValue Op2 = Op.getOperand(2);
12478 EVT VT = Op1.getValueType();
12481 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12482 // are available. Otherwise fp cmovs get lowered into a less efficient branch
12483 // sequence later on.
12484 if (Cond.getOpcode() == ISD::SETCC &&
12485 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12486 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12487 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12488 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12489 int SSECC = translateX86FSETCC(
12490 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12493 if (Subtarget->hasAVX512()) {
12494 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12495 DAG.getConstant(SSECC, MVT::i8));
12496 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12498 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12499 DAG.getConstant(SSECC, MVT::i8));
12500 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12501 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12502 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12506 if (Cond.getOpcode() == ISD::SETCC) {
12507 SDValue NewCond = LowerSETCC(Cond, DAG);
12508 if (NewCond.getNode())
12512 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12513 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12514 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12515 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12516 if (Cond.getOpcode() == X86ISD::SETCC &&
12517 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12518 isZero(Cond.getOperand(1).getOperand(1))) {
12519 SDValue Cmp = Cond.getOperand(1);
12521 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12523 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12524 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12525 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12527 SDValue CmpOp0 = Cmp.getOperand(0);
12528 // Apply further optimizations for special cases
12529 // (select (x != 0), -1, 0) -> neg & sbb
12530 // (select (x == 0), 0, -1) -> neg & sbb
12531 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12532 if (YC->isNullValue() &&
12533 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12534 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12535 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12536 DAG.getConstant(0, CmpOp0.getValueType()),
12538 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12539 DAG.getConstant(X86::COND_B, MVT::i8),
12540 SDValue(Neg.getNode(), 1));
12544 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12545 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12546 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12548 SDValue Res = // Res = 0 or -1.
12549 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12550 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12552 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12553 Res = DAG.getNOT(DL, Res, Res.getValueType());
12555 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12556 if (!N2C || !N2C->isNullValue())
12557 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12562 // Look past (and (setcc_carry (cmp ...)), 1).
12563 if (Cond.getOpcode() == ISD::AND &&
12564 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12565 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12566 if (C && C->getAPIntValue() == 1)
12567 Cond = Cond.getOperand(0);
12570 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12571 // setting operand in place of the X86ISD::SETCC.
12572 unsigned CondOpcode = Cond.getOpcode();
12573 if (CondOpcode == X86ISD::SETCC ||
12574 CondOpcode == X86ISD::SETCC_CARRY) {
12575 CC = Cond.getOperand(0);
12577 SDValue Cmp = Cond.getOperand(1);
12578 unsigned Opc = Cmp.getOpcode();
12579 MVT VT = Op.getSimpleValueType();
12581 bool IllegalFPCMov = false;
12582 if (VT.isFloatingPoint() && !VT.isVector() &&
12583 !isScalarFPTypeInSSEReg(VT)) // FPStack?
12584 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12586 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12587 Opc == X86ISD::BT) { // FIXME
12591 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12592 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12593 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12594 Cond.getOperand(0).getValueType() != MVT::i8)) {
12595 SDValue LHS = Cond.getOperand(0);
12596 SDValue RHS = Cond.getOperand(1);
12597 unsigned X86Opcode;
12600 switch (CondOpcode) {
12601 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12602 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12603 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12604 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12605 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12606 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12607 default: llvm_unreachable("unexpected overflowing operator");
12609 if (CondOpcode == ISD::UMULO)
12610 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12613 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12615 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12617 if (CondOpcode == ISD::UMULO)
12618 Cond = X86Op.getValue(2);
12620 Cond = X86Op.getValue(1);
12622 CC = DAG.getConstant(X86Cond, MVT::i8);
12627 // Look pass the truncate if the high bits are known zero.
12628 if (isTruncWithZeroHighBitsInput(Cond, DAG))
12629 Cond = Cond.getOperand(0);
12631 // We know the result of AND is compared against zero. Try to match
12633 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
12634 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
12635 if (NewSetCC.getNode()) {
12636 CC = NewSetCC.getOperand(0);
12637 Cond = NewSetCC.getOperand(1);
12644 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12645 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
12648 // a < b ? -1 : 0 -> RES = ~setcc_carry
12649 // a < b ? 0 : -1 -> RES = setcc_carry
12650 // a >= b ? -1 : 0 -> RES = setcc_carry
12651 // a >= b ? 0 : -1 -> RES = ~setcc_carry
12652 if (Cond.getOpcode() == X86ISD::SUB) {
12653 Cond = ConvertCmpIfNecessary(Cond, DAG);
12654 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
12656 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
12657 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
12658 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12659 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
12660 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
12661 return DAG.getNOT(DL, Res, Res.getValueType());
12666 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
12667 // widen the cmov and push the truncate through. This avoids introducing a new
12668 // branch during isel and doesn't add any extensions.
12669 if (Op.getValueType() == MVT::i8 &&
12670 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
12671 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
12672 if (T1.getValueType() == T2.getValueType() &&
12673 // Blacklist CopyFromReg to avoid partial register stalls.
12674 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
12675 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
12676 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
12677 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
12681 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
12682 // condition is true.
12683 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
12684 SDValue Ops[] = { Op2, Op1, CC, Cond };
12685 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
12688 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
12689 MVT VT = Op->getSimpleValueType(0);
12690 SDValue In = Op->getOperand(0);
12691 MVT InVT = In.getSimpleValueType();
12694 unsigned int NumElts = VT.getVectorNumElements();
12695 if (NumElts != 8 && NumElts != 16)
12698 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12699 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12702 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12704 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
12705 Constant *C = ConstantInt::get(*DAG.getContext(),
12706 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
12708 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12709 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12710 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
12711 MachinePointerInfo::getConstantPool(),
12712 false, false, false, Alignment);
12713 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
12714 if (VT.is512BitVector())
12716 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
12719 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12720 SelectionDAG &DAG) {
12721 MVT VT = Op->getSimpleValueType(0);
12722 SDValue In = Op->getOperand(0);
12723 MVT InVT = In.getSimpleValueType();
12726 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
12727 return LowerSIGN_EXTEND_AVX512(Op, DAG);
12729 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
12730 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
12731 (VT != MVT::v16i16 || InVT != MVT::v16i8))
12734 if (Subtarget->hasInt256())
12735 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12737 // Optimize vectors in AVX mode
12738 // Sign extend v8i16 to v8i32 and
12741 // Divide input vector into two parts
12742 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
12743 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
12744 // concat the vectors to original VT
12746 unsigned NumElems = InVT.getVectorNumElements();
12747 SDValue Undef = DAG.getUNDEF(InVT);
12749 SmallVector<int,8> ShufMask1(NumElems, -1);
12750 for (unsigned i = 0; i != NumElems/2; ++i)
12753 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
12755 SmallVector<int,8> ShufMask2(NumElems, -1);
12756 for (unsigned i = 0; i != NumElems/2; ++i)
12757 ShufMask2[i] = i + NumElems/2;
12759 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
12761 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
12762 VT.getVectorNumElements()/2);
12764 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
12765 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
12767 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12770 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
12771 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
12772 // from the AND / OR.
12773 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
12774 Opc = Op.getOpcode();
12775 if (Opc != ISD::OR && Opc != ISD::AND)
12777 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12778 Op.getOperand(0).hasOneUse() &&
12779 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
12780 Op.getOperand(1).hasOneUse());
12783 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
12784 // 1 and that the SETCC node has a single use.
12785 static bool isXor1OfSetCC(SDValue Op) {
12786 if (Op.getOpcode() != ISD::XOR)
12788 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
12789 if (N1C && N1C->getAPIntValue() == 1) {
12790 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12791 Op.getOperand(0).hasOneUse();
12796 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
12797 bool addTest = true;
12798 SDValue Chain = Op.getOperand(0);
12799 SDValue Cond = Op.getOperand(1);
12800 SDValue Dest = Op.getOperand(2);
12803 bool Inverted = false;
12805 if (Cond.getOpcode() == ISD::SETCC) {
12806 // Check for setcc([su]{add,sub,mul}o == 0).
12807 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
12808 isa<ConstantSDNode>(Cond.getOperand(1)) &&
12809 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
12810 Cond.getOperand(0).getResNo() == 1 &&
12811 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
12812 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
12813 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
12814 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
12815 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
12816 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
12818 Cond = Cond.getOperand(0);
12820 SDValue NewCond = LowerSETCC(Cond, DAG);
12821 if (NewCond.getNode())
12826 // FIXME: LowerXALUO doesn't handle these!!
12827 else if (Cond.getOpcode() == X86ISD::ADD ||
12828 Cond.getOpcode() == X86ISD::SUB ||
12829 Cond.getOpcode() == X86ISD::SMUL ||
12830 Cond.getOpcode() == X86ISD::UMUL)
12831 Cond = LowerXALUO(Cond, DAG);
12834 // Look pass (and (setcc_carry (cmp ...)), 1).
12835 if (Cond.getOpcode() == ISD::AND &&
12836 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12837 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12838 if (C && C->getAPIntValue() == 1)
12839 Cond = Cond.getOperand(0);
12842 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12843 // setting operand in place of the X86ISD::SETCC.
12844 unsigned CondOpcode = Cond.getOpcode();
12845 if (CondOpcode == X86ISD::SETCC ||
12846 CondOpcode == X86ISD::SETCC_CARRY) {
12847 CC = Cond.getOperand(0);
12849 SDValue Cmp = Cond.getOperand(1);
12850 unsigned Opc = Cmp.getOpcode();
12851 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
12852 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
12856 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
12860 // These can only come from an arithmetic instruction with overflow,
12861 // e.g. SADDO, UADDO.
12862 Cond = Cond.getNode()->getOperand(1);
12868 CondOpcode = Cond.getOpcode();
12869 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12870 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12871 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12872 Cond.getOperand(0).getValueType() != MVT::i8)) {
12873 SDValue LHS = Cond.getOperand(0);
12874 SDValue RHS = Cond.getOperand(1);
12875 unsigned X86Opcode;
12878 // Keep this in sync with LowerXALUO, otherwise we might create redundant
12879 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
12881 switch (CondOpcode) {
12882 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12886 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
12889 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12890 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12892 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12894 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
12897 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12898 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12899 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12900 default: llvm_unreachable("unexpected overflowing operator");
12903 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
12904 if (CondOpcode == ISD::UMULO)
12905 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12908 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12910 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
12912 if (CondOpcode == ISD::UMULO)
12913 Cond = X86Op.getValue(2);
12915 Cond = X86Op.getValue(1);
12917 CC = DAG.getConstant(X86Cond, MVT::i8);
12921 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
12922 SDValue Cmp = Cond.getOperand(0).getOperand(1);
12923 if (CondOpc == ISD::OR) {
12924 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
12925 // two branches instead of an explicit OR instruction with a
12927 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12928 isX86LogicalCmp(Cmp)) {
12929 CC = Cond.getOperand(0).getOperand(0);
12930 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12931 Chain, Dest, CC, Cmp);
12932 CC = Cond.getOperand(1).getOperand(0);
12936 } else { // ISD::AND
12937 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
12938 // two branches instead of an explicit AND instruction with a
12939 // separate test. However, we only do this if this block doesn't
12940 // have a fall-through edge, because this requires an explicit
12941 // jmp when the condition is false.
12942 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12943 isX86LogicalCmp(Cmp) &&
12944 Op.getNode()->hasOneUse()) {
12945 X86::CondCode CCode =
12946 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
12947 CCode = X86::GetOppositeBranchCondition(CCode);
12948 CC = DAG.getConstant(CCode, MVT::i8);
12949 SDNode *User = *Op.getNode()->use_begin();
12950 // Look for an unconditional branch following this conditional branch.
12951 // We need this because we need to reverse the successors in order
12952 // to implement FCMP_OEQ.
12953 if (User->getOpcode() == ISD::BR) {
12954 SDValue FalseBB = User->getOperand(1);
12956 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
12957 assert(NewBR == User);
12961 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12962 Chain, Dest, CC, Cmp);
12963 X86::CondCode CCode =
12964 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
12965 CCode = X86::GetOppositeBranchCondition(CCode);
12966 CC = DAG.getConstant(CCode, MVT::i8);
12972 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
12973 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
12974 // It should be transformed during dag combiner except when the condition
12975 // is set by a arithmetics with overflow node.
12976 X86::CondCode CCode =
12977 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
12978 CCode = X86::GetOppositeBranchCondition(CCode);
12979 CC = DAG.getConstant(CCode, MVT::i8);
12980 Cond = Cond.getOperand(0).getOperand(1);
12982 } else if (Cond.getOpcode() == ISD::SETCC &&
12983 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
12984 // For FCMP_OEQ, we can emit
12985 // two branches instead of an explicit AND instruction with a
12986 // separate test. However, we only do this if this block doesn't
12987 // have a fall-through edge, because this requires an explicit
12988 // jmp when the condition is false.
12989 if (Op.getNode()->hasOneUse()) {
12990 SDNode *User = *Op.getNode()->use_begin();
12991 // Look for an unconditional branch following this conditional branch.
12992 // We need this because we need to reverse the successors in order
12993 // to implement FCMP_OEQ.
12994 if (User->getOpcode() == ISD::BR) {
12995 SDValue FalseBB = User->getOperand(1);
12997 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
12998 assert(NewBR == User);
13002 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13003 Cond.getOperand(0), Cond.getOperand(1));
13004 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13005 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13006 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13007 Chain, Dest, CC, Cmp);
13008 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13013 } else if (Cond.getOpcode() == ISD::SETCC &&
13014 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13015 // For FCMP_UNE, we can emit
13016 // two branches instead of an explicit AND instruction with a
13017 // separate test. However, we only do this if this block doesn't
13018 // have a fall-through edge, because this requires an explicit
13019 // jmp when the condition is false.
13020 if (Op.getNode()->hasOneUse()) {
13021 SDNode *User = *Op.getNode()->use_begin();
13022 // Look for an unconditional branch following this conditional branch.
13023 // We need this because we need to reverse the successors in order
13024 // to implement FCMP_UNE.
13025 if (User->getOpcode() == ISD::BR) {
13026 SDValue FalseBB = User->getOperand(1);
13028 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13029 assert(NewBR == User);
13032 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13033 Cond.getOperand(0), Cond.getOperand(1));
13034 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13035 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13036 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13037 Chain, Dest, CC, Cmp);
13038 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13048 // Look pass the truncate if the high bits are known zero.
13049 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13050 Cond = Cond.getOperand(0);
13052 // We know the result of AND is compared against zero. Try to match
13054 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13055 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13056 if (NewSetCC.getNode()) {
13057 CC = NewSetCC.getOperand(0);
13058 Cond = NewSetCC.getOperand(1);
13065 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13066 CC = DAG.getConstant(X86Cond, MVT::i8);
13067 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13069 Cond = ConvertCmpIfNecessary(Cond, DAG);
13070 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13071 Chain, Dest, CC, Cond);
13074 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13075 // Calls to _alloca is needed to probe the stack when allocating more than 4k
13076 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13077 // that the guard pages used by the OS virtual memory manager are allocated in
13078 // correct sequence.
13080 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13081 SelectionDAG &DAG) const {
13082 MachineFunction &MF = DAG.getMachineFunction();
13083 bool SplitStack = MF.shouldSplitStack();
13084 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13090 SDNode* Node = Op.getNode();
13092 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13093 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13094 " not tell us which reg is the stack pointer!");
13095 EVT VT = Node->getValueType(0);
13096 SDValue Tmp1 = SDValue(Node, 0);
13097 SDValue Tmp2 = SDValue(Node, 1);
13098 SDValue Tmp3 = Node->getOperand(2);
13099 SDValue Chain = Tmp1.getOperand(0);
13101 // Chain the dynamic stack allocation so that it doesn't modify the stack
13102 // pointer when other instructions are using the stack.
13103 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13106 SDValue Size = Tmp2.getOperand(1);
13107 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13108 Chain = SP.getValue(1);
13109 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13110 const TargetFrameLowering &TFI = *DAG.getTarget().getFrameLowering();
13111 unsigned StackAlign = TFI.getStackAlignment();
13112 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13113 if (Align > StackAlign)
13114 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13115 DAG.getConstant(-(uint64_t)Align, VT));
13116 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13118 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13119 DAG.getIntPtrConstant(0, true), SDValue(),
13122 SDValue Ops[2] = { Tmp1, Tmp2 };
13123 return DAG.getMergeValues(Ops, dl);
13127 SDValue Chain = Op.getOperand(0);
13128 SDValue Size = Op.getOperand(1);
13129 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13130 EVT VT = Op.getNode()->getValueType(0);
13132 bool Is64Bit = Subtarget->is64Bit();
13133 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13136 MachineRegisterInfo &MRI = MF.getRegInfo();
13139 // The 64 bit implementation of segmented stacks needs to clobber both r10
13140 // r11. This makes it impossible to use it along with nested parameters.
13141 const Function *F = MF.getFunction();
13143 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13145 if (I->hasNestAttr())
13146 report_fatal_error("Cannot use segmented stacks with functions that "
13147 "have nested arguments.");
13150 const TargetRegisterClass *AddrRegClass =
13151 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13152 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13153 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13154 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13155 DAG.getRegister(Vreg, SPTy));
13156 SDValue Ops1[2] = { Value, Chain };
13157 return DAG.getMergeValues(Ops1, dl);
13160 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13162 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13163 Flag = Chain.getValue(1);
13164 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13166 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13168 const X86RegisterInfo *RegInfo =
13169 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
13170 unsigned SPReg = RegInfo->getStackRegister();
13171 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13172 Chain = SP.getValue(1);
13175 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13176 DAG.getConstant(-(uint64_t)Align, VT));
13177 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13180 SDValue Ops1[2] = { SP, Chain };
13181 return DAG.getMergeValues(Ops1, dl);
13185 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13186 MachineFunction &MF = DAG.getMachineFunction();
13187 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13189 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13192 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13193 // vastart just stores the address of the VarArgsFrameIndex slot into the
13194 // memory location argument.
13195 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13197 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13198 MachinePointerInfo(SV), false, false, 0);
13202 // gp_offset (0 - 6 * 8)
13203 // fp_offset (48 - 48 + 8 * 16)
13204 // overflow_arg_area (point to parameters coming in memory).
13206 SmallVector<SDValue, 8> MemOps;
13207 SDValue FIN = Op.getOperand(1);
13209 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13210 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13212 FIN, MachinePointerInfo(SV), false, false, 0);
13213 MemOps.push_back(Store);
13216 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13217 FIN, DAG.getIntPtrConstant(4));
13218 Store = DAG.getStore(Op.getOperand(0), DL,
13219 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13221 FIN, MachinePointerInfo(SV, 4), false, false, 0);
13222 MemOps.push_back(Store);
13224 // Store ptr to overflow_arg_area
13225 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13226 FIN, DAG.getIntPtrConstant(4));
13227 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13229 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13230 MachinePointerInfo(SV, 8),
13232 MemOps.push_back(Store);
13234 // Store ptr to reg_save_area.
13235 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13236 FIN, DAG.getIntPtrConstant(8));
13237 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13239 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13240 MachinePointerInfo(SV, 16), false, false, 0);
13241 MemOps.push_back(Store);
13242 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13245 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
13246 assert(Subtarget->is64Bit() &&
13247 "LowerVAARG only handles 64-bit va_arg!");
13248 assert((Subtarget->isTargetLinux() ||
13249 Subtarget->isTargetDarwin()) &&
13250 "Unhandled target in LowerVAARG");
13251 assert(Op.getNode()->getNumOperands() == 4);
13252 SDValue Chain = Op.getOperand(0);
13253 SDValue SrcPtr = Op.getOperand(1);
13254 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13255 unsigned Align = Op.getConstantOperandVal(3);
13258 EVT ArgVT = Op.getNode()->getValueType(0);
13259 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13260 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13263 // Decide which area this value should be read from.
13264 // TODO: Implement the AMD64 ABI in its entirety. This simple
13265 // selection mechanism works only for the basic types.
13266 if (ArgVT == MVT::f80) {
13267 llvm_unreachable("va_arg for f80 not yet implemented");
13268 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13269 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13270 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13271 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13273 llvm_unreachable("Unhandled argument type in LowerVAARG");
13276 if (ArgMode == 2) {
13277 // Sanity Check: Make sure using fp_offset makes sense.
13278 assert(!DAG.getTarget().Options.UseSoftFloat &&
13279 !(DAG.getMachineFunction()
13280 .getFunction()->getAttributes()
13281 .hasAttribute(AttributeSet::FunctionIndex,
13282 Attribute::NoImplicitFloat)) &&
13283 Subtarget->hasSSE1());
13286 // Insert VAARG_64 node into the DAG
13287 // VAARG_64 returns two values: Variable Argument Address, Chain
13288 SmallVector<SDValue, 11> InstOps;
13289 InstOps.push_back(Chain);
13290 InstOps.push_back(SrcPtr);
13291 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13292 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13293 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13294 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13295 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13296 VTs, InstOps, MVT::i64,
13297 MachinePointerInfo(SV),
13299 /*Volatile=*/false,
13301 /*WriteMem=*/true);
13302 Chain = VAARG.getValue(1);
13304 // Load the next argument and return it
13305 return DAG.getLoad(ArgVT, dl,
13308 MachinePointerInfo(),
13309 false, false, false, 0);
13312 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
13313 SelectionDAG &DAG) {
13314 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
13315 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
13316 SDValue Chain = Op.getOperand(0);
13317 SDValue DstPtr = Op.getOperand(1);
13318 SDValue SrcPtr = Op.getOperand(2);
13319 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
13320 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
13323 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
13324 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
13326 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
13329 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
13330 // amount is a constant. Takes immediate version of shift as input.
13331 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
13332 SDValue SrcOp, uint64_t ShiftAmt,
13333 SelectionDAG &DAG) {
13334 MVT ElementType = VT.getVectorElementType();
13336 // Fold this packed shift into its first operand if ShiftAmt is 0.
13340 // Check for ShiftAmt >= element width
13341 if (ShiftAmt >= ElementType.getSizeInBits()) {
13342 if (Opc == X86ISD::VSRAI)
13343 ShiftAmt = ElementType.getSizeInBits() - 1;
13345 return DAG.getConstant(0, VT);
13348 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
13349 && "Unknown target vector shift-by-constant node");
13351 // Fold this packed vector shift into a build vector if SrcOp is a
13352 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
13353 if (VT == SrcOp.getSimpleValueType() &&
13354 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
13355 SmallVector<SDValue, 8> Elts;
13356 unsigned NumElts = SrcOp->getNumOperands();
13357 ConstantSDNode *ND;
13360 default: llvm_unreachable(nullptr);
13361 case X86ISD::VSHLI:
13362 for (unsigned i=0; i!=NumElts; ++i) {
13363 SDValue CurrentOp = SrcOp->getOperand(i);
13364 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13365 Elts.push_back(CurrentOp);
13368 ND = cast<ConstantSDNode>(CurrentOp);
13369 const APInt &C = ND->getAPIntValue();
13370 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
13373 case X86ISD::VSRLI:
13374 for (unsigned i=0; i!=NumElts; ++i) {
13375 SDValue CurrentOp = SrcOp->getOperand(i);
13376 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13377 Elts.push_back(CurrentOp);
13380 ND = cast<ConstantSDNode>(CurrentOp);
13381 const APInt &C = ND->getAPIntValue();
13382 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
13385 case X86ISD::VSRAI:
13386 for (unsigned i=0; i!=NumElts; ++i) {
13387 SDValue CurrentOp = SrcOp->getOperand(i);
13388 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13389 Elts.push_back(CurrentOp);
13392 ND = cast<ConstantSDNode>(CurrentOp);
13393 const APInt &C = ND->getAPIntValue();
13394 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
13399 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13402 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
13405 // getTargetVShiftNode - Handle vector element shifts where the shift amount
13406 // may or may not be a constant. Takes immediate version of shift as input.
13407 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
13408 SDValue SrcOp, SDValue ShAmt,
13409 SelectionDAG &DAG) {
13410 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
13412 // Catch shift-by-constant.
13413 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
13414 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
13415 CShAmt->getZExtValue(), DAG);
13417 // Change opcode to non-immediate version
13419 default: llvm_unreachable("Unknown target vector shift node");
13420 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
13421 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
13422 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
13425 // Need to build a vector containing shift amount
13426 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
13429 ShOps[1] = DAG.getConstant(0, MVT::i32);
13430 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
13431 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
13433 // The return type has to be a 128-bit type with the same element
13434 // type as the input type.
13435 MVT EltVT = VT.getVectorElementType();
13436 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
13438 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
13439 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
13442 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
13444 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13446 default: return SDValue(); // Don't custom lower most intrinsics.
13447 // Comparison intrinsics.
13448 case Intrinsic::x86_sse_comieq_ss:
13449 case Intrinsic::x86_sse_comilt_ss:
13450 case Intrinsic::x86_sse_comile_ss:
13451 case Intrinsic::x86_sse_comigt_ss:
13452 case Intrinsic::x86_sse_comige_ss:
13453 case Intrinsic::x86_sse_comineq_ss:
13454 case Intrinsic::x86_sse_ucomieq_ss:
13455 case Intrinsic::x86_sse_ucomilt_ss:
13456 case Intrinsic::x86_sse_ucomile_ss:
13457 case Intrinsic::x86_sse_ucomigt_ss:
13458 case Intrinsic::x86_sse_ucomige_ss:
13459 case Intrinsic::x86_sse_ucomineq_ss:
13460 case Intrinsic::x86_sse2_comieq_sd:
13461 case Intrinsic::x86_sse2_comilt_sd:
13462 case Intrinsic::x86_sse2_comile_sd:
13463 case Intrinsic::x86_sse2_comigt_sd:
13464 case Intrinsic::x86_sse2_comige_sd:
13465 case Intrinsic::x86_sse2_comineq_sd:
13466 case Intrinsic::x86_sse2_ucomieq_sd:
13467 case Intrinsic::x86_sse2_ucomilt_sd:
13468 case Intrinsic::x86_sse2_ucomile_sd:
13469 case Intrinsic::x86_sse2_ucomigt_sd:
13470 case Intrinsic::x86_sse2_ucomige_sd:
13471 case Intrinsic::x86_sse2_ucomineq_sd: {
13475 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13476 case Intrinsic::x86_sse_comieq_ss:
13477 case Intrinsic::x86_sse2_comieq_sd:
13478 Opc = X86ISD::COMI;
13481 case Intrinsic::x86_sse_comilt_ss:
13482 case Intrinsic::x86_sse2_comilt_sd:
13483 Opc = X86ISD::COMI;
13486 case Intrinsic::x86_sse_comile_ss:
13487 case Intrinsic::x86_sse2_comile_sd:
13488 Opc = X86ISD::COMI;
13491 case Intrinsic::x86_sse_comigt_ss:
13492 case Intrinsic::x86_sse2_comigt_sd:
13493 Opc = X86ISD::COMI;
13496 case Intrinsic::x86_sse_comige_ss:
13497 case Intrinsic::x86_sse2_comige_sd:
13498 Opc = X86ISD::COMI;
13501 case Intrinsic::x86_sse_comineq_ss:
13502 case Intrinsic::x86_sse2_comineq_sd:
13503 Opc = X86ISD::COMI;
13506 case Intrinsic::x86_sse_ucomieq_ss:
13507 case Intrinsic::x86_sse2_ucomieq_sd:
13508 Opc = X86ISD::UCOMI;
13511 case Intrinsic::x86_sse_ucomilt_ss:
13512 case Intrinsic::x86_sse2_ucomilt_sd:
13513 Opc = X86ISD::UCOMI;
13516 case Intrinsic::x86_sse_ucomile_ss:
13517 case Intrinsic::x86_sse2_ucomile_sd:
13518 Opc = X86ISD::UCOMI;
13521 case Intrinsic::x86_sse_ucomigt_ss:
13522 case Intrinsic::x86_sse2_ucomigt_sd:
13523 Opc = X86ISD::UCOMI;
13526 case Intrinsic::x86_sse_ucomige_ss:
13527 case Intrinsic::x86_sse2_ucomige_sd:
13528 Opc = X86ISD::UCOMI;
13531 case Intrinsic::x86_sse_ucomineq_ss:
13532 case Intrinsic::x86_sse2_ucomineq_sd:
13533 Opc = X86ISD::UCOMI;
13538 SDValue LHS = Op.getOperand(1);
13539 SDValue RHS = Op.getOperand(2);
13540 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
13541 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
13542 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
13543 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13544 DAG.getConstant(X86CC, MVT::i8), Cond);
13545 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13548 // Arithmetic intrinsics.
13549 case Intrinsic::x86_sse2_pmulu_dq:
13550 case Intrinsic::x86_avx2_pmulu_dq:
13551 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
13552 Op.getOperand(1), Op.getOperand(2));
13554 case Intrinsic::x86_sse41_pmuldq:
13555 case Intrinsic::x86_avx2_pmul_dq:
13556 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
13557 Op.getOperand(1), Op.getOperand(2));
13559 case Intrinsic::x86_sse2_pmulhu_w:
13560 case Intrinsic::x86_avx2_pmulhu_w:
13561 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
13562 Op.getOperand(1), Op.getOperand(2));
13564 case Intrinsic::x86_sse2_pmulh_w:
13565 case Intrinsic::x86_avx2_pmulh_w:
13566 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
13567 Op.getOperand(1), Op.getOperand(2));
13569 // SSE2/AVX2 sub with unsigned saturation intrinsics
13570 case Intrinsic::x86_sse2_psubus_b:
13571 case Intrinsic::x86_sse2_psubus_w:
13572 case Intrinsic::x86_avx2_psubus_b:
13573 case Intrinsic::x86_avx2_psubus_w:
13574 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
13575 Op.getOperand(1), Op.getOperand(2));
13577 // SSE3/AVX horizontal add/sub intrinsics
13578 case Intrinsic::x86_sse3_hadd_ps:
13579 case Intrinsic::x86_sse3_hadd_pd:
13580 case Intrinsic::x86_avx_hadd_ps_256:
13581 case Intrinsic::x86_avx_hadd_pd_256:
13582 case Intrinsic::x86_sse3_hsub_ps:
13583 case Intrinsic::x86_sse3_hsub_pd:
13584 case Intrinsic::x86_avx_hsub_ps_256:
13585 case Intrinsic::x86_avx_hsub_pd_256:
13586 case Intrinsic::x86_ssse3_phadd_w_128:
13587 case Intrinsic::x86_ssse3_phadd_d_128:
13588 case Intrinsic::x86_avx2_phadd_w:
13589 case Intrinsic::x86_avx2_phadd_d:
13590 case Intrinsic::x86_ssse3_phsub_w_128:
13591 case Intrinsic::x86_ssse3_phsub_d_128:
13592 case Intrinsic::x86_avx2_phsub_w:
13593 case Intrinsic::x86_avx2_phsub_d: {
13596 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13597 case Intrinsic::x86_sse3_hadd_ps:
13598 case Intrinsic::x86_sse3_hadd_pd:
13599 case Intrinsic::x86_avx_hadd_ps_256:
13600 case Intrinsic::x86_avx_hadd_pd_256:
13601 Opcode = X86ISD::FHADD;
13603 case Intrinsic::x86_sse3_hsub_ps:
13604 case Intrinsic::x86_sse3_hsub_pd:
13605 case Intrinsic::x86_avx_hsub_ps_256:
13606 case Intrinsic::x86_avx_hsub_pd_256:
13607 Opcode = X86ISD::FHSUB;
13609 case Intrinsic::x86_ssse3_phadd_w_128:
13610 case Intrinsic::x86_ssse3_phadd_d_128:
13611 case Intrinsic::x86_avx2_phadd_w:
13612 case Intrinsic::x86_avx2_phadd_d:
13613 Opcode = X86ISD::HADD;
13615 case Intrinsic::x86_ssse3_phsub_w_128:
13616 case Intrinsic::x86_ssse3_phsub_d_128:
13617 case Intrinsic::x86_avx2_phsub_w:
13618 case Intrinsic::x86_avx2_phsub_d:
13619 Opcode = X86ISD::HSUB;
13622 return DAG.getNode(Opcode, dl, Op.getValueType(),
13623 Op.getOperand(1), Op.getOperand(2));
13626 // SSE2/SSE41/AVX2 integer max/min intrinsics.
13627 case Intrinsic::x86_sse2_pmaxu_b:
13628 case Intrinsic::x86_sse41_pmaxuw:
13629 case Intrinsic::x86_sse41_pmaxud:
13630 case Intrinsic::x86_avx2_pmaxu_b:
13631 case Intrinsic::x86_avx2_pmaxu_w:
13632 case Intrinsic::x86_avx2_pmaxu_d:
13633 case Intrinsic::x86_sse2_pminu_b:
13634 case Intrinsic::x86_sse41_pminuw:
13635 case Intrinsic::x86_sse41_pminud:
13636 case Intrinsic::x86_avx2_pminu_b:
13637 case Intrinsic::x86_avx2_pminu_w:
13638 case Intrinsic::x86_avx2_pminu_d:
13639 case Intrinsic::x86_sse41_pmaxsb:
13640 case Intrinsic::x86_sse2_pmaxs_w:
13641 case Intrinsic::x86_sse41_pmaxsd:
13642 case Intrinsic::x86_avx2_pmaxs_b:
13643 case Intrinsic::x86_avx2_pmaxs_w:
13644 case Intrinsic::x86_avx2_pmaxs_d:
13645 case Intrinsic::x86_sse41_pminsb:
13646 case Intrinsic::x86_sse2_pmins_w:
13647 case Intrinsic::x86_sse41_pminsd:
13648 case Intrinsic::x86_avx2_pmins_b:
13649 case Intrinsic::x86_avx2_pmins_w:
13650 case Intrinsic::x86_avx2_pmins_d: {
13653 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13654 case Intrinsic::x86_sse2_pmaxu_b:
13655 case Intrinsic::x86_sse41_pmaxuw:
13656 case Intrinsic::x86_sse41_pmaxud:
13657 case Intrinsic::x86_avx2_pmaxu_b:
13658 case Intrinsic::x86_avx2_pmaxu_w:
13659 case Intrinsic::x86_avx2_pmaxu_d:
13660 Opcode = X86ISD::UMAX;
13662 case Intrinsic::x86_sse2_pminu_b:
13663 case Intrinsic::x86_sse41_pminuw:
13664 case Intrinsic::x86_sse41_pminud:
13665 case Intrinsic::x86_avx2_pminu_b:
13666 case Intrinsic::x86_avx2_pminu_w:
13667 case Intrinsic::x86_avx2_pminu_d:
13668 Opcode = X86ISD::UMIN;
13670 case Intrinsic::x86_sse41_pmaxsb:
13671 case Intrinsic::x86_sse2_pmaxs_w:
13672 case Intrinsic::x86_sse41_pmaxsd:
13673 case Intrinsic::x86_avx2_pmaxs_b:
13674 case Intrinsic::x86_avx2_pmaxs_w:
13675 case Intrinsic::x86_avx2_pmaxs_d:
13676 Opcode = X86ISD::SMAX;
13678 case Intrinsic::x86_sse41_pminsb:
13679 case Intrinsic::x86_sse2_pmins_w:
13680 case Intrinsic::x86_sse41_pminsd:
13681 case Intrinsic::x86_avx2_pmins_b:
13682 case Intrinsic::x86_avx2_pmins_w:
13683 case Intrinsic::x86_avx2_pmins_d:
13684 Opcode = X86ISD::SMIN;
13687 return DAG.getNode(Opcode, dl, Op.getValueType(),
13688 Op.getOperand(1), Op.getOperand(2));
13691 // SSE/SSE2/AVX floating point max/min intrinsics.
13692 case Intrinsic::x86_sse_max_ps:
13693 case Intrinsic::x86_sse2_max_pd:
13694 case Intrinsic::x86_avx_max_ps_256:
13695 case Intrinsic::x86_avx_max_pd_256:
13696 case Intrinsic::x86_sse_min_ps:
13697 case Intrinsic::x86_sse2_min_pd:
13698 case Intrinsic::x86_avx_min_ps_256:
13699 case Intrinsic::x86_avx_min_pd_256: {
13702 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13703 case Intrinsic::x86_sse_max_ps:
13704 case Intrinsic::x86_sse2_max_pd:
13705 case Intrinsic::x86_avx_max_ps_256:
13706 case Intrinsic::x86_avx_max_pd_256:
13707 Opcode = X86ISD::FMAX;
13709 case Intrinsic::x86_sse_min_ps:
13710 case Intrinsic::x86_sse2_min_pd:
13711 case Intrinsic::x86_avx_min_ps_256:
13712 case Intrinsic::x86_avx_min_pd_256:
13713 Opcode = X86ISD::FMIN;
13716 return DAG.getNode(Opcode, dl, Op.getValueType(),
13717 Op.getOperand(1), Op.getOperand(2));
13720 // AVX2 variable shift intrinsics
13721 case Intrinsic::x86_avx2_psllv_d:
13722 case Intrinsic::x86_avx2_psllv_q:
13723 case Intrinsic::x86_avx2_psllv_d_256:
13724 case Intrinsic::x86_avx2_psllv_q_256:
13725 case Intrinsic::x86_avx2_psrlv_d:
13726 case Intrinsic::x86_avx2_psrlv_q:
13727 case Intrinsic::x86_avx2_psrlv_d_256:
13728 case Intrinsic::x86_avx2_psrlv_q_256:
13729 case Intrinsic::x86_avx2_psrav_d:
13730 case Intrinsic::x86_avx2_psrav_d_256: {
13733 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13734 case Intrinsic::x86_avx2_psllv_d:
13735 case Intrinsic::x86_avx2_psllv_q:
13736 case Intrinsic::x86_avx2_psllv_d_256:
13737 case Intrinsic::x86_avx2_psllv_q_256:
13740 case Intrinsic::x86_avx2_psrlv_d:
13741 case Intrinsic::x86_avx2_psrlv_q:
13742 case Intrinsic::x86_avx2_psrlv_d_256:
13743 case Intrinsic::x86_avx2_psrlv_q_256:
13746 case Intrinsic::x86_avx2_psrav_d:
13747 case Intrinsic::x86_avx2_psrav_d_256:
13751 return DAG.getNode(Opcode, dl, Op.getValueType(),
13752 Op.getOperand(1), Op.getOperand(2));
13755 case Intrinsic::x86_sse2_packssdw_128:
13756 case Intrinsic::x86_sse2_packsswb_128:
13757 case Intrinsic::x86_avx2_packssdw:
13758 case Intrinsic::x86_avx2_packsswb:
13759 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
13760 Op.getOperand(1), Op.getOperand(2));
13762 case Intrinsic::x86_sse2_packuswb_128:
13763 case Intrinsic::x86_sse41_packusdw:
13764 case Intrinsic::x86_avx2_packuswb:
13765 case Intrinsic::x86_avx2_packusdw:
13766 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
13767 Op.getOperand(1), Op.getOperand(2));
13769 case Intrinsic::x86_ssse3_pshuf_b_128:
13770 case Intrinsic::x86_avx2_pshuf_b:
13771 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
13772 Op.getOperand(1), Op.getOperand(2));
13774 case Intrinsic::x86_sse2_pshuf_d:
13775 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
13776 Op.getOperand(1), Op.getOperand(2));
13778 case Intrinsic::x86_sse2_pshufl_w:
13779 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
13780 Op.getOperand(1), Op.getOperand(2));
13782 case Intrinsic::x86_sse2_pshufh_w:
13783 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
13784 Op.getOperand(1), Op.getOperand(2));
13786 case Intrinsic::x86_ssse3_psign_b_128:
13787 case Intrinsic::x86_ssse3_psign_w_128:
13788 case Intrinsic::x86_ssse3_psign_d_128:
13789 case Intrinsic::x86_avx2_psign_b:
13790 case Intrinsic::x86_avx2_psign_w:
13791 case Intrinsic::x86_avx2_psign_d:
13792 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
13793 Op.getOperand(1), Op.getOperand(2));
13795 case Intrinsic::x86_sse41_insertps:
13796 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
13797 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13799 case Intrinsic::x86_avx_vperm2f128_ps_256:
13800 case Intrinsic::x86_avx_vperm2f128_pd_256:
13801 case Intrinsic::x86_avx_vperm2f128_si_256:
13802 case Intrinsic::x86_avx2_vperm2i128:
13803 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
13804 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13806 case Intrinsic::x86_avx2_permd:
13807 case Intrinsic::x86_avx2_permps:
13808 // Operands intentionally swapped. Mask is last operand to intrinsic,
13809 // but second operand for node/instruction.
13810 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
13811 Op.getOperand(2), Op.getOperand(1));
13813 case Intrinsic::x86_sse_sqrt_ps:
13814 case Intrinsic::x86_sse2_sqrt_pd:
13815 case Intrinsic::x86_avx_sqrt_ps_256:
13816 case Intrinsic::x86_avx_sqrt_pd_256:
13817 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
13819 // ptest and testp intrinsics. The intrinsic these come from are designed to
13820 // return an integer value, not just an instruction so lower it to the ptest
13821 // or testp pattern and a setcc for the result.
13822 case Intrinsic::x86_sse41_ptestz:
13823 case Intrinsic::x86_sse41_ptestc:
13824 case Intrinsic::x86_sse41_ptestnzc:
13825 case Intrinsic::x86_avx_ptestz_256:
13826 case Intrinsic::x86_avx_ptestc_256:
13827 case Intrinsic::x86_avx_ptestnzc_256:
13828 case Intrinsic::x86_avx_vtestz_ps:
13829 case Intrinsic::x86_avx_vtestc_ps:
13830 case Intrinsic::x86_avx_vtestnzc_ps:
13831 case Intrinsic::x86_avx_vtestz_pd:
13832 case Intrinsic::x86_avx_vtestc_pd:
13833 case Intrinsic::x86_avx_vtestnzc_pd:
13834 case Intrinsic::x86_avx_vtestz_ps_256:
13835 case Intrinsic::x86_avx_vtestc_ps_256:
13836 case Intrinsic::x86_avx_vtestnzc_ps_256:
13837 case Intrinsic::x86_avx_vtestz_pd_256:
13838 case Intrinsic::x86_avx_vtestc_pd_256:
13839 case Intrinsic::x86_avx_vtestnzc_pd_256: {
13840 bool IsTestPacked = false;
13843 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
13844 case Intrinsic::x86_avx_vtestz_ps:
13845 case Intrinsic::x86_avx_vtestz_pd:
13846 case Intrinsic::x86_avx_vtestz_ps_256:
13847 case Intrinsic::x86_avx_vtestz_pd_256:
13848 IsTestPacked = true; // Fallthrough
13849 case Intrinsic::x86_sse41_ptestz:
13850 case Intrinsic::x86_avx_ptestz_256:
13852 X86CC = X86::COND_E;
13854 case Intrinsic::x86_avx_vtestc_ps:
13855 case Intrinsic::x86_avx_vtestc_pd:
13856 case Intrinsic::x86_avx_vtestc_ps_256:
13857 case Intrinsic::x86_avx_vtestc_pd_256:
13858 IsTestPacked = true; // Fallthrough
13859 case Intrinsic::x86_sse41_ptestc:
13860 case Intrinsic::x86_avx_ptestc_256:
13862 X86CC = X86::COND_B;
13864 case Intrinsic::x86_avx_vtestnzc_ps:
13865 case Intrinsic::x86_avx_vtestnzc_pd:
13866 case Intrinsic::x86_avx_vtestnzc_ps_256:
13867 case Intrinsic::x86_avx_vtestnzc_pd_256:
13868 IsTestPacked = true; // Fallthrough
13869 case Intrinsic::x86_sse41_ptestnzc:
13870 case Intrinsic::x86_avx_ptestnzc_256:
13872 X86CC = X86::COND_A;
13876 SDValue LHS = Op.getOperand(1);
13877 SDValue RHS = Op.getOperand(2);
13878 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
13879 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
13880 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13881 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
13882 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13884 case Intrinsic::x86_avx512_kortestz_w:
13885 case Intrinsic::x86_avx512_kortestc_w: {
13886 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
13887 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
13888 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
13889 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13890 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
13891 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
13892 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13895 // SSE/AVX shift intrinsics
13896 case Intrinsic::x86_sse2_psll_w:
13897 case Intrinsic::x86_sse2_psll_d:
13898 case Intrinsic::x86_sse2_psll_q:
13899 case Intrinsic::x86_avx2_psll_w:
13900 case Intrinsic::x86_avx2_psll_d:
13901 case Intrinsic::x86_avx2_psll_q:
13902 case Intrinsic::x86_sse2_psrl_w:
13903 case Intrinsic::x86_sse2_psrl_d:
13904 case Intrinsic::x86_sse2_psrl_q:
13905 case Intrinsic::x86_avx2_psrl_w:
13906 case Intrinsic::x86_avx2_psrl_d:
13907 case Intrinsic::x86_avx2_psrl_q:
13908 case Intrinsic::x86_sse2_psra_w:
13909 case Intrinsic::x86_sse2_psra_d:
13910 case Intrinsic::x86_avx2_psra_w:
13911 case Intrinsic::x86_avx2_psra_d: {
13914 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13915 case Intrinsic::x86_sse2_psll_w:
13916 case Intrinsic::x86_sse2_psll_d:
13917 case Intrinsic::x86_sse2_psll_q:
13918 case Intrinsic::x86_avx2_psll_w:
13919 case Intrinsic::x86_avx2_psll_d:
13920 case Intrinsic::x86_avx2_psll_q:
13921 Opcode = X86ISD::VSHL;
13923 case Intrinsic::x86_sse2_psrl_w:
13924 case Intrinsic::x86_sse2_psrl_d:
13925 case Intrinsic::x86_sse2_psrl_q:
13926 case Intrinsic::x86_avx2_psrl_w:
13927 case Intrinsic::x86_avx2_psrl_d:
13928 case Intrinsic::x86_avx2_psrl_q:
13929 Opcode = X86ISD::VSRL;
13931 case Intrinsic::x86_sse2_psra_w:
13932 case Intrinsic::x86_sse2_psra_d:
13933 case Intrinsic::x86_avx2_psra_w:
13934 case Intrinsic::x86_avx2_psra_d:
13935 Opcode = X86ISD::VSRA;
13938 return DAG.getNode(Opcode, dl, Op.getValueType(),
13939 Op.getOperand(1), Op.getOperand(2));
13942 // SSE/AVX immediate shift intrinsics
13943 case Intrinsic::x86_sse2_pslli_w:
13944 case Intrinsic::x86_sse2_pslli_d:
13945 case Intrinsic::x86_sse2_pslli_q:
13946 case Intrinsic::x86_avx2_pslli_w:
13947 case Intrinsic::x86_avx2_pslli_d:
13948 case Intrinsic::x86_avx2_pslli_q:
13949 case Intrinsic::x86_sse2_psrli_w:
13950 case Intrinsic::x86_sse2_psrli_d:
13951 case Intrinsic::x86_sse2_psrli_q:
13952 case Intrinsic::x86_avx2_psrli_w:
13953 case Intrinsic::x86_avx2_psrli_d:
13954 case Intrinsic::x86_avx2_psrli_q:
13955 case Intrinsic::x86_sse2_psrai_w:
13956 case Intrinsic::x86_sse2_psrai_d:
13957 case Intrinsic::x86_avx2_psrai_w:
13958 case Intrinsic::x86_avx2_psrai_d: {
13961 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13962 case Intrinsic::x86_sse2_pslli_w:
13963 case Intrinsic::x86_sse2_pslli_d:
13964 case Intrinsic::x86_sse2_pslli_q:
13965 case Intrinsic::x86_avx2_pslli_w:
13966 case Intrinsic::x86_avx2_pslli_d:
13967 case Intrinsic::x86_avx2_pslli_q:
13968 Opcode = X86ISD::VSHLI;
13970 case Intrinsic::x86_sse2_psrli_w:
13971 case Intrinsic::x86_sse2_psrli_d:
13972 case Intrinsic::x86_sse2_psrli_q:
13973 case Intrinsic::x86_avx2_psrli_w:
13974 case Intrinsic::x86_avx2_psrli_d:
13975 case Intrinsic::x86_avx2_psrli_q:
13976 Opcode = X86ISD::VSRLI;
13978 case Intrinsic::x86_sse2_psrai_w:
13979 case Intrinsic::x86_sse2_psrai_d:
13980 case Intrinsic::x86_avx2_psrai_w:
13981 case Intrinsic::x86_avx2_psrai_d:
13982 Opcode = X86ISD::VSRAI;
13985 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
13986 Op.getOperand(1), Op.getOperand(2), DAG);
13989 case Intrinsic::x86_sse42_pcmpistria128:
13990 case Intrinsic::x86_sse42_pcmpestria128:
13991 case Intrinsic::x86_sse42_pcmpistric128:
13992 case Intrinsic::x86_sse42_pcmpestric128:
13993 case Intrinsic::x86_sse42_pcmpistrio128:
13994 case Intrinsic::x86_sse42_pcmpestrio128:
13995 case Intrinsic::x86_sse42_pcmpistris128:
13996 case Intrinsic::x86_sse42_pcmpestris128:
13997 case Intrinsic::x86_sse42_pcmpistriz128:
13998 case Intrinsic::x86_sse42_pcmpestriz128: {
14002 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14003 case Intrinsic::x86_sse42_pcmpistria128:
14004 Opcode = X86ISD::PCMPISTRI;
14005 X86CC = X86::COND_A;
14007 case Intrinsic::x86_sse42_pcmpestria128:
14008 Opcode = X86ISD::PCMPESTRI;
14009 X86CC = X86::COND_A;
14011 case Intrinsic::x86_sse42_pcmpistric128:
14012 Opcode = X86ISD::PCMPISTRI;
14013 X86CC = X86::COND_B;
14015 case Intrinsic::x86_sse42_pcmpestric128:
14016 Opcode = X86ISD::PCMPESTRI;
14017 X86CC = X86::COND_B;
14019 case Intrinsic::x86_sse42_pcmpistrio128:
14020 Opcode = X86ISD::PCMPISTRI;
14021 X86CC = X86::COND_O;
14023 case Intrinsic::x86_sse42_pcmpestrio128:
14024 Opcode = X86ISD::PCMPESTRI;
14025 X86CC = X86::COND_O;
14027 case Intrinsic::x86_sse42_pcmpistris128:
14028 Opcode = X86ISD::PCMPISTRI;
14029 X86CC = X86::COND_S;
14031 case Intrinsic::x86_sse42_pcmpestris128:
14032 Opcode = X86ISD::PCMPESTRI;
14033 X86CC = X86::COND_S;
14035 case Intrinsic::x86_sse42_pcmpistriz128:
14036 Opcode = X86ISD::PCMPISTRI;
14037 X86CC = X86::COND_E;
14039 case Intrinsic::x86_sse42_pcmpestriz128:
14040 Opcode = X86ISD::PCMPESTRI;
14041 X86CC = X86::COND_E;
14044 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14045 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14046 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14047 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14048 DAG.getConstant(X86CC, MVT::i8),
14049 SDValue(PCMP.getNode(), 1));
14050 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14053 case Intrinsic::x86_sse42_pcmpistri128:
14054 case Intrinsic::x86_sse42_pcmpestri128: {
14056 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14057 Opcode = X86ISD::PCMPISTRI;
14059 Opcode = X86ISD::PCMPESTRI;
14061 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14062 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14063 return DAG.getNode(Opcode, dl, VTs, NewOps);
14065 case Intrinsic::x86_fma_vfmadd_ps:
14066 case Intrinsic::x86_fma_vfmadd_pd:
14067 case Intrinsic::x86_fma_vfmsub_ps:
14068 case Intrinsic::x86_fma_vfmsub_pd:
14069 case Intrinsic::x86_fma_vfnmadd_ps:
14070 case Intrinsic::x86_fma_vfnmadd_pd:
14071 case Intrinsic::x86_fma_vfnmsub_ps:
14072 case Intrinsic::x86_fma_vfnmsub_pd:
14073 case Intrinsic::x86_fma_vfmaddsub_ps:
14074 case Intrinsic::x86_fma_vfmaddsub_pd:
14075 case Intrinsic::x86_fma_vfmsubadd_ps:
14076 case Intrinsic::x86_fma_vfmsubadd_pd:
14077 case Intrinsic::x86_fma_vfmadd_ps_256:
14078 case Intrinsic::x86_fma_vfmadd_pd_256:
14079 case Intrinsic::x86_fma_vfmsub_ps_256:
14080 case Intrinsic::x86_fma_vfmsub_pd_256:
14081 case Intrinsic::x86_fma_vfnmadd_ps_256:
14082 case Intrinsic::x86_fma_vfnmadd_pd_256:
14083 case Intrinsic::x86_fma_vfnmsub_ps_256:
14084 case Intrinsic::x86_fma_vfnmsub_pd_256:
14085 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14086 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14087 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14088 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14089 case Intrinsic::x86_fma_vfmadd_ps_512:
14090 case Intrinsic::x86_fma_vfmadd_pd_512:
14091 case Intrinsic::x86_fma_vfmsub_ps_512:
14092 case Intrinsic::x86_fma_vfmsub_pd_512:
14093 case Intrinsic::x86_fma_vfnmadd_ps_512:
14094 case Intrinsic::x86_fma_vfnmadd_pd_512:
14095 case Intrinsic::x86_fma_vfnmsub_ps_512:
14096 case Intrinsic::x86_fma_vfnmsub_pd_512:
14097 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14098 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14099 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14100 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
14103 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14104 case Intrinsic::x86_fma_vfmadd_ps:
14105 case Intrinsic::x86_fma_vfmadd_pd:
14106 case Intrinsic::x86_fma_vfmadd_ps_256:
14107 case Intrinsic::x86_fma_vfmadd_pd_256:
14108 case Intrinsic::x86_fma_vfmadd_ps_512:
14109 case Intrinsic::x86_fma_vfmadd_pd_512:
14110 Opc = X86ISD::FMADD;
14112 case Intrinsic::x86_fma_vfmsub_ps:
14113 case Intrinsic::x86_fma_vfmsub_pd:
14114 case Intrinsic::x86_fma_vfmsub_ps_256:
14115 case Intrinsic::x86_fma_vfmsub_pd_256:
14116 case Intrinsic::x86_fma_vfmsub_ps_512:
14117 case Intrinsic::x86_fma_vfmsub_pd_512:
14118 Opc = X86ISD::FMSUB;
14120 case Intrinsic::x86_fma_vfnmadd_ps:
14121 case Intrinsic::x86_fma_vfnmadd_pd:
14122 case Intrinsic::x86_fma_vfnmadd_ps_256:
14123 case Intrinsic::x86_fma_vfnmadd_pd_256:
14124 case Intrinsic::x86_fma_vfnmadd_ps_512:
14125 case Intrinsic::x86_fma_vfnmadd_pd_512:
14126 Opc = X86ISD::FNMADD;
14128 case Intrinsic::x86_fma_vfnmsub_ps:
14129 case Intrinsic::x86_fma_vfnmsub_pd:
14130 case Intrinsic::x86_fma_vfnmsub_ps_256:
14131 case Intrinsic::x86_fma_vfnmsub_pd_256:
14132 case Intrinsic::x86_fma_vfnmsub_ps_512:
14133 case Intrinsic::x86_fma_vfnmsub_pd_512:
14134 Opc = X86ISD::FNMSUB;
14136 case Intrinsic::x86_fma_vfmaddsub_ps:
14137 case Intrinsic::x86_fma_vfmaddsub_pd:
14138 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14139 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14140 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14141 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14142 Opc = X86ISD::FMADDSUB;
14144 case Intrinsic::x86_fma_vfmsubadd_ps:
14145 case Intrinsic::x86_fma_vfmsubadd_pd:
14146 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14147 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14148 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14149 case Intrinsic::x86_fma_vfmsubadd_pd_512:
14150 Opc = X86ISD::FMSUBADD;
14154 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
14155 Op.getOperand(2), Op.getOperand(3));
14160 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14161 SDValue Src, SDValue Mask, SDValue Base,
14162 SDValue Index, SDValue ScaleOp, SDValue Chain,
14163 const X86Subtarget * Subtarget) {
14165 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14166 assert(C && "Invalid scale type");
14167 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14168 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14169 Index.getSimpleValueType().getVectorNumElements());
14171 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14173 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14175 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14176 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14177 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14178 SDValue Segment = DAG.getRegister(0, MVT::i32);
14179 if (Src.getOpcode() == ISD::UNDEF)
14180 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14181 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14182 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14183 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14184 return DAG.getMergeValues(RetOps, dl);
14187 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14188 SDValue Src, SDValue Mask, SDValue Base,
14189 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14191 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14192 assert(C && "Invalid scale type");
14193 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14194 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14195 SDValue Segment = DAG.getRegister(0, MVT::i32);
14196 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14197 Index.getSimpleValueType().getVectorNumElements());
14199 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14201 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14203 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14204 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14205 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14206 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14207 return SDValue(Res, 1);
14210 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14211 SDValue Mask, SDValue Base, SDValue Index,
14212 SDValue ScaleOp, SDValue Chain) {
14214 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14215 assert(C && "Invalid scale type");
14216 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14217 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14218 SDValue Segment = DAG.getRegister(0, MVT::i32);
14220 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14222 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14224 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14226 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14227 //SDVTList VTs = DAG.getVTList(MVT::Other);
14228 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14229 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14230 return SDValue(Res, 0);
14233 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14234 // read performance monitor counters (x86_rdpmc).
14235 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14236 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14237 SmallVectorImpl<SDValue> &Results) {
14238 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14239 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14242 // The ECX register is used to select the index of the performance counter
14244 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14246 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14248 // Reads the content of a 64-bit performance counter and returns it in the
14249 // registers EDX:EAX.
14250 if (Subtarget->is64Bit()) {
14251 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14252 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14255 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14256 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14259 Chain = HI.getValue(1);
14261 if (Subtarget->is64Bit()) {
14262 // The EAX register is loaded with the low-order 32 bits. The EDX register
14263 // is loaded with the supported high-order bits of the counter.
14264 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14265 DAG.getConstant(32, MVT::i8));
14266 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14267 Results.push_back(Chain);
14271 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14272 SDValue Ops[] = { LO, HI };
14273 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14274 Results.push_back(Pair);
14275 Results.push_back(Chain);
14278 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14279 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14280 // also used to custom lower READCYCLECOUNTER nodes.
14281 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14282 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14283 SmallVectorImpl<SDValue> &Results) {
14284 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14285 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14288 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14289 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14290 // and the EAX register is loaded with the low-order 32 bits.
14291 if (Subtarget->is64Bit()) {
14292 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14293 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14296 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14297 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14300 SDValue Chain = HI.getValue(1);
14302 if (Opcode == X86ISD::RDTSCP_DAG) {
14303 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14305 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14306 // the ECX register. Add 'ecx' explicitly to the chain.
14307 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14309 // Explicitly store the content of ECX at the location passed in input
14310 // to the 'rdtscp' intrinsic.
14311 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14312 MachinePointerInfo(), false, false, 0);
14315 if (Subtarget->is64Bit()) {
14316 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14317 // the EAX register is loaded with the low-order 32 bits.
14318 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14319 DAG.getConstant(32, MVT::i8));
14320 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14321 Results.push_back(Chain);
14325 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14326 SDValue Ops[] = { LO, HI };
14327 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14328 Results.push_back(Pair);
14329 Results.push_back(Chain);
14332 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14333 SelectionDAG &DAG) {
14334 SmallVector<SDValue, 2> Results;
14336 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14338 return DAG.getMergeValues(Results, DL);
14341 enum IntrinsicType {
14342 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
14345 struct IntrinsicData {
14346 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
14347 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
14348 IntrinsicType Type;
14353 std::map < unsigned, IntrinsicData> IntrMap;
14354 static void InitIntinsicsMap() {
14355 static bool Initialized = false;
14358 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14359 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14360 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14361 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14362 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
14363 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
14364 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
14365 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
14366 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
14367 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
14368 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
14369 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
14370 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
14371 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
14372 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
14373 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
14374 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
14375 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
14377 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
14378 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
14379 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
14380 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
14381 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
14382 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
14383 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
14384 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
14385 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
14386 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
14387 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
14388 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
14389 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
14390 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
14391 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
14392 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
14394 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
14395 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
14396 X86::VGATHERPF1QPSm)));
14397 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
14398 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
14399 X86::VGATHERPF1QPDm)));
14400 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
14401 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
14402 X86::VGATHERPF1DPDm)));
14403 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
14404 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
14405 X86::VGATHERPF1DPSm)));
14406 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
14407 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
14408 X86::VSCATTERPF1QPSm)));
14409 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
14410 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
14411 X86::VSCATTERPF1QPDm)));
14412 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
14413 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
14414 X86::VSCATTERPF1DPDm)));
14415 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
14416 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
14417 X86::VSCATTERPF1DPSm)));
14418 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
14419 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14420 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
14421 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14422 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
14423 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14424 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
14425 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14426 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
14427 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14428 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
14429 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14430 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
14431 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
14432 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
14433 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
14434 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
14435 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
14436 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
14437 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
14438 Initialized = true;
14441 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14442 SelectionDAG &DAG) {
14443 InitIntinsicsMap();
14444 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14445 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
14446 if (itr == IntrMap.end())
14450 IntrinsicData Intr = itr->second;
14451 switch(Intr.Type) {
14454 // Emit the node with the right value type.
14455 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14456 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
14458 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
14459 // Otherwise return the value from Rand, which is always 0, casted to i32.
14460 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
14461 DAG.getConstant(1, Op->getValueType(1)),
14462 DAG.getConstant(X86::COND_B, MVT::i32),
14463 SDValue(Result.getNode(), 1) };
14464 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14465 DAG.getVTList(Op->getValueType(1), MVT::Glue),
14468 // Return { result, isValid, chain }.
14469 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
14470 SDValue(Result.getNode(), 2));
14473 //gather(v1, mask, index, base, scale);
14474 SDValue Chain = Op.getOperand(0);
14475 SDValue Src = Op.getOperand(2);
14476 SDValue Base = Op.getOperand(3);
14477 SDValue Index = Op.getOperand(4);
14478 SDValue Mask = Op.getOperand(5);
14479 SDValue Scale = Op.getOperand(6);
14480 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
14484 //scatter(base, mask, index, v1, scale);
14485 SDValue Chain = Op.getOperand(0);
14486 SDValue Base = Op.getOperand(2);
14487 SDValue Mask = Op.getOperand(3);
14488 SDValue Index = Op.getOperand(4);
14489 SDValue Src = Op.getOperand(5);
14490 SDValue Scale = Op.getOperand(6);
14491 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
14494 SDValue Hint = Op.getOperand(6);
14496 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
14497 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
14498 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
14499 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
14500 SDValue Chain = Op.getOperand(0);
14501 SDValue Mask = Op.getOperand(2);
14502 SDValue Index = Op.getOperand(3);
14503 SDValue Base = Op.getOperand(4);
14504 SDValue Scale = Op.getOperand(5);
14505 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
14507 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
14509 SmallVector<SDValue, 2> Results;
14510 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
14511 return DAG.getMergeValues(Results, dl);
14513 // Read Performance Monitoring Counters.
14515 SmallVector<SDValue, 2> Results;
14516 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
14517 return DAG.getMergeValues(Results, dl);
14519 // XTEST intrinsics.
14521 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
14522 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
14523 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14524 DAG.getConstant(X86::COND_NE, MVT::i8),
14526 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
14527 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
14528 Ret, SDValue(InTrans.getNode(), 1));
14531 llvm_unreachable("Unknown Intrinsic Type");
14534 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
14535 SelectionDAG &DAG) const {
14536 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14537 MFI->setReturnAddressIsTaken(true);
14539 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
14542 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14544 EVT PtrVT = getPointerTy();
14547 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
14548 const X86RegisterInfo *RegInfo =
14549 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14550 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
14551 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14552 DAG.getNode(ISD::ADD, dl, PtrVT,
14553 FrameAddr, Offset),
14554 MachinePointerInfo(), false, false, false, 0);
14557 // Just load the return address.
14558 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
14559 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14560 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
14563 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
14564 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14565 MFI->setFrameAddressIsTaken(true);
14567 EVT VT = Op.getValueType();
14568 SDLoc dl(Op); // FIXME probably not meaningful
14569 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14570 const X86RegisterInfo *RegInfo =
14571 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14572 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14573 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
14574 (FrameReg == X86::EBP && VT == MVT::i32)) &&
14575 "Invalid Frame Register!");
14576 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
14578 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
14579 MachinePointerInfo(),
14580 false, false, false, 0);
14584 // FIXME? Maybe this could be a TableGen attribute on some registers and
14585 // this table could be generated automatically from RegInfo.
14586 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
14588 unsigned Reg = StringSwitch<unsigned>(RegName)
14589 .Case("esp", X86::ESP)
14590 .Case("rsp", X86::RSP)
14594 report_fatal_error("Invalid register name global variable");
14597 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
14598 SelectionDAG &DAG) const {
14599 const X86RegisterInfo *RegInfo =
14600 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14601 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
14604 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
14605 SDValue Chain = Op.getOperand(0);
14606 SDValue Offset = Op.getOperand(1);
14607 SDValue Handler = Op.getOperand(2);
14610 EVT PtrVT = getPointerTy();
14611 const X86RegisterInfo *RegInfo =
14612 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14613 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14614 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
14615 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
14616 "Invalid Frame Register!");
14617 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
14618 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
14620 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
14621 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
14622 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
14623 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
14625 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
14627 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
14628 DAG.getRegister(StoreAddrReg, PtrVT));
14631 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
14632 SelectionDAG &DAG) const {
14634 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
14635 DAG.getVTList(MVT::i32, MVT::Other),
14636 Op.getOperand(0), Op.getOperand(1));
14639 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
14640 SelectionDAG &DAG) const {
14642 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
14643 Op.getOperand(0), Op.getOperand(1));
14646 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
14647 return Op.getOperand(0);
14650 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
14651 SelectionDAG &DAG) const {
14652 SDValue Root = Op.getOperand(0);
14653 SDValue Trmp = Op.getOperand(1); // trampoline
14654 SDValue FPtr = Op.getOperand(2); // nested function
14655 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
14658 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14659 const TargetRegisterInfo* TRI = DAG.getTarget().getRegisterInfo();
14661 if (Subtarget->is64Bit()) {
14662 SDValue OutChains[6];
14664 // Large code-model.
14665 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
14666 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
14668 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
14669 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
14671 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
14673 // Load the pointer to the nested function into R11.
14674 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
14675 SDValue Addr = Trmp;
14676 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14677 Addr, MachinePointerInfo(TrmpAddr),
14680 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14681 DAG.getConstant(2, MVT::i64));
14682 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
14683 MachinePointerInfo(TrmpAddr, 2),
14686 // Load the 'nest' parameter value into R10.
14687 // R10 is specified in X86CallingConv.td
14688 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
14689 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14690 DAG.getConstant(10, MVT::i64));
14691 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14692 Addr, MachinePointerInfo(TrmpAddr, 10),
14695 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14696 DAG.getConstant(12, MVT::i64));
14697 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
14698 MachinePointerInfo(TrmpAddr, 12),
14701 // Jump to the nested function.
14702 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
14703 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14704 DAG.getConstant(20, MVT::i64));
14705 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14706 Addr, MachinePointerInfo(TrmpAddr, 20),
14709 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
14710 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14711 DAG.getConstant(22, MVT::i64));
14712 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
14713 MachinePointerInfo(TrmpAddr, 22),
14716 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14718 const Function *Func =
14719 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
14720 CallingConv::ID CC = Func->getCallingConv();
14725 llvm_unreachable("Unsupported calling convention");
14726 case CallingConv::C:
14727 case CallingConv::X86_StdCall: {
14728 // Pass 'nest' parameter in ECX.
14729 // Must be kept in sync with X86CallingConv.td
14730 NestReg = X86::ECX;
14732 // Check that ECX wasn't needed by an 'inreg' parameter.
14733 FunctionType *FTy = Func->getFunctionType();
14734 const AttributeSet &Attrs = Func->getAttributes();
14736 if (!Attrs.isEmpty() && !Func->isVarArg()) {
14737 unsigned InRegCount = 0;
14740 for (FunctionType::param_iterator I = FTy->param_begin(),
14741 E = FTy->param_end(); I != E; ++I, ++Idx)
14742 if (Attrs.hasAttribute(Idx, Attribute::InReg))
14743 // FIXME: should only count parameters that are lowered to integers.
14744 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
14746 if (InRegCount > 2) {
14747 report_fatal_error("Nest register in use - reduce number of inreg"
14753 case CallingConv::X86_FastCall:
14754 case CallingConv::X86_ThisCall:
14755 case CallingConv::Fast:
14756 // Pass 'nest' parameter in EAX.
14757 // Must be kept in sync with X86CallingConv.td
14758 NestReg = X86::EAX;
14762 SDValue OutChains[4];
14763 SDValue Addr, Disp;
14765 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14766 DAG.getConstant(10, MVT::i32));
14767 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
14769 // This is storing the opcode for MOV32ri.
14770 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
14771 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
14772 OutChains[0] = DAG.getStore(Root, dl,
14773 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
14774 Trmp, MachinePointerInfo(TrmpAddr),
14777 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14778 DAG.getConstant(1, MVT::i32));
14779 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
14780 MachinePointerInfo(TrmpAddr, 1),
14783 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
14784 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14785 DAG.getConstant(5, MVT::i32));
14786 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
14787 MachinePointerInfo(TrmpAddr, 5),
14790 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14791 DAG.getConstant(6, MVT::i32));
14792 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
14793 MachinePointerInfo(TrmpAddr, 6),
14796 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14800 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
14801 SelectionDAG &DAG) const {
14803 The rounding mode is in bits 11:10 of FPSR, and has the following
14805 00 Round to nearest
14810 FLT_ROUNDS, on the other hand, expects the following:
14817 To perform the conversion, we do:
14818 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
14821 MachineFunction &MF = DAG.getMachineFunction();
14822 const TargetMachine &TM = MF.getTarget();
14823 const TargetFrameLowering &TFI = *TM.getFrameLowering();
14824 unsigned StackAlignment = TFI.getStackAlignment();
14825 MVT VT = Op.getSimpleValueType();
14828 // Save FP Control Word to stack slot
14829 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
14830 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14832 MachineMemOperand *MMO =
14833 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14834 MachineMemOperand::MOStore, 2, 2);
14836 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
14837 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
14838 DAG.getVTList(MVT::Other),
14839 Ops, MVT::i16, MMO);
14841 // Load FP Control Word from stack slot
14842 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
14843 MachinePointerInfo(), false, false, false, 0);
14845 // Transform as necessary
14847 DAG.getNode(ISD::SRL, DL, MVT::i16,
14848 DAG.getNode(ISD::AND, DL, MVT::i16,
14849 CWD, DAG.getConstant(0x800, MVT::i16)),
14850 DAG.getConstant(11, MVT::i8));
14852 DAG.getNode(ISD::SRL, DL, MVT::i16,
14853 DAG.getNode(ISD::AND, DL, MVT::i16,
14854 CWD, DAG.getConstant(0x400, MVT::i16)),
14855 DAG.getConstant(9, MVT::i8));
14858 DAG.getNode(ISD::AND, DL, MVT::i16,
14859 DAG.getNode(ISD::ADD, DL, MVT::i16,
14860 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
14861 DAG.getConstant(1, MVT::i16)),
14862 DAG.getConstant(3, MVT::i16));
14864 return DAG.getNode((VT.getSizeInBits() < 16 ?
14865 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
14868 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
14869 MVT VT = Op.getSimpleValueType();
14871 unsigned NumBits = VT.getSizeInBits();
14874 Op = Op.getOperand(0);
14875 if (VT == MVT::i8) {
14876 // Zero extend to i32 since there is not an i8 bsr.
14878 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14881 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
14882 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14883 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14885 // If src is zero (i.e. bsr sets ZF), returns NumBits.
14888 DAG.getConstant(NumBits+NumBits-1, OpVT),
14889 DAG.getConstant(X86::COND_E, MVT::i8),
14892 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
14894 // Finally xor with NumBits-1.
14895 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14898 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14902 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
14903 MVT VT = Op.getSimpleValueType();
14905 unsigned NumBits = VT.getSizeInBits();
14908 Op = Op.getOperand(0);
14909 if (VT == MVT::i8) {
14910 // Zero extend to i32 since there is not an i8 bsr.
14912 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14915 // Issue a bsr (scan bits in reverse).
14916 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14917 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14919 // And xor with NumBits-1.
14920 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14923 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14927 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
14928 MVT VT = Op.getSimpleValueType();
14929 unsigned NumBits = VT.getSizeInBits();
14931 Op = Op.getOperand(0);
14933 // Issue a bsf (scan bits forward) which also sets EFLAGS.
14934 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
14935 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
14937 // If src is zero (i.e. bsf sets ZF), returns NumBits.
14940 DAG.getConstant(NumBits, VT),
14941 DAG.getConstant(X86::COND_E, MVT::i8),
14944 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
14947 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
14948 // ones, and then concatenate the result back.
14949 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
14950 MVT VT = Op.getSimpleValueType();
14952 assert(VT.is256BitVector() && VT.isInteger() &&
14953 "Unsupported value type for operation");
14955 unsigned NumElems = VT.getVectorNumElements();
14958 // Extract the LHS vectors
14959 SDValue LHS = Op.getOperand(0);
14960 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14961 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14963 // Extract the RHS vectors
14964 SDValue RHS = Op.getOperand(1);
14965 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14966 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14968 MVT EltVT = VT.getVectorElementType();
14969 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14971 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14972 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
14973 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
14976 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
14977 assert(Op.getSimpleValueType().is256BitVector() &&
14978 Op.getSimpleValueType().isInteger() &&
14979 "Only handle AVX 256-bit vector integer operation");
14980 return Lower256IntArith(Op, DAG);
14983 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
14984 assert(Op.getSimpleValueType().is256BitVector() &&
14985 Op.getSimpleValueType().isInteger() &&
14986 "Only handle AVX 256-bit vector integer operation");
14987 return Lower256IntArith(Op, DAG);
14990 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
14991 SelectionDAG &DAG) {
14993 MVT VT = Op.getSimpleValueType();
14995 // Decompose 256-bit ops into smaller 128-bit ops.
14996 if (VT.is256BitVector() && !Subtarget->hasInt256())
14997 return Lower256IntArith(Op, DAG);
14999 SDValue A = Op.getOperand(0);
15000 SDValue B = Op.getOperand(1);
15002 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15003 if (VT == MVT::v4i32) {
15004 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15005 "Should not custom lower when pmuldq is available!");
15007 // Extract the odd parts.
15008 static const int UnpackMask[] = { 1, -1, 3, -1 };
15009 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15010 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15012 // Multiply the even parts.
15013 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15014 // Now multiply odd parts.
15015 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15017 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15018 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15020 // Merge the two vectors back together with a shuffle. This expands into 2
15022 static const int ShufMask[] = { 0, 4, 2, 6 };
15023 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15026 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15027 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15029 // Ahi = psrlqi(a, 32);
15030 // Bhi = psrlqi(b, 32);
15032 // AloBlo = pmuludq(a, b);
15033 // AloBhi = pmuludq(a, Bhi);
15034 // AhiBlo = pmuludq(Ahi, b);
15036 // AloBhi = psllqi(AloBhi, 32);
15037 // AhiBlo = psllqi(AhiBlo, 32);
15038 // return AloBlo + AloBhi + AhiBlo;
15040 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15041 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15043 // Bit cast to 32-bit vectors for MULUDQ
15044 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15045 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15046 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15047 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15048 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15049 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15051 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15052 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15053 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15055 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15056 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15058 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15059 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15062 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15063 assert(Subtarget->isTargetWin64() && "Unexpected target");
15064 EVT VT = Op.getValueType();
15065 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15066 "Unexpected return type for lowering");
15070 switch (Op->getOpcode()) {
15071 default: llvm_unreachable("Unexpected request for libcall!");
15072 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15073 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15074 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15075 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15076 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15077 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15081 SDValue InChain = DAG.getEntryNode();
15083 TargetLowering::ArgListTy Args;
15084 TargetLowering::ArgListEntry Entry;
15085 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15086 EVT ArgVT = Op->getOperand(i).getValueType();
15087 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15088 "Unexpected argument type for lowering");
15089 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15090 Entry.Node = StackPtr;
15091 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15093 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15094 Entry.Ty = PointerType::get(ArgTy,0);
15095 Entry.isSExt = false;
15096 Entry.isZExt = false;
15097 Args.push_back(Entry);
15100 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15103 TargetLowering::CallLoweringInfo CLI(DAG);
15104 CLI.setDebugLoc(dl).setChain(InChain)
15105 .setCallee(getLibcallCallingConv(LC),
15106 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15107 Callee, std::move(Args), 0)
15108 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15110 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15111 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15114 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15115 SelectionDAG &DAG) {
15116 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15117 EVT VT = Op0.getValueType();
15120 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15121 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15123 // Get the high parts.
15124 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15125 SDValue Hi0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15126 SDValue Hi1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15128 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15130 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15131 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15133 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15134 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15135 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15136 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15137 DAG.getNode(Opcode, dl, MulVT, Hi0, Hi1));
15139 // Shuffle it back into the right order.
15140 SDValue Highs, Lows;
15141 if (VT == MVT::v8i32) {
15142 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15143 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15144 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15145 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15147 const int HighMask[] = {1, 5, 3, 7};
15148 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15149 const int LowMask[] = {0, 4, 2, 6};
15150 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15153 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15154 // unsigned multiply.
15155 if (IsSigned && !Subtarget->hasSSE41()) {
15157 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15158 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15159 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15160 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15161 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15163 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15164 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15167 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getValueType(), Highs, Lows);
15170 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15171 const X86Subtarget *Subtarget) {
15172 MVT VT = Op.getSimpleValueType();
15174 SDValue R = Op.getOperand(0);
15175 SDValue Amt = Op.getOperand(1);
15177 // Optimize shl/srl/sra with constant shift amount.
15178 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15179 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15180 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15182 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15183 (Subtarget->hasInt256() &&
15184 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15185 (Subtarget->hasAVX512() &&
15186 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15187 if (Op.getOpcode() == ISD::SHL)
15188 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15190 if (Op.getOpcode() == ISD::SRL)
15191 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15193 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15194 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15198 if (VT == MVT::v16i8) {
15199 if (Op.getOpcode() == ISD::SHL) {
15200 // Make a large shift.
15201 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15202 MVT::v8i16, R, ShiftAmt,
15204 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15205 // Zero out the rightmost bits.
15206 SmallVector<SDValue, 16> V(16,
15207 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15209 return DAG.getNode(ISD::AND, dl, VT, SHL,
15210 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15212 if (Op.getOpcode() == ISD::SRL) {
15213 // Make a large shift.
15214 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15215 MVT::v8i16, R, ShiftAmt,
15217 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15218 // Zero out the leftmost bits.
15219 SmallVector<SDValue, 16> V(16,
15220 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15222 return DAG.getNode(ISD::AND, dl, VT, SRL,
15223 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15225 if (Op.getOpcode() == ISD::SRA) {
15226 if (ShiftAmt == 7) {
15227 // R s>> 7 === R s< 0
15228 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15229 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15232 // R s>> a === ((R u>> a) ^ m) - m
15233 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15234 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15236 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15237 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15238 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15241 llvm_unreachable("Unknown shift opcode.");
15244 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15245 if (Op.getOpcode() == ISD::SHL) {
15246 // Make a large shift.
15247 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15248 MVT::v16i16, R, ShiftAmt,
15250 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15251 // Zero out the rightmost bits.
15252 SmallVector<SDValue, 32> V(32,
15253 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15255 return DAG.getNode(ISD::AND, dl, VT, SHL,
15256 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15258 if (Op.getOpcode() == ISD::SRL) {
15259 // Make a large shift.
15260 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15261 MVT::v16i16, R, ShiftAmt,
15263 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15264 // Zero out the leftmost bits.
15265 SmallVector<SDValue, 32> V(32,
15266 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15268 return DAG.getNode(ISD::AND, dl, VT, SRL,
15269 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15271 if (Op.getOpcode() == ISD::SRA) {
15272 if (ShiftAmt == 7) {
15273 // R s>> 7 === R s< 0
15274 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15275 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15278 // R s>> a === ((R u>> a) ^ m) - m
15279 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15280 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
15282 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15283 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15284 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15287 llvm_unreachable("Unknown shift opcode.");
15292 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15293 if (!Subtarget->is64Bit() &&
15294 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15295 Amt.getOpcode() == ISD::BITCAST &&
15296 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15297 Amt = Amt.getOperand(0);
15298 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15299 VT.getVectorNumElements();
15300 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15301 uint64_t ShiftAmt = 0;
15302 for (unsigned i = 0; i != Ratio; ++i) {
15303 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15307 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15309 // Check remaining shift amounts.
15310 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15311 uint64_t ShAmt = 0;
15312 for (unsigned j = 0; j != Ratio; ++j) {
15313 ConstantSDNode *C =
15314 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15318 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15320 if (ShAmt != ShiftAmt)
15323 switch (Op.getOpcode()) {
15325 llvm_unreachable("Unknown shift opcode!");
15327 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15330 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15333 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15341 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15342 const X86Subtarget* Subtarget) {
15343 MVT VT = Op.getSimpleValueType();
15345 SDValue R = Op.getOperand(0);
15346 SDValue Amt = Op.getOperand(1);
15348 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15349 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15350 (Subtarget->hasInt256() &&
15351 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15352 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15353 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15355 EVT EltVT = VT.getVectorElementType();
15357 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15358 unsigned NumElts = VT.getVectorNumElements();
15360 for (i = 0; i != NumElts; ++i) {
15361 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
15365 for (j = i; j != NumElts; ++j) {
15366 SDValue Arg = Amt.getOperand(j);
15367 if (Arg.getOpcode() == ISD::UNDEF) continue;
15368 if (Arg != Amt.getOperand(i))
15371 if (i != NumElts && j == NumElts)
15372 BaseShAmt = Amt.getOperand(i);
15374 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15375 Amt = Amt.getOperand(0);
15376 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
15377 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
15378 SDValue InVec = Amt.getOperand(0);
15379 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15380 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15382 for (; i != NumElts; ++i) {
15383 SDValue Arg = InVec.getOperand(i);
15384 if (Arg.getOpcode() == ISD::UNDEF) continue;
15388 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15389 if (ConstantSDNode *C =
15390 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15391 unsigned SplatIdx =
15392 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
15393 if (C->getZExtValue() == SplatIdx)
15394 BaseShAmt = InVec.getOperand(1);
15397 if (!BaseShAmt.getNode())
15398 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
15399 DAG.getIntPtrConstant(0));
15403 if (BaseShAmt.getNode()) {
15404 if (EltVT.bitsGT(MVT::i32))
15405 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
15406 else if (EltVT.bitsLT(MVT::i32))
15407 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15409 switch (Op.getOpcode()) {
15411 llvm_unreachable("Unknown shift opcode!");
15413 switch (VT.SimpleTy) {
15414 default: return SDValue();
15423 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15426 switch (VT.SimpleTy) {
15427 default: return SDValue();
15434 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
15437 switch (VT.SimpleTy) {
15438 default: return SDValue();
15447 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
15453 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15454 if (!Subtarget->is64Bit() &&
15455 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
15456 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
15457 Amt.getOpcode() == ISD::BITCAST &&
15458 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15459 Amt = Amt.getOperand(0);
15460 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15461 VT.getVectorNumElements();
15462 std::vector<SDValue> Vals(Ratio);
15463 for (unsigned i = 0; i != Ratio; ++i)
15464 Vals[i] = Amt.getOperand(i);
15465 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15466 for (unsigned j = 0; j != Ratio; ++j)
15467 if (Vals[j] != Amt.getOperand(i + j))
15470 switch (Op.getOpcode()) {
15472 llvm_unreachable("Unknown shift opcode!");
15474 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
15476 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
15478 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
15485 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
15486 SelectionDAG &DAG) {
15487 MVT VT = Op.getSimpleValueType();
15489 SDValue R = Op.getOperand(0);
15490 SDValue Amt = Op.getOperand(1);
15493 assert(VT.isVector() && "Custom lowering only for vector shifts!");
15494 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
15496 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
15500 V = LowerScalarVariableShift(Op, DAG, Subtarget);
15504 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
15506 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
15507 if (Subtarget->hasInt256()) {
15508 if (Op.getOpcode() == ISD::SRL &&
15509 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15510 VT == MVT::v4i64 || VT == MVT::v8i32))
15512 if (Op.getOpcode() == ISD::SHL &&
15513 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15514 VT == MVT::v4i64 || VT == MVT::v8i32))
15516 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
15520 // If possible, lower this packed shift into a vector multiply instead of
15521 // expanding it into a sequence of scalar shifts.
15522 // Do this only if the vector shift count is a constant build_vector.
15523 if (Op.getOpcode() == ISD::SHL &&
15524 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
15525 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
15526 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15527 SmallVector<SDValue, 8> Elts;
15528 EVT SVT = VT.getScalarType();
15529 unsigned SVTBits = SVT.getSizeInBits();
15530 const APInt &One = APInt(SVTBits, 1);
15531 unsigned NumElems = VT.getVectorNumElements();
15533 for (unsigned i=0; i !=NumElems; ++i) {
15534 SDValue Op = Amt->getOperand(i);
15535 if (Op->getOpcode() == ISD::UNDEF) {
15536 Elts.push_back(Op);
15540 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
15541 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
15542 uint64_t ShAmt = C.getZExtValue();
15543 if (ShAmt >= SVTBits) {
15544 Elts.push_back(DAG.getUNDEF(SVT));
15547 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
15549 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15550 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
15553 // Lower SHL with variable shift amount.
15554 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
15555 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
15557 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
15558 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
15559 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
15560 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
15563 // If possible, lower this shift as a sequence of two shifts by
15564 // constant plus a MOVSS/MOVSD instead of scalarizing it.
15566 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
15568 // Could be rewritten as:
15569 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
15571 // The advantage is that the two shifts from the example would be
15572 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
15573 // the vector shift into four scalar shifts plus four pairs of vector
15575 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
15576 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15577 unsigned TargetOpcode = X86ISD::MOVSS;
15578 bool CanBeSimplified;
15579 // The splat value for the first packed shift (the 'X' from the example).
15580 SDValue Amt1 = Amt->getOperand(0);
15581 // The splat value for the second packed shift (the 'Y' from the example).
15582 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
15583 Amt->getOperand(2);
15585 // See if it is possible to replace this node with a sequence of
15586 // two shifts followed by a MOVSS/MOVSD
15587 if (VT == MVT::v4i32) {
15588 // Check if it is legal to use a MOVSS.
15589 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
15590 Amt2 == Amt->getOperand(3);
15591 if (!CanBeSimplified) {
15592 // Otherwise, check if we can still simplify this node using a MOVSD.
15593 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
15594 Amt->getOperand(2) == Amt->getOperand(3);
15595 TargetOpcode = X86ISD::MOVSD;
15596 Amt2 = Amt->getOperand(2);
15599 // Do similar checks for the case where the machine value type
15601 CanBeSimplified = Amt1 == Amt->getOperand(1);
15602 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
15603 CanBeSimplified = Amt2 == Amt->getOperand(i);
15605 if (!CanBeSimplified) {
15606 TargetOpcode = X86ISD::MOVSD;
15607 CanBeSimplified = true;
15608 Amt2 = Amt->getOperand(4);
15609 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
15610 CanBeSimplified = Amt1 == Amt->getOperand(i);
15611 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
15612 CanBeSimplified = Amt2 == Amt->getOperand(j);
15616 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
15617 isa<ConstantSDNode>(Amt2)) {
15618 // Replace this node with two shifts followed by a MOVSS/MOVSD.
15619 EVT CastVT = MVT::v4i32;
15621 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
15622 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
15624 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
15625 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
15626 if (TargetOpcode == X86ISD::MOVSD)
15627 CastVT = MVT::v2i64;
15628 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
15629 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
15630 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
15632 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15636 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
15637 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
15640 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
15641 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
15643 // Turn 'a' into a mask suitable for VSELECT
15644 SDValue VSelM = DAG.getConstant(0x80, VT);
15645 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15646 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15648 SDValue CM1 = DAG.getConstant(0x0f, VT);
15649 SDValue CM2 = DAG.getConstant(0x3f, VT);
15651 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
15652 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
15653 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
15654 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15655 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15658 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15659 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15660 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15662 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
15663 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
15664 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
15665 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15666 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15669 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15670 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15671 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15673 // return VSELECT(r, r+r, a);
15674 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
15675 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
15679 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
15680 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
15681 // solution better.
15682 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
15683 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
15685 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
15686 R = DAG.getNode(ExtOpc, dl, NewVT, R);
15687 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
15688 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15689 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
15692 // Decompose 256-bit shifts into smaller 128-bit shifts.
15693 if (VT.is256BitVector()) {
15694 unsigned NumElems = VT.getVectorNumElements();
15695 MVT EltVT = VT.getVectorElementType();
15696 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15698 // Extract the two vectors
15699 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
15700 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
15702 // Recreate the shift amount vectors
15703 SDValue Amt1, Amt2;
15704 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15705 // Constant shift amount
15706 SmallVector<SDValue, 4> Amt1Csts;
15707 SmallVector<SDValue, 4> Amt2Csts;
15708 for (unsigned i = 0; i != NumElems/2; ++i)
15709 Amt1Csts.push_back(Amt->getOperand(i));
15710 for (unsigned i = NumElems/2; i != NumElems; ++i)
15711 Amt2Csts.push_back(Amt->getOperand(i));
15713 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
15714 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
15716 // Variable shift amount
15717 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
15718 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
15721 // Issue new vector shifts for the smaller types
15722 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
15723 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
15725 // Concatenate the result back
15726 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
15732 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
15733 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
15734 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
15735 // looks for this combo and may remove the "setcc" instruction if the "setcc"
15736 // has only one use.
15737 SDNode *N = Op.getNode();
15738 SDValue LHS = N->getOperand(0);
15739 SDValue RHS = N->getOperand(1);
15740 unsigned BaseOp = 0;
15743 switch (Op.getOpcode()) {
15744 default: llvm_unreachable("Unknown ovf instruction!");
15746 // A subtract of one will be selected as a INC. Note that INC doesn't
15747 // set CF, so we can't do this for UADDO.
15748 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15750 BaseOp = X86ISD::INC;
15751 Cond = X86::COND_O;
15754 BaseOp = X86ISD::ADD;
15755 Cond = X86::COND_O;
15758 BaseOp = X86ISD::ADD;
15759 Cond = X86::COND_B;
15762 // A subtract of one will be selected as a DEC. Note that DEC doesn't
15763 // set CF, so we can't do this for USUBO.
15764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15766 BaseOp = X86ISD::DEC;
15767 Cond = X86::COND_O;
15770 BaseOp = X86ISD::SUB;
15771 Cond = X86::COND_O;
15774 BaseOp = X86ISD::SUB;
15775 Cond = X86::COND_B;
15778 BaseOp = X86ISD::SMUL;
15779 Cond = X86::COND_O;
15781 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
15782 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
15784 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
15787 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15788 DAG.getConstant(X86::COND_O, MVT::i32),
15789 SDValue(Sum.getNode(), 2));
15791 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15795 // Also sets EFLAGS.
15796 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
15797 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
15800 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
15801 DAG.getConstant(Cond, MVT::i32),
15802 SDValue(Sum.getNode(), 1));
15804 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15807 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
15808 SelectionDAG &DAG) const {
15810 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
15811 MVT VT = Op.getSimpleValueType();
15813 if (!Subtarget->hasSSE2() || !VT.isVector())
15816 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
15817 ExtraVT.getScalarType().getSizeInBits();
15819 switch (VT.SimpleTy) {
15820 default: return SDValue();
15823 if (!Subtarget->hasFp256())
15825 if (!Subtarget->hasInt256()) {
15826 // needs to be split
15827 unsigned NumElems = VT.getVectorNumElements();
15829 // Extract the LHS vectors
15830 SDValue LHS = Op.getOperand(0);
15831 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15832 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15834 MVT EltVT = VT.getVectorElementType();
15835 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15837 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15838 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
15839 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
15841 SDValue Extra = DAG.getValueType(ExtraVT);
15843 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
15844 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
15846 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
15851 SDValue Op0 = Op.getOperand(0);
15852 SDValue Op00 = Op0.getOperand(0);
15854 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
15855 if (Op0.getOpcode() == ISD::BITCAST &&
15856 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
15857 // (sext (vzext x)) -> (vsext x)
15858 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
15859 if (Tmp1.getNode()) {
15860 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15861 // This folding is only valid when the in-reg type is a vector of i8,
15863 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
15864 ExtraEltVT == MVT::i32) {
15865 SDValue Tmp1Op0 = Tmp1.getOperand(0);
15866 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
15867 "This optimization is invalid without a VZEXT.");
15868 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
15874 // If the above didn't work, then just use Shift-Left + Shift-Right.
15875 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
15877 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
15883 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
15884 SelectionDAG &DAG) {
15886 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
15887 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
15888 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
15889 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
15891 // The only fence that needs an instruction is a sequentially-consistent
15892 // cross-thread fence.
15893 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
15894 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
15895 // no-sse2). There isn't any reason to disable it if the target processor
15897 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
15898 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
15900 SDValue Chain = Op.getOperand(0);
15901 SDValue Zero = DAG.getConstant(0, MVT::i32);
15903 DAG.getRegister(X86::ESP, MVT::i32), // Base
15904 DAG.getTargetConstant(1, MVT::i8), // Scale
15905 DAG.getRegister(0, MVT::i32), // Index
15906 DAG.getTargetConstant(0, MVT::i32), // Disp
15907 DAG.getRegister(0, MVT::i32), // Segment.
15911 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
15912 return SDValue(Res, 0);
15915 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
15916 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
15919 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
15920 SelectionDAG &DAG) {
15921 MVT T = Op.getSimpleValueType();
15925 switch(T.SimpleTy) {
15926 default: llvm_unreachable("Invalid value type!");
15927 case MVT::i8: Reg = X86::AL; size = 1; break;
15928 case MVT::i16: Reg = X86::AX; size = 2; break;
15929 case MVT::i32: Reg = X86::EAX; size = 4; break;
15931 assert(Subtarget->is64Bit() && "Node not type legal!");
15932 Reg = X86::RAX; size = 8;
15935 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
15936 Op.getOperand(2), SDValue());
15937 SDValue Ops[] = { cpIn.getValue(0),
15940 DAG.getTargetConstant(size, MVT::i8),
15941 cpIn.getValue(1) };
15942 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15943 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
15944 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
15948 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
15949 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
15950 MVT::i32, cpOut.getValue(2));
15951 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
15952 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
15954 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
15955 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
15956 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
15960 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
15961 SelectionDAG &DAG) {
15962 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
15963 MVT DstVT = Op.getSimpleValueType();
15965 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
15966 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
15967 if (DstVT != MVT::f64)
15968 // This conversion needs to be expanded.
15971 SDValue InVec = Op->getOperand(0);
15973 unsigned NumElts = SrcVT.getVectorNumElements();
15974 EVT SVT = SrcVT.getVectorElementType();
15976 // Widen the vector in input in the case of MVT::v2i32.
15977 // Example: from MVT::v2i32 to MVT::v4i32.
15978 SmallVector<SDValue, 16> Elts;
15979 for (unsigned i = 0, e = NumElts; i != e; ++i)
15980 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
15981 DAG.getIntPtrConstant(i)));
15983 // Explicitly mark the extra elements as Undef.
15984 SDValue Undef = DAG.getUNDEF(SVT);
15985 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
15986 Elts.push_back(Undef);
15988 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
15989 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
15990 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
15991 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
15992 DAG.getIntPtrConstant(0));
15995 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
15996 Subtarget->hasMMX() && "Unexpected custom BITCAST");
15997 assert((DstVT == MVT::i64 ||
15998 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
15999 "Unexpected custom BITCAST");
16000 // i64 <=> MMX conversions are Legal.
16001 if (SrcVT==MVT::i64 && DstVT.isVector())
16003 if (DstVT==MVT::i64 && SrcVT.isVector())
16005 // MMX <=> MMX conversions are Legal.
16006 if (SrcVT.isVector() && DstVT.isVector())
16008 // All other conversions need to be expanded.
16012 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16013 SDNode *Node = Op.getNode();
16015 EVT T = Node->getValueType(0);
16016 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16017 DAG.getConstant(0, T), Node->getOperand(2));
16018 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16019 cast<AtomicSDNode>(Node)->getMemoryVT(),
16020 Node->getOperand(0),
16021 Node->getOperand(1), negOp,
16022 cast<AtomicSDNode>(Node)->getMemOperand(),
16023 cast<AtomicSDNode>(Node)->getOrdering(),
16024 cast<AtomicSDNode>(Node)->getSynchScope());
16027 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16028 SDNode *Node = Op.getNode();
16030 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16032 // Convert seq_cst store -> xchg
16033 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16034 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16035 // (The only way to get a 16-byte store is cmpxchg16b)
16036 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16037 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16038 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16039 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16040 cast<AtomicSDNode>(Node)->getMemoryVT(),
16041 Node->getOperand(0),
16042 Node->getOperand(1), Node->getOperand(2),
16043 cast<AtomicSDNode>(Node)->getMemOperand(),
16044 cast<AtomicSDNode>(Node)->getOrdering(),
16045 cast<AtomicSDNode>(Node)->getSynchScope());
16046 return Swap.getValue(1);
16048 // Other atomic stores have a simple pattern.
16052 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16053 EVT VT = Op.getNode()->getSimpleValueType(0);
16055 // Let legalize expand this if it isn't a legal type yet.
16056 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16059 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16062 bool ExtraOp = false;
16063 switch (Op.getOpcode()) {
16064 default: llvm_unreachable("Invalid code");
16065 case ISD::ADDC: Opc = X86ISD::ADD; break;
16066 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16067 case ISD::SUBC: Opc = X86ISD::SUB; break;
16068 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16072 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16074 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16075 Op.getOperand(1), Op.getOperand(2));
16078 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16079 SelectionDAG &DAG) {
16080 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16082 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16083 // which returns the values as { float, float } (in XMM0) or
16084 // { double, double } (which is returned in XMM0, XMM1).
16086 SDValue Arg = Op.getOperand(0);
16087 EVT ArgVT = Arg.getValueType();
16088 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16090 TargetLowering::ArgListTy Args;
16091 TargetLowering::ArgListEntry Entry;
16095 Entry.isSExt = false;
16096 Entry.isZExt = false;
16097 Args.push_back(Entry);
16099 bool isF64 = ArgVT == MVT::f64;
16100 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16101 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16102 // the results are returned via SRet in memory.
16103 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16104 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16105 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16107 Type *RetTy = isF64
16108 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16109 : (Type*)VectorType::get(ArgTy, 4);
16111 TargetLowering::CallLoweringInfo CLI(DAG);
16112 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16113 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16115 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16118 // Returned in xmm0 and xmm1.
16119 return CallResult.first;
16121 // Returned in bits 0:31 and 32:64 xmm0.
16122 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16123 CallResult.first, DAG.getIntPtrConstant(0));
16124 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16125 CallResult.first, DAG.getIntPtrConstant(1));
16126 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16127 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16130 /// LowerOperation - Provide custom lowering hooks for some operations.
16132 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16133 switch (Op.getOpcode()) {
16134 default: llvm_unreachable("Should not custom lower this!");
16135 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16136 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16137 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16138 return LowerCMP_SWAP(Op, Subtarget, DAG);
16139 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16140 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16141 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16142 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16143 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16144 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16145 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16146 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16147 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16148 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16149 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16150 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16151 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16152 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16153 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16154 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16155 case ISD::SHL_PARTS:
16156 case ISD::SRA_PARTS:
16157 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16158 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16159 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16160 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16161 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16162 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16163 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16164 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16165 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16166 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16167 case ISD::FABS: return LowerFABS(Op, DAG);
16168 case ISD::FNEG: return LowerFNEG(Op, DAG);
16169 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16170 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16171 case ISD::SETCC: return LowerSETCC(Op, DAG);
16172 case ISD::SELECT: return LowerSELECT(Op, DAG);
16173 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16174 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16175 case ISD::VASTART: return LowerVASTART(Op, DAG);
16176 case ISD::VAARG: return LowerVAARG(Op, DAG);
16177 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16178 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16179 case ISD::INTRINSIC_VOID:
16180 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16181 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16182 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16183 case ISD::FRAME_TO_ARGS_OFFSET:
16184 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16185 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16186 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16187 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16188 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16189 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16190 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16191 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16192 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16193 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16194 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16195 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16196 case ISD::UMUL_LOHI:
16197 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16200 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16206 case ISD::UMULO: return LowerXALUO(Op, DAG);
16207 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16208 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16212 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16213 case ISD::ADD: return LowerADD(Op, DAG);
16214 case ISD::SUB: return LowerSUB(Op, DAG);
16215 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16219 static void ReplaceATOMIC_LOAD(SDNode *Node,
16220 SmallVectorImpl<SDValue> &Results,
16221 SelectionDAG &DAG) {
16223 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16225 // Convert wide load -> cmpxchg8b/cmpxchg16b
16226 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16227 // (The only way to get a 16-byte load is cmpxchg16b)
16228 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16229 SDValue Zero = DAG.getConstant(0, VT);
16230 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16232 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16233 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16234 cast<AtomicSDNode>(Node)->getMemOperand(),
16235 cast<AtomicSDNode>(Node)->getOrdering(),
16236 cast<AtomicSDNode>(Node)->getOrdering(),
16237 cast<AtomicSDNode>(Node)->getSynchScope());
16238 Results.push_back(Swap.getValue(0));
16239 Results.push_back(Swap.getValue(2));
16242 /// ReplaceNodeResults - Replace a node with an illegal result type
16243 /// with a new node built out of custom code.
16244 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16245 SmallVectorImpl<SDValue>&Results,
16246 SelectionDAG &DAG) const {
16248 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16249 switch (N->getOpcode()) {
16251 llvm_unreachable("Do not know how to custom type legalize this operation!");
16252 case ISD::SIGN_EXTEND_INREG:
16257 // We don't want to expand or promote these.
16264 case ISD::UDIVREM: {
16265 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16266 Results.push_back(V);
16269 case ISD::FP_TO_SINT:
16270 case ISD::FP_TO_UINT: {
16271 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16273 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16276 std::pair<SDValue,SDValue> Vals =
16277 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16278 SDValue FIST = Vals.first, StackSlot = Vals.second;
16279 if (FIST.getNode()) {
16280 EVT VT = N->getValueType(0);
16281 // Return a load from the stack slot.
16282 if (StackSlot.getNode())
16283 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16284 MachinePointerInfo(),
16285 false, false, false, 0));
16287 Results.push_back(FIST);
16291 case ISD::UINT_TO_FP: {
16292 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16293 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16294 N->getValueType(0) != MVT::v2f32)
16296 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16298 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16300 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16301 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16302 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16303 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16304 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16305 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16308 case ISD::FP_ROUND: {
16309 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16311 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16312 Results.push_back(V);
16315 case ISD::INTRINSIC_W_CHAIN: {
16316 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16318 default : llvm_unreachable("Do not know how to custom type "
16319 "legalize this intrinsic operation!");
16320 case Intrinsic::x86_rdtsc:
16321 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16323 case Intrinsic::x86_rdtscp:
16324 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16326 case Intrinsic::x86_rdpmc:
16327 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16330 case ISD::READCYCLECOUNTER: {
16331 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16334 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16335 EVT T = N->getValueType(0);
16336 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16337 bool Regs64bit = T == MVT::i128;
16338 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16339 SDValue cpInL, cpInH;
16340 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16341 DAG.getConstant(0, HalfT));
16342 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16343 DAG.getConstant(1, HalfT));
16344 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16345 Regs64bit ? X86::RAX : X86::EAX,
16347 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16348 Regs64bit ? X86::RDX : X86::EDX,
16349 cpInH, cpInL.getValue(1));
16350 SDValue swapInL, swapInH;
16351 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16352 DAG.getConstant(0, HalfT));
16353 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16354 DAG.getConstant(1, HalfT));
16355 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16356 Regs64bit ? X86::RBX : X86::EBX,
16357 swapInL, cpInH.getValue(1));
16358 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16359 Regs64bit ? X86::RCX : X86::ECX,
16360 swapInH, swapInL.getValue(1));
16361 SDValue Ops[] = { swapInH.getValue(0),
16363 swapInH.getValue(1) };
16364 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16365 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16366 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16367 X86ISD::LCMPXCHG8_DAG;
16368 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16369 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16370 Regs64bit ? X86::RAX : X86::EAX,
16371 HalfT, Result.getValue(1));
16372 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16373 Regs64bit ? X86::RDX : X86::EDX,
16374 HalfT, cpOutL.getValue(2));
16375 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16377 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16378 MVT::i32, cpOutH.getValue(2));
16380 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16381 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16382 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
16384 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
16385 Results.push_back(Success);
16386 Results.push_back(EFLAGS.getValue(1));
16389 case ISD::ATOMIC_SWAP:
16390 case ISD::ATOMIC_LOAD_ADD:
16391 case ISD::ATOMIC_LOAD_SUB:
16392 case ISD::ATOMIC_LOAD_AND:
16393 case ISD::ATOMIC_LOAD_OR:
16394 case ISD::ATOMIC_LOAD_XOR:
16395 case ISD::ATOMIC_LOAD_NAND:
16396 case ISD::ATOMIC_LOAD_MIN:
16397 case ISD::ATOMIC_LOAD_MAX:
16398 case ISD::ATOMIC_LOAD_UMIN:
16399 case ISD::ATOMIC_LOAD_UMAX:
16400 // Delegate to generic TypeLegalization. Situations we can really handle
16401 // should have already been dealt with by X86AtomicExpand.cpp.
16403 case ISD::ATOMIC_LOAD: {
16404 ReplaceATOMIC_LOAD(N, Results, DAG);
16407 case ISD::BITCAST: {
16408 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16409 EVT DstVT = N->getValueType(0);
16410 EVT SrcVT = N->getOperand(0)->getValueType(0);
16412 if (SrcVT != MVT::f64 ||
16413 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
16416 unsigned NumElts = DstVT.getVectorNumElements();
16417 EVT SVT = DstVT.getVectorElementType();
16418 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16419 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
16420 MVT::v2f64, N->getOperand(0));
16421 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
16423 if (ExperimentalVectorWideningLegalization) {
16424 // If we are legalizing vectors by widening, we already have the desired
16425 // legal vector type, just return it.
16426 Results.push_back(ToVecInt);
16430 SmallVector<SDValue, 8> Elts;
16431 for (unsigned i = 0, e = NumElts; i != e; ++i)
16432 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
16433 ToVecInt, DAG.getIntPtrConstant(i)));
16435 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
16440 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
16442 default: return nullptr;
16443 case X86ISD::BSF: return "X86ISD::BSF";
16444 case X86ISD::BSR: return "X86ISD::BSR";
16445 case X86ISD::SHLD: return "X86ISD::SHLD";
16446 case X86ISD::SHRD: return "X86ISD::SHRD";
16447 case X86ISD::FAND: return "X86ISD::FAND";
16448 case X86ISD::FANDN: return "X86ISD::FANDN";
16449 case X86ISD::FOR: return "X86ISD::FOR";
16450 case X86ISD::FXOR: return "X86ISD::FXOR";
16451 case X86ISD::FSRL: return "X86ISD::FSRL";
16452 case X86ISD::FILD: return "X86ISD::FILD";
16453 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
16454 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
16455 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
16456 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
16457 case X86ISD::FLD: return "X86ISD::FLD";
16458 case X86ISD::FST: return "X86ISD::FST";
16459 case X86ISD::CALL: return "X86ISD::CALL";
16460 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
16461 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
16462 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
16463 case X86ISD::BT: return "X86ISD::BT";
16464 case X86ISD::CMP: return "X86ISD::CMP";
16465 case X86ISD::COMI: return "X86ISD::COMI";
16466 case X86ISD::UCOMI: return "X86ISD::UCOMI";
16467 case X86ISD::CMPM: return "X86ISD::CMPM";
16468 case X86ISD::CMPMU: return "X86ISD::CMPMU";
16469 case X86ISD::SETCC: return "X86ISD::SETCC";
16470 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
16471 case X86ISD::FSETCC: return "X86ISD::FSETCC";
16472 case X86ISD::CMOV: return "X86ISD::CMOV";
16473 case X86ISD::BRCOND: return "X86ISD::BRCOND";
16474 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
16475 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
16476 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
16477 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
16478 case X86ISD::Wrapper: return "X86ISD::Wrapper";
16479 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
16480 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
16481 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
16482 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
16483 case X86ISD::PINSRB: return "X86ISD::PINSRB";
16484 case X86ISD::PINSRW: return "X86ISD::PINSRW";
16485 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
16486 case X86ISD::ANDNP: return "X86ISD::ANDNP";
16487 case X86ISD::PSIGN: return "X86ISD::PSIGN";
16488 case X86ISD::BLENDV: return "X86ISD::BLENDV";
16489 case X86ISD::BLENDI: return "X86ISD::BLENDI";
16490 case X86ISD::SUBUS: return "X86ISD::SUBUS";
16491 case X86ISD::HADD: return "X86ISD::HADD";
16492 case X86ISD::HSUB: return "X86ISD::HSUB";
16493 case X86ISD::FHADD: return "X86ISD::FHADD";
16494 case X86ISD::FHSUB: return "X86ISD::FHSUB";
16495 case X86ISD::UMAX: return "X86ISD::UMAX";
16496 case X86ISD::UMIN: return "X86ISD::UMIN";
16497 case X86ISD::SMAX: return "X86ISD::SMAX";
16498 case X86ISD::SMIN: return "X86ISD::SMIN";
16499 case X86ISD::FMAX: return "X86ISD::FMAX";
16500 case X86ISD::FMIN: return "X86ISD::FMIN";
16501 case X86ISD::FMAXC: return "X86ISD::FMAXC";
16502 case X86ISD::FMINC: return "X86ISD::FMINC";
16503 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
16504 case X86ISD::FRCP: return "X86ISD::FRCP";
16505 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
16506 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
16507 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
16508 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
16509 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
16510 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
16511 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
16512 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
16513 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
16514 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
16515 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
16516 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
16517 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
16518 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
16519 case X86ISD::VZEXT: return "X86ISD::VZEXT";
16520 case X86ISD::VSEXT: return "X86ISD::VSEXT";
16521 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
16522 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
16523 case X86ISD::VINSERT: return "X86ISD::VINSERT";
16524 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
16525 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
16526 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
16527 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
16528 case X86ISD::VSHL: return "X86ISD::VSHL";
16529 case X86ISD::VSRL: return "X86ISD::VSRL";
16530 case X86ISD::VSRA: return "X86ISD::VSRA";
16531 case X86ISD::VSHLI: return "X86ISD::VSHLI";
16532 case X86ISD::VSRLI: return "X86ISD::VSRLI";
16533 case X86ISD::VSRAI: return "X86ISD::VSRAI";
16534 case X86ISD::CMPP: return "X86ISD::CMPP";
16535 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
16536 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
16537 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
16538 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
16539 case X86ISD::ADD: return "X86ISD::ADD";
16540 case X86ISD::SUB: return "X86ISD::SUB";
16541 case X86ISD::ADC: return "X86ISD::ADC";
16542 case X86ISD::SBB: return "X86ISD::SBB";
16543 case X86ISD::SMUL: return "X86ISD::SMUL";
16544 case X86ISD::UMUL: return "X86ISD::UMUL";
16545 case X86ISD::INC: return "X86ISD::INC";
16546 case X86ISD::DEC: return "X86ISD::DEC";
16547 case X86ISD::OR: return "X86ISD::OR";
16548 case X86ISD::XOR: return "X86ISD::XOR";
16549 case X86ISD::AND: return "X86ISD::AND";
16550 case X86ISD::BEXTR: return "X86ISD::BEXTR";
16551 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
16552 case X86ISD::PTEST: return "X86ISD::PTEST";
16553 case X86ISD::TESTP: return "X86ISD::TESTP";
16554 case X86ISD::TESTM: return "X86ISD::TESTM";
16555 case X86ISD::TESTNM: return "X86ISD::TESTNM";
16556 case X86ISD::KORTEST: return "X86ISD::KORTEST";
16557 case X86ISD::PACKSS: return "X86ISD::PACKSS";
16558 case X86ISD::PACKUS: return "X86ISD::PACKUS";
16559 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
16560 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
16561 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
16562 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
16563 case X86ISD::SHUFP: return "X86ISD::SHUFP";
16564 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
16565 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
16566 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
16567 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
16568 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
16569 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
16570 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
16571 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
16572 case X86ISD::MOVSD: return "X86ISD::MOVSD";
16573 case X86ISD::MOVSS: return "X86ISD::MOVSS";
16574 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
16575 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
16576 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
16577 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
16578 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
16579 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
16580 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
16581 case X86ISD::VPERMV: return "X86ISD::VPERMV";
16582 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
16583 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
16584 case X86ISD::VPERMI: return "X86ISD::VPERMI";
16585 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
16586 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
16587 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
16588 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
16589 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
16590 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
16591 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
16592 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
16593 case X86ISD::SAHF: return "X86ISD::SAHF";
16594 case X86ISD::RDRAND: return "X86ISD::RDRAND";
16595 case X86ISD::RDSEED: return "X86ISD::RDSEED";
16596 case X86ISD::FMADD: return "X86ISD::FMADD";
16597 case X86ISD::FMSUB: return "X86ISD::FMSUB";
16598 case X86ISD::FNMADD: return "X86ISD::FNMADD";
16599 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
16600 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
16601 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
16602 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
16603 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
16604 case X86ISD::XTEST: return "X86ISD::XTEST";
16608 // isLegalAddressingMode - Return true if the addressing mode represented
16609 // by AM is legal for this target, for a load/store of the specified type.
16610 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
16612 // X86 supports extremely general addressing modes.
16613 CodeModel::Model M = getTargetMachine().getCodeModel();
16614 Reloc::Model R = getTargetMachine().getRelocationModel();
16616 // X86 allows a sign-extended 32-bit immediate field as a displacement.
16617 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
16622 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
16624 // If a reference to this global requires an extra load, we can't fold it.
16625 if (isGlobalStubReference(GVFlags))
16628 // If BaseGV requires a register for the PIC base, we cannot also have a
16629 // BaseReg specified.
16630 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
16633 // If lower 4G is not available, then we must use rip-relative addressing.
16634 if ((M != CodeModel::Small || R != Reloc::Static) &&
16635 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
16639 switch (AM.Scale) {
16645 // These scales always work.
16650 // These scales are formed with basereg+scalereg. Only accept if there is
16655 default: // Other stuff never works.
16662 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
16663 unsigned Bits = Ty->getScalarSizeInBits();
16665 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
16666 // particularly cheaper than those without.
16670 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
16671 // variable shifts just as cheap as scalar ones.
16672 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
16675 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
16676 // fully general vector.
16680 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
16681 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16683 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
16684 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
16685 return NumBits1 > NumBits2;
16688 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
16689 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16692 if (!isTypeLegal(EVT::getEVT(Ty1)))
16695 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
16697 // Assuming the caller doesn't have a zeroext or signext return parameter,
16698 // truncation all the way down to i1 is valid.
16702 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
16703 return isInt<32>(Imm);
16706 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
16707 // Can also use sub to handle negated immediates.
16708 return isInt<32>(Imm);
16711 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
16712 if (!VT1.isInteger() || !VT2.isInteger())
16714 unsigned NumBits1 = VT1.getSizeInBits();
16715 unsigned NumBits2 = VT2.getSizeInBits();
16716 return NumBits1 > NumBits2;
16719 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
16720 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16721 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
16724 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
16725 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16726 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
16729 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
16730 EVT VT1 = Val.getValueType();
16731 if (isZExtFree(VT1, VT2))
16734 if (Val.getOpcode() != ISD::LOAD)
16737 if (!VT1.isSimple() || !VT1.isInteger() ||
16738 !VT2.isSimple() || !VT2.isInteger())
16741 switch (VT1.getSimpleVT().SimpleTy) {
16746 // X86 has 8, 16, and 32-bit zero-extending loads.
16754 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
16755 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
16758 VT = VT.getScalarType();
16760 if (!VT.isSimple())
16763 switch (VT.getSimpleVT().SimpleTy) {
16774 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
16775 // i16 instructions are longer (0x66 prefix) and potentially slower.
16776 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
16779 /// isShuffleMaskLegal - Targets can use this to indicate that they only
16780 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
16781 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
16782 /// are assumed to be legal.
16784 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
16786 if (!VT.isSimple())
16789 MVT SVT = VT.getSimpleVT();
16791 // Very little shuffling can be done for 64-bit vectors right now.
16792 if (VT.getSizeInBits() == 64)
16795 // If this is a single-input shuffle with no 128 bit lane crossings we can
16796 // lower it into pshufb.
16797 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
16798 (SVT.is256BitVector() && Subtarget->hasInt256())) {
16799 bool isLegal = true;
16800 for (unsigned I = 0, E = M.size(); I != E; ++I) {
16801 if (M[I] >= (int)SVT.getVectorNumElements() ||
16802 ShuffleCrosses128bitLane(SVT, I, M[I])) {
16811 // FIXME: blends, shifts.
16812 return (SVT.getVectorNumElements() == 2 ||
16813 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
16814 isMOVLMask(M, SVT) ||
16815 isSHUFPMask(M, SVT) ||
16816 isPSHUFDMask(M, SVT) ||
16817 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
16818 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
16819 isPALIGNRMask(M, SVT, Subtarget) ||
16820 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
16821 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
16822 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16823 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16824 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
16828 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
16830 if (!VT.isSimple())
16833 MVT SVT = VT.getSimpleVT();
16834 unsigned NumElts = SVT.getVectorNumElements();
16835 // FIXME: This collection of masks seems suspect.
16838 if (NumElts == 4 && SVT.is128BitVector()) {
16839 return (isMOVLMask(Mask, SVT) ||
16840 isCommutedMOVLMask(Mask, SVT, true) ||
16841 isSHUFPMask(Mask, SVT) ||
16842 isSHUFPMask(Mask, SVT, /* Commuted */ true));
16847 //===----------------------------------------------------------------------===//
16848 // X86 Scheduler Hooks
16849 //===----------------------------------------------------------------------===//
16851 /// Utility function to emit xbegin specifying the start of an RTM region.
16852 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
16853 const TargetInstrInfo *TII) {
16854 DebugLoc DL = MI->getDebugLoc();
16856 const BasicBlock *BB = MBB->getBasicBlock();
16857 MachineFunction::iterator I = MBB;
16860 // For the v = xbegin(), we generate
16871 MachineBasicBlock *thisMBB = MBB;
16872 MachineFunction *MF = MBB->getParent();
16873 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
16874 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
16875 MF->insert(I, mainMBB);
16876 MF->insert(I, sinkMBB);
16878 // Transfer the remainder of BB and its successor edges to sinkMBB.
16879 sinkMBB->splice(sinkMBB->begin(), MBB,
16880 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16881 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
16885 // # fallthrough to mainMBB
16886 // # abortion to sinkMBB
16887 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
16888 thisMBB->addSuccessor(mainMBB);
16889 thisMBB->addSuccessor(sinkMBB);
16893 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
16894 mainMBB->addSuccessor(sinkMBB);
16897 // EAX is live into the sinkMBB
16898 sinkMBB->addLiveIn(X86::EAX);
16899 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16900 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16903 MI->eraseFromParent();
16907 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
16908 // or XMM0_V32I8 in AVX all of this code can be replaced with that
16909 // in the .td file.
16910 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
16911 const TargetInstrInfo *TII) {
16913 switch (MI->getOpcode()) {
16914 default: llvm_unreachable("illegal opcode!");
16915 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
16916 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
16917 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
16918 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
16919 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
16920 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
16921 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
16922 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
16925 DebugLoc dl = MI->getDebugLoc();
16926 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
16928 unsigned NumArgs = MI->getNumOperands();
16929 for (unsigned i = 1; i < NumArgs; ++i) {
16930 MachineOperand &Op = MI->getOperand(i);
16931 if (!(Op.isReg() && Op.isImplicit()))
16932 MIB.addOperand(Op);
16934 if (MI->hasOneMemOperand())
16935 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
16937 BuildMI(*BB, MI, dl,
16938 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16939 .addReg(X86::XMM0);
16941 MI->eraseFromParent();
16945 // FIXME: Custom handling because TableGen doesn't support multiple implicit
16946 // defs in an instruction pattern
16947 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
16948 const TargetInstrInfo *TII) {
16950 switch (MI->getOpcode()) {
16951 default: llvm_unreachable("illegal opcode!");
16952 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
16953 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
16954 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
16955 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
16956 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
16957 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
16958 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
16959 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
16962 DebugLoc dl = MI->getDebugLoc();
16963 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
16965 unsigned NumArgs = MI->getNumOperands(); // remove the results
16966 for (unsigned i = 1; i < NumArgs; ++i) {
16967 MachineOperand &Op = MI->getOperand(i);
16968 if (!(Op.isReg() && Op.isImplicit()))
16969 MIB.addOperand(Op);
16971 if (MI->hasOneMemOperand())
16972 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
16974 BuildMI(*BB, MI, dl,
16975 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16978 MI->eraseFromParent();
16982 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
16983 const TargetInstrInfo *TII,
16984 const X86Subtarget* Subtarget) {
16985 DebugLoc dl = MI->getDebugLoc();
16987 // Address into RAX/EAX, other two args into ECX, EDX.
16988 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
16989 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
16990 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
16991 for (int i = 0; i < X86::AddrNumOperands; ++i)
16992 MIB.addOperand(MI->getOperand(i));
16994 unsigned ValOps = X86::AddrNumOperands;
16995 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
16996 .addReg(MI->getOperand(ValOps).getReg());
16997 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
16998 .addReg(MI->getOperand(ValOps+1).getReg());
17000 // The instruction doesn't actually take any operands though.
17001 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17003 MI->eraseFromParent(); // The pseudo is gone now.
17007 MachineBasicBlock *
17008 X86TargetLowering::EmitVAARG64WithCustomInserter(
17010 MachineBasicBlock *MBB) const {
17011 // Emit va_arg instruction on X86-64.
17013 // Operands to this pseudo-instruction:
17014 // 0 ) Output : destination address (reg)
17015 // 1-5) Input : va_list address (addr, i64mem)
17016 // 6 ) ArgSize : Size (in bytes) of vararg type
17017 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17018 // 8 ) Align : Alignment of type
17019 // 9 ) EFLAGS (implicit-def)
17021 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17022 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17024 unsigned DestReg = MI->getOperand(0).getReg();
17025 MachineOperand &Base = MI->getOperand(1);
17026 MachineOperand &Scale = MI->getOperand(2);
17027 MachineOperand &Index = MI->getOperand(3);
17028 MachineOperand &Disp = MI->getOperand(4);
17029 MachineOperand &Segment = MI->getOperand(5);
17030 unsigned ArgSize = MI->getOperand(6).getImm();
17031 unsigned ArgMode = MI->getOperand(7).getImm();
17032 unsigned Align = MI->getOperand(8).getImm();
17034 // Memory Reference
17035 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17036 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17037 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17039 // Machine Information
17040 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17041 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17042 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17043 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17044 DebugLoc DL = MI->getDebugLoc();
17046 // struct va_list {
17049 // i64 overflow_area (address)
17050 // i64 reg_save_area (address)
17052 // sizeof(va_list) = 24
17053 // alignment(va_list) = 8
17055 unsigned TotalNumIntRegs = 6;
17056 unsigned TotalNumXMMRegs = 8;
17057 bool UseGPOffset = (ArgMode == 1);
17058 bool UseFPOffset = (ArgMode == 2);
17059 unsigned MaxOffset = TotalNumIntRegs * 8 +
17060 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17062 /* Align ArgSize to a multiple of 8 */
17063 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17064 bool NeedsAlign = (Align > 8);
17066 MachineBasicBlock *thisMBB = MBB;
17067 MachineBasicBlock *overflowMBB;
17068 MachineBasicBlock *offsetMBB;
17069 MachineBasicBlock *endMBB;
17071 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17072 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17073 unsigned OffsetReg = 0;
17075 if (!UseGPOffset && !UseFPOffset) {
17076 // If we only pull from the overflow region, we don't create a branch.
17077 // We don't need to alter control flow.
17078 OffsetDestReg = 0; // unused
17079 OverflowDestReg = DestReg;
17081 offsetMBB = nullptr;
17082 overflowMBB = thisMBB;
17085 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17086 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17087 // If not, pull from overflow_area. (branch to overflowMBB)
17092 // offsetMBB overflowMBB
17097 // Registers for the PHI in endMBB
17098 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17099 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17101 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17102 MachineFunction *MF = MBB->getParent();
17103 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17104 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17105 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17107 MachineFunction::iterator MBBIter = MBB;
17110 // Insert the new basic blocks
17111 MF->insert(MBBIter, offsetMBB);
17112 MF->insert(MBBIter, overflowMBB);
17113 MF->insert(MBBIter, endMBB);
17115 // Transfer the remainder of MBB and its successor edges to endMBB.
17116 endMBB->splice(endMBB->begin(), thisMBB,
17117 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17118 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17120 // Make offsetMBB and overflowMBB successors of thisMBB
17121 thisMBB->addSuccessor(offsetMBB);
17122 thisMBB->addSuccessor(overflowMBB);
17124 // endMBB is a successor of both offsetMBB and overflowMBB
17125 offsetMBB->addSuccessor(endMBB);
17126 overflowMBB->addSuccessor(endMBB);
17128 // Load the offset value into a register
17129 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17130 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17134 .addDisp(Disp, UseFPOffset ? 4 : 0)
17135 .addOperand(Segment)
17136 .setMemRefs(MMOBegin, MMOEnd);
17138 // Check if there is enough room left to pull this argument.
17139 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17141 .addImm(MaxOffset + 8 - ArgSizeA8);
17143 // Branch to "overflowMBB" if offset >= max
17144 // Fall through to "offsetMBB" otherwise
17145 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17146 .addMBB(overflowMBB);
17149 // In offsetMBB, emit code to use the reg_save_area.
17151 assert(OffsetReg != 0);
17153 // Read the reg_save_area address.
17154 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17155 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17160 .addOperand(Segment)
17161 .setMemRefs(MMOBegin, MMOEnd);
17163 // Zero-extend the offset
17164 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17165 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17168 .addImm(X86::sub_32bit);
17170 // Add the offset to the reg_save_area to get the final address.
17171 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17172 .addReg(OffsetReg64)
17173 .addReg(RegSaveReg);
17175 // Compute the offset for the next argument
17176 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17177 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17179 .addImm(UseFPOffset ? 16 : 8);
17181 // Store it back into the va_list.
17182 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17186 .addDisp(Disp, UseFPOffset ? 4 : 0)
17187 .addOperand(Segment)
17188 .addReg(NextOffsetReg)
17189 .setMemRefs(MMOBegin, MMOEnd);
17192 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17197 // Emit code to use overflow area
17200 // Load the overflow_area address into a register.
17201 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17202 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17207 .addOperand(Segment)
17208 .setMemRefs(MMOBegin, MMOEnd);
17210 // If we need to align it, do so. Otherwise, just copy the address
17211 // to OverflowDestReg.
17213 // Align the overflow address
17214 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17215 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17217 // aligned_addr = (addr + (align-1)) & ~(align-1)
17218 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17219 .addReg(OverflowAddrReg)
17222 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17224 .addImm(~(uint64_t)(Align-1));
17226 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17227 .addReg(OverflowAddrReg);
17230 // Compute the next overflow address after this argument.
17231 // (the overflow address should be kept 8-byte aligned)
17232 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17233 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17234 .addReg(OverflowDestReg)
17235 .addImm(ArgSizeA8);
17237 // Store the new overflow address.
17238 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17243 .addOperand(Segment)
17244 .addReg(NextAddrReg)
17245 .setMemRefs(MMOBegin, MMOEnd);
17247 // If we branched, emit the PHI to the front of endMBB.
17249 BuildMI(*endMBB, endMBB->begin(), DL,
17250 TII->get(X86::PHI), DestReg)
17251 .addReg(OffsetDestReg).addMBB(offsetMBB)
17252 .addReg(OverflowDestReg).addMBB(overflowMBB);
17255 // Erase the pseudo instruction
17256 MI->eraseFromParent();
17261 MachineBasicBlock *
17262 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17264 MachineBasicBlock *MBB) const {
17265 // Emit code to save XMM registers to the stack. The ABI says that the
17266 // number of registers to save is given in %al, so it's theoretically
17267 // possible to do an indirect jump trick to avoid saving all of them,
17268 // however this code takes a simpler approach and just executes all
17269 // of the stores if %al is non-zero. It's less code, and it's probably
17270 // easier on the hardware branch predictor, and stores aren't all that
17271 // expensive anyway.
17273 // Create the new basic blocks. One block contains all the XMM stores,
17274 // and one block is the final destination regardless of whether any
17275 // stores were performed.
17276 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17277 MachineFunction *F = MBB->getParent();
17278 MachineFunction::iterator MBBIter = MBB;
17280 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17281 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17282 F->insert(MBBIter, XMMSaveMBB);
17283 F->insert(MBBIter, EndMBB);
17285 // Transfer the remainder of MBB and its successor edges to EndMBB.
17286 EndMBB->splice(EndMBB->begin(), MBB,
17287 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17288 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17290 // The original block will now fall through to the XMM save block.
17291 MBB->addSuccessor(XMMSaveMBB);
17292 // The XMMSaveMBB will fall through to the end block.
17293 XMMSaveMBB->addSuccessor(EndMBB);
17295 // Now add the instructions.
17296 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17297 DebugLoc DL = MI->getDebugLoc();
17299 unsigned CountReg = MI->getOperand(0).getReg();
17300 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17301 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17303 if (!Subtarget->isTargetWin64()) {
17304 // If %al is 0, branch around the XMM save block.
17305 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17306 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17307 MBB->addSuccessor(EndMBB);
17310 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17311 // that was just emitted, but clearly shouldn't be "saved".
17312 assert((MI->getNumOperands() <= 3 ||
17313 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17314 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17315 && "Expected last argument to be EFLAGS");
17316 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17317 // In the XMM save block, save all the XMM argument registers.
17318 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17319 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17320 MachineMemOperand *MMO =
17321 F->getMachineMemOperand(
17322 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17323 MachineMemOperand::MOStore,
17324 /*Size=*/16, /*Align=*/16);
17325 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17326 .addFrameIndex(RegSaveFrameIndex)
17327 .addImm(/*Scale=*/1)
17328 .addReg(/*IndexReg=*/0)
17329 .addImm(/*Disp=*/Offset)
17330 .addReg(/*Segment=*/0)
17331 .addReg(MI->getOperand(i).getReg())
17332 .addMemOperand(MMO);
17335 MI->eraseFromParent(); // The pseudo instruction is gone now.
17340 // The EFLAGS operand of SelectItr might be missing a kill marker
17341 // because there were multiple uses of EFLAGS, and ISel didn't know
17342 // which to mark. Figure out whether SelectItr should have had a
17343 // kill marker, and set it if it should. Returns the correct kill
17345 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
17346 MachineBasicBlock* BB,
17347 const TargetRegisterInfo* TRI) {
17348 // Scan forward through BB for a use/def of EFLAGS.
17349 MachineBasicBlock::iterator miI(std::next(SelectItr));
17350 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
17351 const MachineInstr& mi = *miI;
17352 if (mi.readsRegister(X86::EFLAGS))
17354 if (mi.definesRegister(X86::EFLAGS))
17355 break; // Should have kill-flag - update below.
17358 // If we hit the end of the block, check whether EFLAGS is live into a
17360 if (miI == BB->end()) {
17361 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
17362 sEnd = BB->succ_end();
17363 sItr != sEnd; ++sItr) {
17364 MachineBasicBlock* succ = *sItr;
17365 if (succ->isLiveIn(X86::EFLAGS))
17370 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
17371 // out. SelectMI should have a kill flag on EFLAGS.
17372 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
17376 MachineBasicBlock *
17377 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
17378 MachineBasicBlock *BB) const {
17379 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17380 DebugLoc DL = MI->getDebugLoc();
17382 // To "insert" a SELECT_CC instruction, we actually have to insert the
17383 // diamond control-flow pattern. The incoming instruction knows the
17384 // destination vreg to set, the condition code register to branch on, the
17385 // true/false values to select between, and a branch opcode to use.
17386 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17387 MachineFunction::iterator It = BB;
17393 // cmpTY ccX, r1, r2
17395 // fallthrough --> copy0MBB
17396 MachineBasicBlock *thisMBB = BB;
17397 MachineFunction *F = BB->getParent();
17398 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
17399 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
17400 F->insert(It, copy0MBB);
17401 F->insert(It, sinkMBB);
17403 // If the EFLAGS register isn't dead in the terminator, then claim that it's
17404 // live into the sink and copy blocks.
17405 const TargetRegisterInfo* TRI = BB->getParent()->getTarget().getRegisterInfo();
17406 if (!MI->killsRegister(X86::EFLAGS) &&
17407 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
17408 copy0MBB->addLiveIn(X86::EFLAGS);
17409 sinkMBB->addLiveIn(X86::EFLAGS);
17412 // Transfer the remainder of BB and its successor edges to sinkMBB.
17413 sinkMBB->splice(sinkMBB->begin(), BB,
17414 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17415 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
17417 // Add the true and fallthrough blocks as its successors.
17418 BB->addSuccessor(copy0MBB);
17419 BB->addSuccessor(sinkMBB);
17421 // Create the conditional branch instruction.
17423 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
17424 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
17427 // %FalseValue = ...
17428 // # fallthrough to sinkMBB
17429 copy0MBB->addSuccessor(sinkMBB);
17432 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
17434 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17435 TII->get(X86::PHI), MI->getOperand(0).getReg())
17436 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
17437 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
17439 MI->eraseFromParent(); // The pseudo instruction is gone now.
17443 MachineBasicBlock *
17444 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
17445 bool Is64Bit) const {
17446 MachineFunction *MF = BB->getParent();
17447 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17448 DebugLoc DL = MI->getDebugLoc();
17449 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17451 assert(MF->shouldSplitStack());
17453 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
17454 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
17457 // ... [Till the alloca]
17458 // If stacklet is not large enough, jump to mallocMBB
17461 // Allocate by subtracting from RSP
17462 // Jump to continueMBB
17465 // Allocate by call to runtime
17469 // [rest of original BB]
17472 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17473 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17474 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17476 MachineRegisterInfo &MRI = MF->getRegInfo();
17477 const TargetRegisterClass *AddrRegClass =
17478 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
17480 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17481 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17482 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
17483 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
17484 sizeVReg = MI->getOperand(1).getReg(),
17485 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
17487 MachineFunction::iterator MBBIter = BB;
17490 MF->insert(MBBIter, bumpMBB);
17491 MF->insert(MBBIter, mallocMBB);
17492 MF->insert(MBBIter, continueMBB);
17494 continueMBB->splice(continueMBB->begin(), BB,
17495 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17496 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
17498 // Add code to the main basic block to check if the stack limit has been hit,
17499 // and if so, jump to mallocMBB otherwise to bumpMBB.
17500 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
17501 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
17502 .addReg(tmpSPVReg).addReg(sizeVReg);
17503 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
17504 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
17505 .addReg(SPLimitVReg);
17506 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
17508 // bumpMBB simply decreases the stack pointer, since we know the current
17509 // stacklet has enough space.
17510 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
17511 .addReg(SPLimitVReg);
17512 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
17513 .addReg(SPLimitVReg);
17514 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17516 // Calls into a routine in libgcc to allocate more space from the heap.
17517 const uint32_t *RegMask =
17518 MF->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17520 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
17522 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
17523 .addExternalSymbol("__morestack_allocate_stack_space")
17524 .addRegMask(RegMask)
17525 .addReg(X86::RDI, RegState::Implicit)
17526 .addReg(X86::RAX, RegState::ImplicitDefine);
17528 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
17530 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
17531 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
17532 .addExternalSymbol("__morestack_allocate_stack_space")
17533 .addRegMask(RegMask)
17534 .addReg(X86::EAX, RegState::ImplicitDefine);
17538 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
17541 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
17542 .addReg(Is64Bit ? X86::RAX : X86::EAX);
17543 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17545 // Set up the CFG correctly.
17546 BB->addSuccessor(bumpMBB);
17547 BB->addSuccessor(mallocMBB);
17548 mallocMBB->addSuccessor(continueMBB);
17549 bumpMBB->addSuccessor(continueMBB);
17551 // Take care of the PHI nodes.
17552 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
17553 MI->getOperand(0).getReg())
17554 .addReg(mallocPtrVReg).addMBB(mallocMBB)
17555 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
17557 // Delete the original pseudo instruction.
17558 MI->eraseFromParent();
17561 return continueMBB;
17564 MachineBasicBlock *
17565 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
17566 MachineBasicBlock *BB) const {
17567 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17568 DebugLoc DL = MI->getDebugLoc();
17570 assert(!Subtarget->isTargetMacho());
17572 // The lowering is pretty easy: we're just emitting the call to _alloca. The
17573 // non-trivial part is impdef of ESP.
17575 if (Subtarget->isTargetWin64()) {
17576 if (Subtarget->isTargetCygMing()) {
17577 // ___chkstk(Mingw64):
17578 // Clobbers R10, R11, RAX and EFLAGS.
17580 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17581 .addExternalSymbol("___chkstk")
17582 .addReg(X86::RAX, RegState::Implicit)
17583 .addReg(X86::RSP, RegState::Implicit)
17584 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
17585 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
17586 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17588 // __chkstk(MSVCRT): does not update stack pointer.
17589 // Clobbers R10, R11 and EFLAGS.
17590 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17591 .addExternalSymbol("__chkstk")
17592 .addReg(X86::RAX, RegState::Implicit)
17593 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17594 // RAX has the offset to be subtracted from RSP.
17595 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
17600 const char *StackProbeSymbol =
17601 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
17603 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
17604 .addExternalSymbol(StackProbeSymbol)
17605 .addReg(X86::EAX, RegState::Implicit)
17606 .addReg(X86::ESP, RegState::Implicit)
17607 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
17608 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
17609 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17612 MI->eraseFromParent(); // The pseudo instruction is gone now.
17616 MachineBasicBlock *
17617 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
17618 MachineBasicBlock *BB) const {
17619 // This is pretty easy. We're taking the value that we received from
17620 // our load from the relocation, sticking it in either RDI (x86-64)
17621 // or EAX and doing an indirect call. The return value will then
17622 // be in the normal return register.
17623 MachineFunction *F = BB->getParent();
17624 const X86InstrInfo *TII
17625 = static_cast<const X86InstrInfo*>(F->getTarget().getInstrInfo());
17626 DebugLoc DL = MI->getDebugLoc();
17628 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
17629 assert(MI->getOperand(3).isGlobal() && "This should be a global");
17631 // Get a register mask for the lowered call.
17632 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
17633 // proper register mask.
17634 const uint32_t *RegMask =
17635 F->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17636 if (Subtarget->is64Bit()) {
17637 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17638 TII->get(X86::MOV64rm), X86::RDI)
17640 .addImm(0).addReg(0)
17641 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17642 MI->getOperand(3).getTargetFlags())
17644 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
17645 addDirectMem(MIB, X86::RDI);
17646 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
17647 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
17648 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17649 TII->get(X86::MOV32rm), X86::EAX)
17651 .addImm(0).addReg(0)
17652 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17653 MI->getOperand(3).getTargetFlags())
17655 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17656 addDirectMem(MIB, X86::EAX);
17657 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17659 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17660 TII->get(X86::MOV32rm), X86::EAX)
17661 .addReg(TII->getGlobalBaseReg(F))
17662 .addImm(0).addReg(0)
17663 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17664 MI->getOperand(3).getTargetFlags())
17666 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17667 addDirectMem(MIB, X86::EAX);
17668 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17671 MI->eraseFromParent(); // The pseudo instruction is gone now.
17675 MachineBasicBlock *
17676 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
17677 MachineBasicBlock *MBB) const {
17678 DebugLoc DL = MI->getDebugLoc();
17679 MachineFunction *MF = MBB->getParent();
17680 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17681 MachineRegisterInfo &MRI = MF->getRegInfo();
17683 const BasicBlock *BB = MBB->getBasicBlock();
17684 MachineFunction::iterator I = MBB;
17687 // Memory Reference
17688 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17689 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17692 unsigned MemOpndSlot = 0;
17694 unsigned CurOp = 0;
17696 DstReg = MI->getOperand(CurOp++).getReg();
17697 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
17698 assert(RC->hasType(MVT::i32) && "Invalid destination!");
17699 unsigned mainDstReg = MRI.createVirtualRegister(RC);
17700 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
17702 MemOpndSlot = CurOp;
17704 MVT PVT = getPointerTy();
17705 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17706 "Invalid Pointer Size!");
17708 // For v = setjmp(buf), we generate
17711 // buf[LabelOffset] = restoreMBB
17712 // SjLjSetup restoreMBB
17718 // v = phi(main, restore)
17723 MachineBasicBlock *thisMBB = MBB;
17724 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17725 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17726 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
17727 MF->insert(I, mainMBB);
17728 MF->insert(I, sinkMBB);
17729 MF->push_back(restoreMBB);
17731 MachineInstrBuilder MIB;
17733 // Transfer the remainder of BB and its successor edges to sinkMBB.
17734 sinkMBB->splice(sinkMBB->begin(), MBB,
17735 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17736 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17739 unsigned PtrStoreOpc = 0;
17740 unsigned LabelReg = 0;
17741 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17742 Reloc::Model RM = MF->getTarget().getRelocationModel();
17743 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
17744 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
17746 // Prepare IP either in reg or imm.
17747 if (!UseImmLabel) {
17748 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
17749 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
17750 LabelReg = MRI.createVirtualRegister(PtrRC);
17751 if (Subtarget->is64Bit()) {
17752 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
17756 .addMBB(restoreMBB)
17759 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
17760 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
17761 .addReg(XII->getGlobalBaseReg(MF))
17764 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
17768 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
17770 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
17771 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17772 if (i == X86::AddrDisp)
17773 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
17775 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
17778 MIB.addReg(LabelReg);
17780 MIB.addMBB(restoreMBB);
17781 MIB.setMemRefs(MMOBegin, MMOEnd);
17783 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
17784 .addMBB(restoreMBB);
17786 const X86RegisterInfo *RegInfo =
17787 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17788 MIB.addRegMask(RegInfo->getNoPreservedMask());
17789 thisMBB->addSuccessor(mainMBB);
17790 thisMBB->addSuccessor(restoreMBB);
17794 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
17795 mainMBB->addSuccessor(sinkMBB);
17798 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17799 TII->get(X86::PHI), DstReg)
17800 .addReg(mainDstReg).addMBB(mainMBB)
17801 .addReg(restoreDstReg).addMBB(restoreMBB);
17804 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
17805 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
17806 restoreMBB->addSuccessor(sinkMBB);
17808 MI->eraseFromParent();
17812 MachineBasicBlock *
17813 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
17814 MachineBasicBlock *MBB) const {
17815 DebugLoc DL = MI->getDebugLoc();
17816 MachineFunction *MF = MBB->getParent();
17817 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17818 MachineRegisterInfo &MRI = MF->getRegInfo();
17820 // Memory Reference
17821 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17822 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17824 MVT PVT = getPointerTy();
17825 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17826 "Invalid Pointer Size!");
17828 const TargetRegisterClass *RC =
17829 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
17830 unsigned Tmp = MRI.createVirtualRegister(RC);
17831 // Since FP is only updated here but NOT referenced, it's treated as GPR.
17832 const X86RegisterInfo *RegInfo =
17833 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17834 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
17835 unsigned SP = RegInfo->getStackRegister();
17837 MachineInstrBuilder MIB;
17839 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17840 const int64_t SPOffset = 2 * PVT.getStoreSize();
17842 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
17843 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
17846 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
17847 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
17848 MIB.addOperand(MI->getOperand(i));
17849 MIB.setMemRefs(MMOBegin, MMOEnd);
17851 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
17852 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17853 if (i == X86::AddrDisp)
17854 MIB.addDisp(MI->getOperand(i), LabelOffset);
17856 MIB.addOperand(MI->getOperand(i));
17858 MIB.setMemRefs(MMOBegin, MMOEnd);
17860 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
17861 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17862 if (i == X86::AddrDisp)
17863 MIB.addDisp(MI->getOperand(i), SPOffset);
17865 MIB.addOperand(MI->getOperand(i));
17867 MIB.setMemRefs(MMOBegin, MMOEnd);
17869 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
17871 MI->eraseFromParent();
17875 // Replace 213-type (isel default) FMA3 instructions with 231-type for
17876 // accumulator loops. Writing back to the accumulator allows the coalescer
17877 // to remove extra copies in the loop.
17878 MachineBasicBlock *
17879 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
17880 MachineBasicBlock *MBB) const {
17881 MachineOperand &AddendOp = MI->getOperand(3);
17883 // Bail out early if the addend isn't a register - we can't switch these.
17884 if (!AddendOp.isReg())
17887 MachineFunction &MF = *MBB->getParent();
17888 MachineRegisterInfo &MRI = MF.getRegInfo();
17890 // Check whether the addend is defined by a PHI:
17891 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
17892 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
17893 if (!AddendDef.isPHI())
17896 // Look for the following pattern:
17898 // %addend = phi [%entry, 0], [%loop, %result]
17900 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
17904 // %addend = phi [%entry, 0], [%loop, %result]
17906 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
17908 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
17909 assert(AddendDef.getOperand(i).isReg());
17910 MachineOperand PHISrcOp = AddendDef.getOperand(i);
17911 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
17912 if (&PHISrcInst == MI) {
17913 // Found a matching instruction.
17914 unsigned NewFMAOpc = 0;
17915 switch (MI->getOpcode()) {
17916 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
17917 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
17918 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
17919 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
17920 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
17921 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
17922 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
17923 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
17924 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
17925 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
17926 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
17927 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
17928 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
17929 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
17930 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
17931 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
17932 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
17933 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
17934 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
17935 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
17936 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
17937 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
17938 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
17939 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
17940 default: llvm_unreachable("Unrecognized FMA variant.");
17943 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
17944 MachineInstrBuilder MIB =
17945 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
17946 .addOperand(MI->getOperand(0))
17947 .addOperand(MI->getOperand(3))
17948 .addOperand(MI->getOperand(2))
17949 .addOperand(MI->getOperand(1));
17950 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
17951 MI->eraseFromParent();
17958 MachineBasicBlock *
17959 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
17960 MachineBasicBlock *BB) const {
17961 switch (MI->getOpcode()) {
17962 default: llvm_unreachable("Unexpected instr type to insert");
17963 case X86::TAILJMPd64:
17964 case X86::TAILJMPr64:
17965 case X86::TAILJMPm64:
17966 llvm_unreachable("TAILJMP64 would not be touched here.");
17967 case X86::TCRETURNdi64:
17968 case X86::TCRETURNri64:
17969 case X86::TCRETURNmi64:
17971 case X86::WIN_ALLOCA:
17972 return EmitLoweredWinAlloca(MI, BB);
17973 case X86::SEG_ALLOCA_32:
17974 return EmitLoweredSegAlloca(MI, BB, false);
17975 case X86::SEG_ALLOCA_64:
17976 return EmitLoweredSegAlloca(MI, BB, true);
17977 case X86::TLSCall_32:
17978 case X86::TLSCall_64:
17979 return EmitLoweredTLSCall(MI, BB);
17980 case X86::CMOV_GR8:
17981 case X86::CMOV_FR32:
17982 case X86::CMOV_FR64:
17983 case X86::CMOV_V4F32:
17984 case X86::CMOV_V2F64:
17985 case X86::CMOV_V2I64:
17986 case X86::CMOV_V8F32:
17987 case X86::CMOV_V4F64:
17988 case X86::CMOV_V4I64:
17989 case X86::CMOV_V16F32:
17990 case X86::CMOV_V8F64:
17991 case X86::CMOV_V8I64:
17992 case X86::CMOV_GR16:
17993 case X86::CMOV_GR32:
17994 case X86::CMOV_RFP32:
17995 case X86::CMOV_RFP64:
17996 case X86::CMOV_RFP80:
17997 return EmitLoweredSelect(MI, BB);
17999 case X86::FP32_TO_INT16_IN_MEM:
18000 case X86::FP32_TO_INT32_IN_MEM:
18001 case X86::FP32_TO_INT64_IN_MEM:
18002 case X86::FP64_TO_INT16_IN_MEM:
18003 case X86::FP64_TO_INT32_IN_MEM:
18004 case X86::FP64_TO_INT64_IN_MEM:
18005 case X86::FP80_TO_INT16_IN_MEM:
18006 case X86::FP80_TO_INT32_IN_MEM:
18007 case X86::FP80_TO_INT64_IN_MEM: {
18008 MachineFunction *F = BB->getParent();
18009 const TargetInstrInfo *TII = F->getTarget().getInstrInfo();
18010 DebugLoc DL = MI->getDebugLoc();
18012 // Change the floating point control register to use "round towards zero"
18013 // mode when truncating to an integer value.
18014 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18015 addFrameReference(BuildMI(*BB, MI, DL,
18016 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18018 // Load the old value of the high byte of the control word...
18020 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18021 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18024 // Set the high part to be round to zero...
18025 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18028 // Reload the modified control word now...
18029 addFrameReference(BuildMI(*BB, MI, DL,
18030 TII->get(X86::FLDCW16m)), CWFrameIdx);
18032 // Restore the memory image of control word to original value
18033 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18036 // Get the X86 opcode to use.
18038 switch (MI->getOpcode()) {
18039 default: llvm_unreachable("illegal opcode!");
18040 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18041 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18042 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18043 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18044 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18045 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18046 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18047 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18048 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18052 MachineOperand &Op = MI->getOperand(0);
18054 AM.BaseType = X86AddressMode::RegBase;
18055 AM.Base.Reg = Op.getReg();
18057 AM.BaseType = X86AddressMode::FrameIndexBase;
18058 AM.Base.FrameIndex = Op.getIndex();
18060 Op = MI->getOperand(1);
18062 AM.Scale = Op.getImm();
18063 Op = MI->getOperand(2);
18065 AM.IndexReg = Op.getImm();
18066 Op = MI->getOperand(3);
18067 if (Op.isGlobal()) {
18068 AM.GV = Op.getGlobal();
18070 AM.Disp = Op.getImm();
18072 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18073 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18075 // Reload the original control word now.
18076 addFrameReference(BuildMI(*BB, MI, DL,
18077 TII->get(X86::FLDCW16m)), CWFrameIdx);
18079 MI->eraseFromParent(); // The pseudo instruction is gone now.
18082 // String/text processing lowering.
18083 case X86::PCMPISTRM128REG:
18084 case X86::VPCMPISTRM128REG:
18085 case X86::PCMPISTRM128MEM:
18086 case X86::VPCMPISTRM128MEM:
18087 case X86::PCMPESTRM128REG:
18088 case X86::VPCMPESTRM128REG:
18089 case X86::PCMPESTRM128MEM:
18090 case X86::VPCMPESTRM128MEM:
18091 assert(Subtarget->hasSSE42() &&
18092 "Target must have SSE4.2 or AVX features enabled");
18093 return EmitPCMPSTRM(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18095 // String/text processing lowering.
18096 case X86::PCMPISTRIREG:
18097 case X86::VPCMPISTRIREG:
18098 case X86::PCMPISTRIMEM:
18099 case X86::VPCMPISTRIMEM:
18100 case X86::PCMPESTRIREG:
18101 case X86::VPCMPESTRIREG:
18102 case X86::PCMPESTRIMEM:
18103 case X86::VPCMPESTRIMEM:
18104 assert(Subtarget->hasSSE42() &&
18105 "Target must have SSE4.2 or AVX features enabled");
18106 return EmitPCMPSTRI(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18108 // Thread synchronization.
18110 return EmitMonitor(MI, BB, BB->getParent()->getTarget().getInstrInfo(), Subtarget);
18114 return EmitXBegin(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18116 case X86::VASTART_SAVE_XMM_REGS:
18117 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18119 case X86::VAARG_64:
18120 return EmitVAARG64WithCustomInserter(MI, BB);
18122 case X86::EH_SjLj_SetJmp32:
18123 case X86::EH_SjLj_SetJmp64:
18124 return emitEHSjLjSetJmp(MI, BB);
18126 case X86::EH_SjLj_LongJmp32:
18127 case X86::EH_SjLj_LongJmp64:
18128 return emitEHSjLjLongJmp(MI, BB);
18130 case TargetOpcode::STACKMAP:
18131 case TargetOpcode::PATCHPOINT:
18132 return emitPatchPoint(MI, BB);
18134 case X86::VFMADDPDr213r:
18135 case X86::VFMADDPSr213r:
18136 case X86::VFMADDSDr213r:
18137 case X86::VFMADDSSr213r:
18138 case X86::VFMSUBPDr213r:
18139 case X86::VFMSUBPSr213r:
18140 case X86::VFMSUBSDr213r:
18141 case X86::VFMSUBSSr213r:
18142 case X86::VFNMADDPDr213r:
18143 case X86::VFNMADDPSr213r:
18144 case X86::VFNMADDSDr213r:
18145 case X86::VFNMADDSSr213r:
18146 case X86::VFNMSUBPDr213r:
18147 case X86::VFNMSUBPSr213r:
18148 case X86::VFNMSUBSDr213r:
18149 case X86::VFNMSUBSSr213r:
18150 case X86::VFMADDPDr213rY:
18151 case X86::VFMADDPSr213rY:
18152 case X86::VFMSUBPDr213rY:
18153 case X86::VFMSUBPSr213rY:
18154 case X86::VFNMADDPDr213rY:
18155 case X86::VFNMADDPSr213rY:
18156 case X86::VFNMSUBPDr213rY:
18157 case X86::VFNMSUBPSr213rY:
18158 return emitFMA3Instr(MI, BB);
18162 //===----------------------------------------------------------------------===//
18163 // X86 Optimization Hooks
18164 //===----------------------------------------------------------------------===//
18166 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18169 const SelectionDAG &DAG,
18170 unsigned Depth) const {
18171 unsigned BitWidth = KnownZero.getBitWidth();
18172 unsigned Opc = Op.getOpcode();
18173 assert((Opc >= ISD::BUILTIN_OP_END ||
18174 Opc == ISD::INTRINSIC_WO_CHAIN ||
18175 Opc == ISD::INTRINSIC_W_CHAIN ||
18176 Opc == ISD::INTRINSIC_VOID) &&
18177 "Should use MaskedValueIsZero if you don't know whether Op"
18178 " is a target node!");
18180 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18194 // These nodes' second result is a boolean.
18195 if (Op.getResNo() == 0)
18198 case X86ISD::SETCC:
18199 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18201 case ISD::INTRINSIC_WO_CHAIN: {
18202 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18203 unsigned NumLoBits = 0;
18206 case Intrinsic::x86_sse_movmsk_ps:
18207 case Intrinsic::x86_avx_movmsk_ps_256:
18208 case Intrinsic::x86_sse2_movmsk_pd:
18209 case Intrinsic::x86_avx_movmsk_pd_256:
18210 case Intrinsic::x86_mmx_pmovmskb:
18211 case Intrinsic::x86_sse2_pmovmskb_128:
18212 case Intrinsic::x86_avx2_pmovmskb: {
18213 // High bits of movmskp{s|d}, pmovmskb are known zero.
18215 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18216 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18217 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18218 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18219 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18220 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18221 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18222 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18224 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18233 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18235 const SelectionDAG &,
18236 unsigned Depth) const {
18237 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18238 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18239 return Op.getValueType().getScalarType().getSizeInBits();
18245 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18246 /// node is a GlobalAddress + offset.
18247 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18248 const GlobalValue* &GA,
18249 int64_t &Offset) const {
18250 if (N->getOpcode() == X86ISD::Wrapper) {
18251 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18252 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18253 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18257 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18260 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18261 /// same as extracting the high 128-bit part of 256-bit vector and then
18262 /// inserting the result into the low part of a new 256-bit vector
18263 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18264 EVT VT = SVOp->getValueType(0);
18265 unsigned NumElems = VT.getVectorNumElements();
18267 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18268 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18269 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18270 SVOp->getMaskElt(j) >= 0)
18276 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18277 /// same as extracting the low 128-bit part of 256-bit vector and then
18278 /// inserting the result into the high part of a new 256-bit vector
18279 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18280 EVT VT = SVOp->getValueType(0);
18281 unsigned NumElems = VT.getVectorNumElements();
18283 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18284 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18285 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18286 SVOp->getMaskElt(j) >= 0)
18292 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18293 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18294 TargetLowering::DAGCombinerInfo &DCI,
18295 const X86Subtarget* Subtarget) {
18297 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18298 SDValue V1 = SVOp->getOperand(0);
18299 SDValue V2 = SVOp->getOperand(1);
18300 EVT VT = SVOp->getValueType(0);
18301 unsigned NumElems = VT.getVectorNumElements();
18303 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18304 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18308 // V UNDEF BUILD_VECTOR UNDEF
18310 // CONCAT_VECTOR CONCAT_VECTOR
18313 // RESULT: V + zero extended
18315 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18316 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18317 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18320 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
18323 // To match the shuffle mask, the first half of the mask should
18324 // be exactly the first vector, and all the rest a splat with the
18325 // first element of the second one.
18326 for (unsigned i = 0; i != NumElems/2; ++i)
18327 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
18328 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
18331 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
18332 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
18333 if (Ld->hasNUsesOfValue(1, 0)) {
18334 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
18335 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
18337 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
18339 Ld->getPointerInfo(),
18340 Ld->getAlignment(),
18341 false/*isVolatile*/, true/*ReadMem*/,
18342 false/*WriteMem*/);
18344 // Make sure the newly-created LOAD is in the same position as Ld in
18345 // terms of dependency. We create a TokenFactor for Ld and ResNode,
18346 // and update uses of Ld's output chain to use the TokenFactor.
18347 if (Ld->hasAnyUseOfValue(1)) {
18348 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18349 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
18350 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
18351 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
18352 SDValue(ResNode.getNode(), 1));
18355 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
18359 // Emit a zeroed vector and insert the desired subvector on its
18361 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18362 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
18363 return DCI.CombineTo(N, InsV);
18366 //===--------------------------------------------------------------------===//
18367 // Combine some shuffles into subvector extracts and inserts:
18370 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18371 if (isShuffleHigh128VectorInsertLow(SVOp)) {
18372 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
18373 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
18374 return DCI.CombineTo(N, InsV);
18377 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18378 if (isShuffleLow128VectorInsertHigh(SVOp)) {
18379 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
18380 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
18381 return DCI.CombineTo(N, InsV);
18387 /// \brief Get the PSHUF-style mask from PSHUF node.
18389 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
18390 /// PSHUF-style masks that can be reused with such instructions.
18391 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
18392 SmallVector<int, 4> Mask;
18394 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
18398 switch (N.getOpcode()) {
18399 case X86ISD::PSHUFD:
18401 case X86ISD::PSHUFLW:
18404 case X86ISD::PSHUFHW:
18405 Mask.erase(Mask.begin(), Mask.begin() + 4);
18406 for (int &M : Mask)
18410 llvm_unreachable("No valid shuffle instruction found!");
18414 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
18416 /// We walk up the chain and look for a combinable shuffle, skipping over
18417 /// shuffles that we could hoist this shuffle's transformation past without
18418 /// altering anything.
18419 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
18421 TargetLowering::DAGCombinerInfo &DCI) {
18422 assert(N.getOpcode() == X86ISD::PSHUFD &&
18423 "Called with something other than an x86 128-bit half shuffle!");
18426 // Walk up a single-use chain looking for a combinable shuffle.
18427 SDValue V = N.getOperand(0);
18428 for (; V.hasOneUse(); V = V.getOperand(0)) {
18429 switch (V.getOpcode()) {
18431 return false; // Nothing combined!
18434 // Skip bitcasts as we always know the type for the target specific
18438 case X86ISD::PSHUFD:
18439 // Found another dword shuffle.
18442 case X86ISD::PSHUFLW:
18443 // Check that the low words (being shuffled) are the identity in the
18444 // dword shuffle, and the high words are self-contained.
18445 if (Mask[0] != 0 || Mask[1] != 1 ||
18446 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
18451 case X86ISD::PSHUFHW:
18452 // Check that the high words (being shuffled) are the identity in the
18453 // dword shuffle, and the low words are self-contained.
18454 if (Mask[2] != 2 || Mask[3] != 3 ||
18455 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
18460 // Break out of the loop if we break out of the switch.
18464 if (!V.hasOneUse())
18465 // We fell out of the loop without finding a viable combining instruction.
18468 // Record the old value to use in RAUW-ing.
18471 // Merge this node's mask and our incoming mask.
18472 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18473 for (int &M : Mask)
18475 V = DAG.getNode(X86ISD::PSHUFD, DL, V.getValueType(), V.getOperand(0),
18476 getV4X86ShuffleImm8ForMask(Mask, DAG));
18478 // It is possible that one of the combinable shuffles was completely absorbed
18479 // by the other, just replace it and revisit all users in that case.
18480 if (Old.getNode() == V.getNode()) {
18481 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
18485 // Replace N with its operand as we're going to combine that shuffle away.
18486 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18488 // Replace the combinable shuffle with the combined one, updating all users
18489 // so that we re-evaluate the chain here.
18490 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18494 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
18496 /// We walk up the chain, skipping shuffles of the other half and looking
18497 /// through shuffles which switch halves trying to find a shuffle of the same
18498 /// pair of dwords.
18499 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
18501 TargetLowering::DAGCombinerInfo &DCI) {
18503 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
18504 "Called with something other than an x86 128-bit half shuffle!");
18506 unsigned CombineOpcode = N.getOpcode();
18508 // Walk up a single-use chain looking for a combinable shuffle.
18509 SDValue V = N.getOperand(0);
18510 for (; V.hasOneUse(); V = V.getOperand(0)) {
18511 switch (V.getOpcode()) {
18513 return false; // Nothing combined!
18516 // Skip bitcasts as we always know the type for the target specific
18520 case X86ISD::PSHUFLW:
18521 case X86ISD::PSHUFHW:
18522 if (V.getOpcode() == CombineOpcode)
18525 // Other-half shuffles are no-ops.
18528 case X86ISD::PSHUFD: {
18529 // We can only handle pshufd if the half we are combining either stays in
18530 // its half, or switches to the other half. Bail if one of these isn't
18532 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18533 int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
18534 if (!((VMask[DOffset + 0] < 2 && VMask[DOffset + 1] < 2) ||
18535 (VMask[DOffset + 0] >= 2 && VMask[DOffset + 1] >= 2)))
18538 // Map the mask through the pshufd and keep walking up the chain.
18539 for (int i = 0; i < 4; ++i)
18540 Mask[i] = 2 * (VMask[DOffset + Mask[i] / 2] % 2) + Mask[i] % 2;
18542 // Switch halves if the pshufd does.
18544 VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18548 // Break out of the loop if we break out of the switch.
18552 if (!V.hasOneUse())
18553 // We fell out of the loop without finding a viable combining instruction.
18556 // Record the old value to use in RAUW-ing.
18559 // Merge this node's mask and our incoming mask (adjusted to account for all
18560 // the pshufd instructions encountered).
18561 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18562 for (int &M : Mask)
18564 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
18565 getV4X86ShuffleImm8ForMask(Mask, DAG));
18567 // Replace N with its operand as we're going to combine that shuffle away.
18568 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18570 // Replace the combinable shuffle with the combined one, updating all users
18571 // so that we re-evaluate the chain here.
18572 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18576 /// \brief Try to combine x86 target specific shuffles.
18577 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
18578 TargetLowering::DAGCombinerInfo &DCI,
18579 const X86Subtarget *Subtarget) {
18581 MVT VT = N.getSimpleValueType();
18582 SmallVector<int, 4> Mask;
18584 switch (N.getOpcode()) {
18585 case X86ISD::PSHUFD:
18586 case X86ISD::PSHUFLW:
18587 case X86ISD::PSHUFHW:
18588 Mask = getPSHUFShuffleMask(N);
18589 assert(Mask.size() == 4);
18595 // Nuke no-op shuffles that show up after combining.
18596 if (isNoopShuffleMask(Mask))
18597 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
18599 // Look for simplifications involving one or two shuffle instructions.
18600 SDValue V = N.getOperand(0);
18601 switch (N.getOpcode()) {
18604 case X86ISD::PSHUFLW:
18605 case X86ISD::PSHUFHW:
18606 assert(VT == MVT::v8i16);
18609 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
18610 return SDValue(); // We combined away this shuffle, so we're done.
18612 // See if this reduces to a PSHUFD which is no more expensive and can
18613 // combine with more operations.
18614 if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
18615 areAdjacentMasksSequential(Mask)) {
18616 int DMask[] = {-1, -1, -1, -1};
18617 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
18618 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
18619 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
18620 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
18621 DCI.AddToWorklist(V.getNode());
18622 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
18623 getV4X86ShuffleImm8ForMask(DMask, DAG));
18624 DCI.AddToWorklist(V.getNode());
18625 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
18630 case X86ISD::PSHUFD:
18631 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
18632 return SDValue(); // We combined away this shuffle.
18640 /// PerformShuffleCombine - Performs several different shuffle combines.
18641 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
18642 TargetLowering::DAGCombinerInfo &DCI,
18643 const X86Subtarget *Subtarget) {
18645 SDValue N0 = N->getOperand(0);
18646 SDValue N1 = N->getOperand(1);
18647 EVT VT = N->getValueType(0);
18649 // Canonicalize shuffles that perform 'addsub' on packed float vectors
18650 // according to the rule:
18651 // (shuffle (FADD A, B), (FSUB A, B), Mask) ->
18652 // (shuffle (FSUB A, -B), (FADD A, -B), Mask)
18654 // Where 'Mask' is:
18655 // <0,5,2,7> -- for v4f32 and v4f64 shuffles;
18656 // <0,3> -- for v2f64 shuffles;
18657 // <0,9,2,11,4,13,6,15> -- for v8f32 shuffles.
18659 // This helps pattern-matching more SSE3/AVX ADDSUB instructions
18660 // during ISel stage.
18661 if (N->getOpcode() == ISD::VECTOR_SHUFFLE &&
18662 ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18663 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18664 N0->getOpcode() == ISD::FADD && N1->getOpcode() == ISD::FSUB &&
18665 // Operands to the FADD and FSUB must be the same.
18666 ((N0->getOperand(0) == N1->getOperand(0) &&
18667 N0->getOperand(1) == N1->getOperand(1)) ||
18668 // FADD is commutable. See if by commuting the operands of the FADD
18669 // we would still be able to match the operands of the FSUB dag node.
18670 (N0->getOperand(1) == N1->getOperand(0) &&
18671 N0->getOperand(0) == N1->getOperand(1))) &&
18672 N0->getOperand(0)->getOpcode() != ISD::UNDEF &&
18673 N0->getOperand(1)->getOpcode() != ISD::UNDEF) {
18675 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
18676 unsigned NumElts = VT.getVectorNumElements();
18677 ArrayRef<int> Mask = SV->getMask();
18678 bool CanFold = true;
18680 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i)
18681 CanFold = Mask[i] == (int)((i & 1) ? i + NumElts : i);
18684 SDValue Op0 = N1->getOperand(0);
18685 SDValue Op1 = DAG.getNode(ISD::FNEG, dl, VT, N1->getOperand(1));
18686 SDValue Sub = DAG.getNode(ISD::FSUB, dl, VT, Op0, Op1);
18687 SDValue Add = DAG.getNode(ISD::FADD, dl, VT, Op0, Op1);
18688 return DAG.getVectorShuffle(VT, dl, Sub, Add, Mask);
18692 // Don't create instructions with illegal types after legalize types has run.
18693 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18694 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
18697 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
18698 if (Subtarget->hasFp256() && VT.is256BitVector() &&
18699 N->getOpcode() == ISD::VECTOR_SHUFFLE)
18700 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
18702 // During Type Legalization, when promoting illegal vector types,
18703 // the backend might introduce new shuffle dag nodes and bitcasts.
18705 // This code performs the following transformation:
18706 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
18707 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
18709 // We do this only if both the bitcast and the BINOP dag nodes have
18710 // one use. Also, perform this transformation only if the new binary
18711 // operation is legal. This is to avoid introducing dag nodes that
18712 // potentially need to be further expanded (or custom lowered) into a
18713 // less optimal sequence of dag nodes.
18714 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
18715 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
18716 N0.getOpcode() == ISD::BITCAST) {
18717 SDValue BC0 = N0.getOperand(0);
18718 EVT SVT = BC0.getValueType();
18719 unsigned Opcode = BC0.getOpcode();
18720 unsigned NumElts = VT.getVectorNumElements();
18722 if (BC0.hasOneUse() && SVT.isVector() &&
18723 SVT.getVectorNumElements() * 2 == NumElts &&
18724 TLI.isOperationLegal(Opcode, VT)) {
18725 bool CanFold = false;
18737 unsigned SVTNumElts = SVT.getVectorNumElements();
18738 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18739 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
18740 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
18741 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
18742 CanFold = SVOp->getMaskElt(i) < 0;
18745 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
18746 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
18747 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
18748 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
18753 // Only handle 128 wide vector from here on.
18754 if (!VT.is128BitVector())
18757 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
18758 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
18759 // consecutive, non-overlapping, and in the right order.
18760 SmallVector<SDValue, 16> Elts;
18761 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
18762 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
18764 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
18768 if (isTargetShuffle(N->getOpcode())) {
18770 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
18771 if (Shuffle.getNode())
18778 /// PerformTruncateCombine - Converts truncate operation to
18779 /// a sequence of vector shuffle operations.
18780 /// It is possible when we truncate 256-bit vector to 128-bit vector
18781 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
18782 TargetLowering::DAGCombinerInfo &DCI,
18783 const X86Subtarget *Subtarget) {
18787 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
18788 /// specific shuffle of a load can be folded into a single element load.
18789 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
18790 /// shuffles have been customed lowered so we need to handle those here.
18791 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
18792 TargetLowering::DAGCombinerInfo &DCI) {
18793 if (DCI.isBeforeLegalizeOps())
18796 SDValue InVec = N->getOperand(0);
18797 SDValue EltNo = N->getOperand(1);
18799 if (!isa<ConstantSDNode>(EltNo))
18802 EVT VT = InVec.getValueType();
18804 bool HasShuffleIntoBitcast = false;
18805 if (InVec.getOpcode() == ISD::BITCAST) {
18806 // Don't duplicate a load with other uses.
18807 if (!InVec.hasOneUse())
18809 EVT BCVT = InVec.getOperand(0).getValueType();
18810 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
18812 InVec = InVec.getOperand(0);
18813 HasShuffleIntoBitcast = true;
18816 if (!isTargetShuffle(InVec.getOpcode()))
18819 // Don't duplicate a load with other uses.
18820 if (!InVec.hasOneUse())
18823 SmallVector<int, 16> ShuffleMask;
18825 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
18829 // Select the input vector, guarding against out of range extract vector.
18830 unsigned NumElems = VT.getVectorNumElements();
18831 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
18832 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
18833 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
18834 : InVec.getOperand(1);
18836 // If inputs to shuffle are the same for both ops, then allow 2 uses
18837 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
18839 if (LdNode.getOpcode() == ISD::BITCAST) {
18840 // Don't duplicate a load with other uses.
18841 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
18844 AllowedUses = 1; // only allow 1 load use if we have a bitcast
18845 LdNode = LdNode.getOperand(0);
18848 if (!ISD::isNormalLoad(LdNode.getNode()))
18851 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
18853 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
18856 if (HasShuffleIntoBitcast) {
18857 // If there's a bitcast before the shuffle, check if the load type and
18858 // alignment is valid.
18859 unsigned Align = LN0->getAlignment();
18860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18861 unsigned NewAlign = TLI.getDataLayout()->
18862 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
18864 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
18868 // All checks match so transform back to vector_shuffle so that DAG combiner
18869 // can finish the job
18872 // Create shuffle node taking into account the case that its a unary shuffle
18873 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
18874 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
18875 InVec.getOperand(0), Shuffle,
18877 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
18878 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
18882 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
18883 /// generation and convert it from being a bunch of shuffles and extracts
18884 /// to a simple store and scalar loads to extract the elements.
18885 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
18886 TargetLowering::DAGCombinerInfo &DCI) {
18887 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
18888 if (NewOp.getNode())
18891 SDValue InputVector = N->getOperand(0);
18893 // Detect whether we are trying to convert from mmx to i32 and the bitcast
18894 // from mmx to v2i32 has a single usage.
18895 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
18896 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
18897 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
18898 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
18899 N->getValueType(0),
18900 InputVector.getNode()->getOperand(0));
18902 // Only operate on vectors of 4 elements, where the alternative shuffling
18903 // gets to be more expensive.
18904 if (InputVector.getValueType() != MVT::v4i32)
18907 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
18908 // single use which is a sign-extend or zero-extend, and all elements are
18910 SmallVector<SDNode *, 4> Uses;
18911 unsigned ExtractedElements = 0;
18912 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
18913 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
18914 if (UI.getUse().getResNo() != InputVector.getResNo())
18917 SDNode *Extract = *UI;
18918 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
18921 if (Extract->getValueType(0) != MVT::i32)
18923 if (!Extract->hasOneUse())
18925 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
18926 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
18928 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
18931 // Record which element was extracted.
18932 ExtractedElements |=
18933 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
18935 Uses.push_back(Extract);
18938 // If not all the elements were used, this may not be worthwhile.
18939 if (ExtractedElements != 15)
18942 // Ok, we've now decided to do the transformation.
18943 SDLoc dl(InputVector);
18945 // Store the value to a temporary stack slot.
18946 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
18947 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
18948 MachinePointerInfo(), false, false, 0);
18950 // Replace each use (extract) with a load of the appropriate element.
18951 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
18952 UE = Uses.end(); UI != UE; ++UI) {
18953 SDNode *Extract = *UI;
18955 // cOMpute the element's address.
18956 SDValue Idx = Extract->getOperand(1);
18958 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
18959 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
18960 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18961 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
18963 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
18964 StackPtr, OffsetVal);
18966 // Load the scalar.
18967 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
18968 ScalarAddr, MachinePointerInfo(),
18969 false, false, false, 0);
18971 // Replace the exact with the load.
18972 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
18975 // The replacement was made in place; don't return anything.
18979 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
18980 static std::pair<unsigned, bool>
18981 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
18982 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
18983 if (!VT.isVector())
18984 return std::make_pair(0, false);
18986 bool NeedSplit = false;
18987 switch (VT.getSimpleVT().SimpleTy) {
18988 default: return std::make_pair(0, false);
18992 if (!Subtarget->hasAVX2())
18994 if (!Subtarget->hasAVX())
18995 return std::make_pair(0, false);
19000 if (!Subtarget->hasSSE2())
19001 return std::make_pair(0, false);
19004 // SSE2 has only a small subset of the operations.
19005 bool hasUnsigned = Subtarget->hasSSE41() ||
19006 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19007 bool hasSigned = Subtarget->hasSSE41() ||
19008 (Subtarget->hasSSE2() && VT == MVT::v8i16);
19010 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19013 // Check for x CC y ? x : y.
19014 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19015 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19020 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19023 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19026 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19029 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19031 // Check for x CC y ? y : x -- a min/max with reversed arms.
19032 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19033 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19038 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19041 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19044 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19047 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19051 return std::make_pair(Opc, NeedSplit);
19055 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
19056 const X86Subtarget *Subtarget) {
19058 SDValue Cond = N->getOperand(0);
19059 SDValue LHS = N->getOperand(1);
19060 SDValue RHS = N->getOperand(2);
19062 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19063 SDValue CondSrc = Cond->getOperand(0);
19064 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
19065 Cond = CondSrc->getOperand(0);
19068 MVT VT = N->getSimpleValueType(0);
19069 MVT EltVT = VT.getVectorElementType();
19070 unsigned NumElems = VT.getVectorNumElements();
19071 // There is no blend with immediate in AVX-512.
19072 if (VT.is512BitVector())
19075 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
19077 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19080 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
19083 unsigned MaskValue = 0;
19084 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
19087 SmallVector<int, 8> ShuffleMask(NumElems, -1);
19088 for (unsigned i = 0; i < NumElems; ++i) {
19089 // Be sure we emit undef where we can.
19090 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
19091 ShuffleMask[i] = -1;
19093 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
19096 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
19099 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
19101 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
19102 TargetLowering::DAGCombinerInfo &DCI,
19103 const X86Subtarget *Subtarget) {
19105 SDValue Cond = N->getOperand(0);
19106 // Get the LHS/RHS of the select.
19107 SDValue LHS = N->getOperand(1);
19108 SDValue RHS = N->getOperand(2);
19109 EVT VT = LHS.getValueType();
19110 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19112 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
19113 // instructions match the semantics of the common C idiom x<y?x:y but not
19114 // x<=y?x:y, because of how they handle negative zero (which can be
19115 // ignored in unsafe-math mode).
19116 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
19117 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
19118 (Subtarget->hasSSE2() ||
19119 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
19120 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19122 unsigned Opcode = 0;
19123 // Check for x CC y ? x : y.
19124 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19125 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19129 // Converting this to a min would handle NaNs incorrectly, and swapping
19130 // the operands would cause it to handle comparisons between positive
19131 // and negative zero incorrectly.
19132 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19133 if (!DAG.getTarget().Options.UnsafeFPMath &&
19134 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19136 std::swap(LHS, RHS);
19138 Opcode = X86ISD::FMIN;
19141 // Converting this to a min would handle comparisons between positive
19142 // and negative zero incorrectly.
19143 if (!DAG.getTarget().Options.UnsafeFPMath &&
19144 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19146 Opcode = X86ISD::FMIN;
19149 // Converting this to a min would handle both negative zeros and NaNs
19150 // incorrectly, but we can swap the operands to fix both.
19151 std::swap(LHS, RHS);
19155 Opcode = X86ISD::FMIN;
19159 // Converting this to a max would handle comparisons between positive
19160 // and negative zero incorrectly.
19161 if (!DAG.getTarget().Options.UnsafeFPMath &&
19162 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19164 Opcode = X86ISD::FMAX;
19167 // Converting this to a max would handle NaNs incorrectly, and swapping
19168 // the operands would cause it to handle comparisons between positive
19169 // and negative zero incorrectly.
19170 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19171 if (!DAG.getTarget().Options.UnsafeFPMath &&
19172 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19174 std::swap(LHS, RHS);
19176 Opcode = X86ISD::FMAX;
19179 // Converting this to a max would handle both negative zeros and NaNs
19180 // incorrectly, but we can swap the operands to fix both.
19181 std::swap(LHS, RHS);
19185 Opcode = X86ISD::FMAX;
19188 // Check for x CC y ? y : x -- a min/max with reversed arms.
19189 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19190 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19194 // Converting this to a min would handle comparisons between positive
19195 // and negative zero incorrectly, and swapping the operands would
19196 // cause it to handle NaNs incorrectly.
19197 if (!DAG.getTarget().Options.UnsafeFPMath &&
19198 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
19199 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19201 std::swap(LHS, RHS);
19203 Opcode = X86ISD::FMIN;
19206 // Converting this to a min would handle NaNs incorrectly.
19207 if (!DAG.getTarget().Options.UnsafeFPMath &&
19208 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
19210 Opcode = X86ISD::FMIN;
19213 // Converting this to a min would handle both negative zeros and NaNs
19214 // incorrectly, but we can swap the operands to fix both.
19215 std::swap(LHS, RHS);
19219 Opcode = X86ISD::FMIN;
19223 // Converting this to a max would handle NaNs incorrectly.
19224 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19226 Opcode = X86ISD::FMAX;
19229 // Converting this to a max would handle comparisons between positive
19230 // and negative zero incorrectly, and swapping the operands would
19231 // cause it to handle NaNs incorrectly.
19232 if (!DAG.getTarget().Options.UnsafeFPMath &&
19233 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
19234 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19236 std::swap(LHS, RHS);
19238 Opcode = X86ISD::FMAX;
19241 // Converting this to a max would handle both negative zeros and NaNs
19242 // incorrectly, but we can swap the operands to fix both.
19243 std::swap(LHS, RHS);
19247 Opcode = X86ISD::FMAX;
19253 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
19256 EVT CondVT = Cond.getValueType();
19257 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
19258 CondVT.getVectorElementType() == MVT::i1) {
19259 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
19260 // lowering on AVX-512. In this case we convert it to
19261 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
19262 // The same situation for all 128 and 256-bit vectors of i8 and i16
19263 EVT OpVT = LHS.getValueType();
19264 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
19265 (OpVT.getVectorElementType() == MVT::i8 ||
19266 OpVT.getVectorElementType() == MVT::i16)) {
19267 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
19268 DCI.AddToWorklist(Cond.getNode());
19269 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
19272 // If this is a select between two integer constants, try to do some
19274 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
19275 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
19276 // Don't do this for crazy integer types.
19277 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
19278 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
19279 // so that TrueC (the true value) is larger than FalseC.
19280 bool NeedsCondInvert = false;
19282 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
19283 // Efficiently invertible.
19284 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
19285 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
19286 isa<ConstantSDNode>(Cond.getOperand(1))))) {
19287 NeedsCondInvert = true;
19288 std::swap(TrueC, FalseC);
19291 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
19292 if (FalseC->getAPIntValue() == 0 &&
19293 TrueC->getAPIntValue().isPowerOf2()) {
19294 if (NeedsCondInvert) // Invert the condition if needed.
19295 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19296 DAG.getConstant(1, Cond.getValueType()));
19298 // Zero extend the condition if needed.
19299 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
19301 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19302 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
19303 DAG.getConstant(ShAmt, MVT::i8));
19306 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
19307 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19308 if (NeedsCondInvert) // Invert the condition if needed.
19309 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19310 DAG.getConstant(1, Cond.getValueType()));
19312 // Zero extend the condition if needed.
19313 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19314 FalseC->getValueType(0), Cond);
19315 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19316 SDValue(FalseC, 0));
19319 // Optimize cases that will turn into an LEA instruction. This requires
19320 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
19321 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
19322 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
19323 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
19325 bool isFastMultiplier = false;
19327 switch ((unsigned char)Diff) {
19329 case 1: // result = add base, cond
19330 case 2: // result = lea base( , cond*2)
19331 case 3: // result = lea base(cond, cond*2)
19332 case 4: // result = lea base( , cond*4)
19333 case 5: // result = lea base(cond, cond*4)
19334 case 8: // result = lea base( , cond*8)
19335 case 9: // result = lea base(cond, cond*8)
19336 isFastMultiplier = true;
19341 if (isFastMultiplier) {
19342 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
19343 if (NeedsCondInvert) // Invert the condition if needed.
19344 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19345 DAG.getConstant(1, Cond.getValueType()));
19347 // Zero extend the condition if needed.
19348 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
19350 // Scale the condition by the difference.
19352 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
19353 DAG.getConstant(Diff, Cond.getValueType()));
19355 // Add the base if non-zero.
19356 if (FalseC->getAPIntValue() != 0)
19357 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19358 SDValue(FalseC, 0));
19365 // Canonicalize max and min:
19366 // (x > y) ? x : y -> (x >= y) ? x : y
19367 // (x < y) ? x : y -> (x <= y) ? x : y
19368 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
19369 // the need for an extra compare
19370 // against zero. e.g.
19371 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
19373 // testl %edi, %edi
19375 // cmovgl %edi, %eax
19379 // cmovsl %eax, %edi
19380 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
19381 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19382 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19383 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19388 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
19389 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
19390 Cond.getOperand(0), Cond.getOperand(1), NewCC);
19391 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
19396 // Early exit check
19397 if (!TLI.isTypeLegal(VT))
19400 // Match VSELECTs into subs with unsigned saturation.
19401 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19402 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
19403 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
19404 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
19405 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19407 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
19408 // left side invert the predicate to simplify logic below.
19410 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
19412 CC = ISD::getSetCCInverse(CC, true);
19413 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
19417 if (Other.getNode() && Other->getNumOperands() == 2 &&
19418 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
19419 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
19420 SDValue CondRHS = Cond->getOperand(1);
19422 // Look for a general sub with unsigned saturation first.
19423 // x >= y ? x-y : 0 --> subus x, y
19424 // x > y ? x-y : 0 --> subus x, y
19425 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
19426 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
19427 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
19429 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
19430 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
19431 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
19432 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
19433 // If the RHS is a constant we have to reverse the const
19434 // canonicalization.
19435 // x > C-1 ? x+-C : 0 --> subus x, C
19436 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
19437 CondRHSConst->getAPIntValue() ==
19438 (-OpRHSConst->getAPIntValue() - 1))
19439 return DAG.getNode(
19440 X86ISD::SUBUS, DL, VT, OpLHS,
19441 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
19443 // Another special case: If C was a sign bit, the sub has been
19444 // canonicalized into a xor.
19445 // FIXME: Would it be better to use computeKnownBits to determine
19446 // whether it's safe to decanonicalize the xor?
19447 // x s< 0 ? x^C : 0 --> subus x, C
19448 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
19449 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
19450 OpRHSConst->getAPIntValue().isSignBit())
19451 // Note that we have to rebuild the RHS constant here to ensure we
19452 // don't rely on particular values of undef lanes.
19453 return DAG.getNode(
19454 X86ISD::SUBUS, DL, VT, OpLHS,
19455 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
19460 // Try to match a min/max vector operation.
19461 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
19462 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
19463 unsigned Opc = ret.first;
19464 bool NeedSplit = ret.second;
19466 if (Opc && NeedSplit) {
19467 unsigned NumElems = VT.getVectorNumElements();
19468 // Extract the LHS vectors
19469 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
19470 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
19472 // Extract the RHS vectors
19473 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
19474 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
19476 // Create min/max for each subvector
19477 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
19478 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
19480 // Merge the result
19481 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
19483 return DAG.getNode(Opc, DL, VT, LHS, RHS);
19486 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
19487 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19488 // Check if SETCC has already been promoted
19489 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
19490 // Check that condition value type matches vselect operand type
19493 assert(Cond.getValueType().isVector() &&
19494 "vector select expects a vector selector!");
19496 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
19497 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
19499 if (!TValIsAllOnes && !FValIsAllZeros) {
19500 // Try invert the condition if true value is not all 1s and false value
19502 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
19503 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
19505 if (TValIsAllZeros || FValIsAllOnes) {
19506 SDValue CC = Cond.getOperand(2);
19507 ISD::CondCode NewCC =
19508 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
19509 Cond.getOperand(0).getValueType().isInteger());
19510 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
19511 std::swap(LHS, RHS);
19512 TValIsAllOnes = FValIsAllOnes;
19513 FValIsAllZeros = TValIsAllZeros;
19517 if (TValIsAllOnes || FValIsAllZeros) {
19520 if (TValIsAllOnes && FValIsAllZeros)
19522 else if (TValIsAllOnes)
19523 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
19524 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
19525 else if (FValIsAllZeros)
19526 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
19527 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
19529 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
19533 // Try to fold this VSELECT into a MOVSS/MOVSD
19534 if (N->getOpcode() == ISD::VSELECT &&
19535 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
19536 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
19537 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
19538 bool CanFold = false;
19539 unsigned NumElems = Cond.getNumOperands();
19543 if (isZero(Cond.getOperand(0))) {
19546 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
19547 // fold (vselect <0,-1> -> (movsd A, B)
19548 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19549 CanFold = isAllOnes(Cond.getOperand(i));
19550 } else if (isAllOnes(Cond.getOperand(0))) {
19554 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
19555 // fold (vselect <-1,0> -> (movsd B, A)
19556 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19557 CanFold = isZero(Cond.getOperand(i));
19561 if (VT == MVT::v4i32 || VT == MVT::v4f32)
19562 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
19563 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
19566 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
19567 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
19568 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
19569 // (v2i64 (bitcast B)))))
19571 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
19572 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
19573 // (v2f64 (bitcast B)))))
19575 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
19576 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
19577 // (v2i64 (bitcast A)))))
19579 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
19580 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
19581 // (v2f64 (bitcast A)))))
19583 CanFold = (isZero(Cond.getOperand(0)) &&
19584 isZero(Cond.getOperand(1)) &&
19585 isAllOnes(Cond.getOperand(2)) &&
19586 isAllOnes(Cond.getOperand(3)));
19588 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
19589 isAllOnes(Cond.getOperand(1)) &&
19590 isZero(Cond.getOperand(2)) &&
19591 isZero(Cond.getOperand(3))) {
19593 std::swap(LHS, RHS);
19597 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
19598 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
19599 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
19600 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
19602 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
19608 // If we know that this node is legal then we know that it is going to be
19609 // matched by one of the SSE/AVX BLEND instructions. These instructions only
19610 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
19611 // to simplify previous instructions.
19612 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
19613 !DCI.isBeforeLegalize() &&
19614 // We explicitly check against v8i16 and v16i16 because, although
19615 // they're marked as Custom, they might only be legal when Cond is a
19616 // build_vector of constants. This will be taken care in a later
19618 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
19619 VT != MVT::v8i16)) {
19620 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
19622 // Don't optimize vector selects that map to mask-registers.
19626 // Check all uses of that condition operand to check whether it will be
19627 // consumed by non-BLEND instructions, which may depend on all bits are set
19629 for (SDNode::use_iterator I = Cond->use_begin(),
19630 E = Cond->use_end(); I != E; ++I)
19631 if (I->getOpcode() != ISD::VSELECT)
19632 // TODO: Add other opcodes eventually lowered into BLEND.
19635 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
19636 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
19638 APInt KnownZero, KnownOne;
19639 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
19640 DCI.isBeforeLegalizeOps());
19641 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
19642 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
19643 DCI.CommitTargetLoweringOpt(TLO);
19646 // We should generate an X86ISD::BLENDI from a vselect if its argument
19647 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
19648 // constants. This specific pattern gets generated when we split a
19649 // selector for a 512 bit vector in a machine without AVX512 (but with
19650 // 256-bit vectors), during legalization:
19652 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
19654 // Iff we find this pattern and the build_vectors are built from
19655 // constants, we translate the vselect into a shuffle_vector that we
19656 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
19657 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
19658 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
19659 if (Shuffle.getNode())
19666 // Check whether a boolean test is testing a boolean value generated by
19667 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
19670 // Simplify the following patterns:
19671 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
19672 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
19673 // to (Op EFLAGS Cond)
19675 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
19676 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
19677 // to (Op EFLAGS !Cond)
19679 // where Op could be BRCOND or CMOV.
19681 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
19682 // Quit if not CMP and SUB with its value result used.
19683 if (Cmp.getOpcode() != X86ISD::CMP &&
19684 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
19687 // Quit if not used as a boolean value.
19688 if (CC != X86::COND_E && CC != X86::COND_NE)
19691 // Check CMP operands. One of them should be 0 or 1 and the other should be
19692 // an SetCC or extended from it.
19693 SDValue Op1 = Cmp.getOperand(0);
19694 SDValue Op2 = Cmp.getOperand(1);
19697 const ConstantSDNode* C = nullptr;
19698 bool needOppositeCond = (CC == X86::COND_E);
19699 bool checkAgainstTrue = false; // Is it a comparison against 1?
19701 if ((C = dyn_cast<ConstantSDNode>(Op1)))
19703 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
19705 else // Quit if all operands are not constants.
19708 if (C->getZExtValue() == 1) {
19709 needOppositeCond = !needOppositeCond;
19710 checkAgainstTrue = true;
19711 } else if (C->getZExtValue() != 0)
19712 // Quit if the constant is neither 0 or 1.
19715 bool truncatedToBoolWithAnd = false;
19716 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
19717 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
19718 SetCC.getOpcode() == ISD::TRUNCATE ||
19719 SetCC.getOpcode() == ISD::AND) {
19720 if (SetCC.getOpcode() == ISD::AND) {
19722 ConstantSDNode *CS;
19723 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
19724 CS->getZExtValue() == 1)
19726 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
19727 CS->getZExtValue() == 1)
19731 SetCC = SetCC.getOperand(OpIdx);
19732 truncatedToBoolWithAnd = true;
19734 SetCC = SetCC.getOperand(0);
19737 switch (SetCC.getOpcode()) {
19738 case X86ISD::SETCC_CARRY:
19739 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
19740 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
19741 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
19742 // truncated to i1 using 'and'.
19743 if (checkAgainstTrue && !truncatedToBoolWithAnd)
19745 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
19746 "Invalid use of SETCC_CARRY!");
19748 case X86ISD::SETCC:
19749 // Set the condition code or opposite one if necessary.
19750 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
19751 if (needOppositeCond)
19752 CC = X86::GetOppositeBranchCondition(CC);
19753 return SetCC.getOperand(1);
19754 case X86ISD::CMOV: {
19755 // Check whether false/true value has canonical one, i.e. 0 or 1.
19756 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
19757 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
19758 // Quit if true value is not a constant.
19761 // Quit if false value is not a constant.
19763 SDValue Op = SetCC.getOperand(0);
19764 // Skip 'zext' or 'trunc' node.
19765 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
19766 Op.getOpcode() == ISD::TRUNCATE)
19767 Op = Op.getOperand(0);
19768 // A special case for rdrand/rdseed, where 0 is set if false cond is
19770 if ((Op.getOpcode() != X86ISD::RDRAND &&
19771 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
19774 // Quit if false value is not the constant 0 or 1.
19775 bool FValIsFalse = true;
19776 if (FVal && FVal->getZExtValue() != 0) {
19777 if (FVal->getZExtValue() != 1)
19779 // If FVal is 1, opposite cond is needed.
19780 needOppositeCond = !needOppositeCond;
19781 FValIsFalse = false;
19783 // Quit if TVal is not the constant opposite of FVal.
19784 if (FValIsFalse && TVal->getZExtValue() != 1)
19786 if (!FValIsFalse && TVal->getZExtValue() != 0)
19788 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
19789 if (needOppositeCond)
19790 CC = X86::GetOppositeBranchCondition(CC);
19791 return SetCC.getOperand(3);
19798 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
19799 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
19800 TargetLowering::DAGCombinerInfo &DCI,
19801 const X86Subtarget *Subtarget) {
19804 // If the flag operand isn't dead, don't touch this CMOV.
19805 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
19808 SDValue FalseOp = N->getOperand(0);
19809 SDValue TrueOp = N->getOperand(1);
19810 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
19811 SDValue Cond = N->getOperand(3);
19813 if (CC == X86::COND_E || CC == X86::COND_NE) {
19814 switch (Cond.getOpcode()) {
19818 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
19819 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
19820 return (CC == X86::COND_E) ? FalseOp : TrueOp;
19826 Flags = checkBoolTestSetCCCombine(Cond, CC);
19827 if (Flags.getNode() &&
19828 // Extra check as FCMOV only supports a subset of X86 cond.
19829 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
19830 SDValue Ops[] = { FalseOp, TrueOp,
19831 DAG.getConstant(CC, MVT::i8), Flags };
19832 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
19835 // If this is a select between two integer constants, try to do some
19836 // optimizations. Note that the operands are ordered the opposite of SELECT
19838 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
19839 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
19840 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
19841 // larger than FalseC (the false value).
19842 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
19843 CC = X86::GetOppositeBranchCondition(CC);
19844 std::swap(TrueC, FalseC);
19845 std::swap(TrueOp, FalseOp);
19848 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
19849 // This is efficient for any integer data type (including i8/i16) and
19851 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
19852 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19853 DAG.getConstant(CC, MVT::i8), Cond);
19855 // Zero extend the condition if needed.
19856 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
19858 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19859 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
19860 DAG.getConstant(ShAmt, MVT::i8));
19861 if (N->getNumValues() == 2) // Dead flag value?
19862 return DCI.CombineTo(N, Cond, SDValue());
19866 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
19867 // for any integer data type, including i8/i16.
19868 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19869 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19870 DAG.getConstant(CC, MVT::i8), Cond);
19872 // Zero extend the condition if needed.
19873 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19874 FalseC->getValueType(0), Cond);
19875 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19876 SDValue(FalseC, 0));
19878 if (N->getNumValues() == 2) // Dead flag value?
19879 return DCI.CombineTo(N, Cond, SDValue());
19883 // Optimize cases that will turn into an LEA instruction. This requires
19884 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
19885 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
19886 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
19887 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
19889 bool isFastMultiplier = false;
19891 switch ((unsigned char)Diff) {
19893 case 1: // result = add base, cond
19894 case 2: // result = lea base( , cond*2)
19895 case 3: // result = lea base(cond, cond*2)
19896 case 4: // result = lea base( , cond*4)
19897 case 5: // result = lea base(cond, cond*4)
19898 case 8: // result = lea base( , cond*8)
19899 case 9: // result = lea base(cond, cond*8)
19900 isFastMultiplier = true;
19905 if (isFastMultiplier) {
19906 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
19907 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19908 DAG.getConstant(CC, MVT::i8), Cond);
19909 // Zero extend the condition if needed.
19910 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
19912 // Scale the condition by the difference.
19914 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
19915 DAG.getConstant(Diff, Cond.getValueType()));
19917 // Add the base if non-zero.
19918 if (FalseC->getAPIntValue() != 0)
19919 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19920 SDValue(FalseC, 0));
19921 if (N->getNumValues() == 2) // Dead flag value?
19922 return DCI.CombineTo(N, Cond, SDValue());
19929 // Handle these cases:
19930 // (select (x != c), e, c) -> select (x != c), e, x),
19931 // (select (x == c), c, e) -> select (x == c), x, e)
19932 // where the c is an integer constant, and the "select" is the combination
19933 // of CMOV and CMP.
19935 // The rationale for this change is that the conditional-move from a constant
19936 // needs two instructions, however, conditional-move from a register needs
19937 // only one instruction.
19939 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
19940 // some instruction-combining opportunities. This opt needs to be
19941 // postponed as late as possible.
19943 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
19944 // the DCI.xxxx conditions are provided to postpone the optimization as
19945 // late as possible.
19947 ConstantSDNode *CmpAgainst = nullptr;
19948 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
19949 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
19950 !isa<ConstantSDNode>(Cond.getOperand(0))) {
19952 if (CC == X86::COND_NE &&
19953 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
19954 CC = X86::GetOppositeBranchCondition(CC);
19955 std::swap(TrueOp, FalseOp);
19958 if (CC == X86::COND_E &&
19959 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
19960 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
19961 DAG.getConstant(CC, MVT::i8), Cond };
19962 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
19970 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
19971 const X86Subtarget *Subtarget) {
19972 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
19974 default: return SDValue();
19975 // SSE/AVX/AVX2 blend intrinsics.
19976 case Intrinsic::x86_avx2_pblendvb:
19977 case Intrinsic::x86_avx2_pblendw:
19978 case Intrinsic::x86_avx2_pblendd_128:
19979 case Intrinsic::x86_avx2_pblendd_256:
19980 // Don't try to simplify this intrinsic if we don't have AVX2.
19981 if (!Subtarget->hasAVX2())
19984 case Intrinsic::x86_avx_blend_pd_256:
19985 case Intrinsic::x86_avx_blend_ps_256:
19986 case Intrinsic::x86_avx_blendv_pd_256:
19987 case Intrinsic::x86_avx_blendv_ps_256:
19988 // Don't try to simplify this intrinsic if we don't have AVX.
19989 if (!Subtarget->hasAVX())
19992 case Intrinsic::x86_sse41_pblendw:
19993 case Intrinsic::x86_sse41_blendpd:
19994 case Intrinsic::x86_sse41_blendps:
19995 case Intrinsic::x86_sse41_blendvps:
19996 case Intrinsic::x86_sse41_blendvpd:
19997 case Intrinsic::x86_sse41_pblendvb: {
19998 SDValue Op0 = N->getOperand(1);
19999 SDValue Op1 = N->getOperand(2);
20000 SDValue Mask = N->getOperand(3);
20002 // Don't try to simplify this intrinsic if we don't have SSE4.1.
20003 if (!Subtarget->hasSSE41())
20006 // fold (blend A, A, Mask) -> A
20009 // fold (blend A, B, allZeros) -> A
20010 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
20012 // fold (blend A, B, allOnes) -> B
20013 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
20016 // Simplify the case where the mask is a constant i32 value.
20017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
20018 if (C->isNullValue())
20020 if (C->isAllOnesValue())
20027 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
20028 case Intrinsic::x86_sse2_psrai_w:
20029 case Intrinsic::x86_sse2_psrai_d:
20030 case Intrinsic::x86_avx2_psrai_w:
20031 case Intrinsic::x86_avx2_psrai_d:
20032 case Intrinsic::x86_sse2_psra_w:
20033 case Intrinsic::x86_sse2_psra_d:
20034 case Intrinsic::x86_avx2_psra_w:
20035 case Intrinsic::x86_avx2_psra_d: {
20036 SDValue Op0 = N->getOperand(1);
20037 SDValue Op1 = N->getOperand(2);
20038 EVT VT = Op0.getValueType();
20039 assert(VT.isVector() && "Expected a vector type!");
20041 if (isa<BuildVectorSDNode>(Op1))
20042 Op1 = Op1.getOperand(0);
20044 if (!isa<ConstantSDNode>(Op1))
20047 EVT SVT = VT.getVectorElementType();
20048 unsigned SVTBits = SVT.getSizeInBits();
20050 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
20051 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
20052 uint64_t ShAmt = C.getZExtValue();
20054 // Don't try to convert this shift into a ISD::SRA if the shift
20055 // count is bigger than or equal to the element size.
20056 if (ShAmt >= SVTBits)
20059 // Trivial case: if the shift count is zero, then fold this
20060 // into the first operand.
20064 // Replace this packed shift intrinsic with a target independent
20066 SDValue Splat = DAG.getConstant(C, VT);
20067 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
20072 /// PerformMulCombine - Optimize a single multiply with constant into two
20073 /// in order to implement it with two cheaper instructions, e.g.
20074 /// LEA + SHL, LEA + LEA.
20075 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
20076 TargetLowering::DAGCombinerInfo &DCI) {
20077 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
20080 EVT VT = N->getValueType(0);
20081 if (VT != MVT::i64)
20084 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
20087 uint64_t MulAmt = C->getZExtValue();
20088 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
20091 uint64_t MulAmt1 = 0;
20092 uint64_t MulAmt2 = 0;
20093 if ((MulAmt % 9) == 0) {
20095 MulAmt2 = MulAmt / 9;
20096 } else if ((MulAmt % 5) == 0) {
20098 MulAmt2 = MulAmt / 5;
20099 } else if ((MulAmt % 3) == 0) {
20101 MulAmt2 = MulAmt / 3;
20104 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
20107 if (isPowerOf2_64(MulAmt2) &&
20108 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
20109 // If second multiplifer is pow2, issue it first. We want the multiply by
20110 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
20112 std::swap(MulAmt1, MulAmt2);
20115 if (isPowerOf2_64(MulAmt1))
20116 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
20117 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
20119 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
20120 DAG.getConstant(MulAmt1, VT));
20122 if (isPowerOf2_64(MulAmt2))
20123 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
20124 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
20126 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
20127 DAG.getConstant(MulAmt2, VT));
20129 // Do not add new nodes to DAG combiner worklist.
20130 DCI.CombineTo(N, NewMul, false);
20135 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
20136 SDValue N0 = N->getOperand(0);
20137 SDValue N1 = N->getOperand(1);
20138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
20139 EVT VT = N0.getValueType();
20141 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
20142 // since the result of setcc_c is all zero's or all ones.
20143 if (VT.isInteger() && !VT.isVector() &&
20144 N1C && N0.getOpcode() == ISD::AND &&
20145 N0.getOperand(1).getOpcode() == ISD::Constant) {
20146 SDValue N00 = N0.getOperand(0);
20147 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
20148 ((N00.getOpcode() == ISD::ANY_EXTEND ||
20149 N00.getOpcode() == ISD::ZERO_EXTEND) &&
20150 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
20151 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
20152 APInt ShAmt = N1C->getAPIntValue();
20153 Mask = Mask.shl(ShAmt);
20155 return DAG.getNode(ISD::AND, SDLoc(N), VT,
20156 N00, DAG.getConstant(Mask, VT));
20160 // Hardware support for vector shifts is sparse which makes us scalarize the
20161 // vector operations in many cases. Also, on sandybridge ADD is faster than
20163 // (shl V, 1) -> add V,V
20164 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
20165 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
20166 assert(N0.getValueType().isVector() && "Invalid vector shift type");
20167 // We shift all of the values by one. In many cases we do not have
20168 // hardware support for this operation. This is better expressed as an ADD
20170 if (N1SplatC->getZExtValue() == 1)
20171 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
20177 /// \brief Returns a vector of 0s if the node in input is a vector logical
20178 /// shift by a constant amount which is known to be bigger than or equal
20179 /// to the vector element size in bits.
20180 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
20181 const X86Subtarget *Subtarget) {
20182 EVT VT = N->getValueType(0);
20184 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
20185 (!Subtarget->hasInt256() ||
20186 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
20189 SDValue Amt = N->getOperand(1);
20191 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
20192 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
20193 APInt ShiftAmt = AmtSplat->getAPIntValue();
20194 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
20196 // SSE2/AVX2 logical shifts always return a vector of 0s
20197 // if the shift amount is bigger than or equal to
20198 // the element size. The constant shift amount will be
20199 // encoded as a 8-bit immediate.
20200 if (ShiftAmt.trunc(8).uge(MaxAmount))
20201 return getZeroVector(VT, Subtarget, DAG, DL);
20207 /// PerformShiftCombine - Combine shifts.
20208 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
20209 TargetLowering::DAGCombinerInfo &DCI,
20210 const X86Subtarget *Subtarget) {
20211 if (N->getOpcode() == ISD::SHL) {
20212 SDValue V = PerformSHLCombine(N, DAG);
20213 if (V.getNode()) return V;
20216 if (N->getOpcode() != ISD::SRA) {
20217 // Try to fold this logical shift into a zero vector.
20218 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
20219 if (V.getNode()) return V;
20225 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
20226 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
20227 // and friends. Likewise for OR -> CMPNEQSS.
20228 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
20229 TargetLowering::DAGCombinerInfo &DCI,
20230 const X86Subtarget *Subtarget) {
20233 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
20234 // we're requiring SSE2 for both.
20235 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
20236 SDValue N0 = N->getOperand(0);
20237 SDValue N1 = N->getOperand(1);
20238 SDValue CMP0 = N0->getOperand(1);
20239 SDValue CMP1 = N1->getOperand(1);
20242 // The SETCCs should both refer to the same CMP.
20243 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
20246 SDValue CMP00 = CMP0->getOperand(0);
20247 SDValue CMP01 = CMP0->getOperand(1);
20248 EVT VT = CMP00.getValueType();
20250 if (VT == MVT::f32 || VT == MVT::f64) {
20251 bool ExpectingFlags = false;
20252 // Check for any users that want flags:
20253 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
20254 !ExpectingFlags && UI != UE; ++UI)
20255 switch (UI->getOpcode()) {
20260 ExpectingFlags = true;
20262 case ISD::CopyToReg:
20263 case ISD::SIGN_EXTEND:
20264 case ISD::ZERO_EXTEND:
20265 case ISD::ANY_EXTEND:
20269 if (!ExpectingFlags) {
20270 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
20271 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
20273 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
20274 X86::CondCode tmp = cc0;
20279 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
20280 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
20281 // FIXME: need symbolic constants for these magic numbers.
20282 // See X86ATTInstPrinter.cpp:printSSECC().
20283 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
20284 if (Subtarget->hasAVX512()) {
20285 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
20286 CMP01, DAG.getConstant(x86cc, MVT::i8));
20287 if (N->getValueType(0) != MVT::i1)
20288 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
20292 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
20293 CMP00.getValueType(), CMP00, CMP01,
20294 DAG.getConstant(x86cc, MVT::i8));
20296 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
20297 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
20299 if (is64BitFP && !Subtarget->is64Bit()) {
20300 // On a 32-bit target, we cannot bitcast the 64-bit float to a
20301 // 64-bit integer, since that's not a legal type. Since
20302 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
20303 // bits, but can do this little dance to extract the lowest 32 bits
20304 // and work with those going forward.
20305 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
20307 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
20309 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
20310 Vector32, DAG.getIntPtrConstant(0));
20314 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
20315 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
20316 DAG.getConstant(1, IntVT));
20317 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
20318 return OneBitOfTruth;
20326 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
20327 /// so it can be folded inside ANDNP.
20328 static bool CanFoldXORWithAllOnes(const SDNode *N) {
20329 EVT VT = N->getValueType(0);
20331 // Match direct AllOnes for 128 and 256-bit vectors
20332 if (ISD::isBuildVectorAllOnes(N))
20335 // Look through a bit convert.
20336 if (N->getOpcode() == ISD::BITCAST)
20337 N = N->getOperand(0).getNode();
20339 // Sometimes the operand may come from a insert_subvector building a 256-bit
20341 if (VT.is256BitVector() &&
20342 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
20343 SDValue V1 = N->getOperand(0);
20344 SDValue V2 = N->getOperand(1);
20346 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
20347 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
20348 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
20349 ISD::isBuildVectorAllOnes(V2.getNode()))
20356 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
20357 // register. In most cases we actually compare or select YMM-sized registers
20358 // and mixing the two types creates horrible code. This method optimizes
20359 // some of the transition sequences.
20360 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
20361 TargetLowering::DAGCombinerInfo &DCI,
20362 const X86Subtarget *Subtarget) {
20363 EVT VT = N->getValueType(0);
20364 if (!VT.is256BitVector())
20367 assert((N->getOpcode() == ISD::ANY_EXTEND ||
20368 N->getOpcode() == ISD::ZERO_EXTEND ||
20369 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
20371 SDValue Narrow = N->getOperand(0);
20372 EVT NarrowVT = Narrow->getValueType(0);
20373 if (!NarrowVT.is128BitVector())
20376 if (Narrow->getOpcode() != ISD::XOR &&
20377 Narrow->getOpcode() != ISD::AND &&
20378 Narrow->getOpcode() != ISD::OR)
20381 SDValue N0 = Narrow->getOperand(0);
20382 SDValue N1 = Narrow->getOperand(1);
20385 // The Left side has to be a trunc.
20386 if (N0.getOpcode() != ISD::TRUNCATE)
20389 // The type of the truncated inputs.
20390 EVT WideVT = N0->getOperand(0)->getValueType(0);
20394 // The right side has to be a 'trunc' or a constant vector.
20395 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
20396 ConstantSDNode *RHSConstSplat = nullptr;
20397 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
20398 RHSConstSplat = RHSBV->getConstantSplatNode();
20399 if (!RHSTrunc && !RHSConstSplat)
20402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20404 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
20407 // Set N0 and N1 to hold the inputs to the new wide operation.
20408 N0 = N0->getOperand(0);
20409 if (RHSConstSplat) {
20410 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
20411 SDValue(RHSConstSplat, 0));
20412 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
20413 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
20414 } else if (RHSTrunc) {
20415 N1 = N1->getOperand(0);
20418 // Generate the wide operation.
20419 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
20420 unsigned Opcode = N->getOpcode();
20422 case ISD::ANY_EXTEND:
20424 case ISD::ZERO_EXTEND: {
20425 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
20426 APInt Mask = APInt::getAllOnesValue(InBits);
20427 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
20428 return DAG.getNode(ISD::AND, DL, VT,
20429 Op, DAG.getConstant(Mask, VT));
20431 case ISD::SIGN_EXTEND:
20432 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
20433 Op, DAG.getValueType(NarrowVT));
20435 llvm_unreachable("Unexpected opcode");
20439 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
20440 TargetLowering::DAGCombinerInfo &DCI,
20441 const X86Subtarget *Subtarget) {
20442 EVT VT = N->getValueType(0);
20443 if (DCI.isBeforeLegalizeOps())
20446 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20450 // Create BEXTR instructions
20451 // BEXTR is ((X >> imm) & (2**size-1))
20452 if (VT == MVT::i32 || VT == MVT::i64) {
20453 SDValue N0 = N->getOperand(0);
20454 SDValue N1 = N->getOperand(1);
20457 // Check for BEXTR.
20458 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
20459 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
20460 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
20461 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
20462 if (MaskNode && ShiftNode) {
20463 uint64_t Mask = MaskNode->getZExtValue();
20464 uint64_t Shift = ShiftNode->getZExtValue();
20465 if (isMask_64(Mask)) {
20466 uint64_t MaskSize = CountPopulation_64(Mask);
20467 if (Shift + MaskSize <= VT.getSizeInBits())
20468 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
20469 DAG.getConstant(Shift | (MaskSize << 8), VT));
20477 // Want to form ANDNP nodes:
20478 // 1) In the hopes of then easily combining them with OR and AND nodes
20479 // to form PBLEND/PSIGN.
20480 // 2) To match ANDN packed intrinsics
20481 if (VT != MVT::v2i64 && VT != MVT::v4i64)
20484 SDValue N0 = N->getOperand(0);
20485 SDValue N1 = N->getOperand(1);
20488 // Check LHS for vnot
20489 if (N0.getOpcode() == ISD::XOR &&
20490 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
20491 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
20492 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
20494 // Check RHS for vnot
20495 if (N1.getOpcode() == ISD::XOR &&
20496 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
20497 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
20498 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
20503 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
20504 TargetLowering::DAGCombinerInfo &DCI,
20505 const X86Subtarget *Subtarget) {
20506 if (DCI.isBeforeLegalizeOps())
20509 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20513 SDValue N0 = N->getOperand(0);
20514 SDValue N1 = N->getOperand(1);
20515 EVT VT = N->getValueType(0);
20517 // look for psign/blend
20518 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
20519 if (!Subtarget->hasSSSE3() ||
20520 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
20523 // Canonicalize pandn to RHS
20524 if (N0.getOpcode() == X86ISD::ANDNP)
20526 // or (and (m, y), (pandn m, x))
20527 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
20528 SDValue Mask = N1.getOperand(0);
20529 SDValue X = N1.getOperand(1);
20531 if (N0.getOperand(0) == Mask)
20532 Y = N0.getOperand(1);
20533 if (N0.getOperand(1) == Mask)
20534 Y = N0.getOperand(0);
20536 // Check to see if the mask appeared in both the AND and ANDNP and
20540 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
20541 // Look through mask bitcast.
20542 if (Mask.getOpcode() == ISD::BITCAST)
20543 Mask = Mask.getOperand(0);
20544 if (X.getOpcode() == ISD::BITCAST)
20545 X = X.getOperand(0);
20546 if (Y.getOpcode() == ISD::BITCAST)
20547 Y = Y.getOperand(0);
20549 EVT MaskVT = Mask.getValueType();
20551 // Validate that the Mask operand is a vector sra node.
20552 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
20553 // there is no psrai.b
20554 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
20555 unsigned SraAmt = ~0;
20556 if (Mask.getOpcode() == ISD::SRA) {
20557 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
20558 if (auto *AmtConst = AmtBV->getConstantSplatNode())
20559 SraAmt = AmtConst->getZExtValue();
20560 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
20561 SDValue SraC = Mask.getOperand(1);
20562 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
20564 if ((SraAmt + 1) != EltBits)
20569 // Now we know we at least have a plendvb with the mask val. See if
20570 // we can form a psignb/w/d.
20571 // psign = x.type == y.type == mask.type && y = sub(0, x);
20572 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
20573 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
20574 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
20575 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
20576 "Unsupported VT for PSIGN");
20577 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
20578 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20580 // PBLENDVB only available on SSE 4.1
20581 if (!Subtarget->hasSSE41())
20584 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
20586 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
20587 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
20588 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
20589 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
20590 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20594 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
20597 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
20598 MachineFunction &MF = DAG.getMachineFunction();
20599 bool OptForSize = MF.getFunction()->getAttributes().
20600 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
20602 // SHLD/SHRD instructions have lower register pressure, but on some
20603 // platforms they have higher latency than the equivalent
20604 // series of shifts/or that would otherwise be generated.
20605 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
20606 // have higher latencies and we are not optimizing for size.
20607 if (!OptForSize && Subtarget->isSHLDSlow())
20610 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
20612 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
20614 if (!N0.hasOneUse() || !N1.hasOneUse())
20617 SDValue ShAmt0 = N0.getOperand(1);
20618 if (ShAmt0.getValueType() != MVT::i8)
20620 SDValue ShAmt1 = N1.getOperand(1);
20621 if (ShAmt1.getValueType() != MVT::i8)
20623 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
20624 ShAmt0 = ShAmt0.getOperand(0);
20625 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
20626 ShAmt1 = ShAmt1.getOperand(0);
20629 unsigned Opc = X86ISD::SHLD;
20630 SDValue Op0 = N0.getOperand(0);
20631 SDValue Op1 = N1.getOperand(0);
20632 if (ShAmt0.getOpcode() == ISD::SUB) {
20633 Opc = X86ISD::SHRD;
20634 std::swap(Op0, Op1);
20635 std::swap(ShAmt0, ShAmt1);
20638 unsigned Bits = VT.getSizeInBits();
20639 if (ShAmt1.getOpcode() == ISD::SUB) {
20640 SDValue Sum = ShAmt1.getOperand(0);
20641 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
20642 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
20643 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
20644 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
20645 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
20646 return DAG.getNode(Opc, DL, VT,
20648 DAG.getNode(ISD::TRUNCATE, DL,
20651 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
20652 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
20654 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
20655 return DAG.getNode(Opc, DL, VT,
20656 N0.getOperand(0), N1.getOperand(0),
20657 DAG.getNode(ISD::TRUNCATE, DL,
20664 // Generate NEG and CMOV for integer abs.
20665 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
20666 EVT VT = N->getValueType(0);
20668 // Since X86 does not have CMOV for 8-bit integer, we don't convert
20669 // 8-bit integer abs to NEG and CMOV.
20670 if (VT.isInteger() && VT.getSizeInBits() == 8)
20673 SDValue N0 = N->getOperand(0);
20674 SDValue N1 = N->getOperand(1);
20677 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
20678 // and change it to SUB and CMOV.
20679 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
20680 N0.getOpcode() == ISD::ADD &&
20681 N0.getOperand(1) == N1 &&
20682 N1.getOpcode() == ISD::SRA &&
20683 N1.getOperand(0) == N0.getOperand(0))
20684 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
20685 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
20686 // Generate SUB & CMOV.
20687 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
20688 DAG.getConstant(0, VT), N0.getOperand(0));
20690 SDValue Ops[] = { N0.getOperand(0), Neg,
20691 DAG.getConstant(X86::COND_GE, MVT::i8),
20692 SDValue(Neg.getNode(), 1) };
20693 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
20698 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
20699 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
20700 TargetLowering::DAGCombinerInfo &DCI,
20701 const X86Subtarget *Subtarget) {
20702 if (DCI.isBeforeLegalizeOps())
20705 if (Subtarget->hasCMov()) {
20706 SDValue RV = performIntegerAbsCombine(N, DAG);
20714 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
20715 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
20716 TargetLowering::DAGCombinerInfo &DCI,
20717 const X86Subtarget *Subtarget) {
20718 LoadSDNode *Ld = cast<LoadSDNode>(N);
20719 EVT RegVT = Ld->getValueType(0);
20720 EVT MemVT = Ld->getMemoryVT();
20722 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20723 unsigned RegSz = RegVT.getSizeInBits();
20725 // On Sandybridge unaligned 256bit loads are inefficient.
20726 ISD::LoadExtType Ext = Ld->getExtensionType();
20727 unsigned Alignment = Ld->getAlignment();
20728 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
20729 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
20730 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
20731 unsigned NumElems = RegVT.getVectorNumElements();
20735 SDValue Ptr = Ld->getBasePtr();
20736 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
20738 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20740 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20741 Ld->getPointerInfo(), Ld->isVolatile(),
20742 Ld->isNonTemporal(), Ld->isInvariant(),
20744 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20745 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20746 Ld->getPointerInfo(), Ld->isVolatile(),
20747 Ld->isNonTemporal(), Ld->isInvariant(),
20748 std::min(16U, Alignment));
20749 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20751 Load2.getValue(1));
20753 SDValue NewVec = DAG.getUNDEF(RegVT);
20754 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
20755 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
20756 return DCI.CombineTo(N, NewVec, TF, true);
20759 // If this is a vector EXT Load then attempt to optimize it using a
20760 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
20761 // expansion is still better than scalar code.
20762 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
20763 // emit a shuffle and a arithmetic shift.
20764 // TODO: It is possible to support ZExt by zeroing the undef values
20765 // during the shuffle phase or after the shuffle.
20766 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
20767 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
20768 assert(MemVT != RegVT && "Cannot extend to the same type");
20769 assert(MemVT.isVector() && "Must load a vector from memory");
20771 unsigned NumElems = RegVT.getVectorNumElements();
20772 unsigned MemSz = MemVT.getSizeInBits();
20773 assert(RegSz > MemSz && "Register size must be greater than the mem size");
20775 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
20778 // All sizes must be a power of two.
20779 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
20782 // Attempt to load the original value using scalar loads.
20783 // Find the largest scalar type that divides the total loaded size.
20784 MVT SclrLoadTy = MVT::i8;
20785 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
20786 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
20787 MVT Tp = (MVT::SimpleValueType)tp;
20788 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
20793 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
20794 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
20796 SclrLoadTy = MVT::f64;
20798 // Calculate the number of scalar loads that we need to perform
20799 // in order to load our vector from memory.
20800 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
20801 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
20804 unsigned loadRegZize = RegSz;
20805 if (Ext == ISD::SEXTLOAD && RegSz == 256)
20808 // Represent our vector as a sequence of elements which are the
20809 // largest scalar that we can load.
20810 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
20811 loadRegZize/SclrLoadTy.getSizeInBits());
20813 // Represent the data using the same element type that is stored in
20814 // memory. In practice, we ''widen'' MemVT.
20816 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20817 loadRegZize/MemVT.getScalarType().getSizeInBits());
20819 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
20820 "Invalid vector type");
20822 // We can't shuffle using an illegal type.
20823 if (!TLI.isTypeLegal(WideVecVT))
20826 SmallVector<SDValue, 8> Chains;
20827 SDValue Ptr = Ld->getBasePtr();
20828 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
20829 TLI.getPointerTy());
20830 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
20832 for (unsigned i = 0; i < NumLoads; ++i) {
20833 // Perform a single load.
20834 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
20835 Ptr, Ld->getPointerInfo(),
20836 Ld->isVolatile(), Ld->isNonTemporal(),
20837 Ld->isInvariant(), Ld->getAlignment());
20838 Chains.push_back(ScalarLoad.getValue(1));
20839 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
20840 // another round of DAGCombining.
20842 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
20844 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
20845 ScalarLoad, DAG.getIntPtrConstant(i));
20847 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20850 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
20852 // Bitcast the loaded value to a vector of the original element type, in
20853 // the size of the target vector type.
20854 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
20855 unsigned SizeRatio = RegSz/MemSz;
20857 if (Ext == ISD::SEXTLOAD) {
20858 // If we have SSE4.1 we can directly emit a VSEXT node.
20859 if (Subtarget->hasSSE41()) {
20860 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
20861 return DCI.CombineTo(N, Sext, TF, true);
20864 // Otherwise we'll shuffle the small elements in the high bits of the
20865 // larger type and perform an arithmetic shift. If the shift is not legal
20866 // it's better to scalarize.
20867 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
20870 // Redistribute the loaded elements into the different locations.
20871 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20872 for (unsigned i = 0; i != NumElems; ++i)
20873 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
20875 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
20876 DAG.getUNDEF(WideVecVT),
20879 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
20881 // Build the arithmetic shift.
20882 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
20883 MemVT.getVectorElementType().getSizeInBits();
20884 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
20885 DAG.getConstant(Amt, RegVT));
20887 return DCI.CombineTo(N, Shuff, TF, true);
20890 // Redistribute the loaded elements into the different locations.
20891 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20892 for (unsigned i = 0; i != NumElems; ++i)
20893 ShuffleVec[i*SizeRatio] = i;
20895 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
20896 DAG.getUNDEF(WideVecVT),
20899 // Bitcast to the requested type.
20900 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
20901 // Replace the original load with the new sequence
20902 // and return the new chain.
20903 return DCI.CombineTo(N, Shuff, TF, true);
20909 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
20910 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
20911 const X86Subtarget *Subtarget) {
20912 StoreSDNode *St = cast<StoreSDNode>(N);
20913 EVT VT = St->getValue().getValueType();
20914 EVT StVT = St->getMemoryVT();
20916 SDValue StoredVal = St->getOperand(1);
20917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20919 // If we are saving a concatenation of two XMM registers, perform two stores.
20920 // On Sandy Bridge, 256-bit memory operations are executed by two
20921 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
20922 // memory operation.
20923 unsigned Alignment = St->getAlignment();
20924 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
20925 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
20926 StVT == VT && !IsAligned) {
20927 unsigned NumElems = VT.getVectorNumElements();
20931 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
20932 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
20934 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
20935 SDValue Ptr0 = St->getBasePtr();
20936 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
20938 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
20939 St->getPointerInfo(), St->isVolatile(),
20940 St->isNonTemporal(), Alignment);
20941 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
20942 St->getPointerInfo(), St->isVolatile(),
20943 St->isNonTemporal(),
20944 std::min(16U, Alignment));
20945 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
20948 // Optimize trunc store (of multiple scalars) to shuffle and store.
20949 // First, pack all of the elements in one place. Next, store to memory
20950 // in fewer chunks.
20951 if (St->isTruncatingStore() && VT.isVector()) {
20952 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20953 unsigned NumElems = VT.getVectorNumElements();
20954 assert(StVT != VT && "Cannot truncate to the same type");
20955 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
20956 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
20958 // From, To sizes and ElemCount must be pow of two
20959 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
20960 // We are going to use the original vector elt for storing.
20961 // Accumulated smaller vector elements must be a multiple of the store size.
20962 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
20964 unsigned SizeRatio = FromSz / ToSz;
20966 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
20968 // Create a type on which we perform the shuffle
20969 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
20970 StVT.getScalarType(), NumElems*SizeRatio);
20972 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
20974 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
20975 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20976 for (unsigned i = 0; i != NumElems; ++i)
20977 ShuffleVec[i] = i * SizeRatio;
20979 // Can't shuffle using an illegal type.
20980 if (!TLI.isTypeLegal(WideVecVT))
20983 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
20984 DAG.getUNDEF(WideVecVT),
20986 // At this point all of the data is stored at the bottom of the
20987 // register. We now need to save it to mem.
20989 // Find the largest store unit
20990 MVT StoreType = MVT::i8;
20991 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
20992 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
20993 MVT Tp = (MVT::SimpleValueType)tp;
20994 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
20998 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
20999 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
21000 (64 <= NumElems * ToSz))
21001 StoreType = MVT::f64;
21003 // Bitcast the original vector into a vector of store-size units
21004 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21005 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21006 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21007 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21008 SmallVector<SDValue, 8> Chains;
21009 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21010 TLI.getPointerTy());
21011 SDValue Ptr = St->getBasePtr();
21013 // Perform one or more big stores into memory.
21014 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21015 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21016 StoreType, ShuffWide,
21017 DAG.getIntPtrConstant(i));
21018 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21019 St->getPointerInfo(), St->isVolatile(),
21020 St->isNonTemporal(), St->getAlignment());
21021 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21022 Chains.push_back(Ch);
21025 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21028 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21029 // the FP state in cases where an emms may be missing.
21030 // A preferable solution to the general problem is to figure out the right
21031 // places to insert EMMS. This qualifies as a quick hack.
21033 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21034 if (VT.getSizeInBits() != 64)
21037 const Function *F = DAG.getMachineFunction().getFunction();
21038 bool NoImplicitFloatOps = F->getAttributes().
21039 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21040 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21041 && Subtarget->hasSSE2();
21042 if ((VT.isVector() ||
21043 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21044 isa<LoadSDNode>(St->getValue()) &&
21045 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21046 St->getChain().hasOneUse() && !St->isVolatile()) {
21047 SDNode* LdVal = St->getValue().getNode();
21048 LoadSDNode *Ld = nullptr;
21049 int TokenFactorIndex = -1;
21050 SmallVector<SDValue, 8> Ops;
21051 SDNode* ChainVal = St->getChain().getNode();
21052 // Must be a store of a load. We currently handle two cases: the load
21053 // is a direct child, and it's under an intervening TokenFactor. It is
21054 // possible to dig deeper under nested TokenFactors.
21055 if (ChainVal == LdVal)
21056 Ld = cast<LoadSDNode>(St->getChain());
21057 else if (St->getValue().hasOneUse() &&
21058 ChainVal->getOpcode() == ISD::TokenFactor) {
21059 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21060 if (ChainVal->getOperand(i).getNode() == LdVal) {
21061 TokenFactorIndex = i;
21062 Ld = cast<LoadSDNode>(St->getValue());
21064 Ops.push_back(ChainVal->getOperand(i));
21068 if (!Ld || !ISD::isNormalLoad(Ld))
21071 // If this is not the MMX case, i.e. we are just turning i64 load/store
21072 // into f64 load/store, avoid the transformation if there are multiple
21073 // uses of the loaded value.
21074 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21079 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21080 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
21082 if (Subtarget->is64Bit() || F64IsLegal) {
21083 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
21084 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
21085 Ld->getPointerInfo(), Ld->isVolatile(),
21086 Ld->isNonTemporal(), Ld->isInvariant(),
21087 Ld->getAlignment());
21088 SDValue NewChain = NewLd.getValue(1);
21089 if (TokenFactorIndex != -1) {
21090 Ops.push_back(NewChain);
21091 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21093 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
21094 St->getPointerInfo(),
21095 St->isVolatile(), St->isNonTemporal(),
21096 St->getAlignment());
21099 // Otherwise, lower to two pairs of 32-bit loads / stores.
21100 SDValue LoAddr = Ld->getBasePtr();
21101 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
21102 DAG.getConstant(4, MVT::i32));
21104 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
21105 Ld->getPointerInfo(),
21106 Ld->isVolatile(), Ld->isNonTemporal(),
21107 Ld->isInvariant(), Ld->getAlignment());
21108 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
21109 Ld->getPointerInfo().getWithOffset(4),
21110 Ld->isVolatile(), Ld->isNonTemporal(),
21112 MinAlign(Ld->getAlignment(), 4));
21114 SDValue NewChain = LoLd.getValue(1);
21115 if (TokenFactorIndex != -1) {
21116 Ops.push_back(LoLd);
21117 Ops.push_back(HiLd);
21118 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21121 LoAddr = St->getBasePtr();
21122 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
21123 DAG.getConstant(4, MVT::i32));
21125 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
21126 St->getPointerInfo(),
21127 St->isVolatile(), St->isNonTemporal(),
21128 St->getAlignment());
21129 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
21130 St->getPointerInfo().getWithOffset(4),
21132 St->isNonTemporal(),
21133 MinAlign(St->getAlignment(), 4));
21134 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
21139 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
21140 /// and return the operands for the horizontal operation in LHS and RHS. A
21141 /// horizontal operation performs the binary operation on successive elements
21142 /// of its first operand, then on successive elements of its second operand,
21143 /// returning the resulting values in a vector. For example, if
21144 /// A = < float a0, float a1, float a2, float a3 >
21146 /// B = < float b0, float b1, float b2, float b3 >
21147 /// then the result of doing a horizontal operation on A and B is
21148 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
21149 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21150 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21151 /// set to A, RHS to B, and the routine returns 'true'.
21152 /// Note that the binary operation should have the property that if one of the
21153 /// operands is UNDEF then the result is UNDEF.
21154 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21155 // Look for the following pattern: if
21156 // A = < float a0, float a1, float a2, float a3 >
21157 // B = < float b0, float b1, float b2, float b3 >
21159 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21160 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
21161 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21162 // which is A horizontal-op B.
21164 // At least one of the operands should be a vector shuffle.
21165 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21166 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
21169 MVT VT = LHS.getSimpleValueType();
21171 assert((VT.is128BitVector() || VT.is256BitVector()) &&
21172 "Unsupported vector type for horizontal add/sub");
21174 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
21175 // operate independently on 128-bit lanes.
21176 unsigned NumElts = VT.getVectorNumElements();
21177 unsigned NumLanes = VT.getSizeInBits()/128;
21178 unsigned NumLaneElts = NumElts / NumLanes;
21179 assert((NumLaneElts % 2 == 0) &&
21180 "Vector type should have an even number of elements in each lane");
21181 unsigned HalfLaneElts = NumLaneElts/2;
21183 // View LHS in the form
21184 // LHS = VECTOR_SHUFFLE A, B, LMask
21185 // If LHS is not a shuffle then pretend it is the shuffle
21186 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21187 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
21190 SmallVector<int, 16> LMask(NumElts);
21191 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21192 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21193 A = LHS.getOperand(0);
21194 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21195 B = LHS.getOperand(1);
21196 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21197 std::copy(Mask.begin(), Mask.end(), LMask.begin());
21199 if (LHS.getOpcode() != ISD::UNDEF)
21201 for (unsigned i = 0; i != NumElts; ++i)
21205 // Likewise, view RHS in the form
21206 // RHS = VECTOR_SHUFFLE C, D, RMask
21208 SmallVector<int, 16> RMask(NumElts);
21209 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21210 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
21211 C = RHS.getOperand(0);
21212 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
21213 D = RHS.getOperand(1);
21214 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
21215 std::copy(Mask.begin(), Mask.end(), RMask.begin());
21217 if (RHS.getOpcode() != ISD::UNDEF)
21219 for (unsigned i = 0; i != NumElts; ++i)
21223 // Check that the shuffles are both shuffling the same vectors.
21224 if (!(A == C && B == D) && !(A == D && B == C))
21227 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
21228 if (!A.getNode() && !B.getNode())
21231 // If A and B occur in reverse order in RHS, then "swap" them (which means
21232 // rewriting the mask).
21234 CommuteVectorShuffleMask(RMask, NumElts);
21236 // At this point LHS and RHS are equivalent to
21237 // LHS = VECTOR_SHUFFLE A, B, LMask
21238 // RHS = VECTOR_SHUFFLE A, B, RMask
21239 // Check that the masks correspond to performing a horizontal operation.
21240 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
21241 for (unsigned i = 0; i != NumLaneElts; ++i) {
21242 int LIdx = LMask[i+l], RIdx = RMask[i+l];
21244 // Ignore any UNDEF components.
21245 if (LIdx < 0 || RIdx < 0 ||
21246 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
21247 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
21250 // Check that successive elements are being operated on. If not, this is
21251 // not a horizontal operation.
21252 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
21253 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
21254 if (!(LIdx == Index && RIdx == Index + 1) &&
21255 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
21260 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
21261 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
21265 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
21266 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
21267 const X86Subtarget *Subtarget) {
21268 EVT VT = N->getValueType(0);
21269 SDValue LHS = N->getOperand(0);
21270 SDValue RHS = N->getOperand(1);
21272 // Try to synthesize horizontal adds from adds of shuffles.
21273 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21274 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21275 isHorizontalBinOp(LHS, RHS, true))
21276 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
21280 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
21281 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
21282 const X86Subtarget *Subtarget) {
21283 EVT VT = N->getValueType(0);
21284 SDValue LHS = N->getOperand(0);
21285 SDValue RHS = N->getOperand(1);
21287 // Try to synthesize horizontal subs from subs of shuffles.
21288 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21289 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21290 isHorizontalBinOp(LHS, RHS, false))
21291 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
21295 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
21296 /// X86ISD::FXOR nodes.
21297 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
21298 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
21299 // F[X]OR(0.0, x) -> x
21300 // F[X]OR(x, 0.0) -> x
21301 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21302 if (C->getValueAPF().isPosZero())
21303 return N->getOperand(1);
21304 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21305 if (C->getValueAPF().isPosZero())
21306 return N->getOperand(0);
21310 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
21311 /// X86ISD::FMAX nodes.
21312 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
21313 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
21315 // Only perform optimizations if UnsafeMath is used.
21316 if (!DAG.getTarget().Options.UnsafeFPMath)
21319 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
21320 // into FMINC and FMAXC, which are Commutative operations.
21321 unsigned NewOp = 0;
21322 switch (N->getOpcode()) {
21323 default: llvm_unreachable("unknown opcode");
21324 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
21325 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
21328 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
21329 N->getOperand(0), N->getOperand(1));
21332 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
21333 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
21334 // FAND(0.0, x) -> 0.0
21335 // FAND(x, 0.0) -> 0.0
21336 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21337 if (C->getValueAPF().isPosZero())
21338 return N->getOperand(0);
21339 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21340 if (C->getValueAPF().isPosZero())
21341 return N->getOperand(1);
21345 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
21346 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
21347 // FANDN(x, 0.0) -> 0.0
21348 // FANDN(0.0, x) -> x
21349 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21350 if (C->getValueAPF().isPosZero())
21351 return N->getOperand(1);
21352 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21353 if (C->getValueAPF().isPosZero())
21354 return N->getOperand(1);
21358 static SDValue PerformBTCombine(SDNode *N,
21360 TargetLowering::DAGCombinerInfo &DCI) {
21361 // BT ignores high bits in the bit index operand.
21362 SDValue Op1 = N->getOperand(1);
21363 if (Op1.hasOneUse()) {
21364 unsigned BitWidth = Op1.getValueSizeInBits();
21365 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
21366 APInt KnownZero, KnownOne;
21367 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
21368 !DCI.isBeforeLegalizeOps());
21369 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21370 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
21371 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
21372 DCI.CommitTargetLoweringOpt(TLO);
21377 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
21378 SDValue Op = N->getOperand(0);
21379 if (Op.getOpcode() == ISD::BITCAST)
21380 Op = Op.getOperand(0);
21381 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
21382 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
21383 VT.getVectorElementType().getSizeInBits() ==
21384 OpVT.getVectorElementType().getSizeInBits()) {
21385 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
21390 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
21391 const X86Subtarget *Subtarget) {
21392 EVT VT = N->getValueType(0);
21393 if (!VT.isVector())
21396 SDValue N0 = N->getOperand(0);
21397 SDValue N1 = N->getOperand(1);
21398 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
21401 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
21402 // both SSE and AVX2 since there is no sign-extended shift right
21403 // operation on a vector with 64-bit elements.
21404 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
21405 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
21406 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
21407 N0.getOpcode() == ISD::SIGN_EXTEND)) {
21408 SDValue N00 = N0.getOperand(0);
21410 // EXTLOAD has a better solution on AVX2,
21411 // it may be replaced with X86ISD::VSEXT node.
21412 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
21413 if (!ISD::isNormalLoad(N00.getNode()))
21416 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
21417 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
21419 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
21425 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
21426 TargetLowering::DAGCombinerInfo &DCI,
21427 const X86Subtarget *Subtarget) {
21428 if (!DCI.isBeforeLegalizeOps())
21431 if (!Subtarget->hasFp256())
21434 EVT VT = N->getValueType(0);
21435 if (VT.isVector() && VT.getSizeInBits() == 256) {
21436 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21444 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
21445 const X86Subtarget* Subtarget) {
21447 EVT VT = N->getValueType(0);
21449 // Let legalize expand this if it isn't a legal type yet.
21450 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
21453 EVT ScalarVT = VT.getScalarType();
21454 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
21455 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
21458 SDValue A = N->getOperand(0);
21459 SDValue B = N->getOperand(1);
21460 SDValue C = N->getOperand(2);
21462 bool NegA = (A.getOpcode() == ISD::FNEG);
21463 bool NegB = (B.getOpcode() == ISD::FNEG);
21464 bool NegC = (C.getOpcode() == ISD::FNEG);
21466 // Negative multiplication when NegA xor NegB
21467 bool NegMul = (NegA != NegB);
21469 A = A.getOperand(0);
21471 B = B.getOperand(0);
21473 C = C.getOperand(0);
21477 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
21479 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
21481 return DAG.getNode(Opcode, dl, VT, A, B, C);
21484 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
21485 TargetLowering::DAGCombinerInfo &DCI,
21486 const X86Subtarget *Subtarget) {
21487 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
21488 // (and (i32 x86isd::setcc_carry), 1)
21489 // This eliminates the zext. This transformation is necessary because
21490 // ISD::SETCC is always legalized to i8.
21492 SDValue N0 = N->getOperand(0);
21493 EVT VT = N->getValueType(0);
21495 if (N0.getOpcode() == ISD::AND &&
21497 N0.getOperand(0).hasOneUse()) {
21498 SDValue N00 = N0.getOperand(0);
21499 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21500 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21501 if (!C || C->getZExtValue() != 1)
21503 return DAG.getNode(ISD::AND, dl, VT,
21504 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21505 N00.getOperand(0), N00.getOperand(1)),
21506 DAG.getConstant(1, VT));
21510 if (N0.getOpcode() == ISD::TRUNCATE &&
21512 N0.getOperand(0).hasOneUse()) {
21513 SDValue N00 = N0.getOperand(0);
21514 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21515 return DAG.getNode(ISD::AND, dl, VT,
21516 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21517 N00.getOperand(0), N00.getOperand(1)),
21518 DAG.getConstant(1, VT));
21521 if (VT.is256BitVector()) {
21522 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21530 // Optimize x == -y --> x+y == 0
21531 // x != -y --> x+y != 0
21532 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
21533 const X86Subtarget* Subtarget) {
21534 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
21535 SDValue LHS = N->getOperand(0);
21536 SDValue RHS = N->getOperand(1);
21537 EVT VT = N->getValueType(0);
21540 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
21541 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
21542 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
21543 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21544 LHS.getValueType(), RHS, LHS.getOperand(1));
21545 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21546 addV, DAG.getConstant(0, addV.getValueType()), CC);
21548 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
21549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
21550 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
21551 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21552 RHS.getValueType(), LHS, RHS.getOperand(1));
21553 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21554 addV, DAG.getConstant(0, addV.getValueType()), CC);
21557 if (VT.getScalarType() == MVT::i1) {
21558 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
21559 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21560 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
21561 if (!IsSEXT0 && !IsVZero0)
21563 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
21564 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21565 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
21567 if (!IsSEXT1 && !IsVZero1)
21570 if (IsSEXT0 && IsVZero1) {
21571 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
21572 if (CC == ISD::SETEQ)
21573 return DAG.getNOT(DL, LHS.getOperand(0), VT);
21574 return LHS.getOperand(0);
21576 if (IsSEXT1 && IsVZero0) {
21577 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
21578 if (CC == ISD::SETEQ)
21579 return DAG.getNOT(DL, RHS.getOperand(0), VT);
21580 return RHS.getOperand(0);
21587 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
21588 const X86Subtarget *Subtarget) {
21590 MVT VT = N->getOperand(1)->getSimpleValueType(0);
21591 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
21592 "X86insertps is only defined for v4x32");
21594 SDValue Ld = N->getOperand(1);
21595 if (MayFoldLoad(Ld)) {
21596 // Extract the countS bits from the immediate so we can get the proper
21597 // address when narrowing the vector load to a specific element.
21598 // When the second source op is a memory address, interps doesn't use
21599 // countS and just gets an f32 from that address.
21600 unsigned DestIndex =
21601 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
21602 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
21606 // Create this as a scalar to vector to match the instruction pattern.
21607 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
21608 // countS bits are ignored when loading from memory on insertps, which
21609 // means we don't need to explicitly set them to 0.
21610 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
21611 LoadScalarToVector, N->getOperand(2));
21614 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
21615 // as "sbb reg,reg", since it can be extended without zext and produces
21616 // an all-ones bit which is more useful than 0/1 in some cases.
21617 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
21620 return DAG.getNode(ISD::AND, DL, VT,
21621 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21622 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
21623 DAG.getConstant(1, VT));
21624 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
21625 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
21626 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21627 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
21630 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
21631 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
21632 TargetLowering::DAGCombinerInfo &DCI,
21633 const X86Subtarget *Subtarget) {
21635 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
21636 SDValue EFLAGS = N->getOperand(1);
21638 if (CC == X86::COND_A) {
21639 // Try to convert COND_A into COND_B in an attempt to facilitate
21640 // materializing "setb reg".
21642 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
21643 // cannot take an immediate as its first operand.
21645 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
21646 EFLAGS.getValueType().isInteger() &&
21647 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
21648 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
21649 EFLAGS.getNode()->getVTList(),
21650 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
21651 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
21652 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
21656 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
21657 // a zext and produces an all-ones bit which is more useful than 0/1 in some
21659 if (CC == X86::COND_B)
21660 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
21664 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21665 if (Flags.getNode()) {
21666 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21667 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
21673 // Optimize branch condition evaluation.
21675 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
21676 TargetLowering::DAGCombinerInfo &DCI,
21677 const X86Subtarget *Subtarget) {
21679 SDValue Chain = N->getOperand(0);
21680 SDValue Dest = N->getOperand(1);
21681 SDValue EFLAGS = N->getOperand(3);
21682 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
21686 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21687 if (Flags.getNode()) {
21688 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21689 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
21696 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
21697 const X86TargetLowering *XTLI) {
21698 SDValue Op0 = N->getOperand(0);
21699 EVT InVT = Op0->getValueType(0);
21701 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
21702 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
21704 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
21705 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
21706 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
21709 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
21710 // a 32-bit target where SSE doesn't support i64->FP operations.
21711 if (Op0.getOpcode() == ISD::LOAD) {
21712 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
21713 EVT VT = Ld->getValueType(0);
21714 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
21715 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
21716 !XTLI->getSubtarget()->is64Bit() &&
21718 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
21719 Ld->getChain(), Op0, DAG);
21720 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
21727 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
21728 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
21729 X86TargetLowering::DAGCombinerInfo &DCI) {
21730 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
21731 // the result is either zero or one (depending on the input carry bit).
21732 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
21733 if (X86::isZeroNode(N->getOperand(0)) &&
21734 X86::isZeroNode(N->getOperand(1)) &&
21735 // We don't have a good way to replace an EFLAGS use, so only do this when
21737 SDValue(N, 1).use_empty()) {
21739 EVT VT = N->getValueType(0);
21740 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
21741 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
21742 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
21743 DAG.getConstant(X86::COND_B,MVT::i8),
21745 DAG.getConstant(1, VT));
21746 return DCI.CombineTo(N, Res1, CarryOut);
21752 // fold (add Y, (sete X, 0)) -> adc 0, Y
21753 // (add Y, (setne X, 0)) -> sbb -1, Y
21754 // (sub (sete X, 0), Y) -> sbb 0, Y
21755 // (sub (setne X, 0), Y) -> adc -1, Y
21756 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
21759 // Look through ZExts.
21760 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
21761 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
21764 SDValue SetCC = Ext.getOperand(0);
21765 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
21768 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
21769 if (CC != X86::COND_E && CC != X86::COND_NE)
21772 SDValue Cmp = SetCC.getOperand(1);
21773 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
21774 !X86::isZeroNode(Cmp.getOperand(1)) ||
21775 !Cmp.getOperand(0).getValueType().isInteger())
21778 SDValue CmpOp0 = Cmp.getOperand(0);
21779 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
21780 DAG.getConstant(1, CmpOp0.getValueType()));
21782 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
21783 if (CC == X86::COND_NE)
21784 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
21785 DL, OtherVal.getValueType(), OtherVal,
21786 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
21787 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
21788 DL, OtherVal.getValueType(), OtherVal,
21789 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
21792 /// PerformADDCombine - Do target-specific dag combines on integer adds.
21793 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
21794 const X86Subtarget *Subtarget) {
21795 EVT VT = N->getValueType(0);
21796 SDValue Op0 = N->getOperand(0);
21797 SDValue Op1 = N->getOperand(1);
21799 // Try to synthesize horizontal adds from adds of shuffles.
21800 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21801 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21802 isHorizontalBinOp(Op0, Op1, true))
21803 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
21805 return OptimizeConditionalInDecrement(N, DAG);
21808 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
21809 const X86Subtarget *Subtarget) {
21810 SDValue Op0 = N->getOperand(0);
21811 SDValue Op1 = N->getOperand(1);
21813 // X86 can't encode an immediate LHS of a sub. See if we can push the
21814 // negation into a preceding instruction.
21815 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
21816 // If the RHS of the sub is a XOR with one use and a constant, invert the
21817 // immediate. Then add one to the LHS of the sub so we can turn
21818 // X-Y -> X+~Y+1, saving one register.
21819 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
21820 isa<ConstantSDNode>(Op1.getOperand(1))) {
21821 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
21822 EVT VT = Op0.getValueType();
21823 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
21825 DAG.getConstant(~XorC, VT));
21826 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
21827 DAG.getConstant(C->getAPIntValue()+1, VT));
21831 // Try to synthesize horizontal adds from adds of shuffles.
21832 EVT VT = N->getValueType(0);
21833 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21834 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21835 isHorizontalBinOp(Op0, Op1, true))
21836 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
21838 return OptimizeConditionalInDecrement(N, DAG);
21841 /// performVZEXTCombine - Performs build vector combines
21842 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
21843 TargetLowering::DAGCombinerInfo &DCI,
21844 const X86Subtarget *Subtarget) {
21845 // (vzext (bitcast (vzext (x)) -> (vzext x)
21846 SDValue In = N->getOperand(0);
21847 while (In.getOpcode() == ISD::BITCAST)
21848 In = In.getOperand(0);
21850 if (In.getOpcode() != X86ISD::VZEXT)
21853 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
21857 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
21858 DAGCombinerInfo &DCI) const {
21859 SelectionDAG &DAG = DCI.DAG;
21860 switch (N->getOpcode()) {
21862 case ISD::EXTRACT_VECTOR_ELT:
21863 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
21865 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
21866 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
21867 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
21868 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
21869 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
21870 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
21873 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
21874 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
21875 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
21876 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
21877 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
21878 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
21879 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
21880 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
21881 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
21883 case X86ISD::FOR: return PerformFORCombine(N, DAG);
21885 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
21886 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
21887 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
21888 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
21889 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
21890 case ISD::ANY_EXTEND:
21891 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
21892 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
21893 case ISD::SIGN_EXTEND_INREG:
21894 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
21895 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
21896 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
21897 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
21898 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
21899 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
21900 case X86ISD::SHUFP: // Handle all target specific shuffles
21901 case X86ISD::PALIGNR:
21902 case X86ISD::UNPCKH:
21903 case X86ISD::UNPCKL:
21904 case X86ISD::MOVHLPS:
21905 case X86ISD::MOVLHPS:
21906 case X86ISD::PSHUFD:
21907 case X86ISD::PSHUFHW:
21908 case X86ISD::PSHUFLW:
21909 case X86ISD::MOVSS:
21910 case X86ISD::MOVSD:
21911 case X86ISD::VPERMILP:
21912 case X86ISD::VPERM2X128:
21913 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
21914 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
21915 case ISD::INTRINSIC_WO_CHAIN:
21916 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
21917 case X86ISD::INSERTPS:
21918 return PerformINSERTPSCombine(N, DAG, Subtarget);
21919 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
21925 /// isTypeDesirableForOp - Return true if the target has native support for
21926 /// the specified value type and it is 'desirable' to use the type for the
21927 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
21928 /// instruction encodings are longer and some i16 instructions are slow.
21929 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
21930 if (!isTypeLegal(VT))
21932 if (VT != MVT::i16)
21939 case ISD::SIGN_EXTEND:
21940 case ISD::ZERO_EXTEND:
21941 case ISD::ANY_EXTEND:
21954 /// IsDesirableToPromoteOp - This method query the target whether it is
21955 /// beneficial for dag combiner to promote the specified node. If true, it
21956 /// should return the desired promotion type by reference.
21957 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
21958 EVT VT = Op.getValueType();
21959 if (VT != MVT::i16)
21962 bool Promote = false;
21963 bool Commute = false;
21964 switch (Op.getOpcode()) {
21967 LoadSDNode *LD = cast<LoadSDNode>(Op);
21968 // If the non-extending load has a single use and it's not live out, then it
21969 // might be folded.
21970 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
21971 Op.hasOneUse()*/) {
21972 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
21973 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
21974 // The only case where we'd want to promote LOAD (rather then it being
21975 // promoted as an operand is when it's only use is liveout.
21976 if (UI->getOpcode() != ISD::CopyToReg)
21983 case ISD::SIGN_EXTEND:
21984 case ISD::ZERO_EXTEND:
21985 case ISD::ANY_EXTEND:
21990 SDValue N0 = Op.getOperand(0);
21991 // Look out for (store (shl (load), x)).
21992 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22005 SDValue N0 = Op.getOperand(0);
22006 SDValue N1 = Op.getOperand(1);
22007 if (!Commute && MayFoldLoad(N1))
22009 // Avoid disabling potential load folding opportunities.
22010 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22012 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22022 //===----------------------------------------------------------------------===//
22023 // X86 Inline Assembly Support
22024 //===----------------------------------------------------------------------===//
22027 // Helper to match a string separated by whitespace.
22028 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
22029 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
22031 for (unsigned i = 0, e = args.size(); i != e; ++i) {
22032 StringRef piece(*args[i]);
22033 if (!s.startswith(piece)) // Check if the piece matches.
22036 s = s.substr(piece.size());
22037 StringRef::size_type pos = s.find_first_not_of(" \t");
22038 if (pos == 0) // We matched a prefix.
22046 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
22049 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
22051 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
22052 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
22053 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
22054 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
22056 if (AsmPieces.size() == 3)
22058 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
22065 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
22066 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22068 std::string AsmStr = IA->getAsmString();
22070 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22071 if (!Ty || Ty->getBitWidth() % 16 != 0)
22074 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22075 SmallVector<StringRef, 4> AsmPieces;
22076 SplitString(AsmStr, AsmPieces, ";\n");
22078 switch (AsmPieces.size()) {
22079 default: return false;
22081 // FIXME: this should verify that we are targeting a 486 or better. If not,
22082 // we will turn this bswap into something that will be lowered to logical
22083 // ops instead of emitting the bswap asm. For now, we don't support 486 or
22084 // lower so don't worry about this.
22086 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22087 matchAsm(AsmPieces[0], "bswapl", "$0") ||
22088 matchAsm(AsmPieces[0], "bswapq", "$0") ||
22089 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22090 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22091 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22092 // No need to check constraints, nothing other than the equivalent of
22093 // "=r,0" would be valid here.
22094 return IntrinsicLowering::LowerToByteSwap(CI);
22097 // rorw $$8, ${0:w} --> llvm.bswap.i16
22098 if (CI->getType()->isIntegerTy(16) &&
22099 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22100 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22101 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22103 const std::string &ConstraintsStr = IA->getConstraintString();
22104 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22105 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22106 if (clobbersFlagRegisters(AsmPieces))
22107 return IntrinsicLowering::LowerToByteSwap(CI);
22111 if (CI->getType()->isIntegerTy(32) &&
22112 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22113 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22114 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22115 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22117 const std::string &ConstraintsStr = IA->getConstraintString();
22118 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22119 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22120 if (clobbersFlagRegisters(AsmPieces))
22121 return IntrinsicLowering::LowerToByteSwap(CI);
22124 if (CI->getType()->isIntegerTy(64)) {
22125 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22126 if (Constraints.size() >= 2 &&
22127 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22128 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22129 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22130 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22131 matchAsm(AsmPieces[1], "bswap", "%edx") &&
22132 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22133 return IntrinsicLowering::LowerToByteSwap(CI);
22141 /// getConstraintType - Given a constraint letter, return the type of
22142 /// constraint it is for this target.
22143 X86TargetLowering::ConstraintType
22144 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
22145 if (Constraint.size() == 1) {
22146 switch (Constraint[0]) {
22157 return C_RegisterClass;
22181 return TargetLowering::getConstraintType(Constraint);
22184 /// Examine constraint type and operand type and determine a weight value.
22185 /// This object must already have been set up with the operand type
22186 /// and the current alternative constraint selected.
22187 TargetLowering::ConstraintWeight
22188 X86TargetLowering::getSingleConstraintMatchWeight(
22189 AsmOperandInfo &info, const char *constraint) const {
22190 ConstraintWeight weight = CW_Invalid;
22191 Value *CallOperandVal = info.CallOperandVal;
22192 // If we don't have a value, we can't do a match,
22193 // but allow it at the lowest weight.
22194 if (!CallOperandVal)
22196 Type *type = CallOperandVal->getType();
22197 // Look at the constraint type.
22198 switch (*constraint) {
22200 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
22211 if (CallOperandVal->getType()->isIntegerTy())
22212 weight = CW_SpecificReg;
22217 if (type->isFloatingPointTy())
22218 weight = CW_SpecificReg;
22221 if (type->isX86_MMXTy() && Subtarget->hasMMX())
22222 weight = CW_SpecificReg;
22226 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
22227 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
22228 weight = CW_Register;
22231 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
22232 if (C->getZExtValue() <= 31)
22233 weight = CW_Constant;
22237 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22238 if (C->getZExtValue() <= 63)
22239 weight = CW_Constant;
22243 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22244 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
22245 weight = CW_Constant;
22249 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22250 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
22251 weight = CW_Constant;
22255 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22256 if (C->getZExtValue() <= 3)
22257 weight = CW_Constant;
22261 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22262 if (C->getZExtValue() <= 0xff)
22263 weight = CW_Constant;
22268 if (dyn_cast<ConstantFP>(CallOperandVal)) {
22269 weight = CW_Constant;
22273 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22274 if ((C->getSExtValue() >= -0x80000000LL) &&
22275 (C->getSExtValue() <= 0x7fffffffLL))
22276 weight = CW_Constant;
22280 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22281 if (C->getZExtValue() <= 0xffffffff)
22282 weight = CW_Constant;
22289 /// LowerXConstraint - try to replace an X constraint, which matches anything,
22290 /// with another that has more specific requirements based on the type of the
22291 /// corresponding operand.
22292 const char *X86TargetLowering::
22293 LowerXConstraint(EVT ConstraintVT) const {
22294 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
22295 // 'f' like normal targets.
22296 if (ConstraintVT.isFloatingPoint()) {
22297 if (Subtarget->hasSSE2())
22299 if (Subtarget->hasSSE1())
22303 return TargetLowering::LowerXConstraint(ConstraintVT);
22306 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
22307 /// vector. If it is invalid, don't add anything to Ops.
22308 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
22309 std::string &Constraint,
22310 std::vector<SDValue>&Ops,
22311 SelectionDAG &DAG) const {
22314 // Only support length 1 constraints for now.
22315 if (Constraint.length() > 1) return;
22317 char ConstraintLetter = Constraint[0];
22318 switch (ConstraintLetter) {
22321 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22322 if (C->getZExtValue() <= 31) {
22323 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22329 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22330 if (C->getZExtValue() <= 63) {
22331 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22337 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22338 if (isInt<8>(C->getSExtValue())) {
22339 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22345 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22346 if (C->getZExtValue() <= 255) {
22347 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22353 // 32-bit signed value
22354 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22355 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22356 C->getSExtValue())) {
22357 // Widen to 64 bits here to get it sign extended.
22358 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
22361 // FIXME gcc accepts some relocatable values here too, but only in certain
22362 // memory models; it's complicated.
22367 // 32-bit unsigned value
22368 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22369 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22370 C->getZExtValue())) {
22371 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22375 // FIXME gcc accepts some relocatable values here too, but only in certain
22376 // memory models; it's complicated.
22380 // Literal immediates are always ok.
22381 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
22382 // Widen to 64 bits here to get it sign extended.
22383 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
22387 // In any sort of PIC mode addresses need to be computed at runtime by
22388 // adding in a register or some sort of table lookup. These can't
22389 // be used as immediates.
22390 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
22393 // If we are in non-pic codegen mode, we allow the address of a global (with
22394 // an optional displacement) to be used with 'i'.
22395 GlobalAddressSDNode *GA = nullptr;
22396 int64_t Offset = 0;
22398 // Match either (GA), (GA+C), (GA+C1+C2), etc.
22400 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
22401 Offset += GA->getOffset();
22403 } else if (Op.getOpcode() == ISD::ADD) {
22404 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22405 Offset += C->getZExtValue();
22406 Op = Op.getOperand(0);
22409 } else if (Op.getOpcode() == ISD::SUB) {
22410 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22411 Offset += -C->getZExtValue();
22412 Op = Op.getOperand(0);
22417 // Otherwise, this isn't something we can handle, reject it.
22421 const GlobalValue *GV = GA->getGlobal();
22422 // If we require an extra load to get this address, as in PIC mode, we
22423 // can't accept it.
22424 if (isGlobalStubReference(
22425 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
22428 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
22429 GA->getValueType(0), Offset);
22434 if (Result.getNode()) {
22435 Ops.push_back(Result);
22438 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
22441 std::pair<unsigned, const TargetRegisterClass*>
22442 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
22444 // First, see if this is a constraint that directly corresponds to an LLVM
22446 if (Constraint.size() == 1) {
22447 // GCC Constraint Letters
22448 switch (Constraint[0]) {
22450 // TODO: Slight differences here in allocation order and leaving
22451 // RIP in the class. Do they matter any more here than they do
22452 // in the normal allocation?
22453 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
22454 if (Subtarget->is64Bit()) {
22455 if (VT == MVT::i32 || VT == MVT::f32)
22456 return std::make_pair(0U, &X86::GR32RegClass);
22457 if (VT == MVT::i16)
22458 return std::make_pair(0U, &X86::GR16RegClass);
22459 if (VT == MVT::i8 || VT == MVT::i1)
22460 return std::make_pair(0U, &X86::GR8RegClass);
22461 if (VT == MVT::i64 || VT == MVT::f64)
22462 return std::make_pair(0U, &X86::GR64RegClass);
22465 // 32-bit fallthrough
22466 case 'Q': // Q_REGS
22467 if (VT == MVT::i32 || VT == MVT::f32)
22468 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
22469 if (VT == MVT::i16)
22470 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
22471 if (VT == MVT::i8 || VT == MVT::i1)
22472 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
22473 if (VT == MVT::i64)
22474 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
22476 case 'r': // GENERAL_REGS
22477 case 'l': // INDEX_REGS
22478 if (VT == MVT::i8 || VT == MVT::i1)
22479 return std::make_pair(0U, &X86::GR8RegClass);
22480 if (VT == MVT::i16)
22481 return std::make_pair(0U, &X86::GR16RegClass);
22482 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
22483 return std::make_pair(0U, &X86::GR32RegClass);
22484 return std::make_pair(0U, &X86::GR64RegClass);
22485 case 'R': // LEGACY_REGS
22486 if (VT == MVT::i8 || VT == MVT::i1)
22487 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
22488 if (VT == MVT::i16)
22489 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
22490 if (VT == MVT::i32 || !Subtarget->is64Bit())
22491 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
22492 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
22493 case 'f': // FP Stack registers.
22494 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
22495 // value to the correct fpstack register class.
22496 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
22497 return std::make_pair(0U, &X86::RFP32RegClass);
22498 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
22499 return std::make_pair(0U, &X86::RFP64RegClass);
22500 return std::make_pair(0U, &X86::RFP80RegClass);
22501 case 'y': // MMX_REGS if MMX allowed.
22502 if (!Subtarget->hasMMX()) break;
22503 return std::make_pair(0U, &X86::VR64RegClass);
22504 case 'Y': // SSE_REGS if SSE2 allowed
22505 if (!Subtarget->hasSSE2()) break;
22507 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
22508 if (!Subtarget->hasSSE1()) break;
22510 switch (VT.SimpleTy) {
22512 // Scalar SSE types.
22515 return std::make_pair(0U, &X86::FR32RegClass);
22518 return std::make_pair(0U, &X86::FR64RegClass);
22526 return std::make_pair(0U, &X86::VR128RegClass);
22534 return std::make_pair(0U, &X86::VR256RegClass);
22539 return std::make_pair(0U, &X86::VR512RegClass);
22545 // Use the default implementation in TargetLowering to convert the register
22546 // constraint into a member of a register class.
22547 std::pair<unsigned, const TargetRegisterClass*> Res;
22548 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
22550 // Not found as a standard register?
22552 // Map st(0) -> st(7) -> ST0
22553 if (Constraint.size() == 7 && Constraint[0] == '{' &&
22554 tolower(Constraint[1]) == 's' &&
22555 tolower(Constraint[2]) == 't' &&
22556 Constraint[3] == '(' &&
22557 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
22558 Constraint[5] == ')' &&
22559 Constraint[6] == '}') {
22561 Res.first = X86::ST0+Constraint[4]-'0';
22562 Res.second = &X86::RFP80RegClass;
22566 // GCC allows "st(0)" to be called just plain "st".
22567 if (StringRef("{st}").equals_lower(Constraint)) {
22568 Res.first = X86::ST0;
22569 Res.second = &X86::RFP80RegClass;
22574 if (StringRef("{flags}").equals_lower(Constraint)) {
22575 Res.first = X86::EFLAGS;
22576 Res.second = &X86::CCRRegClass;
22580 // 'A' means EAX + EDX.
22581 if (Constraint == "A") {
22582 Res.first = X86::EAX;
22583 Res.second = &X86::GR32_ADRegClass;
22589 // Otherwise, check to see if this is a register class of the wrong value
22590 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
22591 // turn into {ax},{dx}.
22592 if (Res.second->hasType(VT))
22593 return Res; // Correct type already, nothing to do.
22595 // All of the single-register GCC register classes map their values onto
22596 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
22597 // really want an 8-bit or 32-bit register, map to the appropriate register
22598 // class and return the appropriate register.
22599 if (Res.second == &X86::GR16RegClass) {
22600 if (VT == MVT::i8 || VT == MVT::i1) {
22601 unsigned DestReg = 0;
22602 switch (Res.first) {
22604 case X86::AX: DestReg = X86::AL; break;
22605 case X86::DX: DestReg = X86::DL; break;
22606 case X86::CX: DestReg = X86::CL; break;
22607 case X86::BX: DestReg = X86::BL; break;
22610 Res.first = DestReg;
22611 Res.second = &X86::GR8RegClass;
22613 } else if (VT == MVT::i32 || VT == MVT::f32) {
22614 unsigned DestReg = 0;
22615 switch (Res.first) {
22617 case X86::AX: DestReg = X86::EAX; break;
22618 case X86::DX: DestReg = X86::EDX; break;
22619 case X86::CX: DestReg = X86::ECX; break;
22620 case X86::BX: DestReg = X86::EBX; break;
22621 case X86::SI: DestReg = X86::ESI; break;
22622 case X86::DI: DestReg = X86::EDI; break;
22623 case X86::BP: DestReg = X86::EBP; break;
22624 case X86::SP: DestReg = X86::ESP; break;
22627 Res.first = DestReg;
22628 Res.second = &X86::GR32RegClass;
22630 } else if (VT == MVT::i64 || VT == MVT::f64) {
22631 unsigned DestReg = 0;
22632 switch (Res.first) {
22634 case X86::AX: DestReg = X86::RAX; break;
22635 case X86::DX: DestReg = X86::RDX; break;
22636 case X86::CX: DestReg = X86::RCX; break;
22637 case X86::BX: DestReg = X86::RBX; break;
22638 case X86::SI: DestReg = X86::RSI; break;
22639 case X86::DI: DestReg = X86::RDI; break;
22640 case X86::BP: DestReg = X86::RBP; break;
22641 case X86::SP: DestReg = X86::RSP; break;
22644 Res.first = DestReg;
22645 Res.second = &X86::GR64RegClass;
22648 } else if (Res.second == &X86::FR32RegClass ||
22649 Res.second == &X86::FR64RegClass ||
22650 Res.second == &X86::VR128RegClass ||
22651 Res.second == &X86::VR256RegClass ||
22652 Res.second == &X86::FR32XRegClass ||
22653 Res.second == &X86::FR64XRegClass ||
22654 Res.second == &X86::VR128XRegClass ||
22655 Res.second == &X86::VR256XRegClass ||
22656 Res.second == &X86::VR512RegClass) {
22657 // Handle references to XMM physical registers that got mapped into the
22658 // wrong class. This can happen with constraints like {xmm0} where the
22659 // target independent register mapper will just pick the first match it can
22660 // find, ignoring the required type.
22662 if (VT == MVT::f32 || VT == MVT::i32)
22663 Res.second = &X86::FR32RegClass;
22664 else if (VT == MVT::f64 || VT == MVT::i64)
22665 Res.second = &X86::FR64RegClass;
22666 else if (X86::VR128RegClass.hasType(VT))
22667 Res.second = &X86::VR128RegClass;
22668 else if (X86::VR256RegClass.hasType(VT))
22669 Res.second = &X86::VR256RegClass;
22670 else if (X86::VR512RegClass.hasType(VT))
22671 Res.second = &X86::VR512RegClass;
22677 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
22679 // Scaling factors are not free at all.
22680 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
22681 // will take 2 allocations in the out of order engine instead of 1
22682 // for plain addressing mode, i.e. inst (reg1).
22684 // vaddps (%rsi,%drx), %ymm0, %ymm1
22685 // Requires two allocations (one for the load, one for the computation)
22687 // vaddps (%rsi), %ymm0, %ymm1
22688 // Requires just 1 allocation, i.e., freeing allocations for other operations
22689 // and having less micro operations to execute.
22691 // For some X86 architectures, this is even worse because for instance for
22692 // stores, the complex addressing mode forces the instruction to use the
22693 // "load" ports instead of the dedicated "store" port.
22694 // E.g., on Haswell:
22695 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
22696 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
22697 if (isLegalAddressingMode(AM, Ty))
22698 // Scale represents reg2 * scale, thus account for 1
22699 // as soon as we use a second register.
22700 return AM.Scale != 0;
22704 bool X86TargetLowering::isTargetFTOL() const {
22705 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();