1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i16, Expand);
526 if (Subtarget->hasPOPCNT()) {
527 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
529 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
531 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
532 if (Subtarget->is64Bit())
533 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
536 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
538 if (!Subtarget->hasMOVBE())
539 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
541 // These should be promoted to a larger select which is supported.
542 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
543 // X86 wants to expand cmov itself.
544 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
546 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
556 if (Subtarget->is64Bit()) {
557 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
560 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
561 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
562 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
563 // support continuation, user-level threading, and etc.. As a result, no
564 // other SjLj exception interfaces are implemented and please don't build
565 // your own exception handling based on them.
566 // LLVM/Clang supports zero-cost DWARF exception handling.
567 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
568 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
571 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
572 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
574 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
575 if (Subtarget->is64Bit())
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
577 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
578 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
579 if (Subtarget->is64Bit()) {
580 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
581 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
582 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
583 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
584 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
586 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
587 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
589 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
596 if (Subtarget->hasSSE1())
597 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
599 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
601 // Expand certain atomics
602 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
604 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
605 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
606 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
609 if (Subtarget->hasCmpxchg16b()) {
610 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
613 // FIXME - use subtarget debug flags
614 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
615 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
616 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
619 if (Subtarget->is64Bit()) {
620 setExceptionPointerRegister(X86::RAX);
621 setExceptionSelectorRegister(X86::RDX);
623 setExceptionPointerRegister(X86::EAX);
624 setExceptionSelectorRegister(X86::EDX);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
627 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
629 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
630 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::TRAP, MVT::Other, Legal);
633 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
635 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
636 setOperationAction(ISD::VASTART , MVT::Other, Custom);
637 setOperationAction(ISD::VAEND , MVT::Other, Expand);
638 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
639 // TargetInfo::X86_64ABIBuiltinVaList
640 setOperationAction(ISD::VAARG , MVT::Other, Custom);
641 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
643 // TargetInfo::CharPtrBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Expand);
645 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
648 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
649 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
651 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
652 MVT::i64 : MVT::i32, Custom);
654 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
655 // f32 and f64 use SSE.
656 // Set up the FP register classes.
657 addRegisterClass(MVT::f32, &X86::FR32RegClass);
658 addRegisterClass(MVT::f64, &X86::FR64RegClass);
660 // Use ANDPD to simulate FABS.
661 setOperationAction(ISD::FABS , MVT::f64, Custom);
662 setOperationAction(ISD::FABS , MVT::f32, Custom);
664 // Use XORP to simulate FNEG.
665 setOperationAction(ISD::FNEG , MVT::f64, Custom);
666 setOperationAction(ISD::FNEG , MVT::f32, Custom);
668 // Use ANDPD and ORPD to simulate FCOPYSIGN.
669 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
670 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
672 // Lower this to FGETSIGNx86 plus an AND.
673 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
674 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
676 // We don't support sin/cos/fmod
677 setOperationAction(ISD::FSIN , MVT::f64, Expand);
678 setOperationAction(ISD::FCOS , MVT::f64, Expand);
679 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
680 setOperationAction(ISD::FSIN , MVT::f32, Expand);
681 setOperationAction(ISD::FCOS , MVT::f32, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
684 // Expand FP immediates into loads from the stack, except for the special
686 addLegalFPImmediate(APFloat(+0.0)); // xorpd
687 addLegalFPImmediate(APFloat(+0.0f)); // xorps
688 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
689 // Use SSE for f32, x87 for f64.
690 // Set up the FP register classes.
691 addRegisterClass(MVT::f32, &X86::FR32RegClass);
692 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
694 // Use ANDPS to simulate FABS.
695 setOperationAction(ISD::FABS , MVT::f32, Custom);
697 // Use XORP to simulate FNEG.
698 setOperationAction(ISD::FNEG , MVT::f32, Custom);
700 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
702 // Use ANDPS and ORPS to simulate FCOPYSIGN.
703 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
704 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
706 // We don't support sin/cos/fmod
707 setOperationAction(ISD::FSIN , MVT::f32, Expand);
708 setOperationAction(ISD::FCOS , MVT::f32, Expand);
709 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
711 // Special cases we handle for FP constants.
712 addLegalFPImmediate(APFloat(+0.0f)); // xorps
713 addLegalFPImmediate(APFloat(+0.0)); // FLD0
714 addLegalFPImmediate(APFloat(+1.0)); // FLD1
715 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
716 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
718 if (!TM.Options.UnsafeFPMath) {
719 setOperationAction(ISD::FSIN , MVT::f64, Expand);
720 setOperationAction(ISD::FCOS , MVT::f64, Expand);
721 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
723 } else if (!TM.Options.UseSoftFloat) {
724 // f32 and f64 in x87.
725 // Set up the FP register classes.
726 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
727 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
729 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
730 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
731 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
734 if (!TM.Options.UnsafeFPMath) {
735 setOperationAction(ISD::FSIN , MVT::f64, Expand);
736 setOperationAction(ISD::FSIN , MVT::f32, Expand);
737 setOperationAction(ISD::FCOS , MVT::f64, Expand);
738 setOperationAction(ISD::FCOS , MVT::f32, Expand);
739 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
742 addLegalFPImmediate(APFloat(+0.0)); // FLD0
743 addLegalFPImmediate(APFloat(+1.0)); // FLD1
744 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
745 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
746 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
747 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
748 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
749 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
752 // We don't support FMA.
753 setOperationAction(ISD::FMA, MVT::f64, Expand);
754 setOperationAction(ISD::FMA, MVT::f32, Expand);
756 // Long double always uses X87.
757 if (!TM.Options.UseSoftFloat) {
758 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
759 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
760 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
762 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
763 addLegalFPImmediate(TmpFlt); // FLD0
765 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
768 APFloat TmpFlt2(+1.0);
769 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
771 addLegalFPImmediate(TmpFlt2); // FLD1
772 TmpFlt2.changeSign();
773 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
776 if (!TM.Options.UnsafeFPMath) {
777 setOperationAction(ISD::FSIN , MVT::f80, Expand);
778 setOperationAction(ISD::FCOS , MVT::f80, Expand);
779 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
782 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
783 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
784 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
785 setOperationAction(ISD::FRINT, MVT::f80, Expand);
786 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
787 setOperationAction(ISD::FMA, MVT::f80, Expand);
790 // Always use a library call for pow.
791 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
792 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
795 setOperationAction(ISD::FLOG, MVT::f80, Expand);
796 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
798 setOperationAction(ISD::FEXP, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
881 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
884 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
885 // with -msoft-float, disable use of MMX as well.
886 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
887 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
888 // No operations on x86mmx supported, everything uses intrinsics.
891 // MMX-sized vectors (other than x86mmx) are expected to be expanded
892 // into smaller operations.
893 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
894 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
895 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
896 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
897 setOperationAction(ISD::AND, MVT::v8i8, Expand);
898 setOperationAction(ISD::AND, MVT::v4i16, Expand);
899 setOperationAction(ISD::AND, MVT::v2i32, Expand);
900 setOperationAction(ISD::AND, MVT::v1i64, Expand);
901 setOperationAction(ISD::OR, MVT::v8i8, Expand);
902 setOperationAction(ISD::OR, MVT::v4i16, Expand);
903 setOperationAction(ISD::OR, MVT::v2i32, Expand);
904 setOperationAction(ISD::OR, MVT::v1i64, Expand);
905 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
906 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
907 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
908 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
909 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
910 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
911 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
912 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
913 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
914 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
915 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
916 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
917 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
918 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
919 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
920 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
921 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
923 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
924 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
926 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
927 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
928 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
929 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
930 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
931 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
932 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
933 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
934 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
935 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
937 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
940 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
941 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
943 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
944 // registers cannot be used even for integer operations.
945 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
946 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
947 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
948 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
950 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
951 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
952 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
953 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
954 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
955 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
956 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
957 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
958 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
959 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
960 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
961 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
962 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
963 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
964 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
965 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
966 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
967 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
968 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
969 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
970 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
971 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
973 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
974 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
975 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
976 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
978 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
979 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
984 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
985 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
986 MVT VT = (MVT::SimpleValueType)i;
987 // Do not attempt to custom lower non-power-of-2 vectors
988 if (!isPowerOf2_32(VT.getVectorNumElements()))
990 // Do not attempt to custom lower non-128-bit vectors
991 if (!VT.is128BitVector())
993 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
994 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
998 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
999 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1000 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1001 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1002 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1005 if (Subtarget->is64Bit()) {
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1010 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1011 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1012 MVT VT = (MVT::SimpleValueType)i;
1014 // Do not attempt to promote non-128-bit vectors
1015 if (!VT.is128BitVector())
1018 setOperationAction(ISD::AND, VT, Promote);
1019 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1020 setOperationAction(ISD::OR, VT, Promote);
1021 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1022 setOperationAction(ISD::XOR, VT, Promote);
1023 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1024 setOperationAction(ISD::LOAD, VT, Promote);
1025 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1026 setOperationAction(ISD::SELECT, VT, Promote);
1027 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1030 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1032 // Custom lower v2i64 and v2f64 selects.
1033 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1034 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1035 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1041 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1042 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1043 // As there is no 64-bit GPR available, we need build a special custom
1044 // sequence to convert from v2i32 to v2f32.
1045 if (!Subtarget->is64Bit())
1046 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1048 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1049 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1051 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1053 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1054 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1055 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1058 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1059 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1060 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1061 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1062 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1063 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1064 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1065 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1066 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1067 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1068 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1075 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1076 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1077 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1078 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1079 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1081 // FIXME: Do we need to handle scalar-to-vector here?
1082 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1084 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1085 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1086 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1087 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1088 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1089 // There is no BLENDI for byte vectors. We don't need to custom lower
1090 // some vselects for now.
1091 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1093 // i8 and i16 vectors are custom , because the source register and source
1094 // source memory operand types are not the same width. f32 vectors are
1095 // custom since the immediate controlling the insert encodes additional
1097 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1098 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1099 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1100 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1103 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1105 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1107 // FIXME: these should be Legal but thats only for the case where
1108 // the index is constant. For now custom expand to deal with that.
1109 if (Subtarget->is64Bit()) {
1110 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1115 if (Subtarget->hasSSE2()) {
1116 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1117 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1120 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1122 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1123 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1125 // In the customized shift lowering, the legal cases in AVX2 will be
1127 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1128 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1130 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1131 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1133 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1136 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1137 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1138 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1139 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1140 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1141 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1142 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1144 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1145 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1146 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1148 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1149 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1150 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1151 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1152 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1155 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1156 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1157 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1158 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1159 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1161 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1162 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1163 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1164 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1165 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1166 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1167 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1168 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1169 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1170 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1171 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1172 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1174 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1175 // even though v8i16 is a legal type.
1176 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1177 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1178 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1180 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1181 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1182 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1184 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1185 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1187 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1189 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1190 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1192 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1193 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1195 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1196 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1198 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1199 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1200 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1201 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1203 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1204 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1205 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1207 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1208 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1209 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1210 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1212 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1213 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1215 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1216 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1218 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1219 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1221 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1222 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1223 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1225 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1226 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1227 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1228 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1229 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1230 setOperationAction(ISD::FMA, MVT::f32, Legal);
1231 setOperationAction(ISD::FMA, MVT::f64, Legal);
1234 if (Subtarget->hasInt256()) {
1235 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1236 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1237 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1238 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1240 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1241 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1242 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1243 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1245 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1247 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1248 // Don't lower v32i8 because there is no 128-bit byte mul
1250 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1252 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1253 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1255 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1256 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1258 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1259 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1260 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1261 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1263 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1264 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1265 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1266 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1268 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1269 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1270 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1271 // Don't lower v32i8 because there is no 128-bit byte mul
1274 // In the customized shift lowering, the legal cases in AVX2 will be
1276 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1277 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1279 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1280 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1282 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1284 // Custom lower several nodes for 256-bit types.
1285 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1286 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1287 MVT VT = (MVT::SimpleValueType)i;
1289 // Extract subvector is special because the value type
1290 // (result) is 128-bit but the source is 256-bit wide.
1291 if (VT.is128BitVector())
1292 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1294 // Do not attempt to custom lower other non-256-bit vectors
1295 if (!VT.is256BitVector())
1298 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1299 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1300 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1301 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1302 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1303 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1304 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1307 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1308 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1309 MVT VT = (MVT::SimpleValueType)i;
1311 // Do not attempt to promote non-256-bit vectors
1312 if (!VT.is256BitVector())
1315 setOperationAction(ISD::AND, VT, Promote);
1316 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1317 setOperationAction(ISD::OR, VT, Promote);
1318 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1319 setOperationAction(ISD::XOR, VT, Promote);
1320 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1321 setOperationAction(ISD::LOAD, VT, Promote);
1322 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1323 setOperationAction(ISD::SELECT, VT, Promote);
1324 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1328 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1329 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1330 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1331 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1332 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1334 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1335 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1336 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1338 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1339 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1340 setOperationAction(ISD::XOR, MVT::i1, Legal);
1341 setOperationAction(ISD::OR, MVT::i1, Legal);
1342 setOperationAction(ISD::AND, MVT::i1, Legal);
1343 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1344 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1346 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1347 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1348 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1350 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1357 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1358 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1363 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1364 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1366 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1368 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1370 if (Subtarget->is64Bit()) {
1371 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1373 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1374 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1376 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1377 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1378 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1379 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1380 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1381 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1382 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1383 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1384 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1385 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1387 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1388 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1391 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1392 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1393 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1394 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1395 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1398 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1399 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1401 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1402 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1403 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1404 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1405 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1406 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1408 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1409 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1411 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1413 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1414 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1415 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1416 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1417 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1418 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1419 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1420 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1421 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1423 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1424 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1426 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1427 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1429 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1431 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1434 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1437 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1438 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1440 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1441 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1442 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1443 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1444 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1445 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1447 if (Subtarget->hasCDI()) {
1448 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1449 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1452 // Custom lower several nodes.
1453 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1454 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1455 MVT VT = (MVT::SimpleValueType)i;
1457 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1458 // Extract subvector is special because the value type
1459 // (result) is 256/128-bit but the source is 512-bit wide.
1460 if (VT.is128BitVector() || VT.is256BitVector())
1461 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1463 if (VT.getVectorElementType() == MVT::i1)
1464 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1466 // Do not attempt to custom lower other non-512-bit vectors
1467 if (!VT.is512BitVector())
1470 if ( EltSize >= 32) {
1471 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1472 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1473 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1474 setOperationAction(ISD::VSELECT, VT, Legal);
1475 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1476 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1477 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1480 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1481 MVT VT = (MVT::SimpleValueType)i;
1483 // Do not attempt to promote non-256-bit vectors
1484 if (!VT.is512BitVector())
1487 setOperationAction(ISD::SELECT, VT, Promote);
1488 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1492 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1493 // of this type with custom code.
1494 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1495 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1496 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1500 // We want to custom lower some of our intrinsics.
1501 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1502 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1503 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1504 if (!Subtarget->is64Bit())
1505 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1507 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1508 // handle type legalization for these operations here.
1510 // FIXME: We really should do custom legalization for addition and
1511 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1512 // than generic legalization for 64-bit multiplication-with-overflow, though.
1513 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1514 // Add/Sub/Mul with overflow operations are custom lowered.
1516 setOperationAction(ISD::SADDO, VT, Custom);
1517 setOperationAction(ISD::UADDO, VT, Custom);
1518 setOperationAction(ISD::SSUBO, VT, Custom);
1519 setOperationAction(ISD::USUBO, VT, Custom);
1520 setOperationAction(ISD::SMULO, VT, Custom);
1521 setOperationAction(ISD::UMULO, VT, Custom);
1524 // There are no 8-bit 3-address imul/mul instructions
1525 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1526 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1528 if (!Subtarget->is64Bit()) {
1529 // These libcalls are not available in 32-bit.
1530 setLibcallName(RTLIB::SHL_I128, nullptr);
1531 setLibcallName(RTLIB::SRL_I128, nullptr);
1532 setLibcallName(RTLIB::SRA_I128, nullptr);
1535 // Combine sin / cos into one node or libcall if possible.
1536 if (Subtarget->hasSinCos()) {
1537 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1538 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1539 if (Subtarget->isTargetDarwin()) {
1540 // For MacOSX, we don't want to the normal expansion of a libcall to
1541 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1543 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1544 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1548 if (Subtarget->isTargetWin64()) {
1549 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1550 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1551 setOperationAction(ISD::SREM, MVT::i128, Custom);
1552 setOperationAction(ISD::UREM, MVT::i128, Custom);
1553 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1554 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1557 // We have target-specific dag combine patterns for the following nodes:
1558 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1559 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1560 setTargetDAGCombine(ISD::VSELECT);
1561 setTargetDAGCombine(ISD::SELECT);
1562 setTargetDAGCombine(ISD::SHL);
1563 setTargetDAGCombine(ISD::SRA);
1564 setTargetDAGCombine(ISD::SRL);
1565 setTargetDAGCombine(ISD::OR);
1566 setTargetDAGCombine(ISD::AND);
1567 setTargetDAGCombine(ISD::ADD);
1568 setTargetDAGCombine(ISD::FADD);
1569 setTargetDAGCombine(ISD::FSUB);
1570 setTargetDAGCombine(ISD::FMA);
1571 setTargetDAGCombine(ISD::SUB);
1572 setTargetDAGCombine(ISD::LOAD);
1573 setTargetDAGCombine(ISD::STORE);
1574 setTargetDAGCombine(ISD::ZERO_EXTEND);
1575 setTargetDAGCombine(ISD::ANY_EXTEND);
1576 setTargetDAGCombine(ISD::SIGN_EXTEND);
1577 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1578 setTargetDAGCombine(ISD::TRUNCATE);
1579 setTargetDAGCombine(ISD::SINT_TO_FP);
1580 setTargetDAGCombine(ISD::SETCC);
1581 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1582 setTargetDAGCombine(ISD::BUILD_VECTOR);
1583 if (Subtarget->is64Bit())
1584 setTargetDAGCombine(ISD::MUL);
1585 setTargetDAGCombine(ISD::XOR);
1587 computeRegisterProperties();
1589 // On Darwin, -Os means optimize for size without hurting performance,
1590 // do not reduce the limit.
1591 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1592 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1593 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1594 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1595 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1596 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1597 setPrefLoopAlignment(4); // 2^4 bytes.
1599 // Predictable cmov don't hurt on atom because it's in-order.
1600 PredictableSelectIsExpensive = !Subtarget->isAtom();
1602 setPrefFunctionAlignment(4); // 2^4 bytes.
1605 TargetLoweringBase::LegalizeTypeAction
1606 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1607 if (ExperimentalVectorWideningLegalization &&
1608 VT.getVectorNumElements() != 1 &&
1609 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1610 return TypeWidenVector;
1612 return TargetLoweringBase::getPreferredVectorAction(VT);
1615 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1617 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1619 if (Subtarget->hasAVX512())
1620 switch(VT.getVectorNumElements()) {
1621 case 8: return MVT::v8i1;
1622 case 16: return MVT::v16i1;
1625 return VT.changeVectorElementTypeToInteger();
1628 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1629 /// the desired ByVal argument alignment.
1630 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1633 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1634 if (VTy->getBitWidth() == 128)
1636 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1637 unsigned EltAlign = 0;
1638 getMaxByValAlign(ATy->getElementType(), EltAlign);
1639 if (EltAlign > MaxAlign)
1640 MaxAlign = EltAlign;
1641 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1642 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1643 unsigned EltAlign = 0;
1644 getMaxByValAlign(STy->getElementType(i), EltAlign);
1645 if (EltAlign > MaxAlign)
1646 MaxAlign = EltAlign;
1653 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1654 /// function arguments in the caller parameter area. For X86, aggregates
1655 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1656 /// are at 4-byte boundaries.
1657 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1658 if (Subtarget->is64Bit()) {
1659 // Max of 8 and alignment of type.
1660 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1667 if (Subtarget->hasSSE1())
1668 getMaxByValAlign(Ty, Align);
1672 /// getOptimalMemOpType - Returns the target specific optimal type for load
1673 /// and store operations as a result of memset, memcpy, and memmove
1674 /// lowering. If DstAlign is zero that means it's safe to destination
1675 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1676 /// means there isn't a need to check it against alignment requirement,
1677 /// probably because the source does not need to be loaded. If 'IsMemset' is
1678 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1679 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1680 /// source is constant so it does not need to be loaded.
1681 /// It returns EVT::Other if the type should be determined using generic
1682 /// target-independent logic.
1684 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1685 unsigned DstAlign, unsigned SrcAlign,
1686 bool IsMemset, bool ZeroMemset,
1688 MachineFunction &MF) const {
1689 const Function *F = MF.getFunction();
1690 if ((!IsMemset || ZeroMemset) &&
1691 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1692 Attribute::NoImplicitFloat)) {
1694 (Subtarget->isUnalignedMemAccessFast() ||
1695 ((DstAlign == 0 || DstAlign >= 16) &&
1696 (SrcAlign == 0 || SrcAlign >= 16)))) {
1698 if (Subtarget->hasInt256())
1700 if (Subtarget->hasFp256())
1703 if (Subtarget->hasSSE2())
1705 if (Subtarget->hasSSE1())
1707 } else if (!MemcpyStrSrc && Size >= 8 &&
1708 !Subtarget->is64Bit() &&
1709 Subtarget->hasSSE2()) {
1710 // Do not use f64 to lower memcpy if source is string constant. It's
1711 // better to use i32 to avoid the loads.
1715 if (Subtarget->is64Bit() && Size >= 8)
1720 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1722 return X86ScalarSSEf32;
1723 else if (VT == MVT::f64)
1724 return X86ScalarSSEf64;
1729 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1733 *Fast = Subtarget->isUnalignedMemAccessFast();
1737 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1738 /// current function. The returned value is a member of the
1739 /// MachineJumpTableInfo::JTEntryKind enum.
1740 unsigned X86TargetLowering::getJumpTableEncoding() const {
1741 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1743 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1744 Subtarget->isPICStyleGOT())
1745 return MachineJumpTableInfo::EK_Custom32;
1747 // Otherwise, use the normal jump table encoding heuristics.
1748 return TargetLowering::getJumpTableEncoding();
1752 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1753 const MachineBasicBlock *MBB,
1754 unsigned uid,MCContext &Ctx) const{
1755 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1756 Subtarget->isPICStyleGOT());
1757 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1759 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1760 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1763 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1765 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1766 SelectionDAG &DAG) const {
1767 if (!Subtarget->is64Bit())
1768 // This doesn't have SDLoc associated with it, but is not really the
1769 // same as a Register.
1770 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1774 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1775 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1777 const MCExpr *X86TargetLowering::
1778 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1779 MCContext &Ctx) const {
1780 // X86-64 uses RIP relative addressing based on the jump table label.
1781 if (Subtarget->isPICStyleRIPRel())
1782 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1784 // Otherwise, the reference is relative to the PIC base.
1785 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1788 // FIXME: Why this routine is here? Move to RegInfo!
1789 std::pair<const TargetRegisterClass*, uint8_t>
1790 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1791 const TargetRegisterClass *RRC = nullptr;
1793 switch (VT.SimpleTy) {
1795 return TargetLowering::findRepresentativeClass(VT);
1796 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1797 RRC = Subtarget->is64Bit() ?
1798 (const TargetRegisterClass*)&X86::GR64RegClass :
1799 (const TargetRegisterClass*)&X86::GR32RegClass;
1802 RRC = &X86::VR64RegClass;
1804 case MVT::f32: case MVT::f64:
1805 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1806 case MVT::v4f32: case MVT::v2f64:
1807 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1809 RRC = &X86::VR128RegClass;
1812 return std::make_pair(RRC, Cost);
1815 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1816 unsigned &Offset) const {
1817 if (!Subtarget->isTargetLinux())
1820 if (Subtarget->is64Bit()) {
1821 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1823 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1835 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1836 unsigned DestAS) const {
1837 assert(SrcAS != DestAS && "Expected different address spaces!");
1839 return SrcAS < 256 && DestAS < 256;
1842 //===----------------------------------------------------------------------===//
1843 // Return Value Calling Convention Implementation
1844 //===----------------------------------------------------------------------===//
1846 #include "X86GenCallingConv.inc"
1849 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1850 MachineFunction &MF, bool isVarArg,
1851 const SmallVectorImpl<ISD::OutputArg> &Outs,
1852 LLVMContext &Context) const {
1853 SmallVector<CCValAssign, 16> RVLocs;
1854 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
1856 return CCInfo.CheckReturn(Outs, RetCC_X86);
1859 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1860 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1865 X86TargetLowering::LowerReturn(SDValue Chain,
1866 CallingConv::ID CallConv, bool isVarArg,
1867 const SmallVectorImpl<ISD::OutputArg> &Outs,
1868 const SmallVectorImpl<SDValue> &OutVals,
1869 SDLoc dl, SelectionDAG &DAG) const {
1870 MachineFunction &MF = DAG.getMachineFunction();
1871 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1873 SmallVector<CCValAssign, 16> RVLocs;
1874 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
1875 RVLocs, *DAG.getContext());
1876 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1879 SmallVector<SDValue, 6> RetOps;
1880 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1881 // Operand #1 = Bytes To Pop
1882 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1885 // Copy the result values into the output registers.
1886 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1887 CCValAssign &VA = RVLocs[i];
1888 assert(VA.isRegLoc() && "Can only return in registers!");
1889 SDValue ValToCopy = OutVals[i];
1890 EVT ValVT = ValToCopy.getValueType();
1892 // Promote values to the appropriate types
1893 if (VA.getLocInfo() == CCValAssign::SExt)
1894 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1895 else if (VA.getLocInfo() == CCValAssign::ZExt)
1896 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1897 else if (VA.getLocInfo() == CCValAssign::AExt)
1898 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1899 else if (VA.getLocInfo() == CCValAssign::BCvt)
1900 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1902 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1903 "Unexpected FP-extend for return value.");
1905 // If this is x86-64, and we disabled SSE, we can't return FP values,
1906 // or SSE or MMX vectors.
1907 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1908 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1909 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1910 report_fatal_error("SSE register return with SSE disabled");
1912 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1913 // llvm-gcc has never done it right and no one has noticed, so this
1914 // should be OK for now.
1915 if (ValVT == MVT::f64 &&
1916 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1917 report_fatal_error("SSE2 register return with SSE2 disabled");
1919 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1920 // the RET instruction and handled by the FP Stackifier.
1921 if (VA.getLocReg() == X86::ST0 ||
1922 VA.getLocReg() == X86::ST1) {
1923 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1924 // change the value to the FP stack register class.
1925 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1926 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1927 RetOps.push_back(ValToCopy);
1928 // Don't emit a copytoreg.
1932 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1933 // which is returned in RAX / RDX.
1934 if (Subtarget->is64Bit()) {
1935 if (ValVT == MVT::x86mmx) {
1936 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1937 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1938 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1940 // If we don't have SSE2 available, convert to v4f32 so the generated
1941 // register is legal.
1942 if (!Subtarget->hasSSE2())
1943 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1948 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1949 Flag = Chain.getValue(1);
1950 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1953 // The x86-64 ABIs require that for returning structs by value we copy
1954 // the sret argument into %rax/%eax (depending on ABI) for the return.
1955 // Win32 requires us to put the sret argument to %eax as well.
1956 // We saved the argument into a virtual register in the entry block,
1957 // so now we copy the value out and into %rax/%eax.
1958 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1959 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1960 MachineFunction &MF = DAG.getMachineFunction();
1961 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1962 unsigned Reg = FuncInfo->getSRetReturnReg();
1964 "SRetReturnReg should have been set in LowerFormalArguments().");
1965 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1968 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1969 X86::RAX : X86::EAX;
1970 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1971 Flag = Chain.getValue(1);
1973 // RAX/EAX now acts like a return value.
1974 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1977 RetOps[0] = Chain; // Update chain.
1979 // Add the flag if we have it.
1981 RetOps.push_back(Flag);
1983 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1986 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1987 if (N->getNumValues() != 1)
1989 if (!N->hasNUsesOfValue(1, 0))
1992 SDValue TCChain = Chain;
1993 SDNode *Copy = *N->use_begin();
1994 if (Copy->getOpcode() == ISD::CopyToReg) {
1995 // If the copy has a glue operand, we conservatively assume it isn't safe to
1996 // perform a tail call.
1997 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1999 TCChain = Copy->getOperand(0);
2000 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2003 bool HasRet = false;
2004 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2006 if (UI->getOpcode() != X86ISD::RET_FLAG)
2019 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
2020 ISD::NodeType ExtendKind) const {
2022 // TODO: Is this also valid on 32-bit?
2023 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2024 ReturnMVT = MVT::i8;
2026 ReturnMVT = MVT::i32;
2028 MVT MinVT = getRegisterType(ReturnMVT);
2029 return VT.bitsLT(MinVT) ? MinVT : VT;
2032 /// LowerCallResult - Lower the result values of a call into the
2033 /// appropriate copies out of appropriate physical registers.
2036 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2037 CallingConv::ID CallConv, bool isVarArg,
2038 const SmallVectorImpl<ISD::InputArg> &Ins,
2039 SDLoc dl, SelectionDAG &DAG,
2040 SmallVectorImpl<SDValue> &InVals) const {
2042 // Assign locations to each value returned by this call.
2043 SmallVector<CCValAssign, 16> RVLocs;
2044 bool Is64Bit = Subtarget->is64Bit();
2045 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2046 DAG.getTarget(), RVLocs, *DAG.getContext());
2047 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2049 // Copy all of the result registers out of their specified physreg.
2050 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2051 CCValAssign &VA = RVLocs[i];
2052 EVT CopyVT = VA.getValVT();
2054 // If this is x86-64, and we disabled SSE, we can't return FP values
2055 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2056 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2057 report_fatal_error("SSE register return with SSE disabled");
2062 // If this is a call to a function that returns an fp value on the floating
2063 // point stack, we must guarantee the value is popped from the stack, so
2064 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2065 // if the return value is not used. We use the FpPOP_RETVAL instruction
2067 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2068 // If we prefer to use the value in xmm registers, copy it out as f80 and
2069 // use a truncate to move it from fp stack reg to xmm reg.
2070 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2071 SDValue Ops[] = { Chain, InFlag };
2072 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2073 MVT::Other, MVT::Glue, Ops), 1);
2074 Val = Chain.getValue(0);
2076 // Round the f80 to the right size, which also moves it to the appropriate
2078 if (CopyVT != VA.getValVT())
2079 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2080 // This truncation won't change the value.
2081 DAG.getIntPtrConstant(1));
2083 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2084 CopyVT, InFlag).getValue(1);
2085 Val = Chain.getValue(0);
2087 InFlag = Chain.getValue(2);
2088 InVals.push_back(Val);
2094 //===----------------------------------------------------------------------===//
2095 // C & StdCall & Fast Calling Convention implementation
2096 //===----------------------------------------------------------------------===//
2097 // StdCall calling convention seems to be standard for many Windows' API
2098 // routines and around. It differs from C calling convention just a little:
2099 // callee should clean up the stack, not caller. Symbols should be also
2100 // decorated in some fancy way :) It doesn't support any vector arguments.
2101 // For info on fast calling convention see Fast Calling Convention (tail call)
2102 // implementation LowerX86_32FastCCCallTo.
2104 /// CallIsStructReturn - Determines whether a call uses struct return
2106 enum StructReturnType {
2111 static StructReturnType
2112 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2114 return NotStructReturn;
2116 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2117 if (!Flags.isSRet())
2118 return NotStructReturn;
2119 if (Flags.isInReg())
2120 return RegStructReturn;
2121 return StackStructReturn;
2124 /// ArgsAreStructReturn - Determines whether a function uses struct
2125 /// return semantics.
2126 static StructReturnType
2127 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2129 return NotStructReturn;
2131 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2132 if (!Flags.isSRet())
2133 return NotStructReturn;
2134 if (Flags.isInReg())
2135 return RegStructReturn;
2136 return StackStructReturn;
2139 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2140 /// by "Src" to address "Dst" with size and alignment information specified by
2141 /// the specific parameter attribute. The copy will be passed as a byval
2142 /// function parameter.
2144 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2145 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2147 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2149 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2150 /*isVolatile*/false, /*AlwaysInline=*/true,
2151 MachinePointerInfo(), MachinePointerInfo());
2154 /// IsTailCallConvention - Return true if the calling convention is one that
2155 /// supports tail call optimization.
2156 static bool IsTailCallConvention(CallingConv::ID CC) {
2157 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2158 CC == CallingConv::HiPE);
2161 /// \brief Return true if the calling convention is a C calling convention.
2162 static bool IsCCallConvention(CallingConv::ID CC) {
2163 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2164 CC == CallingConv::X86_64_SysV);
2167 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2168 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2172 CallingConv::ID CalleeCC = CS.getCallingConv();
2173 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2179 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2180 /// a tailcall target by changing its ABI.
2181 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2182 bool GuaranteedTailCallOpt) {
2183 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2187 X86TargetLowering::LowerMemArgument(SDValue Chain,
2188 CallingConv::ID CallConv,
2189 const SmallVectorImpl<ISD::InputArg> &Ins,
2190 SDLoc dl, SelectionDAG &DAG,
2191 const CCValAssign &VA,
2192 MachineFrameInfo *MFI,
2194 // Create the nodes corresponding to a load from this parameter slot.
2195 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2196 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2197 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2198 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2201 // If value is passed by pointer we have address passed instead of the value
2203 if (VA.getLocInfo() == CCValAssign::Indirect)
2204 ValVT = VA.getLocVT();
2206 ValVT = VA.getValVT();
2208 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2209 // changed with more analysis.
2210 // In case of tail call optimization mark all arguments mutable. Since they
2211 // could be overwritten by lowering of arguments in case of a tail call.
2212 if (Flags.isByVal()) {
2213 unsigned Bytes = Flags.getByValSize();
2214 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2215 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2216 return DAG.getFrameIndex(FI, getPointerTy());
2218 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2219 VA.getLocMemOffset(), isImmutable);
2220 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2221 return DAG.getLoad(ValVT, dl, Chain, FIN,
2222 MachinePointerInfo::getFixedStack(FI),
2223 false, false, false, 0);
2228 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2229 CallingConv::ID CallConv,
2231 const SmallVectorImpl<ISD::InputArg> &Ins,
2234 SmallVectorImpl<SDValue> &InVals)
2236 MachineFunction &MF = DAG.getMachineFunction();
2237 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2239 const Function* Fn = MF.getFunction();
2240 if (Fn->hasExternalLinkage() &&
2241 Subtarget->isTargetCygMing() &&
2242 Fn->getName() == "main")
2243 FuncInfo->setForceFramePointer(true);
2245 MachineFrameInfo *MFI = MF.getFrameInfo();
2246 bool Is64Bit = Subtarget->is64Bit();
2247 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2249 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2250 "Var args not supported with calling convention fastcc, ghc or hipe");
2252 // Assign locations to all of the incoming arguments.
2253 SmallVector<CCValAssign, 16> ArgLocs;
2254 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
2255 ArgLocs, *DAG.getContext());
2257 // Allocate shadow area for Win64
2259 CCInfo.AllocateStack(32, 8);
2261 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2263 unsigned LastVal = ~0U;
2265 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2266 CCValAssign &VA = ArgLocs[i];
2267 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2269 assert(VA.getValNo() != LastVal &&
2270 "Don't support value assigned to multiple locs yet");
2272 LastVal = VA.getValNo();
2274 if (VA.isRegLoc()) {
2275 EVT RegVT = VA.getLocVT();
2276 const TargetRegisterClass *RC;
2277 if (RegVT == MVT::i32)
2278 RC = &X86::GR32RegClass;
2279 else if (Is64Bit && RegVT == MVT::i64)
2280 RC = &X86::GR64RegClass;
2281 else if (RegVT == MVT::f32)
2282 RC = &X86::FR32RegClass;
2283 else if (RegVT == MVT::f64)
2284 RC = &X86::FR64RegClass;
2285 else if (RegVT.is512BitVector())
2286 RC = &X86::VR512RegClass;
2287 else if (RegVT.is256BitVector())
2288 RC = &X86::VR256RegClass;
2289 else if (RegVT.is128BitVector())
2290 RC = &X86::VR128RegClass;
2291 else if (RegVT == MVT::x86mmx)
2292 RC = &X86::VR64RegClass;
2293 else if (RegVT == MVT::i1)
2294 RC = &X86::VK1RegClass;
2295 else if (RegVT == MVT::v8i1)
2296 RC = &X86::VK8RegClass;
2297 else if (RegVT == MVT::v16i1)
2298 RC = &X86::VK16RegClass;
2300 llvm_unreachable("Unknown argument type!");
2302 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2303 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2305 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2306 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2308 if (VA.getLocInfo() == CCValAssign::SExt)
2309 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2310 DAG.getValueType(VA.getValVT()));
2311 else if (VA.getLocInfo() == CCValAssign::ZExt)
2312 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2313 DAG.getValueType(VA.getValVT()));
2314 else if (VA.getLocInfo() == CCValAssign::BCvt)
2315 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2317 if (VA.isExtInLoc()) {
2318 // Handle MMX values passed in XMM regs.
2319 if (RegVT.isVector())
2320 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2322 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2325 assert(VA.isMemLoc());
2326 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2329 // If value is passed via pointer - do a load.
2330 if (VA.getLocInfo() == CCValAssign::Indirect)
2331 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2332 MachinePointerInfo(), false, false, false, 0);
2334 InVals.push_back(ArgValue);
2337 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2338 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2339 // The x86-64 ABIs require that for returning structs by value we copy
2340 // the sret argument into %rax/%eax (depending on ABI) for the return.
2341 // Win32 requires us to put the sret argument to %eax as well.
2342 // Save the argument into a virtual register so that we can access it
2343 // from the return points.
2344 if (Ins[i].Flags.isSRet()) {
2345 unsigned Reg = FuncInfo->getSRetReturnReg();
2347 MVT PtrTy = getPointerTy();
2348 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2349 FuncInfo->setSRetReturnReg(Reg);
2351 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2352 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2358 unsigned StackSize = CCInfo.getNextStackOffset();
2359 // Align stack specially for tail calls.
2360 if (FuncIsMadeTailCallSafe(CallConv,
2361 MF.getTarget().Options.GuaranteedTailCallOpt))
2362 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2364 // If the function takes variable number of arguments, make a frame index for
2365 // the start of the first vararg value... for expansion of llvm.va_start.
2367 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2368 CallConv != CallingConv::X86_ThisCall)) {
2369 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2372 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2374 // FIXME: We should really autogenerate these arrays
2375 static const MCPhysReg GPR64ArgRegsWin64[] = {
2376 X86::RCX, X86::RDX, X86::R8, X86::R9
2378 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2379 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2381 static const MCPhysReg XMMArgRegs64Bit[] = {
2382 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2383 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2385 const MCPhysReg *GPR64ArgRegs;
2386 unsigned NumXMMRegs = 0;
2389 // The XMM registers which might contain var arg parameters are shadowed
2390 // in their paired GPR. So we only need to save the GPR to their home
2392 TotalNumIntRegs = 4;
2393 GPR64ArgRegs = GPR64ArgRegsWin64;
2395 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2396 GPR64ArgRegs = GPR64ArgRegs64Bit;
2398 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2401 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2404 bool NoImplicitFloatOps = Fn->getAttributes().
2405 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2406 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2407 "SSE register cannot be used when SSE is disabled!");
2408 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2409 NoImplicitFloatOps) &&
2410 "SSE register cannot be used when SSE is disabled!");
2411 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2412 !Subtarget->hasSSE1())
2413 // Kernel mode asks for SSE to be disabled, so don't push them
2415 TotalNumXMMRegs = 0;
2418 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
2419 // Get to the caller-allocated home save location. Add 8 to account
2420 // for the return address.
2421 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2422 FuncInfo->setRegSaveFrameIndex(
2423 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2424 // Fixup to set vararg frame on shadow area (4 x i64).
2426 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2428 // For X86-64, if there are vararg parameters that are passed via
2429 // registers, then we must store them to their spots on the stack so
2430 // they may be loaded by deferencing the result of va_next.
2431 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2432 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2433 FuncInfo->setRegSaveFrameIndex(
2434 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2438 // Store the integer parameter registers.
2439 SmallVector<SDValue, 8> MemOps;
2440 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2442 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2443 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2444 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2445 DAG.getIntPtrConstant(Offset));
2446 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2447 &X86::GR64RegClass);
2448 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2450 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2451 MachinePointerInfo::getFixedStack(
2452 FuncInfo->getRegSaveFrameIndex(), Offset),
2454 MemOps.push_back(Store);
2458 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2459 // Now store the XMM (fp + vector) parameter registers.
2460 SmallVector<SDValue, 11> SaveXMMOps;
2461 SaveXMMOps.push_back(Chain);
2463 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2464 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2465 SaveXMMOps.push_back(ALVal);
2467 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2468 FuncInfo->getRegSaveFrameIndex()));
2469 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2470 FuncInfo->getVarArgsFPOffset()));
2472 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2473 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2474 &X86::VR128RegClass);
2475 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2476 SaveXMMOps.push_back(Val);
2478 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2479 MVT::Other, SaveXMMOps));
2482 if (!MemOps.empty())
2483 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2487 // Some CCs need callee pop.
2488 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2489 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2490 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2492 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2493 // If this is an sret function, the return should pop the hidden pointer.
2494 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2495 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2496 argsAreStructReturn(Ins) == StackStructReturn)
2497 FuncInfo->setBytesToPopOnReturn(4);
2501 // RegSaveFrameIndex is X86-64 only.
2502 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2503 if (CallConv == CallingConv::X86_FastCall ||
2504 CallConv == CallingConv::X86_ThisCall)
2505 // fastcc functions can't have varargs.
2506 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2509 FuncInfo->setArgumentStackSize(StackSize);
2515 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2516 SDValue StackPtr, SDValue Arg,
2517 SDLoc dl, SelectionDAG &DAG,
2518 const CCValAssign &VA,
2519 ISD::ArgFlagsTy Flags) const {
2520 unsigned LocMemOffset = VA.getLocMemOffset();
2521 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2522 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2523 if (Flags.isByVal())
2524 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2526 return DAG.getStore(Chain, dl, Arg, PtrOff,
2527 MachinePointerInfo::getStack(LocMemOffset),
2531 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2532 /// optimization is performed and it is required.
2534 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2535 SDValue &OutRetAddr, SDValue Chain,
2536 bool IsTailCall, bool Is64Bit,
2537 int FPDiff, SDLoc dl) const {
2538 // Adjust the Return address stack slot.
2539 EVT VT = getPointerTy();
2540 OutRetAddr = getReturnAddressFrameIndex(DAG);
2542 // Load the "old" Return address.
2543 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2544 false, false, false, 0);
2545 return SDValue(OutRetAddr.getNode(), 1);
2548 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2549 /// optimization is performed and it is required (FPDiff!=0).
2550 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2551 SDValue Chain, SDValue RetAddrFrIdx,
2552 EVT PtrVT, unsigned SlotSize,
2553 int FPDiff, SDLoc dl) {
2554 // Store the return address to the appropriate stack slot.
2555 if (!FPDiff) return Chain;
2556 // Calculate the new stack slot for the return address.
2557 int NewReturnAddrFI =
2558 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2560 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2561 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2562 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2568 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2569 SmallVectorImpl<SDValue> &InVals) const {
2570 SelectionDAG &DAG = CLI.DAG;
2572 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2573 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2574 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2575 SDValue Chain = CLI.Chain;
2576 SDValue Callee = CLI.Callee;
2577 CallingConv::ID CallConv = CLI.CallConv;
2578 bool &isTailCall = CLI.IsTailCall;
2579 bool isVarArg = CLI.IsVarArg;
2581 MachineFunction &MF = DAG.getMachineFunction();
2582 bool Is64Bit = Subtarget->is64Bit();
2583 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2584 StructReturnType SR = callIsStructReturn(Outs);
2585 bool IsSibcall = false;
2587 if (MF.getTarget().Options.DisableTailCalls)
2590 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2592 // Force this to be a tail call. The verifier rules are enough to ensure
2593 // that we can lower this successfully without moving the return address
2596 } else if (isTailCall) {
2597 // Check if it's really possible to do a tail call.
2598 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2599 isVarArg, SR != NotStructReturn,
2600 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2601 Outs, OutVals, Ins, DAG);
2603 // Sibcalls are automatically detected tailcalls which do not require
2605 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2612 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2613 "Var args not supported with calling convention fastcc, ghc or hipe");
2615 // Analyze operands of the call, assigning locations to each operand.
2616 SmallVector<CCValAssign, 16> ArgLocs;
2617 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
2618 ArgLocs, *DAG.getContext());
2620 // Allocate shadow area for Win64
2622 CCInfo.AllocateStack(32, 8);
2624 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2626 // Get a count of how many bytes are to be pushed on the stack.
2627 unsigned NumBytes = CCInfo.getNextStackOffset();
2629 // This is a sibcall. The memory operands are available in caller's
2630 // own caller's stack.
2632 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2633 IsTailCallConvention(CallConv))
2634 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2637 if (isTailCall && !IsSibcall && !IsMustTail) {
2638 // Lower arguments at fp - stackoffset + fpdiff.
2639 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2640 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2642 FPDiff = NumBytesCallerPushed - NumBytes;
2644 // Set the delta of movement of the returnaddr stackslot.
2645 // But only set if delta is greater than previous delta.
2646 if (FPDiff < X86Info->getTCReturnAddrDelta())
2647 X86Info->setTCReturnAddrDelta(FPDiff);
2650 unsigned NumBytesToPush = NumBytes;
2651 unsigned NumBytesToPop = NumBytes;
2653 // If we have an inalloca argument, all stack space has already been allocated
2654 // for us and be right at the top of the stack. We don't support multiple
2655 // arguments passed in memory when using inalloca.
2656 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2658 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2659 "an inalloca argument must be the only memory argument");
2663 Chain = DAG.getCALLSEQ_START(
2664 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2666 SDValue RetAddrFrIdx;
2667 // Load return address for tail calls.
2668 if (isTailCall && FPDiff)
2669 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2670 Is64Bit, FPDiff, dl);
2672 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2673 SmallVector<SDValue, 8> MemOpChains;
2676 // Walk the register/memloc assignments, inserting copies/loads. In the case
2677 // of tail call optimization arguments are handle later.
2678 const X86RegisterInfo *RegInfo =
2679 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
2680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2681 // Skip inalloca arguments, they have already been written.
2682 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2683 if (Flags.isInAlloca())
2686 CCValAssign &VA = ArgLocs[i];
2687 EVT RegVT = VA.getLocVT();
2688 SDValue Arg = OutVals[i];
2689 bool isByVal = Flags.isByVal();
2691 // Promote the value if needed.
2692 switch (VA.getLocInfo()) {
2693 default: llvm_unreachable("Unknown loc info!");
2694 case CCValAssign::Full: break;
2695 case CCValAssign::SExt:
2696 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2698 case CCValAssign::ZExt:
2699 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2701 case CCValAssign::AExt:
2702 if (RegVT.is128BitVector()) {
2703 // Special case: passing MMX values in XMM registers.
2704 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2705 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2706 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2708 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2710 case CCValAssign::BCvt:
2711 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2713 case CCValAssign::Indirect: {
2714 // Store the argument.
2715 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2716 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2717 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2718 MachinePointerInfo::getFixedStack(FI),
2725 if (VA.isRegLoc()) {
2726 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2727 if (isVarArg && IsWin64) {
2728 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2729 // shadow reg if callee is a varargs function.
2730 unsigned ShadowReg = 0;
2731 switch (VA.getLocReg()) {
2732 case X86::XMM0: ShadowReg = X86::RCX; break;
2733 case X86::XMM1: ShadowReg = X86::RDX; break;
2734 case X86::XMM2: ShadowReg = X86::R8; break;
2735 case X86::XMM3: ShadowReg = X86::R9; break;
2738 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2740 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2741 assert(VA.isMemLoc());
2742 if (!StackPtr.getNode())
2743 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2745 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2746 dl, DAG, VA, Flags));
2750 if (!MemOpChains.empty())
2751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2753 if (Subtarget->isPICStyleGOT()) {
2754 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2757 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2758 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2760 // If we are tail calling and generating PIC/GOT style code load the
2761 // address of the callee into ECX. The value in ecx is used as target of
2762 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2763 // for tail calls on PIC/GOT architectures. Normally we would just put the
2764 // address of GOT into ebx and then call target@PLT. But for tail calls
2765 // ebx would be restored (since ebx is callee saved) before jumping to the
2768 // Note: The actual moving to ECX is done further down.
2769 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2770 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2771 !G->getGlobal()->hasProtectedVisibility())
2772 Callee = LowerGlobalAddress(Callee, DAG);
2773 else if (isa<ExternalSymbolSDNode>(Callee))
2774 Callee = LowerExternalSymbol(Callee, DAG);
2778 if (Is64Bit && isVarArg && !IsWin64) {
2779 // From AMD64 ABI document:
2780 // For calls that may call functions that use varargs or stdargs
2781 // (prototype-less calls or calls to functions containing ellipsis (...) in
2782 // the declaration) %al is used as hidden argument to specify the number
2783 // of SSE registers used. The contents of %al do not need to match exactly
2784 // the number of registers, but must be an ubound on the number of SSE
2785 // registers used and is in the range 0 - 8 inclusive.
2787 // Count the number of XMM registers allocated.
2788 static const MCPhysReg XMMArgRegs[] = {
2789 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2790 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2792 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2793 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2794 && "SSE registers cannot be used when SSE is disabled");
2796 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2797 DAG.getConstant(NumXMMRegs, MVT::i8)));
2800 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2801 // don't need this because the eligibility check rejects calls that require
2802 // shuffling arguments passed in memory.
2803 if (!IsSibcall && isTailCall) {
2804 // Force all the incoming stack arguments to be loaded from the stack
2805 // before any new outgoing arguments are stored to the stack, because the
2806 // outgoing stack slots may alias the incoming argument stack slots, and
2807 // the alias isn't otherwise explicit. This is slightly more conservative
2808 // than necessary, because it means that each store effectively depends
2809 // on every argument instead of just those arguments it would clobber.
2810 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2812 SmallVector<SDValue, 8> MemOpChains2;
2815 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2816 CCValAssign &VA = ArgLocs[i];
2819 assert(VA.isMemLoc());
2820 SDValue Arg = OutVals[i];
2821 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2822 // Skip inalloca arguments. They don't require any work.
2823 if (Flags.isInAlloca())
2825 // Create frame index.
2826 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2827 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2828 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2829 FIN = DAG.getFrameIndex(FI, getPointerTy());
2831 if (Flags.isByVal()) {
2832 // Copy relative to framepointer.
2833 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2834 if (!StackPtr.getNode())
2835 StackPtr = DAG.getCopyFromReg(Chain, dl,
2836 RegInfo->getStackRegister(),
2838 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2840 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2844 // Store relative to framepointer.
2845 MemOpChains2.push_back(
2846 DAG.getStore(ArgChain, dl, Arg, FIN,
2847 MachinePointerInfo::getFixedStack(FI),
2852 if (!MemOpChains2.empty())
2853 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2855 // Store the return address to the appropriate stack slot.
2856 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2857 getPointerTy(), RegInfo->getSlotSize(),
2861 // Build a sequence of copy-to-reg nodes chained together with token chain
2862 // and flag operands which copy the outgoing args into registers.
2864 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2865 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2866 RegsToPass[i].second, InFlag);
2867 InFlag = Chain.getValue(1);
2870 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2871 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2872 // In the 64-bit large code model, we have to make all calls
2873 // through a register, since the call instruction's 32-bit
2874 // pc-relative offset may not be large enough to hold the whole
2876 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2877 // If the callee is a GlobalAddress node (quite common, every direct call
2878 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2881 // We should use extra load for direct calls to dllimported functions in
2883 const GlobalValue *GV = G->getGlobal();
2884 if (!GV->hasDLLImportStorageClass()) {
2885 unsigned char OpFlags = 0;
2886 bool ExtraLoad = false;
2887 unsigned WrapperKind = ISD::DELETED_NODE;
2889 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2890 // external symbols most go through the PLT in PIC mode. If the symbol
2891 // has hidden or protected visibility, or if it is static or local, then
2892 // we don't need to use the PLT - we can directly call it.
2893 if (Subtarget->isTargetELF() &&
2894 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2895 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2896 OpFlags = X86II::MO_PLT;
2897 } else if (Subtarget->isPICStyleStubAny() &&
2898 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2899 (!Subtarget->getTargetTriple().isMacOSX() ||
2900 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2901 // PC-relative references to external symbols should go through $stub,
2902 // unless we're building with the leopard linker or later, which
2903 // automatically synthesizes these stubs.
2904 OpFlags = X86II::MO_DARWIN_STUB;
2905 } else if (Subtarget->isPICStyleRIPRel() &&
2906 isa<Function>(GV) &&
2907 cast<Function>(GV)->getAttributes().
2908 hasAttribute(AttributeSet::FunctionIndex,
2909 Attribute::NonLazyBind)) {
2910 // If the function is marked as non-lazy, generate an indirect call
2911 // which loads from the GOT directly. This avoids runtime overhead
2912 // at the cost of eager binding (and one extra byte of encoding).
2913 OpFlags = X86II::MO_GOTPCREL;
2914 WrapperKind = X86ISD::WrapperRIP;
2918 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2919 G->getOffset(), OpFlags);
2921 // Add a wrapper if needed.
2922 if (WrapperKind != ISD::DELETED_NODE)
2923 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2924 // Add extra indirection if needed.
2926 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2927 MachinePointerInfo::getGOT(),
2928 false, false, false, 0);
2930 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2931 unsigned char OpFlags = 0;
2933 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2934 // external symbols should go through the PLT.
2935 if (Subtarget->isTargetELF() &&
2936 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2937 OpFlags = X86II::MO_PLT;
2938 } else if (Subtarget->isPICStyleStubAny() &&
2939 (!Subtarget->getTargetTriple().isMacOSX() ||
2940 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2941 // PC-relative references to external symbols should go through $stub,
2942 // unless we're building with the leopard linker or later, which
2943 // automatically synthesizes these stubs.
2944 OpFlags = X86II::MO_DARWIN_STUB;
2947 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2951 // Returns a chain & a flag for retval copy to use.
2952 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2953 SmallVector<SDValue, 8> Ops;
2955 if (!IsSibcall && isTailCall) {
2956 Chain = DAG.getCALLSEQ_END(Chain,
2957 DAG.getIntPtrConstant(NumBytesToPop, true),
2958 DAG.getIntPtrConstant(0, true), InFlag, dl);
2959 InFlag = Chain.getValue(1);
2962 Ops.push_back(Chain);
2963 Ops.push_back(Callee);
2966 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2968 // Add argument registers to the end of the list so that they are known live
2970 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2971 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2972 RegsToPass[i].second.getValueType()));
2974 // Add a register mask operand representing the call-preserved registers.
2975 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
2976 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2977 assert(Mask && "Missing call preserved mask for calling convention");
2978 Ops.push_back(DAG.getRegisterMask(Mask));
2980 if (InFlag.getNode())
2981 Ops.push_back(InFlag);
2985 //// If this is the first return lowered for this function, add the regs
2986 //// to the liveout set for the function.
2987 // This isn't right, although it's probably harmless on x86; liveouts
2988 // should be computed from returns not tail calls. Consider a void
2989 // function making a tail call to a function returning int.
2990 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
2993 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
2994 InFlag = Chain.getValue(1);
2996 // Create the CALLSEQ_END node.
2997 unsigned NumBytesForCalleeToPop;
2998 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2999 DAG.getTarget().Options.GuaranteedTailCallOpt))
3000 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3001 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3002 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3003 SR == StackStructReturn)
3004 // If this is a call to a struct-return function, the callee
3005 // pops the hidden struct pointer, so we have to push it back.
3006 // This is common for Darwin/X86, Linux & Mingw32 targets.
3007 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3008 NumBytesForCalleeToPop = 4;
3010 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3012 // Returns a flag for retval copy to use.
3014 Chain = DAG.getCALLSEQ_END(Chain,
3015 DAG.getIntPtrConstant(NumBytesToPop, true),
3016 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3019 InFlag = Chain.getValue(1);
3022 // Handle result values, copying them out of physregs into vregs that we
3024 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3025 Ins, dl, DAG, InVals);
3028 //===----------------------------------------------------------------------===//
3029 // Fast Calling Convention (tail call) implementation
3030 //===----------------------------------------------------------------------===//
3032 // Like std call, callee cleans arguments, convention except that ECX is
3033 // reserved for storing the tail called function address. Only 2 registers are
3034 // free for argument passing (inreg). Tail call optimization is performed
3036 // * tailcallopt is enabled
3037 // * caller/callee are fastcc
3038 // On X86_64 architecture with GOT-style position independent code only local
3039 // (within module) calls are supported at the moment.
3040 // To keep the stack aligned according to platform abi the function
3041 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3042 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3043 // If a tail called function callee has more arguments than the caller the
3044 // caller needs to make sure that there is room to move the RETADDR to. This is
3045 // achieved by reserving an area the size of the argument delta right after the
3046 // original REtADDR, but before the saved framepointer or the spilled registers
3047 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3059 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3060 /// for a 16 byte align requirement.
3062 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3063 SelectionDAG& DAG) const {
3064 MachineFunction &MF = DAG.getMachineFunction();
3065 const TargetMachine &TM = MF.getTarget();
3066 const X86RegisterInfo *RegInfo =
3067 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3068 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3069 unsigned StackAlignment = TFI.getStackAlignment();
3070 uint64_t AlignMask = StackAlignment - 1;
3071 int64_t Offset = StackSize;
3072 unsigned SlotSize = RegInfo->getSlotSize();
3073 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3074 // Number smaller than 12 so just add the difference.
3075 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3077 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3078 Offset = ((~AlignMask) & Offset) + StackAlignment +
3079 (StackAlignment-SlotSize);
3084 /// MatchingStackOffset - Return true if the given stack call argument is
3085 /// already available in the same position (relatively) of the caller's
3086 /// incoming argument stack.
3088 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3089 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3090 const X86InstrInfo *TII) {
3091 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3093 if (Arg.getOpcode() == ISD::CopyFromReg) {
3094 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3095 if (!TargetRegisterInfo::isVirtualRegister(VR))
3097 MachineInstr *Def = MRI->getVRegDef(VR);
3100 if (!Flags.isByVal()) {
3101 if (!TII->isLoadFromStackSlot(Def, FI))
3104 unsigned Opcode = Def->getOpcode();
3105 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3106 Def->getOperand(1).isFI()) {
3107 FI = Def->getOperand(1).getIndex();
3108 Bytes = Flags.getByValSize();
3112 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3113 if (Flags.isByVal())
3114 // ByVal argument is passed in as a pointer but it's now being
3115 // dereferenced. e.g.
3116 // define @foo(%struct.X* %A) {
3117 // tail call @bar(%struct.X* byval %A)
3120 SDValue Ptr = Ld->getBasePtr();
3121 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3124 FI = FINode->getIndex();
3125 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3126 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3127 FI = FINode->getIndex();
3128 Bytes = Flags.getByValSize();
3132 assert(FI != INT_MAX);
3133 if (!MFI->isFixedObjectIndex(FI))
3135 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3138 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3139 /// for tail call optimization. Targets which want to do tail call
3140 /// optimization should implement this function.
3142 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3143 CallingConv::ID CalleeCC,
3145 bool isCalleeStructRet,
3146 bool isCallerStructRet,
3148 const SmallVectorImpl<ISD::OutputArg> &Outs,
3149 const SmallVectorImpl<SDValue> &OutVals,
3150 const SmallVectorImpl<ISD::InputArg> &Ins,
3151 SelectionDAG &DAG) const {
3152 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3155 // If -tailcallopt is specified, make fastcc functions tail-callable.
3156 const MachineFunction &MF = DAG.getMachineFunction();
3157 const Function *CallerF = MF.getFunction();
3159 // If the function return type is x86_fp80 and the callee return type is not,
3160 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3161 // perform a tailcall optimization here.
3162 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3165 CallingConv::ID CallerCC = CallerF->getCallingConv();
3166 bool CCMatch = CallerCC == CalleeCC;
3167 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3168 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3170 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3171 if (IsTailCallConvention(CalleeCC) && CCMatch)
3176 // Look for obvious safe cases to perform tail call optimization that do not
3177 // require ABI changes. This is what gcc calls sibcall.
3179 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3180 // emit a special epilogue.
3181 const X86RegisterInfo *RegInfo =
3182 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3183 if (RegInfo->needsStackRealignment(MF))
3186 // Also avoid sibcall optimization if either caller or callee uses struct
3187 // return semantics.
3188 if (isCalleeStructRet || isCallerStructRet)
3191 // An stdcall/thiscall caller is expected to clean up its arguments; the
3192 // callee isn't going to do that.
3193 // FIXME: this is more restrictive than needed. We could produce a tailcall
3194 // when the stack adjustment matches. For example, with a thiscall that takes
3195 // only one argument.
3196 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3197 CallerCC == CallingConv::X86_ThisCall))
3200 // Do not sibcall optimize vararg calls unless all arguments are passed via
3202 if (isVarArg && !Outs.empty()) {
3204 // Optimizing for varargs on Win64 is unlikely to be safe without
3205 // additional testing.
3206 if (IsCalleeWin64 || IsCallerWin64)
3209 SmallVector<CCValAssign, 16> ArgLocs;
3210 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3211 DAG.getTarget(), ArgLocs, *DAG.getContext());
3213 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3214 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3215 if (!ArgLocs[i].isRegLoc())
3219 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3220 // stack. Therefore, if it's not used by the call it is not safe to optimize
3221 // this into a sibcall.
3222 bool Unused = false;
3223 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3230 SmallVector<CCValAssign, 16> RVLocs;
3231 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3232 DAG.getTarget(), RVLocs, *DAG.getContext());
3233 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3234 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3235 CCValAssign &VA = RVLocs[i];
3236 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3241 // If the calling conventions do not match, then we'd better make sure the
3242 // results are returned in the same way as what the caller expects.
3244 SmallVector<CCValAssign, 16> RVLocs1;
3245 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3246 DAG.getTarget(), RVLocs1, *DAG.getContext());
3247 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3249 SmallVector<CCValAssign, 16> RVLocs2;
3250 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3251 DAG.getTarget(), RVLocs2, *DAG.getContext());
3252 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3254 if (RVLocs1.size() != RVLocs2.size())
3256 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3257 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3259 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3261 if (RVLocs1[i].isRegLoc()) {
3262 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3265 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3271 // If the callee takes no arguments then go on to check the results of the
3273 if (!Outs.empty()) {
3274 // Check if stack adjustment is needed. For now, do not do this if any
3275 // argument is passed on the stack.
3276 SmallVector<CCValAssign, 16> ArgLocs;
3277 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3278 DAG.getTarget(), ArgLocs, *DAG.getContext());
3280 // Allocate shadow area for Win64
3282 CCInfo.AllocateStack(32, 8);
3284 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3285 if (CCInfo.getNextStackOffset()) {
3286 MachineFunction &MF = DAG.getMachineFunction();
3287 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3290 // Check if the arguments are already laid out in the right way as
3291 // the caller's fixed stack objects.
3292 MachineFrameInfo *MFI = MF.getFrameInfo();
3293 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3294 const X86InstrInfo *TII =
3295 static_cast<const X86InstrInfo *>(DAG.getTarget().getInstrInfo());
3296 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3297 CCValAssign &VA = ArgLocs[i];
3298 SDValue Arg = OutVals[i];
3299 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3300 if (VA.getLocInfo() == CCValAssign::Indirect)
3302 if (!VA.isRegLoc()) {
3303 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3310 // If the tailcall address may be in a register, then make sure it's
3311 // possible to register allocate for it. In 32-bit, the call address can
3312 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3313 // callee-saved registers are restored. These happen to be the same
3314 // registers used to pass 'inreg' arguments so watch out for those.
3315 if (!Subtarget->is64Bit() &&
3316 ((!isa<GlobalAddressSDNode>(Callee) &&
3317 !isa<ExternalSymbolSDNode>(Callee)) ||
3318 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3319 unsigned NumInRegs = 0;
3320 // In PIC we need an extra register to formulate the address computation
3322 unsigned MaxInRegs =
3323 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3325 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3326 CCValAssign &VA = ArgLocs[i];
3329 unsigned Reg = VA.getLocReg();
3332 case X86::EAX: case X86::EDX: case X86::ECX:
3333 if (++NumInRegs == MaxInRegs)
3345 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3346 const TargetLibraryInfo *libInfo) const {
3347 return X86::createFastISel(funcInfo, libInfo);
3350 //===----------------------------------------------------------------------===//
3351 // Other Lowering Hooks
3352 //===----------------------------------------------------------------------===//
3354 static bool MayFoldLoad(SDValue Op) {
3355 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3358 static bool MayFoldIntoStore(SDValue Op) {
3359 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3362 static bool isTargetShuffle(unsigned Opcode) {
3364 default: return false;
3365 case X86ISD::PSHUFD:
3366 case X86ISD::PSHUFHW:
3367 case X86ISD::PSHUFLW:
3369 case X86ISD::PALIGNR:
3370 case X86ISD::MOVLHPS:
3371 case X86ISD::MOVLHPD:
3372 case X86ISD::MOVHLPS:
3373 case X86ISD::MOVLPS:
3374 case X86ISD::MOVLPD:
3375 case X86ISD::MOVSHDUP:
3376 case X86ISD::MOVSLDUP:
3377 case X86ISD::MOVDDUP:
3380 case X86ISD::UNPCKL:
3381 case X86ISD::UNPCKH:
3382 case X86ISD::VPERMILP:
3383 case X86ISD::VPERM2X128:
3384 case X86ISD::VPERMI:
3389 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3390 SDValue V1, SelectionDAG &DAG) {
3392 default: llvm_unreachable("Unknown x86 shuffle node");
3393 case X86ISD::MOVSHDUP:
3394 case X86ISD::MOVSLDUP:
3395 case X86ISD::MOVDDUP:
3396 return DAG.getNode(Opc, dl, VT, V1);
3400 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3401 SDValue V1, unsigned TargetMask,
3402 SelectionDAG &DAG) {
3404 default: llvm_unreachable("Unknown x86 shuffle node");
3405 case X86ISD::PSHUFD:
3406 case X86ISD::PSHUFHW:
3407 case X86ISD::PSHUFLW:
3408 case X86ISD::VPERMILP:
3409 case X86ISD::VPERMI:
3410 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3414 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3415 SDValue V1, SDValue V2, unsigned TargetMask,
3416 SelectionDAG &DAG) {
3418 default: llvm_unreachable("Unknown x86 shuffle node");
3419 case X86ISD::PALIGNR:
3421 case X86ISD::VPERM2X128:
3422 return DAG.getNode(Opc, dl, VT, V1, V2,
3423 DAG.getConstant(TargetMask, MVT::i8));
3427 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3428 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3430 default: llvm_unreachable("Unknown x86 shuffle node");
3431 case X86ISD::MOVLHPS:
3432 case X86ISD::MOVLHPD:
3433 case X86ISD::MOVHLPS:
3434 case X86ISD::MOVLPS:
3435 case X86ISD::MOVLPD:
3438 case X86ISD::UNPCKL:
3439 case X86ISD::UNPCKH:
3440 return DAG.getNode(Opc, dl, VT, V1, V2);
3444 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3445 MachineFunction &MF = DAG.getMachineFunction();
3446 const X86RegisterInfo *RegInfo =
3447 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3448 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3449 int ReturnAddrIndex = FuncInfo->getRAIndex();
3451 if (ReturnAddrIndex == 0) {
3452 // Set up a frame object for the return address.
3453 unsigned SlotSize = RegInfo->getSlotSize();
3454 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3457 FuncInfo->setRAIndex(ReturnAddrIndex);
3460 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3463 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3464 bool hasSymbolicDisplacement) {
3465 // Offset should fit into 32 bit immediate field.
3466 if (!isInt<32>(Offset))
3469 // If we don't have a symbolic displacement - we don't have any extra
3471 if (!hasSymbolicDisplacement)
3474 // FIXME: Some tweaks might be needed for medium code model.
3475 if (M != CodeModel::Small && M != CodeModel::Kernel)
3478 // For small code model we assume that latest object is 16MB before end of 31
3479 // bits boundary. We may also accept pretty large negative constants knowing
3480 // that all objects are in the positive half of address space.
3481 if (M == CodeModel::Small && Offset < 16*1024*1024)
3484 // For kernel code model we know that all object resist in the negative half
3485 // of 32bits address space. We may not accept negative offsets, since they may
3486 // be just off and we may accept pretty large positive ones.
3487 if (M == CodeModel::Kernel && Offset > 0)
3493 /// isCalleePop - Determines whether the callee is required to pop its
3494 /// own arguments. Callee pop is necessary to support tail calls.
3495 bool X86::isCalleePop(CallingConv::ID CallingConv,
3496 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3500 switch (CallingConv) {
3503 case CallingConv::X86_StdCall:
3505 case CallingConv::X86_FastCall:
3507 case CallingConv::X86_ThisCall:
3509 case CallingConv::Fast:
3511 case CallingConv::GHC:
3513 case CallingConv::HiPE:
3518 /// \brief Return true if the condition is an unsigned comparison operation.
3519 static bool isX86CCUnsigned(unsigned X86CC) {
3521 default: llvm_unreachable("Invalid integer condition!");
3522 case X86::COND_E: return true;
3523 case X86::COND_G: return false;
3524 case X86::COND_GE: return false;
3525 case X86::COND_L: return false;
3526 case X86::COND_LE: return false;
3527 case X86::COND_NE: return true;
3528 case X86::COND_B: return true;
3529 case X86::COND_A: return true;
3530 case X86::COND_BE: return true;
3531 case X86::COND_AE: return true;
3533 llvm_unreachable("covered switch fell through?!");
3536 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3537 /// specific condition code, returning the condition code and the LHS/RHS of the
3538 /// comparison to make.
3539 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3540 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3542 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3543 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3544 // X > -1 -> X == 0, jump !sign.
3545 RHS = DAG.getConstant(0, RHS.getValueType());
3546 return X86::COND_NS;
3548 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3549 // X < 0 -> X == 0, jump on sign.
3552 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3554 RHS = DAG.getConstant(0, RHS.getValueType());
3555 return X86::COND_LE;
3559 switch (SetCCOpcode) {
3560 default: llvm_unreachable("Invalid integer condition!");
3561 case ISD::SETEQ: return X86::COND_E;
3562 case ISD::SETGT: return X86::COND_G;
3563 case ISD::SETGE: return X86::COND_GE;
3564 case ISD::SETLT: return X86::COND_L;
3565 case ISD::SETLE: return X86::COND_LE;
3566 case ISD::SETNE: return X86::COND_NE;
3567 case ISD::SETULT: return X86::COND_B;
3568 case ISD::SETUGT: return X86::COND_A;
3569 case ISD::SETULE: return X86::COND_BE;
3570 case ISD::SETUGE: return X86::COND_AE;
3574 // First determine if it is required or is profitable to flip the operands.
3576 // If LHS is a foldable load, but RHS is not, flip the condition.
3577 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3578 !ISD::isNON_EXTLoad(RHS.getNode())) {
3579 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3580 std::swap(LHS, RHS);
3583 switch (SetCCOpcode) {
3589 std::swap(LHS, RHS);
3593 // On a floating point condition, the flags are set as follows:
3595 // 0 | 0 | 0 | X > Y
3596 // 0 | 0 | 1 | X < Y
3597 // 1 | 0 | 0 | X == Y
3598 // 1 | 1 | 1 | unordered
3599 switch (SetCCOpcode) {
3600 default: llvm_unreachable("Condcode should be pre-legalized away");
3602 case ISD::SETEQ: return X86::COND_E;
3603 case ISD::SETOLT: // flipped
3605 case ISD::SETGT: return X86::COND_A;
3606 case ISD::SETOLE: // flipped
3608 case ISD::SETGE: return X86::COND_AE;
3609 case ISD::SETUGT: // flipped
3611 case ISD::SETLT: return X86::COND_B;
3612 case ISD::SETUGE: // flipped
3614 case ISD::SETLE: return X86::COND_BE;
3616 case ISD::SETNE: return X86::COND_NE;
3617 case ISD::SETUO: return X86::COND_P;
3618 case ISD::SETO: return X86::COND_NP;
3620 case ISD::SETUNE: return X86::COND_INVALID;
3624 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3625 /// code. Current x86 isa includes the following FP cmov instructions:
3626 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3627 static bool hasFPCMov(unsigned X86CC) {
3643 /// isFPImmLegal - Returns true if the target can instruction select the
3644 /// specified FP immediate natively. If false, the legalizer will
3645 /// materialize the FP immediate as a load from a constant pool.
3646 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3647 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3648 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3654 /// \brief Returns true if it is beneficial to convert a load of a constant
3655 /// to just the constant itself.
3656 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3658 assert(Ty->isIntegerTy());
3660 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3661 if (BitSize == 0 || BitSize > 64)
3666 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3667 /// the specified range (L, H].
3668 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3669 return (Val < 0) || (Val >= Low && Val < Hi);
3672 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3673 /// specified value.
3674 static bool isUndefOrEqual(int Val, int CmpVal) {
3675 return (Val < 0 || Val == CmpVal);
3678 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3679 /// from position Pos and ending in Pos+Size, falls within the specified
3680 /// sequential range (L, L+Pos]. or is undef.
3681 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3682 unsigned Pos, unsigned Size, int Low) {
3683 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3684 if (!isUndefOrEqual(Mask[i], Low))
3689 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3690 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3691 /// the second operand.
3692 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3693 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3694 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3695 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3696 return (Mask[0] < 2 && Mask[1] < 2);
3700 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3701 /// is suitable for input to PSHUFHW.
3702 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3703 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3706 // Lower quadword copied in order or undef.
3707 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3710 // Upper quadword shuffled.
3711 for (unsigned i = 4; i != 8; ++i)
3712 if (!isUndefOrInRange(Mask[i], 4, 8))
3715 if (VT == MVT::v16i16) {
3716 // Lower quadword copied in order or undef.
3717 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3720 // Upper quadword shuffled.
3721 for (unsigned i = 12; i != 16; ++i)
3722 if (!isUndefOrInRange(Mask[i], 12, 16))
3729 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3730 /// is suitable for input to PSHUFLW.
3731 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3732 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3735 // Upper quadword copied in order.
3736 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3739 // Lower quadword shuffled.
3740 for (unsigned i = 0; i != 4; ++i)
3741 if (!isUndefOrInRange(Mask[i], 0, 4))
3744 if (VT == MVT::v16i16) {
3745 // Upper quadword copied in order.
3746 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3749 // Lower quadword shuffled.
3750 for (unsigned i = 8; i != 12; ++i)
3751 if (!isUndefOrInRange(Mask[i], 8, 12))
3758 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3759 /// is suitable for input to PALIGNR.
3760 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3761 const X86Subtarget *Subtarget) {
3762 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3763 (VT.is256BitVector() && !Subtarget->hasInt256()))
3766 unsigned NumElts = VT.getVectorNumElements();
3767 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3768 unsigned NumLaneElts = NumElts/NumLanes;
3770 // Do not handle 64-bit element shuffles with palignr.
3771 if (NumLaneElts == 2)
3774 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3776 for (i = 0; i != NumLaneElts; ++i) {
3781 // Lane is all undef, go to next lane
3782 if (i == NumLaneElts)
3785 int Start = Mask[i+l];
3787 // Make sure its in this lane in one of the sources
3788 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3789 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3792 // If not lane 0, then we must match lane 0
3793 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3796 // Correct second source to be contiguous with first source
3797 if (Start >= (int)NumElts)
3798 Start -= NumElts - NumLaneElts;
3800 // Make sure we're shifting in the right direction.
3801 if (Start <= (int)(i+l))
3806 // Check the rest of the elements to see if they are consecutive.
3807 for (++i; i != NumLaneElts; ++i) {
3808 int Idx = Mask[i+l];
3810 // Make sure its in this lane
3811 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3812 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3815 // If not lane 0, then we must match lane 0
3816 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3819 if (Idx >= (int)NumElts)
3820 Idx -= NumElts - NumLaneElts;
3822 if (!isUndefOrEqual(Idx, Start+i))
3831 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3832 /// the two vector operands have swapped position.
3833 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3834 unsigned NumElems) {
3835 for (unsigned i = 0; i != NumElems; ++i) {
3839 else if (idx < (int)NumElems)
3840 Mask[i] = idx + NumElems;
3842 Mask[i] = idx - NumElems;
3846 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3847 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3848 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3849 /// reverse of what x86 shuffles want.
3850 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3852 unsigned NumElems = VT.getVectorNumElements();
3853 unsigned NumLanes = VT.getSizeInBits()/128;
3854 unsigned NumLaneElems = NumElems/NumLanes;
3856 if (NumLaneElems != 2 && NumLaneElems != 4)
3859 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3860 bool symetricMaskRequired =
3861 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3863 // VSHUFPSY divides the resulting vector into 4 chunks.
3864 // The sources are also splitted into 4 chunks, and each destination
3865 // chunk must come from a different source chunk.
3867 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3868 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3870 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3871 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3873 // VSHUFPDY divides the resulting vector into 4 chunks.
3874 // The sources are also splitted into 4 chunks, and each destination
3875 // chunk must come from a different source chunk.
3877 // SRC1 => X3 X2 X1 X0
3878 // SRC2 => Y3 Y2 Y1 Y0
3880 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3882 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3883 unsigned HalfLaneElems = NumLaneElems/2;
3884 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3885 for (unsigned i = 0; i != NumLaneElems; ++i) {
3886 int Idx = Mask[i+l];
3887 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3888 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3890 // For VSHUFPSY, the mask of the second half must be the same as the
3891 // first but with the appropriate offsets. This works in the same way as
3892 // VPERMILPS works with masks.
3893 if (!symetricMaskRequired || Idx < 0)
3895 if (MaskVal[i] < 0) {
3896 MaskVal[i] = Idx - l;
3899 if ((signed)(Idx - l) != MaskVal[i])
3907 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3908 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3909 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3910 if (!VT.is128BitVector())
3913 unsigned NumElems = VT.getVectorNumElements();
3918 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3919 return isUndefOrEqual(Mask[0], 6) &&
3920 isUndefOrEqual(Mask[1], 7) &&
3921 isUndefOrEqual(Mask[2], 2) &&
3922 isUndefOrEqual(Mask[3], 3);
3925 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3926 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3928 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3929 if (!VT.is128BitVector())
3932 unsigned NumElems = VT.getVectorNumElements();
3937 return isUndefOrEqual(Mask[0], 2) &&
3938 isUndefOrEqual(Mask[1], 3) &&
3939 isUndefOrEqual(Mask[2], 2) &&
3940 isUndefOrEqual(Mask[3], 3);
3943 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3944 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3945 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3946 if (!VT.is128BitVector())
3949 unsigned NumElems = VT.getVectorNumElements();
3951 if (NumElems != 2 && NumElems != 4)
3954 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3955 if (!isUndefOrEqual(Mask[i], i + NumElems))
3958 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3959 if (!isUndefOrEqual(Mask[i], i))
3965 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3966 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3967 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3968 if (!VT.is128BitVector())
3971 unsigned NumElems = VT.getVectorNumElements();
3973 if (NumElems != 2 && NumElems != 4)
3976 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3977 if (!isUndefOrEqual(Mask[i], i))
3980 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3981 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3987 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
3988 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
3989 /// i. e: If all but one element come from the same vector.
3990 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
3991 // TODO: Deal with AVX's VINSERTPS
3992 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
3995 unsigned CorrectPosV1 = 0;
3996 unsigned CorrectPosV2 = 0;
3997 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
3998 if (Mask[i] == -1) {
4006 else if (Mask[i] == i + 4)
4010 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4011 // We have 3 elements (undefs count as elements from any vector) from one
4012 // vector, and one from another.
4019 // Some special combinations that can be optimized.
4022 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4023 SelectionDAG &DAG) {
4024 MVT VT = SVOp->getSimpleValueType(0);
4027 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4030 ArrayRef<int> Mask = SVOp->getMask();
4032 // These are the special masks that may be optimized.
4033 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4034 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4035 bool MatchEvenMask = true;
4036 bool MatchOddMask = true;
4037 for (int i=0; i<8; ++i) {
4038 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4039 MatchEvenMask = false;
4040 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4041 MatchOddMask = false;
4044 if (!MatchEvenMask && !MatchOddMask)
4047 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4049 SDValue Op0 = SVOp->getOperand(0);
4050 SDValue Op1 = SVOp->getOperand(1);
4052 if (MatchEvenMask) {
4053 // Shift the second operand right to 32 bits.
4054 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4055 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4057 // Shift the first operand left to 32 bits.
4058 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4059 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4061 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4062 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4065 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4066 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4067 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4068 bool HasInt256, bool V2IsSplat = false) {
4070 assert(VT.getSizeInBits() >= 128 &&
4071 "Unsupported vector type for unpckl");
4073 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4075 unsigned NumOf256BitLanes;
4076 unsigned NumElts = VT.getVectorNumElements();
4077 if (VT.is256BitVector()) {
4078 if (NumElts != 4 && NumElts != 8 &&
4079 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4082 NumOf256BitLanes = 1;
4083 } else if (VT.is512BitVector()) {
4084 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4085 "Unsupported vector type for unpckh");
4087 NumOf256BitLanes = 2;
4090 NumOf256BitLanes = 1;
4093 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4094 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4096 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4097 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4098 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4099 int BitI = Mask[l256*NumEltsInStride+l+i];
4100 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4101 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4103 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4105 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4113 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4114 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4115 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4116 bool HasInt256, bool V2IsSplat = false) {
4117 assert(VT.getSizeInBits() >= 128 &&
4118 "Unsupported vector type for unpckh");
4120 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4122 unsigned NumOf256BitLanes;
4123 unsigned NumElts = VT.getVectorNumElements();
4124 if (VT.is256BitVector()) {
4125 if (NumElts != 4 && NumElts != 8 &&
4126 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4129 NumOf256BitLanes = 1;
4130 } else if (VT.is512BitVector()) {
4131 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4132 "Unsupported vector type for unpckh");
4134 NumOf256BitLanes = 2;
4137 NumOf256BitLanes = 1;
4140 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4141 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4143 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4144 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4145 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4146 int BitI = Mask[l256*NumEltsInStride+l+i];
4147 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4148 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4150 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4152 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4160 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4161 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4163 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4164 unsigned NumElts = VT.getVectorNumElements();
4165 bool Is256BitVec = VT.is256BitVector();
4167 if (VT.is512BitVector())
4169 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4170 "Unsupported vector type for unpckh");
4172 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4173 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4176 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4177 // FIXME: Need a better way to get rid of this, there's no latency difference
4178 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4179 // the former later. We should also remove the "_undef" special mask.
4180 if (NumElts == 4 && Is256BitVec)
4183 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4184 // independently on 128-bit lanes.
4185 unsigned NumLanes = VT.getSizeInBits()/128;
4186 unsigned NumLaneElts = NumElts/NumLanes;
4188 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4189 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4190 int BitI = Mask[l+i];
4191 int BitI1 = Mask[l+i+1];
4193 if (!isUndefOrEqual(BitI, j))
4195 if (!isUndefOrEqual(BitI1, j))
4203 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4204 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4206 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4207 unsigned NumElts = VT.getVectorNumElements();
4209 if (VT.is512BitVector())
4212 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4213 "Unsupported vector type for unpckh");
4215 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4216 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4219 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4220 // independently on 128-bit lanes.
4221 unsigned NumLanes = VT.getSizeInBits()/128;
4222 unsigned NumLaneElts = NumElts/NumLanes;
4224 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4225 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4226 int BitI = Mask[l+i];
4227 int BitI1 = Mask[l+i+1];
4228 if (!isUndefOrEqual(BitI, j))
4230 if (!isUndefOrEqual(BitI1, j))
4237 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4238 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4239 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4240 if (!VT.is512BitVector())
4243 unsigned NumElts = VT.getVectorNumElements();
4244 unsigned HalfSize = NumElts/2;
4245 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4246 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4251 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4252 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4260 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4262 /// MOVSD, and MOVD, i.e. setting the lowest element.
4263 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4264 if (VT.getVectorElementType().getSizeInBits() < 32)
4266 if (!VT.is128BitVector())
4269 unsigned NumElts = VT.getVectorNumElements();
4271 if (!isUndefOrEqual(Mask[0], NumElts))
4274 for (unsigned i = 1; i != NumElts; ++i)
4275 if (!isUndefOrEqual(Mask[i], i))
4281 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4282 /// as permutations between 128-bit chunks or halves. As an example: this
4284 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4285 /// The first half comes from the second half of V1 and the second half from the
4286 /// the second half of V2.
4287 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4288 if (!HasFp256 || !VT.is256BitVector())
4291 // The shuffle result is divided into half A and half B. In total the two
4292 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4293 // B must come from C, D, E or F.
4294 unsigned HalfSize = VT.getVectorNumElements()/2;
4295 bool MatchA = false, MatchB = false;
4297 // Check if A comes from one of C, D, E, F.
4298 for (unsigned Half = 0; Half != 4; ++Half) {
4299 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4305 // Check if B comes from one of C, D, E, F.
4306 for (unsigned Half = 0; Half != 4; ++Half) {
4307 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4313 return MatchA && MatchB;
4316 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4317 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4318 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4319 MVT VT = SVOp->getSimpleValueType(0);
4321 unsigned HalfSize = VT.getVectorNumElements()/2;
4323 unsigned FstHalf = 0, SndHalf = 0;
4324 for (unsigned i = 0; i < HalfSize; ++i) {
4325 if (SVOp->getMaskElt(i) > 0) {
4326 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4330 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4331 if (SVOp->getMaskElt(i) > 0) {
4332 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4337 return (FstHalf | (SndHalf << 4));
4340 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4341 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4342 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4346 unsigned NumElts = VT.getVectorNumElements();
4348 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4349 for (unsigned i = 0; i != NumElts; ++i) {
4352 Imm8 |= Mask[i] << (i*2);
4357 unsigned LaneSize = 4;
4358 SmallVector<int, 4> MaskVal(LaneSize, -1);
4360 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4361 for (unsigned i = 0; i != LaneSize; ++i) {
4362 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4366 if (MaskVal[i] < 0) {
4367 MaskVal[i] = Mask[i+l] - l;
4368 Imm8 |= MaskVal[i] << (i*2);
4371 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4378 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4379 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4380 /// Note that VPERMIL mask matching is different depending whether theunderlying
4381 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4382 /// to the same elements of the low, but to the higher half of the source.
4383 /// In VPERMILPD the two lanes could be shuffled independently of each other
4384 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4385 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4386 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4387 if (VT.getSizeInBits() < 256 || EltSize < 32)
4389 bool symetricMaskRequired = (EltSize == 32);
4390 unsigned NumElts = VT.getVectorNumElements();
4392 unsigned NumLanes = VT.getSizeInBits()/128;
4393 unsigned LaneSize = NumElts/NumLanes;
4394 // 2 or 4 elements in one lane
4396 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4397 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4398 for (unsigned i = 0; i != LaneSize; ++i) {
4399 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4401 if (symetricMaskRequired) {
4402 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4403 ExpectedMaskVal[i] = Mask[i+l] - l;
4406 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4414 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4415 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4416 /// element of vector 2 and the other elements to come from vector 1 in order.
4417 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4418 bool V2IsSplat = false, bool V2IsUndef = false) {
4419 if (!VT.is128BitVector())
4422 unsigned NumOps = VT.getVectorNumElements();
4423 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4426 if (!isUndefOrEqual(Mask[0], 0))
4429 for (unsigned i = 1; i != NumOps; ++i)
4430 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4431 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4432 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4438 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4439 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4440 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4441 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4442 const X86Subtarget *Subtarget) {
4443 if (!Subtarget->hasSSE3())
4446 unsigned NumElems = VT.getVectorNumElements();
4448 if ((VT.is128BitVector() && NumElems != 4) ||
4449 (VT.is256BitVector() && NumElems != 8) ||
4450 (VT.is512BitVector() && NumElems != 16))
4453 // "i+1" is the value the indexed mask element must have
4454 for (unsigned i = 0; i != NumElems; i += 2)
4455 if (!isUndefOrEqual(Mask[i], i+1) ||
4456 !isUndefOrEqual(Mask[i+1], i+1))
4462 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4463 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4464 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4465 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4466 const X86Subtarget *Subtarget) {
4467 if (!Subtarget->hasSSE3())
4470 unsigned NumElems = VT.getVectorNumElements();
4472 if ((VT.is128BitVector() && NumElems != 4) ||
4473 (VT.is256BitVector() && NumElems != 8) ||
4474 (VT.is512BitVector() && NumElems != 16))
4477 // "i" is the value the indexed mask element must have
4478 for (unsigned i = 0; i != NumElems; i += 2)
4479 if (!isUndefOrEqual(Mask[i], i) ||
4480 !isUndefOrEqual(Mask[i+1], i))
4486 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4487 /// specifies a shuffle of elements that is suitable for input to 256-bit
4488 /// version of MOVDDUP.
4489 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4490 if (!HasFp256 || !VT.is256BitVector())
4493 unsigned NumElts = VT.getVectorNumElements();
4497 for (unsigned i = 0; i != NumElts/2; ++i)
4498 if (!isUndefOrEqual(Mask[i], 0))
4500 for (unsigned i = NumElts/2; i != NumElts; ++i)
4501 if (!isUndefOrEqual(Mask[i], NumElts/2))
4506 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4507 /// specifies a shuffle of elements that is suitable for input to 128-bit
4508 /// version of MOVDDUP.
4509 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4510 if (!VT.is128BitVector())
4513 unsigned e = VT.getVectorNumElements() / 2;
4514 for (unsigned i = 0; i != e; ++i)
4515 if (!isUndefOrEqual(Mask[i], i))
4517 for (unsigned i = 0; i != e; ++i)
4518 if (!isUndefOrEqual(Mask[e+i], i))
4523 /// isVEXTRACTIndex - Return true if the specified
4524 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4525 /// suitable for instruction that extract 128 or 256 bit vectors
4526 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4527 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4528 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4531 // The index should be aligned on a vecWidth-bit boundary.
4533 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4535 MVT VT = N->getSimpleValueType(0);
4536 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4537 bool Result = (Index * ElSize) % vecWidth == 0;
4542 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4543 /// operand specifies a subvector insert that is suitable for input to
4544 /// insertion of 128 or 256-bit subvectors
4545 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4546 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4547 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4549 // The index should be aligned on a vecWidth-bit boundary.
4551 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4553 MVT VT = N->getSimpleValueType(0);
4554 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4555 bool Result = (Index * ElSize) % vecWidth == 0;
4560 bool X86::isVINSERT128Index(SDNode *N) {
4561 return isVINSERTIndex(N, 128);
4564 bool X86::isVINSERT256Index(SDNode *N) {
4565 return isVINSERTIndex(N, 256);
4568 bool X86::isVEXTRACT128Index(SDNode *N) {
4569 return isVEXTRACTIndex(N, 128);
4572 bool X86::isVEXTRACT256Index(SDNode *N) {
4573 return isVEXTRACTIndex(N, 256);
4576 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4577 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4578 /// Handles 128-bit and 256-bit.
4579 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4580 MVT VT = N->getSimpleValueType(0);
4582 assert((VT.getSizeInBits() >= 128) &&
4583 "Unsupported vector type for PSHUF/SHUFP");
4585 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4586 // independently on 128-bit lanes.
4587 unsigned NumElts = VT.getVectorNumElements();
4588 unsigned NumLanes = VT.getSizeInBits()/128;
4589 unsigned NumLaneElts = NumElts/NumLanes;
4591 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4592 "Only supports 2, 4 or 8 elements per lane");
4594 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4596 for (unsigned i = 0; i != NumElts; ++i) {
4597 int Elt = N->getMaskElt(i);
4598 if (Elt < 0) continue;
4599 Elt &= NumLaneElts - 1;
4600 unsigned ShAmt = (i << Shift) % 8;
4601 Mask |= Elt << ShAmt;
4607 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4608 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4609 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4610 MVT VT = N->getSimpleValueType(0);
4612 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4613 "Unsupported vector type for PSHUFHW");
4615 unsigned NumElts = VT.getVectorNumElements();
4618 for (unsigned l = 0; l != NumElts; l += 8) {
4619 // 8 nodes per lane, but we only care about the last 4.
4620 for (unsigned i = 0; i < 4; ++i) {
4621 int Elt = N->getMaskElt(l+i+4);
4622 if (Elt < 0) continue;
4623 Elt &= 0x3; // only 2-bits.
4624 Mask |= Elt << (i * 2);
4631 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4632 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4633 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4634 MVT VT = N->getSimpleValueType(0);
4636 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4637 "Unsupported vector type for PSHUFHW");
4639 unsigned NumElts = VT.getVectorNumElements();
4642 for (unsigned l = 0; l != NumElts; l += 8) {
4643 // 8 nodes per lane, but we only care about the first 4.
4644 for (unsigned i = 0; i < 4; ++i) {
4645 int Elt = N->getMaskElt(l+i);
4646 if (Elt < 0) continue;
4647 Elt &= 0x3; // only 2-bits
4648 Mask |= Elt << (i * 2);
4655 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4656 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4657 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4658 MVT VT = SVOp->getSimpleValueType(0);
4659 unsigned EltSize = VT.is512BitVector() ? 1 :
4660 VT.getVectorElementType().getSizeInBits() >> 3;
4662 unsigned NumElts = VT.getVectorNumElements();
4663 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4664 unsigned NumLaneElts = NumElts/NumLanes;
4668 for (i = 0; i != NumElts; ++i) {
4669 Val = SVOp->getMaskElt(i);
4673 if (Val >= (int)NumElts)
4674 Val -= NumElts - NumLaneElts;
4676 assert(Val - i > 0 && "PALIGNR imm should be positive");
4677 return (Val - i) * EltSize;
4680 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4681 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4682 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4683 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4686 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4688 MVT VecVT = N->getOperand(0).getSimpleValueType();
4689 MVT ElVT = VecVT.getVectorElementType();
4691 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4692 return Index / NumElemsPerChunk;
4695 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4696 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4697 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4698 llvm_unreachable("Illegal insert subvector for VINSERT");
4701 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4703 MVT VecVT = N->getSimpleValueType(0);
4704 MVT ElVT = VecVT.getVectorElementType();
4706 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4707 return Index / NumElemsPerChunk;
4710 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4711 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4712 /// and VINSERTI128 instructions.
4713 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4714 return getExtractVEXTRACTImmediate(N, 128);
4717 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4718 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4719 /// and VINSERTI64x4 instructions.
4720 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4721 return getExtractVEXTRACTImmediate(N, 256);
4724 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4725 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4726 /// and VINSERTI128 instructions.
4727 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4728 return getInsertVINSERTImmediate(N, 128);
4731 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4732 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4733 /// and VINSERTI64x4 instructions.
4734 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4735 return getInsertVINSERTImmediate(N, 256);
4738 /// isZero - Returns true if Elt is a constant integer zero
4739 static bool isZero(SDValue V) {
4740 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4741 return C && C->isNullValue();
4744 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4746 bool X86::isZeroNode(SDValue Elt) {
4749 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4750 return CFP->getValueAPF().isPosZero();
4754 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4755 /// their permute mask.
4756 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4757 SelectionDAG &DAG) {
4758 MVT VT = SVOp->getSimpleValueType(0);
4759 unsigned NumElems = VT.getVectorNumElements();
4760 SmallVector<int, 8> MaskVec;
4762 for (unsigned i = 0; i != NumElems; ++i) {
4763 int Idx = SVOp->getMaskElt(i);
4765 if (Idx < (int)NumElems)
4770 MaskVec.push_back(Idx);
4772 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4773 SVOp->getOperand(0), &MaskVec[0]);
4776 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4777 /// match movhlps. The lower half elements should come from upper half of
4778 /// V1 (and in order), and the upper half elements should come from the upper
4779 /// half of V2 (and in order).
4780 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4781 if (!VT.is128BitVector())
4783 if (VT.getVectorNumElements() != 4)
4785 for (unsigned i = 0, e = 2; i != e; ++i)
4786 if (!isUndefOrEqual(Mask[i], i+2))
4788 for (unsigned i = 2; i != 4; ++i)
4789 if (!isUndefOrEqual(Mask[i], i+4))
4794 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4795 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4797 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4798 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4800 N = N->getOperand(0).getNode();
4801 if (!ISD::isNON_EXTLoad(N))
4804 *LD = cast<LoadSDNode>(N);
4808 // Test whether the given value is a vector value which will be legalized
4810 static bool WillBeConstantPoolLoad(SDNode *N) {
4811 if (N->getOpcode() != ISD::BUILD_VECTOR)
4814 // Check for any non-constant elements.
4815 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4816 switch (N->getOperand(i).getNode()->getOpcode()) {
4818 case ISD::ConstantFP:
4825 // Vectors of all-zeros and all-ones are materialized with special
4826 // instructions rather than being loaded.
4827 return !ISD::isBuildVectorAllZeros(N) &&
4828 !ISD::isBuildVectorAllOnes(N);
4831 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4832 /// match movlp{s|d}. The lower half elements should come from lower half of
4833 /// V1 (and in order), and the upper half elements should come from the upper
4834 /// half of V2 (and in order). And since V1 will become the source of the
4835 /// MOVLP, it must be either a vector load or a scalar load to vector.
4836 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4837 ArrayRef<int> Mask, MVT VT) {
4838 if (!VT.is128BitVector())
4841 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4843 // Is V2 is a vector load, don't do this transformation. We will try to use
4844 // load folding shufps op.
4845 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4848 unsigned NumElems = VT.getVectorNumElements();
4850 if (NumElems != 2 && NumElems != 4)
4852 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4853 if (!isUndefOrEqual(Mask[i], i))
4855 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4856 if (!isUndefOrEqual(Mask[i], i+NumElems))
4861 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4862 /// to an zero vector.
4863 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4864 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4865 SDValue V1 = N->getOperand(0);
4866 SDValue V2 = N->getOperand(1);
4867 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4868 for (unsigned i = 0; i != NumElems; ++i) {
4869 int Idx = N->getMaskElt(i);
4870 if (Idx >= (int)NumElems) {
4871 unsigned Opc = V2.getOpcode();
4872 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4874 if (Opc != ISD::BUILD_VECTOR ||
4875 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4877 } else if (Idx >= 0) {
4878 unsigned Opc = V1.getOpcode();
4879 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4881 if (Opc != ISD::BUILD_VECTOR ||
4882 !X86::isZeroNode(V1.getOperand(Idx)))
4889 /// getZeroVector - Returns a vector of specified type with all zero elements.
4891 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4892 SelectionDAG &DAG, SDLoc dl) {
4893 assert(VT.isVector() && "Expected a vector type");
4895 // Always build SSE zero vectors as <4 x i32> bitcasted
4896 // to their dest type. This ensures they get CSE'd.
4898 if (VT.is128BitVector()) { // SSE
4899 if (Subtarget->hasSSE2()) { // SSE2
4900 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4901 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4903 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4904 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4906 } else if (VT.is256BitVector()) { // AVX
4907 if (Subtarget->hasInt256()) { // AVX2
4908 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4909 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4910 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4912 // 256-bit logic and arithmetic instructions in AVX are all
4913 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4914 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4915 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4916 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4918 } else if (VT.is512BitVector()) { // AVX-512
4919 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4920 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4921 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4922 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4923 } else if (VT.getScalarType() == MVT::i1) {
4924 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4925 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4926 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4927 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4929 llvm_unreachable("Unexpected vector type");
4931 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4934 /// getOnesVector - Returns a vector of specified type with all bits set.
4935 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4936 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4937 /// Then bitcast to their original type, ensuring they get CSE'd.
4938 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4940 assert(VT.isVector() && "Expected a vector type");
4942 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4944 if (VT.is256BitVector()) {
4945 if (HasInt256) { // AVX2
4946 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4947 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4949 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4950 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4952 } else if (VT.is128BitVector()) {
4953 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4955 llvm_unreachable("Unexpected vector type");
4957 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4960 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4961 /// that point to V2 points to its first element.
4962 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4963 for (unsigned i = 0; i != NumElems; ++i) {
4964 if (Mask[i] > (int)NumElems) {
4970 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4971 /// operation of specified width.
4972 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4974 unsigned NumElems = VT.getVectorNumElements();
4975 SmallVector<int, 8> Mask;
4976 Mask.push_back(NumElems);
4977 for (unsigned i = 1; i != NumElems; ++i)
4979 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4982 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4983 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4985 unsigned NumElems = VT.getVectorNumElements();
4986 SmallVector<int, 8> Mask;
4987 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4989 Mask.push_back(i + NumElems);
4991 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4994 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4995 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4997 unsigned NumElems = VT.getVectorNumElements();
4998 SmallVector<int, 8> Mask;
4999 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5000 Mask.push_back(i + Half);
5001 Mask.push_back(i + NumElems + Half);
5003 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5006 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5007 // a generic shuffle instruction because the target has no such instructions.
5008 // Generate shuffles which repeat i16 and i8 several times until they can be
5009 // represented by v4f32 and then be manipulated by target suported shuffles.
5010 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5011 MVT VT = V.getSimpleValueType();
5012 int NumElems = VT.getVectorNumElements();
5015 while (NumElems > 4) {
5016 if (EltNo < NumElems/2) {
5017 V = getUnpackl(DAG, dl, VT, V, V);
5019 V = getUnpackh(DAG, dl, VT, V, V);
5020 EltNo -= NumElems/2;
5027 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5028 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5029 MVT VT = V.getSimpleValueType();
5032 if (VT.is128BitVector()) {
5033 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5034 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5035 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5037 } else if (VT.is256BitVector()) {
5038 // To use VPERMILPS to splat scalars, the second half of indicies must
5039 // refer to the higher part, which is a duplication of the lower one,
5040 // because VPERMILPS can only handle in-lane permutations.
5041 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5042 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5044 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5045 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5048 llvm_unreachable("Vector size not supported");
5050 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5053 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5054 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5055 MVT SrcVT = SV->getSimpleValueType(0);
5056 SDValue V1 = SV->getOperand(0);
5059 int EltNo = SV->getSplatIndex();
5060 int NumElems = SrcVT.getVectorNumElements();
5061 bool Is256BitVec = SrcVT.is256BitVector();
5063 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5064 "Unknown how to promote splat for type");
5066 // Extract the 128-bit part containing the splat element and update
5067 // the splat element index when it refers to the higher register.
5069 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5070 if (EltNo >= NumElems/2)
5071 EltNo -= NumElems/2;
5074 // All i16 and i8 vector types can't be used directly by a generic shuffle
5075 // instruction because the target has no such instruction. Generate shuffles
5076 // which repeat i16 and i8 several times until they fit in i32, and then can
5077 // be manipulated by target suported shuffles.
5078 MVT EltVT = SrcVT.getVectorElementType();
5079 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5080 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5082 // Recreate the 256-bit vector and place the same 128-bit vector
5083 // into the low and high part. This is necessary because we want
5084 // to use VPERM* to shuffle the vectors
5086 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5089 return getLegalSplat(DAG, V1, EltNo);
5092 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5093 /// vector of zero or undef vector. This produces a shuffle where the low
5094 /// element of V2 is swizzled into the zero/undef vector, landing at element
5095 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5096 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5098 const X86Subtarget *Subtarget,
5099 SelectionDAG &DAG) {
5100 MVT VT = V2.getSimpleValueType();
5102 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5103 unsigned NumElems = VT.getVectorNumElements();
5104 SmallVector<int, 16> MaskVec;
5105 for (unsigned i = 0; i != NumElems; ++i)
5106 // If this is the insertion idx, put the low elt of V2 here.
5107 MaskVec.push_back(i == Idx ? NumElems : i);
5108 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5111 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5112 /// target specific opcode. Returns true if the Mask could be calculated.
5113 /// Sets IsUnary to true if only uses one source.
5114 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5115 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5116 unsigned NumElems = VT.getVectorNumElements();
5120 switch(N->getOpcode()) {
5122 ImmN = N->getOperand(N->getNumOperands()-1);
5123 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5125 case X86ISD::UNPCKH:
5126 DecodeUNPCKHMask(VT, Mask);
5128 case X86ISD::UNPCKL:
5129 DecodeUNPCKLMask(VT, Mask);
5131 case X86ISD::MOVHLPS:
5132 DecodeMOVHLPSMask(NumElems, Mask);
5134 case X86ISD::MOVLHPS:
5135 DecodeMOVLHPSMask(NumElems, Mask);
5137 case X86ISD::PALIGNR:
5138 ImmN = N->getOperand(N->getNumOperands()-1);
5139 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5141 case X86ISD::PSHUFD:
5142 case X86ISD::VPERMILP:
5143 ImmN = N->getOperand(N->getNumOperands()-1);
5144 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5147 case X86ISD::PSHUFHW:
5148 ImmN = N->getOperand(N->getNumOperands()-1);
5149 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5152 case X86ISD::PSHUFLW:
5153 ImmN = N->getOperand(N->getNumOperands()-1);
5154 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5157 case X86ISD::VPERMI:
5158 ImmN = N->getOperand(N->getNumOperands()-1);
5159 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5163 case X86ISD::MOVSD: {
5164 // The index 0 always comes from the first element of the second source,
5165 // this is why MOVSS and MOVSD are used in the first place. The other
5166 // elements come from the other positions of the first source vector
5167 Mask.push_back(NumElems);
5168 for (unsigned i = 1; i != NumElems; ++i) {
5173 case X86ISD::VPERM2X128:
5174 ImmN = N->getOperand(N->getNumOperands()-1);
5175 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5176 if (Mask.empty()) return false;
5178 case X86ISD::MOVDDUP:
5179 case X86ISD::MOVLHPD:
5180 case X86ISD::MOVLPD:
5181 case X86ISD::MOVLPS:
5182 case X86ISD::MOVSHDUP:
5183 case X86ISD::MOVSLDUP:
5184 // Not yet implemented
5186 default: llvm_unreachable("unknown target shuffle node");
5192 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5193 /// element of the result of the vector shuffle.
5194 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5197 return SDValue(); // Limit search depth.
5199 SDValue V = SDValue(N, 0);
5200 EVT VT = V.getValueType();
5201 unsigned Opcode = V.getOpcode();
5203 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5204 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5205 int Elt = SV->getMaskElt(Index);
5208 return DAG.getUNDEF(VT.getVectorElementType());
5210 unsigned NumElems = VT.getVectorNumElements();
5211 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5212 : SV->getOperand(1);
5213 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5216 // Recurse into target specific vector shuffles to find scalars.
5217 if (isTargetShuffle(Opcode)) {
5218 MVT ShufVT = V.getSimpleValueType();
5219 unsigned NumElems = ShufVT.getVectorNumElements();
5220 SmallVector<int, 16> ShuffleMask;
5223 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5226 int Elt = ShuffleMask[Index];
5228 return DAG.getUNDEF(ShufVT.getVectorElementType());
5230 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5232 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5236 // Actual nodes that may contain scalar elements
5237 if (Opcode == ISD::BITCAST) {
5238 V = V.getOperand(0);
5239 EVT SrcVT = V.getValueType();
5240 unsigned NumElems = VT.getVectorNumElements();
5242 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5246 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5247 return (Index == 0) ? V.getOperand(0)
5248 : DAG.getUNDEF(VT.getVectorElementType());
5250 if (V.getOpcode() == ISD::BUILD_VECTOR)
5251 return V.getOperand(Index);
5256 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5257 /// shuffle operation which come from a consecutively from a zero. The
5258 /// search can start in two different directions, from left or right.
5259 /// We count undefs as zeros until PreferredNum is reached.
5260 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5261 unsigned NumElems, bool ZerosFromLeft,
5263 unsigned PreferredNum = -1U) {
5264 unsigned NumZeros = 0;
5265 for (unsigned i = 0; i != NumElems; ++i) {
5266 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5267 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5271 if (X86::isZeroNode(Elt))
5273 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5274 NumZeros = std::min(NumZeros + 1, PreferredNum);
5282 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5283 /// correspond consecutively to elements from one of the vector operands,
5284 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5286 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5287 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5288 unsigned NumElems, unsigned &OpNum) {
5289 bool SeenV1 = false;
5290 bool SeenV2 = false;
5292 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5293 int Idx = SVOp->getMaskElt(i);
5294 // Ignore undef indicies
5298 if (Idx < (int)NumElems)
5303 // Only accept consecutive elements from the same vector
5304 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5308 OpNum = SeenV1 ? 0 : 1;
5312 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5313 /// logical left shift of a vector.
5314 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5315 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5317 SVOp->getSimpleValueType(0).getVectorNumElements();
5318 unsigned NumZeros = getNumOfConsecutiveZeros(
5319 SVOp, NumElems, false /* check zeros from right */, DAG,
5320 SVOp->getMaskElt(0));
5326 // Considering the elements in the mask that are not consecutive zeros,
5327 // check if they consecutively come from only one of the source vectors.
5329 // V1 = {X, A, B, C} 0
5331 // vector_shuffle V1, V2 <1, 2, 3, X>
5333 if (!isShuffleMaskConsecutive(SVOp,
5334 0, // Mask Start Index
5335 NumElems-NumZeros, // Mask End Index(exclusive)
5336 NumZeros, // Where to start looking in the src vector
5337 NumElems, // Number of elements in vector
5338 OpSrc)) // Which source operand ?
5343 ShVal = SVOp->getOperand(OpSrc);
5347 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5348 /// logical left shift of a vector.
5349 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5350 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5352 SVOp->getSimpleValueType(0).getVectorNumElements();
5353 unsigned NumZeros = getNumOfConsecutiveZeros(
5354 SVOp, NumElems, true /* check zeros from left */, DAG,
5355 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5361 // Considering the elements in the mask that are not consecutive zeros,
5362 // check if they consecutively come from only one of the source vectors.
5364 // 0 { A, B, X, X } = V2
5366 // vector_shuffle V1, V2 <X, X, 4, 5>
5368 if (!isShuffleMaskConsecutive(SVOp,
5369 NumZeros, // Mask Start Index
5370 NumElems, // Mask End Index(exclusive)
5371 0, // Where to start looking in the src vector
5372 NumElems, // Number of elements in vector
5373 OpSrc)) // Which source operand ?
5378 ShVal = SVOp->getOperand(OpSrc);
5382 /// isVectorShift - Returns true if the shuffle can be implemented as a
5383 /// logical left or right shift of a vector.
5384 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5385 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5386 // Although the logic below support any bitwidth size, there are no
5387 // shift instructions which handle more than 128-bit vectors.
5388 if (!SVOp->getSimpleValueType(0).is128BitVector())
5391 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5392 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5398 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5400 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5401 unsigned NumNonZero, unsigned NumZero,
5403 const X86Subtarget* Subtarget,
5404 const TargetLowering &TLI) {
5411 for (unsigned i = 0; i < 16; ++i) {
5412 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5413 if (ThisIsNonZero && First) {
5415 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5417 V = DAG.getUNDEF(MVT::v8i16);
5422 SDValue ThisElt, LastElt;
5423 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5424 if (LastIsNonZero) {
5425 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5426 MVT::i16, Op.getOperand(i-1));
5428 if (ThisIsNonZero) {
5429 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5430 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5431 ThisElt, DAG.getConstant(8, MVT::i8));
5433 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5437 if (ThisElt.getNode())
5438 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5439 DAG.getIntPtrConstant(i/2));
5443 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5446 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5448 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5449 unsigned NumNonZero, unsigned NumZero,
5451 const X86Subtarget* Subtarget,
5452 const TargetLowering &TLI) {
5459 for (unsigned i = 0; i < 8; ++i) {
5460 bool isNonZero = (NonZeros & (1 << i)) != 0;
5464 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5466 V = DAG.getUNDEF(MVT::v8i16);
5469 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5470 MVT::v8i16, V, Op.getOperand(i),
5471 DAG.getIntPtrConstant(i));
5478 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5479 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5480 unsigned NonZeros, unsigned NumNonZero,
5481 unsigned NumZero, SelectionDAG &DAG,
5482 const X86Subtarget *Subtarget,
5483 const TargetLowering &TLI) {
5484 // We know there's at least one non-zero element
5485 unsigned FirstNonZeroIdx = 0;
5486 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5487 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5488 X86::isZeroNode(FirstNonZero)) {
5490 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5493 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5494 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5497 SDValue V = FirstNonZero.getOperand(0);
5498 MVT VVT = V.getSimpleValueType();
5499 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5502 unsigned FirstNonZeroDst =
5503 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5504 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5505 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5506 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5508 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5509 SDValue Elem = Op.getOperand(Idx);
5510 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5513 // TODO: What else can be here? Deal with it.
5514 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5517 // TODO: Some optimizations are still possible here
5518 // ex: Getting one element from a vector, and the rest from another.
5519 if (Elem.getOperand(0) != V)
5522 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5525 else if (IncorrectIdx == -1U) {
5529 // There was already one element with an incorrect index.
5530 // We can't optimize this case to an insertps.
5534 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5536 EVT VT = Op.getSimpleValueType();
5537 unsigned ElementMoveMask = 0;
5538 if (IncorrectIdx == -1U)
5539 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5541 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5543 SDValue InsertpsMask =
5544 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5545 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5551 /// getVShift - Return a vector logical shift node.
5553 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5554 unsigned NumBits, SelectionDAG &DAG,
5555 const TargetLowering &TLI, SDLoc dl) {
5556 assert(VT.is128BitVector() && "Unknown type for VShift");
5557 EVT ShVT = MVT::v2i64;
5558 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5559 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5560 return DAG.getNode(ISD::BITCAST, dl, VT,
5561 DAG.getNode(Opc, dl, ShVT, SrcOp,
5562 DAG.getConstant(NumBits,
5563 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5567 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5569 // Check if the scalar load can be widened into a vector load. And if
5570 // the address is "base + cst" see if the cst can be "absorbed" into
5571 // the shuffle mask.
5572 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5573 SDValue Ptr = LD->getBasePtr();
5574 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5576 EVT PVT = LD->getValueType(0);
5577 if (PVT != MVT::i32 && PVT != MVT::f32)
5582 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5583 FI = FINode->getIndex();
5585 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5586 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5587 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5588 Offset = Ptr.getConstantOperandVal(1);
5589 Ptr = Ptr.getOperand(0);
5594 // FIXME: 256-bit vector instructions don't require a strict alignment,
5595 // improve this code to support it better.
5596 unsigned RequiredAlign = VT.getSizeInBits()/8;
5597 SDValue Chain = LD->getChain();
5598 // Make sure the stack object alignment is at least 16 or 32.
5599 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5600 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5601 if (MFI->isFixedObjectIndex(FI)) {
5602 // Can't change the alignment. FIXME: It's possible to compute
5603 // the exact stack offset and reference FI + adjust offset instead.
5604 // If someone *really* cares about this. That's the way to implement it.
5607 MFI->setObjectAlignment(FI, RequiredAlign);
5611 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5612 // Ptr + (Offset & ~15).
5615 if ((Offset % RequiredAlign) & 3)
5617 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5619 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5620 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5622 int EltNo = (Offset - StartOffset) >> 2;
5623 unsigned NumElems = VT.getVectorNumElements();
5625 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5626 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5627 LD->getPointerInfo().getWithOffset(StartOffset),
5628 false, false, false, 0);
5630 SmallVector<int, 8> Mask;
5631 for (unsigned i = 0; i != NumElems; ++i)
5632 Mask.push_back(EltNo);
5634 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5640 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5641 /// vector of type 'VT', see if the elements can be replaced by a single large
5642 /// load which has the same value as a build_vector whose operands are 'elts'.
5644 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5646 /// FIXME: we'd also like to handle the case where the last elements are zero
5647 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5648 /// There's even a handy isZeroNode for that purpose.
5649 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5650 SDLoc &DL, SelectionDAG &DAG,
5651 bool isAfterLegalize) {
5652 EVT EltVT = VT.getVectorElementType();
5653 unsigned NumElems = Elts.size();
5655 LoadSDNode *LDBase = nullptr;
5656 unsigned LastLoadedElt = -1U;
5658 // For each element in the initializer, see if we've found a load or an undef.
5659 // If we don't find an initial load element, or later load elements are
5660 // non-consecutive, bail out.
5661 for (unsigned i = 0; i < NumElems; ++i) {
5662 SDValue Elt = Elts[i];
5664 if (!Elt.getNode() ||
5665 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5668 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5670 LDBase = cast<LoadSDNode>(Elt.getNode());
5674 if (Elt.getOpcode() == ISD::UNDEF)
5677 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5678 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5683 // If we have found an entire vector of loads and undefs, then return a large
5684 // load of the entire vector width starting at the base pointer. If we found
5685 // consecutive loads for the low half, generate a vzext_load node.
5686 if (LastLoadedElt == NumElems - 1) {
5688 if (isAfterLegalize &&
5689 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5692 SDValue NewLd = SDValue();
5694 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5695 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5696 LDBase->getPointerInfo(),
5697 LDBase->isVolatile(), LDBase->isNonTemporal(),
5698 LDBase->isInvariant(), 0);
5699 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5700 LDBase->getPointerInfo(),
5701 LDBase->isVolatile(), LDBase->isNonTemporal(),
5702 LDBase->isInvariant(), LDBase->getAlignment());
5704 if (LDBase->hasAnyUseOfValue(1)) {
5705 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5707 SDValue(NewLd.getNode(), 1));
5708 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5709 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5710 SDValue(NewLd.getNode(), 1));
5715 if (NumElems == 4 && LastLoadedElt == 1 &&
5716 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5717 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5718 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5720 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5721 LDBase->getPointerInfo(),
5722 LDBase->getAlignment(),
5723 false/*isVolatile*/, true/*ReadMem*/,
5726 // Make sure the newly-created LOAD is in the same position as LDBase in
5727 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5728 // update uses of LDBase's output chain to use the TokenFactor.
5729 if (LDBase->hasAnyUseOfValue(1)) {
5730 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5731 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5732 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5733 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5734 SDValue(ResNode.getNode(), 1));
5737 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5742 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5743 /// to generate a splat value for the following cases:
5744 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5745 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5746 /// a scalar load, or a constant.
5747 /// The VBROADCAST node is returned when a pattern is found,
5748 /// or SDValue() otherwise.
5749 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5750 SelectionDAG &DAG) {
5751 if (!Subtarget->hasFp256())
5754 MVT VT = Op.getSimpleValueType();
5757 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5758 "Unsupported vector type for broadcast.");
5763 switch (Op.getOpcode()) {
5765 // Unknown pattern found.
5768 case ISD::BUILD_VECTOR: {
5769 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5770 BitVector UndefElements;
5771 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5773 // We need a splat of a single value to use broadcast, and it doesn't
5774 // make any sense if the value is only in one element of the vector.
5775 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5779 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5780 Ld.getOpcode() == ISD::ConstantFP);
5782 // Make sure that all of the users of a non-constant load are from the
5783 // BUILD_VECTOR node.
5784 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5789 case ISD::VECTOR_SHUFFLE: {
5790 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5792 // Shuffles must have a splat mask where the first element is
5794 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5797 SDValue Sc = Op.getOperand(0);
5798 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5799 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5801 if (!Subtarget->hasInt256())
5804 // Use the register form of the broadcast instruction available on AVX2.
5805 if (VT.getSizeInBits() >= 256)
5806 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5807 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5810 Ld = Sc.getOperand(0);
5811 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5812 Ld.getOpcode() == ISD::ConstantFP);
5814 // The scalar_to_vector node and the suspected
5815 // load node must have exactly one user.
5816 // Constants may have multiple users.
5818 // AVX-512 has register version of the broadcast
5819 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5820 Ld.getValueType().getSizeInBits() >= 32;
5821 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5828 bool IsGE256 = (VT.getSizeInBits() >= 256);
5830 // Handle the broadcasting a single constant scalar from the constant pool
5831 // into a vector. On Sandybridge it is still better to load a constant vector
5832 // from the constant pool and not to broadcast it from a scalar.
5833 if (ConstSplatVal && Subtarget->hasInt256()) {
5834 EVT CVT = Ld.getValueType();
5835 assert(!CVT.isVector() && "Must not broadcast a vector type");
5836 unsigned ScalarSize = CVT.getSizeInBits();
5838 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5839 const Constant *C = nullptr;
5840 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5841 C = CI->getConstantIntValue();
5842 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5843 C = CF->getConstantFPValue();
5845 assert(C && "Invalid constant type");
5847 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5848 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5849 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5850 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5851 MachinePointerInfo::getConstantPool(),
5852 false, false, false, Alignment);
5854 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5858 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5859 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5861 // Handle AVX2 in-register broadcasts.
5862 if (!IsLoad && Subtarget->hasInt256() &&
5863 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5864 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5866 // The scalar source must be a normal load.
5870 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5871 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5873 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5874 // double since there is no vbroadcastsd xmm
5875 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5876 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5877 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5880 // Unsupported broadcast.
5884 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5885 /// underlying vector and index.
5887 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5889 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5891 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5892 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5895 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5897 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5899 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5900 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5903 // In this case the vector is the extract_subvector expression and the index
5904 // is 2, as specified by the shuffle.
5905 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5906 SDValue ShuffleVec = SVOp->getOperand(0);
5907 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5908 assert(ShuffleVecVT.getVectorElementType() ==
5909 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5911 int ShuffleIdx = SVOp->getMaskElt(Idx);
5912 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5913 ExtractedFromVec = ShuffleVec;
5919 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5920 MVT VT = Op.getSimpleValueType();
5922 // Skip if insert_vec_elt is not supported.
5923 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5924 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5928 unsigned NumElems = Op.getNumOperands();
5932 SmallVector<unsigned, 4> InsertIndices;
5933 SmallVector<int, 8> Mask(NumElems, -1);
5935 for (unsigned i = 0; i != NumElems; ++i) {
5936 unsigned Opc = Op.getOperand(i).getOpcode();
5938 if (Opc == ISD::UNDEF)
5941 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5942 // Quit if more than 1 elements need inserting.
5943 if (InsertIndices.size() > 1)
5946 InsertIndices.push_back(i);
5950 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5951 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5952 // Quit if non-constant index.
5953 if (!isa<ConstantSDNode>(ExtIdx))
5955 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5957 // Quit if extracted from vector of different type.
5958 if (ExtractedFromVec.getValueType() != VT)
5961 if (!VecIn1.getNode())
5962 VecIn1 = ExtractedFromVec;
5963 else if (VecIn1 != ExtractedFromVec) {
5964 if (!VecIn2.getNode())
5965 VecIn2 = ExtractedFromVec;
5966 else if (VecIn2 != ExtractedFromVec)
5967 // Quit if more than 2 vectors to shuffle
5971 if (ExtractedFromVec == VecIn1)
5973 else if (ExtractedFromVec == VecIn2)
5974 Mask[i] = Idx + NumElems;
5977 if (!VecIn1.getNode())
5980 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5981 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5982 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5983 unsigned Idx = InsertIndices[i];
5984 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5985 DAG.getIntPtrConstant(Idx));
5991 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5993 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5995 MVT VT = Op.getSimpleValueType();
5996 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5997 "Unexpected type in LowerBUILD_VECTORvXi1!");
6000 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6001 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6002 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6003 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6006 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6007 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6008 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6009 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6012 bool AllContants = true;
6013 uint64_t Immediate = 0;
6014 int NonConstIdx = -1;
6015 bool IsSplat = true;
6016 unsigned NumNonConsts = 0;
6017 unsigned NumConsts = 0;
6018 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6019 SDValue In = Op.getOperand(idx);
6020 if (In.getOpcode() == ISD::UNDEF)
6022 if (!isa<ConstantSDNode>(In)) {
6023 AllContants = false;
6029 if (cast<ConstantSDNode>(In)->getZExtValue())
6030 Immediate |= (1ULL << idx);
6032 if (In != Op.getOperand(0))
6037 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6038 DAG.getConstant(Immediate, MVT::i16));
6039 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6040 DAG.getIntPtrConstant(0));
6043 if (NumNonConsts == 1 && NonConstIdx != 0) {
6046 SDValue VecAsImm = DAG.getConstant(Immediate,
6047 MVT::getIntegerVT(VT.getSizeInBits()));
6048 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6051 DstVec = DAG.getUNDEF(VT);
6052 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6053 Op.getOperand(NonConstIdx),
6054 DAG.getIntPtrConstant(NonConstIdx));
6056 if (!IsSplat && (NonConstIdx != 0))
6057 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6058 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6061 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6062 DAG.getConstant(-1, SelectVT),
6063 DAG.getConstant(0, SelectVT));
6065 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6066 DAG.getConstant((Immediate | 1), SelectVT),
6067 DAG.getConstant(Immediate, SelectVT));
6068 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6071 /// \brief Return true if \p N implements a horizontal binop and return the
6072 /// operands for the horizontal binop into V0 and V1.
6074 /// This is a helper function of PerformBUILD_VECTORCombine.
6075 /// This function checks that the build_vector \p N in input implements a
6076 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6077 /// operation to match.
6078 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6079 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6080 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6083 /// This function only analyzes elements of \p N whose indices are
6084 /// in range [BaseIdx, LastIdx).
6085 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6087 unsigned BaseIdx, unsigned LastIdx,
6088 SDValue &V0, SDValue &V1) {
6089 EVT VT = N->getValueType(0);
6091 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6092 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6093 "Invalid Vector in input!");
6095 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6096 bool CanFold = true;
6097 unsigned ExpectedVExtractIdx = BaseIdx;
6098 unsigned NumElts = LastIdx - BaseIdx;
6099 V0 = DAG.getUNDEF(VT);
6100 V1 = DAG.getUNDEF(VT);
6102 // Check if N implements a horizontal binop.
6103 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6104 SDValue Op = N->getOperand(i + BaseIdx);
6107 if (Op->getOpcode() == ISD::UNDEF) {
6108 // Update the expected vector extract index.
6109 if (i * 2 == NumElts)
6110 ExpectedVExtractIdx = BaseIdx;
6111 ExpectedVExtractIdx += 2;
6115 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6120 SDValue Op0 = Op.getOperand(0);
6121 SDValue Op1 = Op.getOperand(1);
6123 // Try to match the following pattern:
6124 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6125 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6126 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6127 Op0.getOperand(0) == Op1.getOperand(0) &&
6128 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6129 isa<ConstantSDNode>(Op1.getOperand(1)));
6133 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6134 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6136 if (i * 2 < NumElts) {
6137 if (V0.getOpcode() == ISD::UNDEF)
6138 V0 = Op0.getOperand(0);
6140 if (V1.getOpcode() == ISD::UNDEF)
6141 V1 = Op0.getOperand(0);
6142 if (i * 2 == NumElts)
6143 ExpectedVExtractIdx = BaseIdx;
6146 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6147 if (I0 == ExpectedVExtractIdx)
6148 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6149 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6150 // Try to match the following dag sequence:
6151 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6152 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6156 ExpectedVExtractIdx += 2;
6162 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6163 /// a concat_vector.
6165 /// This is a helper function of PerformBUILD_VECTORCombine.
6166 /// This function expects two 256-bit vectors called V0 and V1.
6167 /// At first, each vector is split into two separate 128-bit vectors.
6168 /// Then, the resulting 128-bit vectors are used to implement two
6169 /// horizontal binary operations.
6171 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6173 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6174 /// the two new horizontal binop.
6175 /// When Mode is set, the first horizontal binop dag node would take as input
6176 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6177 /// horizontal binop dag node would take as input the lower 128-bit of V1
6178 /// and the upper 128-bit of V1.
6180 /// HADD V0_LO, V0_HI
6181 /// HADD V1_LO, V1_HI
6183 /// Otherwise, the first horizontal binop dag node takes as input the lower
6184 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6185 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6187 /// HADD V0_LO, V1_LO
6188 /// HADD V0_HI, V1_HI
6190 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6191 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6192 /// the upper 128-bits of the result.
6193 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6194 SDLoc DL, SelectionDAG &DAG,
6195 unsigned X86Opcode, bool Mode,
6196 bool isUndefLO, bool isUndefHI) {
6197 EVT VT = V0.getValueType();
6198 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6199 "Invalid nodes in input!");
6201 unsigned NumElts = VT.getVectorNumElements();
6202 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6203 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6204 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6205 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6206 EVT NewVT = V0_LO.getValueType();
6208 SDValue LO = DAG.getUNDEF(NewVT);
6209 SDValue HI = DAG.getUNDEF(NewVT);
6212 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6213 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6214 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6215 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6216 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6218 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6219 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6220 V1_LO->getOpcode() != ISD::UNDEF))
6221 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6223 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6224 V1_HI->getOpcode() != ISD::UNDEF))
6225 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6228 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6231 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6232 /// sequence of 'vadd + vsub + blendi'.
6233 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6234 const X86Subtarget *Subtarget) {
6236 EVT VT = BV->getValueType(0);
6237 unsigned NumElts = VT.getVectorNumElements();
6238 SDValue InVec0 = DAG.getUNDEF(VT);
6239 SDValue InVec1 = DAG.getUNDEF(VT);
6241 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6242 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6244 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6246 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6249 // Odd-numbered elements in the input build vector are obtained from
6250 // adding two integer/float elements.
6251 // Even-numbered elements in the input build vector are obtained from
6252 // subtracting two integer/float elements.
6253 unsigned ExpectedOpcode = ISD::FSUB;
6254 unsigned NextExpectedOpcode = ISD::FADD;
6255 bool AddFound = false;
6256 bool SubFound = false;
6258 for (unsigned i = 0, e = NumElts; i != e; i++) {
6259 SDValue Op = BV->getOperand(i);
6261 // Skip 'undef' values.
6262 unsigned Opcode = Op.getOpcode();
6263 if (Opcode == ISD::UNDEF) {
6264 std::swap(ExpectedOpcode, NextExpectedOpcode);
6268 // Early exit if we found an unexpected opcode.
6269 if (Opcode != ExpectedOpcode)
6272 SDValue Op0 = Op.getOperand(0);
6273 SDValue Op1 = Op.getOperand(1);
6275 // Try to match the following pattern:
6276 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6277 // Early exit if we cannot match that sequence.
6278 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6279 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6280 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6281 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6282 Op0.getOperand(1) != Op1.getOperand(1))
6285 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6289 // We found a valid add/sub node. Update the information accordingly.
6295 // Update InVec0 and InVec1.
6296 if (InVec0.getOpcode() == ISD::UNDEF)
6297 InVec0 = Op0.getOperand(0);
6298 if (InVec1.getOpcode() == ISD::UNDEF)
6299 InVec1 = Op1.getOperand(0);
6301 // Make sure that operands in input to each add/sub node always
6302 // come from a same pair of vectors.
6303 if (InVec0 != Op0.getOperand(0)) {
6304 if (ExpectedOpcode == ISD::FSUB)
6307 // FADD is commutable. Try to commute the operands
6308 // and then test again.
6309 std::swap(Op0, Op1);
6310 if (InVec0 != Op0.getOperand(0))
6314 if (InVec1 != Op1.getOperand(0))
6317 // Update the pair of expected opcodes.
6318 std::swap(ExpectedOpcode, NextExpectedOpcode);
6321 // Don't try to fold this build_vector into a VSELECT if it has
6322 // too many UNDEF operands.
6323 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6324 InVec1.getOpcode() != ISD::UNDEF) {
6325 // Emit a sequence of vector add and sub followed by a VSELECT.
6326 // The new VSELECT will be lowered into a BLENDI.
6327 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6328 // and emit a single ADDSUB instruction.
6329 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6330 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6332 // Construct the VSELECT mask.
6333 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6334 EVT SVT = MaskVT.getVectorElementType();
6335 unsigned SVTBits = SVT.getSizeInBits();
6336 SmallVector<SDValue, 8> Ops;
6338 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6339 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6340 APInt::getAllOnesValue(SVTBits);
6341 SDValue Constant = DAG.getConstant(Value, SVT);
6342 Ops.push_back(Constant);
6345 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6346 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6352 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6353 const X86Subtarget *Subtarget) {
6355 EVT VT = N->getValueType(0);
6356 unsigned NumElts = VT.getVectorNumElements();
6357 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6358 SDValue InVec0, InVec1;
6360 // Try to match an ADDSUB.
6361 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6362 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6363 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6364 if (Value.getNode())
6368 // Try to match horizontal ADD/SUB.
6369 unsigned NumUndefsLO = 0;
6370 unsigned NumUndefsHI = 0;
6371 unsigned Half = NumElts/2;
6373 // Count the number of UNDEF operands in the build_vector in input.
6374 for (unsigned i = 0, e = Half; i != e; ++i)
6375 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6378 for (unsigned i = Half, e = NumElts; i != e; ++i)
6379 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6382 // Early exit if this is either a build_vector of all UNDEFs or all the
6383 // operands but one are UNDEF.
6384 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6387 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6388 // Try to match an SSE3 float HADD/HSUB.
6389 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6390 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6392 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6393 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6394 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6395 // Try to match an SSSE3 integer HADD/HSUB.
6396 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6397 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6399 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6400 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6403 if (!Subtarget->hasAVX())
6406 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6407 // Try to match an AVX horizontal add/sub of packed single/double
6408 // precision floating point values from 256-bit vectors.
6409 SDValue InVec2, InVec3;
6410 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6411 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6412 ((InVec0.getOpcode() == ISD::UNDEF ||
6413 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6414 ((InVec1.getOpcode() == ISD::UNDEF ||
6415 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6416 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6418 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6419 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6420 ((InVec0.getOpcode() == ISD::UNDEF ||
6421 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6422 ((InVec1.getOpcode() == ISD::UNDEF ||
6423 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6424 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6425 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6426 // Try to match an AVX2 horizontal add/sub of signed integers.
6427 SDValue InVec2, InVec3;
6429 bool CanFold = true;
6431 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6432 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6433 ((InVec0.getOpcode() == ISD::UNDEF ||
6434 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6435 ((InVec1.getOpcode() == ISD::UNDEF ||
6436 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6437 X86Opcode = X86ISD::HADD;
6438 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6439 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6440 ((InVec0.getOpcode() == ISD::UNDEF ||
6441 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6442 ((InVec1.getOpcode() == ISD::UNDEF ||
6443 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6444 X86Opcode = X86ISD::HSUB;
6449 // Fold this build_vector into a single horizontal add/sub.
6450 // Do this only if the target has AVX2.
6451 if (Subtarget->hasAVX2())
6452 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6454 // Do not try to expand this build_vector into a pair of horizontal
6455 // add/sub if we can emit a pair of scalar add/sub.
6456 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6459 // Convert this build_vector into a pair of horizontal binop followed by
6461 bool isUndefLO = NumUndefsLO == Half;
6462 bool isUndefHI = NumUndefsHI == Half;
6463 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6464 isUndefLO, isUndefHI);
6468 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6469 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6471 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6472 X86Opcode = X86ISD::HADD;
6473 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6474 X86Opcode = X86ISD::HSUB;
6475 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6476 X86Opcode = X86ISD::FHADD;
6477 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6478 X86Opcode = X86ISD::FHSUB;
6482 // Don't try to expand this build_vector into a pair of horizontal add/sub
6483 // if we can simply emit a pair of scalar add/sub.
6484 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6487 // Convert this build_vector into two horizontal add/sub followed by
6489 bool isUndefLO = NumUndefsLO == Half;
6490 bool isUndefHI = NumUndefsHI == Half;
6491 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6492 isUndefLO, isUndefHI);
6499 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6502 MVT VT = Op.getSimpleValueType();
6503 MVT ExtVT = VT.getVectorElementType();
6504 unsigned NumElems = Op.getNumOperands();
6506 // Generate vectors for predicate vectors.
6507 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6508 return LowerBUILD_VECTORvXi1(Op, DAG);
6510 // Vectors containing all zeros can be matched by pxor and xorps later
6511 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6512 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6513 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6514 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6517 return getZeroVector(VT, Subtarget, DAG, dl);
6520 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6521 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6522 // vpcmpeqd on 256-bit vectors.
6523 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6524 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6527 if (!VT.is512BitVector())
6528 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6531 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6532 if (Broadcast.getNode())
6535 unsigned EVTBits = ExtVT.getSizeInBits();
6537 unsigned NumZero = 0;
6538 unsigned NumNonZero = 0;
6539 unsigned NonZeros = 0;
6540 bool IsAllConstants = true;
6541 SmallSet<SDValue, 8> Values;
6542 for (unsigned i = 0; i < NumElems; ++i) {
6543 SDValue Elt = Op.getOperand(i);
6544 if (Elt.getOpcode() == ISD::UNDEF)
6547 if (Elt.getOpcode() != ISD::Constant &&
6548 Elt.getOpcode() != ISD::ConstantFP)
6549 IsAllConstants = false;
6550 if (X86::isZeroNode(Elt))
6553 NonZeros |= (1 << i);
6558 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6559 if (NumNonZero == 0)
6560 return DAG.getUNDEF(VT);
6562 // Special case for single non-zero, non-undef, element.
6563 if (NumNonZero == 1) {
6564 unsigned Idx = countTrailingZeros(NonZeros);
6565 SDValue Item = Op.getOperand(Idx);
6567 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6568 // the value are obviously zero, truncate the value to i32 and do the
6569 // insertion that way. Only do this if the value is non-constant or if the
6570 // value is a constant being inserted into element 0. It is cheaper to do
6571 // a constant pool load than it is to do a movd + shuffle.
6572 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6573 (!IsAllConstants || Idx == 0)) {
6574 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6576 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6577 EVT VecVT = MVT::v4i32;
6578 unsigned VecElts = 4;
6580 // Truncate the value (which may itself be a constant) to i32, and
6581 // convert it to a vector with movd (S2V+shuffle to zero extend).
6582 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6583 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6584 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6586 // Now we have our 32-bit value zero extended in the low element of
6587 // a vector. If Idx != 0, swizzle it into place.
6589 SmallVector<int, 4> Mask;
6590 Mask.push_back(Idx);
6591 for (unsigned i = 1; i != VecElts; ++i)
6593 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6596 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6600 // If we have a constant or non-constant insertion into the low element of
6601 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6602 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6603 // depending on what the source datatype is.
6606 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6608 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6609 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6610 if (VT.is256BitVector() || VT.is512BitVector()) {
6611 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6612 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6613 Item, DAG.getIntPtrConstant(0));
6615 assert(VT.is128BitVector() && "Expected an SSE value type!");
6616 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6617 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6618 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6621 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6622 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6623 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6624 if (VT.is256BitVector()) {
6625 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6626 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6628 assert(VT.is128BitVector() && "Expected an SSE value type!");
6629 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6631 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6635 // Is it a vector logical left shift?
6636 if (NumElems == 2 && Idx == 1 &&
6637 X86::isZeroNode(Op.getOperand(0)) &&
6638 !X86::isZeroNode(Op.getOperand(1))) {
6639 unsigned NumBits = VT.getSizeInBits();
6640 return getVShift(true, VT,
6641 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6642 VT, Op.getOperand(1)),
6643 NumBits/2, DAG, *this, dl);
6646 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6649 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6650 // is a non-constant being inserted into an element other than the low one,
6651 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6652 // movd/movss) to move this into the low element, then shuffle it into
6654 if (EVTBits == 32) {
6655 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6657 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6658 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6659 SmallVector<int, 8> MaskVec;
6660 for (unsigned i = 0; i != NumElems; ++i)
6661 MaskVec.push_back(i == Idx ? 0 : 1);
6662 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6666 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6667 if (Values.size() == 1) {
6668 if (EVTBits == 32) {
6669 // Instead of a shuffle like this:
6670 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6671 // Check if it's possible to issue this instead.
6672 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6673 unsigned Idx = countTrailingZeros(NonZeros);
6674 SDValue Item = Op.getOperand(Idx);
6675 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6676 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6681 // A vector full of immediates; various special cases are already
6682 // handled, so this is best done with a single constant-pool load.
6686 // For AVX-length vectors, build the individual 128-bit pieces and use
6687 // shuffles to put them in place.
6688 if (VT.is256BitVector() || VT.is512BitVector()) {
6689 SmallVector<SDValue, 64> V;
6690 for (unsigned i = 0; i != NumElems; ++i)
6691 V.push_back(Op.getOperand(i));
6693 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6695 // Build both the lower and upper subvector.
6696 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6697 makeArrayRef(&V[0], NumElems/2));
6698 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6699 makeArrayRef(&V[NumElems / 2], NumElems/2));
6701 // Recreate the wider vector with the lower and upper part.
6702 if (VT.is256BitVector())
6703 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6704 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6707 // Let legalizer expand 2-wide build_vectors.
6708 if (EVTBits == 64) {
6709 if (NumNonZero == 1) {
6710 // One half is zero or undef.
6711 unsigned Idx = countTrailingZeros(NonZeros);
6712 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6713 Op.getOperand(Idx));
6714 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6719 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6720 if (EVTBits == 8 && NumElems == 16) {
6721 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6723 if (V.getNode()) return V;
6726 if (EVTBits == 16 && NumElems == 8) {
6727 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6729 if (V.getNode()) return V;
6732 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6733 if (EVTBits == 32 && NumElems == 4) {
6734 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6735 NumZero, DAG, Subtarget, *this);
6740 // If element VT is == 32 bits, turn it into a number of shuffles.
6741 SmallVector<SDValue, 8> V(NumElems);
6742 if (NumElems == 4 && NumZero > 0) {
6743 for (unsigned i = 0; i < 4; ++i) {
6744 bool isZero = !(NonZeros & (1 << i));
6746 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6748 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6751 for (unsigned i = 0; i < 2; ++i) {
6752 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6755 V[i] = V[i*2]; // Must be a zero vector.
6758 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6761 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6764 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6769 bool Reverse1 = (NonZeros & 0x3) == 2;
6770 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6774 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6775 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6777 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6780 if (Values.size() > 1 && VT.is128BitVector()) {
6781 // Check for a build vector of consecutive loads.
6782 for (unsigned i = 0; i < NumElems; ++i)
6783 V[i] = Op.getOperand(i);
6785 // Check for elements which are consecutive loads.
6786 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6790 // Check for a build vector from mostly shuffle plus few inserting.
6791 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6795 // For SSE 4.1, use insertps to put the high elements into the low element.
6796 if (getSubtarget()->hasSSE41()) {
6798 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6799 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6801 Result = DAG.getUNDEF(VT);
6803 for (unsigned i = 1; i < NumElems; ++i) {
6804 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6805 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6806 Op.getOperand(i), DAG.getIntPtrConstant(i));
6811 // Otherwise, expand into a number of unpckl*, start by extending each of
6812 // our (non-undef) elements to the full vector width with the element in the
6813 // bottom slot of the vector (which generates no code for SSE).
6814 for (unsigned i = 0; i < NumElems; ++i) {
6815 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6816 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6818 V[i] = DAG.getUNDEF(VT);
6821 // Next, we iteratively mix elements, e.g. for v4f32:
6822 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6823 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6824 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6825 unsigned EltStride = NumElems >> 1;
6826 while (EltStride != 0) {
6827 for (unsigned i = 0; i < EltStride; ++i) {
6828 // If V[i+EltStride] is undef and this is the first round of mixing,
6829 // then it is safe to just drop this shuffle: V[i] is already in the
6830 // right place, the one element (since it's the first round) being
6831 // inserted as undef can be dropped. This isn't safe for successive
6832 // rounds because they will permute elements within both vectors.
6833 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6834 EltStride == NumElems/2)
6837 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6846 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6847 // to create 256-bit vectors from two other 128-bit ones.
6848 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6850 MVT ResVT = Op.getSimpleValueType();
6852 assert((ResVT.is256BitVector() ||
6853 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6855 SDValue V1 = Op.getOperand(0);
6856 SDValue V2 = Op.getOperand(1);
6857 unsigned NumElems = ResVT.getVectorNumElements();
6858 if(ResVT.is256BitVector())
6859 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6861 if (Op.getNumOperands() == 4) {
6862 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6863 ResVT.getVectorNumElements()/2);
6864 SDValue V3 = Op.getOperand(2);
6865 SDValue V4 = Op.getOperand(3);
6866 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6867 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6869 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6872 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6873 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6874 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6875 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6876 Op.getNumOperands() == 4)));
6878 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6879 // from two other 128-bit ones.
6881 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6882 return LowerAVXCONCAT_VECTORS(Op, DAG);
6886 //===----------------------------------------------------------------------===//
6887 // Vector shuffle lowering
6889 // This is an experimental code path for lowering vector shuffles on x86. It is
6890 // designed to handle arbitrary vector shuffles and blends, gracefully
6891 // degrading performance as necessary. It works hard to recognize idiomatic
6892 // shuffles and lower them to optimal instruction patterns without leaving
6893 // a framework that allows reasonably efficient handling of all vector shuffle
6895 //===----------------------------------------------------------------------===//
6897 /// \brief Tiny helper function to identify a no-op mask.
6899 /// This is a somewhat boring predicate function. It checks whether the mask
6900 /// array input, which is assumed to be a single-input shuffle mask of the kind
6901 /// used by the X86 shuffle instructions (not a fully general
6902 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6903 /// in-place shuffle are 'no-op's.
6904 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6905 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6906 if (Mask[i] != -1 && Mask[i] != i)
6911 /// \brief Helper function to classify a mask as a single-input mask.
6913 /// This isn't a generic single-input test because in the vector shuffle
6914 /// lowering we canonicalize single inputs to be the first input operand. This
6915 /// means we can more quickly test for a single input by only checking whether
6916 /// an input from the second operand exists. We also assume that the size of
6917 /// mask corresponds to the size of the input vectors which isn't true in the
6918 /// fully general case.
6919 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6921 if (M >= (int)Mask.size())
6926 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6928 /// This helper function produces an 8-bit shuffle immediate corresponding to
6929 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6930 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6933 /// NB: We rely heavily on "undef" masks preserving the input lane.
6934 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6935 SelectionDAG &DAG) {
6936 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6937 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6938 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6939 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6940 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6943 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6944 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6945 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6946 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6947 return DAG.getConstant(Imm, MVT::i8);
6950 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
6952 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
6953 /// support for floating point shuffles but not integer shuffles. These
6954 /// instructions will incur a domain crossing penalty on some chips though so
6955 /// it is better to avoid lowering through this for integer vectors where
6957 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6958 const X86Subtarget *Subtarget,
6959 SelectionDAG &DAG) {
6961 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
6962 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6963 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6964 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6965 ArrayRef<int> Mask = SVOp->getMask();
6966 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
6968 if (isSingleInputShuffleMask(Mask)) {
6969 // Straight shuffle of a single input vector. Simulate this by using the
6970 // single input as both of the "inputs" to this instruction..
6971 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
6972 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
6973 DAG.getConstant(SHUFPDMask, MVT::i8));
6975 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
6976 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
6978 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
6979 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
6980 DAG.getConstant(SHUFPDMask, MVT::i8));
6983 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
6985 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
6986 /// the integer unit to minimize domain crossing penalties. However, for blends
6987 /// it falls back to the floating point shuffle operation with appropriate bit
6989 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6990 const X86Subtarget *Subtarget,
6991 SelectionDAG &DAG) {
6993 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
6994 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6995 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6997 ArrayRef<int> Mask = SVOp->getMask();
6998 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7000 if (isSingleInputShuffleMask(Mask)) {
7001 // Straight shuffle of a single input vector. For everything from SSE2
7002 // onward this has a single fast instruction with no scary immediates.
7003 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7004 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7005 int WidenedMask[4] = {
7006 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7007 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7009 ISD::BITCAST, DL, MVT::v2i64,
7010 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7011 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7014 // We implement this with SHUFPD which is pretty lame because it will likely
7015 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7016 // However, all the alternatives are still more cycles and newer chips don't
7017 // have this problem. It would be really nice if x86 had better shuffles here.
7018 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7019 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7020 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7021 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7024 /// \brief Lower 4-lane 32-bit floating point shuffles.
7026 /// Uses instructions exclusively from the floating point unit to minimize
7027 /// domain crossing penalties, as these are sufficient to implement all v4f32
7029 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7030 const X86Subtarget *Subtarget,
7031 SelectionDAG &DAG) {
7033 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7034 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7035 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7037 ArrayRef<int> Mask = SVOp->getMask();
7038 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7040 SDValue LowV = V1, HighV = V2;
7041 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7044 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7046 if (NumV2Elements == 0)
7047 // Straight shuffle of a single input vector. We pass the input vector to
7048 // both operands to simulate this with a SHUFPS.
7049 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7050 getV4X86ShuffleImm8ForMask(Mask, DAG));
7052 if (NumV2Elements == 1) {
7054 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7056 // Compute the index adjacent to V2Index and in the same half by toggling
7058 int V2AdjIndex = V2Index ^ 1;
7060 if (Mask[V2AdjIndex] == -1) {
7061 // Handles all the cases where we have a single V2 element and an undef.
7062 // This will only ever happen in the high lanes because we commute the
7063 // vector otherwise.
7065 std::swap(LowV, HighV);
7066 NewMask[V2Index] -= 4;
7068 // Handle the case where the V2 element ends up adjacent to a V1 element.
7069 // To make this work, blend them together as the first step.
7070 int V1Index = V2AdjIndex;
7071 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7072 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7073 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7075 // Now proceed to reconstruct the final blend as we have the necessary
7076 // high or low half formed.
7083 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7084 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7086 } else if (NumV2Elements == 2) {
7087 if (Mask[0] < 4 && Mask[1] < 4) {
7088 // Handle the easy case where we have V1 in the low lanes and V2 in the
7089 // high lanes. We never see this reversed because we sort the shuffle.
7093 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7094 // trying to place elements directly, just blend them and set up the final
7095 // shuffle to place them.
7097 // The first two blend mask elements are for V1, the second two are for
7099 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7100 Mask[2] < 4 ? Mask[2] : Mask[3],
7101 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7102 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7103 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7104 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7106 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7109 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7110 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7111 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7112 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7115 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7116 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7119 /// \brief Lower 4-lane i32 vector shuffles.
7121 /// We try to handle these with integer-domain shuffles where we can, but for
7122 /// blends we use the floating point domain blend instructions.
7123 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7124 const X86Subtarget *Subtarget,
7125 SelectionDAG &DAG) {
7127 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7128 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7129 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7130 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7131 ArrayRef<int> Mask = SVOp->getMask();
7132 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7134 if (isSingleInputShuffleMask(Mask))
7135 // Straight shuffle of a single input vector. For everything from SSE2
7136 // onward this has a single fast instruction with no scary immediates.
7137 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7138 getV4X86ShuffleImm8ForMask(Mask, DAG));
7140 // We implement this with SHUFPS because it can blend from two vectors.
7141 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7142 // up the inputs, bypassing domain shift penalties that we would encur if we
7143 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7145 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7146 DAG.getVectorShuffle(
7148 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7149 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7152 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7153 /// shuffle lowering, and the most complex part.
7155 /// The lowering strategy is to try to form pairs of input lanes which are
7156 /// targeted at the same half of the final vector, and then use a dword shuffle
7157 /// to place them onto the right half, and finally unpack the paired lanes into
7158 /// their final position.
7160 /// The exact breakdown of how to form these dword pairs and align them on the
7161 /// correct sides is really tricky. See the comments within the function for
7162 /// more of the details.
7163 static SDValue lowerV8I16SingleInputVectorShuffle(
7164 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7165 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7166 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7167 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7168 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7170 SmallVector<int, 4> LoInputs;
7171 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7172 [](int M) { return M >= 0; });
7173 std::sort(LoInputs.begin(), LoInputs.end());
7174 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7175 SmallVector<int, 4> HiInputs;
7176 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7177 [](int M) { return M >= 0; });
7178 std::sort(HiInputs.begin(), HiInputs.end());
7179 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7181 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7182 int NumHToL = LoInputs.size() - NumLToL;
7184 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7185 int NumHToH = HiInputs.size() - NumLToH;
7186 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7187 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7188 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7189 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7191 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7192 // such inputs we can swap two of the dwords across the half mark and end up
7193 // with <=2 inputs to each half in each half. Once there, we can fall through
7194 // to the generic code below. For example:
7196 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7197 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7199 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7201 auto balanceSides = [&](ArrayRef<int> ThreeInputs, int OneInput,
7202 int ThreeInputHalfSum, int OneInputHalfOffset) {
7203 // Compute the index of dword with only one word among the three inputs in
7204 // a half by taking the sum of the half with three inputs and subtracting
7205 // the sum of the actual three inputs. The difference is the remaining
7207 int DWordA = (ThreeInputHalfSum -
7208 std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
7210 int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
7212 int PSHUFDMask[] = {0, 1, 2, 3};
7213 PSHUFDMask[DWordA] = DWordB;
7214 PSHUFDMask[DWordB] = DWordA;
7215 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7216 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7217 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7218 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7220 // Adjust the mask to match the new locations of A and B.
7222 if (M != -1 && M/2 == DWordA)
7223 M = 2 * DWordB + M % 2;
7224 else if (M != -1 && M/2 == DWordB)
7225 M = 2 * DWordA + M % 2;
7227 // Recurse back into this routine to re-compute state now that this isn't
7228 // a 3 and 1 problem.
7229 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7232 if (NumLToL == 3 && NumHToL == 1)
7233 return balanceSides(LToLInputs, HToLInputs[0], 0 + 1 + 2 + 3, 4);
7234 else if (NumLToL == 1 && NumHToL == 3)
7235 return balanceSides(HToLInputs, LToLInputs[0], 4 + 5 + 6 + 7, 0);
7236 else if (NumLToH == 1 && NumHToH == 3)
7237 return balanceSides(HToHInputs, LToHInputs[0], 4 + 5 + 6 + 7, 0);
7238 else if (NumLToH == 3 && NumHToH == 1)
7239 return balanceSides(LToHInputs, HToHInputs[0], 0 + 1 + 2 + 3, 4);
7241 // At this point there are at most two inputs to the low and high halves from
7242 // each half. That means the inputs can always be grouped into dwords and
7243 // those dwords can then be moved to the correct half with a dword shuffle.
7244 // We use at most one low and one high word shuffle to collect these paired
7245 // inputs into dwords, and finally a dword shuffle to place them.
7246 int PSHUFLMask[4] = {-1, -1, -1, -1};
7247 int PSHUFHMask[4] = {-1, -1, -1, -1};
7248 int PSHUFDMask[4] = {-1, -1, -1, -1};
7250 // First fix the masks for all the inputs that are staying in their
7251 // original halves. This will then dictate the targets of the cross-half
7253 auto fixInPlaceInputs = [&PSHUFDMask](
7254 ArrayRef<int> InPlaceInputs, MutableArrayRef<int> SourceHalfMask,
7255 MutableArrayRef<int> HalfMask, int HalfOffset) {
7256 if (InPlaceInputs.empty())
7258 if (InPlaceInputs.size() == 1) {
7259 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7260 InPlaceInputs[0] - HalfOffset;
7261 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7265 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7266 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7267 InPlaceInputs[0] - HalfOffset;
7268 // Put the second input next to the first so that they are packed into
7269 // a dword. We find the adjacent index by toggling the low bit.
7270 int AdjIndex = InPlaceInputs[0] ^ 1;
7271 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7272 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7273 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7275 if (!HToLInputs.empty())
7276 fixInPlaceInputs(LToLInputs, PSHUFLMask, LoMask, 0);
7277 if (!LToHInputs.empty())
7278 fixInPlaceInputs(HToHInputs, PSHUFHMask, HiMask, 4);
7280 // Now gather the cross-half inputs and place them into a free dword of
7281 // their target half.
7282 // FIXME: This operation could almost certainly be simplified dramatically to
7283 // look more like the 3-1 fixing operation.
7284 auto moveInputsToRightHalf = [&PSHUFDMask](
7285 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7286 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7287 int SourceOffset, int DestOffset) {
7288 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7289 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7291 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7293 int LowWord = Word & ~1;
7294 int HighWord = Word | 1;
7295 return isWordClobbered(SourceHalfMask, LowWord) ||
7296 isWordClobbered(SourceHalfMask, HighWord);
7299 if (IncomingInputs.empty())
7302 if (ExistingInputs.empty()) {
7303 // Map any dwords with inputs from them into the right half.
7304 for (int Input : IncomingInputs) {
7305 // If the source half mask maps over the inputs, turn those into
7306 // swaps and use the swapped lane.
7307 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7308 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7309 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7310 Input - SourceOffset;
7311 // We have to swap the uses in our half mask in one sweep.
7312 for (int &M : HalfMask)
7313 if (M == SourceHalfMask[Input - SourceOffset])
7315 else if (M == Input)
7316 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7318 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7319 Input - SourceOffset &&
7320 "Previous placement doesn't match!");
7322 // Note that this correctly re-maps both when we do a swap and when
7323 // we observe the other side of the swap above. We rely on that to
7324 // avoid swapping the members of the input list directly.
7325 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7328 // Map the input's dword into the correct half.
7329 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7330 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7332 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7334 "Previous placement doesn't match!");
7337 // And just directly shift any other-half mask elements to be same-half
7338 // as we will have mirrored the dword containing the element into the
7339 // same position within that half.
7340 for (int &M : HalfMask)
7341 if (M >= SourceOffset && M < SourceOffset + 4) {
7342 M = M - SourceOffset + DestOffset;
7343 assert(M >= 0 && "This should never wrap below zero!");
7348 // Ensure we have the input in a viable dword of its current half. This
7349 // is particularly tricky because the original position may be clobbered
7350 // by inputs being moved and *staying* in that half.
7351 if (IncomingInputs.size() == 1) {
7352 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7353 int InputFixed = std::find(std::begin(SourceHalfMask),
7354 std::end(SourceHalfMask), -1) -
7355 std::begin(SourceHalfMask) + SourceOffset;
7356 SourceHalfMask[InputFixed - SourceOffset] =
7357 IncomingInputs[0] - SourceOffset;
7358 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7360 IncomingInputs[0] = InputFixed;
7362 } else if (IncomingInputs.size() == 2) {
7363 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7364 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7365 int SourceDWordBase = !isDWordClobbered(SourceHalfMask, 0) ? 0 : 2;
7366 assert(!isDWordClobbered(SourceHalfMask, SourceDWordBase) &&
7367 "Not all dwords can be clobbered!");
7368 SourceHalfMask[SourceDWordBase] = IncomingInputs[0] - SourceOffset;
7369 SourceHalfMask[SourceDWordBase + 1] = IncomingInputs[1] - SourceOffset;
7370 for (int &M : HalfMask)
7371 if (M == IncomingInputs[0])
7372 M = SourceDWordBase + SourceOffset;
7373 else if (M == IncomingInputs[1])
7374 M = SourceDWordBase + 1 + SourceOffset;
7375 IncomingInputs[0] = SourceDWordBase + SourceOffset;
7376 IncomingInputs[1] = SourceDWordBase + 1 + SourceOffset;
7379 llvm_unreachable("Unhandled input size!");
7382 // Now hoist the DWord down to the right half.
7383 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7384 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7385 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7386 for (int Input : IncomingInputs)
7387 std::replace(HalfMask.begin(), HalfMask.end(), Input,
7388 FreeDWord * 2 + Input % 2);
7390 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask,
7391 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7392 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask,
7393 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7395 // Now enact all the shuffles we've computed to move the inputs into their
7397 if (!isNoopShuffleMask(PSHUFLMask))
7398 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7399 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7400 if (!isNoopShuffleMask(PSHUFHMask))
7401 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7402 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7403 if (!isNoopShuffleMask(PSHUFDMask))
7404 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7405 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7406 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7407 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7409 // At this point, each half should contain all its inputs, and we can then
7410 // just shuffle them into their final position.
7411 assert(std::count_if(LoMask.begin(), LoMask.end(),
7412 [](int M) { return M >= 4; }) == 0 &&
7413 "Failed to lift all the high half inputs to the low mask!");
7414 assert(std::count_if(HiMask.begin(), HiMask.end(),
7415 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7416 "Failed to lift all the low half inputs to the high mask!");
7418 // Do a half shuffle for the low mask.
7419 if (!isNoopShuffleMask(LoMask))
7420 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7421 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7423 // Do a half shuffle with the high mask after shifting its values down.
7424 for (int &M : HiMask)
7427 if (!isNoopShuffleMask(HiMask))
7428 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7429 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7434 /// \brief Detect whether the mask pattern should be lowered through
7437 /// This essentially tests whether viewing the mask as an interleaving of two
7438 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7439 /// lowering it through interleaving is a significantly better strategy.
7440 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7441 int NumEvenInputs[2] = {0, 0};
7442 int NumOddInputs[2] = {0, 0};
7443 int NumLoInputs[2] = {0, 0};
7444 int NumHiInputs[2] = {0, 0};
7445 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7449 int InputIdx = Mask[i] >= Size;
7452 ++NumLoInputs[InputIdx];
7454 ++NumHiInputs[InputIdx];
7457 ++NumEvenInputs[InputIdx];
7459 ++NumOddInputs[InputIdx];
7462 // The minimum number of cross-input results for both the interleaved and
7463 // split cases. If interleaving results in fewer cross-input results, return
7465 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7466 NumEvenInputs[0] + NumOddInputs[1]);
7467 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7468 NumLoInputs[0] + NumHiInputs[1]);
7469 return InterleavedCrosses < SplitCrosses;
7472 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7474 /// This strategy only works when the inputs from each vector fit into a single
7475 /// half of that vector, and generally there are not so many inputs as to leave
7476 /// the in-place shuffles required highly constrained (and thus expensive). It
7477 /// shifts all the inputs into a single side of both input vectors and then
7478 /// uses an unpack to interleave these inputs in a single vector. At that
7479 /// point, we will fall back on the generic single input shuffle lowering.
7480 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7482 MutableArrayRef<int> Mask,
7483 const X86Subtarget *Subtarget,
7484 SelectionDAG &DAG) {
7485 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7486 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7487 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7488 for (int i = 0; i < 8; ++i)
7489 if (Mask[i] >= 0 && Mask[i] < 4)
7490 LoV1Inputs.push_back(i);
7491 else if (Mask[i] >= 4 && Mask[i] < 8)
7492 HiV1Inputs.push_back(i);
7493 else if (Mask[i] >= 8 && Mask[i] < 12)
7494 LoV2Inputs.push_back(i);
7495 else if (Mask[i] >= 12)
7496 HiV2Inputs.push_back(i);
7498 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7499 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7502 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7503 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7504 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7506 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7507 HiV1Inputs.size() + HiV2Inputs.size();
7509 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7510 ArrayRef<int> HiInputs, bool MoveToLo,
7512 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7513 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7514 if (BadInputs.empty())
7517 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7518 int MoveOffset = MoveToLo ? 0 : 4;
7520 if (GoodInputs.empty()) {
7521 for (int BadInput : BadInputs) {
7522 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7523 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7526 if (GoodInputs.size() == 2) {
7527 // If the low inputs are spread across two dwords, pack them into
7529 MoveMask[Mask[GoodInputs[0]] % 2 + MoveOffset] =
7530 Mask[GoodInputs[0]] - MaskOffset;
7531 MoveMask[Mask[GoodInputs[1]] % 2 + MoveOffset] =
7532 Mask[GoodInputs[1]] - MaskOffset;
7533 Mask[GoodInputs[0]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7534 Mask[GoodInputs[1]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7536 // Otherwise pin the low inputs.
7537 for (int GoodInput : GoodInputs)
7538 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7542 std::find(std::begin(MoveMask) + MoveOffset, std::end(MoveMask), -1) -
7543 std::begin(MoveMask);
7544 assert(MoveMaskIdx >= MoveOffset && "Established above");
7546 if (BadInputs.size() == 2) {
7547 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7548 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7549 MoveMask[MoveMaskIdx + Mask[BadInputs[0]] % 2] =
7550 Mask[BadInputs[0]] - MaskOffset;
7551 MoveMask[MoveMaskIdx + Mask[BadInputs[1]] % 2] =
7552 Mask[BadInputs[1]] - MaskOffset;
7553 Mask[BadInputs[0]] = MoveMaskIdx + Mask[BadInputs[0]] % 2 + MaskOffset;
7554 Mask[BadInputs[1]] = MoveMaskIdx + Mask[BadInputs[1]] % 2 + MaskOffset;
7556 assert(BadInputs.size() == 1 && "All sizes handled");
7557 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7558 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7562 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7565 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7567 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7570 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7571 // cross-half traffic in the final shuffle.
7573 // Munge the mask to be a single-input mask after the unpack merges the
7577 M = 2 * (M % 4) + (M / 8);
7579 return DAG.getVectorShuffle(
7580 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7581 DL, MVT::v8i16, V1, V2),
7582 DAG.getUNDEF(MVT::v8i16), Mask);
7585 /// \brief Generic lowering of 8-lane i16 shuffles.
7587 /// This handles both single-input shuffles and combined shuffle/blends with
7588 /// two inputs. The single input shuffles are immediately delegated to
7589 /// a dedicated lowering routine.
7591 /// The blends are lowered in one of three fundamental ways. If there are few
7592 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7593 /// of the input is significantly cheaper when lowered as an interleaving of
7594 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7595 /// halves of the inputs separately (making them have relatively few inputs)
7596 /// and then concatenate them.
7597 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7598 const X86Subtarget *Subtarget,
7599 SelectionDAG &DAG) {
7601 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7602 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7603 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7604 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7605 ArrayRef<int> OrigMask = SVOp->getMask();
7606 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7607 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7608 MutableArrayRef<int> Mask(MaskStorage);
7610 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7612 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7613 auto isV2 = [](int M) { return M >= 8; };
7615 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7616 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7618 if (NumV2Inputs == 0)
7619 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7621 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7622 "to be V1-input shuffles.");
7624 if (NumV1Inputs + NumV2Inputs <= 4)
7625 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7627 // Check whether an interleaving lowering is likely to be more efficient.
7628 // This isn't perfect but it is a strong heuristic that tends to work well on
7629 // the kinds of shuffles that show up in practice.
7631 // FIXME: Handle 1x, 2x, and 4x interleaving.
7632 if (shouldLowerAsInterleaving(Mask)) {
7633 // FIXME: Figure out whether we should pack these into the low or high
7636 int EMask[8], OMask[8];
7637 for (int i = 0; i < 4; ++i) {
7638 EMask[i] = Mask[2*i];
7639 OMask[i] = Mask[2*i + 1];
7644 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7645 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7647 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7650 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7651 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7653 for (int i = 0; i < 4; ++i) {
7654 LoBlendMask[i] = Mask[i];
7655 HiBlendMask[i] = Mask[i + 4];
7658 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7659 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7660 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7661 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7663 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7664 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7667 /// \brief Generic lowering of v16i8 shuffles.
7669 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7670 /// detect any complexity reducing interleaving. If that doesn't help, it uses
7671 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
7672 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
7674 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7675 const X86Subtarget *Subtarget,
7676 SelectionDAG &DAG) {
7678 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7679 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7680 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7681 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7682 ArrayRef<int> OrigMask = SVOp->getMask();
7683 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
7684 int MaskStorage[16] = {
7685 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7686 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
7687 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
7688 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
7689 MutableArrayRef<int> Mask(MaskStorage);
7690 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
7691 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
7693 // For single-input shuffles, there are some nicer lowering tricks we can use.
7694 if (isSingleInputShuffleMask(Mask)) {
7695 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
7696 // Notably, this handles splat and partial-splat shuffles more efficiently.
7697 // However, it only makes sense if the pre-duplication shuffle simplifies
7698 // things significantly. Currently, this means we need to be able to
7699 // express the pre-duplication shuffle as an i16 shuffle.
7701 // FIXME: We should check for other patterns which can be widened into an
7702 // i16 shuffle as well.
7703 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
7704 for (int i = 0; i < 16; i += 2) {
7705 if (Mask[i] != Mask[i + 1])
7710 auto tryToWidenViaDuplication = [&]() -> SDValue {
7711 if (!canWidenViaDuplication(Mask))
7713 SmallVector<int, 4> LoInputs;
7714 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
7715 [](int M) { return M >= 0 && M < 8; });
7716 std::sort(LoInputs.begin(), LoInputs.end());
7717 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
7719 SmallVector<int, 4> HiInputs;
7720 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
7721 [](int M) { return M >= 8; });
7722 std::sort(HiInputs.begin(), HiInputs.end());
7723 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
7726 bool TargetLo = LoInputs.size() >= HiInputs.size();
7727 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
7728 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
7730 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7731 SmallDenseMap<int, int, 8> LaneMap;
7732 for (int I : InPlaceInputs) {
7733 PreDupI16Shuffle[I/2] = I/2;
7736 int j = TargetLo ? 0 : 4, je = j + 4;
7737 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
7738 // Check if j is already a shuffle of this input. This happens when
7739 // there are two adjacent bytes after we move the low one.
7740 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
7741 // If we haven't yet mapped the input, search for a slot into which
7743 while (j < je && PreDupI16Shuffle[j] != -1)
7747 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
7750 // Map this input with the i16 shuffle.
7751 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
7754 // Update the lane map based on the mapping we ended up with.
7755 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
7758 ISD::BITCAST, DL, MVT::v16i8,
7759 DAG.getVectorShuffle(MVT::v8i16, DL,
7760 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7761 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
7763 // Unpack the bytes to form the i16s that will be shuffled into place.
7764 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7765 MVT::v16i8, V1, V1);
7767 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7768 for (int i = 0; i < 16; i += 2) {
7770 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
7771 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
7774 ISD::BITCAST, DL, MVT::v16i8,
7775 DAG.getVectorShuffle(MVT::v8i16, DL,
7776 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7777 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
7779 if (SDValue V = tryToWidenViaDuplication())
7783 // Check whether an interleaving lowering is likely to be more efficient.
7784 // This isn't perfect but it is a strong heuristic that tends to work well on
7785 // the kinds of shuffles that show up in practice.
7787 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
7788 if (shouldLowerAsInterleaving(Mask)) {
7789 // FIXME: Figure out whether we should pack these into the low or high
7792 int EMask[16], OMask[16];
7793 for (int i = 0; i < 8; ++i) {
7794 EMask[i] = Mask[2*i];
7795 OMask[i] = Mask[2*i + 1];
7800 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
7801 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
7803 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
7806 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7807 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7808 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7809 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7811 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
7812 MutableArrayRef<int> V1HalfBlendMask,
7813 MutableArrayRef<int> V2HalfBlendMask) {
7814 for (int i = 0; i < 8; ++i)
7815 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
7816 V1HalfBlendMask[i] = HalfMask[i];
7818 } else if (HalfMask[i] >= 16) {
7819 V2HalfBlendMask[i] = HalfMask[i] - 16;
7820 HalfMask[i] = i + 8;
7823 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
7824 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
7826 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
7828 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
7829 MutableArrayRef<int> HiBlendMask) {
7831 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
7832 // them out and avoid using UNPCK{L,H} to extract the elements of V as
7834 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
7835 [](int M) { return M >= 0 && M % 2 == 1; }) &&
7836 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
7837 [](int M) { return M >= 0 && M % 2 == 1; })) {
7838 // Use a mask to drop the high bytes.
7839 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
7840 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
7841 DAG.getConstant(0x00FF, MVT::v8i16));
7843 // This will be a single vector shuffle instead of a blend so nuke V2.
7844 V2 = DAG.getUNDEF(MVT::v8i16);
7846 // Squash the masks to point directly into V1.
7847 for (int &M : LoBlendMask)
7850 for (int &M : HiBlendMask)
7854 // Otherwise just unpack the low half of V into V1 and the high half into
7855 // V2 so that we can blend them as i16s.
7856 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7857 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
7858 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7859 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
7862 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7863 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7864 return std::make_pair(BlendedLo, BlendedHi);
7866 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
7867 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
7868 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
7870 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
7871 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
7873 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
7876 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
7878 /// This routine breaks down the specific type of 128-bit shuffle and
7879 /// dispatches to the lowering routines accordingly.
7880 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7881 MVT VT, const X86Subtarget *Subtarget,
7882 SelectionDAG &DAG) {
7883 switch (VT.SimpleTy) {
7885 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7887 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7889 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7891 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7893 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
7895 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
7898 llvm_unreachable("Unimplemented!");
7902 /// \brief Tiny helper function to test whether adjacent masks are sequential.
7903 static bool areAdjacentMasksSequential(ArrayRef<int> Mask) {
7904 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7905 if (Mask[i] + 1 != Mask[i+1])
7911 /// \brief Top-level lowering for x86 vector shuffles.
7913 /// This handles decomposition, canonicalization, and lowering of all x86
7914 /// vector shuffles. Most of the specific lowering strategies are encapsulated
7915 /// above in helper routines. The canonicalization attempts to widen shuffles
7916 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
7917 /// s.t. only one of the two inputs needs to be tested, etc.
7918 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7919 SelectionDAG &DAG) {
7920 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7921 ArrayRef<int> Mask = SVOp->getMask();
7922 SDValue V1 = Op.getOperand(0);
7923 SDValue V2 = Op.getOperand(1);
7924 MVT VT = Op.getSimpleValueType();
7925 int NumElements = VT.getVectorNumElements();
7928 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7930 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7931 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7932 if (V1IsUndef && V2IsUndef)
7933 return DAG.getUNDEF(VT);
7935 // When we create a shuffle node we put the UNDEF node to second operand,
7936 // but in some cases the first operand may be transformed to UNDEF.
7937 // In this case we should just commute the node.
7939 return CommuteVectorShuffle(SVOp, DAG);
7941 // Check for non-undef masks pointing at an undef vector and make the masks
7942 // undef as well. This makes it easier to match the shuffle based solely on
7946 if (M >= NumElements) {
7947 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
7948 for (int &M : NewMask)
7949 if (M >= NumElements)
7951 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
7954 // For integer vector shuffles, try to collapse them into a shuffle of fewer
7955 // lanes but wider integers. We cap this to not form integers larger than i64
7956 // but it might be interesting to form i128 integers to handle flipping the
7957 // low and high halves of AVX 256-bit vectors.
7958 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
7959 areAdjacentMasksSequential(Mask)) {
7960 SmallVector<int, 8> NewMask;
7961 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7962 NewMask.push_back(Mask[i] / 2);
7964 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
7965 VT.getVectorNumElements() / 2);
7966 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
7967 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
7968 return DAG.getNode(ISD::BITCAST, dl, VT,
7969 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
7972 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
7973 for (int M : SVOp->getMask())
7976 else if (M < NumElements)
7981 // Commute the shuffle as needed such that more elements come from V1 than
7982 // V2. This allows us to match the shuffle pattern strictly on how many
7983 // elements come from V1 without handling the symmetric cases.
7984 if (NumV2Elements > NumV1Elements)
7985 return CommuteVectorShuffle(SVOp, DAG);
7987 // When the number of V1 and V2 elements are the same, try to minimize the
7988 // number of uses of V2 in the low half of the vector.
7989 if (NumV1Elements == NumV2Elements) {
7990 int LowV1Elements = 0, LowV2Elements = 0;
7991 for (int M : SVOp->getMask().slice(0, NumElements / 2))
7992 if (M >= NumElements)
7996 if (LowV2Elements > LowV1Elements)
7997 return CommuteVectorShuffle(SVOp, DAG);
8000 // For each vector width, delegate to a specialized lowering routine.
8001 if (VT.getSizeInBits() == 128)
8002 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8004 llvm_unreachable("Unimplemented!");
8008 //===----------------------------------------------------------------------===//
8009 // Legacy vector shuffle lowering
8011 // This code is the legacy code handling vector shuffles until the above
8012 // replaces its functionality and performance.
8013 //===----------------------------------------------------------------------===//
8015 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8016 bool hasInt256, unsigned *MaskOut = nullptr) {
8017 MVT EltVT = VT.getVectorElementType();
8019 // There is no blend with immediate in AVX-512.
8020 if (VT.is512BitVector())
8023 if (!hasSSE41 || EltVT == MVT::i8)
8025 if (!hasInt256 && VT == MVT::v16i16)
8028 unsigned MaskValue = 0;
8029 unsigned NumElems = VT.getVectorNumElements();
8030 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8031 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8032 unsigned NumElemsInLane = NumElems / NumLanes;
8034 // Blend for v16i16 should be symetric for the both lanes.
8035 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8037 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8038 int EltIdx = MaskVals[i];
8040 if ((EltIdx < 0 || EltIdx == (int)i) &&
8041 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8044 if (((unsigned)EltIdx == (i + NumElems)) &&
8045 (SndLaneEltIdx < 0 ||
8046 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8047 MaskValue |= (1 << i);
8053 *MaskOut = MaskValue;
8057 // Try to lower a shuffle node into a simple blend instruction.
8058 // This function assumes isBlendMask returns true for this
8059 // SuffleVectorSDNode
8060 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8062 const X86Subtarget *Subtarget,
8063 SelectionDAG &DAG) {
8064 MVT VT = SVOp->getSimpleValueType(0);
8065 MVT EltVT = VT.getVectorElementType();
8066 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8067 Subtarget->hasInt256() && "Trying to lower a "
8068 "VECTOR_SHUFFLE to a Blend but "
8069 "with the wrong mask"));
8070 SDValue V1 = SVOp->getOperand(0);
8071 SDValue V2 = SVOp->getOperand(1);
8073 unsigned NumElems = VT.getVectorNumElements();
8075 // Convert i32 vectors to floating point if it is not AVX2.
8076 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8078 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8079 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8081 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8082 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8085 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8086 DAG.getConstant(MaskValue, MVT::i32));
8087 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8090 /// In vector type \p VT, return true if the element at index \p InputIdx
8091 /// falls on a different 128-bit lane than \p OutputIdx.
8092 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8093 unsigned OutputIdx) {
8094 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8095 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8098 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8099 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8100 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8101 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8103 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8104 SelectionDAG &DAG) {
8105 MVT VT = V1.getSimpleValueType();
8106 assert(VT.is128BitVector() || VT.is256BitVector());
8108 MVT EltVT = VT.getVectorElementType();
8109 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8110 unsigned NumElts = VT.getVectorNumElements();
8112 SmallVector<SDValue, 32> PshufbMask;
8113 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8114 int InputIdx = MaskVals[OutputIdx];
8115 unsigned InputByteIdx;
8117 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8118 InputByteIdx = 0x80;
8120 // Cross lane is not allowed.
8121 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8123 InputByteIdx = InputIdx * EltSizeInBytes;
8124 // Index is an byte offset within the 128-bit lane.
8125 InputByteIdx &= 0xf;
8128 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8129 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8130 if (InputByteIdx != 0x80)
8135 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8137 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8138 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8139 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8142 // v8i16 shuffles - Prefer shuffles in the following order:
8143 // 1. [all] pshuflw, pshufhw, optional move
8144 // 2. [ssse3] 1 x pshufb
8145 // 3. [ssse3] 2 x pshufb + 1 x por
8146 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8148 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8149 SelectionDAG &DAG) {
8150 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8151 SDValue V1 = SVOp->getOperand(0);
8152 SDValue V2 = SVOp->getOperand(1);
8154 SmallVector<int, 8> MaskVals;
8156 // Determine if more than 1 of the words in each of the low and high quadwords
8157 // of the result come from the same quadword of one of the two inputs. Undef
8158 // mask values count as coming from any quadword, for better codegen.
8160 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8161 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8162 unsigned LoQuad[] = { 0, 0, 0, 0 };
8163 unsigned HiQuad[] = { 0, 0, 0, 0 };
8164 // Indices of quads used.
8165 std::bitset<4> InputQuads;
8166 for (unsigned i = 0; i < 8; ++i) {
8167 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8168 int EltIdx = SVOp->getMaskElt(i);
8169 MaskVals.push_back(EltIdx);
8178 InputQuads.set(EltIdx / 4);
8181 int BestLoQuad = -1;
8182 unsigned MaxQuad = 1;
8183 for (unsigned i = 0; i < 4; ++i) {
8184 if (LoQuad[i] > MaxQuad) {
8186 MaxQuad = LoQuad[i];
8190 int BestHiQuad = -1;
8192 for (unsigned i = 0; i < 4; ++i) {
8193 if (HiQuad[i] > MaxQuad) {
8195 MaxQuad = HiQuad[i];
8199 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8200 // of the two input vectors, shuffle them into one input vector so only a
8201 // single pshufb instruction is necessary. If there are more than 2 input
8202 // quads, disable the next transformation since it does not help SSSE3.
8203 bool V1Used = InputQuads[0] || InputQuads[1];
8204 bool V2Used = InputQuads[2] || InputQuads[3];
8205 if (Subtarget->hasSSSE3()) {
8206 if (InputQuads.count() == 2 && V1Used && V2Used) {
8207 BestLoQuad = InputQuads[0] ? 0 : 1;
8208 BestHiQuad = InputQuads[2] ? 2 : 3;
8210 if (InputQuads.count() > 2) {
8216 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8217 // the shuffle mask. If a quad is scored as -1, that means that it contains
8218 // words from all 4 input quadwords.
8220 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8222 BestLoQuad < 0 ? 0 : BestLoQuad,
8223 BestHiQuad < 0 ? 1 : BestHiQuad
8225 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8226 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8227 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8228 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8230 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8231 // source words for the shuffle, to aid later transformations.
8232 bool AllWordsInNewV = true;
8233 bool InOrder[2] = { true, true };
8234 for (unsigned i = 0; i != 8; ++i) {
8235 int idx = MaskVals[i];
8237 InOrder[i/4] = false;
8238 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8240 AllWordsInNewV = false;
8244 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8245 if (AllWordsInNewV) {
8246 for (int i = 0; i != 8; ++i) {
8247 int idx = MaskVals[i];
8250 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8251 if ((idx != i) && idx < 4)
8253 if ((idx != i) && idx > 3)
8262 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8263 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8264 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8265 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8266 unsigned TargetMask = 0;
8267 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8268 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8269 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8270 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8271 getShufflePSHUFLWImmediate(SVOp);
8272 V1 = NewV.getOperand(0);
8273 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8277 // Promote splats to a larger type which usually leads to more efficient code.
8278 // FIXME: Is this true if pshufb is available?
8279 if (SVOp->isSplat())
8280 return PromoteSplat(SVOp, DAG);
8282 // If we have SSSE3, and all words of the result are from 1 input vector,
8283 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8284 // is present, fall back to case 4.
8285 if (Subtarget->hasSSSE3()) {
8286 SmallVector<SDValue,16> pshufbMask;
8288 // If we have elements from both input vectors, set the high bit of the
8289 // shuffle mask element to zero out elements that come from V2 in the V1
8290 // mask, and elements that come from V1 in the V2 mask, so that the two
8291 // results can be OR'd together.
8292 bool TwoInputs = V1Used && V2Used;
8293 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8295 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8297 // Calculate the shuffle mask for the second input, shuffle it, and
8298 // OR it with the first shuffled input.
8299 CommuteVectorShuffleMask(MaskVals, 8);
8300 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8301 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8302 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8305 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8306 // and update MaskVals with new element order.
8307 std::bitset<8> InOrder;
8308 if (BestLoQuad >= 0) {
8309 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8310 for (int i = 0; i != 4; ++i) {
8311 int idx = MaskVals[i];
8314 } else if ((idx / 4) == BestLoQuad) {
8319 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8322 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8323 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8324 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8326 getShufflePSHUFLWImmediate(SVOp), DAG);
8330 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8331 // and update MaskVals with the new element order.
8332 if (BestHiQuad >= 0) {
8333 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8334 for (unsigned i = 4; i != 8; ++i) {
8335 int idx = MaskVals[i];
8338 } else if ((idx / 4) == BestHiQuad) {
8339 MaskV[i] = (idx & 3) + 4;
8343 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8346 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8348 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8350 getShufflePSHUFHWImmediate(SVOp), DAG);
8354 // In case BestHi & BestLo were both -1, which means each quadword has a word
8355 // from each of the four input quadwords, calculate the InOrder bitvector now
8356 // before falling through to the insert/extract cleanup.
8357 if (BestLoQuad == -1 && BestHiQuad == -1) {
8359 for (int i = 0; i != 8; ++i)
8360 if (MaskVals[i] < 0 || MaskVals[i] == i)
8364 // The other elements are put in the right place using pextrw and pinsrw.
8365 for (unsigned i = 0; i != 8; ++i) {
8368 int EltIdx = MaskVals[i];
8371 SDValue ExtOp = (EltIdx < 8) ?
8372 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8373 DAG.getIntPtrConstant(EltIdx)) :
8374 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8375 DAG.getIntPtrConstant(EltIdx - 8));
8376 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8377 DAG.getIntPtrConstant(i));
8382 /// \brief v16i16 shuffles
8384 /// FIXME: We only support generation of a single pshufb currently. We can
8385 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8386 /// well (e.g 2 x pshufb + 1 x por).
8388 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8389 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8390 SDValue V1 = SVOp->getOperand(0);
8391 SDValue V2 = SVOp->getOperand(1);
8394 if (V2.getOpcode() != ISD::UNDEF)
8397 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8398 return getPSHUFB(MaskVals, V1, dl, DAG);
8401 // v16i8 shuffles - Prefer shuffles in the following order:
8402 // 1. [ssse3] 1 x pshufb
8403 // 2. [ssse3] 2 x pshufb + 1 x por
8404 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8405 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8406 const X86Subtarget* Subtarget,
8407 SelectionDAG &DAG) {
8408 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8409 SDValue V1 = SVOp->getOperand(0);
8410 SDValue V2 = SVOp->getOperand(1);
8412 ArrayRef<int> MaskVals = SVOp->getMask();
8414 // Promote splats to a larger type which usually leads to more efficient code.
8415 // FIXME: Is this true if pshufb is available?
8416 if (SVOp->isSplat())
8417 return PromoteSplat(SVOp, DAG);
8419 // If we have SSSE3, case 1 is generated when all result bytes come from
8420 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8421 // present, fall back to case 3.
8423 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8424 if (Subtarget->hasSSSE3()) {
8425 SmallVector<SDValue,16> pshufbMask;
8427 // If all result elements are from one input vector, then only translate
8428 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8430 // Otherwise, we have elements from both input vectors, and must zero out
8431 // elements that come from V2 in the first mask, and V1 in the second mask
8432 // so that we can OR them together.
8433 for (unsigned i = 0; i != 16; ++i) {
8434 int EltIdx = MaskVals[i];
8435 if (EltIdx < 0 || EltIdx >= 16)
8437 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8439 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8440 DAG.getNode(ISD::BUILD_VECTOR, dl,
8441 MVT::v16i8, pshufbMask));
8443 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8444 // the 2nd operand if it's undefined or zero.
8445 if (V2.getOpcode() == ISD::UNDEF ||
8446 ISD::isBuildVectorAllZeros(V2.getNode()))
8449 // Calculate the shuffle mask for the second input, shuffle it, and
8450 // OR it with the first shuffled input.
8452 for (unsigned i = 0; i != 16; ++i) {
8453 int EltIdx = MaskVals[i];
8454 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8455 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8457 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8458 DAG.getNode(ISD::BUILD_VECTOR, dl,
8459 MVT::v16i8, pshufbMask));
8460 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8463 // No SSSE3 - Calculate in place words and then fix all out of place words
8464 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8465 // the 16 different words that comprise the two doublequadword input vectors.
8466 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8467 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8469 for (int i = 0; i != 8; ++i) {
8470 int Elt0 = MaskVals[i*2];
8471 int Elt1 = MaskVals[i*2+1];
8473 // This word of the result is all undef, skip it.
8474 if (Elt0 < 0 && Elt1 < 0)
8477 // This word of the result is already in the correct place, skip it.
8478 if ((Elt0 == i*2) && (Elt1 == i*2+1))
8481 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8482 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8485 // If Elt0 and Elt1 are defined, are consecutive, and can be load
8486 // using a single extract together, load it and store it.
8487 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
8488 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8489 DAG.getIntPtrConstant(Elt1 / 2));
8490 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8491 DAG.getIntPtrConstant(i));
8495 // If Elt1 is defined, extract it from the appropriate source. If the
8496 // source byte is not also odd, shift the extracted word left 8 bits
8497 // otherwise clear the bottom 8 bits if we need to do an or.
8499 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8500 DAG.getIntPtrConstant(Elt1 / 2));
8501 if ((Elt1 & 1) == 0)
8502 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
8504 TLI.getShiftAmountTy(InsElt.getValueType())));
8506 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
8507 DAG.getConstant(0xFF00, MVT::i16));
8509 // If Elt0 is defined, extract it from the appropriate source. If the
8510 // source byte is not also even, shift the extracted word right 8 bits. If
8511 // Elt1 was also defined, OR the extracted values together before
8512 // inserting them in the result.
8514 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
8515 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
8516 if ((Elt0 & 1) != 0)
8517 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8519 TLI.getShiftAmountTy(InsElt0.getValueType())));
8521 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
8522 DAG.getConstant(0x00FF, MVT::i16));
8523 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
8526 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8527 DAG.getIntPtrConstant(i));
8529 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8532 // v32i8 shuffles - Translate to VPSHUFB if possible.
8534 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
8535 const X86Subtarget *Subtarget,
8536 SelectionDAG &DAG) {
8537 MVT VT = SVOp->getSimpleValueType(0);
8538 SDValue V1 = SVOp->getOperand(0);
8539 SDValue V2 = SVOp->getOperand(1);
8541 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8543 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8544 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
8545 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8547 // VPSHUFB may be generated if
8548 // (1) one of input vector is undefined or zeroinitializer.
8549 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
8550 // And (2) the mask indexes don't cross the 128-bit lane.
8551 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
8552 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
8555 if (V1IsAllZero && !V2IsAllZero) {
8556 CommuteVectorShuffleMask(MaskVals, 32);
8559 return getPSHUFB(MaskVals, V1, dl, DAG);
8562 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8563 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8564 /// done when every pair / quad of shuffle mask elements point to elements in
8565 /// the right sequence. e.g.
8566 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
8568 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
8569 SelectionDAG &DAG) {
8570 MVT VT = SVOp->getSimpleValueType(0);
8572 unsigned NumElems = VT.getVectorNumElements();
8575 switch (VT.SimpleTy) {
8576 default: llvm_unreachable("Unexpected!");
8579 return SDValue(SVOp, 0);
8580 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
8581 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8582 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8583 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8584 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8585 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
8588 SmallVector<int, 8> MaskVec;
8589 for (unsigned i = 0; i != NumElems; i += Scale) {
8591 for (unsigned j = 0; j != Scale; ++j) {
8592 int EltIdx = SVOp->getMaskElt(i+j);
8596 StartIdx = (EltIdx / Scale);
8597 if (EltIdx != (int)(StartIdx*Scale + j))
8600 MaskVec.push_back(StartIdx);
8603 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
8604 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8605 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8608 /// getVZextMovL - Return a zero-extending vector move low node.
8610 static SDValue getVZextMovL(MVT VT, MVT OpVT,
8611 SDValue SrcOp, SelectionDAG &DAG,
8612 const X86Subtarget *Subtarget, SDLoc dl) {
8613 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
8614 LoadSDNode *LD = nullptr;
8615 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
8616 LD = dyn_cast<LoadSDNode>(SrcOp);
8618 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
8620 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
8621 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
8622 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8623 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
8624 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
8626 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8627 return DAG.getNode(ISD::BITCAST, dl, VT,
8628 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8629 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8637 return DAG.getNode(ISD::BITCAST, dl, VT,
8638 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8639 DAG.getNode(ISD::BITCAST, dl,
8643 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
8644 /// which could not be matched by any known target speficic shuffle
8646 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8648 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
8649 if (NewOp.getNode())
8652 MVT VT = SVOp->getSimpleValueType(0);
8654 unsigned NumElems = VT.getVectorNumElements();
8655 unsigned NumLaneElems = NumElems / 2;
8658 MVT EltVT = VT.getVectorElementType();
8659 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
8662 SmallVector<int, 16> Mask;
8663 for (unsigned l = 0; l < 2; ++l) {
8664 // Build a shuffle mask for the output, discovering on the fly which
8665 // input vectors to use as shuffle operands (recorded in InputUsed).
8666 // If building a suitable shuffle vector proves too hard, then bail
8667 // out with UseBuildVector set.
8668 bool UseBuildVector = false;
8669 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
8670 unsigned LaneStart = l * NumLaneElems;
8671 for (unsigned i = 0; i != NumLaneElems; ++i) {
8672 // The mask element. This indexes into the input.
8673 int Idx = SVOp->getMaskElt(i+LaneStart);
8675 // the mask element does not index into any input vector.
8680 // The input vector this mask element indexes into.
8681 int Input = Idx / NumLaneElems;
8683 // Turn the index into an offset from the start of the input vector.
8684 Idx -= Input * NumLaneElems;
8686 // Find or create a shuffle vector operand to hold this input.
8688 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
8689 if (InputUsed[OpNo] == Input)
8690 // This input vector is already an operand.
8692 if (InputUsed[OpNo] < 0) {
8693 // Create a new operand for this input vector.
8694 InputUsed[OpNo] = Input;
8699 if (OpNo >= array_lengthof(InputUsed)) {
8700 // More than two input vectors used! Give up on trying to create a
8701 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
8702 UseBuildVector = true;
8706 // Add the mask index for the new shuffle vector.
8707 Mask.push_back(Idx + OpNo * NumLaneElems);
8710 if (UseBuildVector) {
8711 SmallVector<SDValue, 16> SVOps;
8712 for (unsigned i = 0; i != NumLaneElems; ++i) {
8713 // The mask element. This indexes into the input.
8714 int Idx = SVOp->getMaskElt(i+LaneStart);
8716 SVOps.push_back(DAG.getUNDEF(EltVT));
8720 // The input vector this mask element indexes into.
8721 int Input = Idx / NumElems;
8723 // Turn the index into an offset from the start of the input vector.
8724 Idx -= Input * NumElems;
8726 // Extract the vector element by hand.
8727 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
8728 SVOp->getOperand(Input),
8729 DAG.getIntPtrConstant(Idx)));
8732 // Construct the output using a BUILD_VECTOR.
8733 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
8734 } else if (InputUsed[0] < 0) {
8735 // No input vectors were used! The result is undefined.
8736 Output[l] = DAG.getUNDEF(NVT);
8738 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
8739 (InputUsed[0] % 2) * NumLaneElems,
8741 // If only one input was used, use an undefined vector for the other.
8742 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
8743 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
8744 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
8745 // At least one input vector was used. Create a new shuffle vector.
8746 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
8752 // Concatenate the result back
8753 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
8756 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
8757 /// 4 elements, and match them with several different shuffle types.
8759 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8760 SDValue V1 = SVOp->getOperand(0);
8761 SDValue V2 = SVOp->getOperand(1);
8763 MVT VT = SVOp->getSimpleValueType(0);
8765 assert(VT.is128BitVector() && "Unsupported vector size");
8767 std::pair<int, int> Locs[4];
8768 int Mask1[] = { -1, -1, -1, -1 };
8769 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
8773 for (unsigned i = 0; i != 4; ++i) {
8774 int Idx = PermMask[i];
8776 Locs[i] = std::make_pair(-1, -1);
8778 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
8780 Locs[i] = std::make_pair(0, NumLo);
8784 Locs[i] = std::make_pair(1, NumHi);
8786 Mask1[2+NumHi] = Idx;
8792 if (NumLo <= 2 && NumHi <= 2) {
8793 // If no more than two elements come from either vector. This can be
8794 // implemented with two shuffles. First shuffle gather the elements.
8795 // The second shuffle, which takes the first shuffle as both of its
8796 // vector operands, put the elements into the right order.
8797 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8799 int Mask2[] = { -1, -1, -1, -1 };
8801 for (unsigned i = 0; i != 4; ++i)
8802 if (Locs[i].first != -1) {
8803 unsigned Idx = (i < 2) ? 0 : 4;
8804 Idx += Locs[i].first * 2 + Locs[i].second;
8808 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
8811 if (NumLo == 3 || NumHi == 3) {
8812 // Otherwise, we must have three elements from one vector, call it X, and
8813 // one element from the other, call it Y. First, use a shufps to build an
8814 // intermediate vector with the one element from Y and the element from X
8815 // that will be in the same half in the final destination (the indexes don't
8816 // matter). Then, use a shufps to build the final vector, taking the half
8817 // containing the element from Y from the intermediate, and the other half
8820 // Normalize it so the 3 elements come from V1.
8821 CommuteVectorShuffleMask(PermMask, 4);
8825 // Find the element from V2.
8827 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
8828 int Val = PermMask[HiIndex];
8835 Mask1[0] = PermMask[HiIndex];
8837 Mask1[2] = PermMask[HiIndex^1];
8839 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8842 Mask1[0] = PermMask[0];
8843 Mask1[1] = PermMask[1];
8844 Mask1[2] = HiIndex & 1 ? 6 : 4;
8845 Mask1[3] = HiIndex & 1 ? 4 : 6;
8846 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8849 Mask1[0] = HiIndex & 1 ? 2 : 0;
8850 Mask1[1] = HiIndex & 1 ? 0 : 2;
8851 Mask1[2] = PermMask[2];
8852 Mask1[3] = PermMask[3];
8857 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
8860 // Break it into (shuffle shuffle_hi, shuffle_lo).
8861 int LoMask[] = { -1, -1, -1, -1 };
8862 int HiMask[] = { -1, -1, -1, -1 };
8864 int *MaskPtr = LoMask;
8865 unsigned MaskIdx = 0;
8868 for (unsigned i = 0; i != 4; ++i) {
8875 int Idx = PermMask[i];
8877 Locs[i] = std::make_pair(-1, -1);
8878 } else if (Idx < 4) {
8879 Locs[i] = std::make_pair(MaskIdx, LoIdx);
8880 MaskPtr[LoIdx] = Idx;
8883 Locs[i] = std::make_pair(MaskIdx, HiIdx);
8884 MaskPtr[HiIdx] = Idx;
8889 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
8890 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
8891 int MaskOps[] = { -1, -1, -1, -1 };
8892 for (unsigned i = 0; i != 4; ++i)
8893 if (Locs[i].first != -1)
8894 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
8895 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
8898 static bool MayFoldVectorLoad(SDValue V) {
8899 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
8900 V = V.getOperand(0);
8902 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
8903 V = V.getOperand(0);
8904 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
8905 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
8906 // BUILD_VECTOR (load), undef
8907 V = V.getOperand(0);
8909 return MayFoldLoad(V);
8913 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
8914 MVT VT = Op.getSimpleValueType();
8916 // Canonizalize to v2f64.
8917 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
8918 return DAG.getNode(ISD::BITCAST, dl, VT,
8919 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
8924 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
8926 SDValue V1 = Op.getOperand(0);
8927 SDValue V2 = Op.getOperand(1);
8928 MVT VT = Op.getSimpleValueType();
8930 assert(VT != MVT::v2i64 && "unsupported shuffle type");
8932 if (HasSSE2 && VT == MVT::v2f64)
8933 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
8935 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
8936 return DAG.getNode(ISD::BITCAST, dl, VT,
8937 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
8938 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
8939 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
8943 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
8944 SDValue V1 = Op.getOperand(0);
8945 SDValue V2 = Op.getOperand(1);
8946 MVT VT = Op.getSimpleValueType();
8948 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
8949 "unsupported shuffle type");
8951 if (V2.getOpcode() == ISD::UNDEF)
8955 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
8959 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
8960 SDValue V1 = Op.getOperand(0);
8961 SDValue V2 = Op.getOperand(1);
8962 MVT VT = Op.getSimpleValueType();
8963 unsigned NumElems = VT.getVectorNumElements();
8965 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
8966 // operand of these instructions is only memory, so check if there's a
8967 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
8969 bool CanFoldLoad = false;
8971 // Trivial case, when V2 comes from a load.
8972 if (MayFoldVectorLoad(V2))
8975 // When V1 is a load, it can be folded later into a store in isel, example:
8976 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
8978 // (MOVLPSmr addr:$src1, VR128:$src2)
8979 // So, recognize this potential and also use MOVLPS or MOVLPD
8980 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
8983 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8985 if (HasSSE2 && NumElems == 2)
8986 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
8989 // If we don't care about the second element, proceed to use movss.
8990 if (SVOp->getMaskElt(1) != -1)
8991 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
8994 // movl and movlp will both match v2i64, but v2i64 is never matched by
8995 // movl earlier because we make it strict to avoid messing with the movlp load
8996 // folding logic (see the code above getMOVLP call). Match it here then,
8997 // this is horrible, but will stay like this until we move all shuffle
8998 // matching to x86 specific nodes. Note that for the 1st condition all
8999 // types are matched with movsd.
9001 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9002 // as to remove this logic from here, as much as possible
9003 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9004 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9005 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9008 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9010 // Invert the operand order and use SHUFPS to match it.
9011 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9012 getShuffleSHUFImmediate(SVOp), DAG);
9015 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9016 SelectionDAG &DAG) {
9018 MVT VT = Load->getSimpleValueType(0);
9019 MVT EVT = VT.getVectorElementType();
9020 SDValue Addr = Load->getOperand(1);
9021 SDValue NewAddr = DAG.getNode(
9022 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9023 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9026 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9027 DAG.getMachineFunction().getMachineMemOperand(
9028 Load->getMemOperand(), 0, EVT.getStoreSize()));
9032 // It is only safe to call this function if isINSERTPSMask is true for
9033 // this shufflevector mask.
9034 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9035 SelectionDAG &DAG) {
9036 // Generate an insertps instruction when inserting an f32 from memory onto a
9037 // v4f32 or when copying a member from one v4f32 to another.
9038 // We also use it for transferring i32 from one register to another,
9039 // since it simply copies the same bits.
9040 // If we're transferring an i32 from memory to a specific element in a
9041 // register, we output a generic DAG that will match the PINSRD
9043 MVT VT = SVOp->getSimpleValueType(0);
9044 MVT EVT = VT.getVectorElementType();
9045 SDValue V1 = SVOp->getOperand(0);
9046 SDValue V2 = SVOp->getOperand(1);
9047 auto Mask = SVOp->getMask();
9048 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9049 "unsupported vector type for insertps/pinsrd");
9051 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9052 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9053 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9061 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9064 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9065 "More than one element from V1 and from V2, or no elements from one "
9066 "of the vectors. This case should not have returned true from "
9071 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9074 unsigned SrcIndex = Mask[DestIndex] % 4;
9075 if (MayFoldLoad(From)) {
9076 // Trivial case, when From comes from a load and is only used by the
9077 // shuffle. Make it use insertps from the vector that we need from that
9080 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9081 if (!NewLoad.getNode())
9084 if (EVT == MVT::f32) {
9085 // Create this as a scalar to vector to match the instruction pattern.
9086 SDValue LoadScalarToVector =
9087 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9088 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9089 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9091 } else { // EVT == MVT::i32
9092 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9093 // instruction, to match the PINSRD instruction, which loads an i32 to a
9094 // certain vector element.
9095 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9096 DAG.getConstant(DestIndex, MVT::i32));
9100 // Vector-element-to-vector
9101 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9102 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9105 // Reduce a vector shuffle to zext.
9106 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9107 SelectionDAG &DAG) {
9108 // PMOVZX is only available from SSE41.
9109 if (!Subtarget->hasSSE41())
9112 MVT VT = Op.getSimpleValueType();
9114 // Only AVX2 support 256-bit vector integer extending.
9115 if (!Subtarget->hasInt256() && VT.is256BitVector())
9118 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9120 SDValue V1 = Op.getOperand(0);
9121 SDValue V2 = Op.getOperand(1);
9122 unsigned NumElems = VT.getVectorNumElements();
9124 // Extending is an unary operation and the element type of the source vector
9125 // won't be equal to or larger than i64.
9126 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9127 VT.getVectorElementType() == MVT::i64)
9130 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9131 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9132 while ((1U << Shift) < NumElems) {
9133 if (SVOp->getMaskElt(1U << Shift) == 1)
9136 // The maximal ratio is 8, i.e. from i8 to i64.
9141 // Check the shuffle mask.
9142 unsigned Mask = (1U << Shift) - 1;
9143 for (unsigned i = 0; i != NumElems; ++i) {
9144 int EltIdx = SVOp->getMaskElt(i);
9145 if ((i & Mask) != 0 && EltIdx != -1)
9147 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9151 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9152 MVT NeVT = MVT::getIntegerVT(NBits);
9153 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9155 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9158 // Simplify the operand as it's prepared to be fed into shuffle.
9159 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9160 if (V1.getOpcode() == ISD::BITCAST &&
9161 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9162 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9163 V1.getOperand(0).getOperand(0)
9164 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9165 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9166 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9167 ConstantSDNode *CIdx =
9168 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9169 // If it's foldable, i.e. normal load with single use, we will let code
9170 // selection to fold it. Otherwise, we will short the conversion sequence.
9171 if (CIdx && CIdx->getZExtValue() == 0 &&
9172 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9173 MVT FullVT = V.getSimpleValueType();
9174 MVT V1VT = V1.getSimpleValueType();
9175 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9176 // The "ext_vec_elt" node is wider than the result node.
9177 // In this case we should extract subvector from V.
9178 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9179 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9180 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9181 FullVT.getVectorNumElements()/Ratio);
9182 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9183 DAG.getIntPtrConstant(0));
9185 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9189 return DAG.getNode(ISD::BITCAST, DL, VT,
9190 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9193 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9194 SelectionDAG &DAG) {
9195 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9196 MVT VT = Op.getSimpleValueType();
9198 SDValue V1 = Op.getOperand(0);
9199 SDValue V2 = Op.getOperand(1);
9201 if (isZeroShuffle(SVOp))
9202 return getZeroVector(VT, Subtarget, DAG, dl);
9204 // Handle splat operations
9205 if (SVOp->isSplat()) {
9206 // Use vbroadcast whenever the splat comes from a foldable load
9207 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9208 if (Broadcast.getNode())
9212 // Check integer expanding shuffles.
9213 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9214 if (NewOp.getNode())
9217 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9219 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9221 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9222 if (NewOp.getNode())
9223 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9224 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9225 // FIXME: Figure out a cleaner way to do this.
9226 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9227 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9228 if (NewOp.getNode()) {
9229 MVT NewVT = NewOp.getSimpleValueType();
9230 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9231 NewVT, true, false))
9232 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9235 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9236 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9237 if (NewOp.getNode()) {
9238 MVT NewVT = NewOp.getSimpleValueType();
9239 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9240 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9249 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9250 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9251 SDValue V1 = Op.getOperand(0);
9252 SDValue V2 = Op.getOperand(1);
9253 MVT VT = Op.getSimpleValueType();
9255 unsigned NumElems = VT.getVectorNumElements();
9256 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9257 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9258 bool V1IsSplat = false;
9259 bool V2IsSplat = false;
9260 bool HasSSE2 = Subtarget->hasSSE2();
9261 bool HasFp256 = Subtarget->hasFp256();
9262 bool HasInt256 = Subtarget->hasInt256();
9263 MachineFunction &MF = DAG.getMachineFunction();
9264 bool OptForSize = MF.getFunction()->getAttributes().
9265 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9267 // Check if we should use the experimental vector shuffle lowering. If so,
9268 // delegate completely to that code path.
9269 if (ExperimentalVectorShuffleLowering)
9270 return lowerVectorShuffle(Op, Subtarget, DAG);
9272 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9274 if (V1IsUndef && V2IsUndef)
9275 return DAG.getUNDEF(VT);
9277 // When we create a shuffle node we put the UNDEF node to second operand,
9278 // but in some cases the first operand may be transformed to UNDEF.
9279 // In this case we should just commute the node.
9281 return CommuteVectorShuffle(SVOp, DAG);
9283 // Vector shuffle lowering takes 3 steps:
9285 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9286 // narrowing and commutation of operands should be handled.
9287 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9289 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9290 // so the shuffle can be broken into other shuffles and the legalizer can
9291 // try the lowering again.
9293 // The general idea is that no vector_shuffle operation should be left to
9294 // be matched during isel, all of them must be converted to a target specific
9297 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9298 // narrowing and commutation of operands should be handled. The actual code
9299 // doesn't include all of those, work in progress...
9300 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9301 if (NewOp.getNode())
9304 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9306 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9307 // unpckh_undef). Only use pshufd if speed is more important than size.
9308 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9309 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9310 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9311 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9313 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9314 V2IsUndef && MayFoldVectorLoad(V1))
9315 return getMOVDDup(Op, dl, V1, DAG);
9317 if (isMOVHLPS_v_undef_Mask(M, VT))
9318 return getMOVHighToLow(Op, dl, DAG);
9320 // Use to match splats
9321 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9322 (VT == MVT::v2f64 || VT == MVT::v2i64))
9323 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9325 if (isPSHUFDMask(M, VT)) {
9326 // The actual implementation will match the mask in the if above and then
9327 // during isel it can match several different instructions, not only pshufd
9328 // as its name says, sad but true, emulate the behavior for now...
9329 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9330 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9332 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9334 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9335 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9337 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9338 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9341 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9345 if (isPALIGNRMask(M, VT, Subtarget))
9346 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9347 getShufflePALIGNRImmediate(SVOp),
9350 // Check if this can be converted into a logical shift.
9351 bool isLeft = false;
9354 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9355 if (isShift && ShVal.hasOneUse()) {
9356 // If the shifted value has multiple uses, it may be cheaper to use
9357 // v_set0 + movlhps or movhlps, etc.
9358 MVT EltVT = VT.getVectorElementType();
9359 ShAmt *= EltVT.getSizeInBits();
9360 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9363 if (isMOVLMask(M, VT)) {
9364 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9365 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9366 if (!isMOVLPMask(M, VT)) {
9367 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9368 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9370 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9371 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9375 // FIXME: fold these into legal mask.
9376 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9377 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9379 if (isMOVHLPSMask(M, VT))
9380 return getMOVHighToLow(Op, dl, DAG);
9382 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9383 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9385 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9386 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9388 if (isMOVLPMask(M, VT))
9389 return getMOVLP(Op, dl, DAG, HasSSE2);
9391 if (ShouldXformToMOVHLPS(M, VT) ||
9392 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9393 return CommuteVectorShuffle(SVOp, DAG);
9396 // No better options. Use a vshldq / vsrldq.
9397 MVT EltVT = VT.getVectorElementType();
9398 ShAmt *= EltVT.getSizeInBits();
9399 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9402 bool Commuted = false;
9403 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9404 // 1,1,1,1 -> v8i16 though.
9405 BitVector UndefElements;
9406 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9407 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9409 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9410 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9413 // Canonicalize the splat or undef, if present, to be on the RHS.
9414 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9415 CommuteVectorShuffleMask(M, NumElems);
9417 std::swap(V1IsSplat, V2IsSplat);
9421 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9422 // Shuffling low element of v1 into undef, just return v1.
9425 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9426 // the instruction selector will not match, so get a canonical MOVL with
9427 // swapped operands to undo the commute.
9428 return getMOVL(DAG, dl, VT, V2, V1);
9431 if (isUNPCKLMask(M, VT, HasInt256))
9432 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9434 if (isUNPCKHMask(M, VT, HasInt256))
9435 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9438 // Normalize mask so all entries that point to V2 points to its first
9439 // element then try to match unpck{h|l} again. If match, return a
9440 // new vector_shuffle with the corrected mask.p
9441 SmallVector<int, 8> NewMask(M.begin(), M.end());
9442 NormalizeMask(NewMask, NumElems);
9443 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9444 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9445 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9446 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9450 // Commute is back and try unpck* again.
9451 // FIXME: this seems wrong.
9452 CommuteVectorShuffleMask(M, NumElems);
9454 std::swap(V1IsSplat, V2IsSplat);
9456 if (isUNPCKLMask(M, VT, HasInt256))
9457 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9459 if (isUNPCKHMask(M, VT, HasInt256))
9460 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9463 // Normalize the node to match x86 shuffle ops if needed
9464 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9465 return CommuteVectorShuffle(SVOp, DAG);
9467 // The checks below are all present in isShuffleMaskLegal, but they are
9468 // inlined here right now to enable us to directly emit target specific
9469 // nodes, and remove one by one until they don't return Op anymore.
9471 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9472 SVOp->getSplatIndex() == 0 && V2IsUndef) {
9473 if (VT == MVT::v2f64 || VT == MVT::v2i64)
9474 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9477 if (isPSHUFHWMask(M, VT, HasInt256))
9478 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9479 getShufflePSHUFHWImmediate(SVOp),
9482 if (isPSHUFLWMask(M, VT, HasInt256))
9483 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9484 getShufflePSHUFLWImmediate(SVOp),
9488 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9490 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9492 if (isSHUFPMask(M, VT))
9493 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9494 getShuffleSHUFImmediate(SVOp), DAG);
9496 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9497 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9498 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9499 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9501 //===--------------------------------------------------------------------===//
9502 // Generate target specific nodes for 128 or 256-bit shuffles only
9503 // supported in the AVX instruction set.
9506 // Handle VMOVDDUPY permutations
9507 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9508 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9510 // Handle VPERMILPS/D* permutations
9511 if (isVPERMILPMask(M, VT)) {
9512 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9513 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9514 getShuffleSHUFImmediate(SVOp), DAG);
9515 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9516 getShuffleSHUFImmediate(SVOp), DAG);
9520 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9521 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9522 Idx*(NumElems/2), DAG, dl);
9524 // Handle VPERM2F128/VPERM2I128 permutations
9525 if (isVPERM2X128Mask(M, VT, HasFp256))
9526 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9527 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9529 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9530 return getINSERTPS(SVOp, dl, DAG);
9533 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9534 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9536 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9537 VT.is512BitVector()) {
9538 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9539 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9540 SmallVector<SDValue, 16> permclMask;
9541 for (unsigned i = 0; i != NumElems; ++i) {
9542 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9545 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9547 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9548 return DAG.getNode(X86ISD::VPERMV, dl, VT,
9549 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9550 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9551 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9554 //===--------------------------------------------------------------------===//
9555 // Since no target specific shuffle was selected for this generic one,
9556 // lower it into other known shuffles. FIXME: this isn't true yet, but
9557 // this is the plan.
9560 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9561 if (VT == MVT::v8i16) {
9562 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9563 if (NewOp.getNode())
9567 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9568 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9569 if (NewOp.getNode())
9573 if (VT == MVT::v16i8) {
9574 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9575 if (NewOp.getNode())
9579 if (VT == MVT::v32i8) {
9580 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9581 if (NewOp.getNode())
9585 // Handle all 128-bit wide vectors with 4 elements, and match them with
9586 // several different shuffle types.
9587 if (NumElems == 4 && VT.is128BitVector())
9588 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9590 // Handle general 256-bit shuffles
9591 if (VT.is256BitVector())
9592 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9597 // This function assumes its argument is a BUILD_VECTOR of constants or
9598 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
9600 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
9601 unsigned &MaskValue) {
9603 unsigned NumElems = BuildVector->getNumOperands();
9604 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9605 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9606 unsigned NumElemsInLane = NumElems / NumLanes;
9608 // Blend for v16i16 should be symetric for the both lanes.
9609 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9610 SDValue EltCond = BuildVector->getOperand(i);
9611 SDValue SndLaneEltCond =
9612 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
9614 int Lane1Cond = -1, Lane2Cond = -1;
9615 if (isa<ConstantSDNode>(EltCond))
9616 Lane1Cond = !isZero(EltCond);
9617 if (isa<ConstantSDNode>(SndLaneEltCond))
9618 Lane2Cond = !isZero(SndLaneEltCond);
9620 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
9621 // Lane1Cond != 0, means we want the first argument.
9622 // Lane1Cond == 0, means we want the second argument.
9623 // The encoding of this argument is 0 for the first argument, 1
9624 // for the second. Therefore, invert the condition.
9625 MaskValue |= !Lane1Cond << i;
9626 else if (Lane1Cond < 0)
9627 MaskValue |= !Lane2Cond << i;
9634 // Try to lower a vselect node into a simple blend instruction.
9635 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
9636 SelectionDAG &DAG) {
9637 SDValue Cond = Op.getOperand(0);
9638 SDValue LHS = Op.getOperand(1);
9639 SDValue RHS = Op.getOperand(2);
9641 MVT VT = Op.getSimpleValueType();
9642 MVT EltVT = VT.getVectorElementType();
9643 unsigned NumElems = VT.getVectorNumElements();
9645 // There is no blend with immediate in AVX-512.
9646 if (VT.is512BitVector())
9649 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
9651 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
9654 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
9657 // Check the mask for BLEND and build the value.
9658 unsigned MaskValue = 0;
9659 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
9662 // Convert i32 vectors to floating point if it is not AVX2.
9663 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9665 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9666 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9668 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
9669 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
9672 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
9673 DAG.getConstant(MaskValue, MVT::i32));
9674 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9677 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
9678 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
9679 if (BlendOp.getNode())
9682 // Some types for vselect were previously set to Expand, not Legal or
9683 // Custom. Return an empty SDValue so we fall-through to Expand, after
9684 // the Custom lowering phase.
9685 MVT VT = Op.getSimpleValueType();
9686 switch (VT.SimpleTy) {
9694 // We couldn't create a "Blend with immediate" node.
9695 // This node should still be legal, but we'll have to emit a blendv*
9700 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9701 MVT VT = Op.getSimpleValueType();
9704 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
9707 if (VT.getSizeInBits() == 8) {
9708 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
9709 Op.getOperand(0), Op.getOperand(1));
9710 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9711 DAG.getValueType(VT));
9712 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9715 if (VT.getSizeInBits() == 16) {
9716 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9717 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
9719 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9720 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9721 DAG.getNode(ISD::BITCAST, dl,
9725 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
9726 Op.getOperand(0), Op.getOperand(1));
9727 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9728 DAG.getValueType(VT));
9729 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9732 if (VT == MVT::f32) {
9733 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
9734 // the result back to FR32 register. It's only worth matching if the
9735 // result has a single use which is a store or a bitcast to i32. And in
9736 // the case of a store, it's not worth it if the index is a constant 0,
9737 // because a MOVSSmr can be used instead, which is smaller and faster.
9738 if (!Op.hasOneUse())
9740 SDNode *User = *Op.getNode()->use_begin();
9741 if ((User->getOpcode() != ISD::STORE ||
9742 (isa<ConstantSDNode>(Op.getOperand(1)) &&
9743 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
9744 (User->getOpcode() != ISD::BITCAST ||
9745 User->getValueType(0) != MVT::i32))
9747 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9748 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
9751 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
9754 if (VT == MVT::i32 || VT == MVT::i64) {
9755 // ExtractPS/pextrq works with constant index.
9756 if (isa<ConstantSDNode>(Op.getOperand(1)))
9762 /// Extract one bit from mask vector, like v16i1 or v8i1.
9763 /// AVX-512 feature.
9765 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
9766 SDValue Vec = Op.getOperand(0);
9768 MVT VecVT = Vec.getSimpleValueType();
9769 SDValue Idx = Op.getOperand(1);
9770 MVT EltVT = Op.getSimpleValueType();
9772 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
9774 // variable index can't be handled in mask registers,
9775 // extend vector to VR512
9776 if (!isa<ConstantSDNode>(Idx)) {
9777 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9778 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
9779 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
9780 ExtVT.getVectorElementType(), Ext, Idx);
9781 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
9784 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9785 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9786 unsigned MaxSift = rc->getSize()*8 - 1;
9787 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
9788 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9789 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
9790 DAG.getConstant(MaxSift, MVT::i8));
9791 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
9792 DAG.getIntPtrConstant(0));
9796 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
9797 SelectionDAG &DAG) const {
9799 SDValue Vec = Op.getOperand(0);
9800 MVT VecVT = Vec.getSimpleValueType();
9801 SDValue Idx = Op.getOperand(1);
9803 if (Op.getSimpleValueType() == MVT::i1)
9804 return ExtractBitFromMaskVector(Op, DAG);
9806 if (!isa<ConstantSDNode>(Idx)) {
9807 if (VecVT.is512BitVector() ||
9808 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
9809 VecVT.getVectorElementType().getSizeInBits() == 32)) {
9812 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
9813 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
9814 MaskEltVT.getSizeInBits());
9816 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
9817 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
9818 getZeroVector(MaskVT, Subtarget, DAG, dl),
9819 Idx, DAG.getConstant(0, getPointerTy()));
9820 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
9821 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
9822 Perm, DAG.getConstant(0, getPointerTy()));
9827 // If this is a 256-bit vector result, first extract the 128-bit vector and
9828 // then extract the element from the 128-bit vector.
9829 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
9831 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9832 // Get the 128-bit vector.
9833 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
9834 MVT EltVT = VecVT.getVectorElementType();
9836 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
9838 //if (IdxVal >= NumElems/2)
9839 // IdxVal -= NumElems/2;
9840 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
9841 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
9842 DAG.getConstant(IdxVal, MVT::i32));
9845 assert(VecVT.is128BitVector() && "Unexpected vector length");
9847 if (Subtarget->hasSSE41()) {
9848 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
9853 MVT VT = Op.getSimpleValueType();
9854 // TODO: handle v16i8.
9855 if (VT.getSizeInBits() == 16) {
9856 SDValue Vec = Op.getOperand(0);
9857 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9859 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9860 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9861 DAG.getNode(ISD::BITCAST, dl,
9864 // Transform it so it match pextrw which produces a 32-bit result.
9865 MVT EltVT = MVT::i32;
9866 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
9867 Op.getOperand(0), Op.getOperand(1));
9868 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
9869 DAG.getValueType(VT));
9870 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9873 if (VT.getSizeInBits() == 32) {
9874 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9878 // SHUFPS the element to the lowest double word, then movss.
9879 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
9880 MVT VVT = Op.getOperand(0).getSimpleValueType();
9881 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9882 DAG.getUNDEF(VVT), Mask);
9883 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9884 DAG.getIntPtrConstant(0));
9887 if (VT.getSizeInBits() == 64) {
9888 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
9889 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
9890 // to match extract_elt for f64.
9891 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9895 // UNPCKHPD the element to the lowest double word, then movsd.
9896 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
9897 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
9898 int Mask[2] = { 1, -1 };
9899 MVT VVT = Op.getOperand(0).getSimpleValueType();
9900 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9901 DAG.getUNDEF(VVT), Mask);
9902 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9903 DAG.getIntPtrConstant(0));
9909 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9910 MVT VT = Op.getSimpleValueType();
9911 MVT EltVT = VT.getVectorElementType();
9914 SDValue N0 = Op.getOperand(0);
9915 SDValue N1 = Op.getOperand(1);
9916 SDValue N2 = Op.getOperand(2);
9918 if (!VT.is128BitVector())
9921 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
9922 isa<ConstantSDNode>(N2)) {
9924 if (VT == MVT::v8i16)
9925 Opc = X86ISD::PINSRW;
9926 else if (VT == MVT::v16i8)
9927 Opc = X86ISD::PINSRB;
9929 Opc = X86ISD::PINSRB;
9931 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
9933 if (N1.getValueType() != MVT::i32)
9934 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
9935 if (N2.getValueType() != MVT::i32)
9936 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
9937 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
9940 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
9941 // Bits [7:6] of the constant are the source select. This will always be
9942 // zero here. The DAG Combiner may combine an extract_elt index into these
9943 // bits. For example (insert (extract, 3), 2) could be matched by putting
9944 // the '3' into bits [7:6] of X86ISD::INSERTPS.
9945 // Bits [5:4] of the constant are the destination select. This is the
9946 // value of the incoming immediate.
9947 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
9948 // combine either bitwise AND or insert of float 0.0 to set these bits.
9949 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
9950 // Create this as a scalar to vector..
9951 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
9952 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
9955 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
9956 // PINSR* works with constant index.
9962 /// Insert one bit to mask vector, like v16i1 or v8i1.
9963 /// AVX-512 feature.
9965 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
9967 SDValue Vec = Op.getOperand(0);
9968 SDValue Elt = Op.getOperand(1);
9969 SDValue Idx = Op.getOperand(2);
9970 MVT VecVT = Vec.getSimpleValueType();
9972 if (!isa<ConstantSDNode>(Idx)) {
9973 // Non constant index. Extend source and destination,
9974 // insert element and then truncate the result.
9975 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9976 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
9977 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
9978 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
9979 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
9980 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
9983 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9984 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
9985 if (Vec.getOpcode() == ISD::UNDEF)
9986 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9987 DAG.getConstant(IdxVal, MVT::i8));
9988 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9989 unsigned MaxSift = rc->getSize()*8 - 1;
9990 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9991 DAG.getConstant(MaxSift, MVT::i8));
9992 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
9993 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9994 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
9997 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
9998 MVT VT = Op.getSimpleValueType();
9999 MVT EltVT = VT.getVectorElementType();
10001 if (EltVT == MVT::i1)
10002 return InsertBitToMaskVector(Op, DAG);
10005 SDValue N0 = Op.getOperand(0);
10006 SDValue N1 = Op.getOperand(1);
10007 SDValue N2 = Op.getOperand(2);
10009 // If this is a 256-bit vector result, first extract the 128-bit vector,
10010 // insert the element into the extracted half and then place it back.
10011 if (VT.is256BitVector() || VT.is512BitVector()) {
10012 if (!isa<ConstantSDNode>(N2))
10015 // Get the desired 128-bit vector half.
10016 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10017 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10019 // Insert the element into the desired half.
10020 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10021 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10023 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10024 DAG.getConstant(IdxIn128, MVT::i32));
10026 // Insert the changed part back to the 256-bit vector
10027 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10030 if (Subtarget->hasSSE41())
10031 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10033 if (EltVT == MVT::i8)
10036 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10037 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10038 // as its second argument.
10039 if (N1.getValueType() != MVT::i32)
10040 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10041 if (N2.getValueType() != MVT::i32)
10042 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10043 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10048 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10050 MVT OpVT = Op.getSimpleValueType();
10052 // If this is a 256-bit vector result, first insert into a 128-bit
10053 // vector and then insert into the 256-bit vector.
10054 if (!OpVT.is128BitVector()) {
10055 // Insert into a 128-bit vector.
10056 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10057 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10058 OpVT.getVectorNumElements() / SizeFactor);
10060 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10062 // Insert the 128-bit vector.
10063 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10066 if (OpVT == MVT::v1i64 &&
10067 Op.getOperand(0).getValueType() == MVT::i64)
10068 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10070 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10071 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10072 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10073 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10076 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10077 // a simple subregister reference or explicit instructions to grab
10078 // upper bits of a vector.
10079 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10080 SelectionDAG &DAG) {
10082 SDValue In = Op.getOperand(0);
10083 SDValue Idx = Op.getOperand(1);
10084 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10085 MVT ResVT = Op.getSimpleValueType();
10086 MVT InVT = In.getSimpleValueType();
10088 if (Subtarget->hasFp256()) {
10089 if (ResVT.is128BitVector() &&
10090 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10091 isa<ConstantSDNode>(Idx)) {
10092 return Extract128BitVector(In, IdxVal, DAG, dl);
10094 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10095 isa<ConstantSDNode>(Idx)) {
10096 return Extract256BitVector(In, IdxVal, DAG, dl);
10102 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10103 // simple superregister reference or explicit instructions to insert
10104 // the upper bits of a vector.
10105 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10106 SelectionDAG &DAG) {
10107 if (Subtarget->hasFp256()) {
10108 SDLoc dl(Op.getNode());
10109 SDValue Vec = Op.getNode()->getOperand(0);
10110 SDValue SubVec = Op.getNode()->getOperand(1);
10111 SDValue Idx = Op.getNode()->getOperand(2);
10113 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10114 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10115 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10116 isa<ConstantSDNode>(Idx)) {
10117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10118 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10121 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10122 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10123 isa<ConstantSDNode>(Idx)) {
10124 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10125 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10131 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10132 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10133 // one of the above mentioned nodes. It has to be wrapped because otherwise
10134 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10135 // be used to form addressing mode. These wrapped nodes will be selected
10138 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10139 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10141 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10142 // global base reg.
10143 unsigned char OpFlag = 0;
10144 unsigned WrapperKind = X86ISD::Wrapper;
10145 CodeModel::Model M = DAG.getTarget().getCodeModel();
10147 if (Subtarget->isPICStyleRIPRel() &&
10148 (M == CodeModel::Small || M == CodeModel::Kernel))
10149 WrapperKind = X86ISD::WrapperRIP;
10150 else if (Subtarget->isPICStyleGOT())
10151 OpFlag = X86II::MO_GOTOFF;
10152 else if (Subtarget->isPICStyleStubPIC())
10153 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10155 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10156 CP->getAlignment(),
10157 CP->getOffset(), OpFlag);
10159 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10160 // With PIC, the address is actually $g + Offset.
10162 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10163 DAG.getNode(X86ISD::GlobalBaseReg,
10164 SDLoc(), getPointerTy()),
10171 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10172 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10174 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10175 // global base reg.
10176 unsigned char OpFlag = 0;
10177 unsigned WrapperKind = X86ISD::Wrapper;
10178 CodeModel::Model M = DAG.getTarget().getCodeModel();
10180 if (Subtarget->isPICStyleRIPRel() &&
10181 (M == CodeModel::Small || M == CodeModel::Kernel))
10182 WrapperKind = X86ISD::WrapperRIP;
10183 else if (Subtarget->isPICStyleGOT())
10184 OpFlag = X86II::MO_GOTOFF;
10185 else if (Subtarget->isPICStyleStubPIC())
10186 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10188 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10191 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10193 // With PIC, the address is actually $g + Offset.
10195 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10196 DAG.getNode(X86ISD::GlobalBaseReg,
10197 SDLoc(), getPointerTy()),
10204 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10205 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10207 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10208 // global base reg.
10209 unsigned char OpFlag = 0;
10210 unsigned WrapperKind = X86ISD::Wrapper;
10211 CodeModel::Model M = DAG.getTarget().getCodeModel();
10213 if (Subtarget->isPICStyleRIPRel() &&
10214 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10215 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10216 OpFlag = X86II::MO_GOTPCREL;
10217 WrapperKind = X86ISD::WrapperRIP;
10218 } else if (Subtarget->isPICStyleGOT()) {
10219 OpFlag = X86II::MO_GOT;
10220 } else if (Subtarget->isPICStyleStubPIC()) {
10221 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10222 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10223 OpFlag = X86II::MO_DARWIN_NONLAZY;
10226 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10229 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10231 // With PIC, the address is actually $g + Offset.
10232 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10233 !Subtarget->is64Bit()) {
10234 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10235 DAG.getNode(X86ISD::GlobalBaseReg,
10236 SDLoc(), getPointerTy()),
10240 // For symbols that require a load from a stub to get the address, emit the
10242 if (isGlobalStubReference(OpFlag))
10243 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10244 MachinePointerInfo::getGOT(), false, false, false, 0);
10250 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10251 // Create the TargetBlockAddressAddress node.
10252 unsigned char OpFlags =
10253 Subtarget->ClassifyBlockAddressReference();
10254 CodeModel::Model M = DAG.getTarget().getCodeModel();
10255 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10256 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10258 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10261 if (Subtarget->isPICStyleRIPRel() &&
10262 (M == CodeModel::Small || M == CodeModel::Kernel))
10263 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10265 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10267 // With PIC, the address is actually $g + Offset.
10268 if (isGlobalRelativeToPICBase(OpFlags)) {
10269 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10270 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10278 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10279 int64_t Offset, SelectionDAG &DAG) const {
10280 // Create the TargetGlobalAddress node, folding in the constant
10281 // offset if it is legal.
10282 unsigned char OpFlags =
10283 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10284 CodeModel::Model M = DAG.getTarget().getCodeModel();
10286 if (OpFlags == X86II::MO_NO_FLAG &&
10287 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10288 // A direct static reference to a global.
10289 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10292 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10295 if (Subtarget->isPICStyleRIPRel() &&
10296 (M == CodeModel::Small || M == CodeModel::Kernel))
10297 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10299 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10301 // With PIC, the address is actually $g + Offset.
10302 if (isGlobalRelativeToPICBase(OpFlags)) {
10303 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10304 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10308 // For globals that require a load from a stub to get the address, emit the
10310 if (isGlobalStubReference(OpFlags))
10311 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10312 MachinePointerInfo::getGOT(), false, false, false, 0);
10314 // If there was a non-zero offset that we didn't fold, create an explicit
10315 // addition for it.
10317 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10318 DAG.getConstant(Offset, getPointerTy()));
10324 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10325 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10326 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10327 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10331 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10332 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10333 unsigned char OperandFlags, bool LocalDynamic = false) {
10334 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10335 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10337 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10338 GA->getValueType(0),
10342 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10346 SDValue Ops[] = { Chain, TGA, *InFlag };
10347 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10349 SDValue Ops[] = { Chain, TGA };
10350 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10353 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10354 MFI->setAdjustsStack(true);
10356 SDValue Flag = Chain.getValue(1);
10357 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10360 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10362 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10365 SDLoc dl(GA); // ? function entry point might be better
10366 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10367 DAG.getNode(X86ISD::GlobalBaseReg,
10368 SDLoc(), PtrVT), InFlag);
10369 InFlag = Chain.getValue(1);
10371 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10374 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10376 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10378 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10379 X86::RAX, X86II::MO_TLSGD);
10382 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10388 // Get the start address of the TLS block for this module.
10389 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10390 .getInfo<X86MachineFunctionInfo>();
10391 MFI->incNumLocalDynamicTLSAccesses();
10395 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10396 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10399 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10400 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10401 InFlag = Chain.getValue(1);
10402 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10403 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10406 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10410 unsigned char OperandFlags = X86II::MO_DTPOFF;
10411 unsigned WrapperKind = X86ISD::Wrapper;
10412 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10413 GA->getValueType(0),
10414 GA->getOffset(), OperandFlags);
10415 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10417 // Add x@dtpoff with the base.
10418 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10421 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10422 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10423 const EVT PtrVT, TLSModel::Model model,
10424 bool is64Bit, bool isPIC) {
10427 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10428 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10429 is64Bit ? 257 : 256));
10431 SDValue ThreadPointer =
10432 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10433 MachinePointerInfo(Ptr), false, false, false, 0);
10435 unsigned char OperandFlags = 0;
10436 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10438 unsigned WrapperKind = X86ISD::Wrapper;
10439 if (model == TLSModel::LocalExec) {
10440 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10441 } else if (model == TLSModel::InitialExec) {
10443 OperandFlags = X86II::MO_GOTTPOFF;
10444 WrapperKind = X86ISD::WrapperRIP;
10446 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10449 llvm_unreachable("Unexpected model");
10452 // emit "addl x@ntpoff,%eax" (local exec)
10453 // or "addl x@indntpoff,%eax" (initial exec)
10454 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10456 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10457 GA->getOffset(), OperandFlags);
10458 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10460 if (model == TLSModel::InitialExec) {
10461 if (isPIC && !is64Bit) {
10462 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10463 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10467 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10468 MachinePointerInfo::getGOT(), false, false, false, 0);
10471 // The address of the thread local variable is the add of the thread
10472 // pointer with the offset of the variable.
10473 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10477 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10479 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10480 const GlobalValue *GV = GA->getGlobal();
10482 if (Subtarget->isTargetELF()) {
10483 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10486 case TLSModel::GeneralDynamic:
10487 if (Subtarget->is64Bit())
10488 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10489 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10490 case TLSModel::LocalDynamic:
10491 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10492 Subtarget->is64Bit());
10493 case TLSModel::InitialExec:
10494 case TLSModel::LocalExec:
10495 return LowerToTLSExecModel(
10496 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10497 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10499 llvm_unreachable("Unknown TLS model.");
10502 if (Subtarget->isTargetDarwin()) {
10503 // Darwin only has one model of TLS. Lower to that.
10504 unsigned char OpFlag = 0;
10505 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10506 X86ISD::WrapperRIP : X86ISD::Wrapper;
10508 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10509 // global base reg.
10510 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10511 !Subtarget->is64Bit();
10513 OpFlag = X86II::MO_TLVP_PIC_BASE;
10515 OpFlag = X86II::MO_TLVP;
10517 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10518 GA->getValueType(0),
10519 GA->getOffset(), OpFlag);
10520 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10522 // With PIC32, the address is actually $g + Offset.
10524 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10525 DAG.getNode(X86ISD::GlobalBaseReg,
10526 SDLoc(), getPointerTy()),
10529 // Lowering the machine isd will make sure everything is in the right
10531 SDValue Chain = DAG.getEntryNode();
10532 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10533 SDValue Args[] = { Chain, Offset };
10534 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10536 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10537 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10538 MFI->setAdjustsStack(true);
10540 // And our return value (tls address) is in the standard call return value
10542 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10543 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10544 Chain.getValue(1));
10547 if (Subtarget->isTargetKnownWindowsMSVC() ||
10548 Subtarget->isTargetWindowsGNU()) {
10549 // Just use the implicit TLS architecture
10550 // Need to generate someting similar to:
10551 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10553 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10554 // mov rcx, qword [rdx+rcx*8]
10555 // mov eax, .tls$:tlsvar
10556 // [rax+rcx] contains the address
10557 // Windows 64bit: gs:0x58
10558 // Windows 32bit: fs:__tls_array
10561 SDValue Chain = DAG.getEntryNode();
10563 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10564 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10565 // use its literal value of 0x2C.
10566 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10567 ? Type::getInt8PtrTy(*DAG.getContext(),
10569 : Type::getInt32PtrTy(*DAG.getContext(),
10573 Subtarget->is64Bit()
10574 ? DAG.getIntPtrConstant(0x58)
10575 : (Subtarget->isTargetWindowsGNU()
10576 ? DAG.getIntPtrConstant(0x2C)
10577 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10579 SDValue ThreadPointer =
10580 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10581 MachinePointerInfo(Ptr), false, false, false, 0);
10583 // Load the _tls_index variable
10584 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10585 if (Subtarget->is64Bit())
10586 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10587 IDX, MachinePointerInfo(), MVT::i32,
10590 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10591 false, false, false, 0);
10593 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10595 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10597 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10598 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10599 false, false, false, 0);
10601 // Get the offset of start of .tls section
10602 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10603 GA->getValueType(0),
10604 GA->getOffset(), X86II::MO_SECREL);
10605 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10607 // The address of the thread local variable is the add of the thread
10608 // pointer with the offset of the variable.
10609 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10612 llvm_unreachable("TLS not implemented for this target.");
10615 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
10616 /// and take a 2 x i32 value to shift plus a shift amount.
10617 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
10618 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
10619 MVT VT = Op.getSimpleValueType();
10620 unsigned VTBits = VT.getSizeInBits();
10622 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
10623 SDValue ShOpLo = Op.getOperand(0);
10624 SDValue ShOpHi = Op.getOperand(1);
10625 SDValue ShAmt = Op.getOperand(2);
10626 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
10627 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
10629 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10630 DAG.getConstant(VTBits - 1, MVT::i8));
10631 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
10632 DAG.getConstant(VTBits - 1, MVT::i8))
10633 : DAG.getConstant(0, VT);
10635 SDValue Tmp2, Tmp3;
10636 if (Op.getOpcode() == ISD::SHL_PARTS) {
10637 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
10638 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10640 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
10641 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
10644 // If the shift amount is larger or equal than the width of a part we can't
10645 // rely on the results of shld/shrd. Insert a test and select the appropriate
10646 // values for large shift amounts.
10647 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10648 DAG.getConstant(VTBits, MVT::i8));
10649 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10650 AndNode, DAG.getConstant(0, MVT::i8));
10653 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10654 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
10655 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
10657 if (Op.getOpcode() == ISD::SHL_PARTS) {
10658 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10659 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10661 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10662 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10665 SDValue Ops[2] = { Lo, Hi };
10666 return DAG.getMergeValues(Ops, dl);
10669 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
10670 SelectionDAG &DAG) const {
10671 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
10673 if (SrcVT.isVector())
10676 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
10677 "Unknown SINT_TO_FP to lower!");
10679 // These are really Legal; return the operand so the caller accepts it as
10681 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
10683 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
10684 Subtarget->is64Bit()) {
10689 unsigned Size = SrcVT.getSizeInBits()/8;
10690 MachineFunction &MF = DAG.getMachineFunction();
10691 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
10692 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10693 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10695 MachinePointerInfo::getFixedStack(SSFI),
10697 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
10700 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
10702 SelectionDAG &DAG) const {
10706 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
10708 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
10710 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
10712 unsigned ByteSize = SrcVT.getSizeInBits()/8;
10714 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
10715 MachineMemOperand *MMO;
10717 int SSFI = FI->getIndex();
10719 DAG.getMachineFunction()
10720 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10721 MachineMemOperand::MOLoad, ByteSize, ByteSize);
10723 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
10724 StackSlot = StackSlot.getOperand(1);
10726 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
10727 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
10729 Tys, Ops, SrcVT, MMO);
10732 Chain = Result.getValue(1);
10733 SDValue InFlag = Result.getValue(2);
10735 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
10736 // shouldn't be necessary except that RFP cannot be live across
10737 // multiple blocks. When stackifier is fixed, they can be uncoupled.
10738 MachineFunction &MF = DAG.getMachineFunction();
10739 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
10740 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
10741 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10742 Tys = DAG.getVTList(MVT::Other);
10744 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
10746 MachineMemOperand *MMO =
10747 DAG.getMachineFunction()
10748 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10749 MachineMemOperand::MOStore, SSFISize, SSFISize);
10751 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
10752 Ops, Op.getValueType(), MMO);
10753 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
10754 MachinePointerInfo::getFixedStack(SSFI),
10755 false, false, false, 0);
10761 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
10762 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
10763 SelectionDAG &DAG) const {
10764 // This algorithm is not obvious. Here it is what we're trying to output:
10767 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
10768 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
10770 haddpd %xmm0, %xmm0
10772 pshufd $0x4e, %xmm0, %xmm1
10778 LLVMContext *Context = DAG.getContext();
10780 // Build some magic constants.
10781 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
10782 Constant *C0 = ConstantDataVector::get(*Context, CV0);
10783 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
10785 SmallVector<Constant*,2> CV1;
10787 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10788 APInt(64, 0x4330000000000000ULL))));
10790 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10791 APInt(64, 0x4530000000000000ULL))));
10792 Constant *C1 = ConstantVector::get(CV1);
10793 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
10795 // Load the 64-bit value into an XMM register.
10796 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
10798 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
10799 MachinePointerInfo::getConstantPool(),
10800 false, false, false, 16);
10801 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
10802 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
10805 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
10806 MachinePointerInfo::getConstantPool(),
10807 false, false, false, 16);
10808 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
10809 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
10812 if (Subtarget->hasSSE3()) {
10813 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
10814 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
10816 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
10817 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
10819 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
10820 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
10824 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
10825 DAG.getIntPtrConstant(0));
10828 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
10829 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
10830 SelectionDAG &DAG) const {
10832 // FP constant to bias correct the final result.
10833 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
10836 // Load the 32-bit value into an XMM register.
10837 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
10840 // Zero out the upper parts of the register.
10841 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
10843 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10844 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
10845 DAG.getIntPtrConstant(0));
10847 // Or the load with the bias.
10848 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
10849 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10850 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10851 MVT::v2f64, Load)),
10852 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10853 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10854 MVT::v2f64, Bias)));
10855 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10856 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
10857 DAG.getIntPtrConstant(0));
10859 // Subtract the bias.
10860 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
10862 // Handle final rounding.
10863 EVT DestVT = Op.getValueType();
10865 if (DestVT.bitsLT(MVT::f64))
10866 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
10867 DAG.getIntPtrConstant(0));
10868 if (DestVT.bitsGT(MVT::f64))
10869 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
10871 // Handle final rounding.
10875 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
10876 SelectionDAG &DAG) const {
10877 SDValue N0 = Op.getOperand(0);
10878 MVT SVT = N0.getSimpleValueType();
10881 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
10882 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
10883 "Custom UINT_TO_FP is not supported!");
10885 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
10886 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
10887 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
10890 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
10891 SelectionDAG &DAG) const {
10892 SDValue N0 = Op.getOperand(0);
10895 if (Op.getValueType().isVector())
10896 return lowerUINT_TO_FP_vec(Op, DAG);
10898 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
10899 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
10900 // the optimization here.
10901 if (DAG.SignBitIsZero(N0))
10902 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
10904 MVT SrcVT = N0.getSimpleValueType();
10905 MVT DstVT = Op.getSimpleValueType();
10906 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
10907 return LowerUINT_TO_FP_i64(Op, DAG);
10908 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
10909 return LowerUINT_TO_FP_i32(Op, DAG);
10910 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
10913 // Make a 64-bit buffer, and use it to build an FILD.
10914 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
10915 if (SrcVT == MVT::i32) {
10916 SDValue WordOff = DAG.getConstant(4, getPointerTy());
10917 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
10918 getPointerTy(), StackSlot, WordOff);
10919 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10920 StackSlot, MachinePointerInfo(),
10922 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
10923 OffsetSlot, MachinePointerInfo(),
10925 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
10929 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
10930 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10931 StackSlot, MachinePointerInfo(),
10933 // For i64 source, we need to add the appropriate power of 2 if the input
10934 // was negative. This is the same as the optimization in
10935 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
10936 // we must be careful to do the computation in x87 extended precision, not
10937 // in SSE. (The generic code can't know it's OK to do this, or how to.)
10938 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
10939 MachineMemOperand *MMO =
10940 DAG.getMachineFunction()
10941 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10942 MachineMemOperand::MOLoad, 8, 8);
10944 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
10945 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
10946 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
10949 APInt FF(32, 0x5F800000ULL);
10951 // Check whether the sign bit is set.
10952 SDValue SignSet = DAG.getSetCC(dl,
10953 getSetCCResultType(*DAG.getContext(), MVT::i64),
10954 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
10957 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
10958 SDValue FudgePtr = DAG.getConstantPool(
10959 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
10962 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
10963 SDValue Zero = DAG.getIntPtrConstant(0);
10964 SDValue Four = DAG.getIntPtrConstant(4);
10965 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
10967 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
10969 // Load the value out, extending it from f32 to f80.
10970 // FIXME: Avoid the extend by constructing the right constant pool?
10971 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
10972 FudgePtr, MachinePointerInfo::getConstantPool(),
10973 MVT::f32, false, false, 4);
10974 // Extend everything to 80 bits to force it to be done on x87.
10975 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
10976 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
10979 std::pair<SDValue,SDValue>
10980 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
10981 bool IsSigned, bool IsReplace) const {
10984 EVT DstTy = Op.getValueType();
10986 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
10987 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
10991 assert(DstTy.getSimpleVT() <= MVT::i64 &&
10992 DstTy.getSimpleVT() >= MVT::i16 &&
10993 "Unknown FP_TO_INT to lower!");
10995 // These are really Legal.
10996 if (DstTy == MVT::i32 &&
10997 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
10998 return std::make_pair(SDValue(), SDValue());
10999 if (Subtarget->is64Bit() &&
11000 DstTy == MVT::i64 &&
11001 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11002 return std::make_pair(SDValue(), SDValue());
11004 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11005 // stack slot, or into the FTOL runtime function.
11006 MachineFunction &MF = DAG.getMachineFunction();
11007 unsigned MemSize = DstTy.getSizeInBits()/8;
11008 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11009 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11012 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11013 Opc = X86ISD::WIN_FTOL;
11015 switch (DstTy.getSimpleVT().SimpleTy) {
11016 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11017 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11018 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11019 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11022 SDValue Chain = DAG.getEntryNode();
11023 SDValue Value = Op.getOperand(0);
11024 EVT TheVT = Op.getOperand(0).getValueType();
11025 // FIXME This causes a redundant load/store if the SSE-class value is already
11026 // in memory, such as if it is on the callstack.
11027 if (isScalarFPTypeInSSEReg(TheVT)) {
11028 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11029 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11030 MachinePointerInfo::getFixedStack(SSFI),
11032 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11034 Chain, StackSlot, DAG.getValueType(TheVT)
11037 MachineMemOperand *MMO =
11038 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11039 MachineMemOperand::MOLoad, MemSize, MemSize);
11040 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11041 Chain = Value.getValue(1);
11042 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11043 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11046 MachineMemOperand *MMO =
11047 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11048 MachineMemOperand::MOStore, MemSize, MemSize);
11050 if (Opc != X86ISD::WIN_FTOL) {
11051 // Build the FP_TO_INT*_IN_MEM
11052 SDValue Ops[] = { Chain, Value, StackSlot };
11053 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11055 return std::make_pair(FIST, StackSlot);
11057 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11058 DAG.getVTList(MVT::Other, MVT::Glue),
11060 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11061 MVT::i32, ftol.getValue(1));
11062 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11063 MVT::i32, eax.getValue(2));
11064 SDValue Ops[] = { eax, edx };
11065 SDValue pair = IsReplace
11066 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11067 : DAG.getMergeValues(Ops, DL);
11068 return std::make_pair(pair, SDValue());
11072 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11073 const X86Subtarget *Subtarget) {
11074 MVT VT = Op->getSimpleValueType(0);
11075 SDValue In = Op->getOperand(0);
11076 MVT InVT = In.getSimpleValueType();
11079 // Optimize vectors in AVX mode:
11082 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11083 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11084 // Concat upper and lower parts.
11087 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11088 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11089 // Concat upper and lower parts.
11092 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11093 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11094 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11097 if (Subtarget->hasInt256())
11098 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11100 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11101 SDValue Undef = DAG.getUNDEF(InVT);
11102 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11103 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11104 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11106 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11107 VT.getVectorNumElements()/2);
11109 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11110 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11112 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11115 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11116 SelectionDAG &DAG) {
11117 MVT VT = Op->getSimpleValueType(0);
11118 SDValue In = Op->getOperand(0);
11119 MVT InVT = In.getSimpleValueType();
11121 unsigned int NumElts = VT.getVectorNumElements();
11122 if (NumElts != 8 && NumElts != 16)
11125 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11126 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11128 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11129 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11130 // Now we have only mask extension
11131 assert(InVT.getVectorElementType() == MVT::i1);
11132 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11133 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11134 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11135 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11136 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11137 MachinePointerInfo::getConstantPool(),
11138 false, false, false, Alignment);
11140 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11141 if (VT.is512BitVector())
11143 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11146 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11147 SelectionDAG &DAG) {
11148 if (Subtarget->hasFp256()) {
11149 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11157 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11158 SelectionDAG &DAG) {
11160 MVT VT = Op.getSimpleValueType();
11161 SDValue In = Op.getOperand(0);
11162 MVT SVT = In.getSimpleValueType();
11164 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11165 return LowerZERO_EXTEND_AVX512(Op, DAG);
11167 if (Subtarget->hasFp256()) {
11168 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11173 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11174 VT.getVectorNumElements() != SVT.getVectorNumElements());
11178 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11180 MVT VT = Op.getSimpleValueType();
11181 SDValue In = Op.getOperand(0);
11182 MVT InVT = In.getSimpleValueType();
11184 if (VT == MVT::i1) {
11185 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11186 "Invalid scalar TRUNCATE operation");
11187 if (InVT == MVT::i32)
11189 if (InVT.getSizeInBits() == 64)
11190 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11191 else if (InVT.getSizeInBits() < 32)
11192 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11193 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11195 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11196 "Invalid TRUNCATE operation");
11198 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11199 if (VT.getVectorElementType().getSizeInBits() >=8)
11200 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11202 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11203 unsigned NumElts = InVT.getVectorNumElements();
11204 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11205 if (InVT.getSizeInBits() < 512) {
11206 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11207 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11211 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11212 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11213 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11214 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11215 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11216 MachinePointerInfo::getConstantPool(),
11217 false, false, false, Alignment);
11218 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11219 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11220 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11223 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11224 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11225 if (Subtarget->hasInt256()) {
11226 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11227 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11228 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11230 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11231 DAG.getIntPtrConstant(0));
11234 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11235 DAG.getIntPtrConstant(0));
11236 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11237 DAG.getIntPtrConstant(2));
11238 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11239 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11240 static const int ShufMask[] = {0, 2, 4, 6};
11241 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11244 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11245 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11246 if (Subtarget->hasInt256()) {
11247 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11249 SmallVector<SDValue,32> pshufbMask;
11250 for (unsigned i = 0; i < 2; ++i) {
11251 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11252 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11253 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11254 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11255 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11256 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11257 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11258 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11259 for (unsigned j = 0; j < 8; ++j)
11260 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11262 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11263 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11264 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11266 static const int ShufMask[] = {0, 2, -1, -1};
11267 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11269 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11270 DAG.getIntPtrConstant(0));
11271 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11274 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11275 DAG.getIntPtrConstant(0));
11277 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11278 DAG.getIntPtrConstant(4));
11280 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11281 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11283 // The PSHUFB mask:
11284 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11285 -1, -1, -1, -1, -1, -1, -1, -1};
11287 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11288 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11289 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11291 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11292 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11294 // The MOVLHPS Mask:
11295 static const int ShufMask2[] = {0, 1, 4, 5};
11296 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11297 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11300 // Handle truncation of V256 to V128 using shuffles.
11301 if (!VT.is128BitVector() || !InVT.is256BitVector())
11304 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11306 unsigned NumElems = VT.getVectorNumElements();
11307 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11309 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11310 // Prepare truncation shuffle mask
11311 for (unsigned i = 0; i != NumElems; ++i)
11312 MaskVec[i] = i * 2;
11313 SDValue V = DAG.getVectorShuffle(NVT, DL,
11314 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11315 DAG.getUNDEF(NVT), &MaskVec[0]);
11316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11317 DAG.getIntPtrConstant(0));
11320 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11321 SelectionDAG &DAG) const {
11322 assert(!Op.getSimpleValueType().isVector());
11324 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11325 /*IsSigned=*/ true, /*IsReplace=*/ false);
11326 SDValue FIST = Vals.first, StackSlot = Vals.second;
11327 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11328 if (!FIST.getNode()) return Op;
11330 if (StackSlot.getNode())
11331 // Load the result.
11332 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11333 FIST, StackSlot, MachinePointerInfo(),
11334 false, false, false, 0);
11336 // The node is the result.
11340 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11341 SelectionDAG &DAG) const {
11342 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11343 /*IsSigned=*/ false, /*IsReplace=*/ false);
11344 SDValue FIST = Vals.first, StackSlot = Vals.second;
11345 assert(FIST.getNode() && "Unexpected failure");
11347 if (StackSlot.getNode())
11348 // Load the result.
11349 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11350 FIST, StackSlot, MachinePointerInfo(),
11351 false, false, false, 0);
11353 // The node is the result.
11357 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11359 MVT VT = Op.getSimpleValueType();
11360 SDValue In = Op.getOperand(0);
11361 MVT SVT = In.getSimpleValueType();
11363 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11365 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11366 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11367 In, DAG.getUNDEF(SVT)));
11370 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11371 LLVMContext *Context = DAG.getContext();
11373 MVT VT = Op.getSimpleValueType();
11375 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11376 if (VT.isVector()) {
11377 EltVT = VT.getVectorElementType();
11378 NumElts = VT.getVectorNumElements();
11381 if (EltVT == MVT::f64)
11382 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11383 APInt(64, ~(1ULL << 63))));
11385 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11386 APInt(32, ~(1U << 31))));
11387 C = ConstantVector::getSplat(NumElts, C);
11388 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11389 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11390 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11391 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11392 MachinePointerInfo::getConstantPool(),
11393 false, false, false, Alignment);
11394 if (VT.isVector()) {
11395 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11396 return DAG.getNode(ISD::BITCAST, dl, VT,
11397 DAG.getNode(ISD::AND, dl, ANDVT,
11398 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11400 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11402 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11405 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11406 LLVMContext *Context = DAG.getContext();
11408 MVT VT = Op.getSimpleValueType();
11410 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11411 if (VT.isVector()) {
11412 EltVT = VT.getVectorElementType();
11413 NumElts = VT.getVectorNumElements();
11416 if (EltVT == MVT::f64)
11417 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11418 APInt(64, 1ULL << 63)));
11420 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11421 APInt(32, 1U << 31)));
11422 C = ConstantVector::getSplat(NumElts, C);
11423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11424 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11425 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11426 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11427 MachinePointerInfo::getConstantPool(),
11428 false, false, false, Alignment);
11429 if (VT.isVector()) {
11430 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11431 return DAG.getNode(ISD::BITCAST, dl, VT,
11432 DAG.getNode(ISD::XOR, dl, XORVT,
11433 DAG.getNode(ISD::BITCAST, dl, XORVT,
11435 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11438 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11441 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11443 LLVMContext *Context = DAG.getContext();
11444 SDValue Op0 = Op.getOperand(0);
11445 SDValue Op1 = Op.getOperand(1);
11447 MVT VT = Op.getSimpleValueType();
11448 MVT SrcVT = Op1.getSimpleValueType();
11450 // If second operand is smaller, extend it first.
11451 if (SrcVT.bitsLT(VT)) {
11452 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
11455 // And if it is bigger, shrink it first.
11456 if (SrcVT.bitsGT(VT)) {
11457 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
11461 // At this point the operands and the result should have the same
11462 // type, and that won't be f80 since that is not custom lowered.
11464 // First get the sign bit of second operand.
11465 SmallVector<Constant*,4> CV;
11466 if (SrcVT == MVT::f64) {
11467 const fltSemantics &Sem = APFloat::IEEEdouble;
11468 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
11469 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11471 const fltSemantics &Sem = APFloat::IEEEsingle;
11472 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
11473 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11474 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11475 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11477 Constant *C = ConstantVector::get(CV);
11478 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11479 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
11480 MachinePointerInfo::getConstantPool(),
11481 false, false, false, 16);
11482 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
11484 // Shift sign bit right or left if the two operands have different types.
11485 if (SrcVT.bitsGT(VT)) {
11486 // Op0 is MVT::f32, Op1 is MVT::f64.
11487 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
11488 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
11489 DAG.getConstant(32, MVT::i32));
11490 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11491 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
11492 DAG.getIntPtrConstant(0));
11495 // Clear first operand sign bit.
11497 if (VT == MVT::f64) {
11498 const fltSemantics &Sem = APFloat::IEEEdouble;
11499 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11500 APInt(64, ~(1ULL << 63)))));
11501 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11503 const fltSemantics &Sem = APFloat::IEEEsingle;
11504 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11505 APInt(32, ~(1U << 31)))));
11506 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11507 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11508 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11510 C = ConstantVector::get(CV);
11511 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11512 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11513 MachinePointerInfo::getConstantPool(),
11514 false, false, false, 16);
11515 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
11517 // Or the value with the sign bit.
11518 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
11521 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
11522 SDValue N0 = Op.getOperand(0);
11524 MVT VT = Op.getSimpleValueType();
11526 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
11527 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
11528 DAG.getConstant(1, VT));
11529 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
11532 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
11534 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
11535 SelectionDAG &DAG) {
11536 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
11538 if (!Subtarget->hasSSE41())
11541 if (!Op->hasOneUse())
11544 SDNode *N = Op.getNode();
11547 SmallVector<SDValue, 8> Opnds;
11548 DenseMap<SDValue, unsigned> VecInMap;
11549 SmallVector<SDValue, 8> VecIns;
11550 EVT VT = MVT::Other;
11552 // Recognize a special case where a vector is casted into wide integer to
11554 Opnds.push_back(N->getOperand(0));
11555 Opnds.push_back(N->getOperand(1));
11557 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
11558 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
11559 // BFS traverse all OR'd operands.
11560 if (I->getOpcode() == ISD::OR) {
11561 Opnds.push_back(I->getOperand(0));
11562 Opnds.push_back(I->getOperand(1));
11563 // Re-evaluate the number of nodes to be traversed.
11564 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11568 // Quit if a non-EXTRACT_VECTOR_ELT
11569 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11572 // Quit if without a constant index.
11573 SDValue Idx = I->getOperand(1);
11574 if (!isa<ConstantSDNode>(Idx))
11577 SDValue ExtractedFromVec = I->getOperand(0);
11578 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
11579 if (M == VecInMap.end()) {
11580 VT = ExtractedFromVec.getValueType();
11581 // Quit if not 128/256-bit vector.
11582 if (!VT.is128BitVector() && !VT.is256BitVector())
11584 // Quit if not the same type.
11585 if (VecInMap.begin() != VecInMap.end() &&
11586 VT != VecInMap.begin()->first.getValueType())
11588 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
11589 VecIns.push_back(ExtractedFromVec);
11591 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
11594 assert((VT.is128BitVector() || VT.is256BitVector()) &&
11595 "Not extracted from 128-/256-bit vector.");
11597 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
11599 for (DenseMap<SDValue, unsigned>::const_iterator
11600 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
11601 // Quit if not all elements are used.
11602 if (I->second != FullMask)
11606 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11608 // Cast all vectors into TestVT for PTEST.
11609 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
11610 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
11612 // If more than one full vectors are evaluated, OR them first before PTEST.
11613 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
11614 // Each iteration will OR 2 nodes and append the result until there is only
11615 // 1 node left, i.e. the final OR'd value of all vectors.
11616 SDValue LHS = VecIns[Slot];
11617 SDValue RHS = VecIns[Slot + 1];
11618 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11621 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
11622 VecIns.back(), VecIns.back());
11625 /// \brief return true if \c Op has a use that doesn't just read flags.
11626 static bool hasNonFlagsUse(SDValue Op) {
11627 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
11629 SDNode *User = *UI;
11630 unsigned UOpNo = UI.getOperandNo();
11631 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
11632 // Look pass truncate.
11633 UOpNo = User->use_begin().getOperandNo();
11634 User = *User->use_begin();
11637 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11638 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
11644 /// Emit nodes that will be selected as "test Op0,Op0", or something
11646 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
11647 SelectionDAG &DAG) const {
11648 if (Op.getValueType() == MVT::i1)
11649 // KORTEST instruction should be selected
11650 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11651 DAG.getConstant(0, Op.getValueType()));
11653 // CF and OF aren't always set the way we want. Determine which
11654 // of these we need.
11655 bool NeedCF = false;
11656 bool NeedOF = false;
11659 case X86::COND_A: case X86::COND_AE:
11660 case X86::COND_B: case X86::COND_BE:
11663 case X86::COND_G: case X86::COND_GE:
11664 case X86::COND_L: case X86::COND_LE:
11665 case X86::COND_O: case X86::COND_NO: {
11666 // Check if we really need to set the
11667 // Overflow flag. If NoSignedWrap is present
11668 // that is not actually needed.
11669 switch (Op->getOpcode()) {
11674 const BinaryWithFlagsSDNode *BinNode =
11675 cast<BinaryWithFlagsSDNode>(Op.getNode());
11676 if (BinNode->hasNoSignedWrap())
11686 // See if we can use the EFLAGS value from the operand instead of
11687 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
11688 // we prove that the arithmetic won't overflow, we can't use OF or CF.
11689 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
11690 // Emit a CMP with 0, which is the TEST pattern.
11691 //if (Op.getValueType() == MVT::i1)
11692 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
11693 // DAG.getConstant(0, MVT::i1));
11694 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11695 DAG.getConstant(0, Op.getValueType()));
11697 unsigned Opcode = 0;
11698 unsigned NumOperands = 0;
11700 // Truncate operations may prevent the merge of the SETCC instruction
11701 // and the arithmetic instruction before it. Attempt to truncate the operands
11702 // of the arithmetic instruction and use a reduced bit-width instruction.
11703 bool NeedTruncation = false;
11704 SDValue ArithOp = Op;
11705 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
11706 SDValue Arith = Op->getOperand(0);
11707 // Both the trunc and the arithmetic op need to have one user each.
11708 if (Arith->hasOneUse())
11709 switch (Arith.getOpcode()) {
11716 NeedTruncation = true;
11722 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
11723 // which may be the result of a CAST. We use the variable 'Op', which is the
11724 // non-casted variable when we check for possible users.
11725 switch (ArithOp.getOpcode()) {
11727 // Due to an isel shortcoming, be conservative if this add is likely to be
11728 // selected as part of a load-modify-store instruction. When the root node
11729 // in a match is a store, isel doesn't know how to remap non-chain non-flag
11730 // uses of other nodes in the match, such as the ADD in this case. This
11731 // leads to the ADD being left around and reselected, with the result being
11732 // two adds in the output. Alas, even if none our users are stores, that
11733 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
11734 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
11735 // climbing the DAG back to the root, and it doesn't seem to be worth the
11737 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11738 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11739 if (UI->getOpcode() != ISD::CopyToReg &&
11740 UI->getOpcode() != ISD::SETCC &&
11741 UI->getOpcode() != ISD::STORE)
11744 if (ConstantSDNode *C =
11745 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
11746 // An add of one will be selected as an INC.
11747 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
11748 Opcode = X86ISD::INC;
11753 // An add of negative one (subtract of one) will be selected as a DEC.
11754 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
11755 Opcode = X86ISD::DEC;
11761 // Otherwise use a regular EFLAGS-setting add.
11762 Opcode = X86ISD::ADD;
11767 // If we have a constant logical shift that's only used in a comparison
11768 // against zero turn it into an equivalent AND. This allows turning it into
11769 // a TEST instruction later.
11770 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
11771 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
11772 EVT VT = Op.getValueType();
11773 unsigned BitWidth = VT.getSizeInBits();
11774 unsigned ShAmt = Op->getConstantOperandVal(1);
11775 if (ShAmt >= BitWidth) // Avoid undefined shifts.
11777 APInt Mask = ArithOp.getOpcode() == ISD::SRL
11778 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
11779 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
11780 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
11782 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
11783 DAG.getConstant(Mask, VT));
11784 DAG.ReplaceAllUsesWith(Op, New);
11790 // If the primary and result isn't used, don't bother using X86ISD::AND,
11791 // because a TEST instruction will be better.
11792 if (!hasNonFlagsUse(Op))
11798 // Due to the ISEL shortcoming noted above, be conservative if this op is
11799 // likely to be selected as part of a load-modify-store instruction.
11800 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11801 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11802 if (UI->getOpcode() == ISD::STORE)
11805 // Otherwise use a regular EFLAGS-setting instruction.
11806 switch (ArithOp.getOpcode()) {
11807 default: llvm_unreachable("unexpected operator!");
11808 case ISD::SUB: Opcode = X86ISD::SUB; break;
11809 case ISD::XOR: Opcode = X86ISD::XOR; break;
11810 case ISD::AND: Opcode = X86ISD::AND; break;
11812 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
11813 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
11814 if (EFLAGS.getNode())
11817 Opcode = X86ISD::OR;
11831 return SDValue(Op.getNode(), 1);
11837 // If we found that truncation is beneficial, perform the truncation and
11839 if (NeedTruncation) {
11840 EVT VT = Op.getValueType();
11841 SDValue WideVal = Op->getOperand(0);
11842 EVT WideVT = WideVal.getValueType();
11843 unsigned ConvertedOp = 0;
11844 // Use a target machine opcode to prevent further DAGCombine
11845 // optimizations that may separate the arithmetic operations
11846 // from the setcc node.
11847 switch (WideVal.getOpcode()) {
11849 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
11850 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
11851 case ISD::AND: ConvertedOp = X86ISD::AND; break;
11852 case ISD::OR: ConvertedOp = X86ISD::OR; break;
11853 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
11857 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11858 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
11859 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
11860 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
11861 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
11867 // Emit a CMP with 0, which is the TEST pattern.
11868 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11869 DAG.getConstant(0, Op.getValueType()));
11871 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11872 SmallVector<SDValue, 4> Ops;
11873 for (unsigned i = 0; i != NumOperands; ++i)
11874 Ops.push_back(Op.getOperand(i));
11876 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
11877 DAG.ReplaceAllUsesWith(Op, New);
11878 return SDValue(New.getNode(), 1);
11881 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
11883 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
11884 SDLoc dl, SelectionDAG &DAG) const {
11885 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
11886 if (C->getAPIntValue() == 0)
11887 return EmitTest(Op0, X86CC, dl, DAG);
11889 if (Op0.getValueType() == MVT::i1)
11890 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
11893 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
11894 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
11895 // Do the comparison at i32 if it's smaller, besides the Atom case.
11896 // This avoids subregister aliasing issues. Keep the smaller reference
11897 // if we're optimizing for size, however, as that'll allow better folding
11898 // of memory operations.
11899 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
11900 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
11901 AttributeSet::FunctionIndex, Attribute::MinSize) &&
11902 !Subtarget->isAtom()) {
11903 unsigned ExtendOp =
11904 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
11905 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
11906 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
11908 // Use SUB instead of CMP to enable CSE between SUB and CMP.
11909 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
11910 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
11912 return SDValue(Sub.getNode(), 1);
11914 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
11917 /// Convert a comparison if required by the subtarget.
11918 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
11919 SelectionDAG &DAG) const {
11920 // If the subtarget does not support the FUCOMI instruction, floating-point
11921 // comparisons have to be converted.
11922 if (Subtarget->hasCMov() ||
11923 Cmp.getOpcode() != X86ISD::CMP ||
11924 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
11925 !Cmp.getOperand(1).getValueType().isFloatingPoint())
11928 // The instruction selector will select an FUCOM instruction instead of
11929 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
11930 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
11931 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
11933 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
11934 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
11935 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
11936 DAG.getConstant(8, MVT::i8));
11937 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
11938 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
11941 static bool isAllOnes(SDValue V) {
11942 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
11943 return C && C->isAllOnesValue();
11946 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
11947 /// if it's possible.
11948 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
11949 SDLoc dl, SelectionDAG &DAG) const {
11950 SDValue Op0 = And.getOperand(0);
11951 SDValue Op1 = And.getOperand(1);
11952 if (Op0.getOpcode() == ISD::TRUNCATE)
11953 Op0 = Op0.getOperand(0);
11954 if (Op1.getOpcode() == ISD::TRUNCATE)
11955 Op1 = Op1.getOperand(0);
11958 if (Op1.getOpcode() == ISD::SHL)
11959 std::swap(Op0, Op1);
11960 if (Op0.getOpcode() == ISD::SHL) {
11961 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
11962 if (And00C->getZExtValue() == 1) {
11963 // If we looked past a truncate, check that it's only truncating away
11965 unsigned BitWidth = Op0.getValueSizeInBits();
11966 unsigned AndBitWidth = And.getValueSizeInBits();
11967 if (BitWidth > AndBitWidth) {
11969 DAG.computeKnownBits(Op0, Zeros, Ones);
11970 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
11974 RHS = Op0.getOperand(1);
11976 } else if (Op1.getOpcode() == ISD::Constant) {
11977 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
11978 uint64_t AndRHSVal = AndRHS->getZExtValue();
11979 SDValue AndLHS = Op0;
11981 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
11982 LHS = AndLHS.getOperand(0);
11983 RHS = AndLHS.getOperand(1);
11986 // Use BT if the immediate can't be encoded in a TEST instruction.
11987 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
11989 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
11993 if (LHS.getNode()) {
11994 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
11995 // instruction. Since the shift amount is in-range-or-undefined, we know
11996 // that doing a bittest on the i32 value is ok. We extend to i32 because
11997 // the encoding for the i16 version is larger than the i32 version.
11998 // Also promote i16 to i32 for performance / code size reason.
11999 if (LHS.getValueType() == MVT::i8 ||
12000 LHS.getValueType() == MVT::i16)
12001 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12003 // If the operand types disagree, extend the shift amount to match. Since
12004 // BT ignores high bits (like shifts) we can use anyextend.
12005 if (LHS.getValueType() != RHS.getValueType())
12006 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12008 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12009 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12010 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12011 DAG.getConstant(Cond, MVT::i8), BT);
12017 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12019 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12024 // SSE Condition code mapping:
12033 switch (SetCCOpcode) {
12034 default: llvm_unreachable("Unexpected SETCC condition");
12036 case ISD::SETEQ: SSECC = 0; break;
12038 case ISD::SETGT: Swap = true; // Fallthrough
12040 case ISD::SETOLT: SSECC = 1; break;
12042 case ISD::SETGE: Swap = true; // Fallthrough
12044 case ISD::SETOLE: SSECC = 2; break;
12045 case ISD::SETUO: SSECC = 3; break;
12047 case ISD::SETNE: SSECC = 4; break;
12048 case ISD::SETULE: Swap = true; // Fallthrough
12049 case ISD::SETUGE: SSECC = 5; break;
12050 case ISD::SETULT: Swap = true; // Fallthrough
12051 case ISD::SETUGT: SSECC = 6; break;
12052 case ISD::SETO: SSECC = 7; break;
12054 case ISD::SETONE: SSECC = 8; break;
12057 std::swap(Op0, Op1);
12062 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12063 // ones, and then concatenate the result back.
12064 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12065 MVT VT = Op.getSimpleValueType();
12067 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12068 "Unsupported value type for operation");
12070 unsigned NumElems = VT.getVectorNumElements();
12072 SDValue CC = Op.getOperand(2);
12074 // Extract the LHS vectors
12075 SDValue LHS = Op.getOperand(0);
12076 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12077 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12079 // Extract the RHS vectors
12080 SDValue RHS = Op.getOperand(1);
12081 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12082 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12084 // Issue the operation on the smaller types and concatenate the result back
12085 MVT EltVT = VT.getVectorElementType();
12086 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12087 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12088 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12089 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12092 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12093 const X86Subtarget *Subtarget) {
12094 SDValue Op0 = Op.getOperand(0);
12095 SDValue Op1 = Op.getOperand(1);
12096 SDValue CC = Op.getOperand(2);
12097 MVT VT = Op.getSimpleValueType();
12100 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12101 Op.getValueType().getScalarType() == MVT::i1 &&
12102 "Cannot set masked compare for this operation");
12104 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12106 bool Unsigned = false;
12109 switch (SetCCOpcode) {
12110 default: llvm_unreachable("Unexpected SETCC condition");
12111 case ISD::SETNE: SSECC = 4; break;
12112 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12113 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12114 case ISD::SETLT: Swap = true; //fall-through
12115 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12116 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12117 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12118 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12119 case ISD::SETULE: Unsigned = true; //fall-through
12120 case ISD::SETLE: SSECC = 2; break;
12124 std::swap(Op0, Op1);
12126 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12127 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12128 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12129 DAG.getConstant(SSECC, MVT::i8));
12132 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12133 /// operand \p Op1. If non-trivial (for example because it's not constant)
12134 /// return an empty value.
12135 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12137 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12141 MVT VT = Op1.getSimpleValueType();
12142 MVT EVT = VT.getVectorElementType();
12143 unsigned n = VT.getVectorNumElements();
12144 SmallVector<SDValue, 8> ULTOp1;
12146 for (unsigned i = 0; i < n; ++i) {
12147 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12148 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12151 // Avoid underflow.
12152 APInt Val = Elt->getAPIntValue();
12156 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12159 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12162 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12163 SelectionDAG &DAG) {
12164 SDValue Op0 = Op.getOperand(0);
12165 SDValue Op1 = Op.getOperand(1);
12166 SDValue CC = Op.getOperand(2);
12167 MVT VT = Op.getSimpleValueType();
12168 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12169 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12174 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12175 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12178 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12179 unsigned Opc = X86ISD::CMPP;
12180 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12181 assert(VT.getVectorNumElements() <= 16);
12182 Opc = X86ISD::CMPM;
12184 // In the two special cases we can't handle, emit two comparisons.
12187 unsigned CombineOpc;
12188 if (SetCCOpcode == ISD::SETUEQ) {
12189 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12191 assert(SetCCOpcode == ISD::SETONE);
12192 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12195 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12196 DAG.getConstant(CC0, MVT::i8));
12197 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12198 DAG.getConstant(CC1, MVT::i8));
12199 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12201 // Handle all other FP comparisons here.
12202 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12203 DAG.getConstant(SSECC, MVT::i8));
12206 // Break 256-bit integer vector compare into smaller ones.
12207 if (VT.is256BitVector() && !Subtarget->hasInt256())
12208 return Lower256IntVSETCC(Op, DAG);
12210 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12211 EVT OpVT = Op1.getValueType();
12212 if (Subtarget->hasAVX512()) {
12213 if (Op1.getValueType().is512BitVector() ||
12214 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12215 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12217 // In AVX-512 architecture setcc returns mask with i1 elements,
12218 // But there is no compare instruction for i8 and i16 elements.
12219 // We are not talking about 512-bit operands in this case, these
12220 // types are illegal.
12222 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12223 OpVT.getVectorElementType().getSizeInBits() >= 8))
12224 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12225 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12228 // We are handling one of the integer comparisons here. Since SSE only has
12229 // GT and EQ comparisons for integer, swapping operands and multiple
12230 // operations may be required for some comparisons.
12232 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12233 bool Subus = false;
12235 switch (SetCCOpcode) {
12236 default: llvm_unreachable("Unexpected SETCC condition");
12237 case ISD::SETNE: Invert = true;
12238 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12239 case ISD::SETLT: Swap = true;
12240 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12241 case ISD::SETGE: Swap = true;
12242 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12243 Invert = true; break;
12244 case ISD::SETULT: Swap = true;
12245 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12246 FlipSigns = true; break;
12247 case ISD::SETUGE: Swap = true;
12248 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12249 FlipSigns = true; Invert = true; break;
12252 // Special case: Use min/max operations for SETULE/SETUGE
12253 MVT VET = VT.getVectorElementType();
12255 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12256 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12259 switch (SetCCOpcode) {
12261 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12262 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12265 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12268 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12269 if (!MinMax && hasSubus) {
12270 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12272 // t = psubus Op0, Op1
12273 // pcmpeq t, <0..0>
12274 switch (SetCCOpcode) {
12276 case ISD::SETULT: {
12277 // If the comparison is against a constant we can turn this into a
12278 // setule. With psubus, setule does not require a swap. This is
12279 // beneficial because the constant in the register is no longer
12280 // destructed as the destination so it can be hoisted out of a loop.
12281 // Only do this pre-AVX since vpcmp* is no longer destructive.
12282 if (Subtarget->hasAVX())
12284 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12285 if (ULEOp1.getNode()) {
12287 Subus = true; Invert = false; Swap = false;
12291 // Psubus is better than flip-sign because it requires no inversion.
12292 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12293 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12297 Opc = X86ISD::SUBUS;
12303 std::swap(Op0, Op1);
12305 // Check that the operation in question is available (most are plain SSE2,
12306 // but PCMPGTQ and PCMPEQQ have different requirements).
12307 if (VT == MVT::v2i64) {
12308 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12309 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12311 // First cast everything to the right type.
12312 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12313 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12315 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12316 // bits of the inputs before performing those operations. The lower
12317 // compare is always unsigned.
12320 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12322 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12323 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12324 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12325 Sign, Zero, Sign, Zero);
12327 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12328 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12330 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12331 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12332 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12334 // Create masks for only the low parts/high parts of the 64 bit integers.
12335 static const int MaskHi[] = { 1, 1, 3, 3 };
12336 static const int MaskLo[] = { 0, 0, 2, 2 };
12337 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12338 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12339 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12341 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12342 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12345 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12347 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12350 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12351 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12352 // pcmpeqd + pshufd + pand.
12353 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12355 // First cast everything to the right type.
12356 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12357 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12360 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12362 // Make sure the lower and upper halves are both all-ones.
12363 static const int Mask[] = { 1, 0, 3, 2 };
12364 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12365 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12368 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12370 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12374 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12375 // bits of the inputs before performing those operations.
12377 EVT EltVT = VT.getVectorElementType();
12378 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12379 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12380 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12383 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12385 // If the logical-not of the result is required, perform that now.
12387 Result = DAG.getNOT(dl, Result, VT);
12390 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12393 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12394 getZeroVector(VT, Subtarget, DAG, dl));
12399 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12401 MVT VT = Op.getSimpleValueType();
12403 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12405 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12406 && "SetCC type must be 8-bit or 1-bit integer");
12407 SDValue Op0 = Op.getOperand(0);
12408 SDValue Op1 = Op.getOperand(1);
12410 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12412 // Optimize to BT if possible.
12413 // Lower (X & (1 << N)) == 0 to BT(X, N).
12414 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12415 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12416 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12417 Op1.getOpcode() == ISD::Constant &&
12418 cast<ConstantSDNode>(Op1)->isNullValue() &&
12419 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12420 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12421 if (NewSetCC.getNode())
12425 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12427 if (Op1.getOpcode() == ISD::Constant &&
12428 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12429 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12430 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12432 // If the input is a setcc, then reuse the input setcc or use a new one with
12433 // the inverted condition.
12434 if (Op0.getOpcode() == X86ISD::SETCC) {
12435 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12436 bool Invert = (CC == ISD::SETNE) ^
12437 cast<ConstantSDNode>(Op1)->isNullValue();
12441 CCode = X86::GetOppositeBranchCondition(CCode);
12442 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12443 DAG.getConstant(CCode, MVT::i8),
12444 Op0.getOperand(1));
12446 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12450 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12451 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12452 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12454 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12455 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12458 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12459 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12460 if (X86CC == X86::COND_INVALID)
12463 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12464 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12465 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12466 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12468 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12472 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
12473 static bool isX86LogicalCmp(SDValue Op) {
12474 unsigned Opc = Op.getNode()->getOpcode();
12475 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
12476 Opc == X86ISD::SAHF)
12478 if (Op.getResNo() == 1 &&
12479 (Opc == X86ISD::ADD ||
12480 Opc == X86ISD::SUB ||
12481 Opc == X86ISD::ADC ||
12482 Opc == X86ISD::SBB ||
12483 Opc == X86ISD::SMUL ||
12484 Opc == X86ISD::UMUL ||
12485 Opc == X86ISD::INC ||
12486 Opc == X86ISD::DEC ||
12487 Opc == X86ISD::OR ||
12488 Opc == X86ISD::XOR ||
12489 Opc == X86ISD::AND))
12492 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
12498 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
12499 if (V.getOpcode() != ISD::TRUNCATE)
12502 SDValue VOp0 = V.getOperand(0);
12503 unsigned InBits = VOp0.getValueSizeInBits();
12504 unsigned Bits = V.getValueSizeInBits();
12505 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
12508 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
12509 bool addTest = true;
12510 SDValue Cond = Op.getOperand(0);
12511 SDValue Op1 = Op.getOperand(1);
12512 SDValue Op2 = Op.getOperand(2);
12514 EVT VT = Op1.getValueType();
12517 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12518 // are available. Otherwise fp cmovs get lowered into a less efficient branch
12519 // sequence later on.
12520 if (Cond.getOpcode() == ISD::SETCC &&
12521 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12522 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12523 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12524 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12525 int SSECC = translateX86FSETCC(
12526 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12529 if (Subtarget->hasAVX512()) {
12530 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12531 DAG.getConstant(SSECC, MVT::i8));
12532 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12534 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12535 DAG.getConstant(SSECC, MVT::i8));
12536 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12537 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12538 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12542 if (Cond.getOpcode() == ISD::SETCC) {
12543 SDValue NewCond = LowerSETCC(Cond, DAG);
12544 if (NewCond.getNode())
12548 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12549 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12550 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12551 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12552 if (Cond.getOpcode() == X86ISD::SETCC &&
12553 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12554 isZero(Cond.getOperand(1).getOperand(1))) {
12555 SDValue Cmp = Cond.getOperand(1);
12557 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12559 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12560 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12561 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12563 SDValue CmpOp0 = Cmp.getOperand(0);
12564 // Apply further optimizations for special cases
12565 // (select (x != 0), -1, 0) -> neg & sbb
12566 // (select (x == 0), 0, -1) -> neg & sbb
12567 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12568 if (YC->isNullValue() &&
12569 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12570 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12571 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12572 DAG.getConstant(0, CmpOp0.getValueType()),
12574 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12575 DAG.getConstant(X86::COND_B, MVT::i8),
12576 SDValue(Neg.getNode(), 1));
12580 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12581 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12582 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12584 SDValue Res = // Res = 0 or -1.
12585 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12586 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12588 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12589 Res = DAG.getNOT(DL, Res, Res.getValueType());
12591 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12592 if (!N2C || !N2C->isNullValue())
12593 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12598 // Look past (and (setcc_carry (cmp ...)), 1).
12599 if (Cond.getOpcode() == ISD::AND &&
12600 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12601 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12602 if (C && C->getAPIntValue() == 1)
12603 Cond = Cond.getOperand(0);
12606 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12607 // setting operand in place of the X86ISD::SETCC.
12608 unsigned CondOpcode = Cond.getOpcode();
12609 if (CondOpcode == X86ISD::SETCC ||
12610 CondOpcode == X86ISD::SETCC_CARRY) {
12611 CC = Cond.getOperand(0);
12613 SDValue Cmp = Cond.getOperand(1);
12614 unsigned Opc = Cmp.getOpcode();
12615 MVT VT = Op.getSimpleValueType();
12617 bool IllegalFPCMov = false;
12618 if (VT.isFloatingPoint() && !VT.isVector() &&
12619 !isScalarFPTypeInSSEReg(VT)) // FPStack?
12620 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12622 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12623 Opc == X86ISD::BT) { // FIXME
12627 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12628 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12629 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12630 Cond.getOperand(0).getValueType() != MVT::i8)) {
12631 SDValue LHS = Cond.getOperand(0);
12632 SDValue RHS = Cond.getOperand(1);
12633 unsigned X86Opcode;
12636 switch (CondOpcode) {
12637 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12638 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12639 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12640 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12641 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12642 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12643 default: llvm_unreachable("unexpected overflowing operator");
12645 if (CondOpcode == ISD::UMULO)
12646 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12649 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12651 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12653 if (CondOpcode == ISD::UMULO)
12654 Cond = X86Op.getValue(2);
12656 Cond = X86Op.getValue(1);
12658 CC = DAG.getConstant(X86Cond, MVT::i8);
12663 // Look pass the truncate if the high bits are known zero.
12664 if (isTruncWithZeroHighBitsInput(Cond, DAG))
12665 Cond = Cond.getOperand(0);
12667 // We know the result of AND is compared against zero. Try to match
12669 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
12670 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
12671 if (NewSetCC.getNode()) {
12672 CC = NewSetCC.getOperand(0);
12673 Cond = NewSetCC.getOperand(1);
12680 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12681 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
12684 // a < b ? -1 : 0 -> RES = ~setcc_carry
12685 // a < b ? 0 : -1 -> RES = setcc_carry
12686 // a >= b ? -1 : 0 -> RES = setcc_carry
12687 // a >= b ? 0 : -1 -> RES = ~setcc_carry
12688 if (Cond.getOpcode() == X86ISD::SUB) {
12689 Cond = ConvertCmpIfNecessary(Cond, DAG);
12690 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
12692 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
12693 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
12694 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12695 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
12696 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
12697 return DAG.getNOT(DL, Res, Res.getValueType());
12702 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
12703 // widen the cmov and push the truncate through. This avoids introducing a new
12704 // branch during isel and doesn't add any extensions.
12705 if (Op.getValueType() == MVT::i8 &&
12706 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
12707 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
12708 if (T1.getValueType() == T2.getValueType() &&
12709 // Blacklist CopyFromReg to avoid partial register stalls.
12710 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
12711 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
12712 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
12713 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
12717 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
12718 // condition is true.
12719 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
12720 SDValue Ops[] = { Op2, Op1, CC, Cond };
12721 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
12724 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
12725 MVT VT = Op->getSimpleValueType(0);
12726 SDValue In = Op->getOperand(0);
12727 MVT InVT = In.getSimpleValueType();
12730 unsigned int NumElts = VT.getVectorNumElements();
12731 if (NumElts != 8 && NumElts != 16)
12734 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12735 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12737 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12738 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12740 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
12741 Constant *C = ConstantInt::get(*DAG.getContext(),
12742 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
12744 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12745 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12746 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
12747 MachinePointerInfo::getConstantPool(),
12748 false, false, false, Alignment);
12749 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
12750 if (VT.is512BitVector())
12752 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
12755 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12756 SelectionDAG &DAG) {
12757 MVT VT = Op->getSimpleValueType(0);
12758 SDValue In = Op->getOperand(0);
12759 MVT InVT = In.getSimpleValueType();
12762 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
12763 return LowerSIGN_EXTEND_AVX512(Op, DAG);
12765 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
12766 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
12767 (VT != MVT::v16i16 || InVT != MVT::v16i8))
12770 if (Subtarget->hasInt256())
12771 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12773 // Optimize vectors in AVX mode
12774 // Sign extend v8i16 to v8i32 and
12777 // Divide input vector into two parts
12778 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
12779 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
12780 // concat the vectors to original VT
12782 unsigned NumElems = InVT.getVectorNumElements();
12783 SDValue Undef = DAG.getUNDEF(InVT);
12785 SmallVector<int,8> ShufMask1(NumElems, -1);
12786 for (unsigned i = 0; i != NumElems/2; ++i)
12789 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
12791 SmallVector<int,8> ShufMask2(NumElems, -1);
12792 for (unsigned i = 0; i != NumElems/2; ++i)
12793 ShufMask2[i] = i + NumElems/2;
12795 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
12797 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
12798 VT.getVectorNumElements()/2);
12800 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
12801 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
12803 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12806 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
12807 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
12808 // from the AND / OR.
12809 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
12810 Opc = Op.getOpcode();
12811 if (Opc != ISD::OR && Opc != ISD::AND)
12813 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12814 Op.getOperand(0).hasOneUse() &&
12815 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
12816 Op.getOperand(1).hasOneUse());
12819 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
12820 // 1 and that the SETCC node has a single use.
12821 static bool isXor1OfSetCC(SDValue Op) {
12822 if (Op.getOpcode() != ISD::XOR)
12824 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
12825 if (N1C && N1C->getAPIntValue() == 1) {
12826 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12827 Op.getOperand(0).hasOneUse();
12832 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
12833 bool addTest = true;
12834 SDValue Chain = Op.getOperand(0);
12835 SDValue Cond = Op.getOperand(1);
12836 SDValue Dest = Op.getOperand(2);
12839 bool Inverted = false;
12841 if (Cond.getOpcode() == ISD::SETCC) {
12842 // Check for setcc([su]{add,sub,mul}o == 0).
12843 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
12844 isa<ConstantSDNode>(Cond.getOperand(1)) &&
12845 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
12846 Cond.getOperand(0).getResNo() == 1 &&
12847 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
12848 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
12849 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
12850 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
12851 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
12852 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
12854 Cond = Cond.getOperand(0);
12856 SDValue NewCond = LowerSETCC(Cond, DAG);
12857 if (NewCond.getNode())
12862 // FIXME: LowerXALUO doesn't handle these!!
12863 else if (Cond.getOpcode() == X86ISD::ADD ||
12864 Cond.getOpcode() == X86ISD::SUB ||
12865 Cond.getOpcode() == X86ISD::SMUL ||
12866 Cond.getOpcode() == X86ISD::UMUL)
12867 Cond = LowerXALUO(Cond, DAG);
12870 // Look pass (and (setcc_carry (cmp ...)), 1).
12871 if (Cond.getOpcode() == ISD::AND &&
12872 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12873 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12874 if (C && C->getAPIntValue() == 1)
12875 Cond = Cond.getOperand(0);
12878 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12879 // setting operand in place of the X86ISD::SETCC.
12880 unsigned CondOpcode = Cond.getOpcode();
12881 if (CondOpcode == X86ISD::SETCC ||
12882 CondOpcode == X86ISD::SETCC_CARRY) {
12883 CC = Cond.getOperand(0);
12885 SDValue Cmp = Cond.getOperand(1);
12886 unsigned Opc = Cmp.getOpcode();
12887 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
12888 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
12892 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
12896 // These can only come from an arithmetic instruction with overflow,
12897 // e.g. SADDO, UADDO.
12898 Cond = Cond.getNode()->getOperand(1);
12904 CondOpcode = Cond.getOpcode();
12905 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12906 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12907 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12908 Cond.getOperand(0).getValueType() != MVT::i8)) {
12909 SDValue LHS = Cond.getOperand(0);
12910 SDValue RHS = Cond.getOperand(1);
12911 unsigned X86Opcode;
12914 // Keep this in sync with LowerXALUO, otherwise we might create redundant
12915 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
12917 switch (CondOpcode) {
12918 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12920 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12922 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
12925 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12926 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12928 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12930 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
12933 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12934 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12935 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12936 default: llvm_unreachable("unexpected overflowing operator");
12939 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
12940 if (CondOpcode == ISD::UMULO)
12941 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12944 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12946 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
12948 if (CondOpcode == ISD::UMULO)
12949 Cond = X86Op.getValue(2);
12951 Cond = X86Op.getValue(1);
12953 CC = DAG.getConstant(X86Cond, MVT::i8);
12957 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
12958 SDValue Cmp = Cond.getOperand(0).getOperand(1);
12959 if (CondOpc == ISD::OR) {
12960 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
12961 // two branches instead of an explicit OR instruction with a
12963 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12964 isX86LogicalCmp(Cmp)) {
12965 CC = Cond.getOperand(0).getOperand(0);
12966 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12967 Chain, Dest, CC, Cmp);
12968 CC = Cond.getOperand(1).getOperand(0);
12972 } else { // ISD::AND
12973 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
12974 // two branches instead of an explicit AND instruction with a
12975 // separate test. However, we only do this if this block doesn't
12976 // have a fall-through edge, because this requires an explicit
12977 // jmp when the condition is false.
12978 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12979 isX86LogicalCmp(Cmp) &&
12980 Op.getNode()->hasOneUse()) {
12981 X86::CondCode CCode =
12982 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
12983 CCode = X86::GetOppositeBranchCondition(CCode);
12984 CC = DAG.getConstant(CCode, MVT::i8);
12985 SDNode *User = *Op.getNode()->use_begin();
12986 // Look for an unconditional branch following this conditional branch.
12987 // We need this because we need to reverse the successors in order
12988 // to implement FCMP_OEQ.
12989 if (User->getOpcode() == ISD::BR) {
12990 SDValue FalseBB = User->getOperand(1);
12992 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
12993 assert(NewBR == User);
12997 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12998 Chain, Dest, CC, Cmp);
12999 X86::CondCode CCode =
13000 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13001 CCode = X86::GetOppositeBranchCondition(CCode);
13002 CC = DAG.getConstant(CCode, MVT::i8);
13008 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13009 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13010 // It should be transformed during dag combiner except when the condition
13011 // is set by a arithmetics with overflow node.
13012 X86::CondCode CCode =
13013 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13014 CCode = X86::GetOppositeBranchCondition(CCode);
13015 CC = DAG.getConstant(CCode, MVT::i8);
13016 Cond = Cond.getOperand(0).getOperand(1);
13018 } else if (Cond.getOpcode() == ISD::SETCC &&
13019 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13020 // For FCMP_OEQ, we can emit
13021 // two branches instead of an explicit AND instruction with a
13022 // separate test. However, we only do this if this block doesn't
13023 // have a fall-through edge, because this requires an explicit
13024 // jmp when the condition is false.
13025 if (Op.getNode()->hasOneUse()) {
13026 SDNode *User = *Op.getNode()->use_begin();
13027 // Look for an unconditional branch following this conditional branch.
13028 // We need this because we need to reverse the successors in order
13029 // to implement FCMP_OEQ.
13030 if (User->getOpcode() == ISD::BR) {
13031 SDValue FalseBB = User->getOperand(1);
13033 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13034 assert(NewBR == User);
13038 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13039 Cond.getOperand(0), Cond.getOperand(1));
13040 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13041 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13042 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13043 Chain, Dest, CC, Cmp);
13044 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13049 } else if (Cond.getOpcode() == ISD::SETCC &&
13050 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13051 // For FCMP_UNE, we can emit
13052 // two branches instead of an explicit AND instruction with a
13053 // separate test. However, we only do this if this block doesn't
13054 // have a fall-through edge, because this requires an explicit
13055 // jmp when the condition is false.
13056 if (Op.getNode()->hasOneUse()) {
13057 SDNode *User = *Op.getNode()->use_begin();
13058 // Look for an unconditional branch following this conditional branch.
13059 // We need this because we need to reverse the successors in order
13060 // to implement FCMP_UNE.
13061 if (User->getOpcode() == ISD::BR) {
13062 SDValue FalseBB = User->getOperand(1);
13064 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13065 assert(NewBR == User);
13068 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13069 Cond.getOperand(0), Cond.getOperand(1));
13070 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13071 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13072 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13073 Chain, Dest, CC, Cmp);
13074 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13084 // Look pass the truncate if the high bits are known zero.
13085 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13086 Cond = Cond.getOperand(0);
13088 // We know the result of AND is compared against zero. Try to match
13090 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13091 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13092 if (NewSetCC.getNode()) {
13093 CC = NewSetCC.getOperand(0);
13094 Cond = NewSetCC.getOperand(1);
13101 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13102 CC = DAG.getConstant(X86Cond, MVT::i8);
13103 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13105 Cond = ConvertCmpIfNecessary(Cond, DAG);
13106 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13107 Chain, Dest, CC, Cond);
13110 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13111 // Calls to _alloca is needed to probe the stack when allocating more than 4k
13112 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13113 // that the guard pages used by the OS virtual memory manager are allocated in
13114 // correct sequence.
13116 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13117 SelectionDAG &DAG) const {
13118 MachineFunction &MF = DAG.getMachineFunction();
13119 bool SplitStack = MF.shouldSplitStack();
13120 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13126 SDNode* Node = Op.getNode();
13128 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13129 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13130 " not tell us which reg is the stack pointer!");
13131 EVT VT = Node->getValueType(0);
13132 SDValue Tmp1 = SDValue(Node, 0);
13133 SDValue Tmp2 = SDValue(Node, 1);
13134 SDValue Tmp3 = Node->getOperand(2);
13135 SDValue Chain = Tmp1.getOperand(0);
13137 // Chain the dynamic stack allocation so that it doesn't modify the stack
13138 // pointer when other instructions are using the stack.
13139 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13142 SDValue Size = Tmp2.getOperand(1);
13143 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13144 Chain = SP.getValue(1);
13145 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13146 const TargetFrameLowering &TFI = *DAG.getTarget().getFrameLowering();
13147 unsigned StackAlign = TFI.getStackAlignment();
13148 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13149 if (Align > StackAlign)
13150 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13151 DAG.getConstant(-(uint64_t)Align, VT));
13152 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13154 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13155 DAG.getIntPtrConstant(0, true), SDValue(),
13158 SDValue Ops[2] = { Tmp1, Tmp2 };
13159 return DAG.getMergeValues(Ops, dl);
13163 SDValue Chain = Op.getOperand(0);
13164 SDValue Size = Op.getOperand(1);
13165 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13166 EVT VT = Op.getNode()->getValueType(0);
13168 bool Is64Bit = Subtarget->is64Bit();
13169 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13172 MachineRegisterInfo &MRI = MF.getRegInfo();
13175 // The 64 bit implementation of segmented stacks needs to clobber both r10
13176 // r11. This makes it impossible to use it along with nested parameters.
13177 const Function *F = MF.getFunction();
13179 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13181 if (I->hasNestAttr())
13182 report_fatal_error("Cannot use segmented stacks with functions that "
13183 "have nested arguments.");
13186 const TargetRegisterClass *AddrRegClass =
13187 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13188 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13189 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13190 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13191 DAG.getRegister(Vreg, SPTy));
13192 SDValue Ops1[2] = { Value, Chain };
13193 return DAG.getMergeValues(Ops1, dl);
13196 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13198 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13199 Flag = Chain.getValue(1);
13200 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13202 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13204 const X86RegisterInfo *RegInfo =
13205 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
13206 unsigned SPReg = RegInfo->getStackRegister();
13207 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13208 Chain = SP.getValue(1);
13211 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13212 DAG.getConstant(-(uint64_t)Align, VT));
13213 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13216 SDValue Ops1[2] = { SP, Chain };
13217 return DAG.getMergeValues(Ops1, dl);
13221 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13222 MachineFunction &MF = DAG.getMachineFunction();
13223 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13225 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13228 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13229 // vastart just stores the address of the VarArgsFrameIndex slot into the
13230 // memory location argument.
13231 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13233 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13234 MachinePointerInfo(SV), false, false, 0);
13238 // gp_offset (0 - 6 * 8)
13239 // fp_offset (48 - 48 + 8 * 16)
13240 // overflow_arg_area (point to parameters coming in memory).
13242 SmallVector<SDValue, 8> MemOps;
13243 SDValue FIN = Op.getOperand(1);
13245 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13246 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13248 FIN, MachinePointerInfo(SV), false, false, 0);
13249 MemOps.push_back(Store);
13252 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13253 FIN, DAG.getIntPtrConstant(4));
13254 Store = DAG.getStore(Op.getOperand(0), DL,
13255 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13257 FIN, MachinePointerInfo(SV, 4), false, false, 0);
13258 MemOps.push_back(Store);
13260 // Store ptr to overflow_arg_area
13261 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13262 FIN, DAG.getIntPtrConstant(4));
13263 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13265 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13266 MachinePointerInfo(SV, 8),
13268 MemOps.push_back(Store);
13270 // Store ptr to reg_save_area.
13271 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13272 FIN, DAG.getIntPtrConstant(8));
13273 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13275 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13276 MachinePointerInfo(SV, 16), false, false, 0);
13277 MemOps.push_back(Store);
13278 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13281 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
13282 assert(Subtarget->is64Bit() &&
13283 "LowerVAARG only handles 64-bit va_arg!");
13284 assert((Subtarget->isTargetLinux() ||
13285 Subtarget->isTargetDarwin()) &&
13286 "Unhandled target in LowerVAARG");
13287 assert(Op.getNode()->getNumOperands() == 4);
13288 SDValue Chain = Op.getOperand(0);
13289 SDValue SrcPtr = Op.getOperand(1);
13290 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13291 unsigned Align = Op.getConstantOperandVal(3);
13294 EVT ArgVT = Op.getNode()->getValueType(0);
13295 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13296 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13299 // Decide which area this value should be read from.
13300 // TODO: Implement the AMD64 ABI in its entirety. This simple
13301 // selection mechanism works only for the basic types.
13302 if (ArgVT == MVT::f80) {
13303 llvm_unreachable("va_arg for f80 not yet implemented");
13304 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13305 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13306 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13307 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13309 llvm_unreachable("Unhandled argument type in LowerVAARG");
13312 if (ArgMode == 2) {
13313 // Sanity Check: Make sure using fp_offset makes sense.
13314 assert(!DAG.getTarget().Options.UseSoftFloat &&
13315 !(DAG.getMachineFunction()
13316 .getFunction()->getAttributes()
13317 .hasAttribute(AttributeSet::FunctionIndex,
13318 Attribute::NoImplicitFloat)) &&
13319 Subtarget->hasSSE1());
13322 // Insert VAARG_64 node into the DAG
13323 // VAARG_64 returns two values: Variable Argument Address, Chain
13324 SmallVector<SDValue, 11> InstOps;
13325 InstOps.push_back(Chain);
13326 InstOps.push_back(SrcPtr);
13327 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13328 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13329 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13330 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13331 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13332 VTs, InstOps, MVT::i64,
13333 MachinePointerInfo(SV),
13335 /*Volatile=*/false,
13337 /*WriteMem=*/true);
13338 Chain = VAARG.getValue(1);
13340 // Load the next argument and return it
13341 return DAG.getLoad(ArgVT, dl,
13344 MachinePointerInfo(),
13345 false, false, false, 0);
13348 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
13349 SelectionDAG &DAG) {
13350 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
13351 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
13352 SDValue Chain = Op.getOperand(0);
13353 SDValue DstPtr = Op.getOperand(1);
13354 SDValue SrcPtr = Op.getOperand(2);
13355 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
13356 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
13359 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
13360 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
13362 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
13365 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
13366 // amount is a constant. Takes immediate version of shift as input.
13367 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
13368 SDValue SrcOp, uint64_t ShiftAmt,
13369 SelectionDAG &DAG) {
13370 MVT ElementType = VT.getVectorElementType();
13372 // Fold this packed shift into its first operand if ShiftAmt is 0.
13376 // Check for ShiftAmt >= element width
13377 if (ShiftAmt >= ElementType.getSizeInBits()) {
13378 if (Opc == X86ISD::VSRAI)
13379 ShiftAmt = ElementType.getSizeInBits() - 1;
13381 return DAG.getConstant(0, VT);
13384 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
13385 && "Unknown target vector shift-by-constant node");
13387 // Fold this packed vector shift into a build vector if SrcOp is a
13388 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
13389 if (VT == SrcOp.getSimpleValueType() &&
13390 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
13391 SmallVector<SDValue, 8> Elts;
13392 unsigned NumElts = SrcOp->getNumOperands();
13393 ConstantSDNode *ND;
13396 default: llvm_unreachable(nullptr);
13397 case X86ISD::VSHLI:
13398 for (unsigned i=0; i!=NumElts; ++i) {
13399 SDValue CurrentOp = SrcOp->getOperand(i);
13400 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13401 Elts.push_back(CurrentOp);
13404 ND = cast<ConstantSDNode>(CurrentOp);
13405 const APInt &C = ND->getAPIntValue();
13406 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
13409 case X86ISD::VSRLI:
13410 for (unsigned i=0; i!=NumElts; ++i) {
13411 SDValue CurrentOp = SrcOp->getOperand(i);
13412 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13413 Elts.push_back(CurrentOp);
13416 ND = cast<ConstantSDNode>(CurrentOp);
13417 const APInt &C = ND->getAPIntValue();
13418 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
13421 case X86ISD::VSRAI:
13422 for (unsigned i=0; i!=NumElts; ++i) {
13423 SDValue CurrentOp = SrcOp->getOperand(i);
13424 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13425 Elts.push_back(CurrentOp);
13428 ND = cast<ConstantSDNode>(CurrentOp);
13429 const APInt &C = ND->getAPIntValue();
13430 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
13435 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13438 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
13441 // getTargetVShiftNode - Handle vector element shifts where the shift amount
13442 // may or may not be a constant. Takes immediate version of shift as input.
13443 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
13444 SDValue SrcOp, SDValue ShAmt,
13445 SelectionDAG &DAG) {
13446 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
13448 // Catch shift-by-constant.
13449 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
13450 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
13451 CShAmt->getZExtValue(), DAG);
13453 // Change opcode to non-immediate version
13455 default: llvm_unreachable("Unknown target vector shift node");
13456 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
13457 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
13458 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
13461 // Need to build a vector containing shift amount
13462 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
13465 ShOps[1] = DAG.getConstant(0, MVT::i32);
13466 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
13467 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
13469 // The return type has to be a 128-bit type with the same element
13470 // type as the input type.
13471 MVT EltVT = VT.getVectorElementType();
13472 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
13474 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
13475 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
13478 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
13480 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13482 default: return SDValue(); // Don't custom lower most intrinsics.
13483 // Comparison intrinsics.
13484 case Intrinsic::x86_sse_comieq_ss:
13485 case Intrinsic::x86_sse_comilt_ss:
13486 case Intrinsic::x86_sse_comile_ss:
13487 case Intrinsic::x86_sse_comigt_ss:
13488 case Intrinsic::x86_sse_comige_ss:
13489 case Intrinsic::x86_sse_comineq_ss:
13490 case Intrinsic::x86_sse_ucomieq_ss:
13491 case Intrinsic::x86_sse_ucomilt_ss:
13492 case Intrinsic::x86_sse_ucomile_ss:
13493 case Intrinsic::x86_sse_ucomigt_ss:
13494 case Intrinsic::x86_sse_ucomige_ss:
13495 case Intrinsic::x86_sse_ucomineq_ss:
13496 case Intrinsic::x86_sse2_comieq_sd:
13497 case Intrinsic::x86_sse2_comilt_sd:
13498 case Intrinsic::x86_sse2_comile_sd:
13499 case Intrinsic::x86_sse2_comigt_sd:
13500 case Intrinsic::x86_sse2_comige_sd:
13501 case Intrinsic::x86_sse2_comineq_sd:
13502 case Intrinsic::x86_sse2_ucomieq_sd:
13503 case Intrinsic::x86_sse2_ucomilt_sd:
13504 case Intrinsic::x86_sse2_ucomile_sd:
13505 case Intrinsic::x86_sse2_ucomigt_sd:
13506 case Intrinsic::x86_sse2_ucomige_sd:
13507 case Intrinsic::x86_sse2_ucomineq_sd: {
13511 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13512 case Intrinsic::x86_sse_comieq_ss:
13513 case Intrinsic::x86_sse2_comieq_sd:
13514 Opc = X86ISD::COMI;
13517 case Intrinsic::x86_sse_comilt_ss:
13518 case Intrinsic::x86_sse2_comilt_sd:
13519 Opc = X86ISD::COMI;
13522 case Intrinsic::x86_sse_comile_ss:
13523 case Intrinsic::x86_sse2_comile_sd:
13524 Opc = X86ISD::COMI;
13527 case Intrinsic::x86_sse_comigt_ss:
13528 case Intrinsic::x86_sse2_comigt_sd:
13529 Opc = X86ISD::COMI;
13532 case Intrinsic::x86_sse_comige_ss:
13533 case Intrinsic::x86_sse2_comige_sd:
13534 Opc = X86ISD::COMI;
13537 case Intrinsic::x86_sse_comineq_ss:
13538 case Intrinsic::x86_sse2_comineq_sd:
13539 Opc = X86ISD::COMI;
13542 case Intrinsic::x86_sse_ucomieq_ss:
13543 case Intrinsic::x86_sse2_ucomieq_sd:
13544 Opc = X86ISD::UCOMI;
13547 case Intrinsic::x86_sse_ucomilt_ss:
13548 case Intrinsic::x86_sse2_ucomilt_sd:
13549 Opc = X86ISD::UCOMI;
13552 case Intrinsic::x86_sse_ucomile_ss:
13553 case Intrinsic::x86_sse2_ucomile_sd:
13554 Opc = X86ISD::UCOMI;
13557 case Intrinsic::x86_sse_ucomigt_ss:
13558 case Intrinsic::x86_sse2_ucomigt_sd:
13559 Opc = X86ISD::UCOMI;
13562 case Intrinsic::x86_sse_ucomige_ss:
13563 case Intrinsic::x86_sse2_ucomige_sd:
13564 Opc = X86ISD::UCOMI;
13567 case Intrinsic::x86_sse_ucomineq_ss:
13568 case Intrinsic::x86_sse2_ucomineq_sd:
13569 Opc = X86ISD::UCOMI;
13574 SDValue LHS = Op.getOperand(1);
13575 SDValue RHS = Op.getOperand(2);
13576 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
13577 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
13578 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
13579 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13580 DAG.getConstant(X86CC, MVT::i8), Cond);
13581 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13584 // Arithmetic intrinsics.
13585 case Intrinsic::x86_sse2_pmulu_dq:
13586 case Intrinsic::x86_avx2_pmulu_dq:
13587 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
13588 Op.getOperand(1), Op.getOperand(2));
13590 case Intrinsic::x86_sse41_pmuldq:
13591 case Intrinsic::x86_avx2_pmul_dq:
13592 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
13593 Op.getOperand(1), Op.getOperand(2));
13595 case Intrinsic::x86_sse2_pmulhu_w:
13596 case Intrinsic::x86_avx2_pmulhu_w:
13597 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
13598 Op.getOperand(1), Op.getOperand(2));
13600 case Intrinsic::x86_sse2_pmulh_w:
13601 case Intrinsic::x86_avx2_pmulh_w:
13602 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
13603 Op.getOperand(1), Op.getOperand(2));
13605 // SSE2/AVX2 sub with unsigned saturation intrinsics
13606 case Intrinsic::x86_sse2_psubus_b:
13607 case Intrinsic::x86_sse2_psubus_w:
13608 case Intrinsic::x86_avx2_psubus_b:
13609 case Intrinsic::x86_avx2_psubus_w:
13610 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
13611 Op.getOperand(1), Op.getOperand(2));
13613 // SSE3/AVX horizontal add/sub intrinsics
13614 case Intrinsic::x86_sse3_hadd_ps:
13615 case Intrinsic::x86_sse3_hadd_pd:
13616 case Intrinsic::x86_avx_hadd_ps_256:
13617 case Intrinsic::x86_avx_hadd_pd_256:
13618 case Intrinsic::x86_sse3_hsub_ps:
13619 case Intrinsic::x86_sse3_hsub_pd:
13620 case Intrinsic::x86_avx_hsub_ps_256:
13621 case Intrinsic::x86_avx_hsub_pd_256:
13622 case Intrinsic::x86_ssse3_phadd_w_128:
13623 case Intrinsic::x86_ssse3_phadd_d_128:
13624 case Intrinsic::x86_avx2_phadd_w:
13625 case Intrinsic::x86_avx2_phadd_d:
13626 case Intrinsic::x86_ssse3_phsub_w_128:
13627 case Intrinsic::x86_ssse3_phsub_d_128:
13628 case Intrinsic::x86_avx2_phsub_w:
13629 case Intrinsic::x86_avx2_phsub_d: {
13632 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13633 case Intrinsic::x86_sse3_hadd_ps:
13634 case Intrinsic::x86_sse3_hadd_pd:
13635 case Intrinsic::x86_avx_hadd_ps_256:
13636 case Intrinsic::x86_avx_hadd_pd_256:
13637 Opcode = X86ISD::FHADD;
13639 case Intrinsic::x86_sse3_hsub_ps:
13640 case Intrinsic::x86_sse3_hsub_pd:
13641 case Intrinsic::x86_avx_hsub_ps_256:
13642 case Intrinsic::x86_avx_hsub_pd_256:
13643 Opcode = X86ISD::FHSUB;
13645 case Intrinsic::x86_ssse3_phadd_w_128:
13646 case Intrinsic::x86_ssse3_phadd_d_128:
13647 case Intrinsic::x86_avx2_phadd_w:
13648 case Intrinsic::x86_avx2_phadd_d:
13649 Opcode = X86ISD::HADD;
13651 case Intrinsic::x86_ssse3_phsub_w_128:
13652 case Intrinsic::x86_ssse3_phsub_d_128:
13653 case Intrinsic::x86_avx2_phsub_w:
13654 case Intrinsic::x86_avx2_phsub_d:
13655 Opcode = X86ISD::HSUB;
13658 return DAG.getNode(Opcode, dl, Op.getValueType(),
13659 Op.getOperand(1), Op.getOperand(2));
13662 // SSE2/SSE41/AVX2 integer max/min intrinsics.
13663 case Intrinsic::x86_sse2_pmaxu_b:
13664 case Intrinsic::x86_sse41_pmaxuw:
13665 case Intrinsic::x86_sse41_pmaxud:
13666 case Intrinsic::x86_avx2_pmaxu_b:
13667 case Intrinsic::x86_avx2_pmaxu_w:
13668 case Intrinsic::x86_avx2_pmaxu_d:
13669 case Intrinsic::x86_sse2_pminu_b:
13670 case Intrinsic::x86_sse41_pminuw:
13671 case Intrinsic::x86_sse41_pminud:
13672 case Intrinsic::x86_avx2_pminu_b:
13673 case Intrinsic::x86_avx2_pminu_w:
13674 case Intrinsic::x86_avx2_pminu_d:
13675 case Intrinsic::x86_sse41_pmaxsb:
13676 case Intrinsic::x86_sse2_pmaxs_w:
13677 case Intrinsic::x86_sse41_pmaxsd:
13678 case Intrinsic::x86_avx2_pmaxs_b:
13679 case Intrinsic::x86_avx2_pmaxs_w:
13680 case Intrinsic::x86_avx2_pmaxs_d:
13681 case Intrinsic::x86_sse41_pminsb:
13682 case Intrinsic::x86_sse2_pmins_w:
13683 case Intrinsic::x86_sse41_pminsd:
13684 case Intrinsic::x86_avx2_pmins_b:
13685 case Intrinsic::x86_avx2_pmins_w:
13686 case Intrinsic::x86_avx2_pmins_d: {
13689 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13690 case Intrinsic::x86_sse2_pmaxu_b:
13691 case Intrinsic::x86_sse41_pmaxuw:
13692 case Intrinsic::x86_sse41_pmaxud:
13693 case Intrinsic::x86_avx2_pmaxu_b:
13694 case Intrinsic::x86_avx2_pmaxu_w:
13695 case Intrinsic::x86_avx2_pmaxu_d:
13696 Opcode = X86ISD::UMAX;
13698 case Intrinsic::x86_sse2_pminu_b:
13699 case Intrinsic::x86_sse41_pminuw:
13700 case Intrinsic::x86_sse41_pminud:
13701 case Intrinsic::x86_avx2_pminu_b:
13702 case Intrinsic::x86_avx2_pminu_w:
13703 case Intrinsic::x86_avx2_pminu_d:
13704 Opcode = X86ISD::UMIN;
13706 case Intrinsic::x86_sse41_pmaxsb:
13707 case Intrinsic::x86_sse2_pmaxs_w:
13708 case Intrinsic::x86_sse41_pmaxsd:
13709 case Intrinsic::x86_avx2_pmaxs_b:
13710 case Intrinsic::x86_avx2_pmaxs_w:
13711 case Intrinsic::x86_avx2_pmaxs_d:
13712 Opcode = X86ISD::SMAX;
13714 case Intrinsic::x86_sse41_pminsb:
13715 case Intrinsic::x86_sse2_pmins_w:
13716 case Intrinsic::x86_sse41_pminsd:
13717 case Intrinsic::x86_avx2_pmins_b:
13718 case Intrinsic::x86_avx2_pmins_w:
13719 case Intrinsic::x86_avx2_pmins_d:
13720 Opcode = X86ISD::SMIN;
13723 return DAG.getNode(Opcode, dl, Op.getValueType(),
13724 Op.getOperand(1), Op.getOperand(2));
13727 // SSE/SSE2/AVX floating point max/min intrinsics.
13728 case Intrinsic::x86_sse_max_ps:
13729 case Intrinsic::x86_sse2_max_pd:
13730 case Intrinsic::x86_avx_max_ps_256:
13731 case Intrinsic::x86_avx_max_pd_256:
13732 case Intrinsic::x86_sse_min_ps:
13733 case Intrinsic::x86_sse2_min_pd:
13734 case Intrinsic::x86_avx_min_ps_256:
13735 case Intrinsic::x86_avx_min_pd_256: {
13738 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13739 case Intrinsic::x86_sse_max_ps:
13740 case Intrinsic::x86_sse2_max_pd:
13741 case Intrinsic::x86_avx_max_ps_256:
13742 case Intrinsic::x86_avx_max_pd_256:
13743 Opcode = X86ISD::FMAX;
13745 case Intrinsic::x86_sse_min_ps:
13746 case Intrinsic::x86_sse2_min_pd:
13747 case Intrinsic::x86_avx_min_ps_256:
13748 case Intrinsic::x86_avx_min_pd_256:
13749 Opcode = X86ISD::FMIN;
13752 return DAG.getNode(Opcode, dl, Op.getValueType(),
13753 Op.getOperand(1), Op.getOperand(2));
13756 // AVX2 variable shift intrinsics
13757 case Intrinsic::x86_avx2_psllv_d:
13758 case Intrinsic::x86_avx2_psllv_q:
13759 case Intrinsic::x86_avx2_psllv_d_256:
13760 case Intrinsic::x86_avx2_psllv_q_256:
13761 case Intrinsic::x86_avx2_psrlv_d:
13762 case Intrinsic::x86_avx2_psrlv_q:
13763 case Intrinsic::x86_avx2_psrlv_d_256:
13764 case Intrinsic::x86_avx2_psrlv_q_256:
13765 case Intrinsic::x86_avx2_psrav_d:
13766 case Intrinsic::x86_avx2_psrav_d_256: {
13769 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13770 case Intrinsic::x86_avx2_psllv_d:
13771 case Intrinsic::x86_avx2_psllv_q:
13772 case Intrinsic::x86_avx2_psllv_d_256:
13773 case Intrinsic::x86_avx2_psllv_q_256:
13776 case Intrinsic::x86_avx2_psrlv_d:
13777 case Intrinsic::x86_avx2_psrlv_q:
13778 case Intrinsic::x86_avx2_psrlv_d_256:
13779 case Intrinsic::x86_avx2_psrlv_q_256:
13782 case Intrinsic::x86_avx2_psrav_d:
13783 case Intrinsic::x86_avx2_psrav_d_256:
13787 return DAG.getNode(Opcode, dl, Op.getValueType(),
13788 Op.getOperand(1), Op.getOperand(2));
13791 case Intrinsic::x86_sse2_packssdw_128:
13792 case Intrinsic::x86_sse2_packsswb_128:
13793 case Intrinsic::x86_avx2_packssdw:
13794 case Intrinsic::x86_avx2_packsswb:
13795 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
13796 Op.getOperand(1), Op.getOperand(2));
13798 case Intrinsic::x86_sse2_packuswb_128:
13799 case Intrinsic::x86_sse41_packusdw:
13800 case Intrinsic::x86_avx2_packuswb:
13801 case Intrinsic::x86_avx2_packusdw:
13802 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
13803 Op.getOperand(1), Op.getOperand(2));
13805 case Intrinsic::x86_ssse3_pshuf_b_128:
13806 case Intrinsic::x86_avx2_pshuf_b:
13807 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
13808 Op.getOperand(1), Op.getOperand(2));
13810 case Intrinsic::x86_sse2_pshuf_d:
13811 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
13812 Op.getOperand(1), Op.getOperand(2));
13814 case Intrinsic::x86_sse2_pshufl_w:
13815 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
13816 Op.getOperand(1), Op.getOperand(2));
13818 case Intrinsic::x86_sse2_pshufh_w:
13819 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
13820 Op.getOperand(1), Op.getOperand(2));
13822 case Intrinsic::x86_ssse3_psign_b_128:
13823 case Intrinsic::x86_ssse3_psign_w_128:
13824 case Intrinsic::x86_ssse3_psign_d_128:
13825 case Intrinsic::x86_avx2_psign_b:
13826 case Intrinsic::x86_avx2_psign_w:
13827 case Intrinsic::x86_avx2_psign_d:
13828 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
13829 Op.getOperand(1), Op.getOperand(2));
13831 case Intrinsic::x86_sse41_insertps:
13832 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
13833 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13835 case Intrinsic::x86_avx_vperm2f128_ps_256:
13836 case Intrinsic::x86_avx_vperm2f128_pd_256:
13837 case Intrinsic::x86_avx_vperm2f128_si_256:
13838 case Intrinsic::x86_avx2_vperm2i128:
13839 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
13840 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13842 case Intrinsic::x86_avx2_permd:
13843 case Intrinsic::x86_avx2_permps:
13844 // Operands intentionally swapped. Mask is last operand to intrinsic,
13845 // but second operand for node/instruction.
13846 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
13847 Op.getOperand(2), Op.getOperand(1));
13849 case Intrinsic::x86_sse_sqrt_ps:
13850 case Intrinsic::x86_sse2_sqrt_pd:
13851 case Intrinsic::x86_avx_sqrt_ps_256:
13852 case Intrinsic::x86_avx_sqrt_pd_256:
13853 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
13855 // ptest and testp intrinsics. The intrinsic these come from are designed to
13856 // return an integer value, not just an instruction so lower it to the ptest
13857 // or testp pattern and a setcc for the result.
13858 case Intrinsic::x86_sse41_ptestz:
13859 case Intrinsic::x86_sse41_ptestc:
13860 case Intrinsic::x86_sse41_ptestnzc:
13861 case Intrinsic::x86_avx_ptestz_256:
13862 case Intrinsic::x86_avx_ptestc_256:
13863 case Intrinsic::x86_avx_ptestnzc_256:
13864 case Intrinsic::x86_avx_vtestz_ps:
13865 case Intrinsic::x86_avx_vtestc_ps:
13866 case Intrinsic::x86_avx_vtestnzc_ps:
13867 case Intrinsic::x86_avx_vtestz_pd:
13868 case Intrinsic::x86_avx_vtestc_pd:
13869 case Intrinsic::x86_avx_vtestnzc_pd:
13870 case Intrinsic::x86_avx_vtestz_ps_256:
13871 case Intrinsic::x86_avx_vtestc_ps_256:
13872 case Intrinsic::x86_avx_vtestnzc_ps_256:
13873 case Intrinsic::x86_avx_vtestz_pd_256:
13874 case Intrinsic::x86_avx_vtestc_pd_256:
13875 case Intrinsic::x86_avx_vtestnzc_pd_256: {
13876 bool IsTestPacked = false;
13879 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
13880 case Intrinsic::x86_avx_vtestz_ps:
13881 case Intrinsic::x86_avx_vtestz_pd:
13882 case Intrinsic::x86_avx_vtestz_ps_256:
13883 case Intrinsic::x86_avx_vtestz_pd_256:
13884 IsTestPacked = true; // Fallthrough
13885 case Intrinsic::x86_sse41_ptestz:
13886 case Intrinsic::x86_avx_ptestz_256:
13888 X86CC = X86::COND_E;
13890 case Intrinsic::x86_avx_vtestc_ps:
13891 case Intrinsic::x86_avx_vtestc_pd:
13892 case Intrinsic::x86_avx_vtestc_ps_256:
13893 case Intrinsic::x86_avx_vtestc_pd_256:
13894 IsTestPacked = true; // Fallthrough
13895 case Intrinsic::x86_sse41_ptestc:
13896 case Intrinsic::x86_avx_ptestc_256:
13898 X86CC = X86::COND_B;
13900 case Intrinsic::x86_avx_vtestnzc_ps:
13901 case Intrinsic::x86_avx_vtestnzc_pd:
13902 case Intrinsic::x86_avx_vtestnzc_ps_256:
13903 case Intrinsic::x86_avx_vtestnzc_pd_256:
13904 IsTestPacked = true; // Fallthrough
13905 case Intrinsic::x86_sse41_ptestnzc:
13906 case Intrinsic::x86_avx_ptestnzc_256:
13908 X86CC = X86::COND_A;
13912 SDValue LHS = Op.getOperand(1);
13913 SDValue RHS = Op.getOperand(2);
13914 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
13915 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
13916 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13917 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
13918 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13920 case Intrinsic::x86_avx512_kortestz_w:
13921 case Intrinsic::x86_avx512_kortestc_w: {
13922 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
13923 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
13924 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
13925 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13926 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
13927 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
13928 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13931 // SSE/AVX shift intrinsics
13932 case Intrinsic::x86_sse2_psll_w:
13933 case Intrinsic::x86_sse2_psll_d:
13934 case Intrinsic::x86_sse2_psll_q:
13935 case Intrinsic::x86_avx2_psll_w:
13936 case Intrinsic::x86_avx2_psll_d:
13937 case Intrinsic::x86_avx2_psll_q:
13938 case Intrinsic::x86_sse2_psrl_w:
13939 case Intrinsic::x86_sse2_psrl_d:
13940 case Intrinsic::x86_sse2_psrl_q:
13941 case Intrinsic::x86_avx2_psrl_w:
13942 case Intrinsic::x86_avx2_psrl_d:
13943 case Intrinsic::x86_avx2_psrl_q:
13944 case Intrinsic::x86_sse2_psra_w:
13945 case Intrinsic::x86_sse2_psra_d:
13946 case Intrinsic::x86_avx2_psra_w:
13947 case Intrinsic::x86_avx2_psra_d: {
13950 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13951 case Intrinsic::x86_sse2_psll_w:
13952 case Intrinsic::x86_sse2_psll_d:
13953 case Intrinsic::x86_sse2_psll_q:
13954 case Intrinsic::x86_avx2_psll_w:
13955 case Intrinsic::x86_avx2_psll_d:
13956 case Intrinsic::x86_avx2_psll_q:
13957 Opcode = X86ISD::VSHL;
13959 case Intrinsic::x86_sse2_psrl_w:
13960 case Intrinsic::x86_sse2_psrl_d:
13961 case Intrinsic::x86_sse2_psrl_q:
13962 case Intrinsic::x86_avx2_psrl_w:
13963 case Intrinsic::x86_avx2_psrl_d:
13964 case Intrinsic::x86_avx2_psrl_q:
13965 Opcode = X86ISD::VSRL;
13967 case Intrinsic::x86_sse2_psra_w:
13968 case Intrinsic::x86_sse2_psra_d:
13969 case Intrinsic::x86_avx2_psra_w:
13970 case Intrinsic::x86_avx2_psra_d:
13971 Opcode = X86ISD::VSRA;
13974 return DAG.getNode(Opcode, dl, Op.getValueType(),
13975 Op.getOperand(1), Op.getOperand(2));
13978 // SSE/AVX immediate shift intrinsics
13979 case Intrinsic::x86_sse2_pslli_w:
13980 case Intrinsic::x86_sse2_pslli_d:
13981 case Intrinsic::x86_sse2_pslli_q:
13982 case Intrinsic::x86_avx2_pslli_w:
13983 case Intrinsic::x86_avx2_pslli_d:
13984 case Intrinsic::x86_avx2_pslli_q:
13985 case Intrinsic::x86_sse2_psrli_w:
13986 case Intrinsic::x86_sse2_psrli_d:
13987 case Intrinsic::x86_sse2_psrli_q:
13988 case Intrinsic::x86_avx2_psrli_w:
13989 case Intrinsic::x86_avx2_psrli_d:
13990 case Intrinsic::x86_avx2_psrli_q:
13991 case Intrinsic::x86_sse2_psrai_w:
13992 case Intrinsic::x86_sse2_psrai_d:
13993 case Intrinsic::x86_avx2_psrai_w:
13994 case Intrinsic::x86_avx2_psrai_d: {
13997 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13998 case Intrinsic::x86_sse2_pslli_w:
13999 case Intrinsic::x86_sse2_pslli_d:
14000 case Intrinsic::x86_sse2_pslli_q:
14001 case Intrinsic::x86_avx2_pslli_w:
14002 case Intrinsic::x86_avx2_pslli_d:
14003 case Intrinsic::x86_avx2_pslli_q:
14004 Opcode = X86ISD::VSHLI;
14006 case Intrinsic::x86_sse2_psrli_w:
14007 case Intrinsic::x86_sse2_psrli_d:
14008 case Intrinsic::x86_sse2_psrli_q:
14009 case Intrinsic::x86_avx2_psrli_w:
14010 case Intrinsic::x86_avx2_psrli_d:
14011 case Intrinsic::x86_avx2_psrli_q:
14012 Opcode = X86ISD::VSRLI;
14014 case Intrinsic::x86_sse2_psrai_w:
14015 case Intrinsic::x86_sse2_psrai_d:
14016 case Intrinsic::x86_avx2_psrai_w:
14017 case Intrinsic::x86_avx2_psrai_d:
14018 Opcode = X86ISD::VSRAI;
14021 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
14022 Op.getOperand(1), Op.getOperand(2), DAG);
14025 case Intrinsic::x86_sse42_pcmpistria128:
14026 case Intrinsic::x86_sse42_pcmpestria128:
14027 case Intrinsic::x86_sse42_pcmpistric128:
14028 case Intrinsic::x86_sse42_pcmpestric128:
14029 case Intrinsic::x86_sse42_pcmpistrio128:
14030 case Intrinsic::x86_sse42_pcmpestrio128:
14031 case Intrinsic::x86_sse42_pcmpistris128:
14032 case Intrinsic::x86_sse42_pcmpestris128:
14033 case Intrinsic::x86_sse42_pcmpistriz128:
14034 case Intrinsic::x86_sse42_pcmpestriz128: {
14038 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14039 case Intrinsic::x86_sse42_pcmpistria128:
14040 Opcode = X86ISD::PCMPISTRI;
14041 X86CC = X86::COND_A;
14043 case Intrinsic::x86_sse42_pcmpestria128:
14044 Opcode = X86ISD::PCMPESTRI;
14045 X86CC = X86::COND_A;
14047 case Intrinsic::x86_sse42_pcmpistric128:
14048 Opcode = X86ISD::PCMPISTRI;
14049 X86CC = X86::COND_B;
14051 case Intrinsic::x86_sse42_pcmpestric128:
14052 Opcode = X86ISD::PCMPESTRI;
14053 X86CC = X86::COND_B;
14055 case Intrinsic::x86_sse42_pcmpistrio128:
14056 Opcode = X86ISD::PCMPISTRI;
14057 X86CC = X86::COND_O;
14059 case Intrinsic::x86_sse42_pcmpestrio128:
14060 Opcode = X86ISD::PCMPESTRI;
14061 X86CC = X86::COND_O;
14063 case Intrinsic::x86_sse42_pcmpistris128:
14064 Opcode = X86ISD::PCMPISTRI;
14065 X86CC = X86::COND_S;
14067 case Intrinsic::x86_sse42_pcmpestris128:
14068 Opcode = X86ISD::PCMPESTRI;
14069 X86CC = X86::COND_S;
14071 case Intrinsic::x86_sse42_pcmpistriz128:
14072 Opcode = X86ISD::PCMPISTRI;
14073 X86CC = X86::COND_E;
14075 case Intrinsic::x86_sse42_pcmpestriz128:
14076 Opcode = X86ISD::PCMPESTRI;
14077 X86CC = X86::COND_E;
14080 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14081 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14082 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14083 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14084 DAG.getConstant(X86CC, MVT::i8),
14085 SDValue(PCMP.getNode(), 1));
14086 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14089 case Intrinsic::x86_sse42_pcmpistri128:
14090 case Intrinsic::x86_sse42_pcmpestri128: {
14092 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14093 Opcode = X86ISD::PCMPISTRI;
14095 Opcode = X86ISD::PCMPESTRI;
14097 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14098 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14099 return DAG.getNode(Opcode, dl, VTs, NewOps);
14101 case Intrinsic::x86_fma_vfmadd_ps:
14102 case Intrinsic::x86_fma_vfmadd_pd:
14103 case Intrinsic::x86_fma_vfmsub_ps:
14104 case Intrinsic::x86_fma_vfmsub_pd:
14105 case Intrinsic::x86_fma_vfnmadd_ps:
14106 case Intrinsic::x86_fma_vfnmadd_pd:
14107 case Intrinsic::x86_fma_vfnmsub_ps:
14108 case Intrinsic::x86_fma_vfnmsub_pd:
14109 case Intrinsic::x86_fma_vfmaddsub_ps:
14110 case Intrinsic::x86_fma_vfmaddsub_pd:
14111 case Intrinsic::x86_fma_vfmsubadd_ps:
14112 case Intrinsic::x86_fma_vfmsubadd_pd:
14113 case Intrinsic::x86_fma_vfmadd_ps_256:
14114 case Intrinsic::x86_fma_vfmadd_pd_256:
14115 case Intrinsic::x86_fma_vfmsub_ps_256:
14116 case Intrinsic::x86_fma_vfmsub_pd_256:
14117 case Intrinsic::x86_fma_vfnmadd_ps_256:
14118 case Intrinsic::x86_fma_vfnmadd_pd_256:
14119 case Intrinsic::x86_fma_vfnmsub_ps_256:
14120 case Intrinsic::x86_fma_vfnmsub_pd_256:
14121 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14122 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14123 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14124 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14125 case Intrinsic::x86_fma_vfmadd_ps_512:
14126 case Intrinsic::x86_fma_vfmadd_pd_512:
14127 case Intrinsic::x86_fma_vfmsub_ps_512:
14128 case Intrinsic::x86_fma_vfmsub_pd_512:
14129 case Intrinsic::x86_fma_vfnmadd_ps_512:
14130 case Intrinsic::x86_fma_vfnmadd_pd_512:
14131 case Intrinsic::x86_fma_vfnmsub_ps_512:
14132 case Intrinsic::x86_fma_vfnmsub_pd_512:
14133 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14134 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14135 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14136 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
14139 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14140 case Intrinsic::x86_fma_vfmadd_ps:
14141 case Intrinsic::x86_fma_vfmadd_pd:
14142 case Intrinsic::x86_fma_vfmadd_ps_256:
14143 case Intrinsic::x86_fma_vfmadd_pd_256:
14144 case Intrinsic::x86_fma_vfmadd_ps_512:
14145 case Intrinsic::x86_fma_vfmadd_pd_512:
14146 Opc = X86ISD::FMADD;
14148 case Intrinsic::x86_fma_vfmsub_ps:
14149 case Intrinsic::x86_fma_vfmsub_pd:
14150 case Intrinsic::x86_fma_vfmsub_ps_256:
14151 case Intrinsic::x86_fma_vfmsub_pd_256:
14152 case Intrinsic::x86_fma_vfmsub_ps_512:
14153 case Intrinsic::x86_fma_vfmsub_pd_512:
14154 Opc = X86ISD::FMSUB;
14156 case Intrinsic::x86_fma_vfnmadd_ps:
14157 case Intrinsic::x86_fma_vfnmadd_pd:
14158 case Intrinsic::x86_fma_vfnmadd_ps_256:
14159 case Intrinsic::x86_fma_vfnmadd_pd_256:
14160 case Intrinsic::x86_fma_vfnmadd_ps_512:
14161 case Intrinsic::x86_fma_vfnmadd_pd_512:
14162 Opc = X86ISD::FNMADD;
14164 case Intrinsic::x86_fma_vfnmsub_ps:
14165 case Intrinsic::x86_fma_vfnmsub_pd:
14166 case Intrinsic::x86_fma_vfnmsub_ps_256:
14167 case Intrinsic::x86_fma_vfnmsub_pd_256:
14168 case Intrinsic::x86_fma_vfnmsub_ps_512:
14169 case Intrinsic::x86_fma_vfnmsub_pd_512:
14170 Opc = X86ISD::FNMSUB;
14172 case Intrinsic::x86_fma_vfmaddsub_ps:
14173 case Intrinsic::x86_fma_vfmaddsub_pd:
14174 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14175 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14176 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14177 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14178 Opc = X86ISD::FMADDSUB;
14180 case Intrinsic::x86_fma_vfmsubadd_ps:
14181 case Intrinsic::x86_fma_vfmsubadd_pd:
14182 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14183 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14184 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14185 case Intrinsic::x86_fma_vfmsubadd_pd_512:
14186 Opc = X86ISD::FMSUBADD;
14190 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
14191 Op.getOperand(2), Op.getOperand(3));
14196 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14197 SDValue Src, SDValue Mask, SDValue Base,
14198 SDValue Index, SDValue ScaleOp, SDValue Chain,
14199 const X86Subtarget * Subtarget) {
14201 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14202 assert(C && "Invalid scale type");
14203 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14204 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14205 Index.getSimpleValueType().getVectorNumElements());
14207 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14209 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14211 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14212 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14213 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14214 SDValue Segment = DAG.getRegister(0, MVT::i32);
14215 if (Src.getOpcode() == ISD::UNDEF)
14216 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14217 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14218 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14219 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14220 return DAG.getMergeValues(RetOps, dl);
14223 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14224 SDValue Src, SDValue Mask, SDValue Base,
14225 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14227 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14228 assert(C && "Invalid scale type");
14229 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14230 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14231 SDValue Segment = DAG.getRegister(0, MVT::i32);
14232 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14233 Index.getSimpleValueType().getVectorNumElements());
14235 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14237 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14239 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14240 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14241 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14242 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14243 return SDValue(Res, 1);
14246 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14247 SDValue Mask, SDValue Base, SDValue Index,
14248 SDValue ScaleOp, SDValue Chain) {
14250 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14251 assert(C && "Invalid scale type");
14252 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14253 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14254 SDValue Segment = DAG.getRegister(0, MVT::i32);
14256 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14258 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14260 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14262 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14263 //SDVTList VTs = DAG.getVTList(MVT::Other);
14264 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14265 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14266 return SDValue(Res, 0);
14269 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14270 // read performance monitor counters (x86_rdpmc).
14271 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14272 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14273 SmallVectorImpl<SDValue> &Results) {
14274 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14275 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14278 // The ECX register is used to select the index of the performance counter
14280 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14282 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14284 // Reads the content of a 64-bit performance counter and returns it in the
14285 // registers EDX:EAX.
14286 if (Subtarget->is64Bit()) {
14287 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14288 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14291 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14292 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14295 Chain = HI.getValue(1);
14297 if (Subtarget->is64Bit()) {
14298 // The EAX register is loaded with the low-order 32 bits. The EDX register
14299 // is loaded with the supported high-order bits of the counter.
14300 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14301 DAG.getConstant(32, MVT::i8));
14302 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14303 Results.push_back(Chain);
14307 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14308 SDValue Ops[] = { LO, HI };
14309 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14310 Results.push_back(Pair);
14311 Results.push_back(Chain);
14314 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14315 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14316 // also used to custom lower READCYCLECOUNTER nodes.
14317 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14318 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14319 SmallVectorImpl<SDValue> &Results) {
14320 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14321 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14324 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14325 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14326 // and the EAX register is loaded with the low-order 32 bits.
14327 if (Subtarget->is64Bit()) {
14328 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14329 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14332 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14333 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14336 SDValue Chain = HI.getValue(1);
14338 if (Opcode == X86ISD::RDTSCP_DAG) {
14339 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14341 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14342 // the ECX register. Add 'ecx' explicitly to the chain.
14343 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14345 // Explicitly store the content of ECX at the location passed in input
14346 // to the 'rdtscp' intrinsic.
14347 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14348 MachinePointerInfo(), false, false, 0);
14351 if (Subtarget->is64Bit()) {
14352 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14353 // the EAX register is loaded with the low-order 32 bits.
14354 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14355 DAG.getConstant(32, MVT::i8));
14356 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14357 Results.push_back(Chain);
14361 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14362 SDValue Ops[] = { LO, HI };
14363 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14364 Results.push_back(Pair);
14365 Results.push_back(Chain);
14368 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14369 SelectionDAG &DAG) {
14370 SmallVector<SDValue, 2> Results;
14372 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14374 return DAG.getMergeValues(Results, DL);
14377 enum IntrinsicType {
14378 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
14381 struct IntrinsicData {
14382 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
14383 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
14384 IntrinsicType Type;
14389 std::map < unsigned, IntrinsicData> IntrMap;
14390 static void InitIntinsicsMap() {
14391 static bool Initialized = false;
14394 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14395 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14396 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14397 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14398 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
14399 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
14400 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
14401 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
14402 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
14403 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
14404 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
14405 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
14406 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
14407 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
14408 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
14409 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
14410 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
14411 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
14413 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
14414 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
14415 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
14416 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
14417 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
14418 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
14419 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
14420 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
14421 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
14422 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
14423 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
14424 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
14425 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
14426 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
14427 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
14428 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
14430 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
14431 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
14432 X86::VGATHERPF1QPSm)));
14433 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
14434 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
14435 X86::VGATHERPF1QPDm)));
14436 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
14437 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
14438 X86::VGATHERPF1DPDm)));
14439 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
14440 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
14441 X86::VGATHERPF1DPSm)));
14442 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
14443 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
14444 X86::VSCATTERPF1QPSm)));
14445 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
14446 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
14447 X86::VSCATTERPF1QPDm)));
14448 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
14449 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
14450 X86::VSCATTERPF1DPDm)));
14451 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
14452 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
14453 X86::VSCATTERPF1DPSm)));
14454 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
14455 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14456 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
14457 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14458 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
14459 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14460 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
14461 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14462 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
14463 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14464 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
14465 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14466 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
14467 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
14468 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
14469 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
14470 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
14471 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
14472 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
14473 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
14474 Initialized = true;
14477 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14478 SelectionDAG &DAG) {
14479 InitIntinsicsMap();
14480 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14481 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
14482 if (itr == IntrMap.end())
14486 IntrinsicData Intr = itr->second;
14487 switch(Intr.Type) {
14490 // Emit the node with the right value type.
14491 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14492 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
14494 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
14495 // Otherwise return the value from Rand, which is always 0, casted to i32.
14496 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
14497 DAG.getConstant(1, Op->getValueType(1)),
14498 DAG.getConstant(X86::COND_B, MVT::i32),
14499 SDValue(Result.getNode(), 1) };
14500 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14501 DAG.getVTList(Op->getValueType(1), MVT::Glue),
14504 // Return { result, isValid, chain }.
14505 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
14506 SDValue(Result.getNode(), 2));
14509 //gather(v1, mask, index, base, scale);
14510 SDValue Chain = Op.getOperand(0);
14511 SDValue Src = Op.getOperand(2);
14512 SDValue Base = Op.getOperand(3);
14513 SDValue Index = Op.getOperand(4);
14514 SDValue Mask = Op.getOperand(5);
14515 SDValue Scale = Op.getOperand(6);
14516 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
14520 //scatter(base, mask, index, v1, scale);
14521 SDValue Chain = Op.getOperand(0);
14522 SDValue Base = Op.getOperand(2);
14523 SDValue Mask = Op.getOperand(3);
14524 SDValue Index = Op.getOperand(4);
14525 SDValue Src = Op.getOperand(5);
14526 SDValue Scale = Op.getOperand(6);
14527 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
14530 SDValue Hint = Op.getOperand(6);
14532 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
14533 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
14534 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
14535 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
14536 SDValue Chain = Op.getOperand(0);
14537 SDValue Mask = Op.getOperand(2);
14538 SDValue Index = Op.getOperand(3);
14539 SDValue Base = Op.getOperand(4);
14540 SDValue Scale = Op.getOperand(5);
14541 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
14543 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
14545 SmallVector<SDValue, 2> Results;
14546 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
14547 return DAG.getMergeValues(Results, dl);
14549 // Read Performance Monitoring Counters.
14551 SmallVector<SDValue, 2> Results;
14552 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
14553 return DAG.getMergeValues(Results, dl);
14555 // XTEST intrinsics.
14557 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
14558 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
14559 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14560 DAG.getConstant(X86::COND_NE, MVT::i8),
14562 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
14563 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
14564 Ret, SDValue(InTrans.getNode(), 1));
14567 llvm_unreachable("Unknown Intrinsic Type");
14570 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
14571 SelectionDAG &DAG) const {
14572 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14573 MFI->setReturnAddressIsTaken(true);
14575 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
14578 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14580 EVT PtrVT = getPointerTy();
14583 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
14584 const X86RegisterInfo *RegInfo =
14585 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14586 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
14587 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14588 DAG.getNode(ISD::ADD, dl, PtrVT,
14589 FrameAddr, Offset),
14590 MachinePointerInfo(), false, false, false, 0);
14593 // Just load the return address.
14594 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
14595 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14596 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
14599 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
14600 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14601 MFI->setFrameAddressIsTaken(true);
14603 EVT VT = Op.getValueType();
14604 SDLoc dl(Op); // FIXME probably not meaningful
14605 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14606 const X86RegisterInfo *RegInfo =
14607 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14608 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14609 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
14610 (FrameReg == X86::EBP && VT == MVT::i32)) &&
14611 "Invalid Frame Register!");
14612 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
14614 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
14615 MachinePointerInfo(),
14616 false, false, false, 0);
14620 // FIXME? Maybe this could be a TableGen attribute on some registers and
14621 // this table could be generated automatically from RegInfo.
14622 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
14624 unsigned Reg = StringSwitch<unsigned>(RegName)
14625 .Case("esp", X86::ESP)
14626 .Case("rsp", X86::RSP)
14630 report_fatal_error("Invalid register name global variable");
14633 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
14634 SelectionDAG &DAG) const {
14635 const X86RegisterInfo *RegInfo =
14636 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14637 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
14640 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
14641 SDValue Chain = Op.getOperand(0);
14642 SDValue Offset = Op.getOperand(1);
14643 SDValue Handler = Op.getOperand(2);
14646 EVT PtrVT = getPointerTy();
14647 const X86RegisterInfo *RegInfo =
14648 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14649 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14650 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
14651 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
14652 "Invalid Frame Register!");
14653 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
14654 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
14656 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
14657 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
14658 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
14659 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
14661 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
14663 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
14664 DAG.getRegister(StoreAddrReg, PtrVT));
14667 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
14668 SelectionDAG &DAG) const {
14670 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
14671 DAG.getVTList(MVT::i32, MVT::Other),
14672 Op.getOperand(0), Op.getOperand(1));
14675 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
14676 SelectionDAG &DAG) const {
14678 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
14679 Op.getOperand(0), Op.getOperand(1));
14682 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
14683 return Op.getOperand(0);
14686 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
14687 SelectionDAG &DAG) const {
14688 SDValue Root = Op.getOperand(0);
14689 SDValue Trmp = Op.getOperand(1); // trampoline
14690 SDValue FPtr = Op.getOperand(2); // nested function
14691 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
14694 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14695 const TargetRegisterInfo* TRI = DAG.getTarget().getRegisterInfo();
14697 if (Subtarget->is64Bit()) {
14698 SDValue OutChains[6];
14700 // Large code-model.
14701 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
14702 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
14704 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
14705 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
14707 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
14709 // Load the pointer to the nested function into R11.
14710 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
14711 SDValue Addr = Trmp;
14712 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14713 Addr, MachinePointerInfo(TrmpAddr),
14716 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14717 DAG.getConstant(2, MVT::i64));
14718 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
14719 MachinePointerInfo(TrmpAddr, 2),
14722 // Load the 'nest' parameter value into R10.
14723 // R10 is specified in X86CallingConv.td
14724 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
14725 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14726 DAG.getConstant(10, MVT::i64));
14727 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14728 Addr, MachinePointerInfo(TrmpAddr, 10),
14731 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14732 DAG.getConstant(12, MVT::i64));
14733 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
14734 MachinePointerInfo(TrmpAddr, 12),
14737 // Jump to the nested function.
14738 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
14739 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14740 DAG.getConstant(20, MVT::i64));
14741 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14742 Addr, MachinePointerInfo(TrmpAddr, 20),
14745 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
14746 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14747 DAG.getConstant(22, MVT::i64));
14748 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
14749 MachinePointerInfo(TrmpAddr, 22),
14752 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14754 const Function *Func =
14755 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
14756 CallingConv::ID CC = Func->getCallingConv();
14761 llvm_unreachable("Unsupported calling convention");
14762 case CallingConv::C:
14763 case CallingConv::X86_StdCall: {
14764 // Pass 'nest' parameter in ECX.
14765 // Must be kept in sync with X86CallingConv.td
14766 NestReg = X86::ECX;
14768 // Check that ECX wasn't needed by an 'inreg' parameter.
14769 FunctionType *FTy = Func->getFunctionType();
14770 const AttributeSet &Attrs = Func->getAttributes();
14772 if (!Attrs.isEmpty() && !Func->isVarArg()) {
14773 unsigned InRegCount = 0;
14776 for (FunctionType::param_iterator I = FTy->param_begin(),
14777 E = FTy->param_end(); I != E; ++I, ++Idx)
14778 if (Attrs.hasAttribute(Idx, Attribute::InReg))
14779 // FIXME: should only count parameters that are lowered to integers.
14780 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
14782 if (InRegCount > 2) {
14783 report_fatal_error("Nest register in use - reduce number of inreg"
14789 case CallingConv::X86_FastCall:
14790 case CallingConv::X86_ThisCall:
14791 case CallingConv::Fast:
14792 // Pass 'nest' parameter in EAX.
14793 // Must be kept in sync with X86CallingConv.td
14794 NestReg = X86::EAX;
14798 SDValue OutChains[4];
14799 SDValue Addr, Disp;
14801 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14802 DAG.getConstant(10, MVT::i32));
14803 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
14805 // This is storing the opcode for MOV32ri.
14806 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
14807 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
14808 OutChains[0] = DAG.getStore(Root, dl,
14809 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
14810 Trmp, MachinePointerInfo(TrmpAddr),
14813 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14814 DAG.getConstant(1, MVT::i32));
14815 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
14816 MachinePointerInfo(TrmpAddr, 1),
14819 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
14820 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14821 DAG.getConstant(5, MVT::i32));
14822 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
14823 MachinePointerInfo(TrmpAddr, 5),
14826 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14827 DAG.getConstant(6, MVT::i32));
14828 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
14829 MachinePointerInfo(TrmpAddr, 6),
14832 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14836 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
14837 SelectionDAG &DAG) const {
14839 The rounding mode is in bits 11:10 of FPSR, and has the following
14841 00 Round to nearest
14846 FLT_ROUNDS, on the other hand, expects the following:
14853 To perform the conversion, we do:
14854 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
14857 MachineFunction &MF = DAG.getMachineFunction();
14858 const TargetMachine &TM = MF.getTarget();
14859 const TargetFrameLowering &TFI = *TM.getFrameLowering();
14860 unsigned StackAlignment = TFI.getStackAlignment();
14861 MVT VT = Op.getSimpleValueType();
14864 // Save FP Control Word to stack slot
14865 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
14866 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14868 MachineMemOperand *MMO =
14869 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14870 MachineMemOperand::MOStore, 2, 2);
14872 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
14873 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
14874 DAG.getVTList(MVT::Other),
14875 Ops, MVT::i16, MMO);
14877 // Load FP Control Word from stack slot
14878 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
14879 MachinePointerInfo(), false, false, false, 0);
14881 // Transform as necessary
14883 DAG.getNode(ISD::SRL, DL, MVT::i16,
14884 DAG.getNode(ISD::AND, DL, MVT::i16,
14885 CWD, DAG.getConstant(0x800, MVT::i16)),
14886 DAG.getConstant(11, MVT::i8));
14888 DAG.getNode(ISD::SRL, DL, MVT::i16,
14889 DAG.getNode(ISD::AND, DL, MVT::i16,
14890 CWD, DAG.getConstant(0x400, MVT::i16)),
14891 DAG.getConstant(9, MVT::i8));
14894 DAG.getNode(ISD::AND, DL, MVT::i16,
14895 DAG.getNode(ISD::ADD, DL, MVT::i16,
14896 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
14897 DAG.getConstant(1, MVT::i16)),
14898 DAG.getConstant(3, MVT::i16));
14900 return DAG.getNode((VT.getSizeInBits() < 16 ?
14901 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
14904 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
14905 MVT VT = Op.getSimpleValueType();
14907 unsigned NumBits = VT.getSizeInBits();
14910 Op = Op.getOperand(0);
14911 if (VT == MVT::i8) {
14912 // Zero extend to i32 since there is not an i8 bsr.
14914 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14917 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
14918 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14919 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14921 // If src is zero (i.e. bsr sets ZF), returns NumBits.
14924 DAG.getConstant(NumBits+NumBits-1, OpVT),
14925 DAG.getConstant(X86::COND_E, MVT::i8),
14928 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
14930 // Finally xor with NumBits-1.
14931 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14934 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14938 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
14939 MVT VT = Op.getSimpleValueType();
14941 unsigned NumBits = VT.getSizeInBits();
14944 Op = Op.getOperand(0);
14945 if (VT == MVT::i8) {
14946 // Zero extend to i32 since there is not an i8 bsr.
14948 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14951 // Issue a bsr (scan bits in reverse).
14952 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14953 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14955 // And xor with NumBits-1.
14956 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14959 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14963 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
14964 MVT VT = Op.getSimpleValueType();
14965 unsigned NumBits = VT.getSizeInBits();
14967 Op = Op.getOperand(0);
14969 // Issue a bsf (scan bits forward) which also sets EFLAGS.
14970 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
14971 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
14973 // If src is zero (i.e. bsf sets ZF), returns NumBits.
14976 DAG.getConstant(NumBits, VT),
14977 DAG.getConstant(X86::COND_E, MVT::i8),
14980 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
14983 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
14984 // ones, and then concatenate the result back.
14985 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
14986 MVT VT = Op.getSimpleValueType();
14988 assert(VT.is256BitVector() && VT.isInteger() &&
14989 "Unsupported value type for operation");
14991 unsigned NumElems = VT.getVectorNumElements();
14994 // Extract the LHS vectors
14995 SDValue LHS = Op.getOperand(0);
14996 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14997 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14999 // Extract the RHS vectors
15000 SDValue RHS = Op.getOperand(1);
15001 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15002 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15004 MVT EltVT = VT.getVectorElementType();
15005 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15007 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15008 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15009 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15012 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15013 assert(Op.getSimpleValueType().is256BitVector() &&
15014 Op.getSimpleValueType().isInteger() &&
15015 "Only handle AVX 256-bit vector integer operation");
15016 return Lower256IntArith(Op, DAG);
15019 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15020 assert(Op.getSimpleValueType().is256BitVector() &&
15021 Op.getSimpleValueType().isInteger() &&
15022 "Only handle AVX 256-bit vector integer operation");
15023 return Lower256IntArith(Op, DAG);
15026 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15027 SelectionDAG &DAG) {
15029 MVT VT = Op.getSimpleValueType();
15031 // Decompose 256-bit ops into smaller 128-bit ops.
15032 if (VT.is256BitVector() && !Subtarget->hasInt256())
15033 return Lower256IntArith(Op, DAG);
15035 SDValue A = Op.getOperand(0);
15036 SDValue B = Op.getOperand(1);
15038 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15039 if (VT == MVT::v4i32) {
15040 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15041 "Should not custom lower when pmuldq is available!");
15043 // Extract the odd parts.
15044 static const int UnpackMask[] = { 1, -1, 3, -1 };
15045 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15046 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15048 // Multiply the even parts.
15049 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15050 // Now multiply odd parts.
15051 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15053 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15054 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15056 // Merge the two vectors back together with a shuffle. This expands into 2
15058 static const int ShufMask[] = { 0, 4, 2, 6 };
15059 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15062 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15063 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15065 // Ahi = psrlqi(a, 32);
15066 // Bhi = psrlqi(b, 32);
15068 // AloBlo = pmuludq(a, b);
15069 // AloBhi = pmuludq(a, Bhi);
15070 // AhiBlo = pmuludq(Ahi, b);
15072 // AloBhi = psllqi(AloBhi, 32);
15073 // AhiBlo = psllqi(AhiBlo, 32);
15074 // return AloBlo + AloBhi + AhiBlo;
15076 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15077 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15079 // Bit cast to 32-bit vectors for MULUDQ
15080 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15081 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15082 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15083 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15084 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15085 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15087 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15088 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15089 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15091 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15092 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15094 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15095 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15098 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15099 assert(Subtarget->isTargetWin64() && "Unexpected target");
15100 EVT VT = Op.getValueType();
15101 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15102 "Unexpected return type for lowering");
15106 switch (Op->getOpcode()) {
15107 default: llvm_unreachable("Unexpected request for libcall!");
15108 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15109 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15110 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15111 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15112 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15113 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15117 SDValue InChain = DAG.getEntryNode();
15119 TargetLowering::ArgListTy Args;
15120 TargetLowering::ArgListEntry Entry;
15121 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15122 EVT ArgVT = Op->getOperand(i).getValueType();
15123 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15124 "Unexpected argument type for lowering");
15125 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15126 Entry.Node = StackPtr;
15127 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15129 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15130 Entry.Ty = PointerType::get(ArgTy,0);
15131 Entry.isSExt = false;
15132 Entry.isZExt = false;
15133 Args.push_back(Entry);
15136 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15139 TargetLowering::CallLoweringInfo CLI(DAG);
15140 CLI.setDebugLoc(dl).setChain(InChain)
15141 .setCallee(getLibcallCallingConv(LC),
15142 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15143 Callee, std::move(Args), 0)
15144 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15146 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15147 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15150 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15151 SelectionDAG &DAG) {
15152 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15153 EVT VT = Op0.getValueType();
15156 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15157 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15159 // PMULxD operations multiply each even value (starting at 0) of LHS with
15160 // the related value of RHS and produce a widen result.
15161 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15162 // => <2 x i64> <ae|cg>
15164 // In other word, to have all the results, we need to perform two PMULxD:
15165 // 1. one with the even values.
15166 // 2. one with the odd values.
15167 // To achieve #2, with need to place the odd values at an even position.
15169 // Place the odd value at an even position (basically, shift all values 1
15170 // step to the left):
15171 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15172 // <a|b|c|d> => <b|undef|d|undef>
15173 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15174 // <e|f|g|h> => <f|undef|h|undef>
15175 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15177 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15179 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15180 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15182 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15183 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15184 // => <2 x i64> <ae|cg>
15185 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15186 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15187 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15188 // => <2 x i64> <bf|dh>
15189 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15190 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15192 // Shuffle it back into the right order.
15193 // The internal representation is big endian.
15194 // In other words, a i64 bitcasted to 2 x i32 has its high part at index 0
15195 // and its low part at index 1.
15196 // Moreover, we have: Mul1 = <ae|cg> ; Mul2 = <bf|dh>
15197 // Vector index 0 1 ; 2 3
15198 // We want <ae|bf|cg|dh>
15199 // Vector index 0 2 1 3
15200 // Since each element is seen as 2 x i32, we get:
15201 // high_mask[i] = 2 x vector_index[i]
15202 // low_mask[i] = 2 x vector_index[i] + 1
15203 // where vector_index = {0, Size/2, 1, Size/2 + 1, ...,
15204 // Size/2 - 1, Size/2 + Size/2 - 1}
15205 // where Size is the number of element of the final vector.
15206 SDValue Highs, Lows;
15207 if (VT == MVT::v8i32) {
15208 const int HighMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15209 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15210 const int LowMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15211 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15213 const int HighMask[] = {0, 4, 2, 6};
15214 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15215 const int LowMask[] = {1, 5, 3, 7};
15216 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15219 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15220 // unsigned multiply.
15221 if (IsSigned && !Subtarget->hasSSE41()) {
15223 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15224 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15225 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15226 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15227 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15229 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15230 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15233 // The low part of a MUL_LOHI is supposed to be the first value and the
15234 // high part the second value.
15235 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getValueType(), Lows, Highs);
15238 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15239 const X86Subtarget *Subtarget) {
15240 MVT VT = Op.getSimpleValueType();
15242 SDValue R = Op.getOperand(0);
15243 SDValue Amt = Op.getOperand(1);
15245 // Optimize shl/srl/sra with constant shift amount.
15246 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15247 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15248 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15250 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15251 (Subtarget->hasInt256() &&
15252 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15253 (Subtarget->hasAVX512() &&
15254 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15255 if (Op.getOpcode() == ISD::SHL)
15256 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15258 if (Op.getOpcode() == ISD::SRL)
15259 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15261 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15262 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15266 if (VT == MVT::v16i8) {
15267 if (Op.getOpcode() == ISD::SHL) {
15268 // Make a large shift.
15269 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15270 MVT::v8i16, R, ShiftAmt,
15272 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15273 // Zero out the rightmost bits.
15274 SmallVector<SDValue, 16> V(16,
15275 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15277 return DAG.getNode(ISD::AND, dl, VT, SHL,
15278 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15280 if (Op.getOpcode() == ISD::SRL) {
15281 // Make a large shift.
15282 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15283 MVT::v8i16, R, ShiftAmt,
15285 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15286 // Zero out the leftmost bits.
15287 SmallVector<SDValue, 16> V(16,
15288 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15290 return DAG.getNode(ISD::AND, dl, VT, SRL,
15291 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15293 if (Op.getOpcode() == ISD::SRA) {
15294 if (ShiftAmt == 7) {
15295 // R s>> 7 === R s< 0
15296 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15297 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15300 // R s>> a === ((R u>> a) ^ m) - m
15301 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15302 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15304 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15305 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15306 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15309 llvm_unreachable("Unknown shift opcode.");
15312 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15313 if (Op.getOpcode() == ISD::SHL) {
15314 // Make a large shift.
15315 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15316 MVT::v16i16, R, ShiftAmt,
15318 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15319 // Zero out the rightmost bits.
15320 SmallVector<SDValue, 32> V(32,
15321 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15323 return DAG.getNode(ISD::AND, dl, VT, SHL,
15324 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15326 if (Op.getOpcode() == ISD::SRL) {
15327 // Make a large shift.
15328 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15329 MVT::v16i16, R, ShiftAmt,
15331 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15332 // Zero out the leftmost bits.
15333 SmallVector<SDValue, 32> V(32,
15334 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15336 return DAG.getNode(ISD::AND, dl, VT, SRL,
15337 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15339 if (Op.getOpcode() == ISD::SRA) {
15340 if (ShiftAmt == 7) {
15341 // R s>> 7 === R s< 0
15342 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15343 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15346 // R s>> a === ((R u>> a) ^ m) - m
15347 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15348 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
15350 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15351 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15352 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15355 llvm_unreachable("Unknown shift opcode.");
15360 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15361 if (!Subtarget->is64Bit() &&
15362 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15363 Amt.getOpcode() == ISD::BITCAST &&
15364 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15365 Amt = Amt.getOperand(0);
15366 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15367 VT.getVectorNumElements();
15368 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15369 uint64_t ShiftAmt = 0;
15370 for (unsigned i = 0; i != Ratio; ++i) {
15371 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15375 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15377 // Check remaining shift amounts.
15378 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15379 uint64_t ShAmt = 0;
15380 for (unsigned j = 0; j != Ratio; ++j) {
15381 ConstantSDNode *C =
15382 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15386 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15388 if (ShAmt != ShiftAmt)
15391 switch (Op.getOpcode()) {
15393 llvm_unreachable("Unknown shift opcode!");
15395 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15398 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15401 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15409 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15410 const X86Subtarget* Subtarget) {
15411 MVT VT = Op.getSimpleValueType();
15413 SDValue R = Op.getOperand(0);
15414 SDValue Amt = Op.getOperand(1);
15416 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15417 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15418 (Subtarget->hasInt256() &&
15419 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15420 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15421 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15423 EVT EltVT = VT.getVectorElementType();
15425 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15426 unsigned NumElts = VT.getVectorNumElements();
15428 for (i = 0; i != NumElts; ++i) {
15429 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
15433 for (j = i; j != NumElts; ++j) {
15434 SDValue Arg = Amt.getOperand(j);
15435 if (Arg.getOpcode() == ISD::UNDEF) continue;
15436 if (Arg != Amt.getOperand(i))
15439 if (i != NumElts && j == NumElts)
15440 BaseShAmt = Amt.getOperand(i);
15442 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15443 Amt = Amt.getOperand(0);
15444 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
15445 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
15446 SDValue InVec = Amt.getOperand(0);
15447 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15448 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15450 for (; i != NumElts; ++i) {
15451 SDValue Arg = InVec.getOperand(i);
15452 if (Arg.getOpcode() == ISD::UNDEF) continue;
15456 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15457 if (ConstantSDNode *C =
15458 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15459 unsigned SplatIdx =
15460 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
15461 if (C->getZExtValue() == SplatIdx)
15462 BaseShAmt = InVec.getOperand(1);
15465 if (!BaseShAmt.getNode())
15466 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
15467 DAG.getIntPtrConstant(0));
15471 if (BaseShAmt.getNode()) {
15472 if (EltVT.bitsGT(MVT::i32))
15473 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
15474 else if (EltVT.bitsLT(MVT::i32))
15475 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15477 switch (Op.getOpcode()) {
15479 llvm_unreachable("Unknown shift opcode!");
15481 switch (VT.SimpleTy) {
15482 default: return SDValue();
15491 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15494 switch (VT.SimpleTy) {
15495 default: return SDValue();
15502 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
15505 switch (VT.SimpleTy) {
15506 default: return SDValue();
15515 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
15521 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15522 if (!Subtarget->is64Bit() &&
15523 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
15524 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
15525 Amt.getOpcode() == ISD::BITCAST &&
15526 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15527 Amt = Amt.getOperand(0);
15528 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15529 VT.getVectorNumElements();
15530 std::vector<SDValue> Vals(Ratio);
15531 for (unsigned i = 0; i != Ratio; ++i)
15532 Vals[i] = Amt.getOperand(i);
15533 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15534 for (unsigned j = 0; j != Ratio; ++j)
15535 if (Vals[j] != Amt.getOperand(i + j))
15538 switch (Op.getOpcode()) {
15540 llvm_unreachable("Unknown shift opcode!");
15542 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
15544 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
15546 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
15553 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
15554 SelectionDAG &DAG) {
15555 MVT VT = Op.getSimpleValueType();
15557 SDValue R = Op.getOperand(0);
15558 SDValue Amt = Op.getOperand(1);
15561 assert(VT.isVector() && "Custom lowering only for vector shifts!");
15562 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
15564 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
15568 V = LowerScalarVariableShift(Op, DAG, Subtarget);
15572 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
15574 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
15575 if (Subtarget->hasInt256()) {
15576 if (Op.getOpcode() == ISD::SRL &&
15577 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15578 VT == MVT::v4i64 || VT == MVT::v8i32))
15580 if (Op.getOpcode() == ISD::SHL &&
15581 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15582 VT == MVT::v4i64 || VT == MVT::v8i32))
15584 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
15588 // If possible, lower this packed shift into a vector multiply instead of
15589 // expanding it into a sequence of scalar shifts.
15590 // Do this only if the vector shift count is a constant build_vector.
15591 if (Op.getOpcode() == ISD::SHL &&
15592 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
15593 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
15594 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15595 SmallVector<SDValue, 8> Elts;
15596 EVT SVT = VT.getScalarType();
15597 unsigned SVTBits = SVT.getSizeInBits();
15598 const APInt &One = APInt(SVTBits, 1);
15599 unsigned NumElems = VT.getVectorNumElements();
15601 for (unsigned i=0; i !=NumElems; ++i) {
15602 SDValue Op = Amt->getOperand(i);
15603 if (Op->getOpcode() == ISD::UNDEF) {
15604 Elts.push_back(Op);
15608 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
15609 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
15610 uint64_t ShAmt = C.getZExtValue();
15611 if (ShAmt >= SVTBits) {
15612 Elts.push_back(DAG.getUNDEF(SVT));
15615 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
15617 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15618 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
15621 // Lower SHL with variable shift amount.
15622 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
15623 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
15625 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
15626 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
15627 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
15628 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
15631 // If possible, lower this shift as a sequence of two shifts by
15632 // constant plus a MOVSS/MOVSD instead of scalarizing it.
15634 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
15636 // Could be rewritten as:
15637 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
15639 // The advantage is that the two shifts from the example would be
15640 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
15641 // the vector shift into four scalar shifts plus four pairs of vector
15643 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
15644 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15645 unsigned TargetOpcode = X86ISD::MOVSS;
15646 bool CanBeSimplified;
15647 // The splat value for the first packed shift (the 'X' from the example).
15648 SDValue Amt1 = Amt->getOperand(0);
15649 // The splat value for the second packed shift (the 'Y' from the example).
15650 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
15651 Amt->getOperand(2);
15653 // See if it is possible to replace this node with a sequence of
15654 // two shifts followed by a MOVSS/MOVSD
15655 if (VT == MVT::v4i32) {
15656 // Check if it is legal to use a MOVSS.
15657 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
15658 Amt2 == Amt->getOperand(3);
15659 if (!CanBeSimplified) {
15660 // Otherwise, check if we can still simplify this node using a MOVSD.
15661 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
15662 Amt->getOperand(2) == Amt->getOperand(3);
15663 TargetOpcode = X86ISD::MOVSD;
15664 Amt2 = Amt->getOperand(2);
15667 // Do similar checks for the case where the machine value type
15669 CanBeSimplified = Amt1 == Amt->getOperand(1);
15670 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
15671 CanBeSimplified = Amt2 == Amt->getOperand(i);
15673 if (!CanBeSimplified) {
15674 TargetOpcode = X86ISD::MOVSD;
15675 CanBeSimplified = true;
15676 Amt2 = Amt->getOperand(4);
15677 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
15678 CanBeSimplified = Amt1 == Amt->getOperand(i);
15679 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
15680 CanBeSimplified = Amt2 == Amt->getOperand(j);
15684 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
15685 isa<ConstantSDNode>(Amt2)) {
15686 // Replace this node with two shifts followed by a MOVSS/MOVSD.
15687 EVT CastVT = MVT::v4i32;
15689 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
15690 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
15692 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
15693 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
15694 if (TargetOpcode == X86ISD::MOVSD)
15695 CastVT = MVT::v2i64;
15696 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
15697 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
15698 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
15700 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15704 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
15705 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
15708 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
15709 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
15711 // Turn 'a' into a mask suitable for VSELECT
15712 SDValue VSelM = DAG.getConstant(0x80, VT);
15713 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15714 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15716 SDValue CM1 = DAG.getConstant(0x0f, VT);
15717 SDValue CM2 = DAG.getConstant(0x3f, VT);
15719 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
15720 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
15721 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
15722 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15723 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15726 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15727 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15728 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15730 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
15731 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
15732 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
15733 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15734 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15737 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15738 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15739 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15741 // return VSELECT(r, r+r, a);
15742 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
15743 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
15747 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
15748 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
15749 // solution better.
15750 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
15751 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
15753 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
15754 R = DAG.getNode(ExtOpc, dl, NewVT, R);
15755 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
15756 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15757 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
15760 // Decompose 256-bit shifts into smaller 128-bit shifts.
15761 if (VT.is256BitVector()) {
15762 unsigned NumElems = VT.getVectorNumElements();
15763 MVT EltVT = VT.getVectorElementType();
15764 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15766 // Extract the two vectors
15767 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
15768 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
15770 // Recreate the shift amount vectors
15771 SDValue Amt1, Amt2;
15772 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15773 // Constant shift amount
15774 SmallVector<SDValue, 4> Amt1Csts;
15775 SmallVector<SDValue, 4> Amt2Csts;
15776 for (unsigned i = 0; i != NumElems/2; ++i)
15777 Amt1Csts.push_back(Amt->getOperand(i));
15778 for (unsigned i = NumElems/2; i != NumElems; ++i)
15779 Amt2Csts.push_back(Amt->getOperand(i));
15781 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
15782 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
15784 // Variable shift amount
15785 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
15786 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
15789 // Issue new vector shifts for the smaller types
15790 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
15791 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
15793 // Concatenate the result back
15794 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
15800 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
15801 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
15802 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
15803 // looks for this combo and may remove the "setcc" instruction if the "setcc"
15804 // has only one use.
15805 SDNode *N = Op.getNode();
15806 SDValue LHS = N->getOperand(0);
15807 SDValue RHS = N->getOperand(1);
15808 unsigned BaseOp = 0;
15811 switch (Op.getOpcode()) {
15812 default: llvm_unreachable("Unknown ovf instruction!");
15814 // A subtract of one will be selected as a INC. Note that INC doesn't
15815 // set CF, so we can't do this for UADDO.
15816 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15818 BaseOp = X86ISD::INC;
15819 Cond = X86::COND_O;
15822 BaseOp = X86ISD::ADD;
15823 Cond = X86::COND_O;
15826 BaseOp = X86ISD::ADD;
15827 Cond = X86::COND_B;
15830 // A subtract of one will be selected as a DEC. Note that DEC doesn't
15831 // set CF, so we can't do this for USUBO.
15832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15834 BaseOp = X86ISD::DEC;
15835 Cond = X86::COND_O;
15838 BaseOp = X86ISD::SUB;
15839 Cond = X86::COND_O;
15842 BaseOp = X86ISD::SUB;
15843 Cond = X86::COND_B;
15846 BaseOp = X86ISD::SMUL;
15847 Cond = X86::COND_O;
15849 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
15850 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
15852 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
15855 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15856 DAG.getConstant(X86::COND_O, MVT::i32),
15857 SDValue(Sum.getNode(), 2));
15859 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15863 // Also sets EFLAGS.
15864 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
15865 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
15868 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
15869 DAG.getConstant(Cond, MVT::i32),
15870 SDValue(Sum.getNode(), 1));
15872 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15875 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
15876 SelectionDAG &DAG) const {
15878 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
15879 MVT VT = Op.getSimpleValueType();
15881 if (!Subtarget->hasSSE2() || !VT.isVector())
15884 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
15885 ExtraVT.getScalarType().getSizeInBits();
15887 switch (VT.SimpleTy) {
15888 default: return SDValue();
15891 if (!Subtarget->hasFp256())
15893 if (!Subtarget->hasInt256()) {
15894 // needs to be split
15895 unsigned NumElems = VT.getVectorNumElements();
15897 // Extract the LHS vectors
15898 SDValue LHS = Op.getOperand(0);
15899 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15900 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15902 MVT EltVT = VT.getVectorElementType();
15903 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15905 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15906 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
15907 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
15909 SDValue Extra = DAG.getValueType(ExtraVT);
15911 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
15912 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
15914 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
15919 SDValue Op0 = Op.getOperand(0);
15920 SDValue Op00 = Op0.getOperand(0);
15922 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
15923 if (Op0.getOpcode() == ISD::BITCAST &&
15924 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
15925 // (sext (vzext x)) -> (vsext x)
15926 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
15927 if (Tmp1.getNode()) {
15928 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15929 // This folding is only valid when the in-reg type is a vector of i8,
15931 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
15932 ExtraEltVT == MVT::i32) {
15933 SDValue Tmp1Op0 = Tmp1.getOperand(0);
15934 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
15935 "This optimization is invalid without a VZEXT.");
15936 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
15942 // If the above didn't work, then just use Shift-Left + Shift-Right.
15943 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
15945 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
15951 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
15952 SelectionDAG &DAG) {
15954 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
15955 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
15956 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
15957 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
15959 // The only fence that needs an instruction is a sequentially-consistent
15960 // cross-thread fence.
15961 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
15962 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
15963 // no-sse2). There isn't any reason to disable it if the target processor
15965 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
15966 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
15968 SDValue Chain = Op.getOperand(0);
15969 SDValue Zero = DAG.getConstant(0, MVT::i32);
15971 DAG.getRegister(X86::ESP, MVT::i32), // Base
15972 DAG.getTargetConstant(1, MVT::i8), // Scale
15973 DAG.getRegister(0, MVT::i32), // Index
15974 DAG.getTargetConstant(0, MVT::i32), // Disp
15975 DAG.getRegister(0, MVT::i32), // Segment.
15979 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
15980 return SDValue(Res, 0);
15983 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
15984 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
15987 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
15988 SelectionDAG &DAG) {
15989 MVT T = Op.getSimpleValueType();
15993 switch(T.SimpleTy) {
15994 default: llvm_unreachable("Invalid value type!");
15995 case MVT::i8: Reg = X86::AL; size = 1; break;
15996 case MVT::i16: Reg = X86::AX; size = 2; break;
15997 case MVT::i32: Reg = X86::EAX; size = 4; break;
15999 assert(Subtarget->is64Bit() && "Node not type legal!");
16000 Reg = X86::RAX; size = 8;
16003 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16004 Op.getOperand(2), SDValue());
16005 SDValue Ops[] = { cpIn.getValue(0),
16008 DAG.getTargetConstant(size, MVT::i8),
16009 cpIn.getValue(1) };
16010 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16011 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16012 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16016 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16017 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16018 MVT::i32, cpOut.getValue(2));
16019 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16020 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16022 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16023 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16024 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16028 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16029 SelectionDAG &DAG) {
16030 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16031 MVT DstVT = Op.getSimpleValueType();
16033 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16034 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16035 if (DstVT != MVT::f64)
16036 // This conversion needs to be expanded.
16039 SDValue InVec = Op->getOperand(0);
16041 unsigned NumElts = SrcVT.getVectorNumElements();
16042 EVT SVT = SrcVT.getVectorElementType();
16044 // Widen the vector in input in the case of MVT::v2i32.
16045 // Example: from MVT::v2i32 to MVT::v4i32.
16046 SmallVector<SDValue, 16> Elts;
16047 for (unsigned i = 0, e = NumElts; i != e; ++i)
16048 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16049 DAG.getIntPtrConstant(i)));
16051 // Explicitly mark the extra elements as Undef.
16052 SDValue Undef = DAG.getUNDEF(SVT);
16053 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16054 Elts.push_back(Undef);
16056 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16057 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16058 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16059 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16060 DAG.getIntPtrConstant(0));
16063 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16064 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16065 assert((DstVT == MVT::i64 ||
16066 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16067 "Unexpected custom BITCAST");
16068 // i64 <=> MMX conversions are Legal.
16069 if (SrcVT==MVT::i64 && DstVT.isVector())
16071 if (DstVT==MVT::i64 && SrcVT.isVector())
16073 // MMX <=> MMX conversions are Legal.
16074 if (SrcVT.isVector() && DstVT.isVector())
16076 // All other conversions need to be expanded.
16080 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16081 SDNode *Node = Op.getNode();
16083 EVT T = Node->getValueType(0);
16084 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16085 DAG.getConstant(0, T), Node->getOperand(2));
16086 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16087 cast<AtomicSDNode>(Node)->getMemoryVT(),
16088 Node->getOperand(0),
16089 Node->getOperand(1), negOp,
16090 cast<AtomicSDNode>(Node)->getMemOperand(),
16091 cast<AtomicSDNode>(Node)->getOrdering(),
16092 cast<AtomicSDNode>(Node)->getSynchScope());
16095 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16096 SDNode *Node = Op.getNode();
16098 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16100 // Convert seq_cst store -> xchg
16101 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16102 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16103 // (The only way to get a 16-byte store is cmpxchg16b)
16104 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16105 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16106 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16107 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16108 cast<AtomicSDNode>(Node)->getMemoryVT(),
16109 Node->getOperand(0),
16110 Node->getOperand(1), Node->getOperand(2),
16111 cast<AtomicSDNode>(Node)->getMemOperand(),
16112 cast<AtomicSDNode>(Node)->getOrdering(),
16113 cast<AtomicSDNode>(Node)->getSynchScope());
16114 return Swap.getValue(1);
16116 // Other atomic stores have a simple pattern.
16120 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16121 EVT VT = Op.getNode()->getSimpleValueType(0);
16123 // Let legalize expand this if it isn't a legal type yet.
16124 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16127 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16130 bool ExtraOp = false;
16131 switch (Op.getOpcode()) {
16132 default: llvm_unreachable("Invalid code");
16133 case ISD::ADDC: Opc = X86ISD::ADD; break;
16134 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16135 case ISD::SUBC: Opc = X86ISD::SUB; break;
16136 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16140 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16142 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16143 Op.getOperand(1), Op.getOperand(2));
16146 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16147 SelectionDAG &DAG) {
16148 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16150 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16151 // which returns the values as { float, float } (in XMM0) or
16152 // { double, double } (which is returned in XMM0, XMM1).
16154 SDValue Arg = Op.getOperand(0);
16155 EVT ArgVT = Arg.getValueType();
16156 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16158 TargetLowering::ArgListTy Args;
16159 TargetLowering::ArgListEntry Entry;
16163 Entry.isSExt = false;
16164 Entry.isZExt = false;
16165 Args.push_back(Entry);
16167 bool isF64 = ArgVT == MVT::f64;
16168 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16169 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16170 // the results are returned via SRet in memory.
16171 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16173 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16175 Type *RetTy = isF64
16176 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16177 : (Type*)VectorType::get(ArgTy, 4);
16179 TargetLowering::CallLoweringInfo CLI(DAG);
16180 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16181 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16183 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16186 // Returned in xmm0 and xmm1.
16187 return CallResult.first;
16189 // Returned in bits 0:31 and 32:64 xmm0.
16190 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16191 CallResult.first, DAG.getIntPtrConstant(0));
16192 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16193 CallResult.first, DAG.getIntPtrConstant(1));
16194 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16195 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16198 /// LowerOperation - Provide custom lowering hooks for some operations.
16200 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16201 switch (Op.getOpcode()) {
16202 default: llvm_unreachable("Should not custom lower this!");
16203 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16204 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16205 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16206 return LowerCMP_SWAP(Op, Subtarget, DAG);
16207 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16208 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16209 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16210 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16211 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16212 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16213 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16214 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16215 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16216 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16217 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16218 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16219 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16220 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16221 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16222 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16223 case ISD::SHL_PARTS:
16224 case ISD::SRA_PARTS:
16225 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16226 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16227 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16228 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16229 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16230 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16231 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16232 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16233 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16234 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16235 case ISD::FABS: return LowerFABS(Op, DAG);
16236 case ISD::FNEG: return LowerFNEG(Op, DAG);
16237 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16238 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16239 case ISD::SETCC: return LowerSETCC(Op, DAG);
16240 case ISD::SELECT: return LowerSELECT(Op, DAG);
16241 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16242 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16243 case ISD::VASTART: return LowerVASTART(Op, DAG);
16244 case ISD::VAARG: return LowerVAARG(Op, DAG);
16245 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16246 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16247 case ISD::INTRINSIC_VOID:
16248 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16249 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16250 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16251 case ISD::FRAME_TO_ARGS_OFFSET:
16252 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16253 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16254 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16255 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16256 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16257 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16258 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16259 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16260 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16261 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16262 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16263 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16264 case ISD::UMUL_LOHI:
16265 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16268 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16274 case ISD::UMULO: return LowerXALUO(Op, DAG);
16275 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16276 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16280 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16281 case ISD::ADD: return LowerADD(Op, DAG);
16282 case ISD::SUB: return LowerSUB(Op, DAG);
16283 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16287 static void ReplaceATOMIC_LOAD(SDNode *Node,
16288 SmallVectorImpl<SDValue> &Results,
16289 SelectionDAG &DAG) {
16291 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16293 // Convert wide load -> cmpxchg8b/cmpxchg16b
16294 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16295 // (The only way to get a 16-byte load is cmpxchg16b)
16296 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16297 SDValue Zero = DAG.getConstant(0, VT);
16298 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16300 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16301 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16302 cast<AtomicSDNode>(Node)->getMemOperand(),
16303 cast<AtomicSDNode>(Node)->getOrdering(),
16304 cast<AtomicSDNode>(Node)->getOrdering(),
16305 cast<AtomicSDNode>(Node)->getSynchScope());
16306 Results.push_back(Swap.getValue(0));
16307 Results.push_back(Swap.getValue(2));
16310 /// ReplaceNodeResults - Replace a node with an illegal result type
16311 /// with a new node built out of custom code.
16312 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16313 SmallVectorImpl<SDValue>&Results,
16314 SelectionDAG &DAG) const {
16316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16317 switch (N->getOpcode()) {
16319 llvm_unreachable("Do not know how to custom type legalize this operation!");
16320 case ISD::SIGN_EXTEND_INREG:
16325 // We don't want to expand or promote these.
16332 case ISD::UDIVREM: {
16333 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16334 Results.push_back(V);
16337 case ISD::FP_TO_SINT:
16338 case ISD::FP_TO_UINT: {
16339 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16341 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16344 std::pair<SDValue,SDValue> Vals =
16345 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16346 SDValue FIST = Vals.first, StackSlot = Vals.second;
16347 if (FIST.getNode()) {
16348 EVT VT = N->getValueType(0);
16349 // Return a load from the stack slot.
16350 if (StackSlot.getNode())
16351 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16352 MachinePointerInfo(),
16353 false, false, false, 0));
16355 Results.push_back(FIST);
16359 case ISD::UINT_TO_FP: {
16360 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16361 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16362 N->getValueType(0) != MVT::v2f32)
16364 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16366 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16368 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16369 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16370 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16371 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16372 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16373 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16376 case ISD::FP_ROUND: {
16377 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16379 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16380 Results.push_back(V);
16383 case ISD::INTRINSIC_W_CHAIN: {
16384 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16386 default : llvm_unreachable("Do not know how to custom type "
16387 "legalize this intrinsic operation!");
16388 case Intrinsic::x86_rdtsc:
16389 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16391 case Intrinsic::x86_rdtscp:
16392 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16394 case Intrinsic::x86_rdpmc:
16395 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16398 case ISD::READCYCLECOUNTER: {
16399 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16402 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16403 EVT T = N->getValueType(0);
16404 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16405 bool Regs64bit = T == MVT::i128;
16406 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16407 SDValue cpInL, cpInH;
16408 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16409 DAG.getConstant(0, HalfT));
16410 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16411 DAG.getConstant(1, HalfT));
16412 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16413 Regs64bit ? X86::RAX : X86::EAX,
16415 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16416 Regs64bit ? X86::RDX : X86::EDX,
16417 cpInH, cpInL.getValue(1));
16418 SDValue swapInL, swapInH;
16419 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16420 DAG.getConstant(0, HalfT));
16421 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16422 DAG.getConstant(1, HalfT));
16423 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16424 Regs64bit ? X86::RBX : X86::EBX,
16425 swapInL, cpInH.getValue(1));
16426 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16427 Regs64bit ? X86::RCX : X86::ECX,
16428 swapInH, swapInL.getValue(1));
16429 SDValue Ops[] = { swapInH.getValue(0),
16431 swapInH.getValue(1) };
16432 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16433 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16434 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16435 X86ISD::LCMPXCHG8_DAG;
16436 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16437 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16438 Regs64bit ? X86::RAX : X86::EAX,
16439 HalfT, Result.getValue(1));
16440 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16441 Regs64bit ? X86::RDX : X86::EDX,
16442 HalfT, cpOutL.getValue(2));
16443 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16445 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16446 MVT::i32, cpOutH.getValue(2));
16448 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16449 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16450 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
16452 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
16453 Results.push_back(Success);
16454 Results.push_back(EFLAGS.getValue(1));
16457 case ISD::ATOMIC_SWAP:
16458 case ISD::ATOMIC_LOAD_ADD:
16459 case ISD::ATOMIC_LOAD_SUB:
16460 case ISD::ATOMIC_LOAD_AND:
16461 case ISD::ATOMIC_LOAD_OR:
16462 case ISD::ATOMIC_LOAD_XOR:
16463 case ISD::ATOMIC_LOAD_NAND:
16464 case ISD::ATOMIC_LOAD_MIN:
16465 case ISD::ATOMIC_LOAD_MAX:
16466 case ISD::ATOMIC_LOAD_UMIN:
16467 case ISD::ATOMIC_LOAD_UMAX:
16468 // Delegate to generic TypeLegalization. Situations we can really handle
16469 // should have already been dealt with by X86AtomicExpand.cpp.
16471 case ISD::ATOMIC_LOAD: {
16472 ReplaceATOMIC_LOAD(N, Results, DAG);
16475 case ISD::BITCAST: {
16476 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16477 EVT DstVT = N->getValueType(0);
16478 EVT SrcVT = N->getOperand(0)->getValueType(0);
16480 if (SrcVT != MVT::f64 ||
16481 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
16484 unsigned NumElts = DstVT.getVectorNumElements();
16485 EVT SVT = DstVT.getVectorElementType();
16486 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16487 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
16488 MVT::v2f64, N->getOperand(0));
16489 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
16491 if (ExperimentalVectorWideningLegalization) {
16492 // If we are legalizing vectors by widening, we already have the desired
16493 // legal vector type, just return it.
16494 Results.push_back(ToVecInt);
16498 SmallVector<SDValue, 8> Elts;
16499 for (unsigned i = 0, e = NumElts; i != e; ++i)
16500 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
16501 ToVecInt, DAG.getIntPtrConstant(i)));
16503 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
16508 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
16510 default: return nullptr;
16511 case X86ISD::BSF: return "X86ISD::BSF";
16512 case X86ISD::BSR: return "X86ISD::BSR";
16513 case X86ISD::SHLD: return "X86ISD::SHLD";
16514 case X86ISD::SHRD: return "X86ISD::SHRD";
16515 case X86ISD::FAND: return "X86ISD::FAND";
16516 case X86ISD::FANDN: return "X86ISD::FANDN";
16517 case X86ISD::FOR: return "X86ISD::FOR";
16518 case X86ISD::FXOR: return "X86ISD::FXOR";
16519 case X86ISD::FSRL: return "X86ISD::FSRL";
16520 case X86ISD::FILD: return "X86ISD::FILD";
16521 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
16522 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
16523 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
16524 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
16525 case X86ISD::FLD: return "X86ISD::FLD";
16526 case X86ISD::FST: return "X86ISD::FST";
16527 case X86ISD::CALL: return "X86ISD::CALL";
16528 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
16529 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
16530 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
16531 case X86ISD::BT: return "X86ISD::BT";
16532 case X86ISD::CMP: return "X86ISD::CMP";
16533 case X86ISD::COMI: return "X86ISD::COMI";
16534 case X86ISD::UCOMI: return "X86ISD::UCOMI";
16535 case X86ISD::CMPM: return "X86ISD::CMPM";
16536 case X86ISD::CMPMU: return "X86ISD::CMPMU";
16537 case X86ISD::SETCC: return "X86ISD::SETCC";
16538 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
16539 case X86ISD::FSETCC: return "X86ISD::FSETCC";
16540 case X86ISD::CMOV: return "X86ISD::CMOV";
16541 case X86ISD::BRCOND: return "X86ISD::BRCOND";
16542 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
16543 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
16544 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
16545 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
16546 case X86ISD::Wrapper: return "X86ISD::Wrapper";
16547 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
16548 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
16549 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
16550 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
16551 case X86ISD::PINSRB: return "X86ISD::PINSRB";
16552 case X86ISD::PINSRW: return "X86ISD::PINSRW";
16553 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
16554 case X86ISD::ANDNP: return "X86ISD::ANDNP";
16555 case X86ISD::PSIGN: return "X86ISD::PSIGN";
16556 case X86ISD::BLENDV: return "X86ISD::BLENDV";
16557 case X86ISD::BLENDI: return "X86ISD::BLENDI";
16558 case X86ISD::SUBUS: return "X86ISD::SUBUS";
16559 case X86ISD::HADD: return "X86ISD::HADD";
16560 case X86ISD::HSUB: return "X86ISD::HSUB";
16561 case X86ISD::FHADD: return "X86ISD::FHADD";
16562 case X86ISD::FHSUB: return "X86ISD::FHSUB";
16563 case X86ISD::UMAX: return "X86ISD::UMAX";
16564 case X86ISD::UMIN: return "X86ISD::UMIN";
16565 case X86ISD::SMAX: return "X86ISD::SMAX";
16566 case X86ISD::SMIN: return "X86ISD::SMIN";
16567 case X86ISD::FMAX: return "X86ISD::FMAX";
16568 case X86ISD::FMIN: return "X86ISD::FMIN";
16569 case X86ISD::FMAXC: return "X86ISD::FMAXC";
16570 case X86ISD::FMINC: return "X86ISD::FMINC";
16571 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
16572 case X86ISD::FRCP: return "X86ISD::FRCP";
16573 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
16574 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
16575 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
16576 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
16577 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
16578 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
16579 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
16580 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
16581 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
16582 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
16583 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
16584 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
16585 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
16586 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
16587 case X86ISD::VZEXT: return "X86ISD::VZEXT";
16588 case X86ISD::VSEXT: return "X86ISD::VSEXT";
16589 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
16590 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
16591 case X86ISD::VINSERT: return "X86ISD::VINSERT";
16592 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
16593 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
16594 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
16595 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
16596 case X86ISD::VSHL: return "X86ISD::VSHL";
16597 case X86ISD::VSRL: return "X86ISD::VSRL";
16598 case X86ISD::VSRA: return "X86ISD::VSRA";
16599 case X86ISD::VSHLI: return "X86ISD::VSHLI";
16600 case X86ISD::VSRLI: return "X86ISD::VSRLI";
16601 case X86ISD::VSRAI: return "X86ISD::VSRAI";
16602 case X86ISD::CMPP: return "X86ISD::CMPP";
16603 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
16604 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
16605 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
16606 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
16607 case X86ISD::ADD: return "X86ISD::ADD";
16608 case X86ISD::SUB: return "X86ISD::SUB";
16609 case X86ISD::ADC: return "X86ISD::ADC";
16610 case X86ISD::SBB: return "X86ISD::SBB";
16611 case X86ISD::SMUL: return "X86ISD::SMUL";
16612 case X86ISD::UMUL: return "X86ISD::UMUL";
16613 case X86ISD::INC: return "X86ISD::INC";
16614 case X86ISD::DEC: return "X86ISD::DEC";
16615 case X86ISD::OR: return "X86ISD::OR";
16616 case X86ISD::XOR: return "X86ISD::XOR";
16617 case X86ISD::AND: return "X86ISD::AND";
16618 case X86ISD::BEXTR: return "X86ISD::BEXTR";
16619 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
16620 case X86ISD::PTEST: return "X86ISD::PTEST";
16621 case X86ISD::TESTP: return "X86ISD::TESTP";
16622 case X86ISD::TESTM: return "X86ISD::TESTM";
16623 case X86ISD::TESTNM: return "X86ISD::TESTNM";
16624 case X86ISD::KORTEST: return "X86ISD::KORTEST";
16625 case X86ISD::PACKSS: return "X86ISD::PACKSS";
16626 case X86ISD::PACKUS: return "X86ISD::PACKUS";
16627 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
16628 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
16629 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
16630 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
16631 case X86ISD::SHUFP: return "X86ISD::SHUFP";
16632 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
16633 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
16634 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
16635 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
16636 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
16637 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
16638 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
16639 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
16640 case X86ISD::MOVSD: return "X86ISD::MOVSD";
16641 case X86ISD::MOVSS: return "X86ISD::MOVSS";
16642 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
16643 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
16644 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
16645 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
16646 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
16647 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
16648 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
16649 case X86ISD::VPERMV: return "X86ISD::VPERMV";
16650 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
16651 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
16652 case X86ISD::VPERMI: return "X86ISD::VPERMI";
16653 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
16654 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
16655 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
16656 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
16657 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
16658 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
16659 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
16660 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
16661 case X86ISD::SAHF: return "X86ISD::SAHF";
16662 case X86ISD::RDRAND: return "X86ISD::RDRAND";
16663 case X86ISD::RDSEED: return "X86ISD::RDSEED";
16664 case X86ISD::FMADD: return "X86ISD::FMADD";
16665 case X86ISD::FMSUB: return "X86ISD::FMSUB";
16666 case X86ISD::FNMADD: return "X86ISD::FNMADD";
16667 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
16668 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
16669 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
16670 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
16671 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
16672 case X86ISD::XTEST: return "X86ISD::XTEST";
16676 // isLegalAddressingMode - Return true if the addressing mode represented
16677 // by AM is legal for this target, for a load/store of the specified type.
16678 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
16680 // X86 supports extremely general addressing modes.
16681 CodeModel::Model M = getTargetMachine().getCodeModel();
16682 Reloc::Model R = getTargetMachine().getRelocationModel();
16684 // X86 allows a sign-extended 32-bit immediate field as a displacement.
16685 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
16690 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
16692 // If a reference to this global requires an extra load, we can't fold it.
16693 if (isGlobalStubReference(GVFlags))
16696 // If BaseGV requires a register for the PIC base, we cannot also have a
16697 // BaseReg specified.
16698 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
16701 // If lower 4G is not available, then we must use rip-relative addressing.
16702 if ((M != CodeModel::Small || R != Reloc::Static) &&
16703 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
16707 switch (AM.Scale) {
16713 // These scales always work.
16718 // These scales are formed with basereg+scalereg. Only accept if there is
16723 default: // Other stuff never works.
16730 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
16731 unsigned Bits = Ty->getScalarSizeInBits();
16733 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
16734 // particularly cheaper than those without.
16738 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
16739 // variable shifts just as cheap as scalar ones.
16740 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
16743 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
16744 // fully general vector.
16748 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
16749 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16751 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
16752 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
16753 return NumBits1 > NumBits2;
16756 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
16757 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16760 if (!isTypeLegal(EVT::getEVT(Ty1)))
16763 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
16765 // Assuming the caller doesn't have a zeroext or signext return parameter,
16766 // truncation all the way down to i1 is valid.
16770 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
16771 return isInt<32>(Imm);
16774 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
16775 // Can also use sub to handle negated immediates.
16776 return isInt<32>(Imm);
16779 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
16780 if (!VT1.isInteger() || !VT2.isInteger())
16782 unsigned NumBits1 = VT1.getSizeInBits();
16783 unsigned NumBits2 = VT2.getSizeInBits();
16784 return NumBits1 > NumBits2;
16787 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
16788 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16789 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
16792 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
16793 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16794 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
16797 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
16798 EVT VT1 = Val.getValueType();
16799 if (isZExtFree(VT1, VT2))
16802 if (Val.getOpcode() != ISD::LOAD)
16805 if (!VT1.isSimple() || !VT1.isInteger() ||
16806 !VT2.isSimple() || !VT2.isInteger())
16809 switch (VT1.getSimpleVT().SimpleTy) {
16814 // X86 has 8, 16, and 32-bit zero-extending loads.
16822 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
16823 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
16826 VT = VT.getScalarType();
16828 if (!VT.isSimple())
16831 switch (VT.getSimpleVT().SimpleTy) {
16842 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
16843 // i16 instructions are longer (0x66 prefix) and potentially slower.
16844 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
16847 /// isShuffleMaskLegal - Targets can use this to indicate that they only
16848 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
16849 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
16850 /// are assumed to be legal.
16852 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
16854 if (!VT.isSimple())
16857 MVT SVT = VT.getSimpleVT();
16859 // Very little shuffling can be done for 64-bit vectors right now.
16860 if (VT.getSizeInBits() == 64)
16863 // If this is a single-input shuffle with no 128 bit lane crossings we can
16864 // lower it into pshufb.
16865 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
16866 (SVT.is256BitVector() && Subtarget->hasInt256())) {
16867 bool isLegal = true;
16868 for (unsigned I = 0, E = M.size(); I != E; ++I) {
16869 if (M[I] >= (int)SVT.getVectorNumElements() ||
16870 ShuffleCrosses128bitLane(SVT, I, M[I])) {
16879 // FIXME: blends, shifts.
16880 return (SVT.getVectorNumElements() == 2 ||
16881 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
16882 isMOVLMask(M, SVT) ||
16883 isSHUFPMask(M, SVT) ||
16884 isPSHUFDMask(M, SVT) ||
16885 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
16886 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
16887 isPALIGNRMask(M, SVT, Subtarget) ||
16888 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
16889 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
16890 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16891 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16892 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
16896 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
16898 if (!VT.isSimple())
16901 MVT SVT = VT.getSimpleVT();
16902 unsigned NumElts = SVT.getVectorNumElements();
16903 // FIXME: This collection of masks seems suspect.
16906 if (NumElts == 4 && SVT.is128BitVector()) {
16907 return (isMOVLMask(Mask, SVT) ||
16908 isCommutedMOVLMask(Mask, SVT, true) ||
16909 isSHUFPMask(Mask, SVT) ||
16910 isSHUFPMask(Mask, SVT, /* Commuted */ true));
16915 //===----------------------------------------------------------------------===//
16916 // X86 Scheduler Hooks
16917 //===----------------------------------------------------------------------===//
16919 /// Utility function to emit xbegin specifying the start of an RTM region.
16920 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
16921 const TargetInstrInfo *TII) {
16922 DebugLoc DL = MI->getDebugLoc();
16924 const BasicBlock *BB = MBB->getBasicBlock();
16925 MachineFunction::iterator I = MBB;
16928 // For the v = xbegin(), we generate
16939 MachineBasicBlock *thisMBB = MBB;
16940 MachineFunction *MF = MBB->getParent();
16941 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
16942 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
16943 MF->insert(I, mainMBB);
16944 MF->insert(I, sinkMBB);
16946 // Transfer the remainder of BB and its successor edges to sinkMBB.
16947 sinkMBB->splice(sinkMBB->begin(), MBB,
16948 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16949 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
16953 // # fallthrough to mainMBB
16954 // # abortion to sinkMBB
16955 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
16956 thisMBB->addSuccessor(mainMBB);
16957 thisMBB->addSuccessor(sinkMBB);
16961 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
16962 mainMBB->addSuccessor(sinkMBB);
16965 // EAX is live into the sinkMBB
16966 sinkMBB->addLiveIn(X86::EAX);
16967 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16968 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16971 MI->eraseFromParent();
16975 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
16976 // or XMM0_V32I8 in AVX all of this code can be replaced with that
16977 // in the .td file.
16978 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
16979 const TargetInstrInfo *TII) {
16981 switch (MI->getOpcode()) {
16982 default: llvm_unreachable("illegal opcode!");
16983 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
16984 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
16985 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
16986 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
16987 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
16988 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
16989 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
16990 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
16993 DebugLoc dl = MI->getDebugLoc();
16994 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
16996 unsigned NumArgs = MI->getNumOperands();
16997 for (unsigned i = 1; i < NumArgs; ++i) {
16998 MachineOperand &Op = MI->getOperand(i);
16999 if (!(Op.isReg() && Op.isImplicit()))
17000 MIB.addOperand(Op);
17002 if (MI->hasOneMemOperand())
17003 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17005 BuildMI(*BB, MI, dl,
17006 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17007 .addReg(X86::XMM0);
17009 MI->eraseFromParent();
17013 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17014 // defs in an instruction pattern
17015 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17016 const TargetInstrInfo *TII) {
17018 switch (MI->getOpcode()) {
17019 default: llvm_unreachable("illegal opcode!");
17020 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17021 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17022 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17023 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17024 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17025 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17026 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17027 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17030 DebugLoc dl = MI->getDebugLoc();
17031 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17033 unsigned NumArgs = MI->getNumOperands(); // remove the results
17034 for (unsigned i = 1; i < NumArgs; ++i) {
17035 MachineOperand &Op = MI->getOperand(i);
17036 if (!(Op.isReg() && Op.isImplicit()))
17037 MIB.addOperand(Op);
17039 if (MI->hasOneMemOperand())
17040 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17042 BuildMI(*BB, MI, dl,
17043 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17046 MI->eraseFromParent();
17050 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17051 const TargetInstrInfo *TII,
17052 const X86Subtarget* Subtarget) {
17053 DebugLoc dl = MI->getDebugLoc();
17055 // Address into RAX/EAX, other two args into ECX, EDX.
17056 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17057 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17058 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17059 for (int i = 0; i < X86::AddrNumOperands; ++i)
17060 MIB.addOperand(MI->getOperand(i));
17062 unsigned ValOps = X86::AddrNumOperands;
17063 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17064 .addReg(MI->getOperand(ValOps).getReg());
17065 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17066 .addReg(MI->getOperand(ValOps+1).getReg());
17068 // The instruction doesn't actually take any operands though.
17069 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17071 MI->eraseFromParent(); // The pseudo is gone now.
17075 MachineBasicBlock *
17076 X86TargetLowering::EmitVAARG64WithCustomInserter(
17078 MachineBasicBlock *MBB) const {
17079 // Emit va_arg instruction on X86-64.
17081 // Operands to this pseudo-instruction:
17082 // 0 ) Output : destination address (reg)
17083 // 1-5) Input : va_list address (addr, i64mem)
17084 // 6 ) ArgSize : Size (in bytes) of vararg type
17085 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17086 // 8 ) Align : Alignment of type
17087 // 9 ) EFLAGS (implicit-def)
17089 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17090 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17092 unsigned DestReg = MI->getOperand(0).getReg();
17093 MachineOperand &Base = MI->getOperand(1);
17094 MachineOperand &Scale = MI->getOperand(2);
17095 MachineOperand &Index = MI->getOperand(3);
17096 MachineOperand &Disp = MI->getOperand(4);
17097 MachineOperand &Segment = MI->getOperand(5);
17098 unsigned ArgSize = MI->getOperand(6).getImm();
17099 unsigned ArgMode = MI->getOperand(7).getImm();
17100 unsigned Align = MI->getOperand(8).getImm();
17102 // Memory Reference
17103 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17104 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17105 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17107 // Machine Information
17108 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17109 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17110 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17111 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17112 DebugLoc DL = MI->getDebugLoc();
17114 // struct va_list {
17117 // i64 overflow_area (address)
17118 // i64 reg_save_area (address)
17120 // sizeof(va_list) = 24
17121 // alignment(va_list) = 8
17123 unsigned TotalNumIntRegs = 6;
17124 unsigned TotalNumXMMRegs = 8;
17125 bool UseGPOffset = (ArgMode == 1);
17126 bool UseFPOffset = (ArgMode == 2);
17127 unsigned MaxOffset = TotalNumIntRegs * 8 +
17128 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17130 /* Align ArgSize to a multiple of 8 */
17131 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17132 bool NeedsAlign = (Align > 8);
17134 MachineBasicBlock *thisMBB = MBB;
17135 MachineBasicBlock *overflowMBB;
17136 MachineBasicBlock *offsetMBB;
17137 MachineBasicBlock *endMBB;
17139 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17140 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17141 unsigned OffsetReg = 0;
17143 if (!UseGPOffset && !UseFPOffset) {
17144 // If we only pull from the overflow region, we don't create a branch.
17145 // We don't need to alter control flow.
17146 OffsetDestReg = 0; // unused
17147 OverflowDestReg = DestReg;
17149 offsetMBB = nullptr;
17150 overflowMBB = thisMBB;
17153 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17154 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17155 // If not, pull from overflow_area. (branch to overflowMBB)
17160 // offsetMBB overflowMBB
17165 // Registers for the PHI in endMBB
17166 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17167 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17169 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17170 MachineFunction *MF = MBB->getParent();
17171 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17172 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17173 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17175 MachineFunction::iterator MBBIter = MBB;
17178 // Insert the new basic blocks
17179 MF->insert(MBBIter, offsetMBB);
17180 MF->insert(MBBIter, overflowMBB);
17181 MF->insert(MBBIter, endMBB);
17183 // Transfer the remainder of MBB and its successor edges to endMBB.
17184 endMBB->splice(endMBB->begin(), thisMBB,
17185 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17186 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17188 // Make offsetMBB and overflowMBB successors of thisMBB
17189 thisMBB->addSuccessor(offsetMBB);
17190 thisMBB->addSuccessor(overflowMBB);
17192 // endMBB is a successor of both offsetMBB and overflowMBB
17193 offsetMBB->addSuccessor(endMBB);
17194 overflowMBB->addSuccessor(endMBB);
17196 // Load the offset value into a register
17197 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17198 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17202 .addDisp(Disp, UseFPOffset ? 4 : 0)
17203 .addOperand(Segment)
17204 .setMemRefs(MMOBegin, MMOEnd);
17206 // Check if there is enough room left to pull this argument.
17207 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17209 .addImm(MaxOffset + 8 - ArgSizeA8);
17211 // Branch to "overflowMBB" if offset >= max
17212 // Fall through to "offsetMBB" otherwise
17213 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17214 .addMBB(overflowMBB);
17217 // In offsetMBB, emit code to use the reg_save_area.
17219 assert(OffsetReg != 0);
17221 // Read the reg_save_area address.
17222 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17223 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17228 .addOperand(Segment)
17229 .setMemRefs(MMOBegin, MMOEnd);
17231 // Zero-extend the offset
17232 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17233 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17236 .addImm(X86::sub_32bit);
17238 // Add the offset to the reg_save_area to get the final address.
17239 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17240 .addReg(OffsetReg64)
17241 .addReg(RegSaveReg);
17243 // Compute the offset for the next argument
17244 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17245 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17247 .addImm(UseFPOffset ? 16 : 8);
17249 // Store it back into the va_list.
17250 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17254 .addDisp(Disp, UseFPOffset ? 4 : 0)
17255 .addOperand(Segment)
17256 .addReg(NextOffsetReg)
17257 .setMemRefs(MMOBegin, MMOEnd);
17260 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17265 // Emit code to use overflow area
17268 // Load the overflow_area address into a register.
17269 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17270 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17275 .addOperand(Segment)
17276 .setMemRefs(MMOBegin, MMOEnd);
17278 // If we need to align it, do so. Otherwise, just copy the address
17279 // to OverflowDestReg.
17281 // Align the overflow address
17282 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17283 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17285 // aligned_addr = (addr + (align-1)) & ~(align-1)
17286 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17287 .addReg(OverflowAddrReg)
17290 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17292 .addImm(~(uint64_t)(Align-1));
17294 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17295 .addReg(OverflowAddrReg);
17298 // Compute the next overflow address after this argument.
17299 // (the overflow address should be kept 8-byte aligned)
17300 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17301 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17302 .addReg(OverflowDestReg)
17303 .addImm(ArgSizeA8);
17305 // Store the new overflow address.
17306 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17311 .addOperand(Segment)
17312 .addReg(NextAddrReg)
17313 .setMemRefs(MMOBegin, MMOEnd);
17315 // If we branched, emit the PHI to the front of endMBB.
17317 BuildMI(*endMBB, endMBB->begin(), DL,
17318 TII->get(X86::PHI), DestReg)
17319 .addReg(OffsetDestReg).addMBB(offsetMBB)
17320 .addReg(OverflowDestReg).addMBB(overflowMBB);
17323 // Erase the pseudo instruction
17324 MI->eraseFromParent();
17329 MachineBasicBlock *
17330 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17332 MachineBasicBlock *MBB) const {
17333 // Emit code to save XMM registers to the stack. The ABI says that the
17334 // number of registers to save is given in %al, so it's theoretically
17335 // possible to do an indirect jump trick to avoid saving all of them,
17336 // however this code takes a simpler approach and just executes all
17337 // of the stores if %al is non-zero. It's less code, and it's probably
17338 // easier on the hardware branch predictor, and stores aren't all that
17339 // expensive anyway.
17341 // Create the new basic blocks. One block contains all the XMM stores,
17342 // and one block is the final destination regardless of whether any
17343 // stores were performed.
17344 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17345 MachineFunction *F = MBB->getParent();
17346 MachineFunction::iterator MBBIter = MBB;
17348 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17349 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17350 F->insert(MBBIter, XMMSaveMBB);
17351 F->insert(MBBIter, EndMBB);
17353 // Transfer the remainder of MBB and its successor edges to EndMBB.
17354 EndMBB->splice(EndMBB->begin(), MBB,
17355 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17356 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17358 // The original block will now fall through to the XMM save block.
17359 MBB->addSuccessor(XMMSaveMBB);
17360 // The XMMSaveMBB will fall through to the end block.
17361 XMMSaveMBB->addSuccessor(EndMBB);
17363 // Now add the instructions.
17364 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17365 DebugLoc DL = MI->getDebugLoc();
17367 unsigned CountReg = MI->getOperand(0).getReg();
17368 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17369 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17371 if (!Subtarget->isTargetWin64()) {
17372 // If %al is 0, branch around the XMM save block.
17373 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17374 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17375 MBB->addSuccessor(EndMBB);
17378 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17379 // that was just emitted, but clearly shouldn't be "saved".
17380 assert((MI->getNumOperands() <= 3 ||
17381 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17382 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17383 && "Expected last argument to be EFLAGS");
17384 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17385 // In the XMM save block, save all the XMM argument registers.
17386 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17387 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17388 MachineMemOperand *MMO =
17389 F->getMachineMemOperand(
17390 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17391 MachineMemOperand::MOStore,
17392 /*Size=*/16, /*Align=*/16);
17393 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17394 .addFrameIndex(RegSaveFrameIndex)
17395 .addImm(/*Scale=*/1)
17396 .addReg(/*IndexReg=*/0)
17397 .addImm(/*Disp=*/Offset)
17398 .addReg(/*Segment=*/0)
17399 .addReg(MI->getOperand(i).getReg())
17400 .addMemOperand(MMO);
17403 MI->eraseFromParent(); // The pseudo instruction is gone now.
17408 // The EFLAGS operand of SelectItr might be missing a kill marker
17409 // because there were multiple uses of EFLAGS, and ISel didn't know
17410 // which to mark. Figure out whether SelectItr should have had a
17411 // kill marker, and set it if it should. Returns the correct kill
17413 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
17414 MachineBasicBlock* BB,
17415 const TargetRegisterInfo* TRI) {
17416 // Scan forward through BB for a use/def of EFLAGS.
17417 MachineBasicBlock::iterator miI(std::next(SelectItr));
17418 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
17419 const MachineInstr& mi = *miI;
17420 if (mi.readsRegister(X86::EFLAGS))
17422 if (mi.definesRegister(X86::EFLAGS))
17423 break; // Should have kill-flag - update below.
17426 // If we hit the end of the block, check whether EFLAGS is live into a
17428 if (miI == BB->end()) {
17429 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
17430 sEnd = BB->succ_end();
17431 sItr != sEnd; ++sItr) {
17432 MachineBasicBlock* succ = *sItr;
17433 if (succ->isLiveIn(X86::EFLAGS))
17438 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
17439 // out. SelectMI should have a kill flag on EFLAGS.
17440 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
17444 MachineBasicBlock *
17445 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
17446 MachineBasicBlock *BB) const {
17447 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17448 DebugLoc DL = MI->getDebugLoc();
17450 // To "insert" a SELECT_CC instruction, we actually have to insert the
17451 // diamond control-flow pattern. The incoming instruction knows the
17452 // destination vreg to set, the condition code register to branch on, the
17453 // true/false values to select between, and a branch opcode to use.
17454 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17455 MachineFunction::iterator It = BB;
17461 // cmpTY ccX, r1, r2
17463 // fallthrough --> copy0MBB
17464 MachineBasicBlock *thisMBB = BB;
17465 MachineFunction *F = BB->getParent();
17466 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
17467 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
17468 F->insert(It, copy0MBB);
17469 F->insert(It, sinkMBB);
17471 // If the EFLAGS register isn't dead in the terminator, then claim that it's
17472 // live into the sink and copy blocks.
17473 const TargetRegisterInfo* TRI = BB->getParent()->getTarget().getRegisterInfo();
17474 if (!MI->killsRegister(X86::EFLAGS) &&
17475 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
17476 copy0MBB->addLiveIn(X86::EFLAGS);
17477 sinkMBB->addLiveIn(X86::EFLAGS);
17480 // Transfer the remainder of BB and its successor edges to sinkMBB.
17481 sinkMBB->splice(sinkMBB->begin(), BB,
17482 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17483 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
17485 // Add the true and fallthrough blocks as its successors.
17486 BB->addSuccessor(copy0MBB);
17487 BB->addSuccessor(sinkMBB);
17489 // Create the conditional branch instruction.
17491 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
17492 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
17495 // %FalseValue = ...
17496 // # fallthrough to sinkMBB
17497 copy0MBB->addSuccessor(sinkMBB);
17500 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
17502 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17503 TII->get(X86::PHI), MI->getOperand(0).getReg())
17504 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
17505 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
17507 MI->eraseFromParent(); // The pseudo instruction is gone now.
17511 MachineBasicBlock *
17512 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
17513 bool Is64Bit) const {
17514 MachineFunction *MF = BB->getParent();
17515 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17516 DebugLoc DL = MI->getDebugLoc();
17517 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17519 assert(MF->shouldSplitStack());
17521 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
17522 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
17525 // ... [Till the alloca]
17526 // If stacklet is not large enough, jump to mallocMBB
17529 // Allocate by subtracting from RSP
17530 // Jump to continueMBB
17533 // Allocate by call to runtime
17537 // [rest of original BB]
17540 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17541 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17542 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17544 MachineRegisterInfo &MRI = MF->getRegInfo();
17545 const TargetRegisterClass *AddrRegClass =
17546 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
17548 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17549 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17550 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
17551 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
17552 sizeVReg = MI->getOperand(1).getReg(),
17553 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
17555 MachineFunction::iterator MBBIter = BB;
17558 MF->insert(MBBIter, bumpMBB);
17559 MF->insert(MBBIter, mallocMBB);
17560 MF->insert(MBBIter, continueMBB);
17562 continueMBB->splice(continueMBB->begin(), BB,
17563 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17564 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
17566 // Add code to the main basic block to check if the stack limit has been hit,
17567 // and if so, jump to mallocMBB otherwise to bumpMBB.
17568 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
17569 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
17570 .addReg(tmpSPVReg).addReg(sizeVReg);
17571 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
17572 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
17573 .addReg(SPLimitVReg);
17574 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
17576 // bumpMBB simply decreases the stack pointer, since we know the current
17577 // stacklet has enough space.
17578 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
17579 .addReg(SPLimitVReg);
17580 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
17581 .addReg(SPLimitVReg);
17582 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17584 // Calls into a routine in libgcc to allocate more space from the heap.
17585 const uint32_t *RegMask =
17586 MF->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17588 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
17590 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
17591 .addExternalSymbol("__morestack_allocate_stack_space")
17592 .addRegMask(RegMask)
17593 .addReg(X86::RDI, RegState::Implicit)
17594 .addReg(X86::RAX, RegState::ImplicitDefine);
17596 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
17598 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
17599 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
17600 .addExternalSymbol("__morestack_allocate_stack_space")
17601 .addRegMask(RegMask)
17602 .addReg(X86::EAX, RegState::ImplicitDefine);
17606 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
17609 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
17610 .addReg(Is64Bit ? X86::RAX : X86::EAX);
17611 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17613 // Set up the CFG correctly.
17614 BB->addSuccessor(bumpMBB);
17615 BB->addSuccessor(mallocMBB);
17616 mallocMBB->addSuccessor(continueMBB);
17617 bumpMBB->addSuccessor(continueMBB);
17619 // Take care of the PHI nodes.
17620 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
17621 MI->getOperand(0).getReg())
17622 .addReg(mallocPtrVReg).addMBB(mallocMBB)
17623 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
17625 // Delete the original pseudo instruction.
17626 MI->eraseFromParent();
17629 return continueMBB;
17632 MachineBasicBlock *
17633 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
17634 MachineBasicBlock *BB) const {
17635 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17636 DebugLoc DL = MI->getDebugLoc();
17638 assert(!Subtarget->isTargetMacho());
17640 // The lowering is pretty easy: we're just emitting the call to _alloca. The
17641 // non-trivial part is impdef of ESP.
17643 if (Subtarget->isTargetWin64()) {
17644 if (Subtarget->isTargetCygMing()) {
17645 // ___chkstk(Mingw64):
17646 // Clobbers R10, R11, RAX and EFLAGS.
17648 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17649 .addExternalSymbol("___chkstk")
17650 .addReg(X86::RAX, RegState::Implicit)
17651 .addReg(X86::RSP, RegState::Implicit)
17652 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
17653 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
17654 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17656 // __chkstk(MSVCRT): does not update stack pointer.
17657 // Clobbers R10, R11 and EFLAGS.
17658 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17659 .addExternalSymbol("__chkstk")
17660 .addReg(X86::RAX, RegState::Implicit)
17661 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17662 // RAX has the offset to be subtracted from RSP.
17663 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
17668 const char *StackProbeSymbol =
17669 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
17671 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
17672 .addExternalSymbol(StackProbeSymbol)
17673 .addReg(X86::EAX, RegState::Implicit)
17674 .addReg(X86::ESP, RegState::Implicit)
17675 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
17676 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
17677 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17680 MI->eraseFromParent(); // The pseudo instruction is gone now.
17684 MachineBasicBlock *
17685 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
17686 MachineBasicBlock *BB) const {
17687 // This is pretty easy. We're taking the value that we received from
17688 // our load from the relocation, sticking it in either RDI (x86-64)
17689 // or EAX and doing an indirect call. The return value will then
17690 // be in the normal return register.
17691 MachineFunction *F = BB->getParent();
17692 const X86InstrInfo *TII
17693 = static_cast<const X86InstrInfo*>(F->getTarget().getInstrInfo());
17694 DebugLoc DL = MI->getDebugLoc();
17696 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
17697 assert(MI->getOperand(3).isGlobal() && "This should be a global");
17699 // Get a register mask for the lowered call.
17700 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
17701 // proper register mask.
17702 const uint32_t *RegMask =
17703 F->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17704 if (Subtarget->is64Bit()) {
17705 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17706 TII->get(X86::MOV64rm), X86::RDI)
17708 .addImm(0).addReg(0)
17709 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17710 MI->getOperand(3).getTargetFlags())
17712 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
17713 addDirectMem(MIB, X86::RDI);
17714 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
17715 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
17716 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17717 TII->get(X86::MOV32rm), X86::EAX)
17719 .addImm(0).addReg(0)
17720 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17721 MI->getOperand(3).getTargetFlags())
17723 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17724 addDirectMem(MIB, X86::EAX);
17725 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17727 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17728 TII->get(X86::MOV32rm), X86::EAX)
17729 .addReg(TII->getGlobalBaseReg(F))
17730 .addImm(0).addReg(0)
17731 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17732 MI->getOperand(3).getTargetFlags())
17734 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17735 addDirectMem(MIB, X86::EAX);
17736 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17739 MI->eraseFromParent(); // The pseudo instruction is gone now.
17743 MachineBasicBlock *
17744 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
17745 MachineBasicBlock *MBB) const {
17746 DebugLoc DL = MI->getDebugLoc();
17747 MachineFunction *MF = MBB->getParent();
17748 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17749 MachineRegisterInfo &MRI = MF->getRegInfo();
17751 const BasicBlock *BB = MBB->getBasicBlock();
17752 MachineFunction::iterator I = MBB;
17755 // Memory Reference
17756 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17757 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17760 unsigned MemOpndSlot = 0;
17762 unsigned CurOp = 0;
17764 DstReg = MI->getOperand(CurOp++).getReg();
17765 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
17766 assert(RC->hasType(MVT::i32) && "Invalid destination!");
17767 unsigned mainDstReg = MRI.createVirtualRegister(RC);
17768 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
17770 MemOpndSlot = CurOp;
17772 MVT PVT = getPointerTy();
17773 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17774 "Invalid Pointer Size!");
17776 // For v = setjmp(buf), we generate
17779 // buf[LabelOffset] = restoreMBB
17780 // SjLjSetup restoreMBB
17786 // v = phi(main, restore)
17791 MachineBasicBlock *thisMBB = MBB;
17792 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17793 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17794 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
17795 MF->insert(I, mainMBB);
17796 MF->insert(I, sinkMBB);
17797 MF->push_back(restoreMBB);
17799 MachineInstrBuilder MIB;
17801 // Transfer the remainder of BB and its successor edges to sinkMBB.
17802 sinkMBB->splice(sinkMBB->begin(), MBB,
17803 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17804 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17807 unsigned PtrStoreOpc = 0;
17808 unsigned LabelReg = 0;
17809 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17810 Reloc::Model RM = MF->getTarget().getRelocationModel();
17811 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
17812 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
17814 // Prepare IP either in reg or imm.
17815 if (!UseImmLabel) {
17816 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
17817 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
17818 LabelReg = MRI.createVirtualRegister(PtrRC);
17819 if (Subtarget->is64Bit()) {
17820 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
17824 .addMBB(restoreMBB)
17827 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
17828 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
17829 .addReg(XII->getGlobalBaseReg(MF))
17832 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
17836 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
17838 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
17839 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17840 if (i == X86::AddrDisp)
17841 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
17843 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
17846 MIB.addReg(LabelReg);
17848 MIB.addMBB(restoreMBB);
17849 MIB.setMemRefs(MMOBegin, MMOEnd);
17851 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
17852 .addMBB(restoreMBB);
17854 const X86RegisterInfo *RegInfo =
17855 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17856 MIB.addRegMask(RegInfo->getNoPreservedMask());
17857 thisMBB->addSuccessor(mainMBB);
17858 thisMBB->addSuccessor(restoreMBB);
17862 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
17863 mainMBB->addSuccessor(sinkMBB);
17866 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17867 TII->get(X86::PHI), DstReg)
17868 .addReg(mainDstReg).addMBB(mainMBB)
17869 .addReg(restoreDstReg).addMBB(restoreMBB);
17872 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
17873 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
17874 restoreMBB->addSuccessor(sinkMBB);
17876 MI->eraseFromParent();
17880 MachineBasicBlock *
17881 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
17882 MachineBasicBlock *MBB) const {
17883 DebugLoc DL = MI->getDebugLoc();
17884 MachineFunction *MF = MBB->getParent();
17885 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17886 MachineRegisterInfo &MRI = MF->getRegInfo();
17888 // Memory Reference
17889 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17890 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17892 MVT PVT = getPointerTy();
17893 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17894 "Invalid Pointer Size!");
17896 const TargetRegisterClass *RC =
17897 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
17898 unsigned Tmp = MRI.createVirtualRegister(RC);
17899 // Since FP is only updated here but NOT referenced, it's treated as GPR.
17900 const X86RegisterInfo *RegInfo =
17901 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17902 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
17903 unsigned SP = RegInfo->getStackRegister();
17905 MachineInstrBuilder MIB;
17907 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17908 const int64_t SPOffset = 2 * PVT.getStoreSize();
17910 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
17911 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
17914 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
17915 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
17916 MIB.addOperand(MI->getOperand(i));
17917 MIB.setMemRefs(MMOBegin, MMOEnd);
17919 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
17920 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17921 if (i == X86::AddrDisp)
17922 MIB.addDisp(MI->getOperand(i), LabelOffset);
17924 MIB.addOperand(MI->getOperand(i));
17926 MIB.setMemRefs(MMOBegin, MMOEnd);
17928 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
17929 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17930 if (i == X86::AddrDisp)
17931 MIB.addDisp(MI->getOperand(i), SPOffset);
17933 MIB.addOperand(MI->getOperand(i));
17935 MIB.setMemRefs(MMOBegin, MMOEnd);
17937 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
17939 MI->eraseFromParent();
17943 // Replace 213-type (isel default) FMA3 instructions with 231-type for
17944 // accumulator loops. Writing back to the accumulator allows the coalescer
17945 // to remove extra copies in the loop.
17946 MachineBasicBlock *
17947 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
17948 MachineBasicBlock *MBB) const {
17949 MachineOperand &AddendOp = MI->getOperand(3);
17951 // Bail out early if the addend isn't a register - we can't switch these.
17952 if (!AddendOp.isReg())
17955 MachineFunction &MF = *MBB->getParent();
17956 MachineRegisterInfo &MRI = MF.getRegInfo();
17958 // Check whether the addend is defined by a PHI:
17959 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
17960 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
17961 if (!AddendDef.isPHI())
17964 // Look for the following pattern:
17966 // %addend = phi [%entry, 0], [%loop, %result]
17968 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
17972 // %addend = phi [%entry, 0], [%loop, %result]
17974 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
17976 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
17977 assert(AddendDef.getOperand(i).isReg());
17978 MachineOperand PHISrcOp = AddendDef.getOperand(i);
17979 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
17980 if (&PHISrcInst == MI) {
17981 // Found a matching instruction.
17982 unsigned NewFMAOpc = 0;
17983 switch (MI->getOpcode()) {
17984 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
17985 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
17986 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
17987 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
17988 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
17989 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
17990 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
17991 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
17992 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
17993 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
17994 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
17995 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
17996 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
17997 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
17998 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
17999 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18000 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18001 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18002 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18003 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18004 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18005 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18006 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18007 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18008 default: llvm_unreachable("Unrecognized FMA variant.");
18011 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
18012 MachineInstrBuilder MIB =
18013 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18014 .addOperand(MI->getOperand(0))
18015 .addOperand(MI->getOperand(3))
18016 .addOperand(MI->getOperand(2))
18017 .addOperand(MI->getOperand(1));
18018 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18019 MI->eraseFromParent();
18026 MachineBasicBlock *
18027 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18028 MachineBasicBlock *BB) const {
18029 switch (MI->getOpcode()) {
18030 default: llvm_unreachable("Unexpected instr type to insert");
18031 case X86::TAILJMPd64:
18032 case X86::TAILJMPr64:
18033 case X86::TAILJMPm64:
18034 llvm_unreachable("TAILJMP64 would not be touched here.");
18035 case X86::TCRETURNdi64:
18036 case X86::TCRETURNri64:
18037 case X86::TCRETURNmi64:
18039 case X86::WIN_ALLOCA:
18040 return EmitLoweredWinAlloca(MI, BB);
18041 case X86::SEG_ALLOCA_32:
18042 return EmitLoweredSegAlloca(MI, BB, false);
18043 case X86::SEG_ALLOCA_64:
18044 return EmitLoweredSegAlloca(MI, BB, true);
18045 case X86::TLSCall_32:
18046 case X86::TLSCall_64:
18047 return EmitLoweredTLSCall(MI, BB);
18048 case X86::CMOV_GR8:
18049 case X86::CMOV_FR32:
18050 case X86::CMOV_FR64:
18051 case X86::CMOV_V4F32:
18052 case X86::CMOV_V2F64:
18053 case X86::CMOV_V2I64:
18054 case X86::CMOV_V8F32:
18055 case X86::CMOV_V4F64:
18056 case X86::CMOV_V4I64:
18057 case X86::CMOV_V16F32:
18058 case X86::CMOV_V8F64:
18059 case X86::CMOV_V8I64:
18060 case X86::CMOV_GR16:
18061 case X86::CMOV_GR32:
18062 case X86::CMOV_RFP32:
18063 case X86::CMOV_RFP64:
18064 case X86::CMOV_RFP80:
18065 return EmitLoweredSelect(MI, BB);
18067 case X86::FP32_TO_INT16_IN_MEM:
18068 case X86::FP32_TO_INT32_IN_MEM:
18069 case X86::FP32_TO_INT64_IN_MEM:
18070 case X86::FP64_TO_INT16_IN_MEM:
18071 case X86::FP64_TO_INT32_IN_MEM:
18072 case X86::FP64_TO_INT64_IN_MEM:
18073 case X86::FP80_TO_INT16_IN_MEM:
18074 case X86::FP80_TO_INT32_IN_MEM:
18075 case X86::FP80_TO_INT64_IN_MEM: {
18076 MachineFunction *F = BB->getParent();
18077 const TargetInstrInfo *TII = F->getTarget().getInstrInfo();
18078 DebugLoc DL = MI->getDebugLoc();
18080 // Change the floating point control register to use "round towards zero"
18081 // mode when truncating to an integer value.
18082 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18083 addFrameReference(BuildMI(*BB, MI, DL,
18084 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18086 // Load the old value of the high byte of the control word...
18088 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18089 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18092 // Set the high part to be round to zero...
18093 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18096 // Reload the modified control word now...
18097 addFrameReference(BuildMI(*BB, MI, DL,
18098 TII->get(X86::FLDCW16m)), CWFrameIdx);
18100 // Restore the memory image of control word to original value
18101 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18104 // Get the X86 opcode to use.
18106 switch (MI->getOpcode()) {
18107 default: llvm_unreachable("illegal opcode!");
18108 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18109 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18110 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18111 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18112 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18113 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18114 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18115 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18116 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18120 MachineOperand &Op = MI->getOperand(0);
18122 AM.BaseType = X86AddressMode::RegBase;
18123 AM.Base.Reg = Op.getReg();
18125 AM.BaseType = X86AddressMode::FrameIndexBase;
18126 AM.Base.FrameIndex = Op.getIndex();
18128 Op = MI->getOperand(1);
18130 AM.Scale = Op.getImm();
18131 Op = MI->getOperand(2);
18133 AM.IndexReg = Op.getImm();
18134 Op = MI->getOperand(3);
18135 if (Op.isGlobal()) {
18136 AM.GV = Op.getGlobal();
18138 AM.Disp = Op.getImm();
18140 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18141 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18143 // Reload the original control word now.
18144 addFrameReference(BuildMI(*BB, MI, DL,
18145 TII->get(X86::FLDCW16m)), CWFrameIdx);
18147 MI->eraseFromParent(); // The pseudo instruction is gone now.
18150 // String/text processing lowering.
18151 case X86::PCMPISTRM128REG:
18152 case X86::VPCMPISTRM128REG:
18153 case X86::PCMPISTRM128MEM:
18154 case X86::VPCMPISTRM128MEM:
18155 case X86::PCMPESTRM128REG:
18156 case X86::VPCMPESTRM128REG:
18157 case X86::PCMPESTRM128MEM:
18158 case X86::VPCMPESTRM128MEM:
18159 assert(Subtarget->hasSSE42() &&
18160 "Target must have SSE4.2 or AVX features enabled");
18161 return EmitPCMPSTRM(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18163 // String/text processing lowering.
18164 case X86::PCMPISTRIREG:
18165 case X86::VPCMPISTRIREG:
18166 case X86::PCMPISTRIMEM:
18167 case X86::VPCMPISTRIMEM:
18168 case X86::PCMPESTRIREG:
18169 case X86::VPCMPESTRIREG:
18170 case X86::PCMPESTRIMEM:
18171 case X86::VPCMPESTRIMEM:
18172 assert(Subtarget->hasSSE42() &&
18173 "Target must have SSE4.2 or AVX features enabled");
18174 return EmitPCMPSTRI(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18176 // Thread synchronization.
18178 return EmitMonitor(MI, BB, BB->getParent()->getTarget().getInstrInfo(), Subtarget);
18182 return EmitXBegin(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18184 case X86::VASTART_SAVE_XMM_REGS:
18185 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18187 case X86::VAARG_64:
18188 return EmitVAARG64WithCustomInserter(MI, BB);
18190 case X86::EH_SjLj_SetJmp32:
18191 case X86::EH_SjLj_SetJmp64:
18192 return emitEHSjLjSetJmp(MI, BB);
18194 case X86::EH_SjLj_LongJmp32:
18195 case X86::EH_SjLj_LongJmp64:
18196 return emitEHSjLjLongJmp(MI, BB);
18198 case TargetOpcode::STACKMAP:
18199 case TargetOpcode::PATCHPOINT:
18200 return emitPatchPoint(MI, BB);
18202 case X86::VFMADDPDr213r:
18203 case X86::VFMADDPSr213r:
18204 case X86::VFMADDSDr213r:
18205 case X86::VFMADDSSr213r:
18206 case X86::VFMSUBPDr213r:
18207 case X86::VFMSUBPSr213r:
18208 case X86::VFMSUBSDr213r:
18209 case X86::VFMSUBSSr213r:
18210 case X86::VFNMADDPDr213r:
18211 case X86::VFNMADDPSr213r:
18212 case X86::VFNMADDSDr213r:
18213 case X86::VFNMADDSSr213r:
18214 case X86::VFNMSUBPDr213r:
18215 case X86::VFNMSUBPSr213r:
18216 case X86::VFNMSUBSDr213r:
18217 case X86::VFNMSUBSSr213r:
18218 case X86::VFMADDPDr213rY:
18219 case X86::VFMADDPSr213rY:
18220 case X86::VFMSUBPDr213rY:
18221 case X86::VFMSUBPSr213rY:
18222 case X86::VFNMADDPDr213rY:
18223 case X86::VFNMADDPSr213rY:
18224 case X86::VFNMSUBPDr213rY:
18225 case X86::VFNMSUBPSr213rY:
18226 return emitFMA3Instr(MI, BB);
18230 //===----------------------------------------------------------------------===//
18231 // X86 Optimization Hooks
18232 //===----------------------------------------------------------------------===//
18234 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18237 const SelectionDAG &DAG,
18238 unsigned Depth) const {
18239 unsigned BitWidth = KnownZero.getBitWidth();
18240 unsigned Opc = Op.getOpcode();
18241 assert((Opc >= ISD::BUILTIN_OP_END ||
18242 Opc == ISD::INTRINSIC_WO_CHAIN ||
18243 Opc == ISD::INTRINSIC_W_CHAIN ||
18244 Opc == ISD::INTRINSIC_VOID) &&
18245 "Should use MaskedValueIsZero if you don't know whether Op"
18246 " is a target node!");
18248 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18262 // These nodes' second result is a boolean.
18263 if (Op.getResNo() == 0)
18266 case X86ISD::SETCC:
18267 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18269 case ISD::INTRINSIC_WO_CHAIN: {
18270 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18271 unsigned NumLoBits = 0;
18274 case Intrinsic::x86_sse_movmsk_ps:
18275 case Intrinsic::x86_avx_movmsk_ps_256:
18276 case Intrinsic::x86_sse2_movmsk_pd:
18277 case Intrinsic::x86_avx_movmsk_pd_256:
18278 case Intrinsic::x86_mmx_pmovmskb:
18279 case Intrinsic::x86_sse2_pmovmskb_128:
18280 case Intrinsic::x86_avx2_pmovmskb: {
18281 // High bits of movmskp{s|d}, pmovmskb are known zero.
18283 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18284 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18285 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18286 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18287 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18288 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18289 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18290 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18292 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18301 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18303 const SelectionDAG &,
18304 unsigned Depth) const {
18305 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18306 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18307 return Op.getValueType().getScalarType().getSizeInBits();
18313 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18314 /// node is a GlobalAddress + offset.
18315 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18316 const GlobalValue* &GA,
18317 int64_t &Offset) const {
18318 if (N->getOpcode() == X86ISD::Wrapper) {
18319 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18320 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18321 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18325 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18328 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18329 /// same as extracting the high 128-bit part of 256-bit vector and then
18330 /// inserting the result into the low part of a new 256-bit vector
18331 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18332 EVT VT = SVOp->getValueType(0);
18333 unsigned NumElems = VT.getVectorNumElements();
18335 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18336 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18337 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18338 SVOp->getMaskElt(j) >= 0)
18344 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18345 /// same as extracting the low 128-bit part of 256-bit vector and then
18346 /// inserting the result into the high part of a new 256-bit vector
18347 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18348 EVT VT = SVOp->getValueType(0);
18349 unsigned NumElems = VT.getVectorNumElements();
18351 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18352 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18353 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18354 SVOp->getMaskElt(j) >= 0)
18360 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18361 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18362 TargetLowering::DAGCombinerInfo &DCI,
18363 const X86Subtarget* Subtarget) {
18365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18366 SDValue V1 = SVOp->getOperand(0);
18367 SDValue V2 = SVOp->getOperand(1);
18368 EVT VT = SVOp->getValueType(0);
18369 unsigned NumElems = VT.getVectorNumElements();
18371 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18372 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18376 // V UNDEF BUILD_VECTOR UNDEF
18378 // CONCAT_VECTOR CONCAT_VECTOR
18381 // RESULT: V + zero extended
18383 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18384 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18385 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18388 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
18391 // To match the shuffle mask, the first half of the mask should
18392 // be exactly the first vector, and all the rest a splat with the
18393 // first element of the second one.
18394 for (unsigned i = 0; i != NumElems/2; ++i)
18395 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
18396 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
18399 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
18400 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
18401 if (Ld->hasNUsesOfValue(1, 0)) {
18402 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
18403 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
18405 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
18407 Ld->getPointerInfo(),
18408 Ld->getAlignment(),
18409 false/*isVolatile*/, true/*ReadMem*/,
18410 false/*WriteMem*/);
18412 // Make sure the newly-created LOAD is in the same position as Ld in
18413 // terms of dependency. We create a TokenFactor for Ld and ResNode,
18414 // and update uses of Ld's output chain to use the TokenFactor.
18415 if (Ld->hasAnyUseOfValue(1)) {
18416 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18417 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
18418 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
18419 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
18420 SDValue(ResNode.getNode(), 1));
18423 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
18427 // Emit a zeroed vector and insert the desired subvector on its
18429 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18430 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
18431 return DCI.CombineTo(N, InsV);
18434 //===--------------------------------------------------------------------===//
18435 // Combine some shuffles into subvector extracts and inserts:
18438 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18439 if (isShuffleHigh128VectorInsertLow(SVOp)) {
18440 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
18441 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
18442 return DCI.CombineTo(N, InsV);
18445 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18446 if (isShuffleLow128VectorInsertHigh(SVOp)) {
18447 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
18448 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
18449 return DCI.CombineTo(N, InsV);
18455 /// \brief Get the PSHUF-style mask from PSHUF node.
18457 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
18458 /// PSHUF-style masks that can be reused with such instructions.
18459 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
18460 SmallVector<int, 4> Mask;
18462 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
18466 switch (N.getOpcode()) {
18467 case X86ISD::PSHUFD:
18469 case X86ISD::PSHUFLW:
18472 case X86ISD::PSHUFHW:
18473 Mask.erase(Mask.begin(), Mask.begin() + 4);
18474 for (int &M : Mask)
18478 llvm_unreachable("No valid shuffle instruction found!");
18482 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
18484 /// We walk up the chain and look for a combinable shuffle, skipping over
18485 /// shuffles that we could hoist this shuffle's transformation past without
18486 /// altering anything.
18487 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
18489 TargetLowering::DAGCombinerInfo &DCI) {
18490 assert(N.getOpcode() == X86ISD::PSHUFD &&
18491 "Called with something other than an x86 128-bit half shuffle!");
18494 // Walk up a single-use chain looking for a combinable shuffle.
18495 SDValue V = N.getOperand(0);
18496 for (; V.hasOneUse(); V = V.getOperand(0)) {
18497 switch (V.getOpcode()) {
18499 return false; // Nothing combined!
18502 // Skip bitcasts as we always know the type for the target specific
18506 case X86ISD::PSHUFD:
18507 // Found another dword shuffle.
18510 case X86ISD::PSHUFLW:
18511 // Check that the low words (being shuffled) are the identity in the
18512 // dword shuffle, and the high words are self-contained.
18513 if (Mask[0] != 0 || Mask[1] != 1 ||
18514 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
18519 case X86ISD::PSHUFHW:
18520 // Check that the high words (being shuffled) are the identity in the
18521 // dword shuffle, and the low words are self-contained.
18522 if (Mask[2] != 2 || Mask[3] != 3 ||
18523 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
18528 case X86ISD::UNPCKL:
18529 case X86ISD::UNPCKH:
18530 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
18531 // shuffle into a preceding word shuffle.
18532 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
18535 // Search for a half-shuffle which we can combine with.
18536 unsigned CombineOp =
18537 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18538 if (V.getOperand(0) != V.getOperand(1) ||
18539 !V->isOnlyUserOf(V.getOperand(0).getNode()))
18541 V = V.getOperand(0);
18543 switch (V.getOpcode()) {
18545 return false; // Nothing to combine.
18547 case X86ISD::PSHUFLW:
18548 case X86ISD::PSHUFHW:
18549 if (V.getOpcode() == CombineOp)
18554 V = V.getOperand(0);
18558 } while (V.hasOneUse());
18561 // Break out of the loop if we break out of the switch.
18565 if (!V.hasOneUse())
18566 // We fell out of the loop without finding a viable combining instruction.
18569 // Record the old value to use in RAUW-ing.
18572 // Merge this node's mask and our incoming mask.
18573 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18574 for (int &M : Mask)
18576 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
18577 getV4X86ShuffleImm8ForMask(Mask, DAG));
18579 // It is possible that one of the combinable shuffles was completely absorbed
18580 // by the other, just replace it and revisit all users in that case.
18581 if (Old.getNode() == V.getNode()) {
18582 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
18586 // Replace N with its operand as we're going to combine that shuffle away.
18587 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18589 // Replace the combinable shuffle with the combined one, updating all users
18590 // so that we re-evaluate the chain here.
18591 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18595 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
18597 /// We walk up the chain, skipping shuffles of the other half and looking
18598 /// through shuffles which switch halves trying to find a shuffle of the same
18599 /// pair of dwords.
18600 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
18602 TargetLowering::DAGCombinerInfo &DCI) {
18604 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
18605 "Called with something other than an x86 128-bit half shuffle!");
18607 unsigned CombineOpcode = N.getOpcode();
18609 // Walk up a single-use chain looking for a combinable shuffle.
18610 SDValue V = N.getOperand(0);
18611 for (; V.hasOneUse(); V = V.getOperand(0)) {
18612 switch (V.getOpcode()) {
18614 return false; // Nothing combined!
18617 // Skip bitcasts as we always know the type for the target specific
18621 case X86ISD::PSHUFLW:
18622 case X86ISD::PSHUFHW:
18623 if (V.getOpcode() == CombineOpcode)
18626 // Other-half shuffles are no-ops.
18629 case X86ISD::PSHUFD: {
18630 // We can only handle pshufd if the half we are combining either stays in
18631 // its half, or switches to the other half. Bail if one of these isn't
18633 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18634 int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
18635 if (!((VMask[DOffset + 0] < 2 && VMask[DOffset + 1] < 2) ||
18636 (VMask[DOffset + 0] >= 2 && VMask[DOffset + 1] >= 2)))
18639 // Map the mask through the pshufd and keep walking up the chain.
18640 for (int i = 0; i < 4; ++i)
18641 Mask[i] = 2 * (VMask[DOffset + Mask[i] / 2] % 2) + Mask[i] % 2;
18643 // Switch halves if the pshufd does.
18645 VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18649 // Break out of the loop if we break out of the switch.
18653 if (!V.hasOneUse())
18654 // We fell out of the loop without finding a viable combining instruction.
18657 // Record the old value to use in RAUW-ing.
18660 // Merge this node's mask and our incoming mask (adjusted to account for all
18661 // the pshufd instructions encountered).
18662 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18663 for (int &M : Mask)
18665 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
18666 getV4X86ShuffleImm8ForMask(Mask, DAG));
18668 // Replace N with its operand as we're going to combine that shuffle away.
18669 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18671 // Replace the combinable shuffle with the combined one, updating all users
18672 // so that we re-evaluate the chain here.
18673 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18677 /// \brief Try to combine x86 target specific shuffles.
18678 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
18679 TargetLowering::DAGCombinerInfo &DCI,
18680 const X86Subtarget *Subtarget) {
18682 MVT VT = N.getSimpleValueType();
18683 SmallVector<int, 4> Mask;
18685 switch (N.getOpcode()) {
18686 case X86ISD::PSHUFD:
18687 case X86ISD::PSHUFLW:
18688 case X86ISD::PSHUFHW:
18689 Mask = getPSHUFShuffleMask(N);
18690 assert(Mask.size() == 4);
18696 // Nuke no-op shuffles that show up after combining.
18697 if (isNoopShuffleMask(Mask))
18698 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
18700 // Look for simplifications involving one or two shuffle instructions.
18701 SDValue V = N.getOperand(0);
18702 switch (N.getOpcode()) {
18705 case X86ISD::PSHUFLW:
18706 case X86ISD::PSHUFHW:
18707 assert(VT == MVT::v8i16);
18710 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
18711 return SDValue(); // We combined away this shuffle, so we're done.
18713 // See if this reduces to a PSHUFD which is no more expensive and can
18714 // combine with more operations.
18715 if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
18716 areAdjacentMasksSequential(Mask)) {
18717 int DMask[] = {-1, -1, -1, -1};
18718 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
18719 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
18720 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
18721 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
18722 DCI.AddToWorklist(V.getNode());
18723 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
18724 getV4X86ShuffleImm8ForMask(DMask, DAG));
18725 DCI.AddToWorklist(V.getNode());
18726 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
18729 // Look for shuffle patterns which can be implemented as a single unpack.
18730 // FIXME: This doesn't handle the location of the PSHUFD generically, and
18731 // only works when we have a PSHUFD followed by two half-shuffles.
18732 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
18733 (V.getOpcode() == X86ISD::PSHUFLW ||
18734 V.getOpcode() == X86ISD::PSHUFHW) &&
18735 V.getOpcode() != N.getOpcode() &&
18737 SDValue D = V.getOperand(0);
18738 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
18739 D = D.getOperand(0);
18740 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
18741 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18742 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
18743 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
18744 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
18746 for (int i = 0; i < 4; ++i) {
18747 WordMask[i + NOffset] = Mask[i] + NOffset;
18748 WordMask[i + VOffset] = VMask[i] + VOffset;
18750 // Map the word mask through the DWord mask.
18752 for (int i = 0; i < 8; ++i)
18753 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
18754 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
18755 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
18756 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
18757 std::begin(UnpackLoMask)) ||
18758 std::equal(std::begin(MappedMask), std::end(MappedMask),
18759 std::begin(UnpackHiMask))) {
18760 // We can replace all three shuffles with an unpack.
18761 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
18762 DCI.AddToWorklist(V.getNode());
18763 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
18765 DL, MVT::v8i16, V, V);
18772 case X86ISD::PSHUFD:
18773 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
18774 return SDValue(); // We combined away this shuffle.
18782 /// PerformShuffleCombine - Performs several different shuffle combines.
18783 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
18784 TargetLowering::DAGCombinerInfo &DCI,
18785 const X86Subtarget *Subtarget) {
18787 SDValue N0 = N->getOperand(0);
18788 SDValue N1 = N->getOperand(1);
18789 EVT VT = N->getValueType(0);
18791 // Canonicalize shuffles that perform 'addsub' on packed float vectors
18792 // according to the rule:
18793 // (shuffle (FADD A, B), (FSUB A, B), Mask) ->
18794 // (shuffle (FSUB A, -B), (FADD A, -B), Mask)
18796 // Where 'Mask' is:
18797 // <0,5,2,7> -- for v4f32 and v4f64 shuffles;
18798 // <0,3> -- for v2f64 shuffles;
18799 // <0,9,2,11,4,13,6,15> -- for v8f32 shuffles.
18801 // This helps pattern-matching more SSE3/AVX ADDSUB instructions
18802 // during ISel stage.
18803 if (N->getOpcode() == ISD::VECTOR_SHUFFLE &&
18804 ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18805 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18806 N0->getOpcode() == ISD::FADD && N1->getOpcode() == ISD::FSUB &&
18807 // Operands to the FADD and FSUB must be the same.
18808 ((N0->getOperand(0) == N1->getOperand(0) &&
18809 N0->getOperand(1) == N1->getOperand(1)) ||
18810 // FADD is commutable. See if by commuting the operands of the FADD
18811 // we would still be able to match the operands of the FSUB dag node.
18812 (N0->getOperand(1) == N1->getOperand(0) &&
18813 N0->getOperand(0) == N1->getOperand(1))) &&
18814 N0->getOperand(0)->getOpcode() != ISD::UNDEF &&
18815 N0->getOperand(1)->getOpcode() != ISD::UNDEF) {
18817 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
18818 unsigned NumElts = VT.getVectorNumElements();
18819 ArrayRef<int> Mask = SV->getMask();
18820 bool CanFold = true;
18822 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i)
18823 CanFold = Mask[i] == (int)((i & 1) ? i + NumElts : i);
18826 SDValue Op0 = N1->getOperand(0);
18827 SDValue Op1 = DAG.getNode(ISD::FNEG, dl, VT, N1->getOperand(1));
18828 SDValue Sub = DAG.getNode(ISD::FSUB, dl, VT, Op0, Op1);
18829 SDValue Add = DAG.getNode(ISD::FADD, dl, VT, Op0, Op1);
18830 return DAG.getVectorShuffle(VT, dl, Sub, Add, Mask);
18834 // Don't create instructions with illegal types after legalize types has run.
18835 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18836 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
18839 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
18840 if (Subtarget->hasFp256() && VT.is256BitVector() &&
18841 N->getOpcode() == ISD::VECTOR_SHUFFLE)
18842 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
18844 // During Type Legalization, when promoting illegal vector types,
18845 // the backend might introduce new shuffle dag nodes and bitcasts.
18847 // This code performs the following transformation:
18848 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
18849 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
18851 // We do this only if both the bitcast and the BINOP dag nodes have
18852 // one use. Also, perform this transformation only if the new binary
18853 // operation is legal. This is to avoid introducing dag nodes that
18854 // potentially need to be further expanded (or custom lowered) into a
18855 // less optimal sequence of dag nodes.
18856 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
18857 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
18858 N0.getOpcode() == ISD::BITCAST) {
18859 SDValue BC0 = N0.getOperand(0);
18860 EVT SVT = BC0.getValueType();
18861 unsigned Opcode = BC0.getOpcode();
18862 unsigned NumElts = VT.getVectorNumElements();
18864 if (BC0.hasOneUse() && SVT.isVector() &&
18865 SVT.getVectorNumElements() * 2 == NumElts &&
18866 TLI.isOperationLegal(Opcode, VT)) {
18867 bool CanFold = false;
18879 unsigned SVTNumElts = SVT.getVectorNumElements();
18880 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18881 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
18882 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
18883 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
18884 CanFold = SVOp->getMaskElt(i) < 0;
18887 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
18888 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
18889 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
18890 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
18895 // Only handle 128 wide vector from here on.
18896 if (!VT.is128BitVector())
18899 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
18900 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
18901 // consecutive, non-overlapping, and in the right order.
18902 SmallVector<SDValue, 16> Elts;
18903 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
18904 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
18906 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
18910 if (isTargetShuffle(N->getOpcode())) {
18912 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
18913 if (Shuffle.getNode())
18920 /// PerformTruncateCombine - Converts truncate operation to
18921 /// a sequence of vector shuffle operations.
18922 /// It is possible when we truncate 256-bit vector to 128-bit vector
18923 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
18924 TargetLowering::DAGCombinerInfo &DCI,
18925 const X86Subtarget *Subtarget) {
18929 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
18930 /// specific shuffle of a load can be folded into a single element load.
18931 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
18932 /// shuffles have been customed lowered so we need to handle those here.
18933 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
18934 TargetLowering::DAGCombinerInfo &DCI) {
18935 if (DCI.isBeforeLegalizeOps())
18938 SDValue InVec = N->getOperand(0);
18939 SDValue EltNo = N->getOperand(1);
18941 if (!isa<ConstantSDNode>(EltNo))
18944 EVT VT = InVec.getValueType();
18946 bool HasShuffleIntoBitcast = false;
18947 if (InVec.getOpcode() == ISD::BITCAST) {
18948 // Don't duplicate a load with other uses.
18949 if (!InVec.hasOneUse())
18951 EVT BCVT = InVec.getOperand(0).getValueType();
18952 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
18954 InVec = InVec.getOperand(0);
18955 HasShuffleIntoBitcast = true;
18958 if (!isTargetShuffle(InVec.getOpcode()))
18961 // Don't duplicate a load with other uses.
18962 if (!InVec.hasOneUse())
18965 SmallVector<int, 16> ShuffleMask;
18967 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
18971 // Select the input vector, guarding against out of range extract vector.
18972 unsigned NumElems = VT.getVectorNumElements();
18973 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
18974 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
18975 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
18976 : InVec.getOperand(1);
18978 // If inputs to shuffle are the same for both ops, then allow 2 uses
18979 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
18981 if (LdNode.getOpcode() == ISD::BITCAST) {
18982 // Don't duplicate a load with other uses.
18983 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
18986 AllowedUses = 1; // only allow 1 load use if we have a bitcast
18987 LdNode = LdNode.getOperand(0);
18990 if (!ISD::isNormalLoad(LdNode.getNode()))
18993 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
18995 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
18998 if (HasShuffleIntoBitcast) {
18999 // If there's a bitcast before the shuffle, check if the load type and
19000 // alignment is valid.
19001 unsigned Align = LN0->getAlignment();
19002 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19003 unsigned NewAlign = TLI.getDataLayout()->
19004 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
19006 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
19010 // All checks match so transform back to vector_shuffle so that DAG combiner
19011 // can finish the job
19014 // Create shuffle node taking into account the case that its a unary shuffle
19015 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
19016 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
19017 InVec.getOperand(0), Shuffle,
19019 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
19020 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
19024 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
19025 /// generation and convert it from being a bunch of shuffles and extracts
19026 /// to a simple store and scalar loads to extract the elements.
19027 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
19028 TargetLowering::DAGCombinerInfo &DCI) {
19029 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
19030 if (NewOp.getNode())
19033 SDValue InputVector = N->getOperand(0);
19035 // Detect whether we are trying to convert from mmx to i32 and the bitcast
19036 // from mmx to v2i32 has a single usage.
19037 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
19038 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
19039 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
19040 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
19041 N->getValueType(0),
19042 InputVector.getNode()->getOperand(0));
19044 // Only operate on vectors of 4 elements, where the alternative shuffling
19045 // gets to be more expensive.
19046 if (InputVector.getValueType() != MVT::v4i32)
19049 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
19050 // single use which is a sign-extend or zero-extend, and all elements are
19052 SmallVector<SDNode *, 4> Uses;
19053 unsigned ExtractedElements = 0;
19054 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
19055 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
19056 if (UI.getUse().getResNo() != InputVector.getResNo())
19059 SDNode *Extract = *UI;
19060 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
19063 if (Extract->getValueType(0) != MVT::i32)
19065 if (!Extract->hasOneUse())
19067 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
19068 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
19070 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
19073 // Record which element was extracted.
19074 ExtractedElements |=
19075 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
19077 Uses.push_back(Extract);
19080 // If not all the elements were used, this may not be worthwhile.
19081 if (ExtractedElements != 15)
19084 // Ok, we've now decided to do the transformation.
19085 SDLoc dl(InputVector);
19087 // Store the value to a temporary stack slot.
19088 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
19089 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
19090 MachinePointerInfo(), false, false, 0);
19092 // Replace each use (extract) with a load of the appropriate element.
19093 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
19094 UE = Uses.end(); UI != UE; ++UI) {
19095 SDNode *Extract = *UI;
19097 // cOMpute the element's address.
19098 SDValue Idx = Extract->getOperand(1);
19100 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
19101 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
19102 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19103 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
19105 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
19106 StackPtr, OffsetVal);
19108 // Load the scalar.
19109 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
19110 ScalarAddr, MachinePointerInfo(),
19111 false, false, false, 0);
19113 // Replace the exact with the load.
19114 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
19117 // The replacement was made in place; don't return anything.
19121 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
19122 static std::pair<unsigned, bool>
19123 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
19124 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
19125 if (!VT.isVector())
19126 return std::make_pair(0, false);
19128 bool NeedSplit = false;
19129 switch (VT.getSimpleVT().SimpleTy) {
19130 default: return std::make_pair(0, false);
19134 if (!Subtarget->hasAVX2())
19136 if (!Subtarget->hasAVX())
19137 return std::make_pair(0, false);
19142 if (!Subtarget->hasSSE2())
19143 return std::make_pair(0, false);
19146 // SSE2 has only a small subset of the operations.
19147 bool hasUnsigned = Subtarget->hasSSE41() ||
19148 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19149 bool hasSigned = Subtarget->hasSSE41() ||
19150 (Subtarget->hasSSE2() && VT == MVT::v8i16);
19152 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19155 // Check for x CC y ? x : y.
19156 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19157 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19162 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19165 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19168 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19171 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19173 // Check for x CC y ? y : x -- a min/max with reversed arms.
19174 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19175 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19180 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19183 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19186 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19189 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19193 return std::make_pair(Opc, NeedSplit);
19197 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
19198 const X86Subtarget *Subtarget) {
19200 SDValue Cond = N->getOperand(0);
19201 SDValue LHS = N->getOperand(1);
19202 SDValue RHS = N->getOperand(2);
19204 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19205 SDValue CondSrc = Cond->getOperand(0);
19206 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
19207 Cond = CondSrc->getOperand(0);
19210 MVT VT = N->getSimpleValueType(0);
19211 MVT EltVT = VT.getVectorElementType();
19212 unsigned NumElems = VT.getVectorNumElements();
19213 // There is no blend with immediate in AVX-512.
19214 if (VT.is512BitVector())
19217 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
19219 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19222 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
19225 unsigned MaskValue = 0;
19226 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
19229 SmallVector<int, 8> ShuffleMask(NumElems, -1);
19230 for (unsigned i = 0; i < NumElems; ++i) {
19231 // Be sure we emit undef where we can.
19232 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
19233 ShuffleMask[i] = -1;
19235 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
19238 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
19241 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
19243 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
19244 TargetLowering::DAGCombinerInfo &DCI,
19245 const X86Subtarget *Subtarget) {
19247 SDValue Cond = N->getOperand(0);
19248 // Get the LHS/RHS of the select.
19249 SDValue LHS = N->getOperand(1);
19250 SDValue RHS = N->getOperand(2);
19251 EVT VT = LHS.getValueType();
19252 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19254 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
19255 // instructions match the semantics of the common C idiom x<y?x:y but not
19256 // x<=y?x:y, because of how they handle negative zero (which can be
19257 // ignored in unsafe-math mode).
19258 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
19259 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
19260 (Subtarget->hasSSE2() ||
19261 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
19262 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19264 unsigned Opcode = 0;
19265 // Check for x CC y ? x : y.
19266 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19267 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19271 // Converting this to a min would handle NaNs incorrectly, and swapping
19272 // the operands would cause it to handle comparisons between positive
19273 // and negative zero incorrectly.
19274 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19275 if (!DAG.getTarget().Options.UnsafeFPMath &&
19276 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19278 std::swap(LHS, RHS);
19280 Opcode = X86ISD::FMIN;
19283 // Converting this to a min would handle comparisons between positive
19284 // and negative zero incorrectly.
19285 if (!DAG.getTarget().Options.UnsafeFPMath &&
19286 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19288 Opcode = X86ISD::FMIN;
19291 // Converting this to a min would handle both negative zeros and NaNs
19292 // incorrectly, but we can swap the operands to fix both.
19293 std::swap(LHS, RHS);
19297 Opcode = X86ISD::FMIN;
19301 // Converting this to a max would handle comparisons between positive
19302 // and negative zero incorrectly.
19303 if (!DAG.getTarget().Options.UnsafeFPMath &&
19304 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19306 Opcode = X86ISD::FMAX;
19309 // Converting this to a max would handle NaNs incorrectly, and swapping
19310 // the operands would cause it to handle comparisons between positive
19311 // and negative zero incorrectly.
19312 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19313 if (!DAG.getTarget().Options.UnsafeFPMath &&
19314 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19316 std::swap(LHS, RHS);
19318 Opcode = X86ISD::FMAX;
19321 // Converting this to a max would handle both negative zeros and NaNs
19322 // incorrectly, but we can swap the operands to fix both.
19323 std::swap(LHS, RHS);
19327 Opcode = X86ISD::FMAX;
19330 // Check for x CC y ? y : x -- a min/max with reversed arms.
19331 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19332 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19336 // Converting this to a min would handle comparisons between positive
19337 // and negative zero incorrectly, and swapping the operands would
19338 // cause it to handle NaNs incorrectly.
19339 if (!DAG.getTarget().Options.UnsafeFPMath &&
19340 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
19341 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19343 std::swap(LHS, RHS);
19345 Opcode = X86ISD::FMIN;
19348 // Converting this to a min would handle NaNs incorrectly.
19349 if (!DAG.getTarget().Options.UnsafeFPMath &&
19350 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
19352 Opcode = X86ISD::FMIN;
19355 // Converting this to a min would handle both negative zeros and NaNs
19356 // incorrectly, but we can swap the operands to fix both.
19357 std::swap(LHS, RHS);
19361 Opcode = X86ISD::FMIN;
19365 // Converting this to a max would handle NaNs incorrectly.
19366 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19368 Opcode = X86ISD::FMAX;
19371 // Converting this to a max would handle comparisons between positive
19372 // and negative zero incorrectly, and swapping the operands would
19373 // cause it to handle NaNs incorrectly.
19374 if (!DAG.getTarget().Options.UnsafeFPMath &&
19375 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
19376 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19378 std::swap(LHS, RHS);
19380 Opcode = X86ISD::FMAX;
19383 // Converting this to a max would handle both negative zeros and NaNs
19384 // incorrectly, but we can swap the operands to fix both.
19385 std::swap(LHS, RHS);
19389 Opcode = X86ISD::FMAX;
19395 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
19398 EVT CondVT = Cond.getValueType();
19399 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
19400 CondVT.getVectorElementType() == MVT::i1) {
19401 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
19402 // lowering on AVX-512. In this case we convert it to
19403 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
19404 // The same situation for all 128 and 256-bit vectors of i8 and i16
19405 EVT OpVT = LHS.getValueType();
19406 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
19407 (OpVT.getVectorElementType() == MVT::i8 ||
19408 OpVT.getVectorElementType() == MVT::i16)) {
19409 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
19410 DCI.AddToWorklist(Cond.getNode());
19411 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
19414 // If this is a select between two integer constants, try to do some
19416 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
19417 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
19418 // Don't do this for crazy integer types.
19419 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
19420 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
19421 // so that TrueC (the true value) is larger than FalseC.
19422 bool NeedsCondInvert = false;
19424 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
19425 // Efficiently invertible.
19426 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
19427 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
19428 isa<ConstantSDNode>(Cond.getOperand(1))))) {
19429 NeedsCondInvert = true;
19430 std::swap(TrueC, FalseC);
19433 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
19434 if (FalseC->getAPIntValue() == 0 &&
19435 TrueC->getAPIntValue().isPowerOf2()) {
19436 if (NeedsCondInvert) // Invert the condition if needed.
19437 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19438 DAG.getConstant(1, Cond.getValueType()));
19440 // Zero extend the condition if needed.
19441 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
19443 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19444 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
19445 DAG.getConstant(ShAmt, MVT::i8));
19448 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
19449 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19450 if (NeedsCondInvert) // Invert the condition if needed.
19451 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19452 DAG.getConstant(1, Cond.getValueType()));
19454 // Zero extend the condition if needed.
19455 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19456 FalseC->getValueType(0), Cond);
19457 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19458 SDValue(FalseC, 0));
19461 // Optimize cases that will turn into an LEA instruction. This requires
19462 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
19463 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
19464 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
19465 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
19467 bool isFastMultiplier = false;
19469 switch ((unsigned char)Diff) {
19471 case 1: // result = add base, cond
19472 case 2: // result = lea base( , cond*2)
19473 case 3: // result = lea base(cond, cond*2)
19474 case 4: // result = lea base( , cond*4)
19475 case 5: // result = lea base(cond, cond*4)
19476 case 8: // result = lea base( , cond*8)
19477 case 9: // result = lea base(cond, cond*8)
19478 isFastMultiplier = true;
19483 if (isFastMultiplier) {
19484 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
19485 if (NeedsCondInvert) // Invert the condition if needed.
19486 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19487 DAG.getConstant(1, Cond.getValueType()));
19489 // Zero extend the condition if needed.
19490 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
19492 // Scale the condition by the difference.
19494 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
19495 DAG.getConstant(Diff, Cond.getValueType()));
19497 // Add the base if non-zero.
19498 if (FalseC->getAPIntValue() != 0)
19499 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19500 SDValue(FalseC, 0));
19507 // Canonicalize max and min:
19508 // (x > y) ? x : y -> (x >= y) ? x : y
19509 // (x < y) ? x : y -> (x <= y) ? x : y
19510 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
19511 // the need for an extra compare
19512 // against zero. e.g.
19513 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
19515 // testl %edi, %edi
19517 // cmovgl %edi, %eax
19521 // cmovsl %eax, %edi
19522 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
19523 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19524 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19525 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19530 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
19531 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
19532 Cond.getOperand(0), Cond.getOperand(1), NewCC);
19533 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
19538 // Early exit check
19539 if (!TLI.isTypeLegal(VT))
19542 // Match VSELECTs into subs with unsigned saturation.
19543 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19544 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
19545 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
19546 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
19547 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19549 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
19550 // left side invert the predicate to simplify logic below.
19552 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
19554 CC = ISD::getSetCCInverse(CC, true);
19555 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
19559 if (Other.getNode() && Other->getNumOperands() == 2 &&
19560 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
19561 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
19562 SDValue CondRHS = Cond->getOperand(1);
19564 // Look for a general sub with unsigned saturation first.
19565 // x >= y ? x-y : 0 --> subus x, y
19566 // x > y ? x-y : 0 --> subus x, y
19567 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
19568 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
19569 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
19571 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
19572 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
19573 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
19574 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
19575 // If the RHS is a constant we have to reverse the const
19576 // canonicalization.
19577 // x > C-1 ? x+-C : 0 --> subus x, C
19578 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
19579 CondRHSConst->getAPIntValue() ==
19580 (-OpRHSConst->getAPIntValue() - 1))
19581 return DAG.getNode(
19582 X86ISD::SUBUS, DL, VT, OpLHS,
19583 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
19585 // Another special case: If C was a sign bit, the sub has been
19586 // canonicalized into a xor.
19587 // FIXME: Would it be better to use computeKnownBits to determine
19588 // whether it's safe to decanonicalize the xor?
19589 // x s< 0 ? x^C : 0 --> subus x, C
19590 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
19591 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
19592 OpRHSConst->getAPIntValue().isSignBit())
19593 // Note that we have to rebuild the RHS constant here to ensure we
19594 // don't rely on particular values of undef lanes.
19595 return DAG.getNode(
19596 X86ISD::SUBUS, DL, VT, OpLHS,
19597 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
19602 // Try to match a min/max vector operation.
19603 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
19604 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
19605 unsigned Opc = ret.first;
19606 bool NeedSplit = ret.second;
19608 if (Opc && NeedSplit) {
19609 unsigned NumElems = VT.getVectorNumElements();
19610 // Extract the LHS vectors
19611 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
19612 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
19614 // Extract the RHS vectors
19615 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
19616 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
19618 // Create min/max for each subvector
19619 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
19620 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
19622 // Merge the result
19623 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
19625 return DAG.getNode(Opc, DL, VT, LHS, RHS);
19628 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
19629 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19630 // Check if SETCC has already been promoted
19631 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
19632 // Check that condition value type matches vselect operand type
19635 assert(Cond.getValueType().isVector() &&
19636 "vector select expects a vector selector!");
19638 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
19639 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
19641 if (!TValIsAllOnes && !FValIsAllZeros) {
19642 // Try invert the condition if true value is not all 1s and false value
19644 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
19645 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
19647 if (TValIsAllZeros || FValIsAllOnes) {
19648 SDValue CC = Cond.getOperand(2);
19649 ISD::CondCode NewCC =
19650 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
19651 Cond.getOperand(0).getValueType().isInteger());
19652 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
19653 std::swap(LHS, RHS);
19654 TValIsAllOnes = FValIsAllOnes;
19655 FValIsAllZeros = TValIsAllZeros;
19659 if (TValIsAllOnes || FValIsAllZeros) {
19662 if (TValIsAllOnes && FValIsAllZeros)
19664 else if (TValIsAllOnes)
19665 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
19666 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
19667 else if (FValIsAllZeros)
19668 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
19669 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
19671 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
19675 // Try to fold this VSELECT into a MOVSS/MOVSD
19676 if (N->getOpcode() == ISD::VSELECT &&
19677 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
19678 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
19679 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
19680 bool CanFold = false;
19681 unsigned NumElems = Cond.getNumOperands();
19685 if (isZero(Cond.getOperand(0))) {
19688 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
19689 // fold (vselect <0,-1> -> (movsd A, B)
19690 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19691 CanFold = isAllOnes(Cond.getOperand(i));
19692 } else if (isAllOnes(Cond.getOperand(0))) {
19696 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
19697 // fold (vselect <-1,0> -> (movsd B, A)
19698 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19699 CanFold = isZero(Cond.getOperand(i));
19703 if (VT == MVT::v4i32 || VT == MVT::v4f32)
19704 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
19705 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
19708 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
19709 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
19710 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
19711 // (v2i64 (bitcast B)))))
19713 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
19714 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
19715 // (v2f64 (bitcast B)))))
19717 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
19718 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
19719 // (v2i64 (bitcast A)))))
19721 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
19722 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
19723 // (v2f64 (bitcast A)))))
19725 CanFold = (isZero(Cond.getOperand(0)) &&
19726 isZero(Cond.getOperand(1)) &&
19727 isAllOnes(Cond.getOperand(2)) &&
19728 isAllOnes(Cond.getOperand(3)));
19730 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
19731 isAllOnes(Cond.getOperand(1)) &&
19732 isZero(Cond.getOperand(2)) &&
19733 isZero(Cond.getOperand(3))) {
19735 std::swap(LHS, RHS);
19739 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
19740 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
19741 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
19742 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
19744 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
19750 // If we know that this node is legal then we know that it is going to be
19751 // matched by one of the SSE/AVX BLEND instructions. These instructions only
19752 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
19753 // to simplify previous instructions.
19754 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
19755 !DCI.isBeforeLegalize() &&
19756 // We explicitly check against v8i16 and v16i16 because, although
19757 // they're marked as Custom, they might only be legal when Cond is a
19758 // build_vector of constants. This will be taken care in a later
19760 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
19761 VT != MVT::v8i16)) {
19762 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
19764 // Don't optimize vector selects that map to mask-registers.
19768 // Check all uses of that condition operand to check whether it will be
19769 // consumed by non-BLEND instructions, which may depend on all bits are set
19771 for (SDNode::use_iterator I = Cond->use_begin(),
19772 E = Cond->use_end(); I != E; ++I)
19773 if (I->getOpcode() != ISD::VSELECT)
19774 // TODO: Add other opcodes eventually lowered into BLEND.
19777 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
19778 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
19780 APInt KnownZero, KnownOne;
19781 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
19782 DCI.isBeforeLegalizeOps());
19783 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
19784 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
19785 DCI.CommitTargetLoweringOpt(TLO);
19788 // We should generate an X86ISD::BLENDI from a vselect if its argument
19789 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
19790 // constants. This specific pattern gets generated when we split a
19791 // selector for a 512 bit vector in a machine without AVX512 (but with
19792 // 256-bit vectors), during legalization:
19794 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
19796 // Iff we find this pattern and the build_vectors are built from
19797 // constants, we translate the vselect into a shuffle_vector that we
19798 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
19799 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
19800 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
19801 if (Shuffle.getNode())
19808 // Check whether a boolean test is testing a boolean value generated by
19809 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
19812 // Simplify the following patterns:
19813 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
19814 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
19815 // to (Op EFLAGS Cond)
19817 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
19818 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
19819 // to (Op EFLAGS !Cond)
19821 // where Op could be BRCOND or CMOV.
19823 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
19824 // Quit if not CMP and SUB with its value result used.
19825 if (Cmp.getOpcode() != X86ISD::CMP &&
19826 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
19829 // Quit if not used as a boolean value.
19830 if (CC != X86::COND_E && CC != X86::COND_NE)
19833 // Check CMP operands. One of them should be 0 or 1 and the other should be
19834 // an SetCC or extended from it.
19835 SDValue Op1 = Cmp.getOperand(0);
19836 SDValue Op2 = Cmp.getOperand(1);
19839 const ConstantSDNode* C = nullptr;
19840 bool needOppositeCond = (CC == X86::COND_E);
19841 bool checkAgainstTrue = false; // Is it a comparison against 1?
19843 if ((C = dyn_cast<ConstantSDNode>(Op1)))
19845 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
19847 else // Quit if all operands are not constants.
19850 if (C->getZExtValue() == 1) {
19851 needOppositeCond = !needOppositeCond;
19852 checkAgainstTrue = true;
19853 } else if (C->getZExtValue() != 0)
19854 // Quit if the constant is neither 0 or 1.
19857 bool truncatedToBoolWithAnd = false;
19858 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
19859 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
19860 SetCC.getOpcode() == ISD::TRUNCATE ||
19861 SetCC.getOpcode() == ISD::AND) {
19862 if (SetCC.getOpcode() == ISD::AND) {
19864 ConstantSDNode *CS;
19865 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
19866 CS->getZExtValue() == 1)
19868 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
19869 CS->getZExtValue() == 1)
19873 SetCC = SetCC.getOperand(OpIdx);
19874 truncatedToBoolWithAnd = true;
19876 SetCC = SetCC.getOperand(0);
19879 switch (SetCC.getOpcode()) {
19880 case X86ISD::SETCC_CARRY:
19881 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
19882 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
19883 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
19884 // truncated to i1 using 'and'.
19885 if (checkAgainstTrue && !truncatedToBoolWithAnd)
19887 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
19888 "Invalid use of SETCC_CARRY!");
19890 case X86ISD::SETCC:
19891 // Set the condition code or opposite one if necessary.
19892 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
19893 if (needOppositeCond)
19894 CC = X86::GetOppositeBranchCondition(CC);
19895 return SetCC.getOperand(1);
19896 case X86ISD::CMOV: {
19897 // Check whether false/true value has canonical one, i.e. 0 or 1.
19898 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
19899 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
19900 // Quit if true value is not a constant.
19903 // Quit if false value is not a constant.
19905 SDValue Op = SetCC.getOperand(0);
19906 // Skip 'zext' or 'trunc' node.
19907 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
19908 Op.getOpcode() == ISD::TRUNCATE)
19909 Op = Op.getOperand(0);
19910 // A special case for rdrand/rdseed, where 0 is set if false cond is
19912 if ((Op.getOpcode() != X86ISD::RDRAND &&
19913 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
19916 // Quit if false value is not the constant 0 or 1.
19917 bool FValIsFalse = true;
19918 if (FVal && FVal->getZExtValue() != 0) {
19919 if (FVal->getZExtValue() != 1)
19921 // If FVal is 1, opposite cond is needed.
19922 needOppositeCond = !needOppositeCond;
19923 FValIsFalse = false;
19925 // Quit if TVal is not the constant opposite of FVal.
19926 if (FValIsFalse && TVal->getZExtValue() != 1)
19928 if (!FValIsFalse && TVal->getZExtValue() != 0)
19930 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
19931 if (needOppositeCond)
19932 CC = X86::GetOppositeBranchCondition(CC);
19933 return SetCC.getOperand(3);
19940 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
19941 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
19942 TargetLowering::DAGCombinerInfo &DCI,
19943 const X86Subtarget *Subtarget) {
19946 // If the flag operand isn't dead, don't touch this CMOV.
19947 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
19950 SDValue FalseOp = N->getOperand(0);
19951 SDValue TrueOp = N->getOperand(1);
19952 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
19953 SDValue Cond = N->getOperand(3);
19955 if (CC == X86::COND_E || CC == X86::COND_NE) {
19956 switch (Cond.getOpcode()) {
19960 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
19961 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
19962 return (CC == X86::COND_E) ? FalseOp : TrueOp;
19968 Flags = checkBoolTestSetCCCombine(Cond, CC);
19969 if (Flags.getNode() &&
19970 // Extra check as FCMOV only supports a subset of X86 cond.
19971 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
19972 SDValue Ops[] = { FalseOp, TrueOp,
19973 DAG.getConstant(CC, MVT::i8), Flags };
19974 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
19977 // If this is a select between two integer constants, try to do some
19978 // optimizations. Note that the operands are ordered the opposite of SELECT
19980 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
19981 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
19982 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
19983 // larger than FalseC (the false value).
19984 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
19985 CC = X86::GetOppositeBranchCondition(CC);
19986 std::swap(TrueC, FalseC);
19987 std::swap(TrueOp, FalseOp);
19990 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
19991 // This is efficient for any integer data type (including i8/i16) and
19993 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
19994 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19995 DAG.getConstant(CC, MVT::i8), Cond);
19997 // Zero extend the condition if needed.
19998 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
20000 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20001 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
20002 DAG.getConstant(ShAmt, MVT::i8));
20003 if (N->getNumValues() == 2) // Dead flag value?
20004 return DCI.CombineTo(N, Cond, SDValue());
20008 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
20009 // for any integer data type, including i8/i16.
20010 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20011 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20012 DAG.getConstant(CC, MVT::i8), Cond);
20014 // Zero extend the condition if needed.
20015 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20016 FalseC->getValueType(0), Cond);
20017 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20018 SDValue(FalseC, 0));
20020 if (N->getNumValues() == 2) // Dead flag value?
20021 return DCI.CombineTo(N, Cond, SDValue());
20025 // Optimize cases that will turn into an LEA instruction. This requires
20026 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20027 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20028 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20029 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20031 bool isFastMultiplier = false;
20033 switch ((unsigned char)Diff) {
20035 case 1: // result = add base, cond
20036 case 2: // result = lea base( , cond*2)
20037 case 3: // result = lea base(cond, cond*2)
20038 case 4: // result = lea base( , cond*4)
20039 case 5: // result = lea base(cond, cond*4)
20040 case 8: // result = lea base( , cond*8)
20041 case 9: // result = lea base(cond, cond*8)
20042 isFastMultiplier = true;
20047 if (isFastMultiplier) {
20048 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20049 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20050 DAG.getConstant(CC, MVT::i8), Cond);
20051 // Zero extend the condition if needed.
20052 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20054 // Scale the condition by the difference.
20056 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20057 DAG.getConstant(Diff, Cond.getValueType()));
20059 // Add the base if non-zero.
20060 if (FalseC->getAPIntValue() != 0)
20061 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20062 SDValue(FalseC, 0));
20063 if (N->getNumValues() == 2) // Dead flag value?
20064 return DCI.CombineTo(N, Cond, SDValue());
20071 // Handle these cases:
20072 // (select (x != c), e, c) -> select (x != c), e, x),
20073 // (select (x == c), c, e) -> select (x == c), x, e)
20074 // where the c is an integer constant, and the "select" is the combination
20075 // of CMOV and CMP.
20077 // The rationale for this change is that the conditional-move from a constant
20078 // needs two instructions, however, conditional-move from a register needs
20079 // only one instruction.
20081 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
20082 // some instruction-combining opportunities. This opt needs to be
20083 // postponed as late as possible.
20085 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
20086 // the DCI.xxxx conditions are provided to postpone the optimization as
20087 // late as possible.
20089 ConstantSDNode *CmpAgainst = nullptr;
20090 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
20091 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
20092 !isa<ConstantSDNode>(Cond.getOperand(0))) {
20094 if (CC == X86::COND_NE &&
20095 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
20096 CC = X86::GetOppositeBranchCondition(CC);
20097 std::swap(TrueOp, FalseOp);
20100 if (CC == X86::COND_E &&
20101 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
20102 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
20103 DAG.getConstant(CC, MVT::i8), Cond };
20104 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
20112 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
20113 const X86Subtarget *Subtarget) {
20114 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
20116 default: return SDValue();
20117 // SSE/AVX/AVX2 blend intrinsics.
20118 case Intrinsic::x86_avx2_pblendvb:
20119 case Intrinsic::x86_avx2_pblendw:
20120 case Intrinsic::x86_avx2_pblendd_128:
20121 case Intrinsic::x86_avx2_pblendd_256:
20122 // Don't try to simplify this intrinsic if we don't have AVX2.
20123 if (!Subtarget->hasAVX2())
20126 case Intrinsic::x86_avx_blend_pd_256:
20127 case Intrinsic::x86_avx_blend_ps_256:
20128 case Intrinsic::x86_avx_blendv_pd_256:
20129 case Intrinsic::x86_avx_blendv_ps_256:
20130 // Don't try to simplify this intrinsic if we don't have AVX.
20131 if (!Subtarget->hasAVX())
20134 case Intrinsic::x86_sse41_pblendw:
20135 case Intrinsic::x86_sse41_blendpd:
20136 case Intrinsic::x86_sse41_blendps:
20137 case Intrinsic::x86_sse41_blendvps:
20138 case Intrinsic::x86_sse41_blendvpd:
20139 case Intrinsic::x86_sse41_pblendvb: {
20140 SDValue Op0 = N->getOperand(1);
20141 SDValue Op1 = N->getOperand(2);
20142 SDValue Mask = N->getOperand(3);
20144 // Don't try to simplify this intrinsic if we don't have SSE4.1.
20145 if (!Subtarget->hasSSE41())
20148 // fold (blend A, A, Mask) -> A
20151 // fold (blend A, B, allZeros) -> A
20152 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
20154 // fold (blend A, B, allOnes) -> B
20155 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
20158 // Simplify the case where the mask is a constant i32 value.
20159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
20160 if (C->isNullValue())
20162 if (C->isAllOnesValue())
20169 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
20170 case Intrinsic::x86_sse2_psrai_w:
20171 case Intrinsic::x86_sse2_psrai_d:
20172 case Intrinsic::x86_avx2_psrai_w:
20173 case Intrinsic::x86_avx2_psrai_d:
20174 case Intrinsic::x86_sse2_psra_w:
20175 case Intrinsic::x86_sse2_psra_d:
20176 case Intrinsic::x86_avx2_psra_w:
20177 case Intrinsic::x86_avx2_psra_d: {
20178 SDValue Op0 = N->getOperand(1);
20179 SDValue Op1 = N->getOperand(2);
20180 EVT VT = Op0.getValueType();
20181 assert(VT.isVector() && "Expected a vector type!");
20183 if (isa<BuildVectorSDNode>(Op1))
20184 Op1 = Op1.getOperand(0);
20186 if (!isa<ConstantSDNode>(Op1))
20189 EVT SVT = VT.getVectorElementType();
20190 unsigned SVTBits = SVT.getSizeInBits();
20192 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
20193 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
20194 uint64_t ShAmt = C.getZExtValue();
20196 // Don't try to convert this shift into a ISD::SRA if the shift
20197 // count is bigger than or equal to the element size.
20198 if (ShAmt >= SVTBits)
20201 // Trivial case: if the shift count is zero, then fold this
20202 // into the first operand.
20206 // Replace this packed shift intrinsic with a target independent
20208 SDValue Splat = DAG.getConstant(C, VT);
20209 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
20214 /// PerformMulCombine - Optimize a single multiply with constant into two
20215 /// in order to implement it with two cheaper instructions, e.g.
20216 /// LEA + SHL, LEA + LEA.
20217 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
20218 TargetLowering::DAGCombinerInfo &DCI) {
20219 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
20222 EVT VT = N->getValueType(0);
20223 if (VT != MVT::i64)
20226 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
20229 uint64_t MulAmt = C->getZExtValue();
20230 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
20233 uint64_t MulAmt1 = 0;
20234 uint64_t MulAmt2 = 0;
20235 if ((MulAmt % 9) == 0) {
20237 MulAmt2 = MulAmt / 9;
20238 } else if ((MulAmt % 5) == 0) {
20240 MulAmt2 = MulAmt / 5;
20241 } else if ((MulAmt % 3) == 0) {
20243 MulAmt2 = MulAmt / 3;
20246 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
20249 if (isPowerOf2_64(MulAmt2) &&
20250 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
20251 // If second multiplifer is pow2, issue it first. We want the multiply by
20252 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
20254 std::swap(MulAmt1, MulAmt2);
20257 if (isPowerOf2_64(MulAmt1))
20258 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
20259 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
20261 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
20262 DAG.getConstant(MulAmt1, VT));
20264 if (isPowerOf2_64(MulAmt2))
20265 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
20266 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
20268 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
20269 DAG.getConstant(MulAmt2, VT));
20271 // Do not add new nodes to DAG combiner worklist.
20272 DCI.CombineTo(N, NewMul, false);
20277 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
20278 SDValue N0 = N->getOperand(0);
20279 SDValue N1 = N->getOperand(1);
20280 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
20281 EVT VT = N0.getValueType();
20283 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
20284 // since the result of setcc_c is all zero's or all ones.
20285 if (VT.isInteger() && !VT.isVector() &&
20286 N1C && N0.getOpcode() == ISD::AND &&
20287 N0.getOperand(1).getOpcode() == ISD::Constant) {
20288 SDValue N00 = N0.getOperand(0);
20289 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
20290 ((N00.getOpcode() == ISD::ANY_EXTEND ||
20291 N00.getOpcode() == ISD::ZERO_EXTEND) &&
20292 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
20293 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
20294 APInt ShAmt = N1C->getAPIntValue();
20295 Mask = Mask.shl(ShAmt);
20297 return DAG.getNode(ISD::AND, SDLoc(N), VT,
20298 N00, DAG.getConstant(Mask, VT));
20302 // Hardware support for vector shifts is sparse which makes us scalarize the
20303 // vector operations in many cases. Also, on sandybridge ADD is faster than
20305 // (shl V, 1) -> add V,V
20306 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
20307 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
20308 assert(N0.getValueType().isVector() && "Invalid vector shift type");
20309 // We shift all of the values by one. In many cases we do not have
20310 // hardware support for this operation. This is better expressed as an ADD
20312 if (N1SplatC->getZExtValue() == 1)
20313 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
20319 /// \brief Returns a vector of 0s if the node in input is a vector logical
20320 /// shift by a constant amount which is known to be bigger than or equal
20321 /// to the vector element size in bits.
20322 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
20323 const X86Subtarget *Subtarget) {
20324 EVT VT = N->getValueType(0);
20326 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
20327 (!Subtarget->hasInt256() ||
20328 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
20331 SDValue Amt = N->getOperand(1);
20333 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
20334 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
20335 APInt ShiftAmt = AmtSplat->getAPIntValue();
20336 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
20338 // SSE2/AVX2 logical shifts always return a vector of 0s
20339 // if the shift amount is bigger than or equal to
20340 // the element size. The constant shift amount will be
20341 // encoded as a 8-bit immediate.
20342 if (ShiftAmt.trunc(8).uge(MaxAmount))
20343 return getZeroVector(VT, Subtarget, DAG, DL);
20349 /// PerformShiftCombine - Combine shifts.
20350 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
20351 TargetLowering::DAGCombinerInfo &DCI,
20352 const X86Subtarget *Subtarget) {
20353 if (N->getOpcode() == ISD::SHL) {
20354 SDValue V = PerformSHLCombine(N, DAG);
20355 if (V.getNode()) return V;
20358 if (N->getOpcode() != ISD::SRA) {
20359 // Try to fold this logical shift into a zero vector.
20360 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
20361 if (V.getNode()) return V;
20367 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
20368 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
20369 // and friends. Likewise for OR -> CMPNEQSS.
20370 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
20371 TargetLowering::DAGCombinerInfo &DCI,
20372 const X86Subtarget *Subtarget) {
20375 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
20376 // we're requiring SSE2 for both.
20377 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
20378 SDValue N0 = N->getOperand(0);
20379 SDValue N1 = N->getOperand(1);
20380 SDValue CMP0 = N0->getOperand(1);
20381 SDValue CMP1 = N1->getOperand(1);
20384 // The SETCCs should both refer to the same CMP.
20385 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
20388 SDValue CMP00 = CMP0->getOperand(0);
20389 SDValue CMP01 = CMP0->getOperand(1);
20390 EVT VT = CMP00.getValueType();
20392 if (VT == MVT::f32 || VT == MVT::f64) {
20393 bool ExpectingFlags = false;
20394 // Check for any users that want flags:
20395 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
20396 !ExpectingFlags && UI != UE; ++UI)
20397 switch (UI->getOpcode()) {
20402 ExpectingFlags = true;
20404 case ISD::CopyToReg:
20405 case ISD::SIGN_EXTEND:
20406 case ISD::ZERO_EXTEND:
20407 case ISD::ANY_EXTEND:
20411 if (!ExpectingFlags) {
20412 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
20413 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
20415 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
20416 X86::CondCode tmp = cc0;
20421 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
20422 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
20423 // FIXME: need symbolic constants for these magic numbers.
20424 // See X86ATTInstPrinter.cpp:printSSECC().
20425 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
20426 if (Subtarget->hasAVX512()) {
20427 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
20428 CMP01, DAG.getConstant(x86cc, MVT::i8));
20429 if (N->getValueType(0) != MVT::i1)
20430 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
20434 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
20435 CMP00.getValueType(), CMP00, CMP01,
20436 DAG.getConstant(x86cc, MVT::i8));
20438 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
20439 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
20441 if (is64BitFP && !Subtarget->is64Bit()) {
20442 // On a 32-bit target, we cannot bitcast the 64-bit float to a
20443 // 64-bit integer, since that's not a legal type. Since
20444 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
20445 // bits, but can do this little dance to extract the lowest 32 bits
20446 // and work with those going forward.
20447 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
20449 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
20451 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
20452 Vector32, DAG.getIntPtrConstant(0));
20456 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
20457 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
20458 DAG.getConstant(1, IntVT));
20459 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
20460 return OneBitOfTruth;
20468 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
20469 /// so it can be folded inside ANDNP.
20470 static bool CanFoldXORWithAllOnes(const SDNode *N) {
20471 EVT VT = N->getValueType(0);
20473 // Match direct AllOnes for 128 and 256-bit vectors
20474 if (ISD::isBuildVectorAllOnes(N))
20477 // Look through a bit convert.
20478 if (N->getOpcode() == ISD::BITCAST)
20479 N = N->getOperand(0).getNode();
20481 // Sometimes the operand may come from a insert_subvector building a 256-bit
20483 if (VT.is256BitVector() &&
20484 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
20485 SDValue V1 = N->getOperand(0);
20486 SDValue V2 = N->getOperand(1);
20488 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
20489 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
20490 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
20491 ISD::isBuildVectorAllOnes(V2.getNode()))
20498 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
20499 // register. In most cases we actually compare or select YMM-sized registers
20500 // and mixing the two types creates horrible code. This method optimizes
20501 // some of the transition sequences.
20502 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
20503 TargetLowering::DAGCombinerInfo &DCI,
20504 const X86Subtarget *Subtarget) {
20505 EVT VT = N->getValueType(0);
20506 if (!VT.is256BitVector())
20509 assert((N->getOpcode() == ISD::ANY_EXTEND ||
20510 N->getOpcode() == ISD::ZERO_EXTEND ||
20511 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
20513 SDValue Narrow = N->getOperand(0);
20514 EVT NarrowVT = Narrow->getValueType(0);
20515 if (!NarrowVT.is128BitVector())
20518 if (Narrow->getOpcode() != ISD::XOR &&
20519 Narrow->getOpcode() != ISD::AND &&
20520 Narrow->getOpcode() != ISD::OR)
20523 SDValue N0 = Narrow->getOperand(0);
20524 SDValue N1 = Narrow->getOperand(1);
20527 // The Left side has to be a trunc.
20528 if (N0.getOpcode() != ISD::TRUNCATE)
20531 // The type of the truncated inputs.
20532 EVT WideVT = N0->getOperand(0)->getValueType(0);
20536 // The right side has to be a 'trunc' or a constant vector.
20537 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
20538 ConstantSDNode *RHSConstSplat = nullptr;
20539 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
20540 RHSConstSplat = RHSBV->getConstantSplatNode();
20541 if (!RHSTrunc && !RHSConstSplat)
20544 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20546 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
20549 // Set N0 and N1 to hold the inputs to the new wide operation.
20550 N0 = N0->getOperand(0);
20551 if (RHSConstSplat) {
20552 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
20553 SDValue(RHSConstSplat, 0));
20554 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
20555 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
20556 } else if (RHSTrunc) {
20557 N1 = N1->getOperand(0);
20560 // Generate the wide operation.
20561 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
20562 unsigned Opcode = N->getOpcode();
20564 case ISD::ANY_EXTEND:
20566 case ISD::ZERO_EXTEND: {
20567 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
20568 APInt Mask = APInt::getAllOnesValue(InBits);
20569 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
20570 return DAG.getNode(ISD::AND, DL, VT,
20571 Op, DAG.getConstant(Mask, VT));
20573 case ISD::SIGN_EXTEND:
20574 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
20575 Op, DAG.getValueType(NarrowVT));
20577 llvm_unreachable("Unexpected opcode");
20581 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
20582 TargetLowering::DAGCombinerInfo &DCI,
20583 const X86Subtarget *Subtarget) {
20584 EVT VT = N->getValueType(0);
20585 if (DCI.isBeforeLegalizeOps())
20588 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20592 // Create BEXTR instructions
20593 // BEXTR is ((X >> imm) & (2**size-1))
20594 if (VT == MVT::i32 || VT == MVT::i64) {
20595 SDValue N0 = N->getOperand(0);
20596 SDValue N1 = N->getOperand(1);
20599 // Check for BEXTR.
20600 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
20601 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
20602 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
20603 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
20604 if (MaskNode && ShiftNode) {
20605 uint64_t Mask = MaskNode->getZExtValue();
20606 uint64_t Shift = ShiftNode->getZExtValue();
20607 if (isMask_64(Mask)) {
20608 uint64_t MaskSize = CountPopulation_64(Mask);
20609 if (Shift + MaskSize <= VT.getSizeInBits())
20610 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
20611 DAG.getConstant(Shift | (MaskSize << 8), VT));
20619 // Want to form ANDNP nodes:
20620 // 1) In the hopes of then easily combining them with OR and AND nodes
20621 // to form PBLEND/PSIGN.
20622 // 2) To match ANDN packed intrinsics
20623 if (VT != MVT::v2i64 && VT != MVT::v4i64)
20626 SDValue N0 = N->getOperand(0);
20627 SDValue N1 = N->getOperand(1);
20630 // Check LHS for vnot
20631 if (N0.getOpcode() == ISD::XOR &&
20632 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
20633 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
20634 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
20636 // Check RHS for vnot
20637 if (N1.getOpcode() == ISD::XOR &&
20638 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
20639 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
20640 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
20645 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
20646 TargetLowering::DAGCombinerInfo &DCI,
20647 const X86Subtarget *Subtarget) {
20648 if (DCI.isBeforeLegalizeOps())
20651 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20655 SDValue N0 = N->getOperand(0);
20656 SDValue N1 = N->getOperand(1);
20657 EVT VT = N->getValueType(0);
20659 // look for psign/blend
20660 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
20661 if (!Subtarget->hasSSSE3() ||
20662 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
20665 // Canonicalize pandn to RHS
20666 if (N0.getOpcode() == X86ISD::ANDNP)
20668 // or (and (m, y), (pandn m, x))
20669 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
20670 SDValue Mask = N1.getOperand(0);
20671 SDValue X = N1.getOperand(1);
20673 if (N0.getOperand(0) == Mask)
20674 Y = N0.getOperand(1);
20675 if (N0.getOperand(1) == Mask)
20676 Y = N0.getOperand(0);
20678 // Check to see if the mask appeared in both the AND and ANDNP and
20682 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
20683 // Look through mask bitcast.
20684 if (Mask.getOpcode() == ISD::BITCAST)
20685 Mask = Mask.getOperand(0);
20686 if (X.getOpcode() == ISD::BITCAST)
20687 X = X.getOperand(0);
20688 if (Y.getOpcode() == ISD::BITCAST)
20689 Y = Y.getOperand(0);
20691 EVT MaskVT = Mask.getValueType();
20693 // Validate that the Mask operand is a vector sra node.
20694 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
20695 // there is no psrai.b
20696 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
20697 unsigned SraAmt = ~0;
20698 if (Mask.getOpcode() == ISD::SRA) {
20699 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
20700 if (auto *AmtConst = AmtBV->getConstantSplatNode())
20701 SraAmt = AmtConst->getZExtValue();
20702 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
20703 SDValue SraC = Mask.getOperand(1);
20704 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
20706 if ((SraAmt + 1) != EltBits)
20711 // Now we know we at least have a plendvb with the mask val. See if
20712 // we can form a psignb/w/d.
20713 // psign = x.type == y.type == mask.type && y = sub(0, x);
20714 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
20715 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
20716 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
20717 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
20718 "Unsupported VT for PSIGN");
20719 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
20720 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20722 // PBLENDVB only available on SSE 4.1
20723 if (!Subtarget->hasSSE41())
20726 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
20728 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
20729 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
20730 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
20731 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
20732 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20736 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
20739 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
20740 MachineFunction &MF = DAG.getMachineFunction();
20741 bool OptForSize = MF.getFunction()->getAttributes().
20742 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
20744 // SHLD/SHRD instructions have lower register pressure, but on some
20745 // platforms they have higher latency than the equivalent
20746 // series of shifts/or that would otherwise be generated.
20747 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
20748 // have higher latencies and we are not optimizing for size.
20749 if (!OptForSize && Subtarget->isSHLDSlow())
20752 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
20754 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
20756 if (!N0.hasOneUse() || !N1.hasOneUse())
20759 SDValue ShAmt0 = N0.getOperand(1);
20760 if (ShAmt0.getValueType() != MVT::i8)
20762 SDValue ShAmt1 = N1.getOperand(1);
20763 if (ShAmt1.getValueType() != MVT::i8)
20765 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
20766 ShAmt0 = ShAmt0.getOperand(0);
20767 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
20768 ShAmt1 = ShAmt1.getOperand(0);
20771 unsigned Opc = X86ISD::SHLD;
20772 SDValue Op0 = N0.getOperand(0);
20773 SDValue Op1 = N1.getOperand(0);
20774 if (ShAmt0.getOpcode() == ISD::SUB) {
20775 Opc = X86ISD::SHRD;
20776 std::swap(Op0, Op1);
20777 std::swap(ShAmt0, ShAmt1);
20780 unsigned Bits = VT.getSizeInBits();
20781 if (ShAmt1.getOpcode() == ISD::SUB) {
20782 SDValue Sum = ShAmt1.getOperand(0);
20783 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
20784 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
20785 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
20786 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
20787 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
20788 return DAG.getNode(Opc, DL, VT,
20790 DAG.getNode(ISD::TRUNCATE, DL,
20793 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
20794 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
20796 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
20797 return DAG.getNode(Opc, DL, VT,
20798 N0.getOperand(0), N1.getOperand(0),
20799 DAG.getNode(ISD::TRUNCATE, DL,
20806 // Generate NEG and CMOV for integer abs.
20807 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
20808 EVT VT = N->getValueType(0);
20810 // Since X86 does not have CMOV for 8-bit integer, we don't convert
20811 // 8-bit integer abs to NEG and CMOV.
20812 if (VT.isInteger() && VT.getSizeInBits() == 8)
20815 SDValue N0 = N->getOperand(0);
20816 SDValue N1 = N->getOperand(1);
20819 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
20820 // and change it to SUB and CMOV.
20821 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
20822 N0.getOpcode() == ISD::ADD &&
20823 N0.getOperand(1) == N1 &&
20824 N1.getOpcode() == ISD::SRA &&
20825 N1.getOperand(0) == N0.getOperand(0))
20826 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
20827 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
20828 // Generate SUB & CMOV.
20829 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
20830 DAG.getConstant(0, VT), N0.getOperand(0));
20832 SDValue Ops[] = { N0.getOperand(0), Neg,
20833 DAG.getConstant(X86::COND_GE, MVT::i8),
20834 SDValue(Neg.getNode(), 1) };
20835 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
20840 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
20841 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
20842 TargetLowering::DAGCombinerInfo &DCI,
20843 const X86Subtarget *Subtarget) {
20844 if (DCI.isBeforeLegalizeOps())
20847 if (Subtarget->hasCMov()) {
20848 SDValue RV = performIntegerAbsCombine(N, DAG);
20856 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
20857 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
20858 TargetLowering::DAGCombinerInfo &DCI,
20859 const X86Subtarget *Subtarget) {
20860 LoadSDNode *Ld = cast<LoadSDNode>(N);
20861 EVT RegVT = Ld->getValueType(0);
20862 EVT MemVT = Ld->getMemoryVT();
20864 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20865 unsigned RegSz = RegVT.getSizeInBits();
20867 // On Sandybridge unaligned 256bit loads are inefficient.
20868 ISD::LoadExtType Ext = Ld->getExtensionType();
20869 unsigned Alignment = Ld->getAlignment();
20870 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
20871 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
20872 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
20873 unsigned NumElems = RegVT.getVectorNumElements();
20877 SDValue Ptr = Ld->getBasePtr();
20878 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
20880 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20882 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20883 Ld->getPointerInfo(), Ld->isVolatile(),
20884 Ld->isNonTemporal(), Ld->isInvariant(),
20886 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20887 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20888 Ld->getPointerInfo(), Ld->isVolatile(),
20889 Ld->isNonTemporal(), Ld->isInvariant(),
20890 std::min(16U, Alignment));
20891 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20893 Load2.getValue(1));
20895 SDValue NewVec = DAG.getUNDEF(RegVT);
20896 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
20897 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
20898 return DCI.CombineTo(N, NewVec, TF, true);
20901 // If this is a vector EXT Load then attempt to optimize it using a
20902 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
20903 // expansion is still better than scalar code.
20904 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
20905 // emit a shuffle and a arithmetic shift.
20906 // TODO: It is possible to support ZExt by zeroing the undef values
20907 // during the shuffle phase or after the shuffle.
20908 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
20909 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
20910 assert(MemVT != RegVT && "Cannot extend to the same type");
20911 assert(MemVT.isVector() && "Must load a vector from memory");
20913 unsigned NumElems = RegVT.getVectorNumElements();
20914 unsigned MemSz = MemVT.getSizeInBits();
20915 assert(RegSz > MemSz && "Register size must be greater than the mem size");
20917 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
20920 // All sizes must be a power of two.
20921 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
20924 // Attempt to load the original value using scalar loads.
20925 // Find the largest scalar type that divides the total loaded size.
20926 MVT SclrLoadTy = MVT::i8;
20927 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
20928 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
20929 MVT Tp = (MVT::SimpleValueType)tp;
20930 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
20935 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
20936 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
20938 SclrLoadTy = MVT::f64;
20940 // Calculate the number of scalar loads that we need to perform
20941 // in order to load our vector from memory.
20942 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
20943 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
20946 unsigned loadRegZize = RegSz;
20947 if (Ext == ISD::SEXTLOAD && RegSz == 256)
20950 // Represent our vector as a sequence of elements which are the
20951 // largest scalar that we can load.
20952 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
20953 loadRegZize/SclrLoadTy.getSizeInBits());
20955 // Represent the data using the same element type that is stored in
20956 // memory. In practice, we ''widen'' MemVT.
20958 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20959 loadRegZize/MemVT.getScalarType().getSizeInBits());
20961 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
20962 "Invalid vector type");
20964 // We can't shuffle using an illegal type.
20965 if (!TLI.isTypeLegal(WideVecVT))
20968 SmallVector<SDValue, 8> Chains;
20969 SDValue Ptr = Ld->getBasePtr();
20970 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
20971 TLI.getPointerTy());
20972 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
20974 for (unsigned i = 0; i < NumLoads; ++i) {
20975 // Perform a single load.
20976 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
20977 Ptr, Ld->getPointerInfo(),
20978 Ld->isVolatile(), Ld->isNonTemporal(),
20979 Ld->isInvariant(), Ld->getAlignment());
20980 Chains.push_back(ScalarLoad.getValue(1));
20981 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
20982 // another round of DAGCombining.
20984 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
20986 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
20987 ScalarLoad, DAG.getIntPtrConstant(i));
20989 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20992 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
20994 // Bitcast the loaded value to a vector of the original element type, in
20995 // the size of the target vector type.
20996 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
20997 unsigned SizeRatio = RegSz/MemSz;
20999 if (Ext == ISD::SEXTLOAD) {
21000 // If we have SSE4.1 we can directly emit a VSEXT node.
21001 if (Subtarget->hasSSE41()) {
21002 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
21003 return DCI.CombineTo(N, Sext, TF, true);
21006 // Otherwise we'll shuffle the small elements in the high bits of the
21007 // larger type and perform an arithmetic shift. If the shift is not legal
21008 // it's better to scalarize.
21009 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
21012 // Redistribute the loaded elements into the different locations.
21013 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21014 for (unsigned i = 0; i != NumElems; ++i)
21015 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
21017 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
21018 DAG.getUNDEF(WideVecVT),
21021 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
21023 // Build the arithmetic shift.
21024 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
21025 MemVT.getVectorElementType().getSizeInBits();
21026 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
21027 DAG.getConstant(Amt, RegVT));
21029 return DCI.CombineTo(N, Shuff, TF, true);
21032 // Redistribute the loaded elements into the different locations.
21033 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21034 for (unsigned i = 0; i != NumElems; ++i)
21035 ShuffleVec[i*SizeRatio] = i;
21037 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
21038 DAG.getUNDEF(WideVecVT),
21041 // Bitcast to the requested type.
21042 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
21043 // Replace the original load with the new sequence
21044 // and return the new chain.
21045 return DCI.CombineTo(N, Shuff, TF, true);
21051 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
21052 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
21053 const X86Subtarget *Subtarget) {
21054 StoreSDNode *St = cast<StoreSDNode>(N);
21055 EVT VT = St->getValue().getValueType();
21056 EVT StVT = St->getMemoryVT();
21058 SDValue StoredVal = St->getOperand(1);
21059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21061 // If we are saving a concatenation of two XMM registers, perform two stores.
21062 // On Sandy Bridge, 256-bit memory operations are executed by two
21063 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
21064 // memory operation.
21065 unsigned Alignment = St->getAlignment();
21066 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
21067 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
21068 StVT == VT && !IsAligned) {
21069 unsigned NumElems = VT.getVectorNumElements();
21073 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
21074 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
21076 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
21077 SDValue Ptr0 = St->getBasePtr();
21078 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
21080 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
21081 St->getPointerInfo(), St->isVolatile(),
21082 St->isNonTemporal(), Alignment);
21083 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
21084 St->getPointerInfo(), St->isVolatile(),
21085 St->isNonTemporal(),
21086 std::min(16U, Alignment));
21087 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
21090 // Optimize trunc store (of multiple scalars) to shuffle and store.
21091 // First, pack all of the elements in one place. Next, store to memory
21092 // in fewer chunks.
21093 if (St->isTruncatingStore() && VT.isVector()) {
21094 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21095 unsigned NumElems = VT.getVectorNumElements();
21096 assert(StVT != VT && "Cannot truncate to the same type");
21097 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
21098 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
21100 // From, To sizes and ElemCount must be pow of two
21101 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
21102 // We are going to use the original vector elt for storing.
21103 // Accumulated smaller vector elements must be a multiple of the store size.
21104 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
21106 unsigned SizeRatio = FromSz / ToSz;
21108 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
21110 // Create a type on which we perform the shuffle
21111 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
21112 StVT.getScalarType(), NumElems*SizeRatio);
21114 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
21116 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
21117 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21118 for (unsigned i = 0; i != NumElems; ++i)
21119 ShuffleVec[i] = i * SizeRatio;
21121 // Can't shuffle using an illegal type.
21122 if (!TLI.isTypeLegal(WideVecVT))
21125 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
21126 DAG.getUNDEF(WideVecVT),
21128 // At this point all of the data is stored at the bottom of the
21129 // register. We now need to save it to mem.
21131 // Find the largest store unit
21132 MVT StoreType = MVT::i8;
21133 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
21134 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
21135 MVT Tp = (MVT::SimpleValueType)tp;
21136 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
21140 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
21141 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
21142 (64 <= NumElems * ToSz))
21143 StoreType = MVT::f64;
21145 // Bitcast the original vector into a vector of store-size units
21146 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21147 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21148 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21149 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21150 SmallVector<SDValue, 8> Chains;
21151 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21152 TLI.getPointerTy());
21153 SDValue Ptr = St->getBasePtr();
21155 // Perform one or more big stores into memory.
21156 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21157 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21158 StoreType, ShuffWide,
21159 DAG.getIntPtrConstant(i));
21160 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21161 St->getPointerInfo(), St->isVolatile(),
21162 St->isNonTemporal(), St->getAlignment());
21163 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21164 Chains.push_back(Ch);
21167 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21170 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21171 // the FP state in cases where an emms may be missing.
21172 // A preferable solution to the general problem is to figure out the right
21173 // places to insert EMMS. This qualifies as a quick hack.
21175 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21176 if (VT.getSizeInBits() != 64)
21179 const Function *F = DAG.getMachineFunction().getFunction();
21180 bool NoImplicitFloatOps = F->getAttributes().
21181 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21182 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21183 && Subtarget->hasSSE2();
21184 if ((VT.isVector() ||
21185 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21186 isa<LoadSDNode>(St->getValue()) &&
21187 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21188 St->getChain().hasOneUse() && !St->isVolatile()) {
21189 SDNode* LdVal = St->getValue().getNode();
21190 LoadSDNode *Ld = nullptr;
21191 int TokenFactorIndex = -1;
21192 SmallVector<SDValue, 8> Ops;
21193 SDNode* ChainVal = St->getChain().getNode();
21194 // Must be a store of a load. We currently handle two cases: the load
21195 // is a direct child, and it's under an intervening TokenFactor. It is
21196 // possible to dig deeper under nested TokenFactors.
21197 if (ChainVal == LdVal)
21198 Ld = cast<LoadSDNode>(St->getChain());
21199 else if (St->getValue().hasOneUse() &&
21200 ChainVal->getOpcode() == ISD::TokenFactor) {
21201 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21202 if (ChainVal->getOperand(i).getNode() == LdVal) {
21203 TokenFactorIndex = i;
21204 Ld = cast<LoadSDNode>(St->getValue());
21206 Ops.push_back(ChainVal->getOperand(i));
21210 if (!Ld || !ISD::isNormalLoad(Ld))
21213 // If this is not the MMX case, i.e. we are just turning i64 load/store
21214 // into f64 load/store, avoid the transformation if there are multiple
21215 // uses of the loaded value.
21216 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21221 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21222 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
21224 if (Subtarget->is64Bit() || F64IsLegal) {
21225 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
21226 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
21227 Ld->getPointerInfo(), Ld->isVolatile(),
21228 Ld->isNonTemporal(), Ld->isInvariant(),
21229 Ld->getAlignment());
21230 SDValue NewChain = NewLd.getValue(1);
21231 if (TokenFactorIndex != -1) {
21232 Ops.push_back(NewChain);
21233 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21235 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
21236 St->getPointerInfo(),
21237 St->isVolatile(), St->isNonTemporal(),
21238 St->getAlignment());
21241 // Otherwise, lower to two pairs of 32-bit loads / stores.
21242 SDValue LoAddr = Ld->getBasePtr();
21243 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
21244 DAG.getConstant(4, MVT::i32));
21246 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
21247 Ld->getPointerInfo(),
21248 Ld->isVolatile(), Ld->isNonTemporal(),
21249 Ld->isInvariant(), Ld->getAlignment());
21250 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
21251 Ld->getPointerInfo().getWithOffset(4),
21252 Ld->isVolatile(), Ld->isNonTemporal(),
21254 MinAlign(Ld->getAlignment(), 4));
21256 SDValue NewChain = LoLd.getValue(1);
21257 if (TokenFactorIndex != -1) {
21258 Ops.push_back(LoLd);
21259 Ops.push_back(HiLd);
21260 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21263 LoAddr = St->getBasePtr();
21264 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
21265 DAG.getConstant(4, MVT::i32));
21267 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
21268 St->getPointerInfo(),
21269 St->isVolatile(), St->isNonTemporal(),
21270 St->getAlignment());
21271 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
21272 St->getPointerInfo().getWithOffset(4),
21274 St->isNonTemporal(),
21275 MinAlign(St->getAlignment(), 4));
21276 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
21281 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
21282 /// and return the operands for the horizontal operation in LHS and RHS. A
21283 /// horizontal operation performs the binary operation on successive elements
21284 /// of its first operand, then on successive elements of its second operand,
21285 /// returning the resulting values in a vector. For example, if
21286 /// A = < float a0, float a1, float a2, float a3 >
21288 /// B = < float b0, float b1, float b2, float b3 >
21289 /// then the result of doing a horizontal operation on A and B is
21290 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
21291 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21292 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21293 /// set to A, RHS to B, and the routine returns 'true'.
21294 /// Note that the binary operation should have the property that if one of the
21295 /// operands is UNDEF then the result is UNDEF.
21296 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21297 // Look for the following pattern: if
21298 // A = < float a0, float a1, float a2, float a3 >
21299 // B = < float b0, float b1, float b2, float b3 >
21301 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21302 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
21303 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21304 // which is A horizontal-op B.
21306 // At least one of the operands should be a vector shuffle.
21307 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21308 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
21311 MVT VT = LHS.getSimpleValueType();
21313 assert((VT.is128BitVector() || VT.is256BitVector()) &&
21314 "Unsupported vector type for horizontal add/sub");
21316 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
21317 // operate independently on 128-bit lanes.
21318 unsigned NumElts = VT.getVectorNumElements();
21319 unsigned NumLanes = VT.getSizeInBits()/128;
21320 unsigned NumLaneElts = NumElts / NumLanes;
21321 assert((NumLaneElts % 2 == 0) &&
21322 "Vector type should have an even number of elements in each lane");
21323 unsigned HalfLaneElts = NumLaneElts/2;
21325 // View LHS in the form
21326 // LHS = VECTOR_SHUFFLE A, B, LMask
21327 // If LHS is not a shuffle then pretend it is the shuffle
21328 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21329 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
21332 SmallVector<int, 16> LMask(NumElts);
21333 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21334 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21335 A = LHS.getOperand(0);
21336 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21337 B = LHS.getOperand(1);
21338 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21339 std::copy(Mask.begin(), Mask.end(), LMask.begin());
21341 if (LHS.getOpcode() != ISD::UNDEF)
21343 for (unsigned i = 0; i != NumElts; ++i)
21347 // Likewise, view RHS in the form
21348 // RHS = VECTOR_SHUFFLE C, D, RMask
21350 SmallVector<int, 16> RMask(NumElts);
21351 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21352 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
21353 C = RHS.getOperand(0);
21354 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
21355 D = RHS.getOperand(1);
21356 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
21357 std::copy(Mask.begin(), Mask.end(), RMask.begin());
21359 if (RHS.getOpcode() != ISD::UNDEF)
21361 for (unsigned i = 0; i != NumElts; ++i)
21365 // Check that the shuffles are both shuffling the same vectors.
21366 if (!(A == C && B == D) && !(A == D && B == C))
21369 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
21370 if (!A.getNode() && !B.getNode())
21373 // If A and B occur in reverse order in RHS, then "swap" them (which means
21374 // rewriting the mask).
21376 CommuteVectorShuffleMask(RMask, NumElts);
21378 // At this point LHS and RHS are equivalent to
21379 // LHS = VECTOR_SHUFFLE A, B, LMask
21380 // RHS = VECTOR_SHUFFLE A, B, RMask
21381 // Check that the masks correspond to performing a horizontal operation.
21382 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
21383 for (unsigned i = 0; i != NumLaneElts; ++i) {
21384 int LIdx = LMask[i+l], RIdx = RMask[i+l];
21386 // Ignore any UNDEF components.
21387 if (LIdx < 0 || RIdx < 0 ||
21388 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
21389 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
21392 // Check that successive elements are being operated on. If not, this is
21393 // not a horizontal operation.
21394 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
21395 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
21396 if (!(LIdx == Index && RIdx == Index + 1) &&
21397 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
21402 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
21403 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
21407 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
21408 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
21409 const X86Subtarget *Subtarget) {
21410 EVT VT = N->getValueType(0);
21411 SDValue LHS = N->getOperand(0);
21412 SDValue RHS = N->getOperand(1);
21414 // Try to synthesize horizontal adds from adds of shuffles.
21415 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21416 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21417 isHorizontalBinOp(LHS, RHS, true))
21418 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
21422 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
21423 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
21424 const X86Subtarget *Subtarget) {
21425 EVT VT = N->getValueType(0);
21426 SDValue LHS = N->getOperand(0);
21427 SDValue RHS = N->getOperand(1);
21429 // Try to synthesize horizontal subs from subs of shuffles.
21430 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21431 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21432 isHorizontalBinOp(LHS, RHS, false))
21433 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
21437 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
21438 /// X86ISD::FXOR nodes.
21439 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
21440 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
21441 // F[X]OR(0.0, x) -> x
21442 // F[X]OR(x, 0.0) -> x
21443 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21444 if (C->getValueAPF().isPosZero())
21445 return N->getOperand(1);
21446 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21447 if (C->getValueAPF().isPosZero())
21448 return N->getOperand(0);
21452 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
21453 /// X86ISD::FMAX nodes.
21454 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
21455 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
21457 // Only perform optimizations if UnsafeMath is used.
21458 if (!DAG.getTarget().Options.UnsafeFPMath)
21461 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
21462 // into FMINC and FMAXC, which are Commutative operations.
21463 unsigned NewOp = 0;
21464 switch (N->getOpcode()) {
21465 default: llvm_unreachable("unknown opcode");
21466 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
21467 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
21470 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
21471 N->getOperand(0), N->getOperand(1));
21474 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
21475 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
21476 // FAND(0.0, x) -> 0.0
21477 // FAND(x, 0.0) -> 0.0
21478 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21479 if (C->getValueAPF().isPosZero())
21480 return N->getOperand(0);
21481 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21482 if (C->getValueAPF().isPosZero())
21483 return N->getOperand(1);
21487 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
21488 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
21489 // FANDN(x, 0.0) -> 0.0
21490 // FANDN(0.0, x) -> x
21491 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21492 if (C->getValueAPF().isPosZero())
21493 return N->getOperand(1);
21494 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21495 if (C->getValueAPF().isPosZero())
21496 return N->getOperand(1);
21500 static SDValue PerformBTCombine(SDNode *N,
21502 TargetLowering::DAGCombinerInfo &DCI) {
21503 // BT ignores high bits in the bit index operand.
21504 SDValue Op1 = N->getOperand(1);
21505 if (Op1.hasOneUse()) {
21506 unsigned BitWidth = Op1.getValueSizeInBits();
21507 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
21508 APInt KnownZero, KnownOne;
21509 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
21510 !DCI.isBeforeLegalizeOps());
21511 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21512 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
21513 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
21514 DCI.CommitTargetLoweringOpt(TLO);
21519 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
21520 SDValue Op = N->getOperand(0);
21521 if (Op.getOpcode() == ISD::BITCAST)
21522 Op = Op.getOperand(0);
21523 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
21524 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
21525 VT.getVectorElementType().getSizeInBits() ==
21526 OpVT.getVectorElementType().getSizeInBits()) {
21527 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
21532 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
21533 const X86Subtarget *Subtarget) {
21534 EVT VT = N->getValueType(0);
21535 if (!VT.isVector())
21538 SDValue N0 = N->getOperand(0);
21539 SDValue N1 = N->getOperand(1);
21540 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
21543 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
21544 // both SSE and AVX2 since there is no sign-extended shift right
21545 // operation on a vector with 64-bit elements.
21546 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
21547 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
21548 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
21549 N0.getOpcode() == ISD::SIGN_EXTEND)) {
21550 SDValue N00 = N0.getOperand(0);
21552 // EXTLOAD has a better solution on AVX2,
21553 // it may be replaced with X86ISD::VSEXT node.
21554 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
21555 if (!ISD::isNormalLoad(N00.getNode()))
21558 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
21559 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
21561 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
21567 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
21568 TargetLowering::DAGCombinerInfo &DCI,
21569 const X86Subtarget *Subtarget) {
21570 if (!DCI.isBeforeLegalizeOps())
21573 if (!Subtarget->hasFp256())
21576 EVT VT = N->getValueType(0);
21577 if (VT.isVector() && VT.getSizeInBits() == 256) {
21578 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21586 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
21587 const X86Subtarget* Subtarget) {
21589 EVT VT = N->getValueType(0);
21591 // Let legalize expand this if it isn't a legal type yet.
21592 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
21595 EVT ScalarVT = VT.getScalarType();
21596 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
21597 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
21600 SDValue A = N->getOperand(0);
21601 SDValue B = N->getOperand(1);
21602 SDValue C = N->getOperand(2);
21604 bool NegA = (A.getOpcode() == ISD::FNEG);
21605 bool NegB = (B.getOpcode() == ISD::FNEG);
21606 bool NegC = (C.getOpcode() == ISD::FNEG);
21608 // Negative multiplication when NegA xor NegB
21609 bool NegMul = (NegA != NegB);
21611 A = A.getOperand(0);
21613 B = B.getOperand(0);
21615 C = C.getOperand(0);
21619 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
21621 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
21623 return DAG.getNode(Opcode, dl, VT, A, B, C);
21626 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
21627 TargetLowering::DAGCombinerInfo &DCI,
21628 const X86Subtarget *Subtarget) {
21629 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
21630 // (and (i32 x86isd::setcc_carry), 1)
21631 // This eliminates the zext. This transformation is necessary because
21632 // ISD::SETCC is always legalized to i8.
21634 SDValue N0 = N->getOperand(0);
21635 EVT VT = N->getValueType(0);
21637 if (N0.getOpcode() == ISD::AND &&
21639 N0.getOperand(0).hasOneUse()) {
21640 SDValue N00 = N0.getOperand(0);
21641 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21643 if (!C || C->getZExtValue() != 1)
21645 return DAG.getNode(ISD::AND, dl, VT,
21646 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21647 N00.getOperand(0), N00.getOperand(1)),
21648 DAG.getConstant(1, VT));
21652 if (N0.getOpcode() == ISD::TRUNCATE &&
21654 N0.getOperand(0).hasOneUse()) {
21655 SDValue N00 = N0.getOperand(0);
21656 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21657 return DAG.getNode(ISD::AND, dl, VT,
21658 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21659 N00.getOperand(0), N00.getOperand(1)),
21660 DAG.getConstant(1, VT));
21663 if (VT.is256BitVector()) {
21664 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21672 // Optimize x == -y --> x+y == 0
21673 // x != -y --> x+y != 0
21674 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
21675 const X86Subtarget* Subtarget) {
21676 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
21677 SDValue LHS = N->getOperand(0);
21678 SDValue RHS = N->getOperand(1);
21679 EVT VT = N->getValueType(0);
21682 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
21683 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
21684 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
21685 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21686 LHS.getValueType(), RHS, LHS.getOperand(1));
21687 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21688 addV, DAG.getConstant(0, addV.getValueType()), CC);
21690 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
21691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
21692 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
21693 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21694 RHS.getValueType(), LHS, RHS.getOperand(1));
21695 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21696 addV, DAG.getConstant(0, addV.getValueType()), CC);
21699 if (VT.getScalarType() == MVT::i1) {
21700 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
21701 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21702 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
21703 if (!IsSEXT0 && !IsVZero0)
21705 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
21706 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21707 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
21709 if (!IsSEXT1 && !IsVZero1)
21712 if (IsSEXT0 && IsVZero1) {
21713 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
21714 if (CC == ISD::SETEQ)
21715 return DAG.getNOT(DL, LHS.getOperand(0), VT);
21716 return LHS.getOperand(0);
21718 if (IsSEXT1 && IsVZero0) {
21719 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
21720 if (CC == ISD::SETEQ)
21721 return DAG.getNOT(DL, RHS.getOperand(0), VT);
21722 return RHS.getOperand(0);
21729 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
21730 const X86Subtarget *Subtarget) {
21732 MVT VT = N->getOperand(1)->getSimpleValueType(0);
21733 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
21734 "X86insertps is only defined for v4x32");
21736 SDValue Ld = N->getOperand(1);
21737 if (MayFoldLoad(Ld)) {
21738 // Extract the countS bits from the immediate so we can get the proper
21739 // address when narrowing the vector load to a specific element.
21740 // When the second source op is a memory address, interps doesn't use
21741 // countS and just gets an f32 from that address.
21742 unsigned DestIndex =
21743 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
21744 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
21748 // Create this as a scalar to vector to match the instruction pattern.
21749 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
21750 // countS bits are ignored when loading from memory on insertps, which
21751 // means we don't need to explicitly set them to 0.
21752 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
21753 LoadScalarToVector, N->getOperand(2));
21756 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
21757 // as "sbb reg,reg", since it can be extended without zext and produces
21758 // an all-ones bit which is more useful than 0/1 in some cases.
21759 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
21762 return DAG.getNode(ISD::AND, DL, VT,
21763 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21764 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
21765 DAG.getConstant(1, VT));
21766 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
21767 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
21768 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21769 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
21772 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
21773 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
21774 TargetLowering::DAGCombinerInfo &DCI,
21775 const X86Subtarget *Subtarget) {
21777 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
21778 SDValue EFLAGS = N->getOperand(1);
21780 if (CC == X86::COND_A) {
21781 // Try to convert COND_A into COND_B in an attempt to facilitate
21782 // materializing "setb reg".
21784 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
21785 // cannot take an immediate as its first operand.
21787 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
21788 EFLAGS.getValueType().isInteger() &&
21789 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
21790 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
21791 EFLAGS.getNode()->getVTList(),
21792 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
21793 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
21794 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
21798 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
21799 // a zext and produces an all-ones bit which is more useful than 0/1 in some
21801 if (CC == X86::COND_B)
21802 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
21806 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21807 if (Flags.getNode()) {
21808 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21809 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
21815 // Optimize branch condition evaluation.
21817 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
21818 TargetLowering::DAGCombinerInfo &DCI,
21819 const X86Subtarget *Subtarget) {
21821 SDValue Chain = N->getOperand(0);
21822 SDValue Dest = N->getOperand(1);
21823 SDValue EFLAGS = N->getOperand(3);
21824 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
21828 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21829 if (Flags.getNode()) {
21830 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21831 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
21838 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
21839 const X86TargetLowering *XTLI) {
21840 SDValue Op0 = N->getOperand(0);
21841 EVT InVT = Op0->getValueType(0);
21843 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
21844 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
21846 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
21847 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
21848 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
21851 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
21852 // a 32-bit target where SSE doesn't support i64->FP operations.
21853 if (Op0.getOpcode() == ISD::LOAD) {
21854 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
21855 EVT VT = Ld->getValueType(0);
21856 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
21857 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
21858 !XTLI->getSubtarget()->is64Bit() &&
21860 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
21861 Ld->getChain(), Op0, DAG);
21862 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
21869 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
21870 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
21871 X86TargetLowering::DAGCombinerInfo &DCI) {
21872 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
21873 // the result is either zero or one (depending on the input carry bit).
21874 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
21875 if (X86::isZeroNode(N->getOperand(0)) &&
21876 X86::isZeroNode(N->getOperand(1)) &&
21877 // We don't have a good way to replace an EFLAGS use, so only do this when
21879 SDValue(N, 1).use_empty()) {
21881 EVT VT = N->getValueType(0);
21882 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
21883 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
21884 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
21885 DAG.getConstant(X86::COND_B,MVT::i8),
21887 DAG.getConstant(1, VT));
21888 return DCI.CombineTo(N, Res1, CarryOut);
21894 // fold (add Y, (sete X, 0)) -> adc 0, Y
21895 // (add Y, (setne X, 0)) -> sbb -1, Y
21896 // (sub (sete X, 0), Y) -> sbb 0, Y
21897 // (sub (setne X, 0), Y) -> adc -1, Y
21898 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
21901 // Look through ZExts.
21902 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
21903 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
21906 SDValue SetCC = Ext.getOperand(0);
21907 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
21910 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
21911 if (CC != X86::COND_E && CC != X86::COND_NE)
21914 SDValue Cmp = SetCC.getOperand(1);
21915 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
21916 !X86::isZeroNode(Cmp.getOperand(1)) ||
21917 !Cmp.getOperand(0).getValueType().isInteger())
21920 SDValue CmpOp0 = Cmp.getOperand(0);
21921 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
21922 DAG.getConstant(1, CmpOp0.getValueType()));
21924 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
21925 if (CC == X86::COND_NE)
21926 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
21927 DL, OtherVal.getValueType(), OtherVal,
21928 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
21929 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
21930 DL, OtherVal.getValueType(), OtherVal,
21931 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
21934 /// PerformADDCombine - Do target-specific dag combines on integer adds.
21935 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
21936 const X86Subtarget *Subtarget) {
21937 EVT VT = N->getValueType(0);
21938 SDValue Op0 = N->getOperand(0);
21939 SDValue Op1 = N->getOperand(1);
21941 // Try to synthesize horizontal adds from adds of shuffles.
21942 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21943 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21944 isHorizontalBinOp(Op0, Op1, true))
21945 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
21947 return OptimizeConditionalInDecrement(N, DAG);
21950 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
21951 const X86Subtarget *Subtarget) {
21952 SDValue Op0 = N->getOperand(0);
21953 SDValue Op1 = N->getOperand(1);
21955 // X86 can't encode an immediate LHS of a sub. See if we can push the
21956 // negation into a preceding instruction.
21957 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
21958 // If the RHS of the sub is a XOR with one use and a constant, invert the
21959 // immediate. Then add one to the LHS of the sub so we can turn
21960 // X-Y -> X+~Y+1, saving one register.
21961 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
21962 isa<ConstantSDNode>(Op1.getOperand(1))) {
21963 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
21964 EVT VT = Op0.getValueType();
21965 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
21967 DAG.getConstant(~XorC, VT));
21968 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
21969 DAG.getConstant(C->getAPIntValue()+1, VT));
21973 // Try to synthesize horizontal adds from adds of shuffles.
21974 EVT VT = N->getValueType(0);
21975 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21976 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21977 isHorizontalBinOp(Op0, Op1, true))
21978 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
21980 return OptimizeConditionalInDecrement(N, DAG);
21983 /// performVZEXTCombine - Performs build vector combines
21984 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
21985 TargetLowering::DAGCombinerInfo &DCI,
21986 const X86Subtarget *Subtarget) {
21987 // (vzext (bitcast (vzext (x)) -> (vzext x)
21988 SDValue In = N->getOperand(0);
21989 while (In.getOpcode() == ISD::BITCAST)
21990 In = In.getOperand(0);
21992 if (In.getOpcode() != X86ISD::VZEXT)
21995 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
21999 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
22000 DAGCombinerInfo &DCI) const {
22001 SelectionDAG &DAG = DCI.DAG;
22002 switch (N->getOpcode()) {
22004 case ISD::EXTRACT_VECTOR_ELT:
22005 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22007 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22008 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22009 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
22010 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
22011 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
22012 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
22015 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
22016 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
22017 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
22018 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
22019 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
22020 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
22021 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
22022 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
22023 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
22025 case X86ISD::FOR: return PerformFORCombine(N, DAG);
22027 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
22028 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
22029 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
22030 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
22031 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
22032 case ISD::ANY_EXTEND:
22033 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
22034 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22035 case ISD::SIGN_EXTEND_INREG:
22036 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
22037 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
22038 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22039 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
22040 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
22041 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
22042 case X86ISD::SHUFP: // Handle all target specific shuffles
22043 case X86ISD::PALIGNR:
22044 case X86ISD::UNPCKH:
22045 case X86ISD::UNPCKL:
22046 case X86ISD::MOVHLPS:
22047 case X86ISD::MOVLHPS:
22048 case X86ISD::PSHUFD:
22049 case X86ISD::PSHUFHW:
22050 case X86ISD::PSHUFLW:
22051 case X86ISD::MOVSS:
22052 case X86ISD::MOVSD:
22053 case X86ISD::VPERMILP:
22054 case X86ISD::VPERM2X128:
22055 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
22056 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
22057 case ISD::INTRINSIC_WO_CHAIN:
22058 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
22059 case X86ISD::INSERTPS:
22060 return PerformINSERTPSCombine(N, DAG, Subtarget);
22061 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
22067 /// isTypeDesirableForOp - Return true if the target has native support for
22068 /// the specified value type and it is 'desirable' to use the type for the
22069 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
22070 /// instruction encodings are longer and some i16 instructions are slow.
22071 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
22072 if (!isTypeLegal(VT))
22074 if (VT != MVT::i16)
22081 case ISD::SIGN_EXTEND:
22082 case ISD::ZERO_EXTEND:
22083 case ISD::ANY_EXTEND:
22096 /// IsDesirableToPromoteOp - This method query the target whether it is
22097 /// beneficial for dag combiner to promote the specified node. If true, it
22098 /// should return the desired promotion type by reference.
22099 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
22100 EVT VT = Op.getValueType();
22101 if (VT != MVT::i16)
22104 bool Promote = false;
22105 bool Commute = false;
22106 switch (Op.getOpcode()) {
22109 LoadSDNode *LD = cast<LoadSDNode>(Op);
22110 // If the non-extending load has a single use and it's not live out, then it
22111 // might be folded.
22112 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
22113 Op.hasOneUse()*/) {
22114 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
22115 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
22116 // The only case where we'd want to promote LOAD (rather then it being
22117 // promoted as an operand is when it's only use is liveout.
22118 if (UI->getOpcode() != ISD::CopyToReg)
22125 case ISD::SIGN_EXTEND:
22126 case ISD::ZERO_EXTEND:
22127 case ISD::ANY_EXTEND:
22132 SDValue N0 = Op.getOperand(0);
22133 // Look out for (store (shl (load), x)).
22134 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22147 SDValue N0 = Op.getOperand(0);
22148 SDValue N1 = Op.getOperand(1);
22149 if (!Commute && MayFoldLoad(N1))
22151 // Avoid disabling potential load folding opportunities.
22152 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22154 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22164 //===----------------------------------------------------------------------===//
22165 // X86 Inline Assembly Support
22166 //===----------------------------------------------------------------------===//
22169 // Helper to match a string separated by whitespace.
22170 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
22171 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
22173 for (unsigned i = 0, e = args.size(); i != e; ++i) {
22174 StringRef piece(*args[i]);
22175 if (!s.startswith(piece)) // Check if the piece matches.
22178 s = s.substr(piece.size());
22179 StringRef::size_type pos = s.find_first_not_of(" \t");
22180 if (pos == 0) // We matched a prefix.
22188 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
22191 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
22193 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
22194 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
22195 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
22196 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
22198 if (AsmPieces.size() == 3)
22200 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
22207 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
22208 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22210 std::string AsmStr = IA->getAsmString();
22212 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22213 if (!Ty || Ty->getBitWidth() % 16 != 0)
22216 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22217 SmallVector<StringRef, 4> AsmPieces;
22218 SplitString(AsmStr, AsmPieces, ";\n");
22220 switch (AsmPieces.size()) {
22221 default: return false;
22223 // FIXME: this should verify that we are targeting a 486 or better. If not,
22224 // we will turn this bswap into something that will be lowered to logical
22225 // ops instead of emitting the bswap asm. For now, we don't support 486 or
22226 // lower so don't worry about this.
22228 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22229 matchAsm(AsmPieces[0], "bswapl", "$0") ||
22230 matchAsm(AsmPieces[0], "bswapq", "$0") ||
22231 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22232 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22233 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22234 // No need to check constraints, nothing other than the equivalent of
22235 // "=r,0" would be valid here.
22236 return IntrinsicLowering::LowerToByteSwap(CI);
22239 // rorw $$8, ${0:w} --> llvm.bswap.i16
22240 if (CI->getType()->isIntegerTy(16) &&
22241 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22242 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22243 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22245 const std::string &ConstraintsStr = IA->getConstraintString();
22246 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22247 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22248 if (clobbersFlagRegisters(AsmPieces))
22249 return IntrinsicLowering::LowerToByteSwap(CI);
22253 if (CI->getType()->isIntegerTy(32) &&
22254 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22255 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22256 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22257 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22259 const std::string &ConstraintsStr = IA->getConstraintString();
22260 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22261 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22262 if (clobbersFlagRegisters(AsmPieces))
22263 return IntrinsicLowering::LowerToByteSwap(CI);
22266 if (CI->getType()->isIntegerTy(64)) {
22267 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22268 if (Constraints.size() >= 2 &&
22269 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22270 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22271 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22272 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22273 matchAsm(AsmPieces[1], "bswap", "%edx") &&
22274 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22275 return IntrinsicLowering::LowerToByteSwap(CI);
22283 /// getConstraintType - Given a constraint letter, return the type of
22284 /// constraint it is for this target.
22285 X86TargetLowering::ConstraintType
22286 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
22287 if (Constraint.size() == 1) {
22288 switch (Constraint[0]) {
22299 return C_RegisterClass;
22323 return TargetLowering::getConstraintType(Constraint);
22326 /// Examine constraint type and operand type and determine a weight value.
22327 /// This object must already have been set up with the operand type
22328 /// and the current alternative constraint selected.
22329 TargetLowering::ConstraintWeight
22330 X86TargetLowering::getSingleConstraintMatchWeight(
22331 AsmOperandInfo &info, const char *constraint) const {
22332 ConstraintWeight weight = CW_Invalid;
22333 Value *CallOperandVal = info.CallOperandVal;
22334 // If we don't have a value, we can't do a match,
22335 // but allow it at the lowest weight.
22336 if (!CallOperandVal)
22338 Type *type = CallOperandVal->getType();
22339 // Look at the constraint type.
22340 switch (*constraint) {
22342 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
22353 if (CallOperandVal->getType()->isIntegerTy())
22354 weight = CW_SpecificReg;
22359 if (type->isFloatingPointTy())
22360 weight = CW_SpecificReg;
22363 if (type->isX86_MMXTy() && Subtarget->hasMMX())
22364 weight = CW_SpecificReg;
22368 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
22369 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
22370 weight = CW_Register;
22373 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
22374 if (C->getZExtValue() <= 31)
22375 weight = CW_Constant;
22379 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22380 if (C->getZExtValue() <= 63)
22381 weight = CW_Constant;
22385 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22386 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
22387 weight = CW_Constant;
22391 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22392 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
22393 weight = CW_Constant;
22397 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22398 if (C->getZExtValue() <= 3)
22399 weight = CW_Constant;
22403 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22404 if (C->getZExtValue() <= 0xff)
22405 weight = CW_Constant;
22410 if (dyn_cast<ConstantFP>(CallOperandVal)) {
22411 weight = CW_Constant;
22415 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22416 if ((C->getSExtValue() >= -0x80000000LL) &&
22417 (C->getSExtValue() <= 0x7fffffffLL))
22418 weight = CW_Constant;
22422 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22423 if (C->getZExtValue() <= 0xffffffff)
22424 weight = CW_Constant;
22431 /// LowerXConstraint - try to replace an X constraint, which matches anything,
22432 /// with another that has more specific requirements based on the type of the
22433 /// corresponding operand.
22434 const char *X86TargetLowering::
22435 LowerXConstraint(EVT ConstraintVT) const {
22436 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
22437 // 'f' like normal targets.
22438 if (ConstraintVT.isFloatingPoint()) {
22439 if (Subtarget->hasSSE2())
22441 if (Subtarget->hasSSE1())
22445 return TargetLowering::LowerXConstraint(ConstraintVT);
22448 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
22449 /// vector. If it is invalid, don't add anything to Ops.
22450 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
22451 std::string &Constraint,
22452 std::vector<SDValue>&Ops,
22453 SelectionDAG &DAG) const {
22456 // Only support length 1 constraints for now.
22457 if (Constraint.length() > 1) return;
22459 char ConstraintLetter = Constraint[0];
22460 switch (ConstraintLetter) {
22463 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22464 if (C->getZExtValue() <= 31) {
22465 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22471 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22472 if (C->getZExtValue() <= 63) {
22473 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22479 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22480 if (isInt<8>(C->getSExtValue())) {
22481 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22487 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22488 if (C->getZExtValue() <= 255) {
22489 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22495 // 32-bit signed value
22496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22497 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22498 C->getSExtValue())) {
22499 // Widen to 64 bits here to get it sign extended.
22500 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
22503 // FIXME gcc accepts some relocatable values here too, but only in certain
22504 // memory models; it's complicated.
22509 // 32-bit unsigned value
22510 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22511 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22512 C->getZExtValue())) {
22513 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22517 // FIXME gcc accepts some relocatable values here too, but only in certain
22518 // memory models; it's complicated.
22522 // Literal immediates are always ok.
22523 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
22524 // Widen to 64 bits here to get it sign extended.
22525 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
22529 // In any sort of PIC mode addresses need to be computed at runtime by
22530 // adding in a register or some sort of table lookup. These can't
22531 // be used as immediates.
22532 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
22535 // If we are in non-pic codegen mode, we allow the address of a global (with
22536 // an optional displacement) to be used with 'i'.
22537 GlobalAddressSDNode *GA = nullptr;
22538 int64_t Offset = 0;
22540 // Match either (GA), (GA+C), (GA+C1+C2), etc.
22542 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
22543 Offset += GA->getOffset();
22545 } else if (Op.getOpcode() == ISD::ADD) {
22546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22547 Offset += C->getZExtValue();
22548 Op = Op.getOperand(0);
22551 } else if (Op.getOpcode() == ISD::SUB) {
22552 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22553 Offset += -C->getZExtValue();
22554 Op = Op.getOperand(0);
22559 // Otherwise, this isn't something we can handle, reject it.
22563 const GlobalValue *GV = GA->getGlobal();
22564 // If we require an extra load to get this address, as in PIC mode, we
22565 // can't accept it.
22566 if (isGlobalStubReference(
22567 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
22570 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
22571 GA->getValueType(0), Offset);
22576 if (Result.getNode()) {
22577 Ops.push_back(Result);
22580 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
22583 std::pair<unsigned, const TargetRegisterClass*>
22584 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
22586 // First, see if this is a constraint that directly corresponds to an LLVM
22588 if (Constraint.size() == 1) {
22589 // GCC Constraint Letters
22590 switch (Constraint[0]) {
22592 // TODO: Slight differences here in allocation order and leaving
22593 // RIP in the class. Do they matter any more here than they do
22594 // in the normal allocation?
22595 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
22596 if (Subtarget->is64Bit()) {
22597 if (VT == MVT::i32 || VT == MVT::f32)
22598 return std::make_pair(0U, &X86::GR32RegClass);
22599 if (VT == MVT::i16)
22600 return std::make_pair(0U, &X86::GR16RegClass);
22601 if (VT == MVT::i8 || VT == MVT::i1)
22602 return std::make_pair(0U, &X86::GR8RegClass);
22603 if (VT == MVT::i64 || VT == MVT::f64)
22604 return std::make_pair(0U, &X86::GR64RegClass);
22607 // 32-bit fallthrough
22608 case 'Q': // Q_REGS
22609 if (VT == MVT::i32 || VT == MVT::f32)
22610 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
22611 if (VT == MVT::i16)
22612 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
22613 if (VT == MVT::i8 || VT == MVT::i1)
22614 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
22615 if (VT == MVT::i64)
22616 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
22618 case 'r': // GENERAL_REGS
22619 case 'l': // INDEX_REGS
22620 if (VT == MVT::i8 || VT == MVT::i1)
22621 return std::make_pair(0U, &X86::GR8RegClass);
22622 if (VT == MVT::i16)
22623 return std::make_pair(0U, &X86::GR16RegClass);
22624 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
22625 return std::make_pair(0U, &X86::GR32RegClass);
22626 return std::make_pair(0U, &X86::GR64RegClass);
22627 case 'R': // LEGACY_REGS
22628 if (VT == MVT::i8 || VT == MVT::i1)
22629 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
22630 if (VT == MVT::i16)
22631 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
22632 if (VT == MVT::i32 || !Subtarget->is64Bit())
22633 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
22634 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
22635 case 'f': // FP Stack registers.
22636 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
22637 // value to the correct fpstack register class.
22638 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
22639 return std::make_pair(0U, &X86::RFP32RegClass);
22640 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
22641 return std::make_pair(0U, &X86::RFP64RegClass);
22642 return std::make_pair(0U, &X86::RFP80RegClass);
22643 case 'y': // MMX_REGS if MMX allowed.
22644 if (!Subtarget->hasMMX()) break;
22645 return std::make_pair(0U, &X86::VR64RegClass);
22646 case 'Y': // SSE_REGS if SSE2 allowed
22647 if (!Subtarget->hasSSE2()) break;
22649 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
22650 if (!Subtarget->hasSSE1()) break;
22652 switch (VT.SimpleTy) {
22654 // Scalar SSE types.
22657 return std::make_pair(0U, &X86::FR32RegClass);
22660 return std::make_pair(0U, &X86::FR64RegClass);
22668 return std::make_pair(0U, &X86::VR128RegClass);
22676 return std::make_pair(0U, &X86::VR256RegClass);
22681 return std::make_pair(0U, &X86::VR512RegClass);
22687 // Use the default implementation in TargetLowering to convert the register
22688 // constraint into a member of a register class.
22689 std::pair<unsigned, const TargetRegisterClass*> Res;
22690 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
22692 // Not found as a standard register?
22694 // Map st(0) -> st(7) -> ST0
22695 if (Constraint.size() == 7 && Constraint[0] == '{' &&
22696 tolower(Constraint[1]) == 's' &&
22697 tolower(Constraint[2]) == 't' &&
22698 Constraint[3] == '(' &&
22699 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
22700 Constraint[5] == ')' &&
22701 Constraint[6] == '}') {
22703 Res.first = X86::ST0+Constraint[4]-'0';
22704 Res.second = &X86::RFP80RegClass;
22708 // GCC allows "st(0)" to be called just plain "st".
22709 if (StringRef("{st}").equals_lower(Constraint)) {
22710 Res.first = X86::ST0;
22711 Res.second = &X86::RFP80RegClass;
22716 if (StringRef("{flags}").equals_lower(Constraint)) {
22717 Res.first = X86::EFLAGS;
22718 Res.second = &X86::CCRRegClass;
22722 // 'A' means EAX + EDX.
22723 if (Constraint == "A") {
22724 Res.first = X86::EAX;
22725 Res.second = &X86::GR32_ADRegClass;
22731 // Otherwise, check to see if this is a register class of the wrong value
22732 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
22733 // turn into {ax},{dx}.
22734 if (Res.second->hasType(VT))
22735 return Res; // Correct type already, nothing to do.
22737 // All of the single-register GCC register classes map their values onto
22738 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
22739 // really want an 8-bit or 32-bit register, map to the appropriate register
22740 // class and return the appropriate register.
22741 if (Res.second == &X86::GR16RegClass) {
22742 if (VT == MVT::i8 || VT == MVT::i1) {
22743 unsigned DestReg = 0;
22744 switch (Res.first) {
22746 case X86::AX: DestReg = X86::AL; break;
22747 case X86::DX: DestReg = X86::DL; break;
22748 case X86::CX: DestReg = X86::CL; break;
22749 case X86::BX: DestReg = X86::BL; break;
22752 Res.first = DestReg;
22753 Res.second = &X86::GR8RegClass;
22755 } else if (VT == MVT::i32 || VT == MVT::f32) {
22756 unsigned DestReg = 0;
22757 switch (Res.first) {
22759 case X86::AX: DestReg = X86::EAX; break;
22760 case X86::DX: DestReg = X86::EDX; break;
22761 case X86::CX: DestReg = X86::ECX; break;
22762 case X86::BX: DestReg = X86::EBX; break;
22763 case X86::SI: DestReg = X86::ESI; break;
22764 case X86::DI: DestReg = X86::EDI; break;
22765 case X86::BP: DestReg = X86::EBP; break;
22766 case X86::SP: DestReg = X86::ESP; break;
22769 Res.first = DestReg;
22770 Res.second = &X86::GR32RegClass;
22772 } else if (VT == MVT::i64 || VT == MVT::f64) {
22773 unsigned DestReg = 0;
22774 switch (Res.first) {
22776 case X86::AX: DestReg = X86::RAX; break;
22777 case X86::DX: DestReg = X86::RDX; break;
22778 case X86::CX: DestReg = X86::RCX; break;
22779 case X86::BX: DestReg = X86::RBX; break;
22780 case X86::SI: DestReg = X86::RSI; break;
22781 case X86::DI: DestReg = X86::RDI; break;
22782 case X86::BP: DestReg = X86::RBP; break;
22783 case X86::SP: DestReg = X86::RSP; break;
22786 Res.first = DestReg;
22787 Res.second = &X86::GR64RegClass;
22790 } else if (Res.second == &X86::FR32RegClass ||
22791 Res.second == &X86::FR64RegClass ||
22792 Res.second == &X86::VR128RegClass ||
22793 Res.second == &X86::VR256RegClass ||
22794 Res.second == &X86::FR32XRegClass ||
22795 Res.second == &X86::FR64XRegClass ||
22796 Res.second == &X86::VR128XRegClass ||
22797 Res.second == &X86::VR256XRegClass ||
22798 Res.second == &X86::VR512RegClass) {
22799 // Handle references to XMM physical registers that got mapped into the
22800 // wrong class. This can happen with constraints like {xmm0} where the
22801 // target independent register mapper will just pick the first match it can
22802 // find, ignoring the required type.
22804 if (VT == MVT::f32 || VT == MVT::i32)
22805 Res.second = &X86::FR32RegClass;
22806 else if (VT == MVT::f64 || VT == MVT::i64)
22807 Res.second = &X86::FR64RegClass;
22808 else if (X86::VR128RegClass.hasType(VT))
22809 Res.second = &X86::VR128RegClass;
22810 else if (X86::VR256RegClass.hasType(VT))
22811 Res.second = &X86::VR256RegClass;
22812 else if (X86::VR512RegClass.hasType(VT))
22813 Res.second = &X86::VR512RegClass;
22819 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
22821 // Scaling factors are not free at all.
22822 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
22823 // will take 2 allocations in the out of order engine instead of 1
22824 // for plain addressing mode, i.e. inst (reg1).
22826 // vaddps (%rsi,%drx), %ymm0, %ymm1
22827 // Requires two allocations (one for the load, one for the computation)
22829 // vaddps (%rsi), %ymm0, %ymm1
22830 // Requires just 1 allocation, i.e., freeing allocations for other operations
22831 // and having less micro operations to execute.
22833 // For some X86 architectures, this is even worse because for instance for
22834 // stores, the complex addressing mode forces the instruction to use the
22835 // "load" ports instead of the dedicated "store" port.
22836 // E.g., on Haswell:
22837 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
22838 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
22839 if (isLegalAddressingMode(AM, Ty))
22840 // Scale represents reg2 * scale, thus account for 1
22841 // as soon as we use a second register.
22842 return AM.Scale != 0;
22846 bool X86TargetLowering::isTargetFTOL() const {
22847 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();