1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
814 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
815 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
817 // First set operation action for all vector types to either promote
818 // (for widening) or expand (for scalarization). Then we will selectively
819 // turn on ones that can be effectively codegen'd.
820 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
821 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
822 MVT VT = (MVT::SimpleValueType)i;
823 setOperationAction(ISD::ADD , VT, Expand);
824 setOperationAction(ISD::SUB , VT, Expand);
825 setOperationAction(ISD::FADD, VT, Expand);
826 setOperationAction(ISD::FNEG, VT, Expand);
827 setOperationAction(ISD::FSUB, VT, Expand);
828 setOperationAction(ISD::MUL , VT, Expand);
829 setOperationAction(ISD::FMUL, VT, Expand);
830 setOperationAction(ISD::SDIV, VT, Expand);
831 setOperationAction(ISD::UDIV, VT, Expand);
832 setOperationAction(ISD::FDIV, VT, Expand);
833 setOperationAction(ISD::SREM, VT, Expand);
834 setOperationAction(ISD::UREM, VT, Expand);
835 setOperationAction(ISD::LOAD, VT, Expand);
836 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
837 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
838 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
839 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
840 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
841 setOperationAction(ISD::FABS, VT, Expand);
842 setOperationAction(ISD::FSIN, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FCOS, VT, Expand);
845 setOperationAction(ISD::FSINCOS, VT, Expand);
846 setOperationAction(ISD::FREM, VT, Expand);
847 setOperationAction(ISD::FMA, VT, Expand);
848 setOperationAction(ISD::FPOWI, VT, Expand);
849 setOperationAction(ISD::FSQRT, VT, Expand);
850 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
851 setOperationAction(ISD::FFLOOR, VT, Expand);
852 setOperationAction(ISD::FCEIL, VT, Expand);
853 setOperationAction(ISD::FTRUNC, VT, Expand);
854 setOperationAction(ISD::FRINT, VT, Expand);
855 setOperationAction(ISD::FNEARBYINT, VT, Expand);
856 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHS, VT, Expand);
858 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
859 setOperationAction(ISD::MULHU, VT, Expand);
860 setOperationAction(ISD::SDIVREM, VT, Expand);
861 setOperationAction(ISD::UDIVREM, VT, Expand);
862 setOperationAction(ISD::FPOW, VT, Expand);
863 setOperationAction(ISD::CTPOP, VT, Expand);
864 setOperationAction(ISD::CTTZ, VT, Expand);
865 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::CTLZ, VT, Expand);
867 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
868 setOperationAction(ISD::SHL, VT, Expand);
869 setOperationAction(ISD::SRA, VT, Expand);
870 setOperationAction(ISD::SRL, VT, Expand);
871 setOperationAction(ISD::ROTL, VT, Expand);
872 setOperationAction(ISD::ROTR, VT, Expand);
873 setOperationAction(ISD::BSWAP, VT, Expand);
874 setOperationAction(ISD::SETCC, VT, Expand);
875 setOperationAction(ISD::FLOG, VT, Expand);
876 setOperationAction(ISD::FLOG2, VT, Expand);
877 setOperationAction(ISD::FLOG10, VT, Expand);
878 setOperationAction(ISD::FEXP, VT, Expand);
879 setOperationAction(ISD::FEXP2, VT, Expand);
880 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
881 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
882 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
883 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
885 setOperationAction(ISD::TRUNCATE, VT, Expand);
886 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
887 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
888 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
889 setOperationAction(ISD::VSELECT, VT, Expand);
890 setOperationAction(ISD::SELECT_CC, VT, Expand);
891 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
892 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
893 setTruncStoreAction(VT,
894 (MVT::SimpleValueType)InnerVT, Expand);
895 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
896 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
898 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
899 // we have to deal with them whether we ask for Expansion or not. Setting
900 // Expand causes its own optimisation problems though, so leave them legal.
901 if (VT.getVectorElementType() == MVT::i1)
902 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
905 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
906 // with -msoft-float, disable use of MMX as well.
907 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
908 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
909 // No operations on x86mmx supported, everything uses intrinsics.
912 // MMX-sized vectors (other than x86mmx) are expected to be expanded
913 // into smaller operations.
914 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
915 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
916 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
917 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
918 setOperationAction(ISD::AND, MVT::v8i8, Expand);
919 setOperationAction(ISD::AND, MVT::v4i16, Expand);
920 setOperationAction(ISD::AND, MVT::v2i32, Expand);
921 setOperationAction(ISD::AND, MVT::v1i64, Expand);
922 setOperationAction(ISD::OR, MVT::v8i8, Expand);
923 setOperationAction(ISD::OR, MVT::v4i16, Expand);
924 setOperationAction(ISD::OR, MVT::v2i32, Expand);
925 setOperationAction(ISD::OR, MVT::v1i64, Expand);
926 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
927 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
928 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
929 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
932 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
933 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
935 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
936 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
937 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
938 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
941 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
942 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
944 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
945 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
947 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
948 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
949 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
950 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
951 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
952 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
953 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
954 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
955 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
956 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
957 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
958 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
962 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
963 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
965 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
966 // registers cannot be used even for integer operations.
967 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
968 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
969 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
970 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
972 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
973 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
974 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
975 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
976 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
977 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
978 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
979 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
980 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
981 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
982 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
983 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
984 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
985 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
986 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
987 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
989 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
990 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
991 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
992 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
993 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
995 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
996 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
997 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
998 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
1000 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
1001 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
1002 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1003 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1004 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1006 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1007 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1008 MVT VT = (MVT::SimpleValueType)i;
1009 // Do not attempt to custom lower non-power-of-2 vectors
1010 if (!isPowerOf2_32(VT.getVectorNumElements()))
1012 // Do not attempt to custom lower non-128-bit vectors
1013 if (!VT.is128BitVector())
1015 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1016 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1020 // We support custom legalizing of sext and anyext loads for specific
1021 // memory vector types which we can load as a scalar (or sequence of
1022 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1023 // loads these must work with a single scalar load.
1024 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1025 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1026 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1030 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1031 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1032 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1034 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1035 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1036 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1037 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1038 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1039 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1041 if (Subtarget->is64Bit()) {
1042 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1043 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1046 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1047 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1048 MVT VT = (MVT::SimpleValueType)i;
1050 // Do not attempt to promote non-128-bit vectors
1051 if (!VT.is128BitVector())
1054 setOperationAction(ISD::AND, VT, Promote);
1055 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1056 setOperationAction(ISD::OR, VT, Promote);
1057 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1058 setOperationAction(ISD::XOR, VT, Promote);
1059 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1060 setOperationAction(ISD::LOAD, VT, Promote);
1061 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1062 setOperationAction(ISD::SELECT, VT, Promote);
1063 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1066 // Custom lower v2i64 and v2f64 selects.
1067 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1068 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1069 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1070 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1072 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1073 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1075 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1076 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1077 // As there is no 64-bit GPR available, we need build a special custom
1078 // sequence to convert from v2i32 to v2f32.
1079 if (!Subtarget->is64Bit())
1080 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1082 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1083 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1085 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1087 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1088 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1089 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1092 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1093 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1096 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1098 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1099 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1100 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1101 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1102 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1104 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1107 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1108 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1109 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1111 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1112 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1113 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1115 // FIXME: Do we need to handle scalar-to-vector here?
1116 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1118 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1120 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1121 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1122 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1123 // There is no BLENDI for byte vectors. We don't need to custom lower
1124 // some vselects for now.
1125 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1127 // SSE41 brings specific instructions for doing vector sign extend even in
1128 // cases where we don't have SRA.
1129 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1130 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1131 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1133 // i8 and i16 vectors are custom because the source register and source
1134 // source memory operand types are not the same width. f32 vectors are
1135 // custom since the immediate controlling the insert encodes additional
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1140 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1144 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1145 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1147 // FIXME: these should be Legal, but that's only for the case where
1148 // the index is constant. For now custom expand to deal with that.
1149 if (Subtarget->is64Bit()) {
1150 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1155 if (Subtarget->hasSSE2()) {
1156 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1162 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1163 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1165 // In the customized shift lowering, the legal cases in AVX2 will be
1167 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1171 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1173 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1176 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1177 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1180 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1181 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1182 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1184 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1185 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1186 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1188 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1197 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1198 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1199 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1201 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1210 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1211 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1212 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1214 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1215 // even though v8i16 is a legal type.
1216 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1217 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1218 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1220 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1221 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1222 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1224 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1225 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1227 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1229 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1240 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1243 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1244 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1248 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1249 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1250 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1259 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1260 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1261 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1262 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1263 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1265 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1266 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1267 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1268 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1269 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1270 setOperationAction(ISD::FMA, MVT::f32, Legal);
1271 setOperationAction(ISD::FMA, MVT::f64, Legal);
1274 if (Subtarget->hasInt256()) {
1275 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1276 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1277 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1278 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1280 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1281 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1282 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1283 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1285 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1286 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1287 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1288 // Don't lower v32i8 because there is no 128-bit byte mul
1290 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1291 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1292 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1293 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1295 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1296 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1298 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1299 // when we have a 256bit-wide blend with immediate.
1300 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1302 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1303 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1304 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1305 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1307 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1309 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1310 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1312 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1313 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1314 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1315 // Don't lower v32i8 because there is no 128-bit byte mul
1318 // In the customized shift lowering, the legal cases in AVX2 will be
1320 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1321 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1323 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1324 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1326 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1328 // Custom lower several nodes for 256-bit types.
1329 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1330 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1331 MVT VT = (MVT::SimpleValueType)i;
1333 // Extract subvector is special because the value type
1334 // (result) is 128-bit but the source is 256-bit wide.
1335 if (VT.is128BitVector())
1336 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1338 // Do not attempt to custom lower other non-256-bit vectors
1339 if (!VT.is256BitVector())
1342 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1343 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1344 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1346 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1347 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1348 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1351 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1352 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1353 MVT VT = (MVT::SimpleValueType)i;
1355 // Do not attempt to promote non-256-bit vectors
1356 if (!VT.is256BitVector())
1359 setOperationAction(ISD::AND, VT, Promote);
1360 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1361 setOperationAction(ISD::OR, VT, Promote);
1362 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1363 setOperationAction(ISD::XOR, VT, Promote);
1364 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1365 setOperationAction(ISD::LOAD, VT, Promote);
1366 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1367 setOperationAction(ISD::SELECT, VT, Promote);
1368 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1372 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1373 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1374 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1375 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1376 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1378 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1379 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1380 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1382 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1383 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1384 setOperationAction(ISD::XOR, MVT::i1, Legal);
1385 setOperationAction(ISD::OR, MVT::i1, Legal);
1386 setOperationAction(ISD::AND, MVT::i1, Legal);
1387 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1388 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1389 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1390 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1391 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1392 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1394 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1401 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1402 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1403 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1404 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1405 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1406 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1407 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1408 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1410 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1413 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1414 if (Subtarget->is64Bit()) {
1415 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1416 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1420 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1421 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1426 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1427 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1428 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1429 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1431 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1432 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1433 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1434 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1435 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1436 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1437 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1438 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1443 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1450 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1452 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1453 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1455 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1458 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1459 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1460 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1461 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1462 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1465 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1467 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1468 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1470 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1471 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1473 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1475 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1476 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1478 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1479 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1481 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1482 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1484 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1485 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1486 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1487 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1488 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1489 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1491 if (Subtarget->hasCDI()) {
1492 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1493 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1496 // Custom lower several nodes.
1497 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1498 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1499 MVT VT = (MVT::SimpleValueType)i;
1501 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1502 // Extract subvector is special because the value type
1503 // (result) is 256/128-bit but the source is 512-bit wide.
1504 if (VT.is128BitVector() || VT.is256BitVector())
1505 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1507 if (VT.getVectorElementType() == MVT::i1)
1508 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1510 // Do not attempt to custom lower other non-512-bit vectors
1511 if (!VT.is512BitVector())
1514 if ( EltSize >= 32) {
1515 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1516 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1517 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1518 setOperationAction(ISD::VSELECT, VT, Legal);
1519 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1520 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1521 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1524 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1525 MVT VT = (MVT::SimpleValueType)i;
1527 // Do not attempt to promote non-256-bit vectors
1528 if (!VT.is512BitVector())
1531 setOperationAction(ISD::SELECT, VT, Promote);
1532 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1536 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1537 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1538 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1540 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1541 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1543 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1544 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1545 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1546 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1548 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1549 const MVT VT = (MVT::SimpleValueType)i;
1551 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1553 // Do not attempt to promote non-256-bit vectors
1554 if (!VT.is512BitVector())
1557 if ( EltSize < 32) {
1558 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1559 setOperationAction(ISD::VSELECT, VT, Legal);
1564 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1565 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1566 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1568 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1569 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1570 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1573 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1574 // of this type with custom code.
1575 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1576 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1577 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1581 // We want to custom lower some of our intrinsics.
1582 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1583 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1584 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1585 if (!Subtarget->is64Bit())
1586 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1588 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1589 // handle type legalization for these operations here.
1591 // FIXME: We really should do custom legalization for addition and
1592 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1593 // than generic legalization for 64-bit multiplication-with-overflow, though.
1594 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1595 // Add/Sub/Mul with overflow operations are custom lowered.
1597 setOperationAction(ISD::SADDO, VT, Custom);
1598 setOperationAction(ISD::UADDO, VT, Custom);
1599 setOperationAction(ISD::SSUBO, VT, Custom);
1600 setOperationAction(ISD::USUBO, VT, Custom);
1601 setOperationAction(ISD::SMULO, VT, Custom);
1602 setOperationAction(ISD::UMULO, VT, Custom);
1606 if (!Subtarget->is64Bit()) {
1607 // These libcalls are not available in 32-bit.
1608 setLibcallName(RTLIB::SHL_I128, nullptr);
1609 setLibcallName(RTLIB::SRL_I128, nullptr);
1610 setLibcallName(RTLIB::SRA_I128, nullptr);
1613 // Combine sin / cos into one node or libcall if possible.
1614 if (Subtarget->hasSinCos()) {
1615 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1616 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1617 if (Subtarget->isTargetDarwin()) {
1618 // For MacOSX, we don't want to the normal expansion of a libcall to
1619 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1621 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1622 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1626 if (Subtarget->isTargetWin64()) {
1627 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1628 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1629 setOperationAction(ISD::SREM, MVT::i128, Custom);
1630 setOperationAction(ISD::UREM, MVT::i128, Custom);
1631 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1632 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1635 // We have target-specific dag combine patterns for the following nodes:
1636 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1637 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1638 setTargetDAGCombine(ISD::VSELECT);
1639 setTargetDAGCombine(ISD::SELECT);
1640 setTargetDAGCombine(ISD::SHL);
1641 setTargetDAGCombine(ISD::SRA);
1642 setTargetDAGCombine(ISD::SRL);
1643 setTargetDAGCombine(ISD::OR);
1644 setTargetDAGCombine(ISD::AND);
1645 setTargetDAGCombine(ISD::ADD);
1646 setTargetDAGCombine(ISD::FADD);
1647 setTargetDAGCombine(ISD::FSUB);
1648 setTargetDAGCombine(ISD::FMA);
1649 setTargetDAGCombine(ISD::SUB);
1650 setTargetDAGCombine(ISD::LOAD);
1651 setTargetDAGCombine(ISD::STORE);
1652 setTargetDAGCombine(ISD::ZERO_EXTEND);
1653 setTargetDAGCombine(ISD::ANY_EXTEND);
1654 setTargetDAGCombine(ISD::SIGN_EXTEND);
1655 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1656 setTargetDAGCombine(ISD::TRUNCATE);
1657 setTargetDAGCombine(ISD::SINT_TO_FP);
1658 setTargetDAGCombine(ISD::SETCC);
1659 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1660 setTargetDAGCombine(ISD::BUILD_VECTOR);
1661 if (Subtarget->is64Bit())
1662 setTargetDAGCombine(ISD::MUL);
1663 setTargetDAGCombine(ISD::XOR);
1665 computeRegisterProperties();
1667 // On Darwin, -Os means optimize for size without hurting performance,
1668 // do not reduce the limit.
1669 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1670 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1671 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1672 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1673 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1674 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1675 setPrefLoopAlignment(4); // 2^4 bytes.
1677 // Predictable cmov don't hurt on atom because it's in-order.
1678 PredictableSelectIsExpensive = !Subtarget->isAtom();
1680 setPrefFunctionAlignment(4); // 2^4 bytes.
1682 verifyIntrinsicTables();
1685 // This has so far only been implemented for 64-bit MachO.
1686 bool X86TargetLowering::useLoadStackGuardNode() const {
1687 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1688 Subtarget->is64Bit();
1691 TargetLoweringBase::LegalizeTypeAction
1692 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1693 if (ExperimentalVectorWideningLegalization &&
1694 VT.getVectorNumElements() != 1 &&
1695 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1696 return TypeWidenVector;
1698 return TargetLoweringBase::getPreferredVectorAction(VT);
1701 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1703 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1705 const unsigned NumElts = VT.getVectorNumElements();
1706 const EVT EltVT = VT.getVectorElementType();
1707 if (VT.is512BitVector()) {
1708 if (Subtarget->hasAVX512())
1709 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1710 EltVT == MVT::f32 || EltVT == MVT::f64)
1712 case 8: return MVT::v8i1;
1713 case 16: return MVT::v16i1;
1715 if (Subtarget->hasBWI())
1716 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1718 case 32: return MVT::v32i1;
1719 case 64: return MVT::v64i1;
1723 if (VT.is256BitVector() || VT.is128BitVector()) {
1724 if (Subtarget->hasVLX())
1725 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1726 EltVT == MVT::f32 || EltVT == MVT::f64)
1728 case 2: return MVT::v2i1;
1729 case 4: return MVT::v4i1;
1730 case 8: return MVT::v8i1;
1732 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1733 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1735 case 8: return MVT::v8i1;
1736 case 16: return MVT::v16i1;
1737 case 32: return MVT::v32i1;
1741 return VT.changeVectorElementTypeToInteger();
1744 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1745 /// the desired ByVal argument alignment.
1746 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1749 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1750 if (VTy->getBitWidth() == 128)
1752 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1753 unsigned EltAlign = 0;
1754 getMaxByValAlign(ATy->getElementType(), EltAlign);
1755 if (EltAlign > MaxAlign)
1756 MaxAlign = EltAlign;
1757 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1758 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1759 unsigned EltAlign = 0;
1760 getMaxByValAlign(STy->getElementType(i), EltAlign);
1761 if (EltAlign > MaxAlign)
1762 MaxAlign = EltAlign;
1769 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1770 /// function arguments in the caller parameter area. For X86, aggregates
1771 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1772 /// are at 4-byte boundaries.
1773 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1774 if (Subtarget->is64Bit()) {
1775 // Max of 8 and alignment of type.
1776 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1783 if (Subtarget->hasSSE1())
1784 getMaxByValAlign(Ty, Align);
1788 /// getOptimalMemOpType - Returns the target specific optimal type for load
1789 /// and store operations as a result of memset, memcpy, and memmove
1790 /// lowering. If DstAlign is zero that means it's safe to destination
1791 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1792 /// means there isn't a need to check it against alignment requirement,
1793 /// probably because the source does not need to be loaded. If 'IsMemset' is
1794 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1795 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1796 /// source is constant so it does not need to be loaded.
1797 /// It returns EVT::Other if the type should be determined using generic
1798 /// target-independent logic.
1800 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1801 unsigned DstAlign, unsigned SrcAlign,
1802 bool IsMemset, bool ZeroMemset,
1804 MachineFunction &MF) const {
1805 const Function *F = MF.getFunction();
1806 if ((!IsMemset || ZeroMemset) &&
1807 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1808 Attribute::NoImplicitFloat)) {
1810 (Subtarget->isUnalignedMemAccessFast() ||
1811 ((DstAlign == 0 || DstAlign >= 16) &&
1812 (SrcAlign == 0 || SrcAlign >= 16)))) {
1814 if (Subtarget->hasInt256())
1816 if (Subtarget->hasFp256())
1819 if (Subtarget->hasSSE2())
1821 if (Subtarget->hasSSE1())
1823 } else if (!MemcpyStrSrc && Size >= 8 &&
1824 !Subtarget->is64Bit() &&
1825 Subtarget->hasSSE2()) {
1826 // Do not use f64 to lower memcpy if source is string constant. It's
1827 // better to use i32 to avoid the loads.
1831 if (Subtarget->is64Bit() && Size >= 8)
1836 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1838 return X86ScalarSSEf32;
1839 else if (VT == MVT::f64)
1840 return X86ScalarSSEf64;
1845 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1850 *Fast = Subtarget->isUnalignedMemAccessFast();
1854 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1855 /// current function. The returned value is a member of the
1856 /// MachineJumpTableInfo::JTEntryKind enum.
1857 unsigned X86TargetLowering::getJumpTableEncoding() const {
1858 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1860 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1861 Subtarget->isPICStyleGOT())
1862 return MachineJumpTableInfo::EK_Custom32;
1864 // Otherwise, use the normal jump table encoding heuristics.
1865 return TargetLowering::getJumpTableEncoding();
1869 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1870 const MachineBasicBlock *MBB,
1871 unsigned uid,MCContext &Ctx) const{
1872 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1873 Subtarget->isPICStyleGOT());
1874 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1876 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1877 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1880 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1882 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1883 SelectionDAG &DAG) const {
1884 if (!Subtarget->is64Bit())
1885 // This doesn't have SDLoc associated with it, but is not really the
1886 // same as a Register.
1887 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1891 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1892 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1894 const MCExpr *X86TargetLowering::
1895 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1896 MCContext &Ctx) const {
1897 // X86-64 uses RIP relative addressing based on the jump table label.
1898 if (Subtarget->isPICStyleRIPRel())
1899 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1901 // Otherwise, the reference is relative to the PIC base.
1902 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1905 // FIXME: Why this routine is here? Move to RegInfo!
1906 std::pair<const TargetRegisterClass*, uint8_t>
1907 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1908 const TargetRegisterClass *RRC = nullptr;
1910 switch (VT.SimpleTy) {
1912 return TargetLowering::findRepresentativeClass(VT);
1913 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1914 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1917 RRC = &X86::VR64RegClass;
1919 case MVT::f32: case MVT::f64:
1920 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1921 case MVT::v4f32: case MVT::v2f64:
1922 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1924 RRC = &X86::VR128RegClass;
1927 return std::make_pair(RRC, Cost);
1930 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1931 unsigned &Offset) const {
1932 if (!Subtarget->isTargetLinux())
1935 if (Subtarget->is64Bit()) {
1936 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1938 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1950 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1951 unsigned DestAS) const {
1952 assert(SrcAS != DestAS && "Expected different address spaces!");
1954 return SrcAS < 256 && DestAS < 256;
1957 //===----------------------------------------------------------------------===//
1958 // Return Value Calling Convention Implementation
1959 //===----------------------------------------------------------------------===//
1961 #include "X86GenCallingConv.inc"
1964 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1965 MachineFunction &MF, bool isVarArg,
1966 const SmallVectorImpl<ISD::OutputArg> &Outs,
1967 LLVMContext &Context) const {
1968 SmallVector<CCValAssign, 16> RVLocs;
1969 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1970 return CCInfo.CheckReturn(Outs, RetCC_X86);
1973 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1974 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1979 X86TargetLowering::LowerReturn(SDValue Chain,
1980 CallingConv::ID CallConv, bool isVarArg,
1981 const SmallVectorImpl<ISD::OutputArg> &Outs,
1982 const SmallVectorImpl<SDValue> &OutVals,
1983 SDLoc dl, SelectionDAG &DAG) const {
1984 MachineFunction &MF = DAG.getMachineFunction();
1985 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1987 SmallVector<CCValAssign, 16> RVLocs;
1988 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1989 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1992 SmallVector<SDValue, 6> RetOps;
1993 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1994 // Operand #1 = Bytes To Pop
1995 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1998 // Copy the result values into the output registers.
1999 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2000 CCValAssign &VA = RVLocs[i];
2001 assert(VA.isRegLoc() && "Can only return in registers!");
2002 SDValue ValToCopy = OutVals[i];
2003 EVT ValVT = ValToCopy.getValueType();
2005 // Promote values to the appropriate types
2006 if (VA.getLocInfo() == CCValAssign::SExt)
2007 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::ZExt)
2009 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2010 else if (VA.getLocInfo() == CCValAssign::AExt)
2011 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2012 else if (VA.getLocInfo() == CCValAssign::BCvt)
2013 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2015 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2016 "Unexpected FP-extend for return value.");
2018 // If this is x86-64, and we disabled SSE, we can't return FP values,
2019 // or SSE or MMX vectors.
2020 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2021 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2022 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2023 report_fatal_error("SSE register return with SSE disabled");
2025 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2026 // llvm-gcc has never done it right and no one has noticed, so this
2027 // should be OK for now.
2028 if (ValVT == MVT::f64 &&
2029 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2030 report_fatal_error("SSE2 register return with SSE2 disabled");
2032 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2033 // the RET instruction and handled by the FP Stackifier.
2034 if (VA.getLocReg() == X86::FP0 ||
2035 VA.getLocReg() == X86::FP1) {
2036 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2037 // change the value to the FP stack register class.
2038 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2039 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2040 RetOps.push_back(ValToCopy);
2041 // Don't emit a copytoreg.
2045 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2046 // which is returned in RAX / RDX.
2047 if (Subtarget->is64Bit()) {
2048 if (ValVT == MVT::x86mmx) {
2049 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2050 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2051 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2053 // If we don't have SSE2 available, convert to v4f32 so the generated
2054 // register is legal.
2055 if (!Subtarget->hasSSE2())
2056 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2061 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2062 Flag = Chain.getValue(1);
2063 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2066 // The x86-64 ABIs require that for returning structs by value we copy
2067 // the sret argument into %rax/%eax (depending on ABI) for the return.
2068 // Win32 requires us to put the sret argument to %eax as well.
2069 // We saved the argument into a virtual register in the entry block,
2070 // so now we copy the value out and into %rax/%eax.
2071 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2072 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2073 MachineFunction &MF = DAG.getMachineFunction();
2074 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2075 unsigned Reg = FuncInfo->getSRetReturnReg();
2077 "SRetReturnReg should have been set in LowerFormalArguments().");
2078 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2081 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2082 X86::RAX : X86::EAX;
2083 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2084 Flag = Chain.getValue(1);
2086 // RAX/EAX now acts like a return value.
2087 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2090 RetOps[0] = Chain; // Update chain.
2092 // Add the flag if we have it.
2094 RetOps.push_back(Flag);
2096 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2099 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2100 if (N->getNumValues() != 1)
2102 if (!N->hasNUsesOfValue(1, 0))
2105 SDValue TCChain = Chain;
2106 SDNode *Copy = *N->use_begin();
2107 if (Copy->getOpcode() == ISD::CopyToReg) {
2108 // If the copy has a glue operand, we conservatively assume it isn't safe to
2109 // perform a tail call.
2110 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2112 TCChain = Copy->getOperand(0);
2113 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2116 bool HasRet = false;
2117 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2119 if (UI->getOpcode() != X86ISD::RET_FLAG)
2121 // If we are returning more than one value, we can definitely
2122 // not make a tail call see PR19530
2123 if (UI->getNumOperands() > 4)
2125 if (UI->getNumOperands() == 4 &&
2126 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2139 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2140 ISD::NodeType ExtendKind) const {
2142 // TODO: Is this also valid on 32-bit?
2143 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2144 ReturnMVT = MVT::i8;
2146 ReturnMVT = MVT::i32;
2148 EVT MinVT = getRegisterType(Context, ReturnMVT);
2149 return VT.bitsLT(MinVT) ? MinVT : VT;
2152 /// LowerCallResult - Lower the result values of a call into the
2153 /// appropriate copies out of appropriate physical registers.
2156 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2157 CallingConv::ID CallConv, bool isVarArg,
2158 const SmallVectorImpl<ISD::InputArg> &Ins,
2159 SDLoc dl, SelectionDAG &DAG,
2160 SmallVectorImpl<SDValue> &InVals) const {
2162 // Assign locations to each value returned by this call.
2163 SmallVector<CCValAssign, 16> RVLocs;
2164 bool Is64Bit = Subtarget->is64Bit();
2165 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2167 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2169 // Copy all of the result registers out of their specified physreg.
2170 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2171 CCValAssign &VA = RVLocs[i];
2172 EVT CopyVT = VA.getValVT();
2174 // If this is x86-64, and we disabled SSE, we can't return FP values
2175 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2176 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2177 report_fatal_error("SSE register return with SSE disabled");
2180 // If we prefer to use the value in xmm registers, copy it out as f80 and
2181 // use a truncate to move it from fp stack reg to xmm reg.
2182 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2183 isScalarFPTypeInSSEReg(VA.getValVT()))
2186 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2187 CopyVT, InFlag).getValue(1);
2188 SDValue Val = Chain.getValue(0);
2190 if (CopyVT != VA.getValVT())
2191 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2192 // This truncation won't change the value.
2193 DAG.getIntPtrConstant(1));
2195 InFlag = Chain.getValue(2);
2196 InVals.push_back(Val);
2202 //===----------------------------------------------------------------------===//
2203 // C & StdCall & Fast Calling Convention implementation
2204 //===----------------------------------------------------------------------===//
2205 // StdCall calling convention seems to be standard for many Windows' API
2206 // routines and around. It differs from C calling convention just a little:
2207 // callee should clean up the stack, not caller. Symbols should be also
2208 // decorated in some fancy way :) It doesn't support any vector arguments.
2209 // For info on fast calling convention see Fast Calling Convention (tail call)
2210 // implementation LowerX86_32FastCCCallTo.
2212 /// CallIsStructReturn - Determines whether a call uses struct return
2214 enum StructReturnType {
2219 static StructReturnType
2220 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2222 return NotStructReturn;
2224 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2225 if (!Flags.isSRet())
2226 return NotStructReturn;
2227 if (Flags.isInReg())
2228 return RegStructReturn;
2229 return StackStructReturn;
2232 /// ArgsAreStructReturn - Determines whether a function uses struct
2233 /// return semantics.
2234 static StructReturnType
2235 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2237 return NotStructReturn;
2239 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2240 if (!Flags.isSRet())
2241 return NotStructReturn;
2242 if (Flags.isInReg())
2243 return RegStructReturn;
2244 return StackStructReturn;
2247 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2248 /// by "Src" to address "Dst" with size and alignment information specified by
2249 /// the specific parameter attribute. The copy will be passed as a byval
2250 /// function parameter.
2252 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2253 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2255 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2257 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2258 /*isVolatile*/false, /*AlwaysInline=*/true,
2259 MachinePointerInfo(), MachinePointerInfo());
2262 /// IsTailCallConvention - Return true if the calling convention is one that
2263 /// supports tail call optimization.
2264 static bool IsTailCallConvention(CallingConv::ID CC) {
2265 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2266 CC == CallingConv::HiPE);
2269 /// \brief Return true if the calling convention is a C calling convention.
2270 static bool IsCCallConvention(CallingConv::ID CC) {
2271 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2272 CC == CallingConv::X86_64_SysV);
2275 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2276 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2280 CallingConv::ID CalleeCC = CS.getCallingConv();
2281 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2287 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2288 /// a tailcall target by changing its ABI.
2289 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2290 bool GuaranteedTailCallOpt) {
2291 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2295 X86TargetLowering::LowerMemArgument(SDValue Chain,
2296 CallingConv::ID CallConv,
2297 const SmallVectorImpl<ISD::InputArg> &Ins,
2298 SDLoc dl, SelectionDAG &DAG,
2299 const CCValAssign &VA,
2300 MachineFrameInfo *MFI,
2302 // Create the nodes corresponding to a load from this parameter slot.
2303 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2304 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2305 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2306 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2309 // If value is passed by pointer we have address passed instead of the value
2311 if (VA.getLocInfo() == CCValAssign::Indirect)
2312 ValVT = VA.getLocVT();
2314 ValVT = VA.getValVT();
2316 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2317 // changed with more analysis.
2318 // In case of tail call optimization mark all arguments mutable. Since they
2319 // could be overwritten by lowering of arguments in case of a tail call.
2320 if (Flags.isByVal()) {
2321 unsigned Bytes = Flags.getByValSize();
2322 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2323 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2324 return DAG.getFrameIndex(FI, getPointerTy());
2326 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2327 VA.getLocMemOffset(), isImmutable);
2328 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2329 return DAG.getLoad(ValVT, dl, Chain, FIN,
2330 MachinePointerInfo::getFixedStack(FI),
2331 false, false, false, 0);
2335 // FIXME: Get this from tablegen.
2336 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2337 const X86Subtarget *Subtarget) {
2338 assert(Subtarget->is64Bit());
2340 if (Subtarget->isCallingConvWin64(CallConv)) {
2341 static const MCPhysReg GPR64ArgRegsWin64[] = {
2342 X86::RCX, X86::RDX, X86::R8, X86::R9
2344 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2347 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2348 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2350 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2355 CallingConv::ID CallConv,
2356 const X86Subtarget *Subtarget) {
2357 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 // The XMM registers which might contain var arg parameters are shadowed
2360 // in their paired GPR. So we only need to save the GPR to their home
2362 // TODO: __vectorcall will change this.
2366 const Function *Fn = MF.getFunction();
2367 bool NoImplicitFloatOps = Fn->getAttributes().
2368 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2369 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2370 "SSE register cannot be used when SSE is disabled!");
2371 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2372 !Subtarget->hasSSE1())
2373 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2377 static const MCPhysReg XMMArgRegs64Bit[] = {
2378 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2379 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2381 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2385 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2386 CallingConv::ID CallConv,
2388 const SmallVectorImpl<ISD::InputArg> &Ins,
2391 SmallVectorImpl<SDValue> &InVals)
2393 MachineFunction &MF = DAG.getMachineFunction();
2394 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2396 const Function* Fn = MF.getFunction();
2397 if (Fn->hasExternalLinkage() &&
2398 Subtarget->isTargetCygMing() &&
2399 Fn->getName() == "main")
2400 FuncInfo->setForceFramePointer(true);
2402 MachineFrameInfo *MFI = MF.getFrameInfo();
2403 bool Is64Bit = Subtarget->is64Bit();
2404 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2406 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2407 "Var args not supported with calling convention fastcc, ghc or hipe");
2409 // Assign locations to all of the incoming arguments.
2410 SmallVector<CCValAssign, 16> ArgLocs;
2411 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2413 // Allocate shadow area for Win64
2415 CCInfo.AllocateStack(32, 8);
2417 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2419 unsigned LastVal = ~0U;
2421 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2422 CCValAssign &VA = ArgLocs[i];
2423 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2425 assert(VA.getValNo() != LastVal &&
2426 "Don't support value assigned to multiple locs yet");
2428 LastVal = VA.getValNo();
2430 if (VA.isRegLoc()) {
2431 EVT RegVT = VA.getLocVT();
2432 const TargetRegisterClass *RC;
2433 if (RegVT == MVT::i32)
2434 RC = &X86::GR32RegClass;
2435 else if (Is64Bit && RegVT == MVT::i64)
2436 RC = &X86::GR64RegClass;
2437 else if (RegVT == MVT::f32)
2438 RC = &X86::FR32RegClass;
2439 else if (RegVT == MVT::f64)
2440 RC = &X86::FR64RegClass;
2441 else if (RegVT.is512BitVector())
2442 RC = &X86::VR512RegClass;
2443 else if (RegVT.is256BitVector())
2444 RC = &X86::VR256RegClass;
2445 else if (RegVT.is128BitVector())
2446 RC = &X86::VR128RegClass;
2447 else if (RegVT == MVT::x86mmx)
2448 RC = &X86::VR64RegClass;
2449 else if (RegVT == MVT::i1)
2450 RC = &X86::VK1RegClass;
2451 else if (RegVT == MVT::v8i1)
2452 RC = &X86::VK8RegClass;
2453 else if (RegVT == MVT::v16i1)
2454 RC = &X86::VK16RegClass;
2455 else if (RegVT == MVT::v32i1)
2456 RC = &X86::VK32RegClass;
2457 else if (RegVT == MVT::v64i1)
2458 RC = &X86::VK64RegClass;
2460 llvm_unreachable("Unknown argument type!");
2462 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2463 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2465 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2466 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2468 if (VA.getLocInfo() == CCValAssign::SExt)
2469 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2470 DAG.getValueType(VA.getValVT()));
2471 else if (VA.getLocInfo() == CCValAssign::ZExt)
2472 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2473 DAG.getValueType(VA.getValVT()));
2474 else if (VA.getLocInfo() == CCValAssign::BCvt)
2475 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2477 if (VA.isExtInLoc()) {
2478 // Handle MMX values passed in XMM regs.
2479 if (RegVT.isVector())
2480 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2482 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2485 assert(VA.isMemLoc());
2486 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2489 // If value is passed via pointer - do a load.
2490 if (VA.getLocInfo() == CCValAssign::Indirect)
2491 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2492 MachinePointerInfo(), false, false, false, 0);
2494 InVals.push_back(ArgValue);
2497 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2498 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2499 // The x86-64 ABIs require that for returning structs by value we copy
2500 // the sret argument into %rax/%eax (depending on ABI) for the return.
2501 // Win32 requires us to put the sret argument to %eax as well.
2502 // Save the argument into a virtual register so that we can access it
2503 // from the return points.
2504 if (Ins[i].Flags.isSRet()) {
2505 unsigned Reg = FuncInfo->getSRetReturnReg();
2507 MVT PtrTy = getPointerTy();
2508 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2509 FuncInfo->setSRetReturnReg(Reg);
2511 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2512 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2518 unsigned StackSize = CCInfo.getNextStackOffset();
2519 // Align stack specially for tail calls.
2520 if (FuncIsMadeTailCallSafe(CallConv,
2521 MF.getTarget().Options.GuaranteedTailCallOpt))
2522 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2524 // If the function takes variable number of arguments, make a frame index for
2525 // the start of the first vararg value... for expansion of llvm.va_start. We
2526 // can skip this if there are no va_start calls.
2527 if (MFI->hasVAStart() &&
2528 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2529 CallConv != CallingConv::X86_ThisCall))) {
2530 FuncInfo->setVarArgsFrameIndex(
2531 MFI->CreateFixedObject(1, StackSize, true));
2534 // 64-bit calling conventions support varargs and register parameters, so we
2535 // have to do extra work to spill them in the prologue or forward them to
2537 if (Is64Bit && isVarArg &&
2538 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2539 // Find the first unallocated argument registers.
2540 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2541 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2542 unsigned NumIntRegs =
2543 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2544 unsigned NumXMMRegs =
2545 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2546 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2547 "SSE register cannot be used when SSE is disabled!");
2549 // Gather all the live in physical registers.
2550 SmallVector<SDValue, 6> LiveGPRs;
2551 SmallVector<SDValue, 8> LiveXMMRegs;
2553 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2554 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2556 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2558 if (!ArgXMMs.empty()) {
2559 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2560 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2561 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2562 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2563 LiveXMMRegs.push_back(
2564 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2568 // Store them to the va_list returned by va_start.
2569 if (MFI->hasVAStart()) {
2571 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2572 // Get to the caller-allocated home save location. Add 8 to account
2573 // for the return address.
2574 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2575 FuncInfo->setRegSaveFrameIndex(
2576 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2577 // Fixup to set vararg frame on shadow area (4 x i64).
2579 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2581 // For X86-64, if there are vararg parameters that are passed via
2582 // registers, then we must store them to their spots on the stack so
2583 // they may be loaded by deferencing the result of va_next.
2584 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2585 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2586 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2587 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2590 // Store the integer parameter registers.
2591 SmallVector<SDValue, 8> MemOps;
2592 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2594 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2595 for (SDValue Val : LiveGPRs) {
2596 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2597 DAG.getIntPtrConstant(Offset));
2599 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2600 MachinePointerInfo::getFixedStack(
2601 FuncInfo->getRegSaveFrameIndex(), Offset),
2603 MemOps.push_back(Store);
2607 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2608 // Now store the XMM (fp + vector) parameter registers.
2609 SmallVector<SDValue, 12> SaveXMMOps;
2610 SaveXMMOps.push_back(Chain);
2611 SaveXMMOps.push_back(ALVal);
2612 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2613 FuncInfo->getRegSaveFrameIndex()));
2614 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2615 FuncInfo->getVarArgsFPOffset()));
2616 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2618 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2619 MVT::Other, SaveXMMOps));
2622 if (!MemOps.empty())
2623 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2625 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2626 // to the liveout set on a musttail call.
2627 assert(MFI->hasMustTailInVarArgFunc());
2628 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2629 typedef X86MachineFunctionInfo::Forward Forward;
2631 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2633 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2634 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2635 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2638 if (!ArgXMMs.empty()) {
2640 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2641 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2642 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2644 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2646 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2647 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2649 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2655 // Some CCs need callee pop.
2656 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2657 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2658 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2660 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2661 // If this is an sret function, the return should pop the hidden pointer.
2662 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2663 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2664 argsAreStructReturn(Ins) == StackStructReturn)
2665 FuncInfo->setBytesToPopOnReturn(4);
2669 // RegSaveFrameIndex is X86-64 only.
2670 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2671 if (CallConv == CallingConv::X86_FastCall ||
2672 CallConv == CallingConv::X86_ThisCall)
2673 // fastcc functions can't have varargs.
2674 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2677 FuncInfo->setArgumentStackSize(StackSize);
2683 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2684 SDValue StackPtr, SDValue Arg,
2685 SDLoc dl, SelectionDAG &DAG,
2686 const CCValAssign &VA,
2687 ISD::ArgFlagsTy Flags) const {
2688 unsigned LocMemOffset = VA.getLocMemOffset();
2689 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2690 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2691 if (Flags.isByVal())
2692 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2694 return DAG.getStore(Chain, dl, Arg, PtrOff,
2695 MachinePointerInfo::getStack(LocMemOffset),
2699 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2700 /// optimization is performed and it is required.
2702 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2703 SDValue &OutRetAddr, SDValue Chain,
2704 bool IsTailCall, bool Is64Bit,
2705 int FPDiff, SDLoc dl) const {
2706 // Adjust the Return address stack slot.
2707 EVT VT = getPointerTy();
2708 OutRetAddr = getReturnAddressFrameIndex(DAG);
2710 // Load the "old" Return address.
2711 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2712 false, false, false, 0);
2713 return SDValue(OutRetAddr.getNode(), 1);
2716 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2717 /// optimization is performed and it is required (FPDiff!=0).
2718 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2719 SDValue Chain, SDValue RetAddrFrIdx,
2720 EVT PtrVT, unsigned SlotSize,
2721 int FPDiff, SDLoc dl) {
2722 // Store the return address to the appropriate stack slot.
2723 if (!FPDiff) return Chain;
2724 // Calculate the new stack slot for the return address.
2725 int NewReturnAddrFI =
2726 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2728 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2729 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2730 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2736 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2737 SmallVectorImpl<SDValue> &InVals) const {
2738 SelectionDAG &DAG = CLI.DAG;
2740 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2741 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2742 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2743 SDValue Chain = CLI.Chain;
2744 SDValue Callee = CLI.Callee;
2745 CallingConv::ID CallConv = CLI.CallConv;
2746 bool &isTailCall = CLI.IsTailCall;
2747 bool isVarArg = CLI.IsVarArg;
2749 MachineFunction &MF = DAG.getMachineFunction();
2750 bool Is64Bit = Subtarget->is64Bit();
2751 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2752 StructReturnType SR = callIsStructReturn(Outs);
2753 bool IsSibcall = false;
2754 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2756 if (MF.getTarget().Options.DisableTailCalls)
2759 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2761 // Force this to be a tail call. The verifier rules are enough to ensure
2762 // that we can lower this successfully without moving the return address
2765 } else if (isTailCall) {
2766 // Check if it's really possible to do a tail call.
2767 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2768 isVarArg, SR != NotStructReturn,
2769 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2770 Outs, OutVals, Ins, DAG);
2772 // Sibcalls are automatically detected tailcalls which do not require
2774 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2781 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2782 "Var args not supported with calling convention fastcc, ghc or hipe");
2784 // Analyze operands of the call, assigning locations to each operand.
2785 SmallVector<CCValAssign, 16> ArgLocs;
2786 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2788 // Allocate shadow area for Win64
2790 CCInfo.AllocateStack(32, 8);
2792 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2794 // Get a count of how many bytes are to be pushed on the stack.
2795 unsigned NumBytes = CCInfo.getNextStackOffset();
2797 // This is a sibcall. The memory operands are available in caller's
2798 // own caller's stack.
2800 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2801 IsTailCallConvention(CallConv))
2802 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2805 if (isTailCall && !IsSibcall && !IsMustTail) {
2806 // Lower arguments at fp - stackoffset + fpdiff.
2807 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2809 FPDiff = NumBytesCallerPushed - NumBytes;
2811 // Set the delta of movement of the returnaddr stackslot.
2812 // But only set if delta is greater than previous delta.
2813 if (FPDiff < X86Info->getTCReturnAddrDelta())
2814 X86Info->setTCReturnAddrDelta(FPDiff);
2817 unsigned NumBytesToPush = NumBytes;
2818 unsigned NumBytesToPop = NumBytes;
2820 // If we have an inalloca argument, all stack space has already been allocated
2821 // for us and be right at the top of the stack. We don't support multiple
2822 // arguments passed in memory when using inalloca.
2823 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2825 if (!ArgLocs.back().isMemLoc())
2826 report_fatal_error("cannot use inalloca attribute on a register "
2828 if (ArgLocs.back().getLocMemOffset() != 0)
2829 report_fatal_error("any parameter with the inalloca attribute must be "
2830 "the only memory argument");
2834 Chain = DAG.getCALLSEQ_START(
2835 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2837 SDValue RetAddrFrIdx;
2838 // Load return address for tail calls.
2839 if (isTailCall && FPDiff)
2840 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2841 Is64Bit, FPDiff, dl);
2843 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2844 SmallVector<SDValue, 8> MemOpChains;
2847 // Walk the register/memloc assignments, inserting copies/loads. In the case
2848 // of tail call optimization arguments are handle later.
2849 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2850 DAG.getSubtarget().getRegisterInfo());
2851 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2852 // Skip inalloca arguments, they have already been written.
2853 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2854 if (Flags.isInAlloca())
2857 CCValAssign &VA = ArgLocs[i];
2858 EVT RegVT = VA.getLocVT();
2859 SDValue Arg = OutVals[i];
2860 bool isByVal = Flags.isByVal();
2862 // Promote the value if needed.
2863 switch (VA.getLocInfo()) {
2864 default: llvm_unreachable("Unknown loc info!");
2865 case CCValAssign::Full: break;
2866 case CCValAssign::SExt:
2867 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2869 case CCValAssign::ZExt:
2870 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2872 case CCValAssign::AExt:
2873 if (RegVT.is128BitVector()) {
2874 // Special case: passing MMX values in XMM registers.
2875 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2876 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2877 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2879 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2881 case CCValAssign::BCvt:
2882 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2884 case CCValAssign::Indirect: {
2885 // Store the argument.
2886 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2887 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2888 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2889 MachinePointerInfo::getFixedStack(FI),
2896 if (VA.isRegLoc()) {
2897 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2898 if (isVarArg && IsWin64) {
2899 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2900 // shadow reg if callee is a varargs function.
2901 unsigned ShadowReg = 0;
2902 switch (VA.getLocReg()) {
2903 case X86::XMM0: ShadowReg = X86::RCX; break;
2904 case X86::XMM1: ShadowReg = X86::RDX; break;
2905 case X86::XMM2: ShadowReg = X86::R8; break;
2906 case X86::XMM3: ShadowReg = X86::R9; break;
2909 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2911 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2912 assert(VA.isMemLoc());
2913 if (!StackPtr.getNode())
2914 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2916 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2917 dl, DAG, VA, Flags));
2921 if (!MemOpChains.empty())
2922 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2924 if (Subtarget->isPICStyleGOT()) {
2925 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2928 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2929 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2931 // If we are tail calling and generating PIC/GOT style code load the
2932 // address of the callee into ECX. The value in ecx is used as target of
2933 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2934 // for tail calls on PIC/GOT architectures. Normally we would just put the
2935 // address of GOT into ebx and then call target@PLT. But for tail calls
2936 // ebx would be restored (since ebx is callee saved) before jumping to the
2939 // Note: The actual moving to ECX is done further down.
2940 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2941 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2942 !G->getGlobal()->hasProtectedVisibility())
2943 Callee = LowerGlobalAddress(Callee, DAG);
2944 else if (isa<ExternalSymbolSDNode>(Callee))
2945 Callee = LowerExternalSymbol(Callee, DAG);
2949 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2950 // From AMD64 ABI document:
2951 // For calls that may call functions that use varargs or stdargs
2952 // (prototype-less calls or calls to functions containing ellipsis (...) in
2953 // the declaration) %al is used as hidden argument to specify the number
2954 // of SSE registers used. The contents of %al do not need to match exactly
2955 // the number of registers, but must be an ubound on the number of SSE
2956 // registers used and is in the range 0 - 8 inclusive.
2958 // Count the number of XMM registers allocated.
2959 static const MCPhysReg XMMArgRegs[] = {
2960 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2961 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2963 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2964 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2965 && "SSE registers cannot be used when SSE is disabled");
2967 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2968 DAG.getConstant(NumXMMRegs, MVT::i8)));
2971 if (Is64Bit && isVarArg && IsMustTail) {
2972 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2973 for (const auto &F : Forwards) {
2974 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2975 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2979 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2980 // don't need this because the eligibility check rejects calls that require
2981 // shuffling arguments passed in memory.
2982 if (!IsSibcall && isTailCall) {
2983 // Force all the incoming stack arguments to be loaded from the stack
2984 // before any new outgoing arguments are stored to the stack, because the
2985 // outgoing stack slots may alias the incoming argument stack slots, and
2986 // the alias isn't otherwise explicit. This is slightly more conservative
2987 // than necessary, because it means that each store effectively depends
2988 // on every argument instead of just those arguments it would clobber.
2989 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2991 SmallVector<SDValue, 8> MemOpChains2;
2994 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2995 CCValAssign &VA = ArgLocs[i];
2998 assert(VA.isMemLoc());
2999 SDValue Arg = OutVals[i];
3000 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3001 // Skip inalloca arguments. They don't require any work.
3002 if (Flags.isInAlloca())
3004 // Create frame index.
3005 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3006 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3007 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3008 FIN = DAG.getFrameIndex(FI, getPointerTy());
3010 if (Flags.isByVal()) {
3011 // Copy relative to framepointer.
3012 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3013 if (!StackPtr.getNode())
3014 StackPtr = DAG.getCopyFromReg(Chain, dl,
3015 RegInfo->getStackRegister(),
3017 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3019 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3023 // Store relative to framepointer.
3024 MemOpChains2.push_back(
3025 DAG.getStore(ArgChain, dl, Arg, FIN,
3026 MachinePointerInfo::getFixedStack(FI),
3031 if (!MemOpChains2.empty())
3032 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3034 // Store the return address to the appropriate stack slot.
3035 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3036 getPointerTy(), RegInfo->getSlotSize(),
3040 // Build a sequence of copy-to-reg nodes chained together with token chain
3041 // and flag operands which copy the outgoing args into registers.
3043 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3044 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3045 RegsToPass[i].second, InFlag);
3046 InFlag = Chain.getValue(1);
3049 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3050 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3051 // In the 64-bit large code model, we have to make all calls
3052 // through a register, since the call instruction's 32-bit
3053 // pc-relative offset may not be large enough to hold the whole
3055 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3056 // If the callee is a GlobalAddress node (quite common, every direct call
3057 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3060 // We should use extra load for direct calls to dllimported functions in
3062 const GlobalValue *GV = G->getGlobal();
3063 if (!GV->hasDLLImportStorageClass()) {
3064 unsigned char OpFlags = 0;
3065 bool ExtraLoad = false;
3066 unsigned WrapperKind = ISD::DELETED_NODE;
3068 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3069 // external symbols most go through the PLT in PIC mode. If the symbol
3070 // has hidden or protected visibility, or if it is static or local, then
3071 // we don't need to use the PLT - we can directly call it.
3072 if (Subtarget->isTargetELF() &&
3073 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3074 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3075 OpFlags = X86II::MO_PLT;
3076 } else if (Subtarget->isPICStyleStubAny() &&
3077 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3078 (!Subtarget->getTargetTriple().isMacOSX() ||
3079 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3080 // PC-relative references to external symbols should go through $stub,
3081 // unless we're building with the leopard linker or later, which
3082 // automatically synthesizes these stubs.
3083 OpFlags = X86II::MO_DARWIN_STUB;
3084 } else if (Subtarget->isPICStyleRIPRel() &&
3085 isa<Function>(GV) &&
3086 cast<Function>(GV)->getAttributes().
3087 hasAttribute(AttributeSet::FunctionIndex,
3088 Attribute::NonLazyBind)) {
3089 // If the function is marked as non-lazy, generate an indirect call
3090 // which loads from the GOT directly. This avoids runtime overhead
3091 // at the cost of eager binding (and one extra byte of encoding).
3092 OpFlags = X86II::MO_GOTPCREL;
3093 WrapperKind = X86ISD::WrapperRIP;
3097 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3098 G->getOffset(), OpFlags);
3100 // Add a wrapper if needed.
3101 if (WrapperKind != ISD::DELETED_NODE)
3102 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3103 // Add extra indirection if needed.
3105 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3106 MachinePointerInfo::getGOT(),
3107 false, false, false, 0);
3109 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3110 unsigned char OpFlags = 0;
3112 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3113 // external symbols should go through the PLT.
3114 if (Subtarget->isTargetELF() &&
3115 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3116 OpFlags = X86II::MO_PLT;
3117 } else if (Subtarget->isPICStyleStubAny() &&
3118 (!Subtarget->getTargetTriple().isMacOSX() ||
3119 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3120 // PC-relative references to external symbols should go through $stub,
3121 // unless we're building with the leopard linker or later, which
3122 // automatically synthesizes these stubs.
3123 OpFlags = X86II::MO_DARWIN_STUB;
3126 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3128 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3129 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3130 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3133 // Returns a chain & a flag for retval copy to use.
3134 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3135 SmallVector<SDValue, 8> Ops;
3137 if (!IsSibcall && isTailCall) {
3138 Chain = DAG.getCALLSEQ_END(Chain,
3139 DAG.getIntPtrConstant(NumBytesToPop, true),
3140 DAG.getIntPtrConstant(0, true), InFlag, dl);
3141 InFlag = Chain.getValue(1);
3144 Ops.push_back(Chain);
3145 Ops.push_back(Callee);
3148 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3150 // Add argument registers to the end of the list so that they are known live
3152 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3153 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3154 RegsToPass[i].second.getValueType()));
3156 // Add a register mask operand representing the call-preserved registers.
3157 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3158 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3159 assert(Mask && "Missing call preserved mask for calling convention");
3160 Ops.push_back(DAG.getRegisterMask(Mask));
3162 if (InFlag.getNode())
3163 Ops.push_back(InFlag);
3167 //// If this is the first return lowered for this function, add the regs
3168 //// to the liveout set for the function.
3169 // This isn't right, although it's probably harmless on x86; liveouts
3170 // should be computed from returns not tail calls. Consider a void
3171 // function making a tail call to a function returning int.
3172 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3175 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3176 InFlag = Chain.getValue(1);
3178 // Create the CALLSEQ_END node.
3179 unsigned NumBytesForCalleeToPop;
3180 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3181 DAG.getTarget().Options.GuaranteedTailCallOpt))
3182 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3183 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3184 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3185 SR == StackStructReturn)
3186 // If this is a call to a struct-return function, the callee
3187 // pops the hidden struct pointer, so we have to push it back.
3188 // This is common for Darwin/X86, Linux & Mingw32 targets.
3189 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3190 NumBytesForCalleeToPop = 4;
3192 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3194 // Returns a flag for retval copy to use.
3196 Chain = DAG.getCALLSEQ_END(Chain,
3197 DAG.getIntPtrConstant(NumBytesToPop, true),
3198 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3201 InFlag = Chain.getValue(1);
3204 // Handle result values, copying them out of physregs into vregs that we
3206 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3207 Ins, dl, DAG, InVals);
3210 //===----------------------------------------------------------------------===//
3211 // Fast Calling Convention (tail call) implementation
3212 //===----------------------------------------------------------------------===//
3214 // Like std call, callee cleans arguments, convention except that ECX is
3215 // reserved for storing the tail called function address. Only 2 registers are
3216 // free for argument passing (inreg). Tail call optimization is performed
3218 // * tailcallopt is enabled
3219 // * caller/callee are fastcc
3220 // On X86_64 architecture with GOT-style position independent code only local
3221 // (within module) calls are supported at the moment.
3222 // To keep the stack aligned according to platform abi the function
3223 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3224 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3225 // If a tail called function callee has more arguments than the caller the
3226 // caller needs to make sure that there is room to move the RETADDR to. This is
3227 // achieved by reserving an area the size of the argument delta right after the
3228 // original RETADDR, but before the saved framepointer or the spilled registers
3229 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3241 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3242 /// for a 16 byte align requirement.
3244 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3245 SelectionDAG& DAG) const {
3246 MachineFunction &MF = DAG.getMachineFunction();
3247 const TargetMachine &TM = MF.getTarget();
3248 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3249 TM.getSubtargetImpl()->getRegisterInfo());
3250 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3251 unsigned StackAlignment = TFI.getStackAlignment();
3252 uint64_t AlignMask = StackAlignment - 1;
3253 int64_t Offset = StackSize;
3254 unsigned SlotSize = RegInfo->getSlotSize();
3255 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3256 // Number smaller than 12 so just add the difference.
3257 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3259 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3260 Offset = ((~AlignMask) & Offset) + StackAlignment +
3261 (StackAlignment-SlotSize);
3266 /// MatchingStackOffset - Return true if the given stack call argument is
3267 /// already available in the same position (relatively) of the caller's
3268 /// incoming argument stack.
3270 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3271 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3272 const X86InstrInfo *TII) {
3273 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3275 if (Arg.getOpcode() == ISD::CopyFromReg) {
3276 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3277 if (!TargetRegisterInfo::isVirtualRegister(VR))
3279 MachineInstr *Def = MRI->getVRegDef(VR);
3282 if (!Flags.isByVal()) {
3283 if (!TII->isLoadFromStackSlot(Def, FI))
3286 unsigned Opcode = Def->getOpcode();
3287 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3288 Def->getOperand(1).isFI()) {
3289 FI = Def->getOperand(1).getIndex();
3290 Bytes = Flags.getByValSize();
3294 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3295 if (Flags.isByVal())
3296 // ByVal argument is passed in as a pointer but it's now being
3297 // dereferenced. e.g.
3298 // define @foo(%struct.X* %A) {
3299 // tail call @bar(%struct.X* byval %A)
3302 SDValue Ptr = Ld->getBasePtr();
3303 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3306 FI = FINode->getIndex();
3307 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3308 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3309 FI = FINode->getIndex();
3310 Bytes = Flags.getByValSize();
3314 assert(FI != INT_MAX);
3315 if (!MFI->isFixedObjectIndex(FI))
3317 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3320 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3321 /// for tail call optimization. Targets which want to do tail call
3322 /// optimization should implement this function.
3324 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3325 CallingConv::ID CalleeCC,
3327 bool isCalleeStructRet,
3328 bool isCallerStructRet,
3330 const SmallVectorImpl<ISD::OutputArg> &Outs,
3331 const SmallVectorImpl<SDValue> &OutVals,
3332 const SmallVectorImpl<ISD::InputArg> &Ins,
3333 SelectionDAG &DAG) const {
3334 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3337 // If -tailcallopt is specified, make fastcc functions tail-callable.
3338 const MachineFunction &MF = DAG.getMachineFunction();
3339 const Function *CallerF = MF.getFunction();
3341 // If the function return type is x86_fp80 and the callee return type is not,
3342 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3343 // perform a tailcall optimization here.
3344 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3347 CallingConv::ID CallerCC = CallerF->getCallingConv();
3348 bool CCMatch = CallerCC == CalleeCC;
3349 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3350 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3352 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3353 if (IsTailCallConvention(CalleeCC) && CCMatch)
3358 // Look for obvious safe cases to perform tail call optimization that do not
3359 // require ABI changes. This is what gcc calls sibcall.
3361 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3362 // emit a special epilogue.
3363 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3364 DAG.getSubtarget().getRegisterInfo());
3365 if (RegInfo->needsStackRealignment(MF))
3368 // Also avoid sibcall optimization if either caller or callee uses struct
3369 // return semantics.
3370 if (isCalleeStructRet || isCallerStructRet)
3373 // An stdcall/thiscall caller is expected to clean up its arguments; the
3374 // callee isn't going to do that.
3375 // FIXME: this is more restrictive than needed. We could produce a tailcall
3376 // when the stack adjustment matches. For example, with a thiscall that takes
3377 // only one argument.
3378 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3379 CallerCC == CallingConv::X86_ThisCall))
3382 // Do not sibcall optimize vararg calls unless all arguments are passed via
3384 if (isVarArg && !Outs.empty()) {
3386 // Optimizing for varargs on Win64 is unlikely to be safe without
3387 // additional testing.
3388 if (IsCalleeWin64 || IsCallerWin64)
3391 SmallVector<CCValAssign, 16> ArgLocs;
3392 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3395 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3397 if (!ArgLocs[i].isRegLoc())
3401 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3402 // stack. Therefore, if it's not used by the call it is not safe to optimize
3403 // this into a sibcall.
3404 bool Unused = false;
3405 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3412 SmallVector<CCValAssign, 16> RVLocs;
3413 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3415 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3416 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3417 CCValAssign &VA = RVLocs[i];
3418 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3423 // If the calling conventions do not match, then we'd better make sure the
3424 // results are returned in the same way as what the caller expects.
3426 SmallVector<CCValAssign, 16> RVLocs1;
3427 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3429 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3431 SmallVector<CCValAssign, 16> RVLocs2;
3432 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3434 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3436 if (RVLocs1.size() != RVLocs2.size())
3438 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3439 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3441 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3443 if (RVLocs1[i].isRegLoc()) {
3444 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3447 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3453 // If the callee takes no arguments then go on to check the results of the
3455 if (!Outs.empty()) {
3456 // Check if stack adjustment is needed. For now, do not do this if any
3457 // argument is passed on the stack.
3458 SmallVector<CCValAssign, 16> ArgLocs;
3459 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3462 // Allocate shadow area for Win64
3464 CCInfo.AllocateStack(32, 8);
3466 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3467 if (CCInfo.getNextStackOffset()) {
3468 MachineFunction &MF = DAG.getMachineFunction();
3469 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3472 // Check if the arguments are already laid out in the right way as
3473 // the caller's fixed stack objects.
3474 MachineFrameInfo *MFI = MF.getFrameInfo();
3475 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3476 const X86InstrInfo *TII =
3477 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3478 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3479 CCValAssign &VA = ArgLocs[i];
3480 SDValue Arg = OutVals[i];
3481 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3482 if (VA.getLocInfo() == CCValAssign::Indirect)
3484 if (!VA.isRegLoc()) {
3485 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3492 // If the tailcall address may be in a register, then make sure it's
3493 // possible to register allocate for it. In 32-bit, the call address can
3494 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3495 // callee-saved registers are restored. These happen to be the same
3496 // registers used to pass 'inreg' arguments so watch out for those.
3497 if (!Subtarget->is64Bit() &&
3498 ((!isa<GlobalAddressSDNode>(Callee) &&
3499 !isa<ExternalSymbolSDNode>(Callee)) ||
3500 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3501 unsigned NumInRegs = 0;
3502 // In PIC we need an extra register to formulate the address computation
3504 unsigned MaxInRegs =
3505 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3507 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3508 CCValAssign &VA = ArgLocs[i];
3511 unsigned Reg = VA.getLocReg();
3514 case X86::EAX: case X86::EDX: case X86::ECX:
3515 if (++NumInRegs == MaxInRegs)
3527 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3528 const TargetLibraryInfo *libInfo) const {
3529 return X86::createFastISel(funcInfo, libInfo);
3532 //===----------------------------------------------------------------------===//
3533 // Other Lowering Hooks
3534 //===----------------------------------------------------------------------===//
3536 static bool MayFoldLoad(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3540 static bool MayFoldIntoStore(SDValue Op) {
3541 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3544 static bool isTargetShuffle(unsigned Opcode) {
3546 default: return false;
3547 case X86ISD::BLENDI:
3548 case X86ISD::PSHUFB:
3549 case X86ISD::PSHUFD:
3550 case X86ISD::PSHUFHW:
3551 case X86ISD::PSHUFLW:
3553 case X86ISD::PALIGNR:
3554 case X86ISD::MOVLHPS:
3555 case X86ISD::MOVLHPD:
3556 case X86ISD::MOVHLPS:
3557 case X86ISD::MOVLPS:
3558 case X86ISD::MOVLPD:
3559 case X86ISD::MOVSHDUP:
3560 case X86ISD::MOVSLDUP:
3561 case X86ISD::MOVDDUP:
3564 case X86ISD::UNPCKL:
3565 case X86ISD::UNPCKH:
3566 case X86ISD::VPERMILPI:
3567 case X86ISD::VPERM2X128:
3568 case X86ISD::VPERMI:
3573 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3574 SDValue V1, SelectionDAG &DAG) {
3576 default: llvm_unreachable("Unknown x86 shuffle node");
3577 case X86ISD::MOVSHDUP:
3578 case X86ISD::MOVSLDUP:
3579 case X86ISD::MOVDDUP:
3580 return DAG.getNode(Opc, dl, VT, V1);
3584 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3585 SDValue V1, unsigned TargetMask,
3586 SelectionDAG &DAG) {
3588 default: llvm_unreachable("Unknown x86 shuffle node");
3589 case X86ISD::PSHUFD:
3590 case X86ISD::PSHUFHW:
3591 case X86ISD::PSHUFLW:
3592 case X86ISD::VPERMILPI:
3593 case X86ISD::VPERMI:
3594 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3598 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3599 SDValue V1, SDValue V2, unsigned TargetMask,
3600 SelectionDAG &DAG) {
3602 default: llvm_unreachable("Unknown x86 shuffle node");
3603 case X86ISD::PALIGNR:
3604 case X86ISD::VALIGN:
3606 case X86ISD::VPERM2X128:
3607 return DAG.getNode(Opc, dl, VT, V1, V2,
3608 DAG.getConstant(TargetMask, MVT::i8));
3612 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3613 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3615 default: llvm_unreachable("Unknown x86 shuffle node");
3616 case X86ISD::MOVLHPS:
3617 case X86ISD::MOVLHPD:
3618 case X86ISD::MOVHLPS:
3619 case X86ISD::MOVLPS:
3620 case X86ISD::MOVLPD:
3623 case X86ISD::UNPCKL:
3624 case X86ISD::UNPCKH:
3625 return DAG.getNode(Opc, dl, VT, V1, V2);
3629 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3630 MachineFunction &MF = DAG.getMachineFunction();
3631 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3632 DAG.getSubtarget().getRegisterInfo());
3633 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3634 int ReturnAddrIndex = FuncInfo->getRAIndex();
3636 if (ReturnAddrIndex == 0) {
3637 // Set up a frame object for the return address.
3638 unsigned SlotSize = RegInfo->getSlotSize();
3639 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3642 FuncInfo->setRAIndex(ReturnAddrIndex);
3645 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3648 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3649 bool hasSymbolicDisplacement) {
3650 // Offset should fit into 32 bit immediate field.
3651 if (!isInt<32>(Offset))
3654 // If we don't have a symbolic displacement - we don't have any extra
3656 if (!hasSymbolicDisplacement)
3659 // FIXME: Some tweaks might be needed for medium code model.
3660 if (M != CodeModel::Small && M != CodeModel::Kernel)
3663 // For small code model we assume that latest object is 16MB before end of 31
3664 // bits boundary. We may also accept pretty large negative constants knowing
3665 // that all objects are in the positive half of address space.
3666 if (M == CodeModel::Small && Offset < 16*1024*1024)
3669 // For kernel code model we know that all object resist in the negative half
3670 // of 32bits address space. We may not accept negative offsets, since they may
3671 // be just off and we may accept pretty large positive ones.
3672 if (M == CodeModel::Kernel && Offset > 0)
3678 /// isCalleePop - Determines whether the callee is required to pop its
3679 /// own arguments. Callee pop is necessary to support tail calls.
3680 bool X86::isCalleePop(CallingConv::ID CallingConv,
3681 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3682 switch (CallingConv) {
3685 case CallingConv::X86_StdCall:
3686 case CallingConv::X86_FastCall:
3687 case CallingConv::X86_ThisCall:
3689 case CallingConv::Fast:
3690 case CallingConv::GHC:
3691 case CallingConv::HiPE:
3698 /// \brief Return true if the condition is an unsigned comparison operation.
3699 static bool isX86CCUnsigned(unsigned X86CC) {
3701 default: llvm_unreachable("Invalid integer condition!");
3702 case X86::COND_E: return true;
3703 case X86::COND_G: return false;
3704 case X86::COND_GE: return false;
3705 case X86::COND_L: return false;
3706 case X86::COND_LE: return false;
3707 case X86::COND_NE: return true;
3708 case X86::COND_B: return true;
3709 case X86::COND_A: return true;
3710 case X86::COND_BE: return true;
3711 case X86::COND_AE: return true;
3713 llvm_unreachable("covered switch fell through?!");
3716 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3717 /// specific condition code, returning the condition code and the LHS/RHS of the
3718 /// comparison to make.
3719 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3720 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3722 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3723 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3724 // X > -1 -> X == 0, jump !sign.
3725 RHS = DAG.getConstant(0, RHS.getValueType());
3726 return X86::COND_NS;
3728 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3729 // X < 0 -> X == 0, jump on sign.
3732 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3734 RHS = DAG.getConstant(0, RHS.getValueType());
3735 return X86::COND_LE;
3739 switch (SetCCOpcode) {
3740 default: llvm_unreachable("Invalid integer condition!");
3741 case ISD::SETEQ: return X86::COND_E;
3742 case ISD::SETGT: return X86::COND_G;
3743 case ISD::SETGE: return X86::COND_GE;
3744 case ISD::SETLT: return X86::COND_L;
3745 case ISD::SETLE: return X86::COND_LE;
3746 case ISD::SETNE: return X86::COND_NE;
3747 case ISD::SETULT: return X86::COND_B;
3748 case ISD::SETUGT: return X86::COND_A;
3749 case ISD::SETULE: return X86::COND_BE;
3750 case ISD::SETUGE: return X86::COND_AE;
3754 // First determine if it is required or is profitable to flip the operands.
3756 // If LHS is a foldable load, but RHS is not, flip the condition.
3757 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3758 !ISD::isNON_EXTLoad(RHS.getNode())) {
3759 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3760 std::swap(LHS, RHS);
3763 switch (SetCCOpcode) {
3769 std::swap(LHS, RHS);
3773 // On a floating point condition, the flags are set as follows:
3775 // 0 | 0 | 0 | X > Y
3776 // 0 | 0 | 1 | X < Y
3777 // 1 | 0 | 0 | X == Y
3778 // 1 | 1 | 1 | unordered
3779 switch (SetCCOpcode) {
3780 default: llvm_unreachable("Condcode should be pre-legalized away");
3782 case ISD::SETEQ: return X86::COND_E;
3783 case ISD::SETOLT: // flipped
3785 case ISD::SETGT: return X86::COND_A;
3786 case ISD::SETOLE: // flipped
3788 case ISD::SETGE: return X86::COND_AE;
3789 case ISD::SETUGT: // flipped
3791 case ISD::SETLT: return X86::COND_B;
3792 case ISD::SETUGE: // flipped
3794 case ISD::SETLE: return X86::COND_BE;
3796 case ISD::SETNE: return X86::COND_NE;
3797 case ISD::SETUO: return X86::COND_P;
3798 case ISD::SETO: return X86::COND_NP;
3800 case ISD::SETUNE: return X86::COND_INVALID;
3804 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3805 /// code. Current x86 isa includes the following FP cmov instructions:
3806 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3807 static bool hasFPCMov(unsigned X86CC) {
3823 /// isFPImmLegal - Returns true if the target can instruction select the
3824 /// specified FP immediate natively. If false, the legalizer will
3825 /// materialize the FP immediate as a load from a constant pool.
3826 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3827 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3828 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3834 /// \brief Returns true if it is beneficial to convert a load of a constant
3835 /// to just the constant itself.
3836 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3838 assert(Ty->isIntegerTy());
3840 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3841 if (BitSize == 0 || BitSize > 64)
3846 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3847 /// the specified range (L, H].
3848 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3849 return (Val < 0) || (Val >= Low && Val < Hi);
3852 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3853 /// specified value.
3854 static bool isUndefOrEqual(int Val, int CmpVal) {
3855 return (Val < 0 || Val == CmpVal);
3858 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3859 /// from position Pos and ending in Pos+Size, falls within the specified
3860 /// sequential range (L, L+Pos]. or is undef.
3861 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3862 unsigned Pos, unsigned Size, int Low) {
3863 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3864 if (!isUndefOrEqual(Mask[i], Low))
3869 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3870 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3871 /// the second operand.
3872 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3873 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3874 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3875 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3876 return (Mask[0] < 2 && Mask[1] < 2);
3880 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3881 /// is suitable for input to PSHUFHW.
3882 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3883 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3886 // Lower quadword copied in order or undef.
3887 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3890 // Upper quadword shuffled.
3891 for (unsigned i = 4; i != 8; ++i)
3892 if (!isUndefOrInRange(Mask[i], 4, 8))
3895 if (VT == MVT::v16i16) {
3896 // Lower quadword copied in order or undef.
3897 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3900 // Upper quadword shuffled.
3901 for (unsigned i = 12; i != 16; ++i)
3902 if (!isUndefOrInRange(Mask[i], 12, 16))
3909 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3910 /// is suitable for input to PSHUFLW.
3911 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3912 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3915 // Upper quadword copied in order.
3916 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3919 // Lower quadword shuffled.
3920 for (unsigned i = 0; i != 4; ++i)
3921 if (!isUndefOrInRange(Mask[i], 0, 4))
3924 if (VT == MVT::v16i16) {
3925 // Upper quadword copied in order.
3926 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3929 // Lower quadword shuffled.
3930 for (unsigned i = 8; i != 12; ++i)
3931 if (!isUndefOrInRange(Mask[i], 8, 12))
3938 /// \brief Return true if the mask specifies a shuffle of elements that is
3939 /// suitable for input to intralane (palignr) or interlane (valign) vector
3941 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3942 unsigned NumElts = VT.getVectorNumElements();
3943 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3944 unsigned NumLaneElts = NumElts/NumLanes;
3946 // Do not handle 64-bit element shuffles with palignr.
3947 if (NumLaneElts == 2)
3950 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3952 for (i = 0; i != NumLaneElts; ++i) {
3957 // Lane is all undef, go to next lane
3958 if (i == NumLaneElts)
3961 int Start = Mask[i+l];
3963 // Make sure its in this lane in one of the sources
3964 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3965 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3968 // If not lane 0, then we must match lane 0
3969 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3972 // Correct second source to be contiguous with first source
3973 if (Start >= (int)NumElts)
3974 Start -= NumElts - NumLaneElts;
3976 // Make sure we're shifting in the right direction.
3977 if (Start <= (int)(i+l))
3982 // Check the rest of the elements to see if they are consecutive.
3983 for (++i; i != NumLaneElts; ++i) {
3984 int Idx = Mask[i+l];
3986 // Make sure its in this lane
3987 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3988 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3991 // If not lane 0, then we must match lane 0
3992 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3995 if (Idx >= (int)NumElts)
3996 Idx -= NumElts - NumLaneElts;
3998 if (!isUndefOrEqual(Idx, Start+i))
4007 /// \brief Return true if the node specifies a shuffle of elements that is
4008 /// suitable for input to PALIGNR.
4009 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4010 const X86Subtarget *Subtarget) {
4011 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4012 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4013 VT.is512BitVector())
4014 // FIXME: Add AVX512BW.
4017 return isAlignrMask(Mask, VT, false);
4020 /// \brief Return true if the node specifies a shuffle of elements that is
4021 /// suitable for input to VALIGN.
4022 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4023 const X86Subtarget *Subtarget) {
4024 // FIXME: Add AVX512VL.
4025 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4027 return isAlignrMask(Mask, VT, true);
4030 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4031 /// the two vector operands have swapped position.
4032 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4033 unsigned NumElems) {
4034 for (unsigned i = 0; i != NumElems; ++i) {
4038 else if (idx < (int)NumElems)
4039 Mask[i] = idx + NumElems;
4041 Mask[i] = idx - NumElems;
4045 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4046 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4047 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4048 /// reverse of what x86 shuffles want.
4049 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4051 unsigned NumElems = VT.getVectorNumElements();
4052 unsigned NumLanes = VT.getSizeInBits()/128;
4053 unsigned NumLaneElems = NumElems/NumLanes;
4055 if (NumLaneElems != 2 && NumLaneElems != 4)
4058 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4059 bool symetricMaskRequired =
4060 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4062 // VSHUFPSY divides the resulting vector into 4 chunks.
4063 // The sources are also splitted into 4 chunks, and each destination
4064 // chunk must come from a different source chunk.
4066 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4067 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4069 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4070 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4072 // VSHUFPDY divides the resulting vector into 4 chunks.
4073 // The sources are also splitted into 4 chunks, and each destination
4074 // chunk must come from a different source chunk.
4076 // SRC1 => X3 X2 X1 X0
4077 // SRC2 => Y3 Y2 Y1 Y0
4079 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4081 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4082 unsigned HalfLaneElems = NumLaneElems/2;
4083 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4084 for (unsigned i = 0; i != NumLaneElems; ++i) {
4085 int Idx = Mask[i+l];
4086 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4087 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4089 // For VSHUFPSY, the mask of the second half must be the same as the
4090 // first but with the appropriate offsets. This works in the same way as
4091 // VPERMILPS works with masks.
4092 if (!symetricMaskRequired || Idx < 0)
4094 if (MaskVal[i] < 0) {
4095 MaskVal[i] = Idx - l;
4098 if ((signed)(Idx - l) != MaskVal[i])
4106 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4107 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4108 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4109 if (!VT.is128BitVector())
4112 unsigned NumElems = VT.getVectorNumElements();
4117 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4118 return isUndefOrEqual(Mask[0], 6) &&
4119 isUndefOrEqual(Mask[1], 7) &&
4120 isUndefOrEqual(Mask[2], 2) &&
4121 isUndefOrEqual(Mask[3], 3);
4124 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4125 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4127 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4128 if (!VT.is128BitVector())
4131 unsigned NumElems = VT.getVectorNumElements();
4136 return isUndefOrEqual(Mask[0], 2) &&
4137 isUndefOrEqual(Mask[1], 3) &&
4138 isUndefOrEqual(Mask[2], 2) &&
4139 isUndefOrEqual(Mask[3], 3);
4142 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4143 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4144 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4145 if (!VT.is128BitVector())
4148 unsigned NumElems = VT.getVectorNumElements();
4150 if (NumElems != 2 && NumElems != 4)
4153 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i + NumElems))
4157 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4158 if (!isUndefOrEqual(Mask[i], i))
4164 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4165 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4166 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4167 if (!VT.is128BitVector())
4170 unsigned NumElems = VT.getVectorNumElements();
4172 if (NumElems != 2 && NumElems != 4)
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i], i))
4179 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4180 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4186 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4187 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4188 /// i. e: If all but one element come from the same vector.
4189 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4190 // TODO: Deal with AVX's VINSERTPS
4191 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4194 unsigned CorrectPosV1 = 0;
4195 unsigned CorrectPosV2 = 0;
4196 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4197 if (Mask[i] == -1) {
4205 else if (Mask[i] == i + 4)
4209 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4210 // We have 3 elements (undefs count as elements from any vector) from one
4211 // vector, and one from another.
4218 // Some special combinations that can be optimized.
4221 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4222 SelectionDAG &DAG) {
4223 MVT VT = SVOp->getSimpleValueType(0);
4226 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4229 ArrayRef<int> Mask = SVOp->getMask();
4231 // These are the special masks that may be optimized.
4232 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4233 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4234 bool MatchEvenMask = true;
4235 bool MatchOddMask = true;
4236 for (int i=0; i<8; ++i) {
4237 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4238 MatchEvenMask = false;
4239 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4240 MatchOddMask = false;
4243 if (!MatchEvenMask && !MatchOddMask)
4246 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4248 SDValue Op0 = SVOp->getOperand(0);
4249 SDValue Op1 = SVOp->getOperand(1);
4251 if (MatchEvenMask) {
4252 // Shift the second operand right to 32 bits.
4253 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4254 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4256 // Shift the first operand left to 32 bits.
4257 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4258 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4260 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4261 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4264 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4265 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4266 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4267 bool HasInt256, bool V2IsSplat = false) {
4269 assert(VT.getSizeInBits() >= 128 &&
4270 "Unsupported vector type for unpckl");
4272 unsigned NumElts = VT.getVectorNumElements();
4273 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4274 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4277 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4278 "Unsupported vector type for unpckh");
4280 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4281 unsigned NumLanes = VT.getSizeInBits()/128;
4282 unsigned NumLaneElts = NumElts/NumLanes;
4284 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4285 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4286 int BitI = Mask[l+i];
4287 int BitI1 = Mask[l+i+1];
4288 if (!isUndefOrEqual(BitI, j))
4291 if (!isUndefOrEqual(BitI1, NumElts))
4294 if (!isUndefOrEqual(BitI1, j + NumElts))
4303 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4304 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4305 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4306 bool HasInt256, bool V2IsSplat = false) {
4307 assert(VT.getSizeInBits() >= 128 &&
4308 "Unsupported vector type for unpckh");
4310 unsigned NumElts = VT.getVectorNumElements();
4311 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4312 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4315 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4316 "Unsupported vector type for unpckh");
4318 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4319 unsigned NumLanes = VT.getSizeInBits()/128;
4320 unsigned NumLaneElts = NumElts/NumLanes;
4322 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4323 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4324 int BitI = Mask[l+i];
4325 int BitI1 = Mask[l+i+1];
4326 if (!isUndefOrEqual(BitI, j))
4329 if (isUndefOrEqual(BitI1, NumElts))
4332 if (!isUndefOrEqual(BitI1, j+NumElts))
4340 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4341 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4343 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4344 unsigned NumElts = VT.getVectorNumElements();
4345 bool Is256BitVec = VT.is256BitVector();
4347 if (VT.is512BitVector())
4349 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4350 "Unsupported vector type for unpckh");
4352 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4353 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4356 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4357 // FIXME: Need a better way to get rid of this, there's no latency difference
4358 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4359 // the former later. We should also remove the "_undef" special mask.
4360 if (NumElts == 4 && Is256BitVec)
4363 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4364 // independently on 128-bit lanes.
4365 unsigned NumLanes = VT.getSizeInBits()/128;
4366 unsigned NumLaneElts = NumElts/NumLanes;
4368 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4369 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4370 int BitI = Mask[l+i];
4371 int BitI1 = Mask[l+i+1];
4373 if (!isUndefOrEqual(BitI, j))
4375 if (!isUndefOrEqual(BitI1, j))
4383 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4384 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4386 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4387 unsigned NumElts = VT.getVectorNumElements();
4389 if (VT.is512BitVector())
4392 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4393 "Unsupported vector type for unpckh");
4395 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4396 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4399 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4400 // independently on 128-bit lanes.
4401 unsigned NumLanes = VT.getSizeInBits()/128;
4402 unsigned NumLaneElts = NumElts/NumLanes;
4404 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4405 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4406 int BitI = Mask[l+i];
4407 int BitI1 = Mask[l+i+1];
4408 if (!isUndefOrEqual(BitI, j))
4410 if (!isUndefOrEqual(BitI1, j))
4417 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4418 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4419 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4420 if (!VT.is512BitVector())
4423 unsigned NumElts = VT.getVectorNumElements();
4424 unsigned HalfSize = NumElts/2;
4425 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4426 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4431 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4432 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4440 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4441 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4442 /// MOVSD, and MOVD, i.e. setting the lowest element.
4443 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4444 if (VT.getVectorElementType().getSizeInBits() < 32)
4446 if (!VT.is128BitVector())
4449 unsigned NumElts = VT.getVectorNumElements();
4451 if (!isUndefOrEqual(Mask[0], NumElts))
4454 for (unsigned i = 1; i != NumElts; ++i)
4455 if (!isUndefOrEqual(Mask[i], i))
4461 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4462 /// as permutations between 128-bit chunks or halves. As an example: this
4464 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4465 /// The first half comes from the second half of V1 and the second half from the
4466 /// the second half of V2.
4467 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4468 if (!HasFp256 || !VT.is256BitVector())
4471 // The shuffle result is divided into half A and half B. In total the two
4472 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4473 // B must come from C, D, E or F.
4474 unsigned HalfSize = VT.getVectorNumElements()/2;
4475 bool MatchA = false, MatchB = false;
4477 // Check if A comes from one of C, D, E, F.
4478 for (unsigned Half = 0; Half != 4; ++Half) {
4479 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4485 // Check if B comes from one of C, D, E, F.
4486 for (unsigned Half = 0; Half != 4; ++Half) {
4487 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4493 return MatchA && MatchB;
4496 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4497 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4498 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4499 MVT VT = SVOp->getSimpleValueType(0);
4501 unsigned HalfSize = VT.getVectorNumElements()/2;
4503 unsigned FstHalf = 0, SndHalf = 0;
4504 for (unsigned i = 0; i < HalfSize; ++i) {
4505 if (SVOp->getMaskElt(i) > 0) {
4506 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4510 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4511 if (SVOp->getMaskElt(i) > 0) {
4512 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4517 return (FstHalf | (SndHalf << 4));
4520 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4521 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4522 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4526 unsigned NumElts = VT.getVectorNumElements();
4528 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4529 for (unsigned i = 0; i != NumElts; ++i) {
4532 Imm8 |= Mask[i] << (i*2);
4537 unsigned LaneSize = 4;
4538 SmallVector<int, 4> MaskVal(LaneSize, -1);
4540 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4541 for (unsigned i = 0; i != LaneSize; ++i) {
4542 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4546 if (MaskVal[i] < 0) {
4547 MaskVal[i] = Mask[i+l] - l;
4548 Imm8 |= MaskVal[i] << (i*2);
4551 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4558 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4559 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4560 /// Note that VPERMIL mask matching is different depending whether theunderlying
4561 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4562 /// to the same elements of the low, but to the higher half of the source.
4563 /// In VPERMILPD the two lanes could be shuffled independently of each other
4564 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4565 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4566 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4567 if (VT.getSizeInBits() < 256 || EltSize < 32)
4569 bool symetricMaskRequired = (EltSize == 32);
4570 unsigned NumElts = VT.getVectorNumElements();
4572 unsigned NumLanes = VT.getSizeInBits()/128;
4573 unsigned LaneSize = NumElts/NumLanes;
4574 // 2 or 4 elements in one lane
4576 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4577 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4578 for (unsigned i = 0; i != LaneSize; ++i) {
4579 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4581 if (symetricMaskRequired) {
4582 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4583 ExpectedMaskVal[i] = Mask[i+l] - l;
4586 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4594 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4595 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4596 /// element of vector 2 and the other elements to come from vector 1 in order.
4597 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4598 bool V2IsSplat = false, bool V2IsUndef = false) {
4599 if (!VT.is128BitVector())
4602 unsigned NumOps = VT.getVectorNumElements();
4603 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4606 if (!isUndefOrEqual(Mask[0], 0))
4609 for (unsigned i = 1; i != NumOps; ++i)
4610 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4611 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4612 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4618 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4619 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4620 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4621 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4622 const X86Subtarget *Subtarget) {
4623 if (!Subtarget->hasSSE3())
4626 unsigned NumElems = VT.getVectorNumElements();
4628 if ((VT.is128BitVector() && NumElems != 4) ||
4629 (VT.is256BitVector() && NumElems != 8) ||
4630 (VT.is512BitVector() && NumElems != 16))
4633 // "i+1" is the value the indexed mask element must have
4634 for (unsigned i = 0; i != NumElems; i += 2)
4635 if (!isUndefOrEqual(Mask[i], i+1) ||
4636 !isUndefOrEqual(Mask[i+1], i+1))
4642 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4643 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4644 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4645 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4646 const X86Subtarget *Subtarget) {
4647 if (!Subtarget->hasSSE3())
4650 unsigned NumElems = VT.getVectorNumElements();
4652 if ((VT.is128BitVector() && NumElems != 4) ||
4653 (VT.is256BitVector() && NumElems != 8) ||
4654 (VT.is512BitVector() && NumElems != 16))
4657 // "i" is the value the indexed mask element must have
4658 for (unsigned i = 0; i != NumElems; i += 2)
4659 if (!isUndefOrEqual(Mask[i], i) ||
4660 !isUndefOrEqual(Mask[i+1], i))
4666 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4667 /// specifies a shuffle of elements that is suitable for input to 256-bit
4668 /// version of MOVDDUP.
4669 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4670 if (!HasFp256 || !VT.is256BitVector())
4673 unsigned NumElts = VT.getVectorNumElements();
4677 for (unsigned i = 0; i != NumElts/2; ++i)
4678 if (!isUndefOrEqual(Mask[i], 0))
4680 for (unsigned i = NumElts/2; i != NumElts; ++i)
4681 if (!isUndefOrEqual(Mask[i], NumElts/2))
4686 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4687 /// specifies a shuffle of elements that is suitable for input to 128-bit
4688 /// version of MOVDDUP.
4689 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4690 if (!VT.is128BitVector())
4693 unsigned e = VT.getVectorNumElements() / 2;
4694 for (unsigned i = 0; i != e; ++i)
4695 if (!isUndefOrEqual(Mask[i], i))
4697 for (unsigned i = 0; i != e; ++i)
4698 if (!isUndefOrEqual(Mask[e+i], i))
4703 /// isVEXTRACTIndex - Return true if the specified
4704 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4705 /// suitable for instruction that extract 128 or 256 bit vectors
4706 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4707 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4708 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4711 // The index should be aligned on a vecWidth-bit boundary.
4713 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4715 MVT VT = N->getSimpleValueType(0);
4716 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4717 bool Result = (Index * ElSize) % vecWidth == 0;
4722 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4723 /// operand specifies a subvector insert that is suitable for input to
4724 /// insertion of 128 or 256-bit subvectors
4725 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4726 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4727 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4729 // The index should be aligned on a vecWidth-bit boundary.
4731 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4733 MVT VT = N->getSimpleValueType(0);
4734 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4735 bool Result = (Index * ElSize) % vecWidth == 0;
4740 bool X86::isVINSERT128Index(SDNode *N) {
4741 return isVINSERTIndex(N, 128);
4744 bool X86::isVINSERT256Index(SDNode *N) {
4745 return isVINSERTIndex(N, 256);
4748 bool X86::isVEXTRACT128Index(SDNode *N) {
4749 return isVEXTRACTIndex(N, 128);
4752 bool X86::isVEXTRACT256Index(SDNode *N) {
4753 return isVEXTRACTIndex(N, 256);
4756 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4757 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4758 /// Handles 128-bit and 256-bit.
4759 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4760 MVT VT = N->getSimpleValueType(0);
4762 assert((VT.getSizeInBits() >= 128) &&
4763 "Unsupported vector type for PSHUF/SHUFP");
4765 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4766 // independently on 128-bit lanes.
4767 unsigned NumElts = VT.getVectorNumElements();
4768 unsigned NumLanes = VT.getSizeInBits()/128;
4769 unsigned NumLaneElts = NumElts/NumLanes;
4771 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4772 "Only supports 2, 4 or 8 elements per lane");
4774 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4776 for (unsigned i = 0; i != NumElts; ++i) {
4777 int Elt = N->getMaskElt(i);
4778 if (Elt < 0) continue;
4779 Elt &= NumLaneElts - 1;
4780 unsigned ShAmt = (i << Shift) % 8;
4781 Mask |= Elt << ShAmt;
4787 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4788 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4789 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4790 MVT VT = N->getSimpleValueType(0);
4792 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4793 "Unsupported vector type for PSHUFHW");
4795 unsigned NumElts = VT.getVectorNumElements();
4798 for (unsigned l = 0; l != NumElts; l += 8) {
4799 // 8 nodes per lane, but we only care about the last 4.
4800 for (unsigned i = 0; i < 4; ++i) {
4801 int Elt = N->getMaskElt(l+i+4);
4802 if (Elt < 0) continue;
4803 Elt &= 0x3; // only 2-bits.
4804 Mask |= Elt << (i * 2);
4811 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4812 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4813 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4814 MVT VT = N->getSimpleValueType(0);
4816 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4817 "Unsupported vector type for PSHUFHW");
4819 unsigned NumElts = VT.getVectorNumElements();
4822 for (unsigned l = 0; l != NumElts; l += 8) {
4823 // 8 nodes per lane, but we only care about the first 4.
4824 for (unsigned i = 0; i < 4; ++i) {
4825 int Elt = N->getMaskElt(l+i);
4826 if (Elt < 0) continue;
4827 Elt &= 0x3; // only 2-bits
4828 Mask |= Elt << (i * 2);
4835 /// \brief Return the appropriate immediate to shuffle the specified
4836 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4837 /// VALIGN (if Interlane is true) instructions.
4838 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4840 MVT VT = SVOp->getSimpleValueType(0);
4841 unsigned EltSize = InterLane ? 1 :
4842 VT.getVectorElementType().getSizeInBits() >> 3;
4844 unsigned NumElts = VT.getVectorNumElements();
4845 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4846 unsigned NumLaneElts = NumElts/NumLanes;
4850 for (i = 0; i != NumElts; ++i) {
4851 Val = SVOp->getMaskElt(i);
4855 if (Val >= (int)NumElts)
4856 Val -= NumElts - NumLaneElts;
4858 assert(Val - i > 0 && "PALIGNR imm should be positive");
4859 return (Val - i) * EltSize;
4862 /// \brief Return the appropriate immediate to shuffle the specified
4863 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4864 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4865 return getShuffleAlignrImmediate(SVOp, false);
4868 /// \brief Return the appropriate immediate to shuffle the specified
4869 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4870 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4871 return getShuffleAlignrImmediate(SVOp, true);
4875 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4876 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4877 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4878 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4881 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4883 MVT VecVT = N->getOperand(0).getSimpleValueType();
4884 MVT ElVT = VecVT.getVectorElementType();
4886 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4887 return Index / NumElemsPerChunk;
4890 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4891 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4892 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4893 llvm_unreachable("Illegal insert subvector for VINSERT");
4896 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4898 MVT VecVT = N->getSimpleValueType(0);
4899 MVT ElVT = VecVT.getVectorElementType();
4901 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4902 return Index / NumElemsPerChunk;
4905 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4906 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4907 /// and VINSERTI128 instructions.
4908 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4909 return getExtractVEXTRACTImmediate(N, 128);
4912 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4913 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4914 /// and VINSERTI64x4 instructions.
4915 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4916 return getExtractVEXTRACTImmediate(N, 256);
4919 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4920 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4921 /// and VINSERTI128 instructions.
4922 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4923 return getInsertVINSERTImmediate(N, 128);
4926 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4927 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4928 /// and VINSERTI64x4 instructions.
4929 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4930 return getInsertVINSERTImmediate(N, 256);
4933 /// isZero - Returns true if Elt is a constant integer zero
4934 static bool isZero(SDValue V) {
4935 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4936 return C && C->isNullValue();
4939 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4941 bool X86::isZeroNode(SDValue Elt) {
4944 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4945 return CFP->getValueAPF().isPosZero();
4949 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4950 /// match movhlps. The lower half elements should come from upper half of
4951 /// V1 (and in order), and the upper half elements should come from the upper
4952 /// half of V2 (and in order).
4953 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4954 if (!VT.is128BitVector())
4956 if (VT.getVectorNumElements() != 4)
4958 for (unsigned i = 0, e = 2; i != e; ++i)
4959 if (!isUndefOrEqual(Mask[i], i+2))
4961 for (unsigned i = 2; i != 4; ++i)
4962 if (!isUndefOrEqual(Mask[i], i+4))
4967 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4968 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4970 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4971 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4973 N = N->getOperand(0).getNode();
4974 if (!ISD::isNON_EXTLoad(N))
4977 *LD = cast<LoadSDNode>(N);
4981 // Test whether the given value is a vector value which will be legalized
4983 static bool WillBeConstantPoolLoad(SDNode *N) {
4984 if (N->getOpcode() != ISD::BUILD_VECTOR)
4987 // Check for any non-constant elements.
4988 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4989 switch (N->getOperand(i).getNode()->getOpcode()) {
4991 case ISD::ConstantFP:
4998 // Vectors of all-zeros and all-ones are materialized with special
4999 // instructions rather than being loaded.
5000 return !ISD::isBuildVectorAllZeros(N) &&
5001 !ISD::isBuildVectorAllOnes(N);
5004 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5005 /// match movlp{s|d}. The lower half elements should come from lower half of
5006 /// V1 (and in order), and the upper half elements should come from the upper
5007 /// half of V2 (and in order). And since V1 will become the source of the
5008 /// MOVLP, it must be either a vector load or a scalar load to vector.
5009 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5010 ArrayRef<int> Mask, MVT VT) {
5011 if (!VT.is128BitVector())
5014 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5016 // Is V2 is a vector load, don't do this transformation. We will try to use
5017 // load folding shufps op.
5018 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5021 unsigned NumElems = VT.getVectorNumElements();
5023 if (NumElems != 2 && NumElems != 4)
5025 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5026 if (!isUndefOrEqual(Mask[i], i))
5028 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5029 if (!isUndefOrEqual(Mask[i], i+NumElems))
5034 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5035 /// to an zero vector.
5036 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5037 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5038 SDValue V1 = N->getOperand(0);
5039 SDValue V2 = N->getOperand(1);
5040 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5041 for (unsigned i = 0; i != NumElems; ++i) {
5042 int Idx = N->getMaskElt(i);
5043 if (Idx >= (int)NumElems) {
5044 unsigned Opc = V2.getOpcode();
5045 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5047 if (Opc != ISD::BUILD_VECTOR ||
5048 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5050 } else if (Idx >= 0) {
5051 unsigned Opc = V1.getOpcode();
5052 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5054 if (Opc != ISD::BUILD_VECTOR ||
5055 !X86::isZeroNode(V1.getOperand(Idx)))
5062 /// getZeroVector - Returns a vector of specified type with all zero elements.
5064 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5065 SelectionDAG &DAG, SDLoc dl) {
5066 assert(VT.isVector() && "Expected a vector type");
5068 // Always build SSE zero vectors as <4 x i32> bitcasted
5069 // to their dest type. This ensures they get CSE'd.
5071 if (VT.is128BitVector()) { // SSE
5072 if (Subtarget->hasSSE2()) { // SSE2
5073 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5074 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5076 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5079 } else if (VT.is256BitVector()) { // AVX
5080 if (Subtarget->hasInt256()) { // AVX2
5081 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5085 // 256-bit logic and arithmetic instructions in AVX are all
5086 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5087 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5091 } else if (VT.is512BitVector()) { // AVX-512
5092 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5093 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5094 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5095 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5096 } else if (VT.getScalarType() == MVT::i1) {
5097 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5098 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5099 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5100 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5102 llvm_unreachable("Unexpected vector type");
5104 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5107 /// getOnesVector - Returns a vector of specified type with all bits set.
5108 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5109 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5110 /// Then bitcast to their original type, ensuring they get CSE'd.
5111 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5113 assert(VT.isVector() && "Expected a vector type");
5115 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5117 if (VT.is256BitVector()) {
5118 if (HasInt256) { // AVX2
5119 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5125 } else if (VT.is128BitVector()) {
5126 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5128 llvm_unreachable("Unexpected vector type");
5130 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5133 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5134 /// that point to V2 points to its first element.
5135 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5136 for (unsigned i = 0; i != NumElems; ++i) {
5137 if (Mask[i] > (int)NumElems) {
5143 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5144 /// operation of specified width.
5145 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5147 unsigned NumElems = VT.getVectorNumElements();
5148 SmallVector<int, 8> Mask;
5149 Mask.push_back(NumElems);
5150 for (unsigned i = 1; i != NumElems; ++i)
5152 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5155 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5156 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5158 unsigned NumElems = VT.getVectorNumElements();
5159 SmallVector<int, 8> Mask;
5160 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5162 Mask.push_back(i + NumElems);
5164 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5167 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5168 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5170 unsigned NumElems = VT.getVectorNumElements();
5171 SmallVector<int, 8> Mask;
5172 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5173 Mask.push_back(i + Half);
5174 Mask.push_back(i + NumElems + Half);
5176 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5179 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5180 // a generic shuffle instruction because the target has no such instructions.
5181 // Generate shuffles which repeat i16 and i8 several times until they can be
5182 // represented by v4f32 and then be manipulated by target suported shuffles.
5183 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5184 MVT VT = V.getSimpleValueType();
5185 int NumElems = VT.getVectorNumElements();
5188 while (NumElems > 4) {
5189 if (EltNo < NumElems/2) {
5190 V = getUnpackl(DAG, dl, VT, V, V);
5192 V = getUnpackh(DAG, dl, VT, V, V);
5193 EltNo -= NumElems/2;
5200 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5201 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5202 MVT VT = V.getSimpleValueType();
5205 if (VT.is128BitVector()) {
5206 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5207 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5208 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5210 } else if (VT.is256BitVector()) {
5211 // To use VPERMILPS to splat scalars, the second half of indicies must
5212 // refer to the higher part, which is a duplication of the lower one,
5213 // because VPERMILPS can only handle in-lane permutations.
5214 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5215 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5217 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5218 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5221 llvm_unreachable("Vector size not supported");
5223 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5226 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5227 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5228 MVT SrcVT = SV->getSimpleValueType(0);
5229 SDValue V1 = SV->getOperand(0);
5232 int EltNo = SV->getSplatIndex();
5233 int NumElems = SrcVT.getVectorNumElements();
5234 bool Is256BitVec = SrcVT.is256BitVector();
5236 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5237 "Unknown how to promote splat for type");
5239 // Extract the 128-bit part containing the splat element and update
5240 // the splat element index when it refers to the higher register.
5242 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5243 if (EltNo >= NumElems/2)
5244 EltNo -= NumElems/2;
5247 // All i16 and i8 vector types can't be used directly by a generic shuffle
5248 // instruction because the target has no such instruction. Generate shuffles
5249 // which repeat i16 and i8 several times until they fit in i32, and then can
5250 // be manipulated by target suported shuffles.
5251 MVT EltVT = SrcVT.getVectorElementType();
5252 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5253 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5255 // Recreate the 256-bit vector and place the same 128-bit vector
5256 // into the low and high part. This is necessary because we want
5257 // to use VPERM* to shuffle the vectors
5259 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5262 return getLegalSplat(DAG, V1, EltNo);
5265 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5266 /// vector of zero or undef vector. This produces a shuffle where the low
5267 /// element of V2 is swizzled into the zero/undef vector, landing at element
5268 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5269 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5271 const X86Subtarget *Subtarget,
5272 SelectionDAG &DAG) {
5273 MVT VT = V2.getSimpleValueType();
5275 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5276 unsigned NumElems = VT.getVectorNumElements();
5277 SmallVector<int, 16> MaskVec;
5278 for (unsigned i = 0; i != NumElems; ++i)
5279 // If this is the insertion idx, put the low elt of V2 here.
5280 MaskVec.push_back(i == Idx ? NumElems : i);
5281 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5284 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5285 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5286 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5287 /// shuffles which use a single input multiple times, and in those cases it will
5288 /// adjust the mask to only have indices within that single input.
5289 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5290 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5291 unsigned NumElems = VT.getVectorNumElements();
5295 bool IsFakeUnary = false;
5296 switch(N->getOpcode()) {
5297 case X86ISD::BLENDI:
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5302 ImmN = N->getOperand(N->getNumOperands()-1);
5303 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5306 case X86ISD::UNPCKH:
5307 DecodeUNPCKHMask(VT, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5310 case X86ISD::UNPCKL:
5311 DecodeUNPCKLMask(VT, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5314 case X86ISD::MOVHLPS:
5315 DecodeMOVHLPSMask(NumElems, Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5318 case X86ISD::MOVLHPS:
5319 DecodeMOVLHPSMask(NumElems, Mask);
5320 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5322 case X86ISD::PALIGNR:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5326 case X86ISD::PSHUFD:
5327 case X86ISD::VPERMILPI:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFHW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFLW:
5338 ImmN = N->getOperand(N->getNumOperands()-1);
5339 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5342 case X86ISD::PSHUFB: {
5344 SDValue MaskNode = N->getOperand(1);
5345 while (MaskNode->getOpcode() == ISD::BITCAST)
5346 MaskNode = MaskNode->getOperand(0);
5348 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5349 // If we have a build-vector, then things are easy.
5350 EVT VT = MaskNode.getValueType();
5351 assert(VT.isVector() &&
5352 "Can't produce a non-vector with a build_vector!");
5353 if (!VT.isInteger())
5356 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5358 SmallVector<uint64_t, 32> RawMask;
5359 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5360 SDValue Op = MaskNode->getOperand(i);
5361 if (Op->getOpcode() == ISD::UNDEF) {
5362 RawMask.push_back((uint64_t)SM_SentinelUndef);
5365 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5368 APInt MaskElement = CN->getAPIntValue();
5370 // We now have to decode the element which could be any integer size and
5371 // extract each byte of it.
5372 for (int j = 0; j < NumBytesPerElement; ++j) {
5373 // Note that this is x86 and so always little endian: the low byte is
5374 // the first byte of the mask.
5375 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5376 MaskElement = MaskElement.lshr(8);
5379 DecodePSHUFBMask(RawMask, Mask);
5383 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5387 SDValue Ptr = MaskLoad->getBasePtr();
5388 if (Ptr->getOpcode() == X86ISD::Wrapper)
5389 Ptr = Ptr->getOperand(0);
5391 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5392 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5395 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5396 // FIXME: Support AVX-512 here.
5397 Type *Ty = C->getType();
5398 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5399 Ty->getVectorNumElements() != 32))
5402 DecodePSHUFBMask(C, Mask);
5408 case X86ISD::VPERMI:
5409 ImmN = N->getOperand(N->getNumOperands()-1);
5410 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5414 case X86ISD::MOVSD: {
5415 // The index 0 always comes from the first element of the second source,
5416 // this is why MOVSS and MOVSD are used in the first place. The other
5417 // elements come from the other positions of the first source vector
5418 Mask.push_back(NumElems);
5419 for (unsigned i = 1; i != NumElems; ++i) {
5424 case X86ISD::VPERM2X128:
5425 ImmN = N->getOperand(N->getNumOperands()-1);
5426 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5427 if (Mask.empty()) return false;
5429 case X86ISD::MOVSLDUP:
5430 DecodeMOVSLDUPMask(VT, Mask);
5432 case X86ISD::MOVSHDUP:
5433 DecodeMOVSHDUPMask(VT, Mask);
5435 case X86ISD::MOVDDUP:
5436 case X86ISD::MOVLHPD:
5437 case X86ISD::MOVLPD:
5438 case X86ISD::MOVLPS:
5439 // Not yet implemented
5441 default: llvm_unreachable("unknown target shuffle node");
5444 // If we have a fake unary shuffle, the shuffle mask is spread across two
5445 // inputs that are actually the same node. Re-map the mask to always point
5446 // into the first input.
5449 if (M >= (int)Mask.size())
5455 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5456 /// element of the result of the vector shuffle.
5457 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5460 return SDValue(); // Limit search depth.
5462 SDValue V = SDValue(N, 0);
5463 EVT VT = V.getValueType();
5464 unsigned Opcode = V.getOpcode();
5466 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5467 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5468 int Elt = SV->getMaskElt(Index);
5471 return DAG.getUNDEF(VT.getVectorElementType());
5473 unsigned NumElems = VT.getVectorNumElements();
5474 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5475 : SV->getOperand(1);
5476 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5479 // Recurse into target specific vector shuffles to find scalars.
5480 if (isTargetShuffle(Opcode)) {
5481 MVT ShufVT = V.getSimpleValueType();
5482 unsigned NumElems = ShufVT.getVectorNumElements();
5483 SmallVector<int, 16> ShuffleMask;
5486 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5489 int Elt = ShuffleMask[Index];
5491 return DAG.getUNDEF(ShufVT.getVectorElementType());
5493 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5495 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5499 // Actual nodes that may contain scalar elements
5500 if (Opcode == ISD::BITCAST) {
5501 V = V.getOperand(0);
5502 EVT SrcVT = V.getValueType();
5503 unsigned NumElems = VT.getVectorNumElements();
5505 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5509 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5510 return (Index == 0) ? V.getOperand(0)
5511 : DAG.getUNDEF(VT.getVectorElementType());
5513 if (V.getOpcode() == ISD::BUILD_VECTOR)
5514 return V.getOperand(Index);
5519 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5520 /// shuffle operation which come from a consecutively from a zero. The
5521 /// search can start in two different directions, from left or right.
5522 /// We count undefs as zeros until PreferredNum is reached.
5523 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5524 unsigned NumElems, bool ZerosFromLeft,
5526 unsigned PreferredNum = -1U) {
5527 unsigned NumZeros = 0;
5528 for (unsigned i = 0; i != NumElems; ++i) {
5529 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5530 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5534 if (X86::isZeroNode(Elt))
5536 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5537 NumZeros = std::min(NumZeros + 1, PreferredNum);
5545 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5546 /// correspond consecutively to elements from one of the vector operands,
5547 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5549 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5550 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5551 unsigned NumElems, unsigned &OpNum) {
5552 bool SeenV1 = false;
5553 bool SeenV2 = false;
5555 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5556 int Idx = SVOp->getMaskElt(i);
5557 // Ignore undef indicies
5561 if (Idx < (int)NumElems)
5566 // Only accept consecutive elements from the same vector
5567 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5571 OpNum = SeenV1 ? 0 : 1;
5575 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5576 /// logical left shift of a vector.
5577 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5578 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5580 SVOp->getSimpleValueType(0).getVectorNumElements();
5581 unsigned NumZeros = getNumOfConsecutiveZeros(
5582 SVOp, NumElems, false /* check zeros from right */, DAG,
5583 SVOp->getMaskElt(0));
5589 // Considering the elements in the mask that are not consecutive zeros,
5590 // check if they consecutively come from only one of the source vectors.
5592 // V1 = {X, A, B, C} 0
5594 // vector_shuffle V1, V2 <1, 2, 3, X>
5596 if (!isShuffleMaskConsecutive(SVOp,
5597 0, // Mask Start Index
5598 NumElems-NumZeros, // Mask End Index(exclusive)
5599 NumZeros, // Where to start looking in the src vector
5600 NumElems, // Number of elements in vector
5601 OpSrc)) // Which source operand ?
5606 ShVal = SVOp->getOperand(OpSrc);
5610 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5611 /// logical left shift of a vector.
5612 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5613 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5615 SVOp->getSimpleValueType(0).getVectorNumElements();
5616 unsigned NumZeros = getNumOfConsecutiveZeros(
5617 SVOp, NumElems, true /* check zeros from left */, DAG,
5618 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5624 // Considering the elements in the mask that are not consecutive zeros,
5625 // check if they consecutively come from only one of the source vectors.
5627 // 0 { A, B, X, X } = V2
5629 // vector_shuffle V1, V2 <X, X, 4, 5>
5631 if (!isShuffleMaskConsecutive(SVOp,
5632 NumZeros, // Mask Start Index
5633 NumElems, // Mask End Index(exclusive)
5634 0, // Where to start looking in the src vector
5635 NumElems, // Number of elements in vector
5636 OpSrc)) // Which source operand ?
5641 ShVal = SVOp->getOperand(OpSrc);
5645 /// isVectorShift - Returns true if the shuffle can be implemented as a
5646 /// logical left or right shift of a vector.
5647 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5648 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5649 // Although the logic below support any bitwidth size, there are no
5650 // shift instructions which handle more than 128-bit vectors.
5651 if (!SVOp->getSimpleValueType(0).is128BitVector())
5654 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5655 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5661 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5663 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5664 unsigned NumNonZero, unsigned NumZero,
5666 const X86Subtarget* Subtarget,
5667 const TargetLowering &TLI) {
5674 for (unsigned i = 0; i < 16; ++i) {
5675 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5676 if (ThisIsNonZero && First) {
5678 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5680 V = DAG.getUNDEF(MVT::v8i16);
5685 SDValue ThisElt, LastElt;
5686 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5687 if (LastIsNonZero) {
5688 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5689 MVT::i16, Op.getOperand(i-1));
5691 if (ThisIsNonZero) {
5692 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5693 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5694 ThisElt, DAG.getConstant(8, MVT::i8));
5696 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5700 if (ThisElt.getNode())
5701 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5702 DAG.getIntPtrConstant(i/2));
5706 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5709 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5711 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5712 unsigned NumNonZero, unsigned NumZero,
5714 const X86Subtarget* Subtarget,
5715 const TargetLowering &TLI) {
5722 for (unsigned i = 0; i < 8; ++i) {
5723 bool isNonZero = (NonZeros & (1 << i)) != 0;
5727 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5729 V = DAG.getUNDEF(MVT::v8i16);
5732 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5733 MVT::v8i16, V, Op.getOperand(i),
5734 DAG.getIntPtrConstant(i));
5741 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5742 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5743 unsigned NonZeros, unsigned NumNonZero,
5744 unsigned NumZero, SelectionDAG &DAG,
5745 const X86Subtarget *Subtarget,
5746 const TargetLowering &TLI) {
5747 // We know there's at least one non-zero element
5748 unsigned FirstNonZeroIdx = 0;
5749 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5750 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5751 X86::isZeroNode(FirstNonZero)) {
5753 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5756 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5757 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5760 SDValue V = FirstNonZero.getOperand(0);
5761 MVT VVT = V.getSimpleValueType();
5762 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5765 unsigned FirstNonZeroDst =
5766 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5767 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5768 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5769 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5771 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5772 SDValue Elem = Op.getOperand(Idx);
5773 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5776 // TODO: What else can be here? Deal with it.
5777 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5780 // TODO: Some optimizations are still possible here
5781 // ex: Getting one element from a vector, and the rest from another.
5782 if (Elem.getOperand(0) != V)
5785 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5788 else if (IncorrectIdx == -1U) {
5792 // There was already one element with an incorrect index.
5793 // We can't optimize this case to an insertps.
5797 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5799 EVT VT = Op.getSimpleValueType();
5800 unsigned ElementMoveMask = 0;
5801 if (IncorrectIdx == -1U)
5802 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5804 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5806 SDValue InsertpsMask =
5807 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5808 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5814 /// getVShift - Return a vector logical shift node.
5816 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5817 unsigned NumBits, SelectionDAG &DAG,
5818 const TargetLowering &TLI, SDLoc dl) {
5819 assert(VT.is128BitVector() && "Unknown type for VShift");
5820 EVT ShVT = MVT::v2i64;
5821 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5822 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5823 return DAG.getNode(ISD::BITCAST, dl, VT,
5824 DAG.getNode(Opc, dl, ShVT, SrcOp,
5825 DAG.getConstant(NumBits,
5826 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5830 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5832 // Check if the scalar load can be widened into a vector load. And if
5833 // the address is "base + cst" see if the cst can be "absorbed" into
5834 // the shuffle mask.
5835 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5836 SDValue Ptr = LD->getBasePtr();
5837 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5839 EVT PVT = LD->getValueType(0);
5840 if (PVT != MVT::i32 && PVT != MVT::f32)
5845 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5846 FI = FINode->getIndex();
5848 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5849 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5850 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5851 Offset = Ptr.getConstantOperandVal(1);
5852 Ptr = Ptr.getOperand(0);
5857 // FIXME: 256-bit vector instructions don't require a strict alignment,
5858 // improve this code to support it better.
5859 unsigned RequiredAlign = VT.getSizeInBits()/8;
5860 SDValue Chain = LD->getChain();
5861 // Make sure the stack object alignment is at least 16 or 32.
5862 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5863 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5864 if (MFI->isFixedObjectIndex(FI)) {
5865 // Can't change the alignment. FIXME: It's possible to compute
5866 // the exact stack offset and reference FI + adjust offset instead.
5867 // If someone *really* cares about this. That's the way to implement it.
5870 MFI->setObjectAlignment(FI, RequiredAlign);
5874 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5875 // Ptr + (Offset & ~15).
5878 if ((Offset % RequiredAlign) & 3)
5880 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5882 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5883 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5885 int EltNo = (Offset - StartOffset) >> 2;
5886 unsigned NumElems = VT.getVectorNumElements();
5888 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5889 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5890 LD->getPointerInfo().getWithOffset(StartOffset),
5891 false, false, false, 0);
5893 SmallVector<int, 8> Mask;
5894 for (unsigned i = 0; i != NumElems; ++i)
5895 Mask.push_back(EltNo);
5897 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5903 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5904 /// vector of type 'VT', see if the elements can be replaced by a single large
5905 /// load which has the same value as a build_vector whose operands are 'elts'.
5907 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5909 /// FIXME: we'd also like to handle the case where the last elements are zero
5910 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5911 /// There's even a handy isZeroNode for that purpose.
5912 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5913 SDLoc &DL, SelectionDAG &DAG,
5914 bool isAfterLegalize) {
5915 EVT EltVT = VT.getVectorElementType();
5916 unsigned NumElems = Elts.size();
5918 LoadSDNode *LDBase = nullptr;
5919 unsigned LastLoadedElt = -1U;
5921 // For each element in the initializer, see if we've found a load or an undef.
5922 // If we don't find an initial load element, or later load elements are
5923 // non-consecutive, bail out.
5924 for (unsigned i = 0; i < NumElems; ++i) {
5925 SDValue Elt = Elts[i];
5927 if (!Elt.getNode() ||
5928 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5931 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5933 LDBase = cast<LoadSDNode>(Elt.getNode());
5937 if (Elt.getOpcode() == ISD::UNDEF)
5940 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5941 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5946 // If we have found an entire vector of loads and undefs, then return a large
5947 // load of the entire vector width starting at the base pointer. If we found
5948 // consecutive loads for the low half, generate a vzext_load node.
5949 if (LastLoadedElt == NumElems - 1) {
5951 if (isAfterLegalize &&
5952 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5955 SDValue NewLd = SDValue();
5957 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), 0);
5962 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5963 LDBase->getPointerInfo(),
5964 LDBase->isVolatile(), LDBase->isNonTemporal(),
5965 LDBase->isInvariant(), LDBase->getAlignment());
5967 if (LDBase->hasAnyUseOfValue(1)) {
5968 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5970 SDValue(NewLd.getNode(), 1));
5971 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5972 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5973 SDValue(NewLd.getNode(), 1));
5978 if (NumElems == 4 && LastLoadedElt == 1 &&
5979 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5980 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5981 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5983 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5984 LDBase->getPointerInfo(),
5985 LDBase->getAlignment(),
5986 false/*isVolatile*/, true/*ReadMem*/,
5989 // Make sure the newly-created LOAD is in the same position as LDBase in
5990 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5991 // update uses of LDBase's output chain to use the TokenFactor.
5992 if (LDBase->hasAnyUseOfValue(1)) {
5993 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5994 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5995 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5996 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5997 SDValue(ResNode.getNode(), 1));
6000 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6005 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6006 /// to generate a splat value for the following cases:
6007 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6008 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6009 /// a scalar load, or a constant.
6010 /// The VBROADCAST node is returned when a pattern is found,
6011 /// or SDValue() otherwise.
6012 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6013 SelectionDAG &DAG) {
6014 // VBROADCAST requires AVX.
6015 // TODO: Splats could be generated for non-AVX CPUs using SSE
6016 // instructions, but there's less potential gain for only 128-bit vectors.
6017 if (!Subtarget->hasAVX())
6020 MVT VT = Op.getSimpleValueType();
6023 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6024 "Unsupported vector type for broadcast.");
6029 switch (Op.getOpcode()) {
6031 // Unknown pattern found.
6034 case ISD::BUILD_VECTOR: {
6035 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6036 BitVector UndefElements;
6037 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6039 // We need a splat of a single value to use broadcast, and it doesn't
6040 // make any sense if the value is only in one element of the vector.
6041 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6045 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6046 Ld.getOpcode() == ISD::ConstantFP);
6048 // Make sure that all of the users of a non-constant load are from the
6049 // BUILD_VECTOR node.
6050 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6055 case ISD::VECTOR_SHUFFLE: {
6056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6058 // Shuffles must have a splat mask where the first element is
6060 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6063 SDValue Sc = Op.getOperand(0);
6064 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6065 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6067 if (!Subtarget->hasInt256())
6070 // Use the register form of the broadcast instruction available on AVX2.
6071 if (VT.getSizeInBits() >= 256)
6072 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6073 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6076 Ld = Sc.getOperand(0);
6077 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6078 Ld.getOpcode() == ISD::ConstantFP);
6080 // The scalar_to_vector node and the suspected
6081 // load node must have exactly one user.
6082 // Constants may have multiple users.
6084 // AVX-512 has register version of the broadcast
6085 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6086 Ld.getValueType().getSizeInBits() >= 32;
6087 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6094 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6095 bool IsGE256 = (VT.getSizeInBits() >= 256);
6097 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6098 // instruction to save 8 or more bytes of constant pool data.
6099 // TODO: If multiple splats are generated to load the same constant,
6100 // it may be detrimental to overall size. There needs to be a way to detect
6101 // that condition to know if this is truly a size win.
6102 const Function *F = DAG.getMachineFunction().getFunction();
6103 bool OptForSize = F->getAttributes().
6104 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6106 // Handle broadcasting a single constant scalar from the constant pool
6108 // On Sandybridge (no AVX2), it is still better to load a constant vector
6109 // from the constant pool and not to broadcast it from a scalar.
6110 // But override that restriction when optimizing for size.
6111 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6112 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6113 EVT CVT = Ld.getValueType();
6114 assert(!CVT.isVector() && "Must not broadcast a vector type");
6116 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6117 // For size optimization, also splat v2f64 and v2i64, and for size opt
6118 // with AVX2, also splat i8 and i16.
6119 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6120 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6121 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6122 const Constant *C = nullptr;
6123 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6124 C = CI->getConstantIntValue();
6125 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6126 C = CF->getConstantFPValue();
6128 assert(C && "Invalid constant type");
6130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6131 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6132 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6133 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6134 MachinePointerInfo::getConstantPool(),
6135 false, false, false, Alignment);
6137 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6141 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6143 // Handle AVX2 in-register broadcasts.
6144 if (!IsLoad && Subtarget->hasInt256() &&
6145 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6146 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6148 // The scalar source must be a normal load.
6152 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6153 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6155 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6156 // double since there is no vbroadcastsd xmm
6157 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6158 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6159 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6162 // Unsupported broadcast.
6166 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6167 /// underlying vector and index.
6169 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6171 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6173 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6174 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6177 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6179 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6181 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6182 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6185 // In this case the vector is the extract_subvector expression and the index
6186 // is 2, as specified by the shuffle.
6187 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6188 SDValue ShuffleVec = SVOp->getOperand(0);
6189 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6190 assert(ShuffleVecVT.getVectorElementType() ==
6191 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6193 int ShuffleIdx = SVOp->getMaskElt(Idx);
6194 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6195 ExtractedFromVec = ShuffleVec;
6201 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6202 MVT VT = Op.getSimpleValueType();
6204 // Skip if insert_vec_elt is not supported.
6205 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6206 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6210 unsigned NumElems = Op.getNumOperands();
6214 SmallVector<unsigned, 4> InsertIndices;
6215 SmallVector<int, 8> Mask(NumElems, -1);
6217 for (unsigned i = 0; i != NumElems; ++i) {
6218 unsigned Opc = Op.getOperand(i).getOpcode();
6220 if (Opc == ISD::UNDEF)
6223 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6224 // Quit if more than 1 elements need inserting.
6225 if (InsertIndices.size() > 1)
6228 InsertIndices.push_back(i);
6232 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6233 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6234 // Quit if non-constant index.
6235 if (!isa<ConstantSDNode>(ExtIdx))
6237 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6239 // Quit if extracted from vector of different type.
6240 if (ExtractedFromVec.getValueType() != VT)
6243 if (!VecIn1.getNode())
6244 VecIn1 = ExtractedFromVec;
6245 else if (VecIn1 != ExtractedFromVec) {
6246 if (!VecIn2.getNode())
6247 VecIn2 = ExtractedFromVec;
6248 else if (VecIn2 != ExtractedFromVec)
6249 // Quit if more than 2 vectors to shuffle
6253 if (ExtractedFromVec == VecIn1)
6255 else if (ExtractedFromVec == VecIn2)
6256 Mask[i] = Idx + NumElems;
6259 if (!VecIn1.getNode())
6262 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6263 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6264 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6265 unsigned Idx = InsertIndices[i];
6266 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6267 DAG.getIntPtrConstant(Idx));
6273 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6275 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6277 MVT VT = Op.getSimpleValueType();
6278 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6279 "Unexpected type in LowerBUILD_VECTORvXi1!");
6282 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6283 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6284 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6285 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6288 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6289 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6290 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6291 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6294 bool AllContants = true;
6295 uint64_t Immediate = 0;
6296 int NonConstIdx = -1;
6297 bool IsSplat = true;
6298 unsigned NumNonConsts = 0;
6299 unsigned NumConsts = 0;
6300 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6301 SDValue In = Op.getOperand(idx);
6302 if (In.getOpcode() == ISD::UNDEF)
6304 if (!isa<ConstantSDNode>(In)) {
6305 AllContants = false;
6311 if (cast<ConstantSDNode>(In)->getZExtValue())
6312 Immediate |= (1ULL << idx);
6314 if (In != Op.getOperand(0))
6319 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6320 DAG.getConstant(Immediate, MVT::i16));
6321 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6322 DAG.getIntPtrConstant(0));
6325 if (NumNonConsts == 1 && NonConstIdx != 0) {
6328 SDValue VecAsImm = DAG.getConstant(Immediate,
6329 MVT::getIntegerVT(VT.getSizeInBits()));
6330 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6333 DstVec = DAG.getUNDEF(VT);
6334 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6335 Op.getOperand(NonConstIdx),
6336 DAG.getIntPtrConstant(NonConstIdx));
6338 if (!IsSplat && (NonConstIdx != 0))
6339 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6340 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6343 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6344 DAG.getConstant(-1, SelectVT),
6345 DAG.getConstant(0, SelectVT));
6347 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6348 DAG.getConstant((Immediate | 1), SelectVT),
6349 DAG.getConstant(Immediate, SelectVT));
6350 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6353 /// \brief Return true if \p N implements a horizontal binop and return the
6354 /// operands for the horizontal binop into V0 and V1.
6356 /// This is a helper function of PerformBUILD_VECTORCombine.
6357 /// This function checks that the build_vector \p N in input implements a
6358 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6359 /// operation to match.
6360 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6361 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6362 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6365 /// This function only analyzes elements of \p N whose indices are
6366 /// in range [BaseIdx, LastIdx).
6367 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6369 unsigned BaseIdx, unsigned LastIdx,
6370 SDValue &V0, SDValue &V1) {
6371 EVT VT = N->getValueType(0);
6373 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6374 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6375 "Invalid Vector in input!");
6377 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6378 bool CanFold = true;
6379 unsigned ExpectedVExtractIdx = BaseIdx;
6380 unsigned NumElts = LastIdx - BaseIdx;
6381 V0 = DAG.getUNDEF(VT);
6382 V1 = DAG.getUNDEF(VT);
6384 // Check if N implements a horizontal binop.
6385 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6386 SDValue Op = N->getOperand(i + BaseIdx);
6389 if (Op->getOpcode() == ISD::UNDEF) {
6390 // Update the expected vector extract index.
6391 if (i * 2 == NumElts)
6392 ExpectedVExtractIdx = BaseIdx;
6393 ExpectedVExtractIdx += 2;
6397 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6402 SDValue Op0 = Op.getOperand(0);
6403 SDValue Op1 = Op.getOperand(1);
6405 // Try to match the following pattern:
6406 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6407 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6408 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6409 Op0.getOperand(0) == Op1.getOperand(0) &&
6410 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6411 isa<ConstantSDNode>(Op1.getOperand(1)));
6415 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6416 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6418 if (i * 2 < NumElts) {
6419 if (V0.getOpcode() == ISD::UNDEF)
6420 V0 = Op0.getOperand(0);
6422 if (V1.getOpcode() == ISD::UNDEF)
6423 V1 = Op0.getOperand(0);
6424 if (i * 2 == NumElts)
6425 ExpectedVExtractIdx = BaseIdx;
6428 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6429 if (I0 == ExpectedVExtractIdx)
6430 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6431 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6432 // Try to match the following dag sequence:
6433 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6434 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6438 ExpectedVExtractIdx += 2;
6444 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6445 /// a concat_vector.
6447 /// This is a helper function of PerformBUILD_VECTORCombine.
6448 /// This function expects two 256-bit vectors called V0 and V1.
6449 /// At first, each vector is split into two separate 128-bit vectors.
6450 /// Then, the resulting 128-bit vectors are used to implement two
6451 /// horizontal binary operations.
6453 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6455 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6456 /// the two new horizontal binop.
6457 /// When Mode is set, the first horizontal binop dag node would take as input
6458 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6459 /// horizontal binop dag node would take as input the lower 128-bit of V1
6460 /// and the upper 128-bit of V1.
6462 /// HADD V0_LO, V0_HI
6463 /// HADD V1_LO, V1_HI
6465 /// Otherwise, the first horizontal binop dag node takes as input the lower
6466 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6467 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6469 /// HADD V0_LO, V1_LO
6470 /// HADD V0_HI, V1_HI
6472 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6473 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6474 /// the upper 128-bits of the result.
6475 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6476 SDLoc DL, SelectionDAG &DAG,
6477 unsigned X86Opcode, bool Mode,
6478 bool isUndefLO, bool isUndefHI) {
6479 EVT VT = V0.getValueType();
6480 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6481 "Invalid nodes in input!");
6483 unsigned NumElts = VT.getVectorNumElements();
6484 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6485 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6486 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6487 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6488 EVT NewVT = V0_LO.getValueType();
6490 SDValue LO = DAG.getUNDEF(NewVT);
6491 SDValue HI = DAG.getUNDEF(NewVT);
6494 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6495 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6496 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6497 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6498 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6500 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6501 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6502 V1_LO->getOpcode() != ISD::UNDEF))
6503 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6505 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6506 V1_HI->getOpcode() != ISD::UNDEF))
6507 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6510 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6513 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6514 /// sequence of 'vadd + vsub + blendi'.
6515 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6516 const X86Subtarget *Subtarget) {
6518 EVT VT = BV->getValueType(0);
6519 unsigned NumElts = VT.getVectorNumElements();
6520 SDValue InVec0 = DAG.getUNDEF(VT);
6521 SDValue InVec1 = DAG.getUNDEF(VT);
6523 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6524 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6526 // Odd-numbered elements in the input build vector are obtained from
6527 // adding two integer/float elements.
6528 // Even-numbered elements in the input build vector are obtained from
6529 // subtracting two integer/float elements.
6530 unsigned ExpectedOpcode = ISD::FSUB;
6531 unsigned NextExpectedOpcode = ISD::FADD;
6532 bool AddFound = false;
6533 bool SubFound = false;
6535 for (unsigned i = 0, e = NumElts; i != e; i++) {
6536 SDValue Op = BV->getOperand(i);
6538 // Skip 'undef' values.
6539 unsigned Opcode = Op.getOpcode();
6540 if (Opcode == ISD::UNDEF) {
6541 std::swap(ExpectedOpcode, NextExpectedOpcode);
6545 // Early exit if we found an unexpected opcode.
6546 if (Opcode != ExpectedOpcode)
6549 SDValue Op0 = Op.getOperand(0);
6550 SDValue Op1 = Op.getOperand(1);
6552 // Try to match the following pattern:
6553 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6554 // Early exit if we cannot match that sequence.
6555 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6556 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6557 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6558 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6559 Op0.getOperand(1) != Op1.getOperand(1))
6562 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6566 // We found a valid add/sub node. Update the information accordingly.
6572 // Update InVec0 and InVec1.
6573 if (InVec0.getOpcode() == ISD::UNDEF)
6574 InVec0 = Op0.getOperand(0);
6575 if (InVec1.getOpcode() == ISD::UNDEF)
6576 InVec1 = Op1.getOperand(0);
6578 // Make sure that operands in input to each add/sub node always
6579 // come from a same pair of vectors.
6580 if (InVec0 != Op0.getOperand(0)) {
6581 if (ExpectedOpcode == ISD::FSUB)
6584 // FADD is commutable. Try to commute the operands
6585 // and then test again.
6586 std::swap(Op0, Op1);
6587 if (InVec0 != Op0.getOperand(0))
6591 if (InVec1 != Op1.getOperand(0))
6594 // Update the pair of expected opcodes.
6595 std::swap(ExpectedOpcode, NextExpectedOpcode);
6598 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6599 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6600 InVec1.getOpcode() != ISD::UNDEF)
6601 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6606 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6607 const X86Subtarget *Subtarget) {
6609 EVT VT = N->getValueType(0);
6610 unsigned NumElts = VT.getVectorNumElements();
6611 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6612 SDValue InVec0, InVec1;
6614 // Try to match an ADDSUB.
6615 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6616 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6617 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6618 if (Value.getNode())
6622 // Try to match horizontal ADD/SUB.
6623 unsigned NumUndefsLO = 0;
6624 unsigned NumUndefsHI = 0;
6625 unsigned Half = NumElts/2;
6627 // Count the number of UNDEF operands in the build_vector in input.
6628 for (unsigned i = 0, e = Half; i != e; ++i)
6629 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6632 for (unsigned i = Half, e = NumElts; i != e; ++i)
6633 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6636 // Early exit if this is either a build_vector of all UNDEFs or all the
6637 // operands but one are UNDEF.
6638 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6641 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6642 // Try to match an SSE3 float HADD/HSUB.
6643 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6644 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6646 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6647 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6648 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6649 // Try to match an SSSE3 integer HADD/HSUB.
6650 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6651 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6653 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6654 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6657 if (!Subtarget->hasAVX())
6660 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6661 // Try to match an AVX horizontal add/sub of packed single/double
6662 // precision floating point values from 256-bit vectors.
6663 SDValue InVec2, InVec3;
6664 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6665 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6666 ((InVec0.getOpcode() == ISD::UNDEF ||
6667 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6668 ((InVec1.getOpcode() == ISD::UNDEF ||
6669 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6670 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6672 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6673 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6674 ((InVec0.getOpcode() == ISD::UNDEF ||
6675 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6676 ((InVec1.getOpcode() == ISD::UNDEF ||
6677 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6678 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6679 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6680 // Try to match an AVX2 horizontal add/sub of signed integers.
6681 SDValue InVec2, InVec3;
6683 bool CanFold = true;
6685 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6686 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6687 ((InVec0.getOpcode() == ISD::UNDEF ||
6688 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6689 ((InVec1.getOpcode() == ISD::UNDEF ||
6690 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6691 X86Opcode = X86ISD::HADD;
6692 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6693 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6694 ((InVec0.getOpcode() == ISD::UNDEF ||
6695 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6696 ((InVec1.getOpcode() == ISD::UNDEF ||
6697 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6698 X86Opcode = X86ISD::HSUB;
6703 // Fold this build_vector into a single horizontal add/sub.
6704 // Do this only if the target has AVX2.
6705 if (Subtarget->hasAVX2())
6706 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6708 // Do not try to expand this build_vector into a pair of horizontal
6709 // add/sub if we can emit a pair of scalar add/sub.
6710 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6713 // Convert this build_vector into a pair of horizontal binop followed by
6715 bool isUndefLO = NumUndefsLO == Half;
6716 bool isUndefHI = NumUndefsHI == Half;
6717 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6718 isUndefLO, isUndefHI);
6722 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6723 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6725 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::HADD;
6727 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::HSUB;
6729 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6730 X86Opcode = X86ISD::FHADD;
6731 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6732 X86Opcode = X86ISD::FHSUB;
6736 // Don't try to expand this build_vector into a pair of horizontal add/sub
6737 // if we can simply emit a pair of scalar add/sub.
6738 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6741 // Convert this build_vector into two horizontal add/sub followed by
6743 bool isUndefLO = NumUndefsLO == Half;
6744 bool isUndefHI = NumUndefsHI == Half;
6745 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6746 isUndefLO, isUndefHI);
6753 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6756 MVT VT = Op.getSimpleValueType();
6757 MVT ExtVT = VT.getVectorElementType();
6758 unsigned NumElems = Op.getNumOperands();
6760 // Generate vectors for predicate vectors.
6761 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6762 return LowerBUILD_VECTORvXi1(Op, DAG);
6764 // Vectors containing all zeros can be matched by pxor and xorps later
6765 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6766 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6767 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6768 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6771 return getZeroVector(VT, Subtarget, DAG, dl);
6774 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6775 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6776 // vpcmpeqd on 256-bit vectors.
6777 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6778 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6781 if (!VT.is512BitVector())
6782 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6785 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6786 if (Broadcast.getNode())
6789 unsigned EVTBits = ExtVT.getSizeInBits();
6791 unsigned NumZero = 0;
6792 unsigned NumNonZero = 0;
6793 unsigned NonZeros = 0;
6794 bool IsAllConstants = true;
6795 SmallSet<SDValue, 8> Values;
6796 for (unsigned i = 0; i < NumElems; ++i) {
6797 SDValue Elt = Op.getOperand(i);
6798 if (Elt.getOpcode() == ISD::UNDEF)
6801 if (Elt.getOpcode() != ISD::Constant &&
6802 Elt.getOpcode() != ISD::ConstantFP)
6803 IsAllConstants = false;
6804 if (X86::isZeroNode(Elt))
6807 NonZeros |= (1 << i);
6812 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6813 if (NumNonZero == 0)
6814 return DAG.getUNDEF(VT);
6816 // Special case for single non-zero, non-undef, element.
6817 if (NumNonZero == 1) {
6818 unsigned Idx = countTrailingZeros(NonZeros);
6819 SDValue Item = Op.getOperand(Idx);
6821 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6822 // the value are obviously zero, truncate the value to i32 and do the
6823 // insertion that way. Only do this if the value is non-constant or if the
6824 // value is a constant being inserted into element 0. It is cheaper to do
6825 // a constant pool load than it is to do a movd + shuffle.
6826 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6827 (!IsAllConstants || Idx == 0)) {
6828 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6830 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6831 EVT VecVT = MVT::v4i32;
6832 unsigned VecElts = 4;
6834 // Truncate the value (which may itself be a constant) to i32, and
6835 // convert it to a vector with movd (S2V+shuffle to zero extend).
6836 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6837 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6839 // If using the new shuffle lowering, just directly insert this.
6840 if (ExperimentalVectorShuffleLowering)
6842 ISD::BITCAST, dl, VT,
6843 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6845 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6847 // Now we have our 32-bit value zero extended in the low element of
6848 // a vector. If Idx != 0, swizzle it into place.
6850 SmallVector<int, 4> Mask;
6851 Mask.push_back(Idx);
6852 for (unsigned i = 1; i != VecElts; ++i)
6854 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6857 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6861 // If we have a constant or non-constant insertion into the low element of
6862 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6863 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6864 // depending on what the source datatype is.
6867 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6869 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6870 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6871 if (VT.is256BitVector() || VT.is512BitVector()) {
6872 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6873 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6874 Item, DAG.getIntPtrConstant(0));
6876 assert(VT.is128BitVector() && "Expected an SSE value type!");
6877 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6878 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6879 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6882 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6883 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6884 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6885 if (VT.is256BitVector()) {
6886 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6887 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6889 assert(VT.is128BitVector() && "Expected an SSE value type!");
6890 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6892 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6896 // Is it a vector logical left shift?
6897 if (NumElems == 2 && Idx == 1 &&
6898 X86::isZeroNode(Op.getOperand(0)) &&
6899 !X86::isZeroNode(Op.getOperand(1))) {
6900 unsigned NumBits = VT.getSizeInBits();
6901 return getVShift(true, VT,
6902 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6903 VT, Op.getOperand(1)),
6904 NumBits/2, DAG, *this, dl);
6907 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6910 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6911 // is a non-constant being inserted into an element other than the low one,
6912 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6913 // movd/movss) to move this into the low element, then shuffle it into
6915 if (EVTBits == 32) {
6916 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6918 // If using the new shuffle lowering, just directly insert this.
6919 if (ExperimentalVectorShuffleLowering)
6920 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6922 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6923 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6924 SmallVector<int, 8> MaskVec;
6925 for (unsigned i = 0; i != NumElems; ++i)
6926 MaskVec.push_back(i == Idx ? 0 : 1);
6927 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6931 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6932 if (Values.size() == 1) {
6933 if (EVTBits == 32) {
6934 // Instead of a shuffle like this:
6935 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6936 // Check if it's possible to issue this instead.
6937 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6938 unsigned Idx = countTrailingZeros(NonZeros);
6939 SDValue Item = Op.getOperand(Idx);
6940 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6941 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6946 // A vector full of immediates; various special cases are already
6947 // handled, so this is best done with a single constant-pool load.
6951 // For AVX-length vectors, build the individual 128-bit pieces and use
6952 // shuffles to put them in place.
6953 if (VT.is256BitVector() || VT.is512BitVector()) {
6954 SmallVector<SDValue, 64> V;
6955 for (unsigned i = 0; i != NumElems; ++i)
6956 V.push_back(Op.getOperand(i));
6958 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6960 // Build both the lower and upper subvector.
6961 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6962 makeArrayRef(&V[0], NumElems/2));
6963 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6964 makeArrayRef(&V[NumElems / 2], NumElems/2));
6966 // Recreate the wider vector with the lower and upper part.
6967 if (VT.is256BitVector())
6968 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6969 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6972 // Let legalizer expand 2-wide build_vectors.
6973 if (EVTBits == 64) {
6974 if (NumNonZero == 1) {
6975 // One half is zero or undef.
6976 unsigned Idx = countTrailingZeros(NonZeros);
6977 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6978 Op.getOperand(Idx));
6979 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6984 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6985 if (EVTBits == 8 && NumElems == 16) {
6986 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6988 if (V.getNode()) return V;
6991 if (EVTBits == 16 && NumElems == 8) {
6992 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6994 if (V.getNode()) return V;
6997 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6998 if (EVTBits == 32 && NumElems == 4) {
6999 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
7000 NumZero, DAG, Subtarget, *this);
7005 // If element VT is == 32 bits, turn it into a number of shuffles.
7006 SmallVector<SDValue, 8> V(NumElems);
7007 if (NumElems == 4 && NumZero > 0) {
7008 for (unsigned i = 0; i < 4; ++i) {
7009 bool isZero = !(NonZeros & (1 << i));
7011 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7013 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7016 for (unsigned i = 0; i < 2; ++i) {
7017 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7020 V[i] = V[i*2]; // Must be a zero vector.
7023 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7026 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7034 bool Reverse1 = (NonZeros & 0x3) == 2;
7035 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7039 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7040 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7042 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7045 if (Values.size() > 1 && VT.is128BitVector()) {
7046 // Check for a build vector of consecutive loads.
7047 for (unsigned i = 0; i < NumElems; ++i)
7048 V[i] = Op.getOperand(i);
7050 // Check for elements which are consecutive loads.
7051 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7055 // Check for a build vector from mostly shuffle plus few inserting.
7056 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7060 // For SSE 4.1, use insertps to put the high elements into the low element.
7061 if (getSubtarget()->hasSSE41()) {
7063 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7064 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7066 Result = DAG.getUNDEF(VT);
7068 for (unsigned i = 1; i < NumElems; ++i) {
7069 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7070 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7071 Op.getOperand(i), DAG.getIntPtrConstant(i));
7076 // Otherwise, expand into a number of unpckl*, start by extending each of
7077 // our (non-undef) elements to the full vector width with the element in the
7078 // bottom slot of the vector (which generates no code for SSE).
7079 for (unsigned i = 0; i < NumElems; ++i) {
7080 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7081 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7083 V[i] = DAG.getUNDEF(VT);
7086 // Next, we iteratively mix elements, e.g. for v4f32:
7087 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7088 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7089 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7090 unsigned EltStride = NumElems >> 1;
7091 while (EltStride != 0) {
7092 for (unsigned i = 0; i < EltStride; ++i) {
7093 // If V[i+EltStride] is undef and this is the first round of mixing,
7094 // then it is safe to just drop this shuffle: V[i] is already in the
7095 // right place, the one element (since it's the first round) being
7096 // inserted as undef can be dropped. This isn't safe for successive
7097 // rounds because they will permute elements within both vectors.
7098 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7099 EltStride == NumElems/2)
7102 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7111 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7112 // to create 256-bit vectors from two other 128-bit ones.
7113 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7115 MVT ResVT = Op.getSimpleValueType();
7117 assert((ResVT.is256BitVector() ||
7118 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7120 SDValue V1 = Op.getOperand(0);
7121 SDValue V2 = Op.getOperand(1);
7122 unsigned NumElems = ResVT.getVectorNumElements();
7123 if(ResVT.is256BitVector())
7124 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7126 if (Op.getNumOperands() == 4) {
7127 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7128 ResVT.getVectorNumElements()/2);
7129 SDValue V3 = Op.getOperand(2);
7130 SDValue V4 = Op.getOperand(3);
7131 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7132 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7134 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7137 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7138 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7139 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7140 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7141 Op.getNumOperands() == 4)));
7143 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7144 // from two other 128-bit ones.
7146 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7147 return LowerAVXCONCAT_VECTORS(Op, DAG);
7151 //===----------------------------------------------------------------------===//
7152 // Vector shuffle lowering
7154 // This is an experimental code path for lowering vector shuffles on x86. It is
7155 // designed to handle arbitrary vector shuffles and blends, gracefully
7156 // degrading performance as necessary. It works hard to recognize idiomatic
7157 // shuffles and lower them to optimal instruction patterns without leaving
7158 // a framework that allows reasonably efficient handling of all vector shuffle
7160 //===----------------------------------------------------------------------===//
7162 /// \brief Tiny helper function to identify a no-op mask.
7164 /// This is a somewhat boring predicate function. It checks whether the mask
7165 /// array input, which is assumed to be a single-input shuffle mask of the kind
7166 /// used by the X86 shuffle instructions (not a fully general
7167 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7168 /// in-place shuffle are 'no-op's.
7169 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7170 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7171 if (Mask[i] != -1 && Mask[i] != i)
7176 /// \brief Helper function to classify a mask as a single-input mask.
7178 /// This isn't a generic single-input test because in the vector shuffle
7179 /// lowering we canonicalize single inputs to be the first input operand. This
7180 /// means we can more quickly test for a single input by only checking whether
7181 /// an input from the second operand exists. We also assume that the size of
7182 /// mask corresponds to the size of the input vectors which isn't true in the
7183 /// fully general case.
7184 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7186 if (M >= (int)Mask.size())
7191 /// \brief Test whether there are elements crossing 128-bit lanes in this
7194 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7195 /// and we routinely test for these.
7196 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7197 int LaneSize = 128 / VT.getScalarSizeInBits();
7198 int Size = Mask.size();
7199 for (int i = 0; i < Size; ++i)
7200 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7205 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7207 /// This checks a shuffle mask to see if it is performing the same
7208 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7209 /// that it is also not lane-crossing. It may however involve a blend from the
7210 /// same lane of a second vector.
7212 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7213 /// non-trivial to compute in the face of undef lanes. The representation is
7214 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7215 /// entries from both V1 and V2 inputs to the wider mask.
7217 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7218 SmallVectorImpl<int> &RepeatedMask) {
7219 int LaneSize = 128 / VT.getScalarSizeInBits();
7220 RepeatedMask.resize(LaneSize, -1);
7221 int Size = Mask.size();
7222 for (int i = 0; i < Size; ++i) {
7225 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7226 // This entry crosses lanes, so there is no way to model this shuffle.
7229 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7230 if (RepeatedMask[i % LaneSize] == -1)
7231 // This is the first non-undef entry in this slot of a 128-bit lane.
7232 RepeatedMask[i % LaneSize] =
7233 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7234 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7235 // Found a mismatch with the repeated mask.
7241 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7242 // 2013 will allow us to use it as a non-type template parameter.
7245 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7247 /// See its documentation for details.
7248 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7249 if (Mask.size() != Args.size())
7251 for (int i = 0, e = Mask.size(); i < e; ++i) {
7252 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7253 if (Mask[i] != -1 && Mask[i] != *Args[i])
7261 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7264 /// This is a fast way to test a shuffle mask against a fixed pattern:
7266 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7268 /// It returns true if the mask is exactly as wide as the argument list, and
7269 /// each element of the mask is either -1 (signifying undef) or the value given
7270 /// in the argument.
7271 static const VariadicFunction1<
7272 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7274 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7276 /// This helper function produces an 8-bit shuffle immediate corresponding to
7277 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7278 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7281 /// NB: We rely heavily on "undef" masks preserving the input lane.
7282 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7283 SelectionDAG &DAG) {
7284 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7285 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7286 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7287 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7288 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7291 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7292 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7293 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7294 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7295 return DAG.getConstant(Imm, MVT::i8);
7298 /// \brief Try to emit a blend instruction for a shuffle.
7300 /// This doesn't do any checks for the availability of instructions for blending
7301 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7302 /// be matched in the backend with the type given. What it does check for is
7303 /// that the shuffle mask is in fact a blend.
7304 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7305 SDValue V2, ArrayRef<int> Mask,
7306 const X86Subtarget *Subtarget,
7307 SelectionDAG &DAG) {
7309 unsigned BlendMask = 0;
7310 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7311 if (Mask[i] >= Size) {
7312 if (Mask[i] != i + Size)
7313 return SDValue(); // Shuffled V2 input!
7314 BlendMask |= 1u << i;
7317 if (Mask[i] >= 0 && Mask[i] != i)
7318 return SDValue(); // Shuffled V1 input!
7320 switch (VT.SimpleTy) {
7325 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7326 DAG.getConstant(BlendMask, MVT::i8));
7330 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7334 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7335 // that instruction.
7336 if (Subtarget->hasAVX2()) {
7337 // Scale the blend by the number of 32-bit dwords per element.
7338 int Scale = VT.getScalarSizeInBits() / 32;
7340 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7341 if (Mask[i] >= Size)
7342 for (int j = 0; j < Scale; ++j)
7343 BlendMask |= 1u << (i * Scale + j);
7345 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7346 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7347 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7348 return DAG.getNode(ISD::BITCAST, DL, VT,
7349 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7350 DAG.getConstant(BlendMask, MVT::i8)));
7354 // For integer shuffles we need to expand the mask and cast the inputs to
7355 // v8i16s prior to blending.
7356 int Scale = 8 / VT.getVectorNumElements();
7358 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7359 if (Mask[i] >= Size)
7360 for (int j = 0; j < Scale; ++j)
7361 BlendMask |= 1u << (i * Scale + j);
7363 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7364 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7365 return DAG.getNode(ISD::BITCAST, DL, VT,
7366 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7367 DAG.getConstant(BlendMask, MVT::i8)));
7371 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7372 SmallVector<int, 8> RepeatedMask;
7373 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7374 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7375 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7377 for (int i = 0; i < 8; ++i)
7378 if (RepeatedMask[i] >= 16)
7379 BlendMask |= 1u << i;
7380 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7381 DAG.getConstant(BlendMask, MVT::i8));
7386 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7387 // Scale the blend by the number of bytes per element.
7388 int Scale = VT.getScalarSizeInBits() / 8;
7389 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7391 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7392 // mix of LLVM's code generator and the x86 backend. We tell the code
7393 // generator that boolean values in the elements of an x86 vector register
7394 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7395 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7396 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7397 // of the element (the remaining are ignored) and 0 in that high bit would
7398 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7399 // the LLVM model for boolean values in vector elements gets the relevant
7400 // bit set, it is set backwards and over constrained relative to x86's
7402 SDValue VSELECTMask[32];
7403 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7404 for (int j = 0; j < Scale; ++j)
7405 VSELECTMask[Scale * i + j] =
7406 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7407 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7409 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7410 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7412 ISD::BITCAST, DL, VT,
7413 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7414 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7419 llvm_unreachable("Not a supported integer vector type!");
7423 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7424 /// unblended shuffles followed by an unshuffled blend.
7426 /// This matches the extremely common pattern for handling combined
7427 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7429 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7433 SelectionDAG &DAG) {
7434 // Shuffle the input elements into the desired positions in V1 and V2 and
7435 // blend them together.
7436 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7437 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7438 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7439 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7440 if (Mask[i] >= 0 && Mask[i] < Size) {
7441 V1Mask[i] = Mask[i];
7443 } else if (Mask[i] >= Size) {
7444 V2Mask[i] = Mask[i] - Size;
7445 BlendMask[i] = i + Size;
7448 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7449 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7450 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7453 /// \brief Try to lower a vector shuffle as a byte rotation.
7455 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7456 /// byte-rotation of the concatenation of two vectors. This routine will
7457 /// try to generically lower a vector shuffle through such an instruction. It
7458 /// does not check for the availability of PALIGNR-based lowerings, only the
7459 /// applicability of this strategy to the given mask. This matches shuffle
7460 /// vectors that look like:
7462 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7464 /// Essentially it concatenates V1 and V2, shifts right by some number of
7465 /// elements, and takes the low elements as the result. Note that while this is
7466 /// specified as a *right shift* because x86 is little-endian, it is a *left
7467 /// rotate* of the vector lanes.
7469 /// Note that this only handles 128-bit vector widths currently.
7470 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7473 SelectionDAG &DAG) {
7474 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7476 // We need to detect various ways of spelling a rotation:
7477 // [11, 12, 13, 14, 15, 0, 1, 2]
7478 // [-1, 12, 13, 14, -1, -1, 1, -1]
7479 // [-1, -1, -1, -1, -1, -1, 1, 2]
7480 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7481 // [-1, 4, 5, 6, -1, -1, 9, -1]
7482 // [-1, 4, 5, 6, -1, -1, -1, -1]
7485 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7488 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7490 // Based on the mod-Size value of this mask element determine where
7491 // a rotated vector would have started.
7492 int StartIdx = i - (Mask[i] % Size);
7494 // The identity rotation isn't interesting, stop.
7497 // If we found the tail of a vector the rotation must be the missing
7498 // front. If we found the head of a vector, it must be how much of the head.
7499 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7502 Rotation = CandidateRotation;
7503 else if (Rotation != CandidateRotation)
7504 // The rotations don't match, so we can't match this mask.
7507 // Compute which value this mask is pointing at.
7508 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7510 // Compute which of the two target values this index should be assigned to.
7511 // This reflects whether the high elements are remaining or the low elements
7513 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7515 // Either set up this value if we've not encountered it before, or check
7516 // that it remains consistent.
7519 else if (TargetV != MaskV)
7520 // This may be a rotation, but it pulls from the inputs in some
7521 // unsupported interleaving.
7525 // Check that we successfully analyzed the mask, and normalize the results.
7526 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7527 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7533 // Cast the inputs to v16i8 to match PALIGNR.
7534 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7535 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7537 assert(VT.getSizeInBits() == 128 &&
7538 "Rotate-based lowering only supports 128-bit lowering!");
7539 assert(Mask.size() <= 16 &&
7540 "Can shuffle at most 16 bytes in a 128-bit vector!");
7541 // The actual rotate instruction rotates bytes, so we need to scale the
7542 // rotation based on how many bytes are in the vector.
7543 int Scale = 16 / Mask.size();
7545 return DAG.getNode(ISD::BITCAST, DL, VT,
7546 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7547 DAG.getConstant(Rotation * Scale, MVT::i8)));
7550 /// \brief Compute whether each element of a shuffle is zeroable.
7552 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7553 /// Either it is an undef element in the shuffle mask, the element of the input
7554 /// referenced is undef, or the element of the input referenced is known to be
7555 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7556 /// as many lanes with this technique as possible to simplify the remaining
7558 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7559 SDValue V1, SDValue V2) {
7560 SmallBitVector Zeroable(Mask.size(), false);
7562 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7563 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7565 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7567 // Handle the easy cases.
7568 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7573 // If this is an index into a build_vector node, dig out the input value and
7575 SDValue V = M < Size ? V1 : V2;
7576 if (V.getOpcode() != ISD::BUILD_VECTOR)
7579 SDValue Input = V.getOperand(M % Size);
7580 // The UNDEF opcode check really should be dead code here, but not quite
7581 // worth asserting on (it isn't invalid, just unexpected).
7582 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7589 /// \brief Lower a vector shuffle as a zero or any extension.
7591 /// Given a specific number of elements, element bit width, and extension
7592 /// stride, produce either a zero or any extension based on the available
7593 /// features of the subtarget.
7594 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7595 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7596 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7597 assert(Scale > 1 && "Need a scale to extend.");
7598 int EltBits = VT.getSizeInBits() / NumElements;
7599 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7600 "Only 8, 16, and 32 bit elements can be extended.");
7601 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7603 // Found a valid zext mask! Try various lowering strategies based on the
7604 // input type and available ISA extensions.
7605 if (Subtarget->hasSSE41()) {
7606 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7607 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7608 NumElements / Scale);
7609 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7610 return DAG.getNode(ISD::BITCAST, DL, VT,
7611 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7614 // For any extends we can cheat for larger element sizes and use shuffle
7615 // instructions that can fold with a load and/or copy.
7616 if (AnyExt && EltBits == 32) {
7617 int PSHUFDMask[4] = {0, -1, 1, -1};
7619 ISD::BITCAST, DL, VT,
7620 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7621 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7622 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7624 if (AnyExt && EltBits == 16 && Scale > 2) {
7625 int PSHUFDMask[4] = {0, -1, 0, -1};
7626 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7627 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7628 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7629 int PSHUFHWMask[4] = {1, -1, -1, -1};
7631 ISD::BITCAST, DL, VT,
7632 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7633 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7634 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7637 // If this would require more than 2 unpack instructions to expand, use
7638 // pshufb when available. We can only use more than 2 unpack instructions
7639 // when zero extending i8 elements which also makes it easier to use pshufb.
7640 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7641 assert(NumElements == 16 && "Unexpected byte vector width!");
7642 SDValue PSHUFBMask[16];
7643 for (int i = 0; i < 16; ++i)
7645 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7646 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7647 return DAG.getNode(ISD::BITCAST, DL, VT,
7648 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7649 DAG.getNode(ISD::BUILD_VECTOR, DL,
7650 MVT::v16i8, PSHUFBMask)));
7653 // Otherwise emit a sequence of unpacks.
7655 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7656 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7657 : getZeroVector(InputVT, Subtarget, DAG, DL);
7658 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7659 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7663 } while (Scale > 1);
7664 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7667 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7669 /// This routine will try to do everything in its power to cleverly lower
7670 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7671 /// check for the profitability of this lowering, it tries to aggressively
7672 /// match this pattern. It will use all of the micro-architectural details it
7673 /// can to emit an efficient lowering. It handles both blends with all-zero
7674 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7675 /// masking out later).
7677 /// The reason we have dedicated lowering for zext-style shuffles is that they
7678 /// are both incredibly common and often quite performance sensitive.
7679 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7680 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7681 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7682 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7684 int Bits = VT.getSizeInBits();
7685 int NumElements = Mask.size();
7687 // Define a helper function to check a particular ext-scale and lower to it if
7689 auto Lower = [&](int Scale) -> SDValue {
7692 for (int i = 0; i < NumElements; ++i) {
7694 continue; // Valid anywhere but doesn't tell us anything.
7695 if (i % Scale != 0) {
7696 // Each of the extend elements needs to be zeroable.
7700 // We no lorger are in the anyext case.
7705 // Each of the base elements needs to be consecutive indices into the
7706 // same input vector.
7707 SDValue V = Mask[i] < NumElements ? V1 : V2;
7710 else if (InputV != V)
7711 return SDValue(); // Flip-flopping inputs.
7713 if (Mask[i] % NumElements != i / Scale)
7714 return SDValue(); // Non-consecutive strided elemenst.
7717 // If we fail to find an input, we have a zero-shuffle which should always
7718 // have already been handled.
7719 // FIXME: Maybe handle this here in case during blending we end up with one?
7723 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7724 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7727 // The widest scale possible for extending is to a 64-bit integer.
7728 assert(Bits % 64 == 0 &&
7729 "The number of bits in a vector must be divisible by 64 on x86!");
7730 int NumExtElements = Bits / 64;
7732 // Each iteration, try extending the elements half as much, but into twice as
7734 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7735 assert(NumElements % NumExtElements == 0 &&
7736 "The input vector size must be divisble by the extended size.");
7737 if (SDValue V = Lower(NumElements / NumExtElements))
7741 // No viable ext lowering found.
7745 /// \brief Try to get a scalar value for a specific element of a vector.
7747 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7748 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7749 SelectionDAG &DAG) {
7750 MVT VT = V.getSimpleValueType();
7751 MVT EltVT = VT.getVectorElementType();
7752 while (V.getOpcode() == ISD::BITCAST)
7753 V = V.getOperand(0);
7754 // If the bitcasts shift the element size, we can't extract an equivalent
7756 MVT NewVT = V.getSimpleValueType();
7757 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7760 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7761 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7762 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7767 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7769 /// This is particularly important because the set of instructions varies
7770 /// significantly based on whether the operand is a load or not.
7771 static bool isShuffleFoldableLoad(SDValue V) {
7772 while (V.getOpcode() == ISD::BITCAST)
7773 V = V.getOperand(0);
7775 return ISD::isNON_EXTLoad(V.getNode());
7778 /// \brief Try to lower insertion of a single element into a zero vector.
7780 /// This is a common pattern that we have especially efficient patterns to lower
7781 /// across all subtarget feature sets.
7782 static SDValue lowerVectorShuffleAsElementInsertion(
7783 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7784 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7785 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7787 MVT EltVT = VT.getVectorElementType();
7789 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7790 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7792 bool IsV1Zeroable = true;
7793 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7794 if (i != V2Index && !Zeroable[i]) {
7795 IsV1Zeroable = false;
7799 // Check for a single input from a SCALAR_TO_VECTOR node.
7800 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7801 // all the smarts here sunk into that routine. However, the current
7802 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7803 // vector shuffle lowering is dead.
7804 if (SDValue V2S = getScalarValueForVectorElement(
7805 V2, Mask[V2Index] - Mask.size(), DAG)) {
7806 // We need to zext the scalar if it is smaller than an i32.
7807 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7808 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7809 // Using zext to expand a narrow element won't work for non-zero
7814 // Zero-extend directly to i32.
7816 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7818 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7819 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7820 EltVT == MVT::i16) {
7821 // Either not inserting from the low element of the input or the input
7822 // element size is too small to use VZEXT_MOVL to clear the high bits.
7826 if (!IsV1Zeroable) {
7827 // If V1 can't be treated as a zero vector we have fewer options to lower
7828 // this. We can't support integer vectors or non-zero targets cheaply, and
7829 // the V1 elements can't be permuted in any way.
7830 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7831 if (!VT.isFloatingPoint() || V2Index != 0)
7833 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7834 V1Mask[V2Index] = -1;
7835 if (!isNoopShuffleMask(V1Mask))
7837 // This is essentially a special case blend operation, but if we have
7838 // general purpose blend operations, they are always faster. Bail and let
7839 // the rest of the lowering handle these as blends.
7840 if (Subtarget->hasSSE41())
7843 // Otherwise, use MOVSD or MOVSS.
7844 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7845 "Only two types of floating point element types to handle!");
7846 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7850 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7852 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7855 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7856 // the desired position. Otherwise it is more efficient to do a vector
7857 // shift left. We know that we can do a vector shift left because all
7858 // the inputs are zero.
7859 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7860 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7861 V2Shuffle[V2Index] = 0;
7862 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7864 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7866 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7868 V2Index * EltVT.getSizeInBits(),
7869 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7870 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7876 /// \brief Try to lower broadcast of a single element.
7878 /// For convenience, this code also bundles all of the subtarget feature set
7879 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7880 /// a convenient way to factor it out.
7881 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7883 const X86Subtarget *Subtarget,
7884 SelectionDAG &DAG) {
7885 if (!Subtarget->hasAVX())
7887 if (VT.isInteger() && !Subtarget->hasAVX2())
7890 // Check that the mask is a broadcast.
7891 int BroadcastIdx = -1;
7893 if (M >= 0 && BroadcastIdx == -1)
7895 else if (M >= 0 && M != BroadcastIdx)
7898 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7899 "a sorted mask where the broadcast "
7902 // Go up the chain of (vector) values to try and find a scalar load that
7903 // we can combine with the broadcast.
7905 switch (V.getOpcode()) {
7906 case ISD::CONCAT_VECTORS: {
7907 int OperandSize = Mask.size() / V.getNumOperands();
7908 V = V.getOperand(BroadcastIdx / OperandSize);
7909 BroadcastIdx %= OperandSize;
7913 case ISD::INSERT_SUBVECTOR: {
7914 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7915 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7919 int BeginIdx = (int)ConstantIdx->getZExtValue();
7921 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7922 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7923 BroadcastIdx -= BeginIdx;
7934 // Check if this is a broadcast of a scalar. We special case lowering
7935 // for scalars so that we can more effectively fold with loads.
7936 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7937 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7938 V = V.getOperand(BroadcastIdx);
7940 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7942 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7944 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7945 // We can't broadcast from a vector register w/o AVX2, and we can only
7946 // broadcast from the zero-element of a vector register.
7950 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7953 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7955 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7956 /// support for floating point shuffles but not integer shuffles. These
7957 /// instructions will incur a domain crossing penalty on some chips though so
7958 /// it is better to avoid lowering through this for integer vectors where
7960 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7961 const X86Subtarget *Subtarget,
7962 SelectionDAG &DAG) {
7964 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7965 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7966 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7967 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7968 ArrayRef<int> Mask = SVOp->getMask();
7969 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7971 if (isSingleInputShuffleMask(Mask)) {
7972 // Straight shuffle of a single input vector. Simulate this by using the
7973 // single input as both of the "inputs" to this instruction..
7974 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7976 if (Subtarget->hasAVX()) {
7977 // If we have AVX, we can use VPERMILPS which will allow folding a load
7978 // into the shuffle.
7979 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7980 DAG.getConstant(SHUFPDMask, MVT::i8));
7983 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7984 DAG.getConstant(SHUFPDMask, MVT::i8));
7986 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7987 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7989 // Use dedicated unpack instructions for masks that match their pattern.
7990 if (isShuffleEquivalent(Mask, 0, 2))
7991 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7992 if (isShuffleEquivalent(Mask, 1, 3))
7993 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7995 // If we have a single input, insert that into V1 if we can do so cheaply.
7996 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7997 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7998 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8000 // Try inverting the insertion since for v2 masks it is easy to do and we
8001 // can't reliably sort the mask one way or the other.
8002 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8003 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8004 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8005 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8009 // Try to use one of the special instruction patterns to handle two common
8010 // blend patterns if a zero-blend above didn't work.
8011 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8012 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8013 // We can either use a special instruction to load over the low double or
8014 // to move just the low double.
8016 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8018 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8020 if (Subtarget->hasSSE41())
8021 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8025 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8026 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8027 DAG.getConstant(SHUFPDMask, MVT::i8));
8030 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8032 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8033 /// the integer unit to minimize domain crossing penalties. However, for blends
8034 /// it falls back to the floating point shuffle operation with appropriate bit
8036 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8037 const X86Subtarget *Subtarget,
8038 SelectionDAG &DAG) {
8040 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8041 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8042 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8044 ArrayRef<int> Mask = SVOp->getMask();
8045 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8047 if (isSingleInputShuffleMask(Mask)) {
8048 // Check for being able to broadcast a single element.
8049 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8050 Mask, Subtarget, DAG))
8053 // Straight shuffle of a single input vector. For everything from SSE2
8054 // onward this has a single fast instruction with no scary immediates.
8055 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8056 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8057 int WidenedMask[4] = {
8058 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8059 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8061 ISD::BITCAST, DL, MVT::v2i64,
8062 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8063 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8066 // If we have a single input from V2 insert that into V1 if we can do so
8068 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8069 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8070 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8072 // Try inverting the insertion since for v2 masks it is easy to do and we
8073 // can't reliably sort the mask one way or the other.
8074 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8075 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8076 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8077 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8081 // Use dedicated unpack instructions for masks that match their pattern.
8082 if (isShuffleEquivalent(Mask, 0, 2))
8083 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8084 if (isShuffleEquivalent(Mask, 1, 3))
8085 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8087 if (Subtarget->hasSSE41())
8088 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8092 // Try to use rotation instructions if available.
8093 if (Subtarget->hasSSSE3())
8094 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8095 DL, MVT::v2i64, V1, V2, Mask, DAG))
8098 // We implement this with SHUFPD which is pretty lame because it will likely
8099 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8100 // However, all the alternatives are still more cycles and newer chips don't
8101 // have this problem. It would be really nice if x86 had better shuffles here.
8102 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8103 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8104 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8105 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8108 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8110 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8111 /// It makes no assumptions about whether this is the *best* lowering, it simply
8113 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8114 ArrayRef<int> Mask, SDValue V1,
8115 SDValue V2, SelectionDAG &DAG) {
8116 SDValue LowV = V1, HighV = V2;
8117 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8120 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8122 if (NumV2Elements == 1) {
8124 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8127 // Compute the index adjacent to V2Index and in the same half by toggling
8129 int V2AdjIndex = V2Index ^ 1;
8131 if (Mask[V2AdjIndex] == -1) {
8132 // Handles all the cases where we have a single V2 element and an undef.
8133 // This will only ever happen in the high lanes because we commute the
8134 // vector otherwise.
8136 std::swap(LowV, HighV);
8137 NewMask[V2Index] -= 4;
8139 // Handle the case where the V2 element ends up adjacent to a V1 element.
8140 // To make this work, blend them together as the first step.
8141 int V1Index = V2AdjIndex;
8142 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8143 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8144 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8146 // Now proceed to reconstruct the final blend as we have the necessary
8147 // high or low half formed.
8154 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8155 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8157 } else if (NumV2Elements == 2) {
8158 if (Mask[0] < 4 && Mask[1] < 4) {
8159 // Handle the easy case where we have V1 in the low lanes and V2 in the
8163 } else if (Mask[2] < 4 && Mask[3] < 4) {
8164 // We also handle the reversed case because this utility may get called
8165 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8166 // arrange things in the right direction.
8172 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8173 // trying to place elements directly, just blend them and set up the final
8174 // shuffle to place them.
8176 // The first two blend mask elements are for V1, the second two are for
8178 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8179 Mask[2] < 4 ? Mask[2] : Mask[3],
8180 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8181 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8182 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8183 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8185 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8188 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8189 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8190 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8191 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8194 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8195 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8198 /// \brief Lower 4-lane 32-bit floating point shuffles.
8200 /// Uses instructions exclusively from the floating point unit to minimize
8201 /// domain crossing penalties, as these are sufficient to implement all v4f32
8203 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8204 const X86Subtarget *Subtarget,
8205 SelectionDAG &DAG) {
8207 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8208 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8209 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8210 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8211 ArrayRef<int> Mask = SVOp->getMask();
8212 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8215 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8217 if (NumV2Elements == 0) {
8218 // Check for being able to broadcast a single element.
8219 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8220 Mask, Subtarget, DAG))
8223 if (Subtarget->hasAVX()) {
8224 // If we have AVX, we can use VPERMILPS which will allow folding a load
8225 // into the shuffle.
8226 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8227 getV4X86ShuffleImm8ForMask(Mask, DAG));
8230 // Otherwise, use a straight shuffle of a single input vector. We pass the
8231 // input vector to both operands to simulate this with a SHUFPS.
8232 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8233 getV4X86ShuffleImm8ForMask(Mask, DAG));
8236 // Use dedicated unpack instructions for masks that match their pattern.
8237 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8238 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8239 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8240 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8242 // There are special ways we can lower some single-element blends. However, we
8243 // have custom ways we can lower more complex single-element blends below that
8244 // we defer to if both this and BLENDPS fail to match, so restrict this to
8245 // when the V2 input is targeting element 0 of the mask -- that is the fast
8247 if (NumV2Elements == 1 && Mask[0] >= 4)
8248 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8249 Mask, Subtarget, DAG))
8252 if (Subtarget->hasSSE41())
8253 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8257 // Check for whether we can use INSERTPS to perform the blend. We only use
8258 // INSERTPS when the V1 elements are already in the correct locations
8259 // because otherwise we can just always use two SHUFPS instructions which
8260 // are much smaller to encode than a SHUFPS and an INSERTPS.
8261 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8263 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8266 // When using INSERTPS we can zero any lane of the destination. Collect
8267 // the zero inputs into a mask and drop them from the lanes of V1 which
8268 // actually need to be present as inputs to the INSERTPS.
8269 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8271 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8272 bool InsertNeedsShuffle = false;
8274 for (int i = 0; i < 4; ++i)
8278 } else if (Mask[i] != i) {
8279 InsertNeedsShuffle = true;
8284 // We don't want to use INSERTPS or other insertion techniques if it will
8285 // require shuffling anyways.
8286 if (!InsertNeedsShuffle) {
8287 // If all of V1 is zeroable, replace it with undef.
8288 if ((ZMask | 1 << V2Index) == 0xF)
8289 V1 = DAG.getUNDEF(MVT::v4f32);
8291 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8292 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8294 // Insert the V2 element into the desired position.
8295 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8296 DAG.getConstant(InsertPSMask, MVT::i8));
8300 // Otherwise fall back to a SHUFPS lowering strategy.
8301 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8304 /// \brief Lower 4-lane i32 vector shuffles.
8306 /// We try to handle these with integer-domain shuffles where we can, but for
8307 /// blends we use the floating point domain blend instructions.
8308 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8309 const X86Subtarget *Subtarget,
8310 SelectionDAG &DAG) {
8312 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8313 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8314 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8316 ArrayRef<int> Mask = SVOp->getMask();
8317 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8319 // Whenever we can lower this as a zext, that instruction is strictly faster
8320 // than any alternative. It also allows us to fold memory operands into the
8321 // shuffle in many cases.
8322 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8323 Mask, Subtarget, DAG))
8327 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8329 if (NumV2Elements == 0) {
8330 // Check for being able to broadcast a single element.
8331 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8332 Mask, Subtarget, DAG))
8335 // Straight shuffle of a single input vector. For everything from SSE2
8336 // onward this has a single fast instruction with no scary immediates.
8337 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8338 // but we aren't actually going to use the UNPCK instruction because doing
8339 // so prevents folding a load into this instruction or making a copy.
8340 const int UnpackLoMask[] = {0, 0, 1, 1};
8341 const int UnpackHiMask[] = {2, 2, 3, 3};
8342 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8343 Mask = UnpackLoMask;
8344 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8345 Mask = UnpackHiMask;
8347 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8348 getV4X86ShuffleImm8ForMask(Mask, DAG));
8351 // There are special ways we can lower some single-element blends.
8352 if (NumV2Elements == 1)
8353 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8354 Mask, Subtarget, DAG))
8357 // Use dedicated unpack instructions for masks that match their pattern.
8358 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8359 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8360 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8361 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8363 if (Subtarget->hasSSE41())
8364 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8368 // Try to use rotation instructions if available.
8369 if (Subtarget->hasSSSE3())
8370 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8371 DL, MVT::v4i32, V1, V2, Mask, DAG))
8374 // We implement this with SHUFPS because it can blend from two vectors.
8375 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8376 // up the inputs, bypassing domain shift penalties that we would encur if we
8377 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8379 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8380 DAG.getVectorShuffle(
8382 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8383 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8386 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8387 /// shuffle lowering, and the most complex part.
8389 /// The lowering strategy is to try to form pairs of input lanes which are
8390 /// targeted at the same half of the final vector, and then use a dword shuffle
8391 /// to place them onto the right half, and finally unpack the paired lanes into
8392 /// their final position.
8394 /// The exact breakdown of how to form these dword pairs and align them on the
8395 /// correct sides is really tricky. See the comments within the function for
8396 /// more of the details.
8397 static SDValue lowerV8I16SingleInputVectorShuffle(
8398 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8399 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8400 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8401 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8402 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8404 SmallVector<int, 4> LoInputs;
8405 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8406 [](int M) { return M >= 0; });
8407 std::sort(LoInputs.begin(), LoInputs.end());
8408 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8409 SmallVector<int, 4> HiInputs;
8410 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8411 [](int M) { return M >= 0; });
8412 std::sort(HiInputs.begin(), HiInputs.end());
8413 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8415 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8416 int NumHToL = LoInputs.size() - NumLToL;
8418 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8419 int NumHToH = HiInputs.size() - NumLToH;
8420 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8421 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8422 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8423 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8425 // Check for being able to broadcast a single element.
8426 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8427 Mask, Subtarget, DAG))
8430 // Use dedicated unpack instructions for masks that match their pattern.
8431 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8432 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8433 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8434 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8436 // Try to use rotation instructions if available.
8437 if (Subtarget->hasSSSE3())
8438 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8439 DL, MVT::v8i16, V, V, Mask, DAG))
8442 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8443 // such inputs we can swap two of the dwords across the half mark and end up
8444 // with <=2 inputs to each half in each half. Once there, we can fall through
8445 // to the generic code below. For example:
8447 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8448 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8450 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8451 // and an existing 2-into-2 on the other half. In this case we may have to
8452 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8453 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8454 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8455 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8456 // half than the one we target for fixing) will be fixed when we re-enter this
8457 // path. We will also combine away any sequence of PSHUFD instructions that
8458 // result into a single instruction. Here is an example of the tricky case:
8460 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8461 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8463 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8465 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8466 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8468 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8469 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8471 // The result is fine to be handled by the generic logic.
8472 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8473 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8474 int AOffset, int BOffset) {
8475 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8476 "Must call this with A having 3 or 1 inputs from the A half.");
8477 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8478 "Must call this with B having 1 or 3 inputs from the B half.");
8479 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8480 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8482 // Compute the index of dword with only one word among the three inputs in
8483 // a half by taking the sum of the half with three inputs and subtracting
8484 // the sum of the actual three inputs. The difference is the remaining
8487 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8488 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8489 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8490 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8491 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8492 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8493 int TripleNonInputIdx =
8494 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8495 TripleDWord = TripleNonInputIdx / 2;
8497 // We use xor with one to compute the adjacent DWord to whichever one the
8499 OneInputDWord = (OneInput / 2) ^ 1;
8501 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8502 // and BToA inputs. If there is also such a problem with the BToB and AToB
8503 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8504 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8505 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8506 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8507 // Compute how many inputs will be flipped by swapping these DWords. We
8509 // to balance this to ensure we don't form a 3-1 shuffle in the other
8511 int NumFlippedAToBInputs =
8512 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8513 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8514 int NumFlippedBToBInputs =
8515 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8516 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8517 if ((NumFlippedAToBInputs == 1 &&
8518 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8519 (NumFlippedBToBInputs == 1 &&
8520 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8521 // We choose whether to fix the A half or B half based on whether that
8522 // half has zero flipped inputs. At zero, we may not be able to fix it
8523 // with that half. We also bias towards fixing the B half because that
8524 // will more commonly be the high half, and we have to bias one way.
8525 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8526 ArrayRef<int> Inputs) {
8527 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8528 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8529 PinnedIdx ^ 1) != Inputs.end();
8530 // Determine whether the free index is in the flipped dword or the
8531 // unflipped dword based on where the pinned index is. We use this bit
8532 // in an xor to conditionally select the adjacent dword.
8533 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8534 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8535 FixFreeIdx) != Inputs.end();
8536 if (IsFixIdxInput == IsFixFreeIdxInput)
8538 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8539 FixFreeIdx) != Inputs.end();
8540 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8541 "We need to be changing the number of flipped inputs!");
8542 int PSHUFHalfMask[] = {0, 1, 2, 3};
8543 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8544 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8546 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8549 if (M != -1 && M == FixIdx)
8551 else if (M != -1 && M == FixFreeIdx)
8554 if (NumFlippedBToBInputs != 0) {
8556 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8557 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8559 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8561 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8562 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8567 int PSHUFDMask[] = {0, 1, 2, 3};
8568 PSHUFDMask[ADWord] = BDWord;
8569 PSHUFDMask[BDWord] = ADWord;
8570 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8571 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8572 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8573 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8575 // Adjust the mask to match the new locations of A and B.
8577 if (M != -1 && M/2 == ADWord)
8578 M = 2 * BDWord + M % 2;
8579 else if (M != -1 && M/2 == BDWord)
8580 M = 2 * ADWord + M % 2;
8582 // Recurse back into this routine to re-compute state now that this isn't
8583 // a 3 and 1 problem.
8584 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8587 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8588 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8589 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8590 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8592 // At this point there are at most two inputs to the low and high halves from
8593 // each half. That means the inputs can always be grouped into dwords and
8594 // those dwords can then be moved to the correct half with a dword shuffle.
8595 // We use at most one low and one high word shuffle to collect these paired
8596 // inputs into dwords, and finally a dword shuffle to place them.
8597 int PSHUFLMask[4] = {-1, -1, -1, -1};
8598 int PSHUFHMask[4] = {-1, -1, -1, -1};
8599 int PSHUFDMask[4] = {-1, -1, -1, -1};
8601 // First fix the masks for all the inputs that are staying in their
8602 // original halves. This will then dictate the targets of the cross-half
8604 auto fixInPlaceInputs =
8605 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8606 MutableArrayRef<int> SourceHalfMask,
8607 MutableArrayRef<int> HalfMask, int HalfOffset) {
8608 if (InPlaceInputs.empty())
8610 if (InPlaceInputs.size() == 1) {
8611 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8612 InPlaceInputs[0] - HalfOffset;
8613 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8616 if (IncomingInputs.empty()) {
8617 // Just fix all of the in place inputs.
8618 for (int Input : InPlaceInputs) {
8619 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8620 PSHUFDMask[Input / 2] = Input / 2;
8625 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8626 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8627 InPlaceInputs[0] - HalfOffset;
8628 // Put the second input next to the first so that they are packed into
8629 // a dword. We find the adjacent index by toggling the low bit.
8630 int AdjIndex = InPlaceInputs[0] ^ 1;
8631 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8632 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8633 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8635 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8636 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8638 // Now gather the cross-half inputs and place them into a free dword of
8639 // their target half.
8640 // FIXME: This operation could almost certainly be simplified dramatically to
8641 // look more like the 3-1 fixing operation.
8642 auto moveInputsToRightHalf = [&PSHUFDMask](
8643 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8644 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8645 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8647 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8648 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8650 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8652 int LowWord = Word & ~1;
8653 int HighWord = Word | 1;
8654 return isWordClobbered(SourceHalfMask, LowWord) ||
8655 isWordClobbered(SourceHalfMask, HighWord);
8658 if (IncomingInputs.empty())
8661 if (ExistingInputs.empty()) {
8662 // Map any dwords with inputs from them into the right half.
8663 for (int Input : IncomingInputs) {
8664 // If the source half mask maps over the inputs, turn those into
8665 // swaps and use the swapped lane.
8666 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8667 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8668 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8669 Input - SourceOffset;
8670 // We have to swap the uses in our half mask in one sweep.
8671 for (int &M : HalfMask)
8672 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8674 else if (M == Input)
8675 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8677 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8678 Input - SourceOffset &&
8679 "Previous placement doesn't match!");
8681 // Note that this correctly re-maps both when we do a swap and when
8682 // we observe the other side of the swap above. We rely on that to
8683 // avoid swapping the members of the input list directly.
8684 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8687 // Map the input's dword into the correct half.
8688 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8689 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8691 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8693 "Previous placement doesn't match!");
8696 // And just directly shift any other-half mask elements to be same-half
8697 // as we will have mirrored the dword containing the element into the
8698 // same position within that half.
8699 for (int &M : HalfMask)
8700 if (M >= SourceOffset && M < SourceOffset + 4) {
8701 M = M - SourceOffset + DestOffset;
8702 assert(M >= 0 && "This should never wrap below zero!");
8707 // Ensure we have the input in a viable dword of its current half. This
8708 // is particularly tricky because the original position may be clobbered
8709 // by inputs being moved and *staying* in that half.
8710 if (IncomingInputs.size() == 1) {
8711 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8712 int InputFixed = std::find(std::begin(SourceHalfMask),
8713 std::end(SourceHalfMask), -1) -
8714 std::begin(SourceHalfMask) + SourceOffset;
8715 SourceHalfMask[InputFixed - SourceOffset] =
8716 IncomingInputs[0] - SourceOffset;
8717 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8719 IncomingInputs[0] = InputFixed;
8721 } else if (IncomingInputs.size() == 2) {
8722 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8723 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8724 // We have two non-adjacent or clobbered inputs we need to extract from
8725 // the source half. To do this, we need to map them into some adjacent
8726 // dword slot in the source mask.
8727 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8728 IncomingInputs[1] - SourceOffset};
8730 // If there is a free slot in the source half mask adjacent to one of
8731 // the inputs, place the other input in it. We use (Index XOR 1) to
8732 // compute an adjacent index.
8733 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8734 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8735 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8736 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8737 InputsFixed[1] = InputsFixed[0] ^ 1;
8738 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8739 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8740 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8741 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8742 InputsFixed[0] = InputsFixed[1] ^ 1;
8743 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8744 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8745 // The two inputs are in the same DWord but it is clobbered and the
8746 // adjacent DWord isn't used at all. Move both inputs to the free
8748 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8749 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8750 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8751 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8753 // The only way we hit this point is if there is no clobbering
8754 // (because there are no off-half inputs to this half) and there is no
8755 // free slot adjacent to one of the inputs. In this case, we have to
8756 // swap an input with a non-input.
8757 for (int i = 0; i < 4; ++i)
8758 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8759 "We can't handle any clobbers here!");
8760 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8761 "Cannot have adjacent inputs here!");
8763 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8764 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8766 // We also have to update the final source mask in this case because
8767 // it may need to undo the above swap.
8768 for (int &M : FinalSourceHalfMask)
8769 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8770 M = InputsFixed[1] + SourceOffset;
8771 else if (M == InputsFixed[1] + SourceOffset)
8772 M = (InputsFixed[0] ^ 1) + SourceOffset;
8774 InputsFixed[1] = InputsFixed[0] ^ 1;
8777 // Point everything at the fixed inputs.
8778 for (int &M : HalfMask)
8779 if (M == IncomingInputs[0])
8780 M = InputsFixed[0] + SourceOffset;
8781 else if (M == IncomingInputs[1])
8782 M = InputsFixed[1] + SourceOffset;
8784 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8785 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8788 llvm_unreachable("Unhandled input size!");
8791 // Now hoist the DWord down to the right half.
8792 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8793 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8794 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8795 for (int &M : HalfMask)
8796 for (int Input : IncomingInputs)
8798 M = FreeDWord * 2 + Input % 2;
8800 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8801 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8802 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8803 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8805 // Now enact all the shuffles we've computed to move the inputs into their
8807 if (!isNoopShuffleMask(PSHUFLMask))
8808 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8809 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8810 if (!isNoopShuffleMask(PSHUFHMask))
8811 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8812 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8813 if (!isNoopShuffleMask(PSHUFDMask))
8814 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8815 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8816 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8817 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8819 // At this point, each half should contain all its inputs, and we can then
8820 // just shuffle them into their final position.
8821 assert(std::count_if(LoMask.begin(), LoMask.end(),
8822 [](int M) { return M >= 4; }) == 0 &&
8823 "Failed to lift all the high half inputs to the low mask!");
8824 assert(std::count_if(HiMask.begin(), HiMask.end(),
8825 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8826 "Failed to lift all the low half inputs to the high mask!");
8828 // Do a half shuffle for the low mask.
8829 if (!isNoopShuffleMask(LoMask))
8830 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8831 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8833 // Do a half shuffle with the high mask after shifting its values down.
8834 for (int &M : HiMask)
8837 if (!isNoopShuffleMask(HiMask))
8838 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8839 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8844 /// \brief Detect whether the mask pattern should be lowered through
8847 /// This essentially tests whether viewing the mask as an interleaving of two
8848 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8849 /// lowering it through interleaving is a significantly better strategy.
8850 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8851 int NumEvenInputs[2] = {0, 0};
8852 int NumOddInputs[2] = {0, 0};
8853 int NumLoInputs[2] = {0, 0};
8854 int NumHiInputs[2] = {0, 0};
8855 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8859 int InputIdx = Mask[i] >= Size;
8862 ++NumLoInputs[InputIdx];
8864 ++NumHiInputs[InputIdx];
8867 ++NumEvenInputs[InputIdx];
8869 ++NumOddInputs[InputIdx];
8872 // The minimum number of cross-input results for both the interleaved and
8873 // split cases. If interleaving results in fewer cross-input results, return
8875 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8876 NumEvenInputs[0] + NumOddInputs[1]);
8877 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8878 NumLoInputs[0] + NumHiInputs[1]);
8879 return InterleavedCrosses < SplitCrosses;
8882 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8884 /// This strategy only works when the inputs from each vector fit into a single
8885 /// half of that vector, and generally there are not so many inputs as to leave
8886 /// the in-place shuffles required highly constrained (and thus expensive). It
8887 /// shifts all the inputs into a single side of both input vectors and then
8888 /// uses an unpack to interleave these inputs in a single vector. At that
8889 /// point, we will fall back on the generic single input shuffle lowering.
8890 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8892 MutableArrayRef<int> Mask,
8893 const X86Subtarget *Subtarget,
8894 SelectionDAG &DAG) {
8895 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8896 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8897 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8898 for (int i = 0; i < 8; ++i)
8899 if (Mask[i] >= 0 && Mask[i] < 4)
8900 LoV1Inputs.push_back(i);
8901 else if (Mask[i] >= 4 && Mask[i] < 8)
8902 HiV1Inputs.push_back(i);
8903 else if (Mask[i] >= 8 && Mask[i] < 12)
8904 LoV2Inputs.push_back(i);
8905 else if (Mask[i] >= 12)
8906 HiV2Inputs.push_back(i);
8908 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8909 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8912 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8913 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8914 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8916 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8917 HiV1Inputs.size() + HiV2Inputs.size();
8919 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8920 ArrayRef<int> HiInputs, bool MoveToLo,
8922 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8923 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8924 if (BadInputs.empty())
8927 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8928 int MoveOffset = MoveToLo ? 0 : 4;
8930 if (GoodInputs.empty()) {
8931 for (int BadInput : BadInputs) {
8932 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8933 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8936 if (GoodInputs.size() == 2) {
8937 // If the low inputs are spread across two dwords, pack them into
8939 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8940 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8941 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8942 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8944 // Otherwise pin the good inputs.
8945 for (int GoodInput : GoodInputs)
8946 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8949 if (BadInputs.size() == 2) {
8950 // If we have two bad inputs then there may be either one or two good
8951 // inputs fixed in place. Find a fixed input, and then find the *other*
8952 // two adjacent indices by using modular arithmetic.
8954 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8955 [](int M) { return M >= 0; }) -
8956 std::begin(MoveMask);
8958 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8959 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8960 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8961 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8962 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8963 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8964 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8966 assert(BadInputs.size() == 1 && "All sizes handled");
8967 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8968 std::end(MoveMask), -1) -
8969 std::begin(MoveMask);
8970 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8971 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8975 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8978 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8980 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8983 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8984 // cross-half traffic in the final shuffle.
8986 // Munge the mask to be a single-input mask after the unpack merges the
8990 M = 2 * (M % 4) + (M / 8);
8992 return DAG.getVectorShuffle(
8993 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8994 DL, MVT::v8i16, V1, V2),
8995 DAG.getUNDEF(MVT::v8i16), Mask);
8998 /// \brief Generic lowering of 8-lane i16 shuffles.
9000 /// This handles both single-input shuffles and combined shuffle/blends with
9001 /// two inputs. The single input shuffles are immediately delegated to
9002 /// a dedicated lowering routine.
9004 /// The blends are lowered in one of three fundamental ways. If there are few
9005 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9006 /// of the input is significantly cheaper when lowered as an interleaving of
9007 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9008 /// halves of the inputs separately (making them have relatively few inputs)
9009 /// and then concatenate them.
9010 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9011 const X86Subtarget *Subtarget,
9012 SelectionDAG &DAG) {
9014 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9015 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9016 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9018 ArrayRef<int> OrigMask = SVOp->getMask();
9019 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9020 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9021 MutableArrayRef<int> Mask(MaskStorage);
9023 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9025 // Whenever we can lower this as a zext, that instruction is strictly faster
9026 // than any alternative.
9027 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9028 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9031 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9032 auto isV2 = [](int M) { return M >= 8; };
9034 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9035 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9037 if (NumV2Inputs == 0)
9038 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9040 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9041 "to be V1-input shuffles.");
9043 // There are special ways we can lower some single-element blends.
9044 if (NumV2Inputs == 1)
9045 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9046 Mask, Subtarget, DAG))
9049 if (Subtarget->hasSSE41())
9050 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9054 // Try to use rotation instructions if available.
9055 if (Subtarget->hasSSSE3())
9056 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9057 DL, MVT::v8i16, V1, V2, Mask, DAG))
9060 if (NumV1Inputs + NumV2Inputs <= 4)
9061 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9063 // Check whether an interleaving lowering is likely to be more efficient.
9064 // This isn't perfect but it is a strong heuristic that tends to work well on
9065 // the kinds of shuffles that show up in practice.
9067 // FIXME: Handle 1x, 2x, and 4x interleaving.
9068 if (shouldLowerAsInterleaving(Mask)) {
9069 // FIXME: Figure out whether we should pack these into the low or high
9072 int EMask[8], OMask[8];
9073 for (int i = 0; i < 4; ++i) {
9074 EMask[i] = Mask[2*i];
9075 OMask[i] = Mask[2*i + 1];
9080 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9081 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9083 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9086 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9087 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9089 for (int i = 0; i < 4; ++i) {
9090 LoBlendMask[i] = Mask[i];
9091 HiBlendMask[i] = Mask[i + 4];
9094 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9095 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9096 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9097 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9099 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9100 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9103 /// \brief Check whether a compaction lowering can be done by dropping even
9104 /// elements and compute how many times even elements must be dropped.
9106 /// This handles shuffles which take every Nth element where N is a power of
9107 /// two. Example shuffle masks:
9109 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9110 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9111 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9112 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9113 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9114 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9116 /// Any of these lanes can of course be undef.
9118 /// This routine only supports N <= 3.
9119 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9122 /// \returns N above, or the number of times even elements must be dropped if
9123 /// there is such a number. Otherwise returns zero.
9124 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9125 // Figure out whether we're looping over two inputs or just one.
9126 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9128 // The modulus for the shuffle vector entries is based on whether this is
9129 // a single input or not.
9130 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9131 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9132 "We should only be called with masks with a power-of-2 size!");
9134 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9136 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9137 // and 2^3 simultaneously. This is because we may have ambiguity with
9138 // partially undef inputs.
9139 bool ViableForN[3] = {true, true, true};
9141 for (int i = 0, e = Mask.size(); i < e; ++i) {
9142 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9147 bool IsAnyViable = false;
9148 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9149 if (ViableForN[j]) {
9152 // The shuffle mask must be equal to (i * 2^N) % M.
9153 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9156 ViableForN[j] = false;
9158 // Early exit if we exhaust the possible powers of two.
9163 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9167 // Return 0 as there is no viable power of two.
9171 /// \brief Generic lowering of v16i8 shuffles.
9173 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9174 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9175 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9176 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9178 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9179 const X86Subtarget *Subtarget,
9180 SelectionDAG &DAG) {
9182 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9183 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9184 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9185 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9186 ArrayRef<int> OrigMask = SVOp->getMask();
9187 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9189 // Try to use rotation instructions if available.
9190 if (Subtarget->hasSSSE3())
9191 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9192 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9195 // Try to use a zext lowering.
9196 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9197 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9200 int MaskStorage[16] = {
9201 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9202 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9203 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9204 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9205 MutableArrayRef<int> Mask(MaskStorage);
9206 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9207 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9210 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9212 // For single-input shuffles, there are some nicer lowering tricks we can use.
9213 if (NumV2Elements == 0) {
9214 // Check for being able to broadcast a single element.
9215 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9216 Mask, Subtarget, DAG))
9219 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9220 // Notably, this handles splat and partial-splat shuffles more efficiently.
9221 // However, it only makes sense if the pre-duplication shuffle simplifies
9222 // things significantly. Currently, this means we need to be able to
9223 // express the pre-duplication shuffle as an i16 shuffle.
9225 // FIXME: We should check for other patterns which can be widened into an
9226 // i16 shuffle as well.
9227 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9228 for (int i = 0; i < 16; i += 2)
9229 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9234 auto tryToWidenViaDuplication = [&]() -> SDValue {
9235 if (!canWidenViaDuplication(Mask))
9237 SmallVector<int, 4> LoInputs;
9238 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9239 [](int M) { return M >= 0 && M < 8; });
9240 std::sort(LoInputs.begin(), LoInputs.end());
9241 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9243 SmallVector<int, 4> HiInputs;
9244 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9245 [](int M) { return M >= 8; });
9246 std::sort(HiInputs.begin(), HiInputs.end());
9247 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9250 bool TargetLo = LoInputs.size() >= HiInputs.size();
9251 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9252 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9254 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9255 SmallDenseMap<int, int, 8> LaneMap;
9256 for (int I : InPlaceInputs) {
9257 PreDupI16Shuffle[I/2] = I/2;
9260 int j = TargetLo ? 0 : 4, je = j + 4;
9261 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9262 // Check if j is already a shuffle of this input. This happens when
9263 // there are two adjacent bytes after we move the low one.
9264 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9265 // If we haven't yet mapped the input, search for a slot into which
9267 while (j < je && PreDupI16Shuffle[j] != -1)
9271 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9274 // Map this input with the i16 shuffle.
9275 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9278 // Update the lane map based on the mapping we ended up with.
9279 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9282 ISD::BITCAST, DL, MVT::v16i8,
9283 DAG.getVectorShuffle(MVT::v8i16, DL,
9284 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9285 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9287 // Unpack the bytes to form the i16s that will be shuffled into place.
9288 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9289 MVT::v16i8, V1, V1);
9291 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9292 for (int i = 0; i < 16; ++i)
9293 if (Mask[i] != -1) {
9294 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9295 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9296 if (PostDupI16Shuffle[i / 2] == -1)
9297 PostDupI16Shuffle[i / 2] = MappedMask;
9299 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9300 "Conflicting entrties in the original shuffle!");
9303 ISD::BITCAST, DL, MVT::v16i8,
9304 DAG.getVectorShuffle(MVT::v8i16, DL,
9305 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9306 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9308 if (SDValue V = tryToWidenViaDuplication())
9312 // Check whether an interleaving lowering is likely to be more efficient.
9313 // This isn't perfect but it is a strong heuristic that tends to work well on
9314 // the kinds of shuffles that show up in practice.
9316 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9317 if (shouldLowerAsInterleaving(Mask)) {
9318 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9319 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9321 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9322 return (M >= 8 && M < 16) || M >= 24;
9324 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9325 -1, -1, -1, -1, -1, -1, -1, -1};
9326 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9327 -1, -1, -1, -1, -1, -1, -1, -1};
9328 bool UnpackLo = NumLoHalf >= NumHiHalf;
9329 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9330 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9331 for (int i = 0; i < 8; ++i) {
9332 TargetEMask[i] = Mask[2 * i];
9333 TargetOMask[i] = Mask[2 * i + 1];
9336 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9337 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9339 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9340 MVT::v16i8, Evens, Odds);
9343 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9344 // with PSHUFB. It is important to do this before we attempt to generate any
9345 // blends but after all of the single-input lowerings. If the single input
9346 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9347 // want to preserve that and we can DAG combine any longer sequences into
9348 // a PSHUFB in the end. But once we start blending from multiple inputs,
9349 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9350 // and there are *very* few patterns that would actually be faster than the
9351 // PSHUFB approach because of its ability to zero lanes.
9353 // FIXME: The only exceptions to the above are blends which are exact
9354 // interleavings with direct instructions supporting them. We currently don't
9355 // handle those well here.
9356 if (Subtarget->hasSSSE3()) {
9359 for (int i = 0; i < 16; ++i)
9360 if (Mask[i] == -1) {
9361 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9363 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9365 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9367 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9368 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9369 if (isSingleInputShuffleMask(Mask))
9370 return V1; // Single inputs are easy.
9372 // Otherwise, blend the two.
9373 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9374 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9375 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9378 // There are special ways we can lower some single-element blends.
9379 if (NumV2Elements == 1)
9380 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9381 Mask, Subtarget, DAG))
9384 // Check whether a compaction lowering can be done. This handles shuffles
9385 // which take every Nth element for some even N. See the helper function for
9388 // We special case these as they can be particularly efficiently handled with
9389 // the PACKUSB instruction on x86 and they show up in common patterns of
9390 // rearranging bytes to truncate wide elements.
9391 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9392 // NumEvenDrops is the power of two stride of the elements. Another way of
9393 // thinking about it is that we need to drop the even elements this many
9394 // times to get the original input.
9395 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9397 // First we need to zero all the dropped bytes.
9398 assert(NumEvenDrops <= 3 &&
9399 "No support for dropping even elements more than 3 times.");
9400 // We use the mask type to pick which bytes are preserved based on how many
9401 // elements are dropped.
9402 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9403 SDValue ByteClearMask =
9404 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9405 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9406 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9408 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9410 // Now pack things back together.
9411 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9412 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9413 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9414 for (int i = 1; i < NumEvenDrops; ++i) {
9415 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9416 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9422 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9423 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9424 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9425 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9427 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9428 MutableArrayRef<int> V1HalfBlendMask,
9429 MutableArrayRef<int> V2HalfBlendMask) {
9430 for (int i = 0; i < 8; ++i)
9431 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9432 V1HalfBlendMask[i] = HalfMask[i];
9434 } else if (HalfMask[i] >= 16) {
9435 V2HalfBlendMask[i] = HalfMask[i] - 16;
9436 HalfMask[i] = i + 8;
9439 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9440 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9442 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9444 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9445 MutableArrayRef<int> HiBlendMask) {
9447 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9448 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9450 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9451 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9452 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9453 [](int M) { return M >= 0 && M % 2 == 1; })) {
9454 // Use a mask to drop the high bytes.
9455 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9456 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9457 DAG.getConstant(0x00FF, MVT::v8i16));
9459 // This will be a single vector shuffle instead of a blend so nuke V2.
9460 V2 = DAG.getUNDEF(MVT::v8i16);
9462 // Squash the masks to point directly into V1.
9463 for (int &M : LoBlendMask)
9466 for (int &M : HiBlendMask)
9470 // Otherwise just unpack the low half of V into V1 and the high half into
9471 // V2 so that we can blend them as i16s.
9472 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9473 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9474 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9475 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9478 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9479 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9480 return std::make_pair(BlendedLo, BlendedHi);
9482 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9483 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9484 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9486 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9487 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9489 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9492 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9494 /// This routine breaks down the specific type of 128-bit shuffle and
9495 /// dispatches to the lowering routines accordingly.
9496 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9497 MVT VT, const X86Subtarget *Subtarget,
9498 SelectionDAG &DAG) {
9499 switch (VT.SimpleTy) {
9501 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9503 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9505 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9507 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9509 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9511 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9514 llvm_unreachable("Unimplemented!");
9518 /// \brief Helper function to test whether a shuffle mask could be
9519 /// simplified by widening the elements being shuffled.
9521 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9522 /// leaves it in an unspecified state.
9524 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9525 /// shuffle masks. The latter have the special property of a '-2' representing
9526 /// a zero-ed lane of a vector.
9527 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9528 SmallVectorImpl<int> &WidenedMask) {
9529 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9530 // If both elements are undef, its trivial.
9531 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9532 WidenedMask.push_back(SM_SentinelUndef);
9536 // Check for an undef mask and a mask value properly aligned to fit with
9537 // a pair of values. If we find such a case, use the non-undef mask's value.
9538 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9539 WidenedMask.push_back(Mask[i + 1] / 2);
9542 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9543 WidenedMask.push_back(Mask[i] / 2);
9547 // When zeroing, we need to spread the zeroing across both lanes to widen.
9548 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9549 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9550 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9551 WidenedMask.push_back(SM_SentinelZero);
9557 // Finally check if the two mask values are adjacent and aligned with
9559 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9560 WidenedMask.push_back(Mask[i] / 2);
9564 // Otherwise we can't safely widen the elements used in this shuffle.
9567 assert(WidenedMask.size() == Mask.size() / 2 &&
9568 "Incorrect size of mask after widening the elements!");
9573 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9575 /// This routine just extracts two subvectors, shuffles them independently, and
9576 /// then concatenates them back together. This should work effectively with all
9577 /// AVX vector shuffle types.
9578 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9579 SDValue V2, ArrayRef<int> Mask,
9580 SelectionDAG &DAG) {
9581 assert(VT.getSizeInBits() >= 256 &&
9582 "Only for 256-bit or wider vector shuffles!");
9583 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9584 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9586 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9587 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9589 int NumElements = VT.getVectorNumElements();
9590 int SplitNumElements = NumElements / 2;
9591 MVT ScalarVT = VT.getScalarType();
9592 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9594 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9595 DAG.getIntPtrConstant(0));
9596 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9597 DAG.getIntPtrConstant(SplitNumElements));
9598 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9599 DAG.getIntPtrConstant(0));
9600 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9601 DAG.getIntPtrConstant(SplitNumElements));
9603 // Now create two 4-way blends of these half-width vectors.
9604 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9605 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9606 for (int i = 0; i < SplitNumElements; ++i) {
9607 int M = HalfMask[i];
9608 if (M >= NumElements) {
9609 V2BlendMask.push_back(M - NumElements);
9610 V1BlendMask.push_back(-1);
9611 BlendMask.push_back(SplitNumElements + i);
9612 } else if (M >= 0) {
9613 V2BlendMask.push_back(-1);
9614 V1BlendMask.push_back(M);
9615 BlendMask.push_back(i);
9617 V2BlendMask.push_back(-1);
9618 V1BlendMask.push_back(-1);
9619 BlendMask.push_back(-1);
9623 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9625 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9626 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9628 SDValue Lo = HalfBlend(LoMask);
9629 SDValue Hi = HalfBlend(HiMask);
9630 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9633 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9634 /// a permutation and blend of those lanes.
9636 /// This essentially blends the out-of-lane inputs to each lane into the lane
9637 /// from a permuted copy of the vector. This lowering strategy results in four
9638 /// instructions in the worst case for a single-input cross lane shuffle which
9639 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9640 /// of. Special cases for each particular shuffle pattern should be handled
9641 /// prior to trying this lowering.
9642 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9643 SDValue V1, SDValue V2,
9645 SelectionDAG &DAG) {
9646 // FIXME: This should probably be generalized for 512-bit vectors as well.
9647 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9648 int LaneSize = Mask.size() / 2;
9650 // If there are only inputs from one 128-bit lane, splitting will in fact be
9651 // less expensive. The flags track wether the given lane contains an element
9652 // that crosses to another lane.
9653 bool LaneCrossing[2] = {false, false};
9654 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9655 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9656 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9657 if (!LaneCrossing[0] || !LaneCrossing[1])
9658 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9660 if (isSingleInputShuffleMask(Mask)) {
9661 SmallVector<int, 32> FlippedBlendMask;
9662 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9663 FlippedBlendMask.push_back(
9664 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9666 : Mask[i] % LaneSize +
9667 (i / LaneSize) * LaneSize + Size));
9669 // Flip the vector, and blend the results which should now be in-lane. The
9670 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9671 // 5 for the high source. The value 3 selects the high half of source 2 and
9672 // the value 2 selects the low half of source 2. We only use source 2 to
9673 // allow folding it into a memory operand.
9674 unsigned PERMMask = 3 | 2 << 4;
9675 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9676 V1, DAG.getConstant(PERMMask, MVT::i8));
9677 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9680 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9681 // will be handled by the above logic and a blend of the results, much like
9682 // other patterns in AVX.
9683 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9686 /// \brief Handle lowering 2-lane 128-bit shuffles.
9687 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9688 SDValue V2, ArrayRef<int> Mask,
9689 const X86Subtarget *Subtarget,
9690 SelectionDAG &DAG) {
9691 // Blends are faster and handle all the non-lane-crossing cases.
9692 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9696 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9697 VT.getVectorNumElements() / 2);
9698 // Check for patterns which can be matched with a single insert of a 128-bit
9700 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9701 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9702 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9703 DAG.getIntPtrConstant(0));
9704 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9705 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9706 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9708 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9709 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9710 DAG.getIntPtrConstant(0));
9711 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9712 DAG.getIntPtrConstant(2));
9713 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9716 // Otherwise form a 128-bit permutation.
9717 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9718 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9719 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9720 DAG.getConstant(PermMask, MVT::i8));
9723 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9725 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9726 /// isn't available.
9727 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9728 const X86Subtarget *Subtarget,
9729 SelectionDAG &DAG) {
9731 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9732 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9733 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9734 ArrayRef<int> Mask = SVOp->getMask();
9735 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9737 SmallVector<int, 4> WidenedMask;
9738 if (canWidenShuffleElements(Mask, WidenedMask))
9739 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9742 if (isSingleInputShuffleMask(Mask)) {
9743 // Check for being able to broadcast a single element.
9744 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9745 Mask, Subtarget, DAG))
9748 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9749 // Non-half-crossing single input shuffles can be lowerid with an
9750 // interleaved permutation.
9751 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9752 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9753 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9754 DAG.getConstant(VPERMILPMask, MVT::i8));
9757 // With AVX2 we have direct support for this permutation.
9758 if (Subtarget->hasAVX2())
9759 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9760 getV4X86ShuffleImm8ForMask(Mask, DAG));
9762 // Otherwise, fall back.
9763 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9767 // X86 has dedicated unpack instructions that can handle specific blend
9768 // operations: UNPCKH and UNPCKL.
9769 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9770 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9771 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9772 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9774 // If we have a single input to the zero element, insert that into V1 if we
9775 // can do so cheaply.
9777 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9778 if (NumV2Elements == 1 && Mask[0] >= 4)
9779 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9780 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9783 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9787 // Check if the blend happens to exactly fit that of SHUFPD.
9788 if ((Mask[0] == -1 || Mask[0] < 2) &&
9789 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9790 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9791 (Mask[3] == -1 || Mask[3] >= 6)) {
9792 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9793 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9794 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9795 DAG.getConstant(SHUFPDMask, MVT::i8));
9797 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9798 (Mask[1] == -1 || Mask[1] < 2) &&
9799 (Mask[2] == -1 || Mask[2] >= 6) &&
9800 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9801 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9802 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9803 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9804 DAG.getConstant(SHUFPDMask, MVT::i8));
9807 // Otherwise fall back on generic blend lowering.
9808 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9812 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9814 /// This routine is only called when we have AVX2 and thus a reasonable
9815 /// instruction set for v4i64 shuffling..
9816 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9817 const X86Subtarget *Subtarget,
9818 SelectionDAG &DAG) {
9820 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9821 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9823 ArrayRef<int> Mask = SVOp->getMask();
9824 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9825 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9827 SmallVector<int, 4> WidenedMask;
9828 if (canWidenShuffleElements(Mask, WidenedMask))
9829 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9832 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9836 // Check for being able to broadcast a single element.
9837 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9838 Mask, Subtarget, DAG))
9841 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9842 // use lower latency instructions that will operate on both 128-bit lanes.
9843 SmallVector<int, 2> RepeatedMask;
9844 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9845 if (isSingleInputShuffleMask(Mask)) {
9846 int PSHUFDMask[] = {-1, -1, -1, -1};
9847 for (int i = 0; i < 2; ++i)
9848 if (RepeatedMask[i] >= 0) {
9849 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9850 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9853 ISD::BITCAST, DL, MVT::v4i64,
9854 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9855 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9856 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9859 // Use dedicated unpack instructions for masks that match their pattern.
9860 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9861 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9862 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9863 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9866 // AVX2 provides a direct instruction for permuting a single input across
9868 if (isSingleInputShuffleMask(Mask))
9869 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9870 getV4X86ShuffleImm8ForMask(Mask, DAG));
9872 // Otherwise fall back on generic blend lowering.
9873 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9877 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9879 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9880 /// isn't available.
9881 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9882 const X86Subtarget *Subtarget,
9883 SelectionDAG &DAG) {
9885 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9886 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9887 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9888 ArrayRef<int> Mask = SVOp->getMask();
9889 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9891 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9895 // Check for being able to broadcast a single element.
9896 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9897 Mask, Subtarget, DAG))
9900 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9901 // options to efficiently lower the shuffle.
9902 SmallVector<int, 4> RepeatedMask;
9903 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9904 assert(RepeatedMask.size() == 4 &&
9905 "Repeated masks must be half the mask width!");
9906 if (isSingleInputShuffleMask(Mask))
9907 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9908 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9910 // Use dedicated unpack instructions for masks that match their pattern.
9911 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9912 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9913 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9914 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9916 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9917 // have already handled any direct blends. We also need to squash the
9918 // repeated mask into a simulated v4f32 mask.
9919 for (int i = 0; i < 4; ++i)
9920 if (RepeatedMask[i] >= 8)
9921 RepeatedMask[i] -= 4;
9922 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9925 // If we have a single input shuffle with different shuffle patterns in the
9926 // two 128-bit lanes use the variable mask to VPERMILPS.
9927 if (isSingleInputShuffleMask(Mask)) {
9928 SDValue VPermMask[8];
9929 for (int i = 0; i < 8; ++i)
9930 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9931 : DAG.getConstant(Mask[i], MVT::i32);
9932 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9934 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9935 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9937 if (Subtarget->hasAVX2())
9938 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9939 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9940 DAG.getNode(ISD::BUILD_VECTOR, DL,
9941 MVT::v8i32, VPermMask)),
9944 // Otherwise, fall back.
9945 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9949 // Otherwise fall back on generic blend lowering.
9950 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9954 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9956 /// This routine is only called when we have AVX2 and thus a reasonable
9957 /// instruction set for v8i32 shuffling..
9958 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9959 const X86Subtarget *Subtarget,
9960 SelectionDAG &DAG) {
9962 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9963 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9964 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9965 ArrayRef<int> Mask = SVOp->getMask();
9966 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9967 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9969 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9973 // Check for being able to broadcast a single element.
9974 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9975 Mask, Subtarget, DAG))
9978 // If the shuffle mask is repeated in each 128-bit lane we can use more
9979 // efficient instructions that mirror the shuffles across the two 128-bit
9981 SmallVector<int, 4> RepeatedMask;
9982 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9983 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9984 if (isSingleInputShuffleMask(Mask))
9985 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9986 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9988 // Use dedicated unpack instructions for masks that match their pattern.
9989 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9990 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9991 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9992 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9995 // If the shuffle patterns aren't repeated but it is a single input, directly
9996 // generate a cross-lane VPERMD instruction.
9997 if (isSingleInputShuffleMask(Mask)) {
9998 SDValue VPermMask[8];
9999 for (int i = 0; i < 8; ++i)
10000 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10001 : DAG.getConstant(Mask[i], MVT::i32);
10002 return DAG.getNode(
10003 X86ISD::VPERMV, DL, MVT::v8i32,
10004 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10007 // Otherwise fall back on generic blend lowering.
10008 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10012 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10014 /// This routine is only called when we have AVX2 and thus a reasonable
10015 /// instruction set for v16i16 shuffling..
10016 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10017 const X86Subtarget *Subtarget,
10018 SelectionDAG &DAG) {
10020 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10021 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10022 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10023 ArrayRef<int> Mask = SVOp->getMask();
10024 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10025 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10027 // Check for being able to broadcast a single element.
10028 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10029 Mask, Subtarget, DAG))
10032 // There are no generalized cross-lane shuffle operations available on i16
10034 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10035 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10038 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10042 // Use dedicated unpack instructions for masks that match their pattern.
10043 if (isShuffleEquivalent(Mask,
10044 // First 128-bit lane:
10045 0, 16, 1, 17, 2, 18, 3, 19,
10046 // Second 128-bit lane:
10047 8, 24, 9, 25, 10, 26, 11, 27))
10048 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10049 if (isShuffleEquivalent(Mask,
10050 // First 128-bit lane:
10051 4, 20, 5, 21, 6, 22, 7, 23,
10052 // Second 128-bit lane:
10053 12, 28, 13, 29, 14, 30, 15, 31))
10054 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10056 if (isSingleInputShuffleMask(Mask)) {
10057 SDValue PSHUFBMask[32];
10058 for (int i = 0; i < 16; ++i) {
10059 if (Mask[i] == -1) {
10060 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10064 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10065 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10066 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10067 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10069 return DAG.getNode(
10070 ISD::BITCAST, DL, MVT::v16i16,
10072 X86ISD::PSHUFB, DL, MVT::v32i8,
10073 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10074 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10077 // Otherwise fall back on generic blend lowering.
10078 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
10082 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10084 /// This routine is only called when we have AVX2 and thus a reasonable
10085 /// instruction set for v32i8 shuffling..
10086 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10087 const X86Subtarget *Subtarget,
10088 SelectionDAG &DAG) {
10090 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10091 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10092 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10093 ArrayRef<int> Mask = SVOp->getMask();
10094 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10095 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10097 // Check for being able to broadcast a single element.
10098 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10099 Mask, Subtarget, DAG))
10102 // There are no generalized cross-lane shuffle operations available on i8
10104 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10105 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10108 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10112 // Use dedicated unpack instructions for masks that match their pattern.
10113 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10115 if (isShuffleEquivalent(
10117 // First 128-bit lane:
10118 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10119 // Second 128-bit lane:
10120 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10121 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10122 if (isShuffleEquivalent(
10124 // First 128-bit lane:
10125 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10126 // Second 128-bit lane:
10127 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10128 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10130 if (isSingleInputShuffleMask(Mask)) {
10131 SDValue PSHUFBMask[32];
10132 for (int i = 0; i < 32; ++i)
10135 ? DAG.getUNDEF(MVT::i8)
10136 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10138 return DAG.getNode(
10139 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10140 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10143 // Otherwise fall back on generic blend lowering.
10144 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
10148 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10150 /// This routine either breaks down the specific type of a 256-bit x86 vector
10151 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10152 /// together based on the available instructions.
10153 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10154 MVT VT, const X86Subtarget *Subtarget,
10155 SelectionDAG &DAG) {
10157 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10158 ArrayRef<int> Mask = SVOp->getMask();
10160 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10161 // check for those subtargets here and avoid much of the subtarget querying in
10162 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10163 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10164 // floating point types there eventually, just immediately cast everything to
10165 // a float and operate entirely in that domain.
10166 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10167 int ElementBits = VT.getScalarSizeInBits();
10168 if (ElementBits < 32)
10169 // No floating point type available, decompose into 128-bit vectors.
10170 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10172 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10173 VT.getVectorNumElements());
10174 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10175 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10176 return DAG.getNode(ISD::BITCAST, DL, VT,
10177 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10180 switch (VT.SimpleTy) {
10182 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10184 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10186 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10188 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10190 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10192 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10195 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10199 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10200 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10201 const X86Subtarget *Subtarget,
10202 SelectionDAG &DAG) {
10204 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10205 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10206 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10207 ArrayRef<int> Mask = SVOp->getMask();
10208 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10210 // FIXME: Implement direct support for this type!
10211 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10214 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10215 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10216 const X86Subtarget *Subtarget,
10217 SelectionDAG &DAG) {
10219 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10220 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10221 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10222 ArrayRef<int> Mask = SVOp->getMask();
10223 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10225 // FIXME: Implement direct support for this type!
10226 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10229 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10230 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10231 const X86Subtarget *Subtarget,
10232 SelectionDAG &DAG) {
10234 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10235 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10236 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10237 ArrayRef<int> Mask = SVOp->getMask();
10238 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10240 // FIXME: Implement direct support for this type!
10241 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10244 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10245 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10246 const X86Subtarget *Subtarget,
10247 SelectionDAG &DAG) {
10249 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10250 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10251 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10252 ArrayRef<int> Mask = SVOp->getMask();
10253 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10255 // FIXME: Implement direct support for this type!
10256 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10259 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10260 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10261 const X86Subtarget *Subtarget,
10262 SelectionDAG &DAG) {
10264 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10265 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10266 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10267 ArrayRef<int> Mask = SVOp->getMask();
10268 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10269 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10271 // FIXME: Implement direct support for this type!
10272 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10275 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10276 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10277 const X86Subtarget *Subtarget,
10278 SelectionDAG &DAG) {
10280 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10281 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10282 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10283 ArrayRef<int> Mask = SVOp->getMask();
10284 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10285 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10287 // FIXME: Implement direct support for this type!
10288 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10291 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10293 /// This routine either breaks down the specific type of a 512-bit x86 vector
10294 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10295 /// together based on the available instructions.
10296 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10297 MVT VT, const X86Subtarget *Subtarget,
10298 SelectionDAG &DAG) {
10300 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10301 ArrayRef<int> Mask = SVOp->getMask();
10302 assert(Subtarget->hasAVX512() &&
10303 "Cannot lower 512-bit vectors w/ basic ISA!");
10305 // Check for being able to broadcast a single element.
10306 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10307 Mask, Subtarget, DAG))
10310 // Dispatch to each element type for lowering. If we don't have supprot for
10311 // specific element type shuffles at 512 bits, immediately split them and
10312 // lower them. Each lowering routine of a given type is allowed to assume that
10313 // the requisite ISA extensions for that element type are available.
10314 switch (VT.SimpleTy) {
10316 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10318 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10320 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10322 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10324 if (Subtarget->hasBWI())
10325 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10328 if (Subtarget->hasBWI())
10329 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10333 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10336 // Otherwise fall back on splitting.
10337 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10340 /// \brief Top-level lowering for x86 vector shuffles.
10342 /// This handles decomposition, canonicalization, and lowering of all x86
10343 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10344 /// above in helper routines. The canonicalization attempts to widen shuffles
10345 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10346 /// s.t. only one of the two inputs needs to be tested, etc.
10347 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10348 SelectionDAG &DAG) {
10349 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10350 ArrayRef<int> Mask = SVOp->getMask();
10351 SDValue V1 = Op.getOperand(0);
10352 SDValue V2 = Op.getOperand(1);
10353 MVT VT = Op.getSimpleValueType();
10354 int NumElements = VT.getVectorNumElements();
10357 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10359 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10360 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10361 if (V1IsUndef && V2IsUndef)
10362 return DAG.getUNDEF(VT);
10364 // When we create a shuffle node we put the UNDEF node to second operand,
10365 // but in some cases the first operand may be transformed to UNDEF.
10366 // In this case we should just commute the node.
10368 return DAG.getCommutedVectorShuffle(*SVOp);
10370 // Check for non-undef masks pointing at an undef vector and make the masks
10371 // undef as well. This makes it easier to match the shuffle based solely on
10375 if (M >= NumElements) {
10376 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10377 for (int &M : NewMask)
10378 if (M >= NumElements)
10380 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10383 // Try to collapse shuffles into using a vector type with fewer elements but
10384 // wider element types. We cap this to not form integers or floating point
10385 // elements wider than 64 bits, but it might be interesting to form i128
10386 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10387 SmallVector<int, 16> WidenedMask;
10388 if (VT.getScalarSizeInBits() < 64 &&
10389 canWidenShuffleElements(Mask, WidenedMask)) {
10390 MVT NewEltVT = VT.isFloatingPoint()
10391 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10392 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10393 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10394 // Make sure that the new vector type is legal. For example, v2f64 isn't
10396 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10397 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10398 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10399 return DAG.getNode(ISD::BITCAST, dl, VT,
10400 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10404 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10405 for (int M : SVOp->getMask())
10407 ++NumUndefElements;
10408 else if (M < NumElements)
10413 // Commute the shuffle as needed such that more elements come from V1 than
10414 // V2. This allows us to match the shuffle pattern strictly on how many
10415 // elements come from V1 without handling the symmetric cases.
10416 if (NumV2Elements > NumV1Elements)
10417 return DAG.getCommutedVectorShuffle(*SVOp);
10419 // When the number of V1 and V2 elements are the same, try to minimize the
10420 // number of uses of V2 in the low half of the vector. When that is tied,
10421 // ensure that the sum of indices for V1 is equal to or lower than the sum
10423 if (NumV1Elements == NumV2Elements) {
10424 int LowV1Elements = 0, LowV2Elements = 0;
10425 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10426 if (M >= NumElements)
10430 if (LowV2Elements > LowV1Elements) {
10431 return DAG.getCommutedVectorShuffle(*SVOp);
10432 } else if (LowV2Elements == LowV1Elements) {
10433 int SumV1Indices = 0, SumV2Indices = 0;
10434 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10435 if (SVOp->getMask()[i] >= NumElements)
10437 else if (SVOp->getMask()[i] >= 0)
10439 if (SumV2Indices < SumV1Indices)
10440 return DAG.getCommutedVectorShuffle(*SVOp);
10444 // For each vector width, delegate to a specialized lowering routine.
10445 if (VT.getSizeInBits() == 128)
10446 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10448 if (VT.getSizeInBits() == 256)
10449 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10451 // Force AVX-512 vectors to be scalarized for now.
10452 // FIXME: Implement AVX-512 support!
10453 if (VT.getSizeInBits() == 512)
10454 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10456 llvm_unreachable("Unimplemented!");
10460 //===----------------------------------------------------------------------===//
10461 // Legacy vector shuffle lowering
10463 // This code is the legacy code handling vector shuffles until the above
10464 // replaces its functionality and performance.
10465 //===----------------------------------------------------------------------===//
10467 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10468 bool hasInt256, unsigned *MaskOut = nullptr) {
10469 MVT EltVT = VT.getVectorElementType();
10471 // There is no blend with immediate in AVX-512.
10472 if (VT.is512BitVector())
10475 if (!hasSSE41 || EltVT == MVT::i8)
10477 if (!hasInt256 && VT == MVT::v16i16)
10480 unsigned MaskValue = 0;
10481 unsigned NumElems = VT.getVectorNumElements();
10482 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10483 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10484 unsigned NumElemsInLane = NumElems / NumLanes;
10486 // Blend for v16i16 should be symetric for the both lanes.
10487 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10489 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10490 int EltIdx = MaskVals[i];
10492 if ((EltIdx < 0 || EltIdx == (int)i) &&
10493 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10496 if (((unsigned)EltIdx == (i + NumElems)) &&
10497 (SndLaneEltIdx < 0 ||
10498 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10499 MaskValue |= (1 << i);
10505 *MaskOut = MaskValue;
10509 // Try to lower a shuffle node into a simple blend instruction.
10510 // This function assumes isBlendMask returns true for this
10511 // SuffleVectorSDNode
10512 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10513 unsigned MaskValue,
10514 const X86Subtarget *Subtarget,
10515 SelectionDAG &DAG) {
10516 MVT VT = SVOp->getSimpleValueType(0);
10517 MVT EltVT = VT.getVectorElementType();
10518 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10519 Subtarget->hasInt256() && "Trying to lower a "
10520 "VECTOR_SHUFFLE to a Blend but "
10521 "with the wrong mask"));
10522 SDValue V1 = SVOp->getOperand(0);
10523 SDValue V2 = SVOp->getOperand(1);
10525 unsigned NumElems = VT.getVectorNumElements();
10527 // Convert i32 vectors to floating point if it is not AVX2.
10528 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10530 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10531 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10533 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10534 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10537 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10538 DAG.getConstant(MaskValue, MVT::i32));
10539 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10542 /// In vector type \p VT, return true if the element at index \p InputIdx
10543 /// falls on a different 128-bit lane than \p OutputIdx.
10544 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10545 unsigned OutputIdx) {
10546 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10547 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10550 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10551 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10552 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10553 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10555 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10556 SelectionDAG &DAG) {
10557 MVT VT = V1.getSimpleValueType();
10558 assert(VT.is128BitVector() || VT.is256BitVector());
10560 MVT EltVT = VT.getVectorElementType();
10561 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10562 unsigned NumElts = VT.getVectorNumElements();
10564 SmallVector<SDValue, 32> PshufbMask;
10565 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10566 int InputIdx = MaskVals[OutputIdx];
10567 unsigned InputByteIdx;
10569 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10570 InputByteIdx = 0x80;
10572 // Cross lane is not allowed.
10573 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10575 InputByteIdx = InputIdx * EltSizeInBytes;
10576 // Index is an byte offset within the 128-bit lane.
10577 InputByteIdx &= 0xf;
10580 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10581 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10582 if (InputByteIdx != 0x80)
10587 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10589 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10590 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10591 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10594 // v8i16 shuffles - Prefer shuffles in the following order:
10595 // 1. [all] pshuflw, pshufhw, optional move
10596 // 2. [ssse3] 1 x pshufb
10597 // 3. [ssse3] 2 x pshufb + 1 x por
10598 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10600 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10601 SelectionDAG &DAG) {
10602 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10603 SDValue V1 = SVOp->getOperand(0);
10604 SDValue V2 = SVOp->getOperand(1);
10606 SmallVector<int, 8> MaskVals;
10608 // Determine if more than 1 of the words in each of the low and high quadwords
10609 // of the result come from the same quadword of one of the two inputs. Undef
10610 // mask values count as coming from any quadword, for better codegen.
10612 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10613 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10614 unsigned LoQuad[] = { 0, 0, 0, 0 };
10615 unsigned HiQuad[] = { 0, 0, 0, 0 };
10616 // Indices of quads used.
10617 std::bitset<4> InputQuads;
10618 for (unsigned i = 0; i < 8; ++i) {
10619 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10620 int EltIdx = SVOp->getMaskElt(i);
10621 MaskVals.push_back(EltIdx);
10629 ++Quad[EltIdx / 4];
10630 InputQuads.set(EltIdx / 4);
10633 int BestLoQuad = -1;
10634 unsigned MaxQuad = 1;
10635 for (unsigned i = 0; i < 4; ++i) {
10636 if (LoQuad[i] > MaxQuad) {
10638 MaxQuad = LoQuad[i];
10642 int BestHiQuad = -1;
10644 for (unsigned i = 0; i < 4; ++i) {
10645 if (HiQuad[i] > MaxQuad) {
10647 MaxQuad = HiQuad[i];
10651 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10652 // of the two input vectors, shuffle them into one input vector so only a
10653 // single pshufb instruction is necessary. If there are more than 2 input
10654 // quads, disable the next transformation since it does not help SSSE3.
10655 bool V1Used = InputQuads[0] || InputQuads[1];
10656 bool V2Used = InputQuads[2] || InputQuads[3];
10657 if (Subtarget->hasSSSE3()) {
10658 if (InputQuads.count() == 2 && V1Used && V2Used) {
10659 BestLoQuad = InputQuads[0] ? 0 : 1;
10660 BestHiQuad = InputQuads[2] ? 2 : 3;
10662 if (InputQuads.count() > 2) {
10668 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10669 // the shuffle mask. If a quad is scored as -1, that means that it contains
10670 // words from all 4 input quadwords.
10672 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10674 BestLoQuad < 0 ? 0 : BestLoQuad,
10675 BestHiQuad < 0 ? 1 : BestHiQuad
10677 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10678 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10679 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10680 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10682 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10683 // source words for the shuffle, to aid later transformations.
10684 bool AllWordsInNewV = true;
10685 bool InOrder[2] = { true, true };
10686 for (unsigned i = 0; i != 8; ++i) {
10687 int idx = MaskVals[i];
10689 InOrder[i/4] = false;
10690 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10692 AllWordsInNewV = false;
10696 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10697 if (AllWordsInNewV) {
10698 for (int i = 0; i != 8; ++i) {
10699 int idx = MaskVals[i];
10702 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10703 if ((idx != i) && idx < 4)
10705 if ((idx != i) && idx > 3)
10714 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10715 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10716 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10717 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10718 unsigned TargetMask = 0;
10719 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10720 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10721 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10722 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10723 getShufflePSHUFLWImmediate(SVOp);
10724 V1 = NewV.getOperand(0);
10725 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10729 // Promote splats to a larger type which usually leads to more efficient code.
10730 // FIXME: Is this true if pshufb is available?
10731 if (SVOp->isSplat())
10732 return PromoteSplat(SVOp, DAG);
10734 // If we have SSSE3, and all words of the result are from 1 input vector,
10735 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10736 // is present, fall back to case 4.
10737 if (Subtarget->hasSSSE3()) {
10738 SmallVector<SDValue,16> pshufbMask;
10740 // If we have elements from both input vectors, set the high bit of the
10741 // shuffle mask element to zero out elements that come from V2 in the V1
10742 // mask, and elements that come from V1 in the V2 mask, so that the two
10743 // results can be OR'd together.
10744 bool TwoInputs = V1Used && V2Used;
10745 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10747 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10749 // Calculate the shuffle mask for the second input, shuffle it, and
10750 // OR it with the first shuffled input.
10751 CommuteVectorShuffleMask(MaskVals, 8);
10752 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10753 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10754 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10757 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10758 // and update MaskVals with new element order.
10759 std::bitset<8> InOrder;
10760 if (BestLoQuad >= 0) {
10761 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10762 for (int i = 0; i != 4; ++i) {
10763 int idx = MaskVals[i];
10766 } else if ((idx / 4) == BestLoQuad) {
10767 MaskV[i] = idx & 3;
10771 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10774 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10775 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10776 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10777 NewV.getOperand(0),
10778 getShufflePSHUFLWImmediate(SVOp), DAG);
10782 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10783 // and update MaskVals with the new element order.
10784 if (BestHiQuad >= 0) {
10785 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10786 for (unsigned i = 4; i != 8; ++i) {
10787 int idx = MaskVals[i];
10790 } else if ((idx / 4) == BestHiQuad) {
10791 MaskV[i] = (idx & 3) + 4;
10795 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10798 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10799 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10800 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10801 NewV.getOperand(0),
10802 getShufflePSHUFHWImmediate(SVOp), DAG);
10806 // In case BestHi & BestLo were both -1, which means each quadword has a word
10807 // from each of the four input quadwords, calculate the InOrder bitvector now
10808 // before falling through to the insert/extract cleanup.
10809 if (BestLoQuad == -1 && BestHiQuad == -1) {
10811 for (int i = 0; i != 8; ++i)
10812 if (MaskVals[i] < 0 || MaskVals[i] == i)
10816 // The other elements are put in the right place using pextrw and pinsrw.
10817 for (unsigned i = 0; i != 8; ++i) {
10820 int EltIdx = MaskVals[i];
10823 SDValue ExtOp = (EltIdx < 8) ?
10824 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10825 DAG.getIntPtrConstant(EltIdx)) :
10826 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10827 DAG.getIntPtrConstant(EltIdx - 8));
10828 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10829 DAG.getIntPtrConstant(i));
10834 /// \brief v16i16 shuffles
10836 /// FIXME: We only support generation of a single pshufb currently. We can
10837 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10838 /// well (e.g 2 x pshufb + 1 x por).
10840 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10841 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10842 SDValue V1 = SVOp->getOperand(0);
10843 SDValue V2 = SVOp->getOperand(1);
10846 if (V2.getOpcode() != ISD::UNDEF)
10849 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10850 return getPSHUFB(MaskVals, V1, dl, DAG);
10853 // v16i8 shuffles - Prefer shuffles in the following order:
10854 // 1. [ssse3] 1 x pshufb
10855 // 2. [ssse3] 2 x pshufb + 1 x por
10856 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10857 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10858 const X86Subtarget* Subtarget,
10859 SelectionDAG &DAG) {
10860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10861 SDValue V1 = SVOp->getOperand(0);
10862 SDValue V2 = SVOp->getOperand(1);
10864 ArrayRef<int> MaskVals = SVOp->getMask();
10866 // Promote splats to a larger type which usually leads to more efficient code.
10867 // FIXME: Is this true if pshufb is available?
10868 if (SVOp->isSplat())
10869 return PromoteSplat(SVOp, DAG);
10871 // If we have SSSE3, case 1 is generated when all result bytes come from
10872 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10873 // present, fall back to case 3.
10875 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10876 if (Subtarget->hasSSSE3()) {
10877 SmallVector<SDValue,16> pshufbMask;
10879 // If all result elements are from one input vector, then only translate
10880 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10882 // Otherwise, we have elements from both input vectors, and must zero out
10883 // elements that come from V2 in the first mask, and V1 in the second mask
10884 // so that we can OR them together.
10885 for (unsigned i = 0; i != 16; ++i) {
10886 int EltIdx = MaskVals[i];
10887 if (EltIdx < 0 || EltIdx >= 16)
10889 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10891 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10892 DAG.getNode(ISD::BUILD_VECTOR, dl,
10893 MVT::v16i8, pshufbMask));
10895 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10896 // the 2nd operand if it's undefined or zero.
10897 if (V2.getOpcode() == ISD::UNDEF ||
10898 ISD::isBuildVectorAllZeros(V2.getNode()))
10901 // Calculate the shuffle mask for the second input, shuffle it, and
10902 // OR it with the first shuffled input.
10903 pshufbMask.clear();
10904 for (unsigned i = 0; i != 16; ++i) {
10905 int EltIdx = MaskVals[i];
10906 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10907 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10909 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10910 DAG.getNode(ISD::BUILD_VECTOR, dl,
10911 MVT::v16i8, pshufbMask));
10912 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10915 // No SSSE3 - Calculate in place words and then fix all out of place words
10916 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10917 // the 16 different words that comprise the two doublequadword input vectors.
10918 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10919 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10921 for (int i = 0; i != 8; ++i) {
10922 int Elt0 = MaskVals[i*2];
10923 int Elt1 = MaskVals[i*2+1];
10925 // This word of the result is all undef, skip it.
10926 if (Elt0 < 0 && Elt1 < 0)
10929 // This word of the result is already in the correct place, skip it.
10930 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10933 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10934 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10937 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10938 // using a single extract together, load it and store it.
10939 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10940 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10941 DAG.getIntPtrConstant(Elt1 / 2));
10942 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10943 DAG.getIntPtrConstant(i));
10947 // If Elt1 is defined, extract it from the appropriate source. If the
10948 // source byte is not also odd, shift the extracted word left 8 bits
10949 // otherwise clear the bottom 8 bits if we need to do an or.
10951 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10952 DAG.getIntPtrConstant(Elt1 / 2));
10953 if ((Elt1 & 1) == 0)
10954 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10956 TLI.getShiftAmountTy(InsElt.getValueType())));
10957 else if (Elt0 >= 0)
10958 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10959 DAG.getConstant(0xFF00, MVT::i16));
10961 // If Elt0 is defined, extract it from the appropriate source. If the
10962 // source byte is not also even, shift the extracted word right 8 bits. If
10963 // Elt1 was also defined, OR the extracted values together before
10964 // inserting them in the result.
10966 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10967 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10968 if ((Elt0 & 1) != 0)
10969 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10971 TLI.getShiftAmountTy(InsElt0.getValueType())));
10972 else if (Elt1 >= 0)
10973 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10974 DAG.getConstant(0x00FF, MVT::i16));
10975 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10978 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10979 DAG.getIntPtrConstant(i));
10981 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10984 // v32i8 shuffles - Translate to VPSHUFB if possible.
10986 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10987 const X86Subtarget *Subtarget,
10988 SelectionDAG &DAG) {
10989 MVT VT = SVOp->getSimpleValueType(0);
10990 SDValue V1 = SVOp->getOperand(0);
10991 SDValue V2 = SVOp->getOperand(1);
10993 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10995 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10996 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10997 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10999 // VPSHUFB may be generated if
11000 // (1) one of input vector is undefined or zeroinitializer.
11001 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11002 // And (2) the mask indexes don't cross the 128-bit lane.
11003 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11004 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11007 if (V1IsAllZero && !V2IsAllZero) {
11008 CommuteVectorShuffleMask(MaskVals, 32);
11011 return getPSHUFB(MaskVals, V1, dl, DAG);
11014 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11015 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11016 /// done when every pair / quad of shuffle mask elements point to elements in
11017 /// the right sequence. e.g.
11018 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11020 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11021 SelectionDAG &DAG) {
11022 MVT VT = SVOp->getSimpleValueType(0);
11024 unsigned NumElems = VT.getVectorNumElements();
11027 switch (VT.SimpleTy) {
11028 default: llvm_unreachable("Unexpected!");
11031 return SDValue(SVOp, 0);
11032 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11033 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11034 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11035 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11036 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11037 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11040 SmallVector<int, 8> MaskVec;
11041 for (unsigned i = 0; i != NumElems; i += Scale) {
11043 for (unsigned j = 0; j != Scale; ++j) {
11044 int EltIdx = SVOp->getMaskElt(i+j);
11048 StartIdx = (EltIdx / Scale);
11049 if (EltIdx != (int)(StartIdx*Scale + j))
11052 MaskVec.push_back(StartIdx);
11055 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11056 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11057 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11060 /// getVZextMovL - Return a zero-extending vector move low node.
11062 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11063 SDValue SrcOp, SelectionDAG &DAG,
11064 const X86Subtarget *Subtarget, SDLoc dl) {
11065 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11066 LoadSDNode *LD = nullptr;
11067 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11068 LD = dyn_cast<LoadSDNode>(SrcOp);
11070 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11072 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11073 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11074 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11075 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11076 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11078 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11079 return DAG.getNode(ISD::BITCAST, dl, VT,
11080 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11081 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11083 SrcOp.getOperand(0)
11089 return DAG.getNode(ISD::BITCAST, dl, VT,
11090 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11091 DAG.getNode(ISD::BITCAST, dl,
11095 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11096 /// which could not be matched by any known target speficic shuffle
11098 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11100 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11101 if (NewOp.getNode())
11104 MVT VT = SVOp->getSimpleValueType(0);
11106 unsigned NumElems = VT.getVectorNumElements();
11107 unsigned NumLaneElems = NumElems / 2;
11110 MVT EltVT = VT.getVectorElementType();
11111 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11114 SmallVector<int, 16> Mask;
11115 for (unsigned l = 0; l < 2; ++l) {
11116 // Build a shuffle mask for the output, discovering on the fly which
11117 // input vectors to use as shuffle operands (recorded in InputUsed).
11118 // If building a suitable shuffle vector proves too hard, then bail
11119 // out with UseBuildVector set.
11120 bool UseBuildVector = false;
11121 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11122 unsigned LaneStart = l * NumLaneElems;
11123 for (unsigned i = 0; i != NumLaneElems; ++i) {
11124 // The mask element. This indexes into the input.
11125 int Idx = SVOp->getMaskElt(i+LaneStart);
11127 // the mask element does not index into any input vector.
11128 Mask.push_back(-1);
11132 // The input vector this mask element indexes into.
11133 int Input = Idx / NumLaneElems;
11135 // Turn the index into an offset from the start of the input vector.
11136 Idx -= Input * NumLaneElems;
11138 // Find or create a shuffle vector operand to hold this input.
11140 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11141 if (InputUsed[OpNo] == Input)
11142 // This input vector is already an operand.
11144 if (InputUsed[OpNo] < 0) {
11145 // Create a new operand for this input vector.
11146 InputUsed[OpNo] = Input;
11151 if (OpNo >= array_lengthof(InputUsed)) {
11152 // More than two input vectors used! Give up on trying to create a
11153 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11154 UseBuildVector = true;
11158 // Add the mask index for the new shuffle vector.
11159 Mask.push_back(Idx + OpNo * NumLaneElems);
11162 if (UseBuildVector) {
11163 SmallVector<SDValue, 16> SVOps;
11164 for (unsigned i = 0; i != NumLaneElems; ++i) {
11165 // The mask element. This indexes into the input.
11166 int Idx = SVOp->getMaskElt(i+LaneStart);
11168 SVOps.push_back(DAG.getUNDEF(EltVT));
11172 // The input vector this mask element indexes into.
11173 int Input = Idx / NumElems;
11175 // Turn the index into an offset from the start of the input vector.
11176 Idx -= Input * NumElems;
11178 // Extract the vector element by hand.
11179 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11180 SVOp->getOperand(Input),
11181 DAG.getIntPtrConstant(Idx)));
11184 // Construct the output using a BUILD_VECTOR.
11185 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11186 } else if (InputUsed[0] < 0) {
11187 // No input vectors were used! The result is undefined.
11188 Output[l] = DAG.getUNDEF(NVT);
11190 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11191 (InputUsed[0] % 2) * NumLaneElems,
11193 // If only one input was used, use an undefined vector for the other.
11194 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11195 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11196 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11197 // At least one input vector was used. Create a new shuffle vector.
11198 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11204 // Concatenate the result back
11205 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11208 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11209 /// 4 elements, and match them with several different shuffle types.
11211 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11212 SDValue V1 = SVOp->getOperand(0);
11213 SDValue V2 = SVOp->getOperand(1);
11215 MVT VT = SVOp->getSimpleValueType(0);
11217 assert(VT.is128BitVector() && "Unsupported vector size");
11219 std::pair<int, int> Locs[4];
11220 int Mask1[] = { -1, -1, -1, -1 };
11221 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11223 unsigned NumHi = 0;
11224 unsigned NumLo = 0;
11225 for (unsigned i = 0; i != 4; ++i) {
11226 int Idx = PermMask[i];
11228 Locs[i] = std::make_pair(-1, -1);
11230 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11232 Locs[i] = std::make_pair(0, NumLo);
11233 Mask1[NumLo] = Idx;
11236 Locs[i] = std::make_pair(1, NumHi);
11238 Mask1[2+NumHi] = Idx;
11244 if (NumLo <= 2 && NumHi <= 2) {
11245 // If no more than two elements come from either vector. This can be
11246 // implemented with two shuffles. First shuffle gather the elements.
11247 // The second shuffle, which takes the first shuffle as both of its
11248 // vector operands, put the elements into the right order.
11249 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11251 int Mask2[] = { -1, -1, -1, -1 };
11253 for (unsigned i = 0; i != 4; ++i)
11254 if (Locs[i].first != -1) {
11255 unsigned Idx = (i < 2) ? 0 : 4;
11256 Idx += Locs[i].first * 2 + Locs[i].second;
11260 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11263 if (NumLo == 3 || NumHi == 3) {
11264 // Otherwise, we must have three elements from one vector, call it X, and
11265 // one element from the other, call it Y. First, use a shufps to build an
11266 // intermediate vector with the one element from Y and the element from X
11267 // that will be in the same half in the final destination (the indexes don't
11268 // matter). Then, use a shufps to build the final vector, taking the half
11269 // containing the element from Y from the intermediate, and the other half
11272 // Normalize it so the 3 elements come from V1.
11273 CommuteVectorShuffleMask(PermMask, 4);
11277 // Find the element from V2.
11279 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11280 int Val = PermMask[HiIndex];
11287 Mask1[0] = PermMask[HiIndex];
11289 Mask1[2] = PermMask[HiIndex^1];
11291 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11293 if (HiIndex >= 2) {
11294 Mask1[0] = PermMask[0];
11295 Mask1[1] = PermMask[1];
11296 Mask1[2] = HiIndex & 1 ? 6 : 4;
11297 Mask1[3] = HiIndex & 1 ? 4 : 6;
11298 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11301 Mask1[0] = HiIndex & 1 ? 2 : 0;
11302 Mask1[1] = HiIndex & 1 ? 0 : 2;
11303 Mask1[2] = PermMask[2];
11304 Mask1[3] = PermMask[3];
11309 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11312 // Break it into (shuffle shuffle_hi, shuffle_lo).
11313 int LoMask[] = { -1, -1, -1, -1 };
11314 int HiMask[] = { -1, -1, -1, -1 };
11316 int *MaskPtr = LoMask;
11317 unsigned MaskIdx = 0;
11318 unsigned LoIdx = 0;
11319 unsigned HiIdx = 2;
11320 for (unsigned i = 0; i != 4; ++i) {
11327 int Idx = PermMask[i];
11329 Locs[i] = std::make_pair(-1, -1);
11330 } else if (Idx < 4) {
11331 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11332 MaskPtr[LoIdx] = Idx;
11335 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11336 MaskPtr[HiIdx] = Idx;
11341 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11342 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11343 int MaskOps[] = { -1, -1, -1, -1 };
11344 for (unsigned i = 0; i != 4; ++i)
11345 if (Locs[i].first != -1)
11346 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11347 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11350 static bool MayFoldVectorLoad(SDValue V) {
11351 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11352 V = V.getOperand(0);
11354 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11355 V = V.getOperand(0);
11356 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11357 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11358 // BUILD_VECTOR (load), undef
11359 V = V.getOperand(0);
11361 return MayFoldLoad(V);
11365 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11366 MVT VT = Op.getSimpleValueType();
11368 // Canonizalize to v2f64.
11369 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11370 return DAG.getNode(ISD::BITCAST, dl, VT,
11371 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11376 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11378 SDValue V1 = Op.getOperand(0);
11379 SDValue V2 = Op.getOperand(1);
11380 MVT VT = Op.getSimpleValueType();
11382 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11384 if (HasSSE2 && VT == MVT::v2f64)
11385 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11387 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11388 return DAG.getNode(ISD::BITCAST, dl, VT,
11389 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11390 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11391 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11395 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11396 SDValue V1 = Op.getOperand(0);
11397 SDValue V2 = Op.getOperand(1);
11398 MVT VT = Op.getSimpleValueType();
11400 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11401 "unsupported shuffle type");
11403 if (V2.getOpcode() == ISD::UNDEF)
11407 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11411 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11412 SDValue V1 = Op.getOperand(0);
11413 SDValue V2 = Op.getOperand(1);
11414 MVT VT = Op.getSimpleValueType();
11415 unsigned NumElems = VT.getVectorNumElements();
11417 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11418 // operand of these instructions is only memory, so check if there's a
11419 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11421 bool CanFoldLoad = false;
11423 // Trivial case, when V2 comes from a load.
11424 if (MayFoldVectorLoad(V2))
11425 CanFoldLoad = true;
11427 // When V1 is a load, it can be folded later into a store in isel, example:
11428 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11430 // (MOVLPSmr addr:$src1, VR128:$src2)
11431 // So, recognize this potential and also use MOVLPS or MOVLPD
11432 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11433 CanFoldLoad = true;
11435 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11437 if (HasSSE2 && NumElems == 2)
11438 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11441 // If we don't care about the second element, proceed to use movss.
11442 if (SVOp->getMaskElt(1) != -1)
11443 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11446 // movl and movlp will both match v2i64, but v2i64 is never matched by
11447 // movl earlier because we make it strict to avoid messing with the movlp load
11448 // folding logic (see the code above getMOVLP call). Match it here then,
11449 // this is horrible, but will stay like this until we move all shuffle
11450 // matching to x86 specific nodes. Note that for the 1st condition all
11451 // types are matched with movsd.
11453 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11454 // as to remove this logic from here, as much as possible
11455 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11456 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11457 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11460 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11462 // Invert the operand order and use SHUFPS to match it.
11463 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11464 getShuffleSHUFImmediate(SVOp), DAG);
11467 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11468 SelectionDAG &DAG) {
11470 MVT VT = Load->getSimpleValueType(0);
11471 MVT EVT = VT.getVectorElementType();
11472 SDValue Addr = Load->getOperand(1);
11473 SDValue NewAddr = DAG.getNode(
11474 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11475 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11478 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11479 DAG.getMachineFunction().getMachineMemOperand(
11480 Load->getMemOperand(), 0, EVT.getStoreSize()));
11484 // It is only safe to call this function if isINSERTPSMask is true for
11485 // this shufflevector mask.
11486 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11487 SelectionDAG &DAG) {
11488 // Generate an insertps instruction when inserting an f32 from memory onto a
11489 // v4f32 or when copying a member from one v4f32 to another.
11490 // We also use it for transferring i32 from one register to another,
11491 // since it simply copies the same bits.
11492 // If we're transferring an i32 from memory to a specific element in a
11493 // register, we output a generic DAG that will match the PINSRD
11495 MVT VT = SVOp->getSimpleValueType(0);
11496 MVT EVT = VT.getVectorElementType();
11497 SDValue V1 = SVOp->getOperand(0);
11498 SDValue V2 = SVOp->getOperand(1);
11499 auto Mask = SVOp->getMask();
11500 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11501 "unsupported vector type for insertps/pinsrd");
11503 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11504 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11505 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11509 unsigned DestIndex;
11513 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11516 // If we have 1 element from each vector, we have to check if we're
11517 // changing V1's element's place. If so, we're done. Otherwise, we
11518 // should assume we're changing V2's element's place and behave
11520 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11521 assert(DestIndex <= INT32_MAX && "truncated destination index");
11522 if (FromV1 == FromV2 &&
11523 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11527 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11530 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11531 "More than one element from V1 and from V2, or no elements from one "
11532 "of the vectors. This case should not have returned true from "
11537 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11540 // Get an index into the source vector in the range [0,4) (the mask is
11541 // in the range [0,8) because it can address V1 and V2)
11542 unsigned SrcIndex = Mask[DestIndex] % 4;
11543 if (MayFoldLoad(From)) {
11544 // Trivial case, when From comes from a load and is only used by the
11545 // shuffle. Make it use insertps from the vector that we need from that
11548 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11549 if (!NewLoad.getNode())
11552 if (EVT == MVT::f32) {
11553 // Create this as a scalar to vector to match the instruction pattern.
11554 SDValue LoadScalarToVector =
11555 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11556 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11557 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11559 } else { // EVT == MVT::i32
11560 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11561 // instruction, to match the PINSRD instruction, which loads an i32 to a
11562 // certain vector element.
11563 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11564 DAG.getConstant(DestIndex, MVT::i32));
11568 // Vector-element-to-vector
11569 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11570 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11573 // Reduce a vector shuffle to zext.
11574 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11575 SelectionDAG &DAG) {
11576 // PMOVZX is only available from SSE41.
11577 if (!Subtarget->hasSSE41())
11580 MVT VT = Op.getSimpleValueType();
11582 // Only AVX2 support 256-bit vector integer extending.
11583 if (!Subtarget->hasInt256() && VT.is256BitVector())
11586 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11588 SDValue V1 = Op.getOperand(0);
11589 SDValue V2 = Op.getOperand(1);
11590 unsigned NumElems = VT.getVectorNumElements();
11592 // Extending is an unary operation and the element type of the source vector
11593 // won't be equal to or larger than i64.
11594 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11595 VT.getVectorElementType() == MVT::i64)
11598 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11599 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11600 while ((1U << Shift) < NumElems) {
11601 if (SVOp->getMaskElt(1U << Shift) == 1)
11604 // The maximal ratio is 8, i.e. from i8 to i64.
11609 // Check the shuffle mask.
11610 unsigned Mask = (1U << Shift) - 1;
11611 for (unsigned i = 0; i != NumElems; ++i) {
11612 int EltIdx = SVOp->getMaskElt(i);
11613 if ((i & Mask) != 0 && EltIdx != -1)
11615 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11619 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11620 MVT NeVT = MVT::getIntegerVT(NBits);
11621 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11623 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11626 return DAG.getNode(ISD::BITCAST, DL, VT,
11627 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11630 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11631 SelectionDAG &DAG) {
11632 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11633 MVT VT = Op.getSimpleValueType();
11635 SDValue V1 = Op.getOperand(0);
11636 SDValue V2 = Op.getOperand(1);
11638 if (isZeroShuffle(SVOp))
11639 return getZeroVector(VT, Subtarget, DAG, dl);
11641 // Handle splat operations
11642 if (SVOp->isSplat()) {
11643 // Use vbroadcast whenever the splat comes from a foldable load
11644 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11645 if (Broadcast.getNode())
11649 // Check integer expanding shuffles.
11650 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11651 if (NewOp.getNode())
11654 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11656 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11657 VT == MVT::v32i8) {
11658 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11659 if (NewOp.getNode())
11660 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11661 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11662 // FIXME: Figure out a cleaner way to do this.
11663 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11664 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11665 if (NewOp.getNode()) {
11666 MVT NewVT = NewOp.getSimpleValueType();
11667 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11668 NewVT, true, false))
11669 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11672 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11673 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11674 if (NewOp.getNode()) {
11675 MVT NewVT = NewOp.getSimpleValueType();
11676 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11677 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11686 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11687 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11688 SDValue V1 = Op.getOperand(0);
11689 SDValue V2 = Op.getOperand(1);
11690 MVT VT = Op.getSimpleValueType();
11692 unsigned NumElems = VT.getVectorNumElements();
11693 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11694 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11695 bool V1IsSplat = false;
11696 bool V2IsSplat = false;
11697 bool HasSSE2 = Subtarget->hasSSE2();
11698 bool HasFp256 = Subtarget->hasFp256();
11699 bool HasInt256 = Subtarget->hasInt256();
11700 MachineFunction &MF = DAG.getMachineFunction();
11701 bool OptForSize = MF.getFunction()->getAttributes().
11702 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11704 // Check if we should use the experimental vector shuffle lowering. If so,
11705 // delegate completely to that code path.
11706 if (ExperimentalVectorShuffleLowering)
11707 return lowerVectorShuffle(Op, Subtarget, DAG);
11709 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11711 if (V1IsUndef && V2IsUndef)
11712 return DAG.getUNDEF(VT);
11714 // When we create a shuffle node we put the UNDEF node to second operand,
11715 // but in some cases the first operand may be transformed to UNDEF.
11716 // In this case we should just commute the node.
11718 return DAG.getCommutedVectorShuffle(*SVOp);
11720 // Vector shuffle lowering takes 3 steps:
11722 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11723 // narrowing and commutation of operands should be handled.
11724 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11726 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11727 // so the shuffle can be broken into other shuffles and the legalizer can
11728 // try the lowering again.
11730 // The general idea is that no vector_shuffle operation should be left to
11731 // be matched during isel, all of them must be converted to a target specific
11734 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11735 // narrowing and commutation of operands should be handled. The actual code
11736 // doesn't include all of those, work in progress...
11737 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11738 if (NewOp.getNode())
11741 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11743 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11744 // unpckh_undef). Only use pshufd if speed is more important than size.
11745 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11746 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11747 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11748 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11750 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11751 V2IsUndef && MayFoldVectorLoad(V1))
11752 return getMOVDDup(Op, dl, V1, DAG);
11754 if (isMOVHLPS_v_undef_Mask(M, VT))
11755 return getMOVHighToLow(Op, dl, DAG);
11757 // Use to match splats
11758 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11759 (VT == MVT::v2f64 || VT == MVT::v2i64))
11760 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11762 if (isPSHUFDMask(M, VT)) {
11763 // The actual implementation will match the mask in the if above and then
11764 // during isel it can match several different instructions, not only pshufd
11765 // as its name says, sad but true, emulate the behavior for now...
11766 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11767 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11769 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11771 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11772 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11774 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11775 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11778 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11782 if (isPALIGNRMask(M, VT, Subtarget))
11783 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11784 getShufflePALIGNRImmediate(SVOp),
11787 if (isVALIGNMask(M, VT, Subtarget))
11788 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11789 getShuffleVALIGNImmediate(SVOp),
11792 // Check if this can be converted into a logical shift.
11793 bool isLeft = false;
11794 unsigned ShAmt = 0;
11796 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11797 if (isShift && ShVal.hasOneUse()) {
11798 // If the shifted value has multiple uses, it may be cheaper to use
11799 // v_set0 + movlhps or movhlps, etc.
11800 MVT EltVT = VT.getVectorElementType();
11801 ShAmt *= EltVT.getSizeInBits();
11802 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11805 if (isMOVLMask(M, VT)) {
11806 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11807 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11808 if (!isMOVLPMask(M, VT)) {
11809 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11810 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11812 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11813 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11817 // FIXME: fold these into legal mask.
11818 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11819 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11821 if (isMOVHLPSMask(M, VT))
11822 return getMOVHighToLow(Op, dl, DAG);
11824 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11825 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11827 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11828 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11830 if (isMOVLPMask(M, VT))
11831 return getMOVLP(Op, dl, DAG, HasSSE2);
11833 if (ShouldXformToMOVHLPS(M, VT) ||
11834 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11835 return DAG.getCommutedVectorShuffle(*SVOp);
11838 // No better options. Use a vshldq / vsrldq.
11839 MVT EltVT = VT.getVectorElementType();
11840 ShAmt *= EltVT.getSizeInBits();
11841 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11844 bool Commuted = false;
11845 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11846 // 1,1,1,1 -> v8i16 though.
11847 BitVector UndefElements;
11848 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11849 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11851 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11852 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11855 // Canonicalize the splat or undef, if present, to be on the RHS.
11856 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11857 CommuteVectorShuffleMask(M, NumElems);
11859 std::swap(V1IsSplat, V2IsSplat);
11863 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11864 // Shuffling low element of v1 into undef, just return v1.
11867 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11868 // the instruction selector will not match, so get a canonical MOVL with
11869 // swapped operands to undo the commute.
11870 return getMOVL(DAG, dl, VT, V2, V1);
11873 if (isUNPCKLMask(M, VT, HasInt256))
11874 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11876 if (isUNPCKHMask(M, VT, HasInt256))
11877 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11880 // Normalize mask so all entries that point to V2 points to its first
11881 // element then try to match unpck{h|l} again. If match, return a
11882 // new vector_shuffle with the corrected mask.p
11883 SmallVector<int, 8> NewMask(M.begin(), M.end());
11884 NormalizeMask(NewMask, NumElems);
11885 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11886 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11887 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11888 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11892 // Commute is back and try unpck* again.
11893 // FIXME: this seems wrong.
11894 CommuteVectorShuffleMask(M, NumElems);
11896 std::swap(V1IsSplat, V2IsSplat);
11898 if (isUNPCKLMask(M, VT, HasInt256))
11899 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11901 if (isUNPCKHMask(M, VT, HasInt256))
11902 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11905 // Normalize the node to match x86 shuffle ops if needed
11906 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11907 return DAG.getCommutedVectorShuffle(*SVOp);
11909 // The checks below are all present in isShuffleMaskLegal, but they are
11910 // inlined here right now to enable us to directly emit target specific
11911 // nodes, and remove one by one until they don't return Op anymore.
11913 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11914 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11915 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11916 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11919 if (isPSHUFHWMask(M, VT, HasInt256))
11920 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11921 getShufflePSHUFHWImmediate(SVOp),
11924 if (isPSHUFLWMask(M, VT, HasInt256))
11925 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11926 getShufflePSHUFLWImmediate(SVOp),
11929 unsigned MaskValue;
11930 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11932 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11934 if (isSHUFPMask(M, VT))
11935 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11936 getShuffleSHUFImmediate(SVOp), DAG);
11938 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11939 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11940 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11941 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11943 //===--------------------------------------------------------------------===//
11944 // Generate target specific nodes for 128 or 256-bit shuffles only
11945 // supported in the AVX instruction set.
11948 // Handle VMOVDDUPY permutations
11949 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11950 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11952 // Handle VPERMILPS/D* permutations
11953 if (isVPERMILPMask(M, VT)) {
11954 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11955 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11956 getShuffleSHUFImmediate(SVOp), DAG);
11957 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11958 getShuffleSHUFImmediate(SVOp), DAG);
11962 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11963 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11964 Idx*(NumElems/2), DAG, dl);
11966 // Handle VPERM2F128/VPERM2I128 permutations
11967 if (isVPERM2X128Mask(M, VT, HasFp256))
11968 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11969 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11971 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11972 return getINSERTPS(SVOp, dl, DAG);
11975 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11976 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11978 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11979 VT.is512BitVector()) {
11980 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11981 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11982 SmallVector<SDValue, 16> permclMask;
11983 for (unsigned i = 0; i != NumElems; ++i) {
11984 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11987 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11989 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11990 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11991 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11992 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11993 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11996 //===--------------------------------------------------------------------===//
11997 // Since no target specific shuffle was selected for this generic one,
11998 // lower it into other known shuffles. FIXME: this isn't true yet, but
11999 // this is the plan.
12002 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12003 if (VT == MVT::v8i16) {
12004 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12005 if (NewOp.getNode())
12009 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12010 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12011 if (NewOp.getNode())
12015 if (VT == MVT::v16i8) {
12016 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12017 if (NewOp.getNode())
12021 if (VT == MVT::v32i8) {
12022 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12023 if (NewOp.getNode())
12027 // Handle all 128-bit wide vectors with 4 elements, and match them with
12028 // several different shuffle types.
12029 if (NumElems == 4 && VT.is128BitVector())
12030 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12032 // Handle general 256-bit shuffles
12033 if (VT.is256BitVector())
12034 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12039 // This function assumes its argument is a BUILD_VECTOR of constants or
12040 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12042 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12043 unsigned &MaskValue) {
12045 unsigned NumElems = BuildVector->getNumOperands();
12046 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12047 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12048 unsigned NumElemsInLane = NumElems / NumLanes;
12050 // Blend for v16i16 should be symetric for the both lanes.
12051 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12052 SDValue EltCond = BuildVector->getOperand(i);
12053 SDValue SndLaneEltCond =
12054 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12056 int Lane1Cond = -1, Lane2Cond = -1;
12057 if (isa<ConstantSDNode>(EltCond))
12058 Lane1Cond = !isZero(EltCond);
12059 if (isa<ConstantSDNode>(SndLaneEltCond))
12060 Lane2Cond = !isZero(SndLaneEltCond);
12062 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12063 // Lane1Cond != 0, means we want the first argument.
12064 // Lane1Cond == 0, means we want the second argument.
12065 // The encoding of this argument is 0 for the first argument, 1
12066 // for the second. Therefore, invert the condition.
12067 MaskValue |= !Lane1Cond << i;
12068 else if (Lane1Cond < 0)
12069 MaskValue |= !Lane2Cond << i;
12076 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12078 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12079 SelectionDAG &DAG) {
12080 SDValue Cond = Op.getOperand(0);
12081 SDValue LHS = Op.getOperand(1);
12082 SDValue RHS = Op.getOperand(2);
12084 MVT VT = Op.getSimpleValueType();
12085 MVT EltVT = VT.getVectorElementType();
12086 unsigned NumElems = VT.getVectorNumElements();
12088 // There is no blend with immediate in AVX-512.
12089 if (VT.is512BitVector())
12092 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12094 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12097 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12100 // Check the mask for BLEND and build the value.
12101 unsigned MaskValue = 0;
12102 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12105 // Convert i32 vectors to floating point if it is not AVX2.
12106 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12108 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12109 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12111 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12112 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12115 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12116 DAG.getConstant(MaskValue, MVT::i32));
12117 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12120 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12121 // A vselect where all conditions and data are constants can be optimized into
12122 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12123 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12124 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12125 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12128 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12129 if (BlendOp.getNode())
12132 // Some types for vselect were previously set to Expand, not Legal or
12133 // Custom. Return an empty SDValue so we fall-through to Expand, after
12134 // the Custom lowering phase.
12135 MVT VT = Op.getSimpleValueType();
12136 switch (VT.SimpleTy) {
12141 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12146 // We couldn't create a "Blend with immediate" node.
12147 // This node should still be legal, but we'll have to emit a blendv*
12152 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12153 MVT VT = Op.getSimpleValueType();
12156 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12159 if (VT.getSizeInBits() == 8) {
12160 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12161 Op.getOperand(0), Op.getOperand(1));
12162 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12163 DAG.getValueType(VT));
12164 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12167 if (VT.getSizeInBits() == 16) {
12168 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12169 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12171 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12172 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12173 DAG.getNode(ISD::BITCAST, dl,
12176 Op.getOperand(1)));
12177 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12178 Op.getOperand(0), Op.getOperand(1));
12179 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12180 DAG.getValueType(VT));
12181 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12184 if (VT == MVT::f32) {
12185 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12186 // the result back to FR32 register. It's only worth matching if the
12187 // result has a single use which is a store or a bitcast to i32. And in
12188 // the case of a store, it's not worth it if the index is a constant 0,
12189 // because a MOVSSmr can be used instead, which is smaller and faster.
12190 if (!Op.hasOneUse())
12192 SDNode *User = *Op.getNode()->use_begin();
12193 if ((User->getOpcode() != ISD::STORE ||
12194 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12195 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12196 (User->getOpcode() != ISD::BITCAST ||
12197 User->getValueType(0) != MVT::i32))
12199 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12200 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12203 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12206 if (VT == MVT::i32 || VT == MVT::i64) {
12207 // ExtractPS/pextrq works with constant index.
12208 if (isa<ConstantSDNode>(Op.getOperand(1)))
12214 /// Extract one bit from mask vector, like v16i1 or v8i1.
12215 /// AVX-512 feature.
12217 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12218 SDValue Vec = Op.getOperand(0);
12220 MVT VecVT = Vec.getSimpleValueType();
12221 SDValue Idx = Op.getOperand(1);
12222 MVT EltVT = Op.getSimpleValueType();
12224 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12226 // variable index can't be handled in mask registers,
12227 // extend vector to VR512
12228 if (!isa<ConstantSDNode>(Idx)) {
12229 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12230 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12231 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12232 ExtVT.getVectorElementType(), Ext, Idx);
12233 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12236 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12237 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12238 unsigned MaxSift = rc->getSize()*8 - 1;
12239 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12240 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12241 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12242 DAG.getConstant(MaxSift, MVT::i8));
12243 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12244 DAG.getIntPtrConstant(0));
12248 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12249 SelectionDAG &DAG) const {
12251 SDValue Vec = Op.getOperand(0);
12252 MVT VecVT = Vec.getSimpleValueType();
12253 SDValue Idx = Op.getOperand(1);
12255 if (Op.getSimpleValueType() == MVT::i1)
12256 return ExtractBitFromMaskVector(Op, DAG);
12258 if (!isa<ConstantSDNode>(Idx)) {
12259 if (VecVT.is512BitVector() ||
12260 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12261 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12264 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12265 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12266 MaskEltVT.getSizeInBits());
12268 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12269 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12270 getZeroVector(MaskVT, Subtarget, DAG, dl),
12271 Idx, DAG.getConstant(0, getPointerTy()));
12272 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12273 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12274 Perm, DAG.getConstant(0, getPointerTy()));
12279 // If this is a 256-bit vector result, first extract the 128-bit vector and
12280 // then extract the element from the 128-bit vector.
12281 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12283 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12284 // Get the 128-bit vector.
12285 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12286 MVT EltVT = VecVT.getVectorElementType();
12288 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12290 //if (IdxVal >= NumElems/2)
12291 // IdxVal -= NumElems/2;
12292 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12293 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12294 DAG.getConstant(IdxVal, MVT::i32));
12297 assert(VecVT.is128BitVector() && "Unexpected vector length");
12299 if (Subtarget->hasSSE41()) {
12300 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12305 MVT VT = Op.getSimpleValueType();
12306 // TODO: handle v16i8.
12307 if (VT.getSizeInBits() == 16) {
12308 SDValue Vec = Op.getOperand(0);
12309 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12311 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12312 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12313 DAG.getNode(ISD::BITCAST, dl,
12315 Op.getOperand(1)));
12316 // Transform it so it match pextrw which produces a 32-bit result.
12317 MVT EltVT = MVT::i32;
12318 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12319 Op.getOperand(0), Op.getOperand(1));
12320 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12321 DAG.getValueType(VT));
12322 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12325 if (VT.getSizeInBits() == 32) {
12326 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12330 // SHUFPS the element to the lowest double word, then movss.
12331 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12332 MVT VVT = Op.getOperand(0).getSimpleValueType();
12333 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12334 DAG.getUNDEF(VVT), Mask);
12335 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12336 DAG.getIntPtrConstant(0));
12339 if (VT.getSizeInBits() == 64) {
12340 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12341 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12342 // to match extract_elt for f64.
12343 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12347 // UNPCKHPD the element to the lowest double word, then movsd.
12348 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12349 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12350 int Mask[2] = { 1, -1 };
12351 MVT VVT = Op.getOperand(0).getSimpleValueType();
12352 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12353 DAG.getUNDEF(VVT), Mask);
12354 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12355 DAG.getIntPtrConstant(0));
12361 /// Insert one bit to mask vector, like v16i1 or v8i1.
12362 /// AVX-512 feature.
12364 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12366 SDValue Vec = Op.getOperand(0);
12367 SDValue Elt = Op.getOperand(1);
12368 SDValue Idx = Op.getOperand(2);
12369 MVT VecVT = Vec.getSimpleValueType();
12371 if (!isa<ConstantSDNode>(Idx)) {
12372 // Non constant index. Extend source and destination,
12373 // insert element and then truncate the result.
12374 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12375 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12376 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12377 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12378 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12379 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12382 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12383 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12384 if (Vec.getOpcode() == ISD::UNDEF)
12385 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12386 DAG.getConstant(IdxVal, MVT::i8));
12387 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12388 unsigned MaxSift = rc->getSize()*8 - 1;
12389 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12390 DAG.getConstant(MaxSift, MVT::i8));
12391 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12392 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12393 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12396 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12397 SelectionDAG &DAG) const {
12398 MVT VT = Op.getSimpleValueType();
12399 MVT EltVT = VT.getVectorElementType();
12401 if (EltVT == MVT::i1)
12402 return InsertBitToMaskVector(Op, DAG);
12405 SDValue N0 = Op.getOperand(0);
12406 SDValue N1 = Op.getOperand(1);
12407 SDValue N2 = Op.getOperand(2);
12408 if (!isa<ConstantSDNode>(N2))
12410 auto *N2C = cast<ConstantSDNode>(N2);
12411 unsigned IdxVal = N2C->getZExtValue();
12413 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12414 // into that, and then insert the subvector back into the result.
12415 if (VT.is256BitVector() || VT.is512BitVector()) {
12416 // Get the desired 128-bit vector half.
12417 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12419 // Insert the element into the desired half.
12420 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12421 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12423 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12424 DAG.getConstant(IdxIn128, MVT::i32));
12426 // Insert the changed part back to the 256-bit vector
12427 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12429 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12431 if (Subtarget->hasSSE41()) {
12432 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12434 if (VT == MVT::v8i16) {
12435 Opc = X86ISD::PINSRW;
12437 assert(VT == MVT::v16i8);
12438 Opc = X86ISD::PINSRB;
12441 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12443 if (N1.getValueType() != MVT::i32)
12444 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12445 if (N2.getValueType() != MVT::i32)
12446 N2 = DAG.getIntPtrConstant(IdxVal);
12447 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12450 if (EltVT == MVT::f32) {
12451 // Bits [7:6] of the constant are the source select. This will always be
12452 // zero here. The DAG Combiner may combine an extract_elt index into
12454 // bits. For example (insert (extract, 3), 2) could be matched by
12456 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12457 // Bits [5:4] of the constant are the destination select. This is the
12458 // value of the incoming immediate.
12459 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12460 // combine either bitwise AND or insert of float 0.0 to set these bits.
12461 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12462 // Create this as a scalar to vector..
12463 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12464 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12467 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12468 // PINSR* works with constant index.
12473 if (EltVT == MVT::i8)
12476 if (EltVT.getSizeInBits() == 16) {
12477 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12478 // as its second argument.
12479 if (N1.getValueType() != MVT::i32)
12480 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12481 if (N2.getValueType() != MVT::i32)
12482 N2 = DAG.getIntPtrConstant(IdxVal);
12483 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12488 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12490 MVT OpVT = Op.getSimpleValueType();
12492 // If this is a 256-bit vector result, first insert into a 128-bit
12493 // vector and then insert into the 256-bit vector.
12494 if (!OpVT.is128BitVector()) {
12495 // Insert into a 128-bit vector.
12496 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12497 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12498 OpVT.getVectorNumElements() / SizeFactor);
12500 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12502 // Insert the 128-bit vector.
12503 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12506 if (OpVT == MVT::v1i64 &&
12507 Op.getOperand(0).getValueType() == MVT::i64)
12508 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12510 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12511 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12512 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12513 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12516 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12517 // a simple subregister reference or explicit instructions to grab
12518 // upper bits of a vector.
12519 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12520 SelectionDAG &DAG) {
12522 SDValue In = Op.getOperand(0);
12523 SDValue Idx = Op.getOperand(1);
12524 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12525 MVT ResVT = Op.getSimpleValueType();
12526 MVT InVT = In.getSimpleValueType();
12528 if (Subtarget->hasFp256()) {
12529 if (ResVT.is128BitVector() &&
12530 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12531 isa<ConstantSDNode>(Idx)) {
12532 return Extract128BitVector(In, IdxVal, DAG, dl);
12534 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12535 isa<ConstantSDNode>(Idx)) {
12536 return Extract256BitVector(In, IdxVal, DAG, dl);
12542 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12543 // simple superregister reference or explicit instructions to insert
12544 // the upper bits of a vector.
12545 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12546 SelectionDAG &DAG) {
12547 if (Subtarget->hasFp256()) {
12548 SDLoc dl(Op.getNode());
12549 SDValue Vec = Op.getNode()->getOperand(0);
12550 SDValue SubVec = Op.getNode()->getOperand(1);
12551 SDValue Idx = Op.getNode()->getOperand(2);
12553 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12554 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12555 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12556 isa<ConstantSDNode>(Idx)) {
12557 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12558 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12561 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12562 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12563 isa<ConstantSDNode>(Idx)) {
12564 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12565 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12571 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12572 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12573 // one of the above mentioned nodes. It has to be wrapped because otherwise
12574 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12575 // be used to form addressing mode. These wrapped nodes will be selected
12578 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12579 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12581 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12582 // global base reg.
12583 unsigned char OpFlag = 0;
12584 unsigned WrapperKind = X86ISD::Wrapper;
12585 CodeModel::Model M = DAG.getTarget().getCodeModel();
12587 if (Subtarget->isPICStyleRIPRel() &&
12588 (M == CodeModel::Small || M == CodeModel::Kernel))
12589 WrapperKind = X86ISD::WrapperRIP;
12590 else if (Subtarget->isPICStyleGOT())
12591 OpFlag = X86II::MO_GOTOFF;
12592 else if (Subtarget->isPICStyleStubPIC())
12593 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12595 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12596 CP->getAlignment(),
12597 CP->getOffset(), OpFlag);
12599 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12600 // With PIC, the address is actually $g + Offset.
12602 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12603 DAG.getNode(X86ISD::GlobalBaseReg,
12604 SDLoc(), getPointerTy()),
12611 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12612 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12614 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12615 // global base reg.
12616 unsigned char OpFlag = 0;
12617 unsigned WrapperKind = X86ISD::Wrapper;
12618 CodeModel::Model M = DAG.getTarget().getCodeModel();
12620 if (Subtarget->isPICStyleRIPRel() &&
12621 (M == CodeModel::Small || M == CodeModel::Kernel))
12622 WrapperKind = X86ISD::WrapperRIP;
12623 else if (Subtarget->isPICStyleGOT())
12624 OpFlag = X86II::MO_GOTOFF;
12625 else if (Subtarget->isPICStyleStubPIC())
12626 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12628 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12631 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12633 // With PIC, the address is actually $g + Offset.
12635 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12636 DAG.getNode(X86ISD::GlobalBaseReg,
12637 SDLoc(), getPointerTy()),
12644 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12645 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12647 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12648 // global base reg.
12649 unsigned char OpFlag = 0;
12650 unsigned WrapperKind = X86ISD::Wrapper;
12651 CodeModel::Model M = DAG.getTarget().getCodeModel();
12653 if (Subtarget->isPICStyleRIPRel() &&
12654 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12655 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12656 OpFlag = X86II::MO_GOTPCREL;
12657 WrapperKind = X86ISD::WrapperRIP;
12658 } else if (Subtarget->isPICStyleGOT()) {
12659 OpFlag = X86II::MO_GOT;
12660 } else if (Subtarget->isPICStyleStubPIC()) {
12661 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12662 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12663 OpFlag = X86II::MO_DARWIN_NONLAZY;
12666 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12669 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12671 // With PIC, the address is actually $g + Offset.
12672 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12673 !Subtarget->is64Bit()) {
12674 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12675 DAG.getNode(X86ISD::GlobalBaseReg,
12676 SDLoc(), getPointerTy()),
12680 // For symbols that require a load from a stub to get the address, emit the
12682 if (isGlobalStubReference(OpFlag))
12683 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12684 MachinePointerInfo::getGOT(), false, false, false, 0);
12690 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12691 // Create the TargetBlockAddressAddress node.
12692 unsigned char OpFlags =
12693 Subtarget->ClassifyBlockAddressReference();
12694 CodeModel::Model M = DAG.getTarget().getCodeModel();
12695 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12696 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12698 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12701 if (Subtarget->isPICStyleRIPRel() &&
12702 (M == CodeModel::Small || M == CodeModel::Kernel))
12703 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12705 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12707 // With PIC, the address is actually $g + Offset.
12708 if (isGlobalRelativeToPICBase(OpFlags)) {
12709 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12710 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12718 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12719 int64_t Offset, SelectionDAG &DAG) const {
12720 // Create the TargetGlobalAddress node, folding in the constant
12721 // offset if it is legal.
12722 unsigned char OpFlags =
12723 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12724 CodeModel::Model M = DAG.getTarget().getCodeModel();
12726 if (OpFlags == X86II::MO_NO_FLAG &&
12727 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12728 // A direct static reference to a global.
12729 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12732 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12735 if (Subtarget->isPICStyleRIPRel() &&
12736 (M == CodeModel::Small || M == CodeModel::Kernel))
12737 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12739 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12741 // With PIC, the address is actually $g + Offset.
12742 if (isGlobalRelativeToPICBase(OpFlags)) {
12743 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12744 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12748 // For globals that require a load from a stub to get the address, emit the
12750 if (isGlobalStubReference(OpFlags))
12751 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12752 MachinePointerInfo::getGOT(), false, false, false, 0);
12754 // If there was a non-zero offset that we didn't fold, create an explicit
12755 // addition for it.
12757 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12758 DAG.getConstant(Offset, getPointerTy()));
12764 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12765 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12766 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12767 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12771 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12772 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12773 unsigned char OperandFlags, bool LocalDynamic = false) {
12774 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12775 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12777 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12778 GA->getValueType(0),
12782 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12786 SDValue Ops[] = { Chain, TGA, *InFlag };
12787 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12789 SDValue Ops[] = { Chain, TGA };
12790 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12793 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12794 MFI->setAdjustsStack(true);
12795 MFI->setHasCalls(true);
12797 SDValue Flag = Chain.getValue(1);
12798 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12801 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12803 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12806 SDLoc dl(GA); // ? function entry point might be better
12807 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12808 DAG.getNode(X86ISD::GlobalBaseReg,
12809 SDLoc(), PtrVT), InFlag);
12810 InFlag = Chain.getValue(1);
12812 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12815 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12817 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12819 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12820 X86::RAX, X86II::MO_TLSGD);
12823 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12829 // Get the start address of the TLS block for this module.
12830 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12831 .getInfo<X86MachineFunctionInfo>();
12832 MFI->incNumLocalDynamicTLSAccesses();
12836 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12837 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12840 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12841 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12842 InFlag = Chain.getValue(1);
12843 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12844 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12847 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12851 unsigned char OperandFlags = X86II::MO_DTPOFF;
12852 unsigned WrapperKind = X86ISD::Wrapper;
12853 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12854 GA->getValueType(0),
12855 GA->getOffset(), OperandFlags);
12856 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12858 // Add x@dtpoff with the base.
12859 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12862 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12863 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12864 const EVT PtrVT, TLSModel::Model model,
12865 bool is64Bit, bool isPIC) {
12868 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12869 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12870 is64Bit ? 257 : 256));
12872 SDValue ThreadPointer =
12873 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12874 MachinePointerInfo(Ptr), false, false, false, 0);
12876 unsigned char OperandFlags = 0;
12877 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12879 unsigned WrapperKind = X86ISD::Wrapper;
12880 if (model == TLSModel::LocalExec) {
12881 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12882 } else if (model == TLSModel::InitialExec) {
12884 OperandFlags = X86II::MO_GOTTPOFF;
12885 WrapperKind = X86ISD::WrapperRIP;
12887 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12890 llvm_unreachable("Unexpected model");
12893 // emit "addl x@ntpoff,%eax" (local exec)
12894 // or "addl x@indntpoff,%eax" (initial exec)
12895 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12897 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12898 GA->getOffset(), OperandFlags);
12899 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12901 if (model == TLSModel::InitialExec) {
12902 if (isPIC && !is64Bit) {
12903 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12904 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12908 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12909 MachinePointerInfo::getGOT(), false, false, false, 0);
12912 // The address of the thread local variable is the add of the thread
12913 // pointer with the offset of the variable.
12914 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12918 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12920 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12921 const GlobalValue *GV = GA->getGlobal();
12923 if (Subtarget->isTargetELF()) {
12924 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12927 case TLSModel::GeneralDynamic:
12928 if (Subtarget->is64Bit())
12929 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12930 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12931 case TLSModel::LocalDynamic:
12932 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12933 Subtarget->is64Bit());
12934 case TLSModel::InitialExec:
12935 case TLSModel::LocalExec:
12936 return LowerToTLSExecModel(
12937 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12938 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12940 llvm_unreachable("Unknown TLS model.");
12943 if (Subtarget->isTargetDarwin()) {
12944 // Darwin only has one model of TLS. Lower to that.
12945 unsigned char OpFlag = 0;
12946 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12947 X86ISD::WrapperRIP : X86ISD::Wrapper;
12949 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12950 // global base reg.
12951 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12952 !Subtarget->is64Bit();
12954 OpFlag = X86II::MO_TLVP_PIC_BASE;
12956 OpFlag = X86II::MO_TLVP;
12958 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12959 GA->getValueType(0),
12960 GA->getOffset(), OpFlag);
12961 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12963 // With PIC32, the address is actually $g + Offset.
12965 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12966 DAG.getNode(X86ISD::GlobalBaseReg,
12967 SDLoc(), getPointerTy()),
12970 // Lowering the machine isd will make sure everything is in the right
12972 SDValue Chain = DAG.getEntryNode();
12973 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12974 SDValue Args[] = { Chain, Offset };
12975 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12977 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12978 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12979 MFI->setAdjustsStack(true);
12981 // And our return value (tls address) is in the standard call return value
12983 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12984 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12985 Chain.getValue(1));
12988 if (Subtarget->isTargetKnownWindowsMSVC() ||
12989 Subtarget->isTargetWindowsGNU()) {
12990 // Just use the implicit TLS architecture
12991 // Need to generate someting similar to:
12992 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12994 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12995 // mov rcx, qword [rdx+rcx*8]
12996 // mov eax, .tls$:tlsvar
12997 // [rax+rcx] contains the address
12998 // Windows 64bit: gs:0x58
12999 // Windows 32bit: fs:__tls_array
13002 SDValue Chain = DAG.getEntryNode();
13004 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13005 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13006 // use its literal value of 0x2C.
13007 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13008 ? Type::getInt8PtrTy(*DAG.getContext(),
13010 : Type::getInt32PtrTy(*DAG.getContext(),
13014 Subtarget->is64Bit()
13015 ? DAG.getIntPtrConstant(0x58)
13016 : (Subtarget->isTargetWindowsGNU()
13017 ? DAG.getIntPtrConstant(0x2C)
13018 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13020 SDValue ThreadPointer =
13021 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13022 MachinePointerInfo(Ptr), false, false, false, 0);
13024 // Load the _tls_index variable
13025 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13026 if (Subtarget->is64Bit())
13027 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13028 IDX, MachinePointerInfo(), MVT::i32,
13029 false, false, false, 0);
13031 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13032 false, false, false, 0);
13034 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13036 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13038 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13039 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13040 false, false, false, 0);
13042 // Get the offset of start of .tls section
13043 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13044 GA->getValueType(0),
13045 GA->getOffset(), X86II::MO_SECREL);
13046 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13048 // The address of the thread local variable is the add of the thread
13049 // pointer with the offset of the variable.
13050 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13053 llvm_unreachable("TLS not implemented for this target.");
13056 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13057 /// and take a 2 x i32 value to shift plus a shift amount.
13058 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13059 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13060 MVT VT = Op.getSimpleValueType();
13061 unsigned VTBits = VT.getSizeInBits();
13063 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13064 SDValue ShOpLo = Op.getOperand(0);
13065 SDValue ShOpHi = Op.getOperand(1);
13066 SDValue ShAmt = Op.getOperand(2);
13067 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13068 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13070 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13071 DAG.getConstant(VTBits - 1, MVT::i8));
13072 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13073 DAG.getConstant(VTBits - 1, MVT::i8))
13074 : DAG.getConstant(0, VT);
13076 SDValue Tmp2, Tmp3;
13077 if (Op.getOpcode() == ISD::SHL_PARTS) {
13078 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13079 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13081 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13082 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13085 // If the shift amount is larger or equal than the width of a part we can't
13086 // rely on the results of shld/shrd. Insert a test and select the appropriate
13087 // values for large shift amounts.
13088 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13089 DAG.getConstant(VTBits, MVT::i8));
13090 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13091 AndNode, DAG.getConstant(0, MVT::i8));
13094 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13095 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13096 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13098 if (Op.getOpcode() == ISD::SHL_PARTS) {
13099 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13100 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13102 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13103 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13106 SDValue Ops[2] = { Lo, Hi };
13107 return DAG.getMergeValues(Ops, dl);
13110 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13111 SelectionDAG &DAG) const {
13112 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13114 if (SrcVT.isVector())
13117 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13118 "Unknown SINT_TO_FP to lower!");
13120 // These are really Legal; return the operand so the caller accepts it as
13122 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13124 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13125 Subtarget->is64Bit()) {
13130 unsigned Size = SrcVT.getSizeInBits()/8;
13131 MachineFunction &MF = DAG.getMachineFunction();
13132 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13133 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13134 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13136 MachinePointerInfo::getFixedStack(SSFI),
13138 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13141 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13143 SelectionDAG &DAG) const {
13147 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13149 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13151 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13153 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13155 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13156 MachineMemOperand *MMO;
13158 int SSFI = FI->getIndex();
13160 DAG.getMachineFunction()
13161 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13162 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13164 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13165 StackSlot = StackSlot.getOperand(1);
13167 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13168 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13170 Tys, Ops, SrcVT, MMO);
13173 Chain = Result.getValue(1);
13174 SDValue InFlag = Result.getValue(2);
13176 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13177 // shouldn't be necessary except that RFP cannot be live across
13178 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13179 MachineFunction &MF = DAG.getMachineFunction();
13180 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13181 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13182 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13183 Tys = DAG.getVTList(MVT::Other);
13185 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13187 MachineMemOperand *MMO =
13188 DAG.getMachineFunction()
13189 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13190 MachineMemOperand::MOStore, SSFISize, SSFISize);
13192 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13193 Ops, Op.getValueType(), MMO);
13194 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13195 MachinePointerInfo::getFixedStack(SSFI),
13196 false, false, false, 0);
13202 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13203 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13204 SelectionDAG &DAG) const {
13205 // This algorithm is not obvious. Here it is what we're trying to output:
13208 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13209 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13211 haddpd %xmm0, %xmm0
13213 pshufd $0x4e, %xmm0, %xmm1
13219 LLVMContext *Context = DAG.getContext();
13221 // Build some magic constants.
13222 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13223 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13224 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13226 SmallVector<Constant*,2> CV1;
13228 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13229 APInt(64, 0x4330000000000000ULL))));
13231 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13232 APInt(64, 0x4530000000000000ULL))));
13233 Constant *C1 = ConstantVector::get(CV1);
13234 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13236 // Load the 64-bit value into an XMM register.
13237 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13239 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13240 MachinePointerInfo::getConstantPool(),
13241 false, false, false, 16);
13242 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13243 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13246 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13247 MachinePointerInfo::getConstantPool(),
13248 false, false, false, 16);
13249 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13250 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13253 if (Subtarget->hasSSE3()) {
13254 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13255 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13257 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13258 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13260 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13261 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13265 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13266 DAG.getIntPtrConstant(0));
13269 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13270 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13271 SelectionDAG &DAG) const {
13273 // FP constant to bias correct the final result.
13274 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13277 // Load the 32-bit value into an XMM register.
13278 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13281 // Zero out the upper parts of the register.
13282 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13284 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13285 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13286 DAG.getIntPtrConstant(0));
13288 // Or the load with the bias.
13289 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13290 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13291 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13292 MVT::v2f64, Load)),
13293 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13294 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13295 MVT::v2f64, Bias)));
13296 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13297 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13298 DAG.getIntPtrConstant(0));
13300 // Subtract the bias.
13301 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13303 // Handle final rounding.
13304 EVT DestVT = Op.getValueType();
13306 if (DestVT.bitsLT(MVT::f64))
13307 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13308 DAG.getIntPtrConstant(0));
13309 if (DestVT.bitsGT(MVT::f64))
13310 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13312 // Handle final rounding.
13316 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13317 const X86Subtarget &Subtarget) {
13318 // The algorithm is the following:
13319 // #ifdef __SSE4_1__
13320 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13321 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13322 // (uint4) 0x53000000, 0xaa);
13324 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13325 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13327 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13328 // return (float4) lo + fhi;
13331 SDValue V = Op->getOperand(0);
13332 EVT VecIntVT = V.getValueType();
13333 bool Is128 = VecIntVT == MVT::v4i32;
13334 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13335 unsigned NumElts = VecIntVT.getVectorNumElements();
13336 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13337 "Unsupported custom type");
13338 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13340 // In the #idef/#else code, we have in common:
13341 // - The vector of constants:
13347 // Create the splat vector for 0x4b000000.
13348 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13349 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13350 CstLow, CstLow, CstLow, CstLow};
13351 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13352 makeArrayRef(&CstLowArray[0], NumElts));
13353 // Create the splat vector for 0x53000000.
13354 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13355 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13356 CstHigh, CstHigh, CstHigh, CstHigh};
13357 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13358 makeArrayRef(&CstHighArray[0], NumElts));
13360 // Create the right shift.
13361 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13362 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13363 CstShift, CstShift, CstShift, CstShift};
13364 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13365 makeArrayRef(&CstShiftArray[0], NumElts));
13366 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13369 if (Subtarget.hasSSE41()) {
13370 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13371 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13372 SDValue VecCstLowBitcast =
13373 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13374 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13375 // Low will be bitcasted right away, so do not bother bitcasting back to its
13377 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13378 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13379 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13380 // (uint4) 0x53000000, 0xaa);
13381 SDValue VecCstHighBitcast =
13382 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13383 SDValue VecShiftBitcast =
13384 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13385 // High will be bitcasted right away, so do not bother bitcasting back to
13386 // its original type.
13387 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13388 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13390 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13391 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13392 CstMask, CstMask, CstMask);
13393 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13394 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13395 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13397 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13398 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13401 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13402 SDValue CstFAdd = DAG.getConstantFP(
13403 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13404 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13405 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13406 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13407 makeArrayRef(&CstFAddArray[0], NumElts));
13409 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13410 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13412 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13413 // return (float4) lo + fhi;
13414 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13415 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13418 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13419 SelectionDAG &DAG) const {
13420 SDValue N0 = Op.getOperand(0);
13421 MVT SVT = N0.getSimpleValueType();
13424 switch (SVT.SimpleTy) {
13426 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13431 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13432 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13433 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13437 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13439 llvm_unreachable(nullptr);
13442 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13443 SelectionDAG &DAG) const {
13444 SDValue N0 = Op.getOperand(0);
13447 if (Op.getValueType().isVector())
13448 return lowerUINT_TO_FP_vec(Op, DAG);
13450 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13451 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13452 // the optimization here.
13453 if (DAG.SignBitIsZero(N0))
13454 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13456 MVT SrcVT = N0.getSimpleValueType();
13457 MVT DstVT = Op.getSimpleValueType();
13458 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13459 return LowerUINT_TO_FP_i64(Op, DAG);
13460 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13461 return LowerUINT_TO_FP_i32(Op, DAG);
13462 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13465 // Make a 64-bit buffer, and use it to build an FILD.
13466 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13467 if (SrcVT == MVT::i32) {
13468 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13469 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13470 getPointerTy(), StackSlot, WordOff);
13471 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13472 StackSlot, MachinePointerInfo(),
13474 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13475 OffsetSlot, MachinePointerInfo(),
13477 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13481 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13482 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13483 StackSlot, MachinePointerInfo(),
13485 // For i64 source, we need to add the appropriate power of 2 if the input
13486 // was negative. This is the same as the optimization in
13487 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13488 // we must be careful to do the computation in x87 extended precision, not
13489 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13490 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13491 MachineMemOperand *MMO =
13492 DAG.getMachineFunction()
13493 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13494 MachineMemOperand::MOLoad, 8, 8);
13496 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13497 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13498 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13501 APInt FF(32, 0x5F800000ULL);
13503 // Check whether the sign bit is set.
13504 SDValue SignSet = DAG.getSetCC(dl,
13505 getSetCCResultType(*DAG.getContext(), MVT::i64),
13506 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13509 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13510 SDValue FudgePtr = DAG.getConstantPool(
13511 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13514 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13515 SDValue Zero = DAG.getIntPtrConstant(0);
13516 SDValue Four = DAG.getIntPtrConstant(4);
13517 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13519 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13521 // Load the value out, extending it from f32 to f80.
13522 // FIXME: Avoid the extend by constructing the right constant pool?
13523 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13524 FudgePtr, MachinePointerInfo::getConstantPool(),
13525 MVT::f32, false, false, false, 4);
13526 // Extend everything to 80 bits to force it to be done on x87.
13527 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13528 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13531 std::pair<SDValue,SDValue>
13532 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13533 bool IsSigned, bool IsReplace) const {
13536 EVT DstTy = Op.getValueType();
13538 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13539 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13543 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13544 DstTy.getSimpleVT() >= MVT::i16 &&
13545 "Unknown FP_TO_INT to lower!");
13547 // These are really Legal.
13548 if (DstTy == MVT::i32 &&
13549 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13550 return std::make_pair(SDValue(), SDValue());
13551 if (Subtarget->is64Bit() &&
13552 DstTy == MVT::i64 &&
13553 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13554 return std::make_pair(SDValue(), SDValue());
13556 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13557 // stack slot, or into the FTOL runtime function.
13558 MachineFunction &MF = DAG.getMachineFunction();
13559 unsigned MemSize = DstTy.getSizeInBits()/8;
13560 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13561 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13564 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13565 Opc = X86ISD::WIN_FTOL;
13567 switch (DstTy.getSimpleVT().SimpleTy) {
13568 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13569 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13570 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13571 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13574 SDValue Chain = DAG.getEntryNode();
13575 SDValue Value = Op.getOperand(0);
13576 EVT TheVT = Op.getOperand(0).getValueType();
13577 // FIXME This causes a redundant load/store if the SSE-class value is already
13578 // in memory, such as if it is on the callstack.
13579 if (isScalarFPTypeInSSEReg(TheVT)) {
13580 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13581 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13582 MachinePointerInfo::getFixedStack(SSFI),
13584 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13586 Chain, StackSlot, DAG.getValueType(TheVT)
13589 MachineMemOperand *MMO =
13590 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13591 MachineMemOperand::MOLoad, MemSize, MemSize);
13592 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13593 Chain = Value.getValue(1);
13594 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13595 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13598 MachineMemOperand *MMO =
13599 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13600 MachineMemOperand::MOStore, MemSize, MemSize);
13602 if (Opc != X86ISD::WIN_FTOL) {
13603 // Build the FP_TO_INT*_IN_MEM
13604 SDValue Ops[] = { Chain, Value, StackSlot };
13605 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13607 return std::make_pair(FIST, StackSlot);
13609 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13610 DAG.getVTList(MVT::Other, MVT::Glue),
13612 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13613 MVT::i32, ftol.getValue(1));
13614 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13615 MVT::i32, eax.getValue(2));
13616 SDValue Ops[] = { eax, edx };
13617 SDValue pair = IsReplace
13618 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13619 : DAG.getMergeValues(Ops, DL);
13620 return std::make_pair(pair, SDValue());
13624 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13625 const X86Subtarget *Subtarget) {
13626 MVT VT = Op->getSimpleValueType(0);
13627 SDValue In = Op->getOperand(0);
13628 MVT InVT = In.getSimpleValueType();
13631 // Optimize vectors in AVX mode:
13634 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13635 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13636 // Concat upper and lower parts.
13639 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13640 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13641 // Concat upper and lower parts.
13644 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13645 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13646 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13649 if (Subtarget->hasInt256())
13650 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13652 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13653 SDValue Undef = DAG.getUNDEF(InVT);
13654 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13655 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13656 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13658 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13659 VT.getVectorNumElements()/2);
13661 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13662 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13664 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13667 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13668 SelectionDAG &DAG) {
13669 MVT VT = Op->getSimpleValueType(0);
13670 SDValue In = Op->getOperand(0);
13671 MVT InVT = In.getSimpleValueType();
13673 unsigned int NumElts = VT.getVectorNumElements();
13674 if (NumElts != 8 && NumElts != 16)
13677 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13678 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13680 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13682 // Now we have only mask extension
13683 assert(InVT.getVectorElementType() == MVT::i1);
13684 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13685 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13686 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13687 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13688 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13689 MachinePointerInfo::getConstantPool(),
13690 false, false, false, Alignment);
13692 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13693 if (VT.is512BitVector())
13695 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13698 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13699 SelectionDAG &DAG) {
13700 if (Subtarget->hasFp256()) {
13701 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13709 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13710 SelectionDAG &DAG) {
13712 MVT VT = Op.getSimpleValueType();
13713 SDValue In = Op.getOperand(0);
13714 MVT SVT = In.getSimpleValueType();
13716 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13717 return LowerZERO_EXTEND_AVX512(Op, DAG);
13719 if (Subtarget->hasFp256()) {
13720 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13725 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13726 VT.getVectorNumElements() != SVT.getVectorNumElements());
13730 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13732 MVT VT = Op.getSimpleValueType();
13733 SDValue In = Op.getOperand(0);
13734 MVT InVT = In.getSimpleValueType();
13736 if (VT == MVT::i1) {
13737 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13738 "Invalid scalar TRUNCATE operation");
13739 if (InVT.getSizeInBits() >= 32)
13741 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13742 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13744 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13745 "Invalid TRUNCATE operation");
13747 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13748 if (VT.getVectorElementType().getSizeInBits() >=8)
13749 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13751 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13752 unsigned NumElts = InVT.getVectorNumElements();
13753 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13754 if (InVT.getSizeInBits() < 512) {
13755 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13756 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13760 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13761 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13762 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13763 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13764 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13765 MachinePointerInfo::getConstantPool(),
13766 false, false, false, Alignment);
13767 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13768 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13769 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13772 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13773 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13774 if (Subtarget->hasInt256()) {
13775 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13776 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13777 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13779 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13780 DAG.getIntPtrConstant(0));
13783 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13784 DAG.getIntPtrConstant(0));
13785 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13786 DAG.getIntPtrConstant(2));
13787 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13788 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13789 static const int ShufMask[] = {0, 2, 4, 6};
13790 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13793 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13794 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13795 if (Subtarget->hasInt256()) {
13796 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13798 SmallVector<SDValue,32> pshufbMask;
13799 for (unsigned i = 0; i < 2; ++i) {
13800 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13801 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13802 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13803 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13804 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13805 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13806 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13807 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13808 for (unsigned j = 0; j < 8; ++j)
13809 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13811 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13812 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13813 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13815 static const int ShufMask[] = {0, 2, -1, -1};
13816 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13818 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13819 DAG.getIntPtrConstant(0));
13820 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13823 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13824 DAG.getIntPtrConstant(0));
13826 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13827 DAG.getIntPtrConstant(4));
13829 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13830 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13832 // The PSHUFB mask:
13833 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13834 -1, -1, -1, -1, -1, -1, -1, -1};
13836 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13837 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13838 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13840 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13841 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13843 // The MOVLHPS Mask:
13844 static const int ShufMask2[] = {0, 1, 4, 5};
13845 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13846 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13849 // Handle truncation of V256 to V128 using shuffles.
13850 if (!VT.is128BitVector() || !InVT.is256BitVector())
13853 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13855 unsigned NumElems = VT.getVectorNumElements();
13856 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13858 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13859 // Prepare truncation shuffle mask
13860 for (unsigned i = 0; i != NumElems; ++i)
13861 MaskVec[i] = i * 2;
13862 SDValue V = DAG.getVectorShuffle(NVT, DL,
13863 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13864 DAG.getUNDEF(NVT), &MaskVec[0]);
13865 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13866 DAG.getIntPtrConstant(0));
13869 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13870 SelectionDAG &DAG) const {
13871 assert(!Op.getSimpleValueType().isVector());
13873 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13874 /*IsSigned=*/ true, /*IsReplace=*/ false);
13875 SDValue FIST = Vals.first, StackSlot = Vals.second;
13876 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13877 if (!FIST.getNode()) return Op;
13879 if (StackSlot.getNode())
13880 // Load the result.
13881 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13882 FIST, StackSlot, MachinePointerInfo(),
13883 false, false, false, 0);
13885 // The node is the result.
13889 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13890 SelectionDAG &DAG) const {
13891 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13892 /*IsSigned=*/ false, /*IsReplace=*/ false);
13893 SDValue FIST = Vals.first, StackSlot = Vals.second;
13894 assert(FIST.getNode() && "Unexpected failure");
13896 if (StackSlot.getNode())
13897 // Load the result.
13898 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13899 FIST, StackSlot, MachinePointerInfo(),
13900 false, false, false, 0);
13902 // The node is the result.
13906 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13908 MVT VT = Op.getSimpleValueType();
13909 SDValue In = Op.getOperand(0);
13910 MVT SVT = In.getSimpleValueType();
13912 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13914 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13915 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13916 In, DAG.getUNDEF(SVT)));
13919 /// The only differences between FABS and FNEG are the mask and the logic op.
13920 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13921 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13922 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13923 "Wrong opcode for lowering FABS or FNEG.");
13925 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13927 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13928 // into an FNABS. We'll lower the FABS after that if it is still in use.
13930 for (SDNode *User : Op->uses())
13931 if (User->getOpcode() == ISD::FNEG)
13934 SDValue Op0 = Op.getOperand(0);
13935 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13938 MVT VT = Op.getSimpleValueType();
13939 // Assume scalar op for initialization; update for vector if needed.
13940 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13941 // generate a 16-byte vector constant and logic op even for the scalar case.
13942 // Using a 16-byte mask allows folding the load of the mask with
13943 // the logic op, so it can save (~4 bytes) on code size.
13945 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13946 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13947 // decide if we should generate a 16-byte constant mask when we only need 4 or
13948 // 8 bytes for the scalar case.
13949 if (VT.isVector()) {
13950 EltVT = VT.getVectorElementType();
13951 NumElts = VT.getVectorNumElements();
13954 unsigned EltBits = EltVT.getSizeInBits();
13955 LLVMContext *Context = DAG.getContext();
13956 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13958 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13959 Constant *C = ConstantInt::get(*Context, MaskElt);
13960 C = ConstantVector::getSplat(NumElts, C);
13961 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13962 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13963 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13964 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13965 MachinePointerInfo::getConstantPool(),
13966 false, false, false, Alignment);
13968 if (VT.isVector()) {
13969 // For a vector, cast operands to a vector type, perform the logic op,
13970 // and cast the result back to the original value type.
13971 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13972 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13973 SDValue Operand = IsFNABS ?
13974 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
13975 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
13976 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
13977 return DAG.getNode(ISD::BITCAST, dl, VT,
13978 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
13981 // If not vector, then scalar.
13982 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13983 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13984 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
13987 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13988 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13989 LLVMContext *Context = DAG.getContext();
13990 SDValue Op0 = Op.getOperand(0);
13991 SDValue Op1 = Op.getOperand(1);
13993 MVT VT = Op.getSimpleValueType();
13994 MVT SrcVT = Op1.getSimpleValueType();
13996 // If second operand is smaller, extend it first.
13997 if (SrcVT.bitsLT(VT)) {
13998 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14001 // And if it is bigger, shrink it first.
14002 if (SrcVT.bitsGT(VT)) {
14003 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14007 // At this point the operands and the result should have the same
14008 // type, and that won't be f80 since that is not custom lowered.
14010 // First get the sign bit of second operand.
14011 SmallVector<Constant*,4> CV;
14012 if (SrcVT == MVT::f64) {
14013 const fltSemantics &Sem = APFloat::IEEEdouble;
14014 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14015 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14017 const fltSemantics &Sem = APFloat::IEEEsingle;
14018 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14019 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14020 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14021 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14023 Constant *C = ConstantVector::get(CV);
14024 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14025 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14026 MachinePointerInfo::getConstantPool(),
14027 false, false, false, 16);
14028 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14030 // Shift sign bit right or left if the two operands have different types.
14031 if (SrcVT.bitsGT(VT)) {
14032 // Op0 is MVT::f32, Op1 is MVT::f64.
14033 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14034 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14035 DAG.getConstant(32, MVT::i32));
14036 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14037 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14038 DAG.getIntPtrConstant(0));
14041 // Clear first operand sign bit.
14043 if (VT == MVT::f64) {
14044 const fltSemantics &Sem = APFloat::IEEEdouble;
14045 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14046 APInt(64, ~(1ULL << 63)))));
14047 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14049 const fltSemantics &Sem = APFloat::IEEEsingle;
14050 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14051 APInt(32, ~(1U << 31)))));
14052 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14053 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14054 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14056 C = ConstantVector::get(CV);
14057 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14058 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14059 MachinePointerInfo::getConstantPool(),
14060 false, false, false, 16);
14061 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14063 // Or the value with the sign bit.
14064 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14067 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14068 SDValue N0 = Op.getOperand(0);
14070 MVT VT = Op.getSimpleValueType();
14072 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14073 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14074 DAG.getConstant(1, VT));
14075 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14078 // Check whether an OR'd tree is PTEST-able.
14079 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14080 SelectionDAG &DAG) {
14081 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14083 if (!Subtarget->hasSSE41())
14086 if (!Op->hasOneUse())
14089 SDNode *N = Op.getNode();
14092 SmallVector<SDValue, 8> Opnds;
14093 DenseMap<SDValue, unsigned> VecInMap;
14094 SmallVector<SDValue, 8> VecIns;
14095 EVT VT = MVT::Other;
14097 // Recognize a special case where a vector is casted into wide integer to
14099 Opnds.push_back(N->getOperand(0));
14100 Opnds.push_back(N->getOperand(1));
14102 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14103 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14104 // BFS traverse all OR'd operands.
14105 if (I->getOpcode() == ISD::OR) {
14106 Opnds.push_back(I->getOperand(0));
14107 Opnds.push_back(I->getOperand(1));
14108 // Re-evaluate the number of nodes to be traversed.
14109 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14113 // Quit if a non-EXTRACT_VECTOR_ELT
14114 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14117 // Quit if without a constant index.
14118 SDValue Idx = I->getOperand(1);
14119 if (!isa<ConstantSDNode>(Idx))
14122 SDValue ExtractedFromVec = I->getOperand(0);
14123 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14124 if (M == VecInMap.end()) {
14125 VT = ExtractedFromVec.getValueType();
14126 // Quit if not 128/256-bit vector.
14127 if (!VT.is128BitVector() && !VT.is256BitVector())
14129 // Quit if not the same type.
14130 if (VecInMap.begin() != VecInMap.end() &&
14131 VT != VecInMap.begin()->first.getValueType())
14133 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14134 VecIns.push_back(ExtractedFromVec);
14136 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14139 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14140 "Not extracted from 128-/256-bit vector.");
14142 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14144 for (DenseMap<SDValue, unsigned>::const_iterator
14145 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14146 // Quit if not all elements are used.
14147 if (I->second != FullMask)
14151 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14153 // Cast all vectors into TestVT for PTEST.
14154 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14155 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14157 // If more than one full vectors are evaluated, OR them first before PTEST.
14158 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14159 // Each iteration will OR 2 nodes and append the result until there is only
14160 // 1 node left, i.e. the final OR'd value of all vectors.
14161 SDValue LHS = VecIns[Slot];
14162 SDValue RHS = VecIns[Slot + 1];
14163 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14166 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14167 VecIns.back(), VecIns.back());
14170 /// \brief return true if \c Op has a use that doesn't just read flags.
14171 static bool hasNonFlagsUse(SDValue Op) {
14172 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14174 SDNode *User = *UI;
14175 unsigned UOpNo = UI.getOperandNo();
14176 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14177 // Look pass truncate.
14178 UOpNo = User->use_begin().getOperandNo();
14179 User = *User->use_begin();
14182 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14183 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14189 /// Emit nodes that will be selected as "test Op0,Op0", or something
14191 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14192 SelectionDAG &DAG) const {
14193 if (Op.getValueType() == MVT::i1)
14194 // KORTEST instruction should be selected
14195 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14196 DAG.getConstant(0, Op.getValueType()));
14198 // CF and OF aren't always set the way we want. Determine which
14199 // of these we need.
14200 bool NeedCF = false;
14201 bool NeedOF = false;
14204 case X86::COND_A: case X86::COND_AE:
14205 case X86::COND_B: case X86::COND_BE:
14208 case X86::COND_G: case X86::COND_GE:
14209 case X86::COND_L: case X86::COND_LE:
14210 case X86::COND_O: case X86::COND_NO: {
14211 // Check if we really need to set the
14212 // Overflow flag. If NoSignedWrap is present
14213 // that is not actually needed.
14214 switch (Op->getOpcode()) {
14219 const BinaryWithFlagsSDNode *BinNode =
14220 cast<BinaryWithFlagsSDNode>(Op.getNode());
14221 if (BinNode->hasNoSignedWrap())
14231 // See if we can use the EFLAGS value from the operand instead of
14232 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14233 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14234 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14235 // Emit a CMP with 0, which is the TEST pattern.
14236 //if (Op.getValueType() == MVT::i1)
14237 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14238 // DAG.getConstant(0, MVT::i1));
14239 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14240 DAG.getConstant(0, Op.getValueType()));
14242 unsigned Opcode = 0;
14243 unsigned NumOperands = 0;
14245 // Truncate operations may prevent the merge of the SETCC instruction
14246 // and the arithmetic instruction before it. Attempt to truncate the operands
14247 // of the arithmetic instruction and use a reduced bit-width instruction.
14248 bool NeedTruncation = false;
14249 SDValue ArithOp = Op;
14250 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14251 SDValue Arith = Op->getOperand(0);
14252 // Both the trunc and the arithmetic op need to have one user each.
14253 if (Arith->hasOneUse())
14254 switch (Arith.getOpcode()) {
14261 NeedTruncation = true;
14267 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14268 // which may be the result of a CAST. We use the variable 'Op', which is the
14269 // non-casted variable when we check for possible users.
14270 switch (ArithOp.getOpcode()) {
14272 // Due to an isel shortcoming, be conservative if this add is likely to be
14273 // selected as part of a load-modify-store instruction. When the root node
14274 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14275 // uses of other nodes in the match, such as the ADD in this case. This
14276 // leads to the ADD being left around and reselected, with the result being
14277 // two adds in the output. Alas, even if none our users are stores, that
14278 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14279 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14280 // climbing the DAG back to the root, and it doesn't seem to be worth the
14282 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14283 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14284 if (UI->getOpcode() != ISD::CopyToReg &&
14285 UI->getOpcode() != ISD::SETCC &&
14286 UI->getOpcode() != ISD::STORE)
14289 if (ConstantSDNode *C =
14290 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14291 // An add of one will be selected as an INC.
14292 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14293 Opcode = X86ISD::INC;
14298 // An add of negative one (subtract of one) will be selected as a DEC.
14299 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14300 Opcode = X86ISD::DEC;
14306 // Otherwise use a regular EFLAGS-setting add.
14307 Opcode = X86ISD::ADD;
14312 // If we have a constant logical shift that's only used in a comparison
14313 // against zero turn it into an equivalent AND. This allows turning it into
14314 // a TEST instruction later.
14315 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14316 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14317 EVT VT = Op.getValueType();
14318 unsigned BitWidth = VT.getSizeInBits();
14319 unsigned ShAmt = Op->getConstantOperandVal(1);
14320 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14322 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14323 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14324 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14325 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14327 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14328 DAG.getConstant(Mask, VT));
14329 DAG.ReplaceAllUsesWith(Op, New);
14335 // If the primary and result isn't used, don't bother using X86ISD::AND,
14336 // because a TEST instruction will be better.
14337 if (!hasNonFlagsUse(Op))
14343 // Due to the ISEL shortcoming noted above, be conservative if this op is
14344 // likely to be selected as part of a load-modify-store instruction.
14345 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14346 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14347 if (UI->getOpcode() == ISD::STORE)
14350 // Otherwise use a regular EFLAGS-setting instruction.
14351 switch (ArithOp.getOpcode()) {
14352 default: llvm_unreachable("unexpected operator!");
14353 case ISD::SUB: Opcode = X86ISD::SUB; break;
14354 case ISD::XOR: Opcode = X86ISD::XOR; break;
14355 case ISD::AND: Opcode = X86ISD::AND; break;
14357 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14358 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14359 if (EFLAGS.getNode())
14362 Opcode = X86ISD::OR;
14376 return SDValue(Op.getNode(), 1);
14382 // If we found that truncation is beneficial, perform the truncation and
14384 if (NeedTruncation) {
14385 EVT VT = Op.getValueType();
14386 SDValue WideVal = Op->getOperand(0);
14387 EVT WideVT = WideVal.getValueType();
14388 unsigned ConvertedOp = 0;
14389 // Use a target machine opcode to prevent further DAGCombine
14390 // optimizations that may separate the arithmetic operations
14391 // from the setcc node.
14392 switch (WideVal.getOpcode()) {
14394 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14395 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14396 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14397 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14398 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14403 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14404 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14405 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14406 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14412 // Emit a CMP with 0, which is the TEST pattern.
14413 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14414 DAG.getConstant(0, Op.getValueType()));
14416 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14417 SmallVector<SDValue, 4> Ops;
14418 for (unsigned i = 0; i != NumOperands; ++i)
14419 Ops.push_back(Op.getOperand(i));
14421 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14422 DAG.ReplaceAllUsesWith(Op, New);
14423 return SDValue(New.getNode(), 1);
14426 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14428 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14429 SDLoc dl, SelectionDAG &DAG) const {
14430 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14431 if (C->getAPIntValue() == 0)
14432 return EmitTest(Op0, X86CC, dl, DAG);
14434 if (Op0.getValueType() == MVT::i1)
14435 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14438 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14439 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14440 // Do the comparison at i32 if it's smaller, besides the Atom case.
14441 // This avoids subregister aliasing issues. Keep the smaller reference
14442 // if we're optimizing for size, however, as that'll allow better folding
14443 // of memory operations.
14444 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14445 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14446 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14447 !Subtarget->isAtom()) {
14448 unsigned ExtendOp =
14449 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14450 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14451 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14453 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14454 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14455 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14457 return SDValue(Sub.getNode(), 1);
14459 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14462 /// Convert a comparison if required by the subtarget.
14463 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14464 SelectionDAG &DAG) const {
14465 // If the subtarget does not support the FUCOMI instruction, floating-point
14466 // comparisons have to be converted.
14467 if (Subtarget->hasCMov() ||
14468 Cmp.getOpcode() != X86ISD::CMP ||
14469 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14470 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14473 // The instruction selector will select an FUCOM instruction instead of
14474 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14475 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14476 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14478 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14479 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14480 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14481 DAG.getConstant(8, MVT::i8));
14482 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14483 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14486 /// The minimum architected relative accuracy is 2^-12. We need one
14487 /// Newton-Raphson step to have a good float result (24 bits of precision).
14488 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14489 DAGCombinerInfo &DCI,
14490 unsigned &RefinementSteps,
14491 bool &UseOneConstNR) const {
14492 // FIXME: We should use instruction latency models to calculate the cost of
14493 // each potential sequence, but this is very hard to do reliably because
14494 // at least Intel's Core* chips have variable timing based on the number of
14495 // significant digits in the divisor and/or sqrt operand.
14496 if (!Subtarget->useSqrtEst())
14499 EVT VT = Op.getValueType();
14501 // SSE1 has rsqrtss and rsqrtps.
14502 // TODO: Add support for AVX512 (v16f32).
14503 // It is likely not profitable to do this for f64 because a double-precision
14504 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14505 // instructions: convert to single, rsqrtss, convert back to double, refine
14506 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14507 // along with FMA, this could be a throughput win.
14508 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14509 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14510 RefinementSteps = 1;
14511 UseOneConstNR = false;
14512 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14517 /// The minimum architected relative accuracy is 2^-12. We need one
14518 /// Newton-Raphson step to have a good float result (24 bits of precision).
14519 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14520 DAGCombinerInfo &DCI,
14521 unsigned &RefinementSteps) const {
14522 // FIXME: We should use instruction latency models to calculate the cost of
14523 // each potential sequence, but this is very hard to do reliably because
14524 // at least Intel's Core* chips have variable timing based on the number of
14525 // significant digits in the divisor.
14526 if (!Subtarget->useReciprocalEst())
14529 EVT VT = Op.getValueType();
14531 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14532 // TODO: Add support for AVX512 (v16f32).
14533 // It is likely not profitable to do this for f64 because a double-precision
14534 // reciprocal estimate with refinement on x86 prior to FMA requires
14535 // 15 instructions: convert to single, rcpss, convert back to double, refine
14536 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14537 // along with FMA, this could be a throughput win.
14538 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14539 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14540 // TODO: Expose this as a user-configurable parameter to allow for
14541 // speed vs. accuracy flexibility.
14542 RefinementSteps = 1;
14543 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14548 static bool isAllOnes(SDValue V) {
14549 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14550 return C && C->isAllOnesValue();
14553 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14554 /// if it's possible.
14555 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14556 SDLoc dl, SelectionDAG &DAG) const {
14557 SDValue Op0 = And.getOperand(0);
14558 SDValue Op1 = And.getOperand(1);
14559 if (Op0.getOpcode() == ISD::TRUNCATE)
14560 Op0 = Op0.getOperand(0);
14561 if (Op1.getOpcode() == ISD::TRUNCATE)
14562 Op1 = Op1.getOperand(0);
14565 if (Op1.getOpcode() == ISD::SHL)
14566 std::swap(Op0, Op1);
14567 if (Op0.getOpcode() == ISD::SHL) {
14568 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14569 if (And00C->getZExtValue() == 1) {
14570 // If we looked past a truncate, check that it's only truncating away
14572 unsigned BitWidth = Op0.getValueSizeInBits();
14573 unsigned AndBitWidth = And.getValueSizeInBits();
14574 if (BitWidth > AndBitWidth) {
14576 DAG.computeKnownBits(Op0, Zeros, Ones);
14577 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14581 RHS = Op0.getOperand(1);
14583 } else if (Op1.getOpcode() == ISD::Constant) {
14584 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14585 uint64_t AndRHSVal = AndRHS->getZExtValue();
14586 SDValue AndLHS = Op0;
14588 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14589 LHS = AndLHS.getOperand(0);
14590 RHS = AndLHS.getOperand(1);
14593 // Use BT if the immediate can't be encoded in a TEST instruction.
14594 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14596 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14600 if (LHS.getNode()) {
14601 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14602 // instruction. Since the shift amount is in-range-or-undefined, we know
14603 // that doing a bittest on the i32 value is ok. We extend to i32 because
14604 // the encoding for the i16 version is larger than the i32 version.
14605 // Also promote i16 to i32 for performance / code size reason.
14606 if (LHS.getValueType() == MVT::i8 ||
14607 LHS.getValueType() == MVT::i16)
14608 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14610 // If the operand types disagree, extend the shift amount to match. Since
14611 // BT ignores high bits (like shifts) we can use anyextend.
14612 if (LHS.getValueType() != RHS.getValueType())
14613 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14615 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14616 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14617 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14618 DAG.getConstant(Cond, MVT::i8), BT);
14624 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14626 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14631 // SSE Condition code mapping:
14640 switch (SetCCOpcode) {
14641 default: llvm_unreachable("Unexpected SETCC condition");
14643 case ISD::SETEQ: SSECC = 0; break;
14645 case ISD::SETGT: Swap = true; // Fallthrough
14647 case ISD::SETOLT: SSECC = 1; break;
14649 case ISD::SETGE: Swap = true; // Fallthrough
14651 case ISD::SETOLE: SSECC = 2; break;
14652 case ISD::SETUO: SSECC = 3; break;
14654 case ISD::SETNE: SSECC = 4; break;
14655 case ISD::SETULE: Swap = true; // Fallthrough
14656 case ISD::SETUGE: SSECC = 5; break;
14657 case ISD::SETULT: Swap = true; // Fallthrough
14658 case ISD::SETUGT: SSECC = 6; break;
14659 case ISD::SETO: SSECC = 7; break;
14661 case ISD::SETONE: SSECC = 8; break;
14664 std::swap(Op0, Op1);
14669 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14670 // ones, and then concatenate the result back.
14671 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14672 MVT VT = Op.getSimpleValueType();
14674 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14675 "Unsupported value type for operation");
14677 unsigned NumElems = VT.getVectorNumElements();
14679 SDValue CC = Op.getOperand(2);
14681 // Extract the LHS vectors
14682 SDValue LHS = Op.getOperand(0);
14683 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14684 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14686 // Extract the RHS vectors
14687 SDValue RHS = Op.getOperand(1);
14688 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14689 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14691 // Issue the operation on the smaller types and concatenate the result back
14692 MVT EltVT = VT.getVectorElementType();
14693 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14694 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14695 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14696 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14699 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14700 const X86Subtarget *Subtarget) {
14701 SDValue Op0 = Op.getOperand(0);
14702 SDValue Op1 = Op.getOperand(1);
14703 SDValue CC = Op.getOperand(2);
14704 MVT VT = Op.getSimpleValueType();
14707 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14708 Op.getValueType().getScalarType() == MVT::i1 &&
14709 "Cannot set masked compare for this operation");
14711 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14713 bool Unsigned = false;
14716 switch (SetCCOpcode) {
14717 default: llvm_unreachable("Unexpected SETCC condition");
14718 case ISD::SETNE: SSECC = 4; break;
14719 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14720 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14721 case ISD::SETLT: Swap = true; //fall-through
14722 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14723 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14724 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14725 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14726 case ISD::SETULE: Unsigned = true; //fall-through
14727 case ISD::SETLE: SSECC = 2; break;
14731 std::swap(Op0, Op1);
14733 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14734 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14735 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14736 DAG.getConstant(SSECC, MVT::i8));
14739 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14740 /// operand \p Op1. If non-trivial (for example because it's not constant)
14741 /// return an empty value.
14742 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14744 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14748 MVT VT = Op1.getSimpleValueType();
14749 MVT EVT = VT.getVectorElementType();
14750 unsigned n = VT.getVectorNumElements();
14751 SmallVector<SDValue, 8> ULTOp1;
14753 for (unsigned i = 0; i < n; ++i) {
14754 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14755 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14758 // Avoid underflow.
14759 APInt Val = Elt->getAPIntValue();
14763 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14766 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14769 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14770 SelectionDAG &DAG) {
14771 SDValue Op0 = Op.getOperand(0);
14772 SDValue Op1 = Op.getOperand(1);
14773 SDValue CC = Op.getOperand(2);
14774 MVT VT = Op.getSimpleValueType();
14775 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14776 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14781 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14782 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14785 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14786 unsigned Opc = X86ISD::CMPP;
14787 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14788 assert(VT.getVectorNumElements() <= 16);
14789 Opc = X86ISD::CMPM;
14791 // In the two special cases we can't handle, emit two comparisons.
14794 unsigned CombineOpc;
14795 if (SetCCOpcode == ISD::SETUEQ) {
14796 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14798 assert(SetCCOpcode == ISD::SETONE);
14799 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14802 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14803 DAG.getConstant(CC0, MVT::i8));
14804 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14805 DAG.getConstant(CC1, MVT::i8));
14806 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14808 // Handle all other FP comparisons here.
14809 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14810 DAG.getConstant(SSECC, MVT::i8));
14813 // Break 256-bit integer vector compare into smaller ones.
14814 if (VT.is256BitVector() && !Subtarget->hasInt256())
14815 return Lower256IntVSETCC(Op, DAG);
14817 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14818 EVT OpVT = Op1.getValueType();
14819 if (Subtarget->hasAVX512()) {
14820 if (Op1.getValueType().is512BitVector() ||
14821 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14822 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14823 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14825 // In AVX-512 architecture setcc returns mask with i1 elements,
14826 // But there is no compare instruction for i8 and i16 elements in KNL.
14827 // We are not talking about 512-bit operands in this case, these
14828 // types are illegal.
14830 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14831 OpVT.getVectorElementType().getSizeInBits() >= 8))
14832 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14833 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14836 // We are handling one of the integer comparisons here. Since SSE only has
14837 // GT and EQ comparisons for integer, swapping operands and multiple
14838 // operations may be required for some comparisons.
14840 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14841 bool Subus = false;
14843 switch (SetCCOpcode) {
14844 default: llvm_unreachable("Unexpected SETCC condition");
14845 case ISD::SETNE: Invert = true;
14846 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14847 case ISD::SETLT: Swap = true;
14848 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14849 case ISD::SETGE: Swap = true;
14850 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14851 Invert = true; break;
14852 case ISD::SETULT: Swap = true;
14853 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14854 FlipSigns = true; break;
14855 case ISD::SETUGE: Swap = true;
14856 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14857 FlipSigns = true; Invert = true; break;
14860 // Special case: Use min/max operations for SETULE/SETUGE
14861 MVT VET = VT.getVectorElementType();
14863 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14864 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14867 switch (SetCCOpcode) {
14869 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14870 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14873 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14876 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14877 if (!MinMax && hasSubus) {
14878 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14880 // t = psubus Op0, Op1
14881 // pcmpeq t, <0..0>
14882 switch (SetCCOpcode) {
14884 case ISD::SETULT: {
14885 // If the comparison is against a constant we can turn this into a
14886 // setule. With psubus, setule does not require a swap. This is
14887 // beneficial because the constant in the register is no longer
14888 // destructed as the destination so it can be hoisted out of a loop.
14889 // Only do this pre-AVX since vpcmp* is no longer destructive.
14890 if (Subtarget->hasAVX())
14892 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14893 if (ULEOp1.getNode()) {
14895 Subus = true; Invert = false; Swap = false;
14899 // Psubus is better than flip-sign because it requires no inversion.
14900 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14901 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14905 Opc = X86ISD::SUBUS;
14911 std::swap(Op0, Op1);
14913 // Check that the operation in question is available (most are plain SSE2,
14914 // but PCMPGTQ and PCMPEQQ have different requirements).
14915 if (VT == MVT::v2i64) {
14916 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14917 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14919 // First cast everything to the right type.
14920 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14921 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14923 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14924 // bits of the inputs before performing those operations. The lower
14925 // compare is always unsigned.
14928 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14930 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14931 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14932 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14933 Sign, Zero, Sign, Zero);
14935 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14936 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14938 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14939 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14940 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14942 // Create masks for only the low parts/high parts of the 64 bit integers.
14943 static const int MaskHi[] = { 1, 1, 3, 3 };
14944 static const int MaskLo[] = { 0, 0, 2, 2 };
14945 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14946 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14947 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14949 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14950 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14953 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14955 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14958 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14959 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14960 // pcmpeqd + pshufd + pand.
14961 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14963 // First cast everything to the right type.
14964 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14965 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14968 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14970 // Make sure the lower and upper halves are both all-ones.
14971 static const int Mask[] = { 1, 0, 3, 2 };
14972 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14973 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14976 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14978 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14982 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14983 // bits of the inputs before performing those operations.
14985 EVT EltVT = VT.getVectorElementType();
14986 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14987 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14988 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14991 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14993 // If the logical-not of the result is required, perform that now.
14995 Result = DAG.getNOT(dl, Result, VT);
14998 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15001 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15002 getZeroVector(VT, Subtarget, DAG, dl));
15007 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15009 MVT VT = Op.getSimpleValueType();
15011 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15013 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15014 && "SetCC type must be 8-bit or 1-bit integer");
15015 SDValue Op0 = Op.getOperand(0);
15016 SDValue Op1 = Op.getOperand(1);
15018 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15020 // Optimize to BT if possible.
15021 // Lower (X & (1 << N)) == 0 to BT(X, N).
15022 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15023 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15024 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15025 Op1.getOpcode() == ISD::Constant &&
15026 cast<ConstantSDNode>(Op1)->isNullValue() &&
15027 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15028 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15029 if (NewSetCC.getNode())
15033 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15035 if (Op1.getOpcode() == ISD::Constant &&
15036 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15037 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15038 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15040 // If the input is a setcc, then reuse the input setcc or use a new one with
15041 // the inverted condition.
15042 if (Op0.getOpcode() == X86ISD::SETCC) {
15043 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15044 bool Invert = (CC == ISD::SETNE) ^
15045 cast<ConstantSDNode>(Op1)->isNullValue();
15049 CCode = X86::GetOppositeBranchCondition(CCode);
15050 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15051 DAG.getConstant(CCode, MVT::i8),
15052 Op0.getOperand(1));
15054 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15058 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15059 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15060 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15062 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15063 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15066 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15067 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15068 if (X86CC == X86::COND_INVALID)
15071 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15072 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15073 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15074 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15076 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15080 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15081 static bool isX86LogicalCmp(SDValue Op) {
15082 unsigned Opc = Op.getNode()->getOpcode();
15083 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15084 Opc == X86ISD::SAHF)
15086 if (Op.getResNo() == 1 &&
15087 (Opc == X86ISD::ADD ||
15088 Opc == X86ISD::SUB ||
15089 Opc == X86ISD::ADC ||
15090 Opc == X86ISD::SBB ||
15091 Opc == X86ISD::SMUL ||
15092 Opc == X86ISD::UMUL ||
15093 Opc == X86ISD::INC ||
15094 Opc == X86ISD::DEC ||
15095 Opc == X86ISD::OR ||
15096 Opc == X86ISD::XOR ||
15097 Opc == X86ISD::AND))
15100 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15106 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15107 if (V.getOpcode() != ISD::TRUNCATE)
15110 SDValue VOp0 = V.getOperand(0);
15111 unsigned InBits = VOp0.getValueSizeInBits();
15112 unsigned Bits = V.getValueSizeInBits();
15113 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15116 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15117 bool addTest = true;
15118 SDValue Cond = Op.getOperand(0);
15119 SDValue Op1 = Op.getOperand(1);
15120 SDValue Op2 = Op.getOperand(2);
15122 EVT VT = Op1.getValueType();
15125 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15126 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15127 // sequence later on.
15128 if (Cond.getOpcode() == ISD::SETCC &&
15129 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15130 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15131 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15132 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15133 int SSECC = translateX86FSETCC(
15134 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15137 if (Subtarget->hasAVX512()) {
15138 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15139 DAG.getConstant(SSECC, MVT::i8));
15140 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15142 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15143 DAG.getConstant(SSECC, MVT::i8));
15144 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15145 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15146 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15150 if (Cond.getOpcode() == ISD::SETCC) {
15151 SDValue NewCond = LowerSETCC(Cond, DAG);
15152 if (NewCond.getNode())
15156 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15157 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15158 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15159 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15160 if (Cond.getOpcode() == X86ISD::SETCC &&
15161 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15162 isZero(Cond.getOperand(1).getOperand(1))) {
15163 SDValue Cmp = Cond.getOperand(1);
15165 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15167 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15168 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15169 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15171 SDValue CmpOp0 = Cmp.getOperand(0);
15172 // Apply further optimizations for special cases
15173 // (select (x != 0), -1, 0) -> neg & sbb
15174 // (select (x == 0), 0, -1) -> neg & sbb
15175 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15176 if (YC->isNullValue() &&
15177 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15178 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15179 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15180 DAG.getConstant(0, CmpOp0.getValueType()),
15182 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15183 DAG.getConstant(X86::COND_B, MVT::i8),
15184 SDValue(Neg.getNode(), 1));
15188 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15189 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15190 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15192 SDValue Res = // Res = 0 or -1.
15193 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15194 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15196 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15197 Res = DAG.getNOT(DL, Res, Res.getValueType());
15199 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15200 if (!N2C || !N2C->isNullValue())
15201 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15206 // Look past (and (setcc_carry (cmp ...)), 1).
15207 if (Cond.getOpcode() == ISD::AND &&
15208 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15209 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15210 if (C && C->getAPIntValue() == 1)
15211 Cond = Cond.getOperand(0);
15214 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15215 // setting operand in place of the X86ISD::SETCC.
15216 unsigned CondOpcode = Cond.getOpcode();
15217 if (CondOpcode == X86ISD::SETCC ||
15218 CondOpcode == X86ISD::SETCC_CARRY) {
15219 CC = Cond.getOperand(0);
15221 SDValue Cmp = Cond.getOperand(1);
15222 unsigned Opc = Cmp.getOpcode();
15223 MVT VT = Op.getSimpleValueType();
15225 bool IllegalFPCMov = false;
15226 if (VT.isFloatingPoint() && !VT.isVector() &&
15227 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15228 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15230 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15231 Opc == X86ISD::BT) { // FIXME
15235 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15236 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15237 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15238 Cond.getOperand(0).getValueType() != MVT::i8)) {
15239 SDValue LHS = Cond.getOperand(0);
15240 SDValue RHS = Cond.getOperand(1);
15241 unsigned X86Opcode;
15244 switch (CondOpcode) {
15245 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15246 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15247 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15248 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15249 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15250 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15251 default: llvm_unreachable("unexpected overflowing operator");
15253 if (CondOpcode == ISD::UMULO)
15254 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15257 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15259 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15261 if (CondOpcode == ISD::UMULO)
15262 Cond = X86Op.getValue(2);
15264 Cond = X86Op.getValue(1);
15266 CC = DAG.getConstant(X86Cond, MVT::i8);
15271 // Look pass the truncate if the high bits are known zero.
15272 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15273 Cond = Cond.getOperand(0);
15275 // We know the result of AND is compared against zero. Try to match
15277 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15278 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15279 if (NewSetCC.getNode()) {
15280 CC = NewSetCC.getOperand(0);
15281 Cond = NewSetCC.getOperand(1);
15288 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15289 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15292 // a < b ? -1 : 0 -> RES = ~setcc_carry
15293 // a < b ? 0 : -1 -> RES = setcc_carry
15294 // a >= b ? -1 : 0 -> RES = setcc_carry
15295 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15296 if (Cond.getOpcode() == X86ISD::SUB) {
15297 Cond = ConvertCmpIfNecessary(Cond, DAG);
15298 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15300 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15301 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15302 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15303 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15304 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15305 return DAG.getNOT(DL, Res, Res.getValueType());
15310 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15311 // widen the cmov and push the truncate through. This avoids introducing a new
15312 // branch during isel and doesn't add any extensions.
15313 if (Op.getValueType() == MVT::i8 &&
15314 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15315 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15316 if (T1.getValueType() == T2.getValueType() &&
15317 // Blacklist CopyFromReg to avoid partial register stalls.
15318 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15319 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15320 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15321 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15325 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15326 // condition is true.
15327 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15328 SDValue Ops[] = { Op2, Op1, CC, Cond };
15329 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15332 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15333 SelectionDAG &DAG) {
15334 MVT VT = Op->getSimpleValueType(0);
15335 SDValue In = Op->getOperand(0);
15336 MVT InVT = In.getSimpleValueType();
15337 MVT VTElt = VT.getVectorElementType();
15338 MVT InVTElt = InVT.getVectorElementType();
15342 if ((InVTElt == MVT::i1) &&
15343 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15344 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15346 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15347 VTElt.getSizeInBits() <= 16)) ||
15349 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15350 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15352 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15353 VTElt.getSizeInBits() >= 32))))
15354 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15356 unsigned int NumElts = VT.getVectorNumElements();
15358 if (NumElts != 8 && NumElts != 16)
15361 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15362 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15364 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15365 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15367 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15368 Constant *C = ConstantInt::get(*DAG.getContext(),
15369 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15371 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15372 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15373 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15374 MachinePointerInfo::getConstantPool(),
15375 false, false, false, Alignment);
15376 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15377 if (VT.is512BitVector())
15379 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15382 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15383 SelectionDAG &DAG) {
15384 MVT VT = Op->getSimpleValueType(0);
15385 SDValue In = Op->getOperand(0);
15386 MVT InVT = In.getSimpleValueType();
15389 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15390 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15392 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15393 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15394 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15397 if (Subtarget->hasInt256())
15398 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15400 // Optimize vectors in AVX mode
15401 // Sign extend v8i16 to v8i32 and
15404 // Divide input vector into two parts
15405 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15406 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15407 // concat the vectors to original VT
15409 unsigned NumElems = InVT.getVectorNumElements();
15410 SDValue Undef = DAG.getUNDEF(InVT);
15412 SmallVector<int,8> ShufMask1(NumElems, -1);
15413 for (unsigned i = 0; i != NumElems/2; ++i)
15416 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15418 SmallVector<int,8> ShufMask2(NumElems, -1);
15419 for (unsigned i = 0; i != NumElems/2; ++i)
15420 ShufMask2[i] = i + NumElems/2;
15422 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15424 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15425 VT.getVectorNumElements()/2);
15427 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15428 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15430 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15433 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15434 // may emit an illegal shuffle but the expansion is still better than scalar
15435 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15436 // we'll emit a shuffle and a arithmetic shift.
15437 // TODO: It is possible to support ZExt by zeroing the undef values during
15438 // the shuffle phase or after the shuffle.
15439 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15440 SelectionDAG &DAG) {
15441 MVT RegVT = Op.getSimpleValueType();
15442 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15443 assert(RegVT.isInteger() &&
15444 "We only custom lower integer vector sext loads.");
15446 // Nothing useful we can do without SSE2 shuffles.
15447 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15449 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15451 EVT MemVT = Ld->getMemoryVT();
15452 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15453 unsigned RegSz = RegVT.getSizeInBits();
15455 ISD::LoadExtType Ext = Ld->getExtensionType();
15457 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15458 && "Only anyext and sext are currently implemented.");
15459 assert(MemVT != RegVT && "Cannot extend to the same type");
15460 assert(MemVT.isVector() && "Must load a vector from memory");
15462 unsigned NumElems = RegVT.getVectorNumElements();
15463 unsigned MemSz = MemVT.getSizeInBits();
15464 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15466 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15467 // The only way in which we have a legal 256-bit vector result but not the
15468 // integer 256-bit operations needed to directly lower a sextload is if we
15469 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15470 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15471 // correctly legalized. We do this late to allow the canonical form of
15472 // sextload to persist throughout the rest of the DAG combiner -- it wants
15473 // to fold together any extensions it can, and so will fuse a sign_extend
15474 // of an sextload into a sextload targeting a wider value.
15476 if (MemSz == 128) {
15477 // Just switch this to a normal load.
15478 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15479 "it must be a legal 128-bit vector "
15481 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15482 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15483 Ld->isInvariant(), Ld->getAlignment());
15485 assert(MemSz < 128 &&
15486 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15487 // Do an sext load to a 128-bit vector type. We want to use the same
15488 // number of elements, but elements half as wide. This will end up being
15489 // recursively lowered by this routine, but will succeed as we definitely
15490 // have all the necessary features if we're using AVX1.
15492 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15493 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15495 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15496 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15497 Ld->isNonTemporal(), Ld->isInvariant(),
15498 Ld->getAlignment());
15501 // Replace chain users with the new chain.
15502 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15503 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15505 // Finally, do a normal sign-extend to the desired register.
15506 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15509 // All sizes must be a power of two.
15510 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15511 "Non-power-of-two elements are not custom lowered!");
15513 // Attempt to load the original value using scalar loads.
15514 // Find the largest scalar type that divides the total loaded size.
15515 MVT SclrLoadTy = MVT::i8;
15516 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15517 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15518 MVT Tp = (MVT::SimpleValueType)tp;
15519 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15524 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15525 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15527 SclrLoadTy = MVT::f64;
15529 // Calculate the number of scalar loads that we need to perform
15530 // in order to load our vector from memory.
15531 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15533 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15534 "Can only lower sext loads with a single scalar load!");
15536 unsigned loadRegZize = RegSz;
15537 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15540 // Represent our vector as a sequence of elements which are the
15541 // largest scalar that we can load.
15542 EVT LoadUnitVecVT = EVT::getVectorVT(
15543 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15545 // Represent the data using the same element type that is stored in
15546 // memory. In practice, we ''widen'' MemVT.
15548 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15549 loadRegZize / MemVT.getScalarType().getSizeInBits());
15551 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15552 "Invalid vector type");
15554 // We can't shuffle using an illegal type.
15555 assert(TLI.isTypeLegal(WideVecVT) &&
15556 "We only lower types that form legal widened vector types");
15558 SmallVector<SDValue, 8> Chains;
15559 SDValue Ptr = Ld->getBasePtr();
15560 SDValue Increment =
15561 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15562 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15564 for (unsigned i = 0; i < NumLoads; ++i) {
15565 // Perform a single load.
15566 SDValue ScalarLoad =
15567 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15568 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15569 Ld->getAlignment());
15570 Chains.push_back(ScalarLoad.getValue(1));
15571 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15572 // another round of DAGCombining.
15574 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15576 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15577 ScalarLoad, DAG.getIntPtrConstant(i));
15579 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15582 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15584 // Bitcast the loaded value to a vector of the original element type, in
15585 // the size of the target vector type.
15586 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15587 unsigned SizeRatio = RegSz / MemSz;
15589 if (Ext == ISD::SEXTLOAD) {
15590 // If we have SSE4.1, we can directly emit a VSEXT node.
15591 if (Subtarget->hasSSE41()) {
15592 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15593 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15597 // Otherwise we'll shuffle the small elements in the high bits of the
15598 // larger type and perform an arithmetic shift. If the shift is not legal
15599 // it's better to scalarize.
15600 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15601 "We can't implement a sext load without an arithmetic right shift!");
15603 // Redistribute the loaded elements into the different locations.
15604 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15605 for (unsigned i = 0; i != NumElems; ++i)
15606 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15608 SDValue Shuff = DAG.getVectorShuffle(
15609 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15611 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15613 // Build the arithmetic shift.
15614 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15615 MemVT.getVectorElementType().getSizeInBits();
15617 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15619 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15623 // Redistribute the loaded elements into the different locations.
15624 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15625 for (unsigned i = 0; i != NumElems; ++i)
15626 ShuffleVec[i * SizeRatio] = i;
15628 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15629 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15631 // Bitcast to the requested type.
15632 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15633 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15637 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15638 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15639 // from the AND / OR.
15640 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15641 Opc = Op.getOpcode();
15642 if (Opc != ISD::OR && Opc != ISD::AND)
15644 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15645 Op.getOperand(0).hasOneUse() &&
15646 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15647 Op.getOperand(1).hasOneUse());
15650 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15651 // 1 and that the SETCC node has a single use.
15652 static bool isXor1OfSetCC(SDValue Op) {
15653 if (Op.getOpcode() != ISD::XOR)
15655 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15656 if (N1C && N1C->getAPIntValue() == 1) {
15657 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15658 Op.getOperand(0).hasOneUse();
15663 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15664 bool addTest = true;
15665 SDValue Chain = Op.getOperand(0);
15666 SDValue Cond = Op.getOperand(1);
15667 SDValue Dest = Op.getOperand(2);
15670 bool Inverted = false;
15672 if (Cond.getOpcode() == ISD::SETCC) {
15673 // Check for setcc([su]{add,sub,mul}o == 0).
15674 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15675 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15676 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15677 Cond.getOperand(0).getResNo() == 1 &&
15678 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15679 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15680 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15681 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15682 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15683 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15685 Cond = Cond.getOperand(0);
15687 SDValue NewCond = LowerSETCC(Cond, DAG);
15688 if (NewCond.getNode())
15693 // FIXME: LowerXALUO doesn't handle these!!
15694 else if (Cond.getOpcode() == X86ISD::ADD ||
15695 Cond.getOpcode() == X86ISD::SUB ||
15696 Cond.getOpcode() == X86ISD::SMUL ||
15697 Cond.getOpcode() == X86ISD::UMUL)
15698 Cond = LowerXALUO(Cond, DAG);
15701 // Look pass (and (setcc_carry (cmp ...)), 1).
15702 if (Cond.getOpcode() == ISD::AND &&
15703 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15704 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15705 if (C && C->getAPIntValue() == 1)
15706 Cond = Cond.getOperand(0);
15709 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15710 // setting operand in place of the X86ISD::SETCC.
15711 unsigned CondOpcode = Cond.getOpcode();
15712 if (CondOpcode == X86ISD::SETCC ||
15713 CondOpcode == X86ISD::SETCC_CARRY) {
15714 CC = Cond.getOperand(0);
15716 SDValue Cmp = Cond.getOperand(1);
15717 unsigned Opc = Cmp.getOpcode();
15718 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15719 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15723 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15727 // These can only come from an arithmetic instruction with overflow,
15728 // e.g. SADDO, UADDO.
15729 Cond = Cond.getNode()->getOperand(1);
15735 CondOpcode = Cond.getOpcode();
15736 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15737 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15738 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15739 Cond.getOperand(0).getValueType() != MVT::i8)) {
15740 SDValue LHS = Cond.getOperand(0);
15741 SDValue RHS = Cond.getOperand(1);
15742 unsigned X86Opcode;
15745 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15746 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15748 switch (CondOpcode) {
15749 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15751 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15753 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15756 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15757 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15759 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15761 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15764 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15765 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15766 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15767 default: llvm_unreachable("unexpected overflowing operator");
15770 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15771 if (CondOpcode == ISD::UMULO)
15772 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15775 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15777 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15779 if (CondOpcode == ISD::UMULO)
15780 Cond = X86Op.getValue(2);
15782 Cond = X86Op.getValue(1);
15784 CC = DAG.getConstant(X86Cond, MVT::i8);
15788 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15789 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15790 if (CondOpc == ISD::OR) {
15791 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15792 // two branches instead of an explicit OR instruction with a
15794 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15795 isX86LogicalCmp(Cmp)) {
15796 CC = Cond.getOperand(0).getOperand(0);
15797 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15798 Chain, Dest, CC, Cmp);
15799 CC = Cond.getOperand(1).getOperand(0);
15803 } else { // ISD::AND
15804 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15805 // two branches instead of an explicit AND instruction with a
15806 // separate test. However, we only do this if this block doesn't
15807 // have a fall-through edge, because this requires an explicit
15808 // jmp when the condition is false.
15809 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15810 isX86LogicalCmp(Cmp) &&
15811 Op.getNode()->hasOneUse()) {
15812 X86::CondCode CCode =
15813 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15814 CCode = X86::GetOppositeBranchCondition(CCode);
15815 CC = DAG.getConstant(CCode, MVT::i8);
15816 SDNode *User = *Op.getNode()->use_begin();
15817 // Look for an unconditional branch following this conditional branch.
15818 // We need this because we need to reverse the successors in order
15819 // to implement FCMP_OEQ.
15820 if (User->getOpcode() == ISD::BR) {
15821 SDValue FalseBB = User->getOperand(1);
15823 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15824 assert(NewBR == User);
15828 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15829 Chain, Dest, CC, Cmp);
15830 X86::CondCode CCode =
15831 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15832 CCode = X86::GetOppositeBranchCondition(CCode);
15833 CC = DAG.getConstant(CCode, MVT::i8);
15839 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15840 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15841 // It should be transformed during dag combiner except when the condition
15842 // is set by a arithmetics with overflow node.
15843 X86::CondCode CCode =
15844 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15845 CCode = X86::GetOppositeBranchCondition(CCode);
15846 CC = DAG.getConstant(CCode, MVT::i8);
15847 Cond = Cond.getOperand(0).getOperand(1);
15849 } else if (Cond.getOpcode() == ISD::SETCC &&
15850 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15851 // For FCMP_OEQ, we can emit
15852 // two branches instead of an explicit AND instruction with a
15853 // separate test. However, we only do this if this block doesn't
15854 // have a fall-through edge, because this requires an explicit
15855 // jmp when the condition is false.
15856 if (Op.getNode()->hasOneUse()) {
15857 SDNode *User = *Op.getNode()->use_begin();
15858 // Look for an unconditional branch following this conditional branch.
15859 // We need this because we need to reverse the successors in order
15860 // to implement FCMP_OEQ.
15861 if (User->getOpcode() == ISD::BR) {
15862 SDValue FalseBB = User->getOperand(1);
15864 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15865 assert(NewBR == User);
15869 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15870 Cond.getOperand(0), Cond.getOperand(1));
15871 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15872 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15873 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15874 Chain, Dest, CC, Cmp);
15875 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15880 } else if (Cond.getOpcode() == ISD::SETCC &&
15881 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15882 // For FCMP_UNE, we can emit
15883 // two branches instead of an explicit AND instruction with a
15884 // separate test. However, we only do this if this block doesn't
15885 // have a fall-through edge, because this requires an explicit
15886 // jmp when the condition is false.
15887 if (Op.getNode()->hasOneUse()) {
15888 SDNode *User = *Op.getNode()->use_begin();
15889 // Look for an unconditional branch following this conditional branch.
15890 // We need this because we need to reverse the successors in order
15891 // to implement FCMP_UNE.
15892 if (User->getOpcode() == ISD::BR) {
15893 SDValue FalseBB = User->getOperand(1);
15895 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15896 assert(NewBR == User);
15899 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15900 Cond.getOperand(0), Cond.getOperand(1));
15901 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15902 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15903 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15904 Chain, Dest, CC, Cmp);
15905 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15915 // Look pass the truncate if the high bits are known zero.
15916 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15917 Cond = Cond.getOperand(0);
15919 // We know the result of AND is compared against zero. Try to match
15921 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15922 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15923 if (NewSetCC.getNode()) {
15924 CC = NewSetCC.getOperand(0);
15925 Cond = NewSetCC.getOperand(1);
15932 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15933 CC = DAG.getConstant(X86Cond, MVT::i8);
15934 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15936 Cond = ConvertCmpIfNecessary(Cond, DAG);
15937 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15938 Chain, Dest, CC, Cond);
15941 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15942 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15943 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15944 // that the guard pages used by the OS virtual memory manager are allocated in
15945 // correct sequence.
15947 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15948 SelectionDAG &DAG) const {
15949 MachineFunction &MF = DAG.getMachineFunction();
15950 bool SplitStack = MF.shouldSplitStack();
15951 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15956 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15957 SDNode* Node = Op.getNode();
15959 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15960 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15961 " not tell us which reg is the stack pointer!");
15962 EVT VT = Node->getValueType(0);
15963 SDValue Tmp1 = SDValue(Node, 0);
15964 SDValue Tmp2 = SDValue(Node, 1);
15965 SDValue Tmp3 = Node->getOperand(2);
15966 SDValue Chain = Tmp1.getOperand(0);
15968 // Chain the dynamic stack allocation so that it doesn't modify the stack
15969 // pointer when other instructions are using the stack.
15970 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15973 SDValue Size = Tmp2.getOperand(1);
15974 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15975 Chain = SP.getValue(1);
15976 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15977 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15978 unsigned StackAlign = TFI.getStackAlignment();
15979 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15980 if (Align > StackAlign)
15981 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15982 DAG.getConstant(-(uint64_t)Align, VT));
15983 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15985 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15986 DAG.getIntPtrConstant(0, true), SDValue(),
15989 SDValue Ops[2] = { Tmp1, Tmp2 };
15990 return DAG.getMergeValues(Ops, dl);
15994 SDValue Chain = Op.getOperand(0);
15995 SDValue Size = Op.getOperand(1);
15996 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15997 EVT VT = Op.getNode()->getValueType(0);
15999 bool Is64Bit = Subtarget->is64Bit();
16000 EVT SPTy = getPointerTy();
16003 MachineRegisterInfo &MRI = MF.getRegInfo();
16006 // The 64 bit implementation of segmented stacks needs to clobber both r10
16007 // r11. This makes it impossible to use it along with nested parameters.
16008 const Function *F = MF.getFunction();
16010 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16012 if (I->hasNestAttr())
16013 report_fatal_error("Cannot use segmented stacks with functions that "
16014 "have nested arguments.");
16017 const TargetRegisterClass *AddrRegClass =
16018 getRegClassFor(getPointerTy());
16019 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16020 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16021 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16022 DAG.getRegister(Vreg, SPTy));
16023 SDValue Ops1[2] = { Value, Chain };
16024 return DAG.getMergeValues(Ops1, dl);
16027 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16029 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16030 Flag = Chain.getValue(1);
16031 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16033 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16035 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16036 DAG.getSubtarget().getRegisterInfo());
16037 unsigned SPReg = RegInfo->getStackRegister();
16038 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16039 Chain = SP.getValue(1);
16042 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16043 DAG.getConstant(-(uint64_t)Align, VT));
16044 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16047 SDValue Ops1[2] = { SP, Chain };
16048 return DAG.getMergeValues(Ops1, dl);
16052 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16053 MachineFunction &MF = DAG.getMachineFunction();
16054 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16056 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16059 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16060 // vastart just stores the address of the VarArgsFrameIndex slot into the
16061 // memory location argument.
16062 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16064 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16065 MachinePointerInfo(SV), false, false, 0);
16069 // gp_offset (0 - 6 * 8)
16070 // fp_offset (48 - 48 + 8 * 16)
16071 // overflow_arg_area (point to parameters coming in memory).
16073 SmallVector<SDValue, 8> MemOps;
16074 SDValue FIN = Op.getOperand(1);
16076 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16077 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16079 FIN, MachinePointerInfo(SV), false, false, 0);
16080 MemOps.push_back(Store);
16083 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16084 FIN, DAG.getIntPtrConstant(4));
16085 Store = DAG.getStore(Op.getOperand(0), DL,
16086 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16088 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16089 MemOps.push_back(Store);
16091 // Store ptr to overflow_arg_area
16092 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16093 FIN, DAG.getIntPtrConstant(4));
16094 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16096 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16097 MachinePointerInfo(SV, 8),
16099 MemOps.push_back(Store);
16101 // Store ptr to reg_save_area.
16102 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16103 FIN, DAG.getIntPtrConstant(8));
16104 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16106 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16107 MachinePointerInfo(SV, 16), false, false, 0);
16108 MemOps.push_back(Store);
16109 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16112 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16113 assert(Subtarget->is64Bit() &&
16114 "LowerVAARG only handles 64-bit va_arg!");
16115 assert((Subtarget->isTargetLinux() ||
16116 Subtarget->isTargetDarwin()) &&
16117 "Unhandled target in LowerVAARG");
16118 assert(Op.getNode()->getNumOperands() == 4);
16119 SDValue Chain = Op.getOperand(0);
16120 SDValue SrcPtr = Op.getOperand(1);
16121 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16122 unsigned Align = Op.getConstantOperandVal(3);
16125 EVT ArgVT = Op.getNode()->getValueType(0);
16126 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16127 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16130 // Decide which area this value should be read from.
16131 // TODO: Implement the AMD64 ABI in its entirety. This simple
16132 // selection mechanism works only for the basic types.
16133 if (ArgVT == MVT::f80) {
16134 llvm_unreachable("va_arg for f80 not yet implemented");
16135 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16136 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16137 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16138 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16140 llvm_unreachable("Unhandled argument type in LowerVAARG");
16143 if (ArgMode == 2) {
16144 // Sanity Check: Make sure using fp_offset makes sense.
16145 assert(!DAG.getTarget().Options.UseSoftFloat &&
16146 !(DAG.getMachineFunction()
16147 .getFunction()->getAttributes()
16148 .hasAttribute(AttributeSet::FunctionIndex,
16149 Attribute::NoImplicitFloat)) &&
16150 Subtarget->hasSSE1());
16153 // Insert VAARG_64 node into the DAG
16154 // VAARG_64 returns two values: Variable Argument Address, Chain
16155 SmallVector<SDValue, 11> InstOps;
16156 InstOps.push_back(Chain);
16157 InstOps.push_back(SrcPtr);
16158 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16159 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16160 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16161 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16162 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16163 VTs, InstOps, MVT::i64,
16164 MachinePointerInfo(SV),
16166 /*Volatile=*/false,
16168 /*WriteMem=*/true);
16169 Chain = VAARG.getValue(1);
16171 // Load the next argument and return it
16172 return DAG.getLoad(ArgVT, dl,
16175 MachinePointerInfo(),
16176 false, false, false, 0);
16179 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16180 SelectionDAG &DAG) {
16181 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16182 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16183 SDValue Chain = Op.getOperand(0);
16184 SDValue DstPtr = Op.getOperand(1);
16185 SDValue SrcPtr = Op.getOperand(2);
16186 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16187 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16190 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16191 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16193 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16196 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16197 // amount is a constant. Takes immediate version of shift as input.
16198 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16199 SDValue SrcOp, uint64_t ShiftAmt,
16200 SelectionDAG &DAG) {
16201 MVT ElementType = VT.getVectorElementType();
16203 // Fold this packed shift into its first operand if ShiftAmt is 0.
16207 // Check for ShiftAmt >= element width
16208 if (ShiftAmt >= ElementType.getSizeInBits()) {
16209 if (Opc == X86ISD::VSRAI)
16210 ShiftAmt = ElementType.getSizeInBits() - 1;
16212 return DAG.getConstant(0, VT);
16215 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16216 && "Unknown target vector shift-by-constant node");
16218 // Fold this packed vector shift into a build vector if SrcOp is a
16219 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16220 if (VT == SrcOp.getSimpleValueType() &&
16221 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16222 SmallVector<SDValue, 8> Elts;
16223 unsigned NumElts = SrcOp->getNumOperands();
16224 ConstantSDNode *ND;
16227 default: llvm_unreachable(nullptr);
16228 case X86ISD::VSHLI:
16229 for (unsigned i=0; i!=NumElts; ++i) {
16230 SDValue CurrentOp = SrcOp->getOperand(i);
16231 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16232 Elts.push_back(CurrentOp);
16235 ND = cast<ConstantSDNode>(CurrentOp);
16236 const APInt &C = ND->getAPIntValue();
16237 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16240 case X86ISD::VSRLI:
16241 for (unsigned i=0; i!=NumElts; ++i) {
16242 SDValue CurrentOp = SrcOp->getOperand(i);
16243 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16244 Elts.push_back(CurrentOp);
16247 ND = cast<ConstantSDNode>(CurrentOp);
16248 const APInt &C = ND->getAPIntValue();
16249 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16252 case X86ISD::VSRAI:
16253 for (unsigned i=0; i!=NumElts; ++i) {
16254 SDValue CurrentOp = SrcOp->getOperand(i);
16255 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16256 Elts.push_back(CurrentOp);
16259 ND = cast<ConstantSDNode>(CurrentOp);
16260 const APInt &C = ND->getAPIntValue();
16261 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16266 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16269 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16272 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16273 // may or may not be a constant. Takes immediate version of shift as input.
16274 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16275 SDValue SrcOp, SDValue ShAmt,
16276 SelectionDAG &DAG) {
16277 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16279 // Catch shift-by-constant.
16280 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16281 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16282 CShAmt->getZExtValue(), DAG);
16284 // Change opcode to non-immediate version
16286 default: llvm_unreachable("Unknown target vector shift node");
16287 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16288 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16289 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16292 // Need to build a vector containing shift amount
16293 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16296 ShOps[1] = DAG.getConstant(0, MVT::i32);
16297 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16298 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16300 // The return type has to be a 128-bit type with the same element
16301 // type as the input type.
16302 MVT EltVT = VT.getVectorElementType();
16303 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16305 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16306 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16309 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16310 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16311 /// necessary casting for \p Mask when lowering masking intrinsics.
16312 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16313 SDValue PreservedSrc,
16314 const X86Subtarget *Subtarget,
16315 SelectionDAG &DAG) {
16316 EVT VT = Op.getValueType();
16317 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16318 MVT::i1, VT.getVectorNumElements());
16319 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16320 Mask.getValueType().getSizeInBits());
16323 assert(MaskVT.isSimple() && "invalid mask type");
16325 if (isAllOnes(Mask))
16328 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16329 // are extracted by EXTRACT_SUBVECTOR.
16330 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16331 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16332 DAG.getIntPtrConstant(0));
16334 switch (Op.getOpcode()) {
16336 case X86ISD::PCMPEQM:
16337 case X86ISD::PCMPGTM:
16339 case X86ISD::CMPMU:
16340 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16342 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16343 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16344 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16347 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16349 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16350 case Intrinsic::x86_fma_vfmadd_ps:
16351 case Intrinsic::x86_fma_vfmadd_pd:
16352 case Intrinsic::x86_fma_vfmadd_ps_256:
16353 case Intrinsic::x86_fma_vfmadd_pd_256:
16354 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16355 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16356 return X86ISD::FMADD;
16357 case Intrinsic::x86_fma_vfmsub_ps:
16358 case Intrinsic::x86_fma_vfmsub_pd:
16359 case Intrinsic::x86_fma_vfmsub_ps_256:
16360 case Intrinsic::x86_fma_vfmsub_pd_256:
16361 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16362 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16363 return X86ISD::FMSUB;
16364 case Intrinsic::x86_fma_vfnmadd_ps:
16365 case Intrinsic::x86_fma_vfnmadd_pd:
16366 case Intrinsic::x86_fma_vfnmadd_ps_256:
16367 case Intrinsic::x86_fma_vfnmadd_pd_256:
16368 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16369 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16370 return X86ISD::FNMADD;
16371 case Intrinsic::x86_fma_vfnmsub_ps:
16372 case Intrinsic::x86_fma_vfnmsub_pd:
16373 case Intrinsic::x86_fma_vfnmsub_ps_256:
16374 case Intrinsic::x86_fma_vfnmsub_pd_256:
16375 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16376 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16377 return X86ISD::FNMSUB;
16378 case Intrinsic::x86_fma_vfmaddsub_ps:
16379 case Intrinsic::x86_fma_vfmaddsub_pd:
16380 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16381 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16382 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16383 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16384 return X86ISD::FMADDSUB;
16385 case Intrinsic::x86_fma_vfmsubadd_ps:
16386 case Intrinsic::x86_fma_vfmsubadd_pd:
16387 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16388 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16389 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16390 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16391 return X86ISD::FMSUBADD;
16395 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16396 SelectionDAG &DAG) {
16398 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16399 EVT VT = Op.getValueType();
16400 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16402 switch(IntrData->Type) {
16403 case INTR_TYPE_1OP:
16404 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16405 case INTR_TYPE_2OP:
16406 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16408 case INTR_TYPE_3OP:
16409 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16410 Op.getOperand(2), Op.getOperand(3));
16411 case INTR_TYPE_1OP_MASK_RM: {
16412 SDValue Src = Op.getOperand(1);
16413 SDValue Src0 = Op.getOperand(2);
16414 SDValue Mask = Op.getOperand(3);
16415 SDValue RoundingMode = Op.getOperand(4);
16416 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16418 Mask, Src0, Subtarget, DAG);
16422 case CMP_MASK_CC: {
16423 // Comparison intrinsics with masks.
16424 // Example of transformation:
16425 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16426 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16428 // (v8i1 (insert_subvector undef,
16429 // (v2i1 (and (PCMPEQM %a, %b),
16430 // (extract_subvector
16431 // (v8i1 (bitcast %mask)), 0))), 0))))
16432 EVT VT = Op.getOperand(1).getValueType();
16433 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16434 VT.getVectorNumElements());
16435 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16436 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16437 Mask.getValueType().getSizeInBits());
16439 if (IntrData->Type == CMP_MASK_CC) {
16440 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16441 Op.getOperand(2), Op.getOperand(3));
16443 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16444 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16447 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16448 DAG.getTargetConstant(0, MaskVT),
16450 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16451 DAG.getUNDEF(BitcastVT), CmpMask,
16452 DAG.getIntPtrConstant(0));
16453 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16455 case COMI: { // Comparison intrinsics
16456 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16457 SDValue LHS = Op.getOperand(1);
16458 SDValue RHS = Op.getOperand(2);
16459 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16460 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16461 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16462 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16463 DAG.getConstant(X86CC, MVT::i8), Cond);
16464 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16467 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16468 Op.getOperand(1), Op.getOperand(2), DAG);
16475 default: return SDValue(); // Don't custom lower most intrinsics.
16477 // Arithmetic intrinsics.
16478 case Intrinsic::x86_sse2_pmulu_dq:
16479 case Intrinsic::x86_avx2_pmulu_dq:
16480 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16481 Op.getOperand(1), Op.getOperand(2));
16483 case Intrinsic::x86_sse41_pmuldq:
16484 case Intrinsic::x86_avx2_pmul_dq:
16485 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16486 Op.getOperand(1), Op.getOperand(2));
16488 case Intrinsic::x86_sse2_pmulhu_w:
16489 case Intrinsic::x86_avx2_pmulhu_w:
16490 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16491 Op.getOperand(1), Op.getOperand(2));
16493 case Intrinsic::x86_sse2_pmulh_w:
16494 case Intrinsic::x86_avx2_pmulh_w:
16495 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16496 Op.getOperand(1), Op.getOperand(2));
16498 // SSE/SSE2/AVX floating point max/min intrinsics.
16499 case Intrinsic::x86_sse_max_ps:
16500 case Intrinsic::x86_sse2_max_pd:
16501 case Intrinsic::x86_avx_max_ps_256:
16502 case Intrinsic::x86_avx_max_pd_256:
16503 case Intrinsic::x86_sse_min_ps:
16504 case Intrinsic::x86_sse2_min_pd:
16505 case Intrinsic::x86_avx_min_ps_256:
16506 case Intrinsic::x86_avx_min_pd_256: {
16509 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16510 case Intrinsic::x86_sse_max_ps:
16511 case Intrinsic::x86_sse2_max_pd:
16512 case Intrinsic::x86_avx_max_ps_256:
16513 case Intrinsic::x86_avx_max_pd_256:
16514 Opcode = X86ISD::FMAX;
16516 case Intrinsic::x86_sse_min_ps:
16517 case Intrinsic::x86_sse2_min_pd:
16518 case Intrinsic::x86_avx_min_ps_256:
16519 case Intrinsic::x86_avx_min_pd_256:
16520 Opcode = X86ISD::FMIN;
16523 return DAG.getNode(Opcode, dl, Op.getValueType(),
16524 Op.getOperand(1), Op.getOperand(2));
16527 // AVX2 variable shift intrinsics
16528 case Intrinsic::x86_avx2_psllv_d:
16529 case Intrinsic::x86_avx2_psllv_q:
16530 case Intrinsic::x86_avx2_psllv_d_256:
16531 case Intrinsic::x86_avx2_psllv_q_256:
16532 case Intrinsic::x86_avx2_psrlv_d:
16533 case Intrinsic::x86_avx2_psrlv_q:
16534 case Intrinsic::x86_avx2_psrlv_d_256:
16535 case Intrinsic::x86_avx2_psrlv_q_256:
16536 case Intrinsic::x86_avx2_psrav_d:
16537 case Intrinsic::x86_avx2_psrav_d_256: {
16540 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16541 case Intrinsic::x86_avx2_psllv_d:
16542 case Intrinsic::x86_avx2_psllv_q:
16543 case Intrinsic::x86_avx2_psllv_d_256:
16544 case Intrinsic::x86_avx2_psllv_q_256:
16547 case Intrinsic::x86_avx2_psrlv_d:
16548 case Intrinsic::x86_avx2_psrlv_q:
16549 case Intrinsic::x86_avx2_psrlv_d_256:
16550 case Intrinsic::x86_avx2_psrlv_q_256:
16553 case Intrinsic::x86_avx2_psrav_d:
16554 case Intrinsic::x86_avx2_psrav_d_256:
16558 return DAG.getNode(Opcode, dl, Op.getValueType(),
16559 Op.getOperand(1), Op.getOperand(2));
16562 case Intrinsic::x86_sse2_packssdw_128:
16563 case Intrinsic::x86_sse2_packsswb_128:
16564 case Intrinsic::x86_avx2_packssdw:
16565 case Intrinsic::x86_avx2_packsswb:
16566 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16567 Op.getOperand(1), Op.getOperand(2));
16569 case Intrinsic::x86_sse2_packuswb_128:
16570 case Intrinsic::x86_sse41_packusdw:
16571 case Intrinsic::x86_avx2_packuswb:
16572 case Intrinsic::x86_avx2_packusdw:
16573 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16574 Op.getOperand(1), Op.getOperand(2));
16576 case Intrinsic::x86_ssse3_pshuf_b_128:
16577 case Intrinsic::x86_avx2_pshuf_b:
16578 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16579 Op.getOperand(1), Op.getOperand(2));
16581 case Intrinsic::x86_sse2_pshuf_d:
16582 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16583 Op.getOperand(1), Op.getOperand(2));
16585 case Intrinsic::x86_sse2_pshufl_w:
16586 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16587 Op.getOperand(1), Op.getOperand(2));
16589 case Intrinsic::x86_sse2_pshufh_w:
16590 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16591 Op.getOperand(1), Op.getOperand(2));
16593 case Intrinsic::x86_ssse3_psign_b_128:
16594 case Intrinsic::x86_ssse3_psign_w_128:
16595 case Intrinsic::x86_ssse3_psign_d_128:
16596 case Intrinsic::x86_avx2_psign_b:
16597 case Intrinsic::x86_avx2_psign_w:
16598 case Intrinsic::x86_avx2_psign_d:
16599 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16600 Op.getOperand(1), Op.getOperand(2));
16602 case Intrinsic::x86_avx2_permd:
16603 case Intrinsic::x86_avx2_permps:
16604 // Operands intentionally swapped. Mask is last operand to intrinsic,
16605 // but second operand for node/instruction.
16606 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16607 Op.getOperand(2), Op.getOperand(1));
16609 case Intrinsic::x86_avx512_mask_valign_q_512:
16610 case Intrinsic::x86_avx512_mask_valign_d_512:
16611 // Vector source operands are swapped.
16612 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16613 Op.getValueType(), Op.getOperand(2),
16616 Op.getOperand(5), Op.getOperand(4),
16619 // ptest and testp intrinsics. The intrinsic these come from are designed to
16620 // return an integer value, not just an instruction so lower it to the ptest
16621 // or testp pattern and a setcc for the result.
16622 case Intrinsic::x86_sse41_ptestz:
16623 case Intrinsic::x86_sse41_ptestc:
16624 case Intrinsic::x86_sse41_ptestnzc:
16625 case Intrinsic::x86_avx_ptestz_256:
16626 case Intrinsic::x86_avx_ptestc_256:
16627 case Intrinsic::x86_avx_ptestnzc_256:
16628 case Intrinsic::x86_avx_vtestz_ps:
16629 case Intrinsic::x86_avx_vtestc_ps:
16630 case Intrinsic::x86_avx_vtestnzc_ps:
16631 case Intrinsic::x86_avx_vtestz_pd:
16632 case Intrinsic::x86_avx_vtestc_pd:
16633 case Intrinsic::x86_avx_vtestnzc_pd:
16634 case Intrinsic::x86_avx_vtestz_ps_256:
16635 case Intrinsic::x86_avx_vtestc_ps_256:
16636 case Intrinsic::x86_avx_vtestnzc_ps_256:
16637 case Intrinsic::x86_avx_vtestz_pd_256:
16638 case Intrinsic::x86_avx_vtestc_pd_256:
16639 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16640 bool IsTestPacked = false;
16643 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16644 case Intrinsic::x86_avx_vtestz_ps:
16645 case Intrinsic::x86_avx_vtestz_pd:
16646 case Intrinsic::x86_avx_vtestz_ps_256:
16647 case Intrinsic::x86_avx_vtestz_pd_256:
16648 IsTestPacked = true; // Fallthrough
16649 case Intrinsic::x86_sse41_ptestz:
16650 case Intrinsic::x86_avx_ptestz_256:
16652 X86CC = X86::COND_E;
16654 case Intrinsic::x86_avx_vtestc_ps:
16655 case Intrinsic::x86_avx_vtestc_pd:
16656 case Intrinsic::x86_avx_vtestc_ps_256:
16657 case Intrinsic::x86_avx_vtestc_pd_256:
16658 IsTestPacked = true; // Fallthrough
16659 case Intrinsic::x86_sse41_ptestc:
16660 case Intrinsic::x86_avx_ptestc_256:
16662 X86CC = X86::COND_B;
16664 case Intrinsic::x86_avx_vtestnzc_ps:
16665 case Intrinsic::x86_avx_vtestnzc_pd:
16666 case Intrinsic::x86_avx_vtestnzc_ps_256:
16667 case Intrinsic::x86_avx_vtestnzc_pd_256:
16668 IsTestPacked = true; // Fallthrough
16669 case Intrinsic::x86_sse41_ptestnzc:
16670 case Intrinsic::x86_avx_ptestnzc_256:
16672 X86CC = X86::COND_A;
16676 SDValue LHS = Op.getOperand(1);
16677 SDValue RHS = Op.getOperand(2);
16678 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16679 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16680 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16681 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16682 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16684 case Intrinsic::x86_avx512_kortestz_w:
16685 case Intrinsic::x86_avx512_kortestc_w: {
16686 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16687 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16688 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16689 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16690 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16691 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16692 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16695 case Intrinsic::x86_sse42_pcmpistria128:
16696 case Intrinsic::x86_sse42_pcmpestria128:
16697 case Intrinsic::x86_sse42_pcmpistric128:
16698 case Intrinsic::x86_sse42_pcmpestric128:
16699 case Intrinsic::x86_sse42_pcmpistrio128:
16700 case Intrinsic::x86_sse42_pcmpestrio128:
16701 case Intrinsic::x86_sse42_pcmpistris128:
16702 case Intrinsic::x86_sse42_pcmpestris128:
16703 case Intrinsic::x86_sse42_pcmpistriz128:
16704 case Intrinsic::x86_sse42_pcmpestriz128: {
16708 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16709 case Intrinsic::x86_sse42_pcmpistria128:
16710 Opcode = X86ISD::PCMPISTRI;
16711 X86CC = X86::COND_A;
16713 case Intrinsic::x86_sse42_pcmpestria128:
16714 Opcode = X86ISD::PCMPESTRI;
16715 X86CC = X86::COND_A;
16717 case Intrinsic::x86_sse42_pcmpistric128:
16718 Opcode = X86ISD::PCMPISTRI;
16719 X86CC = X86::COND_B;
16721 case Intrinsic::x86_sse42_pcmpestric128:
16722 Opcode = X86ISD::PCMPESTRI;
16723 X86CC = X86::COND_B;
16725 case Intrinsic::x86_sse42_pcmpistrio128:
16726 Opcode = X86ISD::PCMPISTRI;
16727 X86CC = X86::COND_O;
16729 case Intrinsic::x86_sse42_pcmpestrio128:
16730 Opcode = X86ISD::PCMPESTRI;
16731 X86CC = X86::COND_O;
16733 case Intrinsic::x86_sse42_pcmpistris128:
16734 Opcode = X86ISD::PCMPISTRI;
16735 X86CC = X86::COND_S;
16737 case Intrinsic::x86_sse42_pcmpestris128:
16738 Opcode = X86ISD::PCMPESTRI;
16739 X86CC = X86::COND_S;
16741 case Intrinsic::x86_sse42_pcmpistriz128:
16742 Opcode = X86ISD::PCMPISTRI;
16743 X86CC = X86::COND_E;
16745 case Intrinsic::x86_sse42_pcmpestriz128:
16746 Opcode = X86ISD::PCMPESTRI;
16747 X86CC = X86::COND_E;
16750 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16751 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16752 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16753 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16754 DAG.getConstant(X86CC, MVT::i8),
16755 SDValue(PCMP.getNode(), 1));
16756 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16759 case Intrinsic::x86_sse42_pcmpistri128:
16760 case Intrinsic::x86_sse42_pcmpestri128: {
16762 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16763 Opcode = X86ISD::PCMPISTRI;
16765 Opcode = X86ISD::PCMPESTRI;
16767 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16768 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16769 return DAG.getNode(Opcode, dl, VTs, NewOps);
16772 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16773 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16774 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16775 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16776 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16777 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16778 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16779 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16780 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16781 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16782 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16783 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16784 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16785 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16786 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16787 dl, Op.getValueType(),
16791 Op.getOperand(4), Op.getOperand(1),
16797 case Intrinsic::x86_fma_vfmadd_ps:
16798 case Intrinsic::x86_fma_vfmadd_pd:
16799 case Intrinsic::x86_fma_vfmsub_ps:
16800 case Intrinsic::x86_fma_vfmsub_pd:
16801 case Intrinsic::x86_fma_vfnmadd_ps:
16802 case Intrinsic::x86_fma_vfnmadd_pd:
16803 case Intrinsic::x86_fma_vfnmsub_ps:
16804 case Intrinsic::x86_fma_vfnmsub_pd:
16805 case Intrinsic::x86_fma_vfmaddsub_ps:
16806 case Intrinsic::x86_fma_vfmaddsub_pd:
16807 case Intrinsic::x86_fma_vfmsubadd_ps:
16808 case Intrinsic::x86_fma_vfmsubadd_pd:
16809 case Intrinsic::x86_fma_vfmadd_ps_256:
16810 case Intrinsic::x86_fma_vfmadd_pd_256:
16811 case Intrinsic::x86_fma_vfmsub_ps_256:
16812 case Intrinsic::x86_fma_vfmsub_pd_256:
16813 case Intrinsic::x86_fma_vfnmadd_ps_256:
16814 case Intrinsic::x86_fma_vfnmadd_pd_256:
16815 case Intrinsic::x86_fma_vfnmsub_ps_256:
16816 case Intrinsic::x86_fma_vfnmsub_pd_256:
16817 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16818 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16819 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16820 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16821 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16822 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16826 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16827 SDValue Src, SDValue Mask, SDValue Base,
16828 SDValue Index, SDValue ScaleOp, SDValue Chain,
16829 const X86Subtarget * Subtarget) {
16831 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16832 assert(C && "Invalid scale type");
16833 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16834 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16835 Index.getSimpleValueType().getVectorNumElements());
16837 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16839 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16841 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16842 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16843 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16844 SDValue Segment = DAG.getRegister(0, MVT::i32);
16845 if (Src.getOpcode() == ISD::UNDEF)
16846 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16847 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16848 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16849 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16850 return DAG.getMergeValues(RetOps, dl);
16853 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16854 SDValue Src, SDValue Mask, SDValue Base,
16855 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16857 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16858 assert(C && "Invalid scale type");
16859 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16860 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16861 SDValue Segment = DAG.getRegister(0, MVT::i32);
16862 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16863 Index.getSimpleValueType().getVectorNumElements());
16865 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16867 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16869 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16870 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16871 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16872 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16873 return SDValue(Res, 1);
16876 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16877 SDValue Mask, SDValue Base, SDValue Index,
16878 SDValue ScaleOp, SDValue Chain) {
16880 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16881 assert(C && "Invalid scale type");
16882 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16883 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16884 SDValue Segment = DAG.getRegister(0, MVT::i32);
16886 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16888 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16890 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16892 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16893 //SDVTList VTs = DAG.getVTList(MVT::Other);
16894 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16895 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16896 return SDValue(Res, 0);
16899 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16900 // read performance monitor counters (x86_rdpmc).
16901 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16902 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16903 SmallVectorImpl<SDValue> &Results) {
16904 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16905 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16908 // The ECX register is used to select the index of the performance counter
16910 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16912 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16914 // Reads the content of a 64-bit performance counter and returns it in the
16915 // registers EDX:EAX.
16916 if (Subtarget->is64Bit()) {
16917 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16918 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16921 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16922 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16925 Chain = HI.getValue(1);
16927 if (Subtarget->is64Bit()) {
16928 // The EAX register is loaded with the low-order 32 bits. The EDX register
16929 // is loaded with the supported high-order bits of the counter.
16930 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16931 DAG.getConstant(32, MVT::i8));
16932 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16933 Results.push_back(Chain);
16937 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16938 SDValue Ops[] = { LO, HI };
16939 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16940 Results.push_back(Pair);
16941 Results.push_back(Chain);
16944 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16945 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16946 // also used to custom lower READCYCLECOUNTER nodes.
16947 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16948 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16949 SmallVectorImpl<SDValue> &Results) {
16950 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16951 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16954 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16955 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16956 // and the EAX register is loaded with the low-order 32 bits.
16957 if (Subtarget->is64Bit()) {
16958 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16959 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16962 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16963 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16966 SDValue Chain = HI.getValue(1);
16968 if (Opcode == X86ISD::RDTSCP_DAG) {
16969 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16971 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16972 // the ECX register. Add 'ecx' explicitly to the chain.
16973 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16975 // Explicitly store the content of ECX at the location passed in input
16976 // to the 'rdtscp' intrinsic.
16977 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16978 MachinePointerInfo(), false, false, 0);
16981 if (Subtarget->is64Bit()) {
16982 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16983 // the EAX register is loaded with the low-order 32 bits.
16984 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16985 DAG.getConstant(32, MVT::i8));
16986 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16987 Results.push_back(Chain);
16991 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16992 SDValue Ops[] = { LO, HI };
16993 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16994 Results.push_back(Pair);
16995 Results.push_back(Chain);
16998 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16999 SelectionDAG &DAG) {
17000 SmallVector<SDValue, 2> Results;
17002 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17004 return DAG.getMergeValues(Results, DL);
17008 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17009 SelectionDAG &DAG) {
17010 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17012 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17017 switch(IntrData->Type) {
17019 llvm_unreachable("Unknown Intrinsic Type");
17023 // Emit the node with the right value type.
17024 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17025 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17027 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17028 // Otherwise return the value from Rand, which is always 0, casted to i32.
17029 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17030 DAG.getConstant(1, Op->getValueType(1)),
17031 DAG.getConstant(X86::COND_B, MVT::i32),
17032 SDValue(Result.getNode(), 1) };
17033 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17034 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17037 // Return { result, isValid, chain }.
17038 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17039 SDValue(Result.getNode(), 2));
17042 //gather(v1, mask, index, base, scale);
17043 SDValue Chain = Op.getOperand(0);
17044 SDValue Src = Op.getOperand(2);
17045 SDValue Base = Op.getOperand(3);
17046 SDValue Index = Op.getOperand(4);
17047 SDValue Mask = Op.getOperand(5);
17048 SDValue Scale = Op.getOperand(6);
17049 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17053 //scatter(base, mask, index, v1, scale);
17054 SDValue Chain = Op.getOperand(0);
17055 SDValue Base = Op.getOperand(2);
17056 SDValue Mask = Op.getOperand(3);
17057 SDValue Index = Op.getOperand(4);
17058 SDValue Src = Op.getOperand(5);
17059 SDValue Scale = Op.getOperand(6);
17060 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17063 SDValue Hint = Op.getOperand(6);
17065 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17066 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17067 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17068 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17069 SDValue Chain = Op.getOperand(0);
17070 SDValue Mask = Op.getOperand(2);
17071 SDValue Index = Op.getOperand(3);
17072 SDValue Base = Op.getOperand(4);
17073 SDValue Scale = Op.getOperand(5);
17074 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17076 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17078 SmallVector<SDValue, 2> Results;
17079 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17080 return DAG.getMergeValues(Results, dl);
17082 // Read Performance Monitoring Counters.
17084 SmallVector<SDValue, 2> Results;
17085 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17086 return DAG.getMergeValues(Results, dl);
17088 // XTEST intrinsics.
17090 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17091 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17092 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17093 DAG.getConstant(X86::COND_NE, MVT::i8),
17095 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17096 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17097 Ret, SDValue(InTrans.getNode(), 1));
17101 SmallVector<SDValue, 2> Results;
17102 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17103 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17104 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17105 DAG.getConstant(-1, MVT::i8));
17106 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17107 Op.getOperand(4), GenCF.getValue(1));
17108 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17109 Op.getOperand(5), MachinePointerInfo(),
17111 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17112 DAG.getConstant(X86::COND_B, MVT::i8),
17114 Results.push_back(SetCC);
17115 Results.push_back(Store);
17116 return DAG.getMergeValues(Results, dl);
17121 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17122 SelectionDAG &DAG) const {
17123 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17124 MFI->setReturnAddressIsTaken(true);
17126 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17129 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17131 EVT PtrVT = getPointerTy();
17134 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17135 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17136 DAG.getSubtarget().getRegisterInfo());
17137 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17138 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17139 DAG.getNode(ISD::ADD, dl, PtrVT,
17140 FrameAddr, Offset),
17141 MachinePointerInfo(), false, false, false, 0);
17144 // Just load the return address.
17145 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17146 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17147 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17150 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17151 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17152 MFI->setFrameAddressIsTaken(true);
17154 EVT VT = Op.getValueType();
17155 SDLoc dl(Op); // FIXME probably not meaningful
17156 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17157 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17158 DAG.getSubtarget().getRegisterInfo());
17159 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17160 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17161 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17162 "Invalid Frame Register!");
17163 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17165 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17166 MachinePointerInfo(),
17167 false, false, false, 0);
17171 // FIXME? Maybe this could be a TableGen attribute on some registers and
17172 // this table could be generated automatically from RegInfo.
17173 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17175 unsigned Reg = StringSwitch<unsigned>(RegName)
17176 .Case("esp", X86::ESP)
17177 .Case("rsp", X86::RSP)
17181 report_fatal_error("Invalid register name global variable");
17184 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17185 SelectionDAG &DAG) const {
17186 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17187 DAG.getSubtarget().getRegisterInfo());
17188 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17191 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17192 SDValue Chain = Op.getOperand(0);
17193 SDValue Offset = Op.getOperand(1);
17194 SDValue Handler = Op.getOperand(2);
17197 EVT PtrVT = getPointerTy();
17198 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17199 DAG.getSubtarget().getRegisterInfo());
17200 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17201 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17202 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17203 "Invalid Frame Register!");
17204 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17205 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17207 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17208 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17209 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17210 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17212 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17214 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17215 DAG.getRegister(StoreAddrReg, PtrVT));
17218 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17219 SelectionDAG &DAG) const {
17221 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17222 DAG.getVTList(MVT::i32, MVT::Other),
17223 Op.getOperand(0), Op.getOperand(1));
17226 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17227 SelectionDAG &DAG) const {
17229 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17230 Op.getOperand(0), Op.getOperand(1));
17233 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17234 return Op.getOperand(0);
17237 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17238 SelectionDAG &DAG) const {
17239 SDValue Root = Op.getOperand(0);
17240 SDValue Trmp = Op.getOperand(1); // trampoline
17241 SDValue FPtr = Op.getOperand(2); // nested function
17242 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17245 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17246 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17248 if (Subtarget->is64Bit()) {
17249 SDValue OutChains[6];
17251 // Large code-model.
17252 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17253 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17255 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17256 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17258 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17260 // Load the pointer to the nested function into R11.
17261 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17262 SDValue Addr = Trmp;
17263 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17264 Addr, MachinePointerInfo(TrmpAddr),
17267 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17268 DAG.getConstant(2, MVT::i64));
17269 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17270 MachinePointerInfo(TrmpAddr, 2),
17273 // Load the 'nest' parameter value into R10.
17274 // R10 is specified in X86CallingConv.td
17275 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17276 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17277 DAG.getConstant(10, MVT::i64));
17278 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17279 Addr, MachinePointerInfo(TrmpAddr, 10),
17282 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17283 DAG.getConstant(12, MVT::i64));
17284 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17285 MachinePointerInfo(TrmpAddr, 12),
17288 // Jump to the nested function.
17289 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17290 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17291 DAG.getConstant(20, MVT::i64));
17292 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17293 Addr, MachinePointerInfo(TrmpAddr, 20),
17296 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17297 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17298 DAG.getConstant(22, MVT::i64));
17299 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17300 MachinePointerInfo(TrmpAddr, 22),
17303 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17305 const Function *Func =
17306 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17307 CallingConv::ID CC = Func->getCallingConv();
17312 llvm_unreachable("Unsupported calling convention");
17313 case CallingConv::C:
17314 case CallingConv::X86_StdCall: {
17315 // Pass 'nest' parameter in ECX.
17316 // Must be kept in sync with X86CallingConv.td
17317 NestReg = X86::ECX;
17319 // Check that ECX wasn't needed by an 'inreg' parameter.
17320 FunctionType *FTy = Func->getFunctionType();
17321 const AttributeSet &Attrs = Func->getAttributes();
17323 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17324 unsigned InRegCount = 0;
17327 for (FunctionType::param_iterator I = FTy->param_begin(),
17328 E = FTy->param_end(); I != E; ++I, ++Idx)
17329 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17330 // FIXME: should only count parameters that are lowered to integers.
17331 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17333 if (InRegCount > 2) {
17334 report_fatal_error("Nest register in use - reduce number of inreg"
17340 case CallingConv::X86_FastCall:
17341 case CallingConv::X86_ThisCall:
17342 case CallingConv::Fast:
17343 // Pass 'nest' parameter in EAX.
17344 // Must be kept in sync with X86CallingConv.td
17345 NestReg = X86::EAX;
17349 SDValue OutChains[4];
17350 SDValue Addr, Disp;
17352 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17353 DAG.getConstant(10, MVT::i32));
17354 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17356 // This is storing the opcode for MOV32ri.
17357 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17358 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17359 OutChains[0] = DAG.getStore(Root, dl,
17360 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17361 Trmp, MachinePointerInfo(TrmpAddr),
17364 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17365 DAG.getConstant(1, MVT::i32));
17366 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17367 MachinePointerInfo(TrmpAddr, 1),
17370 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17371 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17372 DAG.getConstant(5, MVT::i32));
17373 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17374 MachinePointerInfo(TrmpAddr, 5),
17377 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17378 DAG.getConstant(6, MVT::i32));
17379 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17380 MachinePointerInfo(TrmpAddr, 6),
17383 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17387 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17388 SelectionDAG &DAG) const {
17390 The rounding mode is in bits 11:10 of FPSR, and has the following
17392 00 Round to nearest
17397 FLT_ROUNDS, on the other hand, expects the following:
17404 To perform the conversion, we do:
17405 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17408 MachineFunction &MF = DAG.getMachineFunction();
17409 const TargetMachine &TM = MF.getTarget();
17410 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17411 unsigned StackAlignment = TFI.getStackAlignment();
17412 MVT VT = Op.getSimpleValueType();
17415 // Save FP Control Word to stack slot
17416 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17417 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17419 MachineMemOperand *MMO =
17420 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17421 MachineMemOperand::MOStore, 2, 2);
17423 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17424 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17425 DAG.getVTList(MVT::Other),
17426 Ops, MVT::i16, MMO);
17428 // Load FP Control Word from stack slot
17429 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17430 MachinePointerInfo(), false, false, false, 0);
17432 // Transform as necessary
17434 DAG.getNode(ISD::SRL, DL, MVT::i16,
17435 DAG.getNode(ISD::AND, DL, MVT::i16,
17436 CWD, DAG.getConstant(0x800, MVT::i16)),
17437 DAG.getConstant(11, MVT::i8));
17439 DAG.getNode(ISD::SRL, DL, MVT::i16,
17440 DAG.getNode(ISD::AND, DL, MVT::i16,
17441 CWD, DAG.getConstant(0x400, MVT::i16)),
17442 DAG.getConstant(9, MVT::i8));
17445 DAG.getNode(ISD::AND, DL, MVT::i16,
17446 DAG.getNode(ISD::ADD, DL, MVT::i16,
17447 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17448 DAG.getConstant(1, MVT::i16)),
17449 DAG.getConstant(3, MVT::i16));
17451 return DAG.getNode((VT.getSizeInBits() < 16 ?
17452 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17455 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17456 MVT VT = Op.getSimpleValueType();
17458 unsigned NumBits = VT.getSizeInBits();
17461 Op = Op.getOperand(0);
17462 if (VT == MVT::i8) {
17463 // Zero extend to i32 since there is not an i8 bsr.
17465 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17468 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17469 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17470 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17472 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17475 DAG.getConstant(NumBits+NumBits-1, OpVT),
17476 DAG.getConstant(X86::COND_E, MVT::i8),
17479 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17481 // Finally xor with NumBits-1.
17482 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17485 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17489 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17490 MVT VT = Op.getSimpleValueType();
17492 unsigned NumBits = VT.getSizeInBits();
17495 Op = Op.getOperand(0);
17496 if (VT == MVT::i8) {
17497 // Zero extend to i32 since there is not an i8 bsr.
17499 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17502 // Issue a bsr (scan bits in reverse).
17503 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17504 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17506 // And xor with NumBits-1.
17507 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17510 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17514 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17515 MVT VT = Op.getSimpleValueType();
17516 unsigned NumBits = VT.getSizeInBits();
17518 Op = Op.getOperand(0);
17520 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17521 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17522 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17524 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17527 DAG.getConstant(NumBits, VT),
17528 DAG.getConstant(X86::COND_E, MVT::i8),
17531 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17534 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17535 // ones, and then concatenate the result back.
17536 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17537 MVT VT = Op.getSimpleValueType();
17539 assert(VT.is256BitVector() && VT.isInteger() &&
17540 "Unsupported value type for operation");
17542 unsigned NumElems = VT.getVectorNumElements();
17545 // Extract the LHS vectors
17546 SDValue LHS = Op.getOperand(0);
17547 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17548 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17550 // Extract the RHS vectors
17551 SDValue RHS = Op.getOperand(1);
17552 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17553 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17555 MVT EltVT = VT.getVectorElementType();
17556 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17558 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17559 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17560 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17563 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17564 assert(Op.getSimpleValueType().is256BitVector() &&
17565 Op.getSimpleValueType().isInteger() &&
17566 "Only handle AVX 256-bit vector integer operation");
17567 return Lower256IntArith(Op, DAG);
17570 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17571 assert(Op.getSimpleValueType().is256BitVector() &&
17572 Op.getSimpleValueType().isInteger() &&
17573 "Only handle AVX 256-bit vector integer operation");
17574 return Lower256IntArith(Op, DAG);
17577 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17578 SelectionDAG &DAG) {
17580 MVT VT = Op.getSimpleValueType();
17582 // Decompose 256-bit ops into smaller 128-bit ops.
17583 if (VT.is256BitVector() && !Subtarget->hasInt256())
17584 return Lower256IntArith(Op, DAG);
17586 SDValue A = Op.getOperand(0);
17587 SDValue B = Op.getOperand(1);
17589 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17590 if (VT == MVT::v4i32) {
17591 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17592 "Should not custom lower when pmuldq is available!");
17594 // Extract the odd parts.
17595 static const int UnpackMask[] = { 1, -1, 3, -1 };
17596 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17597 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17599 // Multiply the even parts.
17600 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17601 // Now multiply odd parts.
17602 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17604 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17605 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17607 // Merge the two vectors back together with a shuffle. This expands into 2
17609 static const int ShufMask[] = { 0, 4, 2, 6 };
17610 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17613 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17614 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17616 // Ahi = psrlqi(a, 32);
17617 // Bhi = psrlqi(b, 32);
17619 // AloBlo = pmuludq(a, b);
17620 // AloBhi = pmuludq(a, Bhi);
17621 // AhiBlo = pmuludq(Ahi, b);
17623 // AloBhi = psllqi(AloBhi, 32);
17624 // AhiBlo = psllqi(AhiBlo, 32);
17625 // return AloBlo + AloBhi + AhiBlo;
17627 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17628 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17630 // Bit cast to 32-bit vectors for MULUDQ
17631 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17632 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17633 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17634 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17635 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17636 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17638 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17639 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17640 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17642 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17643 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17645 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17646 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17649 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17650 assert(Subtarget->isTargetWin64() && "Unexpected target");
17651 EVT VT = Op.getValueType();
17652 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17653 "Unexpected return type for lowering");
17657 switch (Op->getOpcode()) {
17658 default: llvm_unreachable("Unexpected request for libcall!");
17659 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17660 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17661 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17662 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17663 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17664 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17668 SDValue InChain = DAG.getEntryNode();
17670 TargetLowering::ArgListTy Args;
17671 TargetLowering::ArgListEntry Entry;
17672 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17673 EVT ArgVT = Op->getOperand(i).getValueType();
17674 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17675 "Unexpected argument type for lowering");
17676 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17677 Entry.Node = StackPtr;
17678 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17680 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17681 Entry.Ty = PointerType::get(ArgTy,0);
17682 Entry.isSExt = false;
17683 Entry.isZExt = false;
17684 Args.push_back(Entry);
17687 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17690 TargetLowering::CallLoweringInfo CLI(DAG);
17691 CLI.setDebugLoc(dl).setChain(InChain)
17692 .setCallee(getLibcallCallingConv(LC),
17693 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17694 Callee, std::move(Args), 0)
17695 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17697 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17698 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17701 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17702 SelectionDAG &DAG) {
17703 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17704 EVT VT = Op0.getValueType();
17707 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17708 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17710 // PMULxD operations multiply each even value (starting at 0) of LHS with
17711 // the related value of RHS and produce a widen result.
17712 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17713 // => <2 x i64> <ae|cg>
17715 // In other word, to have all the results, we need to perform two PMULxD:
17716 // 1. one with the even values.
17717 // 2. one with the odd values.
17718 // To achieve #2, with need to place the odd values at an even position.
17720 // Place the odd value at an even position (basically, shift all values 1
17721 // step to the left):
17722 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17723 // <a|b|c|d> => <b|undef|d|undef>
17724 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17725 // <e|f|g|h> => <f|undef|h|undef>
17726 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17728 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17730 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17731 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17733 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17734 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17735 // => <2 x i64> <ae|cg>
17736 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17737 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17738 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17739 // => <2 x i64> <bf|dh>
17740 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17741 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17743 // Shuffle it back into the right order.
17744 SDValue Highs, Lows;
17745 if (VT == MVT::v8i32) {
17746 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17747 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17748 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17749 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17751 const int HighMask[] = {1, 5, 3, 7};
17752 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17753 const int LowMask[] = {0, 4, 2, 6};
17754 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17757 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17758 // unsigned multiply.
17759 if (IsSigned && !Subtarget->hasSSE41()) {
17761 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17762 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17763 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17764 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17765 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17767 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17768 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17771 // The first result of MUL_LOHI is actually the low value, followed by the
17773 SDValue Ops[] = {Lows, Highs};
17774 return DAG.getMergeValues(Ops, dl);
17777 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17778 const X86Subtarget *Subtarget) {
17779 MVT VT = Op.getSimpleValueType();
17781 SDValue R = Op.getOperand(0);
17782 SDValue Amt = Op.getOperand(1);
17784 // Optimize shl/srl/sra with constant shift amount.
17785 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17786 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17787 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17789 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17790 (Subtarget->hasInt256() &&
17791 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17792 (Subtarget->hasAVX512() &&
17793 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17794 if (Op.getOpcode() == ISD::SHL)
17795 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17797 if (Op.getOpcode() == ISD::SRL)
17798 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17800 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17801 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17805 if (VT == MVT::v16i8) {
17806 if (Op.getOpcode() == ISD::SHL) {
17807 // Make a large shift.
17808 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17809 MVT::v8i16, R, ShiftAmt,
17811 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17812 // Zero out the rightmost bits.
17813 SmallVector<SDValue, 16> V(16,
17814 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17816 return DAG.getNode(ISD::AND, dl, VT, SHL,
17817 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17819 if (Op.getOpcode() == ISD::SRL) {
17820 // Make a large shift.
17821 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17822 MVT::v8i16, R, ShiftAmt,
17824 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17825 // Zero out the leftmost bits.
17826 SmallVector<SDValue, 16> V(16,
17827 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17829 return DAG.getNode(ISD::AND, dl, VT, SRL,
17830 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17832 if (Op.getOpcode() == ISD::SRA) {
17833 if (ShiftAmt == 7) {
17834 // R s>> 7 === R s< 0
17835 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17836 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17839 // R s>> a === ((R u>> a) ^ m) - m
17840 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17841 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17843 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17844 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17845 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17848 llvm_unreachable("Unknown shift opcode.");
17851 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17852 if (Op.getOpcode() == ISD::SHL) {
17853 // Make a large shift.
17854 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17855 MVT::v16i16, R, ShiftAmt,
17857 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17858 // Zero out the rightmost bits.
17859 SmallVector<SDValue, 32> V(32,
17860 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17862 return DAG.getNode(ISD::AND, dl, VT, SHL,
17863 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17865 if (Op.getOpcode() == ISD::SRL) {
17866 // Make a large shift.
17867 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17868 MVT::v16i16, R, ShiftAmt,
17870 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17871 // Zero out the leftmost bits.
17872 SmallVector<SDValue, 32> V(32,
17873 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17875 return DAG.getNode(ISD::AND, dl, VT, SRL,
17876 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17878 if (Op.getOpcode() == ISD::SRA) {
17879 if (ShiftAmt == 7) {
17880 // R s>> 7 === R s< 0
17881 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17882 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17885 // R s>> a === ((R u>> a) ^ m) - m
17886 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17887 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17889 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17890 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17891 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17894 llvm_unreachable("Unknown shift opcode.");
17899 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17900 if (!Subtarget->is64Bit() &&
17901 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17902 Amt.getOpcode() == ISD::BITCAST &&
17903 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17904 Amt = Amt.getOperand(0);
17905 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17906 VT.getVectorNumElements();
17907 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17908 uint64_t ShiftAmt = 0;
17909 for (unsigned i = 0; i != Ratio; ++i) {
17910 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17914 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17916 // Check remaining shift amounts.
17917 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17918 uint64_t ShAmt = 0;
17919 for (unsigned j = 0; j != Ratio; ++j) {
17920 ConstantSDNode *C =
17921 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17925 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17927 if (ShAmt != ShiftAmt)
17930 switch (Op.getOpcode()) {
17932 llvm_unreachable("Unknown shift opcode!");
17934 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17937 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17940 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17948 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17949 const X86Subtarget* Subtarget) {
17950 MVT VT = Op.getSimpleValueType();
17952 SDValue R = Op.getOperand(0);
17953 SDValue Amt = Op.getOperand(1);
17955 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17956 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17957 (Subtarget->hasInt256() &&
17958 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17959 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17960 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17962 EVT EltVT = VT.getVectorElementType();
17964 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17965 unsigned NumElts = VT.getVectorNumElements();
17967 for (i = 0; i != NumElts; ++i) {
17968 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17972 for (j = i; j != NumElts; ++j) {
17973 SDValue Arg = Amt.getOperand(j);
17974 if (Arg.getOpcode() == ISD::UNDEF) continue;
17975 if (Arg != Amt.getOperand(i))
17978 if (i != NumElts && j == NumElts)
17979 BaseShAmt = Amt.getOperand(i);
17981 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17982 Amt = Amt.getOperand(0);
17983 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17984 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17985 SDValue InVec = Amt.getOperand(0);
17986 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17987 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17989 for (; i != NumElts; ++i) {
17990 SDValue Arg = InVec.getOperand(i);
17991 if (Arg.getOpcode() == ISD::UNDEF) continue;
17995 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17996 if (ConstantSDNode *C =
17997 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17998 unsigned SplatIdx =
17999 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18000 if (C->getZExtValue() == SplatIdx)
18001 BaseShAmt = InVec.getOperand(1);
18004 if (!BaseShAmt.getNode())
18005 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18006 DAG.getIntPtrConstant(0));
18010 if (BaseShAmt.getNode()) {
18011 if (EltVT.bitsGT(MVT::i32))
18012 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18013 else if (EltVT.bitsLT(MVT::i32))
18014 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18016 switch (Op.getOpcode()) {
18018 llvm_unreachable("Unknown shift opcode!");
18020 switch (VT.SimpleTy) {
18021 default: return SDValue();
18030 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18033 switch (VT.SimpleTy) {
18034 default: return SDValue();
18041 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18044 switch (VT.SimpleTy) {
18045 default: return SDValue();
18054 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18060 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18061 if (!Subtarget->is64Bit() &&
18062 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18063 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18064 Amt.getOpcode() == ISD::BITCAST &&
18065 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18066 Amt = Amt.getOperand(0);
18067 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18068 VT.getVectorNumElements();
18069 std::vector<SDValue> Vals(Ratio);
18070 for (unsigned i = 0; i != Ratio; ++i)
18071 Vals[i] = Amt.getOperand(i);
18072 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18073 for (unsigned j = 0; j != Ratio; ++j)
18074 if (Vals[j] != Amt.getOperand(i + j))
18077 switch (Op.getOpcode()) {
18079 llvm_unreachable("Unknown shift opcode!");
18081 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18083 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18085 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18092 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18093 SelectionDAG &DAG) {
18094 MVT VT = Op.getSimpleValueType();
18096 SDValue R = Op.getOperand(0);
18097 SDValue Amt = Op.getOperand(1);
18100 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18101 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18103 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18107 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18111 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18113 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18114 if (Subtarget->hasInt256()) {
18115 if (Op.getOpcode() == ISD::SRL &&
18116 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18117 VT == MVT::v4i64 || VT == MVT::v8i32))
18119 if (Op.getOpcode() == ISD::SHL &&
18120 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18121 VT == MVT::v4i64 || VT == MVT::v8i32))
18123 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18127 // If possible, lower this packed shift into a vector multiply instead of
18128 // expanding it into a sequence of scalar shifts.
18129 // Do this only if the vector shift count is a constant build_vector.
18130 if (Op.getOpcode() == ISD::SHL &&
18131 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18132 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18133 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18134 SmallVector<SDValue, 8> Elts;
18135 EVT SVT = VT.getScalarType();
18136 unsigned SVTBits = SVT.getSizeInBits();
18137 const APInt &One = APInt(SVTBits, 1);
18138 unsigned NumElems = VT.getVectorNumElements();
18140 for (unsigned i=0; i !=NumElems; ++i) {
18141 SDValue Op = Amt->getOperand(i);
18142 if (Op->getOpcode() == ISD::UNDEF) {
18143 Elts.push_back(Op);
18147 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18148 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18149 uint64_t ShAmt = C.getZExtValue();
18150 if (ShAmt >= SVTBits) {
18151 Elts.push_back(DAG.getUNDEF(SVT));
18154 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18156 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18157 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18160 // Lower SHL with variable shift amount.
18161 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18162 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18164 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18165 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18166 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18167 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18170 // If possible, lower this shift as a sequence of two shifts by
18171 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18173 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18175 // Could be rewritten as:
18176 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18178 // The advantage is that the two shifts from the example would be
18179 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18180 // the vector shift into four scalar shifts plus four pairs of vector
18182 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18183 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18184 unsigned TargetOpcode = X86ISD::MOVSS;
18185 bool CanBeSimplified;
18186 // The splat value for the first packed shift (the 'X' from the example).
18187 SDValue Amt1 = Amt->getOperand(0);
18188 // The splat value for the second packed shift (the 'Y' from the example).
18189 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18190 Amt->getOperand(2);
18192 // See if it is possible to replace this node with a sequence of
18193 // two shifts followed by a MOVSS/MOVSD
18194 if (VT == MVT::v4i32) {
18195 // Check if it is legal to use a MOVSS.
18196 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18197 Amt2 == Amt->getOperand(3);
18198 if (!CanBeSimplified) {
18199 // Otherwise, check if we can still simplify this node using a MOVSD.
18200 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18201 Amt->getOperand(2) == Amt->getOperand(3);
18202 TargetOpcode = X86ISD::MOVSD;
18203 Amt2 = Amt->getOperand(2);
18206 // Do similar checks for the case where the machine value type
18208 CanBeSimplified = Amt1 == Amt->getOperand(1);
18209 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18210 CanBeSimplified = Amt2 == Amt->getOperand(i);
18212 if (!CanBeSimplified) {
18213 TargetOpcode = X86ISD::MOVSD;
18214 CanBeSimplified = true;
18215 Amt2 = Amt->getOperand(4);
18216 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18217 CanBeSimplified = Amt1 == Amt->getOperand(i);
18218 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18219 CanBeSimplified = Amt2 == Amt->getOperand(j);
18223 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18224 isa<ConstantSDNode>(Amt2)) {
18225 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18226 EVT CastVT = MVT::v4i32;
18228 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18229 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18231 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18232 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18233 if (TargetOpcode == X86ISD::MOVSD)
18234 CastVT = MVT::v2i64;
18235 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18236 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18237 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18239 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18243 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18244 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18247 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18248 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18250 // Turn 'a' into a mask suitable for VSELECT
18251 SDValue VSelM = DAG.getConstant(0x80, VT);
18252 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18253 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18255 SDValue CM1 = DAG.getConstant(0x0f, VT);
18256 SDValue CM2 = DAG.getConstant(0x3f, VT);
18258 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18259 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18260 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18261 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18262 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18265 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18266 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18267 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18269 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18270 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18271 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18272 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18273 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18276 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18277 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18278 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18280 // return VSELECT(r, r+r, a);
18281 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18282 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18286 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18287 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18288 // solution better.
18289 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18290 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18292 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18293 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18294 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18295 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18296 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18299 // Decompose 256-bit shifts into smaller 128-bit shifts.
18300 if (VT.is256BitVector()) {
18301 unsigned NumElems = VT.getVectorNumElements();
18302 MVT EltVT = VT.getVectorElementType();
18303 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18305 // Extract the two vectors
18306 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18307 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18309 // Recreate the shift amount vectors
18310 SDValue Amt1, Amt2;
18311 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18312 // Constant shift amount
18313 SmallVector<SDValue, 4> Amt1Csts;
18314 SmallVector<SDValue, 4> Amt2Csts;
18315 for (unsigned i = 0; i != NumElems/2; ++i)
18316 Amt1Csts.push_back(Amt->getOperand(i));
18317 for (unsigned i = NumElems/2; i != NumElems; ++i)
18318 Amt2Csts.push_back(Amt->getOperand(i));
18320 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18321 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18323 // Variable shift amount
18324 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18325 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18328 // Issue new vector shifts for the smaller types
18329 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18330 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18332 // Concatenate the result back
18333 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18339 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18340 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18341 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18342 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18343 // has only one use.
18344 SDNode *N = Op.getNode();
18345 SDValue LHS = N->getOperand(0);
18346 SDValue RHS = N->getOperand(1);
18347 unsigned BaseOp = 0;
18350 switch (Op.getOpcode()) {
18351 default: llvm_unreachable("Unknown ovf instruction!");
18353 // A subtract of one will be selected as a INC. Note that INC doesn't
18354 // set CF, so we can't do this for UADDO.
18355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18357 BaseOp = X86ISD::INC;
18358 Cond = X86::COND_O;
18361 BaseOp = X86ISD::ADD;
18362 Cond = X86::COND_O;
18365 BaseOp = X86ISD::ADD;
18366 Cond = X86::COND_B;
18369 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18370 // set CF, so we can't do this for USUBO.
18371 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18373 BaseOp = X86ISD::DEC;
18374 Cond = X86::COND_O;
18377 BaseOp = X86ISD::SUB;
18378 Cond = X86::COND_O;
18381 BaseOp = X86ISD::SUB;
18382 Cond = X86::COND_B;
18385 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18386 Cond = X86::COND_O;
18388 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18389 if (N->getValueType(0) == MVT::i8) {
18390 BaseOp = X86ISD::UMUL8;
18391 Cond = X86::COND_O;
18394 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18396 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18399 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18400 DAG.getConstant(X86::COND_O, MVT::i32),
18401 SDValue(Sum.getNode(), 2));
18403 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18407 // Also sets EFLAGS.
18408 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18409 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18412 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18413 DAG.getConstant(Cond, MVT::i32),
18414 SDValue(Sum.getNode(), 1));
18416 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18419 // Sign extension of the low part of vector elements. This may be used either
18420 // when sign extend instructions are not available or if the vector element
18421 // sizes already match the sign-extended size. If the vector elements are in
18422 // their pre-extended size and sign extend instructions are available, that will
18423 // be handled by LowerSIGN_EXTEND.
18424 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18425 SelectionDAG &DAG) const {
18427 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18428 MVT VT = Op.getSimpleValueType();
18430 if (!Subtarget->hasSSE2() || !VT.isVector())
18433 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18434 ExtraVT.getScalarType().getSizeInBits();
18436 switch (VT.SimpleTy) {
18437 default: return SDValue();
18440 if (!Subtarget->hasFp256())
18442 if (!Subtarget->hasInt256()) {
18443 // needs to be split
18444 unsigned NumElems = VT.getVectorNumElements();
18446 // Extract the LHS vectors
18447 SDValue LHS = Op.getOperand(0);
18448 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18449 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18451 MVT EltVT = VT.getVectorElementType();
18452 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18454 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18455 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18456 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18458 SDValue Extra = DAG.getValueType(ExtraVT);
18460 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18461 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18463 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18468 SDValue Op0 = Op.getOperand(0);
18470 // This is a sign extension of some low part of vector elements without
18471 // changing the size of the vector elements themselves:
18472 // Shift-Left + Shift-Right-Algebraic.
18473 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18475 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18481 /// Returns true if the operand type is exactly twice the native width, and
18482 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18483 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18484 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18485 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18486 const X86Subtarget &Subtarget =
18487 getTargetMachine().getSubtarget<X86Subtarget>();
18488 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18491 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18492 else if (OpWidth == 128)
18493 return Subtarget.hasCmpxchg16b();
18498 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18499 return needsCmpXchgNb(SI->getValueOperand()->getType());
18502 // Note: this turns large loads into lock cmpxchg8b/16b.
18503 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18504 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18505 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18506 return needsCmpXchgNb(PTy->getElementType());
18509 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18510 const X86Subtarget &Subtarget =
18511 getTargetMachine().getSubtarget<X86Subtarget>();
18512 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18513 const Type *MemType = AI->getType();
18515 // If the operand is too big, we must see if cmpxchg8/16b is available
18516 // and default to library calls otherwise.
18517 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18518 return needsCmpXchgNb(MemType);
18520 AtomicRMWInst::BinOp Op = AI->getOperation();
18523 llvm_unreachable("Unknown atomic operation");
18524 case AtomicRMWInst::Xchg:
18525 case AtomicRMWInst::Add:
18526 case AtomicRMWInst::Sub:
18527 // It's better to use xadd, xsub or xchg for these in all cases.
18529 case AtomicRMWInst::Or:
18530 case AtomicRMWInst::And:
18531 case AtomicRMWInst::Xor:
18532 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18533 // prefix to a normal instruction for these operations.
18534 return !AI->use_empty();
18535 case AtomicRMWInst::Nand:
18536 case AtomicRMWInst::Max:
18537 case AtomicRMWInst::Min:
18538 case AtomicRMWInst::UMax:
18539 case AtomicRMWInst::UMin:
18540 // These always require a non-trivial set of data operations on x86. We must
18541 // use a cmpxchg loop.
18546 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18547 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18548 // no-sse2). There isn't any reason to disable it if the target processor
18550 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18554 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18555 const X86Subtarget &Subtarget =
18556 getTargetMachine().getSubtarget<X86Subtarget>();
18557 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18558 const Type *MemType = AI->getType();
18559 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18560 // there is no benefit in turning such RMWs into loads, and it is actually
18561 // harmful as it introduces a mfence.
18562 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18565 auto Builder = IRBuilder<>(AI);
18566 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18567 auto SynchScope = AI->getSynchScope();
18568 // We must restrict the ordering to avoid generating loads with Release or
18569 // ReleaseAcquire orderings.
18570 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18571 auto Ptr = AI->getPointerOperand();
18573 // Before the load we need a fence. Here is an example lifted from
18574 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18577 // x.store(1, relaxed);
18578 // r1 = y.fetch_add(0, release);
18580 // y.fetch_add(42, acquire);
18581 // r2 = x.load(relaxed);
18582 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18583 // lowered to just a load without a fence. A mfence flushes the store buffer,
18584 // making the optimization clearly correct.
18585 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18586 // otherwise, we might be able to be more agressive on relaxed idempotent
18587 // rmw. In practice, they do not look useful, so we don't try to be
18588 // especially clever.
18589 if (SynchScope == SingleThread) {
18590 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18591 // the IR level, so we must wrap it in an intrinsic.
18593 } else if (hasMFENCE(Subtarget)) {
18594 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18595 Intrinsic::x86_sse2_mfence);
18596 Builder.CreateCall(MFence);
18598 // FIXME: it might make sense to use a locked operation here but on a
18599 // different cache-line to prevent cache-line bouncing. In practice it
18600 // is probably a small win, and x86 processors without mfence are rare
18601 // enough that we do not bother.
18605 // Finally we can emit the atomic load.
18606 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18607 AI->getType()->getPrimitiveSizeInBits());
18608 Loaded->setAtomic(Order, SynchScope);
18609 AI->replaceAllUsesWith(Loaded);
18610 AI->eraseFromParent();
18614 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18615 SelectionDAG &DAG) {
18617 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18618 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18619 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18620 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18622 // The only fence that needs an instruction is a sequentially-consistent
18623 // cross-thread fence.
18624 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18625 if (hasMFENCE(*Subtarget))
18626 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18628 SDValue Chain = Op.getOperand(0);
18629 SDValue Zero = DAG.getConstant(0, MVT::i32);
18631 DAG.getRegister(X86::ESP, MVT::i32), // Base
18632 DAG.getTargetConstant(1, MVT::i8), // Scale
18633 DAG.getRegister(0, MVT::i32), // Index
18634 DAG.getTargetConstant(0, MVT::i32), // Disp
18635 DAG.getRegister(0, MVT::i32), // Segment.
18639 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18640 return SDValue(Res, 0);
18643 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18644 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18647 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18648 SelectionDAG &DAG) {
18649 MVT T = Op.getSimpleValueType();
18653 switch(T.SimpleTy) {
18654 default: llvm_unreachable("Invalid value type!");
18655 case MVT::i8: Reg = X86::AL; size = 1; break;
18656 case MVT::i16: Reg = X86::AX; size = 2; break;
18657 case MVT::i32: Reg = X86::EAX; size = 4; break;
18659 assert(Subtarget->is64Bit() && "Node not type legal!");
18660 Reg = X86::RAX; size = 8;
18663 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18664 Op.getOperand(2), SDValue());
18665 SDValue Ops[] = { cpIn.getValue(0),
18668 DAG.getTargetConstant(size, MVT::i8),
18669 cpIn.getValue(1) };
18670 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18671 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18672 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18676 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18677 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18678 MVT::i32, cpOut.getValue(2));
18679 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18680 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18682 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18683 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18684 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18688 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18689 SelectionDAG &DAG) {
18690 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18691 MVT DstVT = Op.getSimpleValueType();
18693 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18694 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18695 if (DstVT != MVT::f64)
18696 // This conversion needs to be expanded.
18699 SDValue InVec = Op->getOperand(0);
18701 unsigned NumElts = SrcVT.getVectorNumElements();
18702 EVT SVT = SrcVT.getVectorElementType();
18704 // Widen the vector in input in the case of MVT::v2i32.
18705 // Example: from MVT::v2i32 to MVT::v4i32.
18706 SmallVector<SDValue, 16> Elts;
18707 for (unsigned i = 0, e = NumElts; i != e; ++i)
18708 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18709 DAG.getIntPtrConstant(i)));
18711 // Explicitly mark the extra elements as Undef.
18712 SDValue Undef = DAG.getUNDEF(SVT);
18713 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18714 Elts.push_back(Undef);
18716 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18717 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18718 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18719 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18720 DAG.getIntPtrConstant(0));
18723 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18724 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18725 assert((DstVT == MVT::i64 ||
18726 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18727 "Unexpected custom BITCAST");
18728 // i64 <=> MMX conversions are Legal.
18729 if (SrcVT==MVT::i64 && DstVT.isVector())
18731 if (DstVT==MVT::i64 && SrcVT.isVector())
18733 // MMX <=> MMX conversions are Legal.
18734 if (SrcVT.isVector() && DstVT.isVector())
18736 // All other conversions need to be expanded.
18740 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18741 SDNode *Node = Op.getNode();
18743 EVT T = Node->getValueType(0);
18744 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18745 DAG.getConstant(0, T), Node->getOperand(2));
18746 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18747 cast<AtomicSDNode>(Node)->getMemoryVT(),
18748 Node->getOperand(0),
18749 Node->getOperand(1), negOp,
18750 cast<AtomicSDNode>(Node)->getMemOperand(),
18751 cast<AtomicSDNode>(Node)->getOrdering(),
18752 cast<AtomicSDNode>(Node)->getSynchScope());
18755 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18756 SDNode *Node = Op.getNode();
18758 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18760 // Convert seq_cst store -> xchg
18761 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18762 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18763 // (The only way to get a 16-byte store is cmpxchg16b)
18764 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18765 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18766 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18767 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18768 cast<AtomicSDNode>(Node)->getMemoryVT(),
18769 Node->getOperand(0),
18770 Node->getOperand(1), Node->getOperand(2),
18771 cast<AtomicSDNode>(Node)->getMemOperand(),
18772 cast<AtomicSDNode>(Node)->getOrdering(),
18773 cast<AtomicSDNode>(Node)->getSynchScope());
18774 return Swap.getValue(1);
18776 // Other atomic stores have a simple pattern.
18780 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18781 EVT VT = Op.getNode()->getSimpleValueType(0);
18783 // Let legalize expand this if it isn't a legal type yet.
18784 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18787 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18790 bool ExtraOp = false;
18791 switch (Op.getOpcode()) {
18792 default: llvm_unreachable("Invalid code");
18793 case ISD::ADDC: Opc = X86ISD::ADD; break;
18794 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18795 case ISD::SUBC: Opc = X86ISD::SUB; break;
18796 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18800 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18802 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18803 Op.getOperand(1), Op.getOperand(2));
18806 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18807 SelectionDAG &DAG) {
18808 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18810 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18811 // which returns the values as { float, float } (in XMM0) or
18812 // { double, double } (which is returned in XMM0, XMM1).
18814 SDValue Arg = Op.getOperand(0);
18815 EVT ArgVT = Arg.getValueType();
18816 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18818 TargetLowering::ArgListTy Args;
18819 TargetLowering::ArgListEntry Entry;
18823 Entry.isSExt = false;
18824 Entry.isZExt = false;
18825 Args.push_back(Entry);
18827 bool isF64 = ArgVT == MVT::f64;
18828 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18829 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18830 // the results are returned via SRet in memory.
18831 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18832 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18833 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18835 Type *RetTy = isF64
18836 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18837 : (Type*)VectorType::get(ArgTy, 4);
18839 TargetLowering::CallLoweringInfo CLI(DAG);
18840 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18841 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18843 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18846 // Returned in xmm0 and xmm1.
18847 return CallResult.first;
18849 // Returned in bits 0:31 and 32:64 xmm0.
18850 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18851 CallResult.first, DAG.getIntPtrConstant(0));
18852 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18853 CallResult.first, DAG.getIntPtrConstant(1));
18854 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18855 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18858 /// LowerOperation - Provide custom lowering hooks for some operations.
18860 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18861 switch (Op.getOpcode()) {
18862 default: llvm_unreachable("Should not custom lower this!");
18863 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18864 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18865 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18866 return LowerCMP_SWAP(Op, Subtarget, DAG);
18867 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18868 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18869 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18870 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18871 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18872 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18873 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18874 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18875 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18876 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18877 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18878 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18879 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18880 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18881 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18882 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18883 case ISD::SHL_PARTS:
18884 case ISD::SRA_PARTS:
18885 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18886 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18887 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18888 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18889 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18890 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18891 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18892 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18893 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18894 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18895 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18897 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18898 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18899 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18900 case ISD::SETCC: return LowerSETCC(Op, DAG);
18901 case ISD::SELECT: return LowerSELECT(Op, DAG);
18902 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18903 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18904 case ISD::VASTART: return LowerVASTART(Op, DAG);
18905 case ISD::VAARG: return LowerVAARG(Op, DAG);
18906 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18907 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18908 case ISD::INTRINSIC_VOID:
18909 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18910 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18911 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18912 case ISD::FRAME_TO_ARGS_OFFSET:
18913 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18914 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18915 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18916 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18917 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18918 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18919 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18920 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18921 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18922 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18923 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18924 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18925 case ISD::UMUL_LOHI:
18926 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18929 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18935 case ISD::UMULO: return LowerXALUO(Op, DAG);
18936 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18937 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18941 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18942 case ISD::ADD: return LowerADD(Op, DAG);
18943 case ISD::SUB: return LowerSUB(Op, DAG);
18944 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18948 /// ReplaceNodeResults - Replace a node with an illegal result type
18949 /// with a new node built out of custom code.
18950 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18951 SmallVectorImpl<SDValue>&Results,
18952 SelectionDAG &DAG) const {
18954 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18955 switch (N->getOpcode()) {
18957 llvm_unreachable("Do not know how to custom type legalize this operation!");
18958 case ISD::SIGN_EXTEND_INREG:
18963 // We don't want to expand or promote these.
18970 case ISD::UDIVREM: {
18971 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18972 Results.push_back(V);
18975 case ISD::FP_TO_SINT:
18976 case ISD::FP_TO_UINT: {
18977 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18979 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18982 std::pair<SDValue,SDValue> Vals =
18983 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18984 SDValue FIST = Vals.first, StackSlot = Vals.second;
18985 if (FIST.getNode()) {
18986 EVT VT = N->getValueType(0);
18987 // Return a load from the stack slot.
18988 if (StackSlot.getNode())
18989 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18990 MachinePointerInfo(),
18991 false, false, false, 0));
18993 Results.push_back(FIST);
18997 case ISD::UINT_TO_FP: {
18998 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18999 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19000 N->getValueType(0) != MVT::v2f32)
19002 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19004 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19006 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19007 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19008 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19009 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19010 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19011 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19014 case ISD::FP_ROUND: {
19015 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19017 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19018 Results.push_back(V);
19021 case ISD::INTRINSIC_W_CHAIN: {
19022 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19024 default : llvm_unreachable("Do not know how to custom type "
19025 "legalize this intrinsic operation!");
19026 case Intrinsic::x86_rdtsc:
19027 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19029 case Intrinsic::x86_rdtscp:
19030 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19032 case Intrinsic::x86_rdpmc:
19033 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19036 case ISD::READCYCLECOUNTER: {
19037 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19040 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19041 EVT T = N->getValueType(0);
19042 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19043 bool Regs64bit = T == MVT::i128;
19044 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19045 SDValue cpInL, cpInH;
19046 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19047 DAG.getConstant(0, HalfT));
19048 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19049 DAG.getConstant(1, HalfT));
19050 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19051 Regs64bit ? X86::RAX : X86::EAX,
19053 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19054 Regs64bit ? X86::RDX : X86::EDX,
19055 cpInH, cpInL.getValue(1));
19056 SDValue swapInL, swapInH;
19057 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19058 DAG.getConstant(0, HalfT));
19059 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19060 DAG.getConstant(1, HalfT));
19061 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19062 Regs64bit ? X86::RBX : X86::EBX,
19063 swapInL, cpInH.getValue(1));
19064 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19065 Regs64bit ? X86::RCX : X86::ECX,
19066 swapInH, swapInL.getValue(1));
19067 SDValue Ops[] = { swapInH.getValue(0),
19069 swapInH.getValue(1) };
19070 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19071 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19072 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19073 X86ISD::LCMPXCHG8_DAG;
19074 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19075 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19076 Regs64bit ? X86::RAX : X86::EAX,
19077 HalfT, Result.getValue(1));
19078 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19079 Regs64bit ? X86::RDX : X86::EDX,
19080 HalfT, cpOutL.getValue(2));
19081 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19083 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19084 MVT::i32, cpOutH.getValue(2));
19086 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19087 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19088 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19090 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19091 Results.push_back(Success);
19092 Results.push_back(EFLAGS.getValue(1));
19095 case ISD::ATOMIC_SWAP:
19096 case ISD::ATOMIC_LOAD_ADD:
19097 case ISD::ATOMIC_LOAD_SUB:
19098 case ISD::ATOMIC_LOAD_AND:
19099 case ISD::ATOMIC_LOAD_OR:
19100 case ISD::ATOMIC_LOAD_XOR:
19101 case ISD::ATOMIC_LOAD_NAND:
19102 case ISD::ATOMIC_LOAD_MIN:
19103 case ISD::ATOMIC_LOAD_MAX:
19104 case ISD::ATOMIC_LOAD_UMIN:
19105 case ISD::ATOMIC_LOAD_UMAX:
19106 case ISD::ATOMIC_LOAD: {
19107 // Delegate to generic TypeLegalization. Situations we can really handle
19108 // should have already been dealt with by AtomicExpandPass.cpp.
19111 case ISD::BITCAST: {
19112 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19113 EVT DstVT = N->getValueType(0);
19114 EVT SrcVT = N->getOperand(0)->getValueType(0);
19116 if (SrcVT != MVT::f64 ||
19117 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19120 unsigned NumElts = DstVT.getVectorNumElements();
19121 EVT SVT = DstVT.getVectorElementType();
19122 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19123 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19124 MVT::v2f64, N->getOperand(0));
19125 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19127 if (ExperimentalVectorWideningLegalization) {
19128 // If we are legalizing vectors by widening, we already have the desired
19129 // legal vector type, just return it.
19130 Results.push_back(ToVecInt);
19134 SmallVector<SDValue, 8> Elts;
19135 for (unsigned i = 0, e = NumElts; i != e; ++i)
19136 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19137 ToVecInt, DAG.getIntPtrConstant(i)));
19139 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19144 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19146 default: return nullptr;
19147 case X86ISD::BSF: return "X86ISD::BSF";
19148 case X86ISD::BSR: return "X86ISD::BSR";
19149 case X86ISD::SHLD: return "X86ISD::SHLD";
19150 case X86ISD::SHRD: return "X86ISD::SHRD";
19151 case X86ISD::FAND: return "X86ISD::FAND";
19152 case X86ISD::FANDN: return "X86ISD::FANDN";
19153 case X86ISD::FOR: return "X86ISD::FOR";
19154 case X86ISD::FXOR: return "X86ISD::FXOR";
19155 case X86ISD::FSRL: return "X86ISD::FSRL";
19156 case X86ISD::FILD: return "X86ISD::FILD";
19157 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19158 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19159 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19160 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19161 case X86ISD::FLD: return "X86ISD::FLD";
19162 case X86ISD::FST: return "X86ISD::FST";
19163 case X86ISD::CALL: return "X86ISD::CALL";
19164 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19165 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19166 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19167 case X86ISD::BT: return "X86ISD::BT";
19168 case X86ISD::CMP: return "X86ISD::CMP";
19169 case X86ISD::COMI: return "X86ISD::COMI";
19170 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19171 case X86ISD::CMPM: return "X86ISD::CMPM";
19172 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19173 case X86ISD::SETCC: return "X86ISD::SETCC";
19174 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19175 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19176 case X86ISD::CMOV: return "X86ISD::CMOV";
19177 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19178 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19179 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19180 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19181 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19182 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19183 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19184 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19185 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19186 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19187 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19188 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19189 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19190 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19191 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19192 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19193 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19194 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19195 case X86ISD::HADD: return "X86ISD::HADD";
19196 case X86ISD::HSUB: return "X86ISD::HSUB";
19197 case X86ISD::FHADD: return "X86ISD::FHADD";
19198 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19199 case X86ISD::UMAX: return "X86ISD::UMAX";
19200 case X86ISD::UMIN: return "X86ISD::UMIN";
19201 case X86ISD::SMAX: return "X86ISD::SMAX";
19202 case X86ISD::SMIN: return "X86ISD::SMIN";
19203 case X86ISD::FMAX: return "X86ISD::FMAX";
19204 case X86ISD::FMIN: return "X86ISD::FMIN";
19205 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19206 case X86ISD::FMINC: return "X86ISD::FMINC";
19207 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19208 case X86ISD::FRCP: return "X86ISD::FRCP";
19209 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19210 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19211 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19212 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19213 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19214 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19215 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19216 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19217 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19218 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19219 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19220 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19221 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19222 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19223 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19224 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19225 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19226 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19227 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19228 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19229 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19230 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19231 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19232 case X86ISD::VSHL: return "X86ISD::VSHL";
19233 case X86ISD::VSRL: return "X86ISD::VSRL";
19234 case X86ISD::VSRA: return "X86ISD::VSRA";
19235 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19236 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19237 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19238 case X86ISD::CMPP: return "X86ISD::CMPP";
19239 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19240 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19241 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19242 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19243 case X86ISD::ADD: return "X86ISD::ADD";
19244 case X86ISD::SUB: return "X86ISD::SUB";
19245 case X86ISD::ADC: return "X86ISD::ADC";
19246 case X86ISD::SBB: return "X86ISD::SBB";
19247 case X86ISD::SMUL: return "X86ISD::SMUL";
19248 case X86ISD::UMUL: return "X86ISD::UMUL";
19249 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19250 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19251 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19252 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19253 case X86ISD::INC: return "X86ISD::INC";
19254 case X86ISD::DEC: return "X86ISD::DEC";
19255 case X86ISD::OR: return "X86ISD::OR";
19256 case X86ISD::XOR: return "X86ISD::XOR";
19257 case X86ISD::AND: return "X86ISD::AND";
19258 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19259 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19260 case X86ISD::PTEST: return "X86ISD::PTEST";
19261 case X86ISD::TESTP: return "X86ISD::TESTP";
19262 case X86ISD::TESTM: return "X86ISD::TESTM";
19263 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19264 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19265 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19266 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19267 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19268 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19269 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19270 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19271 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19272 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19273 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19274 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19275 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19276 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19277 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19278 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19279 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19280 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19281 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19282 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19283 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19284 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19285 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19286 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19287 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19288 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19289 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19290 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19291 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19292 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19293 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19294 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19295 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19296 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19297 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19298 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19299 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19300 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19301 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19302 case X86ISD::SAHF: return "X86ISD::SAHF";
19303 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19304 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19305 case X86ISD::FMADD: return "X86ISD::FMADD";
19306 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19307 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19308 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19309 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19310 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19311 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19312 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19313 case X86ISD::XTEST: return "X86ISD::XTEST";
19317 // isLegalAddressingMode - Return true if the addressing mode represented
19318 // by AM is legal for this target, for a load/store of the specified type.
19319 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19321 // X86 supports extremely general addressing modes.
19322 CodeModel::Model M = getTargetMachine().getCodeModel();
19323 Reloc::Model R = getTargetMachine().getRelocationModel();
19325 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19326 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19331 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19333 // If a reference to this global requires an extra load, we can't fold it.
19334 if (isGlobalStubReference(GVFlags))
19337 // If BaseGV requires a register for the PIC base, we cannot also have a
19338 // BaseReg specified.
19339 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19342 // If lower 4G is not available, then we must use rip-relative addressing.
19343 if ((M != CodeModel::Small || R != Reloc::Static) &&
19344 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19348 switch (AM.Scale) {
19354 // These scales always work.
19359 // These scales are formed with basereg+scalereg. Only accept if there is
19364 default: // Other stuff never works.
19371 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19372 unsigned Bits = Ty->getScalarSizeInBits();
19374 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19375 // particularly cheaper than those without.
19379 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19380 // variable shifts just as cheap as scalar ones.
19381 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19384 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19385 // fully general vector.
19389 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19390 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19392 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19393 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19394 return NumBits1 > NumBits2;
19397 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19398 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19401 if (!isTypeLegal(EVT::getEVT(Ty1)))
19404 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19406 // Assuming the caller doesn't have a zeroext or signext return parameter,
19407 // truncation all the way down to i1 is valid.
19411 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19412 return isInt<32>(Imm);
19415 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19416 // Can also use sub to handle negated immediates.
19417 return isInt<32>(Imm);
19420 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19421 if (!VT1.isInteger() || !VT2.isInteger())
19423 unsigned NumBits1 = VT1.getSizeInBits();
19424 unsigned NumBits2 = VT2.getSizeInBits();
19425 return NumBits1 > NumBits2;
19428 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19429 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19430 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19433 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19434 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19435 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19438 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19439 EVT VT1 = Val.getValueType();
19440 if (isZExtFree(VT1, VT2))
19443 if (Val.getOpcode() != ISD::LOAD)
19446 if (!VT1.isSimple() || !VT1.isInteger() ||
19447 !VT2.isSimple() || !VT2.isInteger())
19450 switch (VT1.getSimpleVT().SimpleTy) {
19455 // X86 has 8, 16, and 32-bit zero-extending loads.
19463 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19464 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19467 VT = VT.getScalarType();
19469 if (!VT.isSimple())
19472 switch (VT.getSimpleVT().SimpleTy) {
19483 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19484 // i16 instructions are longer (0x66 prefix) and potentially slower.
19485 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19488 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19489 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19490 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19491 /// are assumed to be legal.
19493 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19495 if (!VT.isSimple())
19498 MVT SVT = VT.getSimpleVT();
19500 // Very little shuffling can be done for 64-bit vectors right now.
19501 if (VT.getSizeInBits() == 64)
19504 // If this is a single-input shuffle with no 128 bit lane crossings we can
19505 // lower it into pshufb.
19506 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19507 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19508 bool isLegal = true;
19509 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19510 if (M[I] >= (int)SVT.getVectorNumElements() ||
19511 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19520 // FIXME: blends, shifts.
19521 return (SVT.getVectorNumElements() == 2 ||
19522 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19523 isMOVLMask(M, SVT) ||
19524 isMOVHLPSMask(M, SVT) ||
19525 isSHUFPMask(M, SVT) ||
19526 isPSHUFDMask(M, SVT) ||
19527 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19528 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19529 isPALIGNRMask(M, SVT, Subtarget) ||
19530 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19531 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19532 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19533 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19534 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19535 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19539 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19541 if (!VT.isSimple())
19544 MVT SVT = VT.getSimpleVT();
19545 unsigned NumElts = SVT.getVectorNumElements();
19546 // FIXME: This collection of masks seems suspect.
19549 if (NumElts == 4 && SVT.is128BitVector()) {
19550 return (isMOVLMask(Mask, SVT) ||
19551 isCommutedMOVLMask(Mask, SVT, true) ||
19552 isSHUFPMask(Mask, SVT) ||
19553 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19554 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19555 Subtarget->hasInt256()));
19560 //===----------------------------------------------------------------------===//
19561 // X86 Scheduler Hooks
19562 //===----------------------------------------------------------------------===//
19564 /// Utility function to emit xbegin specifying the start of an RTM region.
19565 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19566 const TargetInstrInfo *TII) {
19567 DebugLoc DL = MI->getDebugLoc();
19569 const BasicBlock *BB = MBB->getBasicBlock();
19570 MachineFunction::iterator I = MBB;
19573 // For the v = xbegin(), we generate
19584 MachineBasicBlock *thisMBB = MBB;
19585 MachineFunction *MF = MBB->getParent();
19586 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19587 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19588 MF->insert(I, mainMBB);
19589 MF->insert(I, sinkMBB);
19591 // Transfer the remainder of BB and its successor edges to sinkMBB.
19592 sinkMBB->splice(sinkMBB->begin(), MBB,
19593 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19594 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19598 // # fallthrough to mainMBB
19599 // # abortion to sinkMBB
19600 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19601 thisMBB->addSuccessor(mainMBB);
19602 thisMBB->addSuccessor(sinkMBB);
19606 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19607 mainMBB->addSuccessor(sinkMBB);
19610 // EAX is live into the sinkMBB
19611 sinkMBB->addLiveIn(X86::EAX);
19612 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19613 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19616 MI->eraseFromParent();
19620 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19621 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19622 // in the .td file.
19623 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19624 const TargetInstrInfo *TII) {
19626 switch (MI->getOpcode()) {
19627 default: llvm_unreachable("illegal opcode!");
19628 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19629 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19630 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19631 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19632 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19633 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19634 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19635 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19638 DebugLoc dl = MI->getDebugLoc();
19639 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19641 unsigned NumArgs = MI->getNumOperands();
19642 for (unsigned i = 1; i < NumArgs; ++i) {
19643 MachineOperand &Op = MI->getOperand(i);
19644 if (!(Op.isReg() && Op.isImplicit()))
19645 MIB.addOperand(Op);
19647 if (MI->hasOneMemOperand())
19648 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19650 BuildMI(*BB, MI, dl,
19651 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19652 .addReg(X86::XMM0);
19654 MI->eraseFromParent();
19658 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19659 // defs in an instruction pattern
19660 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19661 const TargetInstrInfo *TII) {
19663 switch (MI->getOpcode()) {
19664 default: llvm_unreachable("illegal opcode!");
19665 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19666 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19667 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19668 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19669 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19670 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19671 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19672 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19675 DebugLoc dl = MI->getDebugLoc();
19676 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19678 unsigned NumArgs = MI->getNumOperands(); // remove the results
19679 for (unsigned i = 1; i < NumArgs; ++i) {
19680 MachineOperand &Op = MI->getOperand(i);
19681 if (!(Op.isReg() && Op.isImplicit()))
19682 MIB.addOperand(Op);
19684 if (MI->hasOneMemOperand())
19685 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19687 BuildMI(*BB, MI, dl,
19688 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19691 MI->eraseFromParent();
19695 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19696 const TargetInstrInfo *TII,
19697 const X86Subtarget* Subtarget) {
19698 DebugLoc dl = MI->getDebugLoc();
19700 // Address into RAX/EAX, other two args into ECX, EDX.
19701 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19702 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19703 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19704 for (int i = 0; i < X86::AddrNumOperands; ++i)
19705 MIB.addOperand(MI->getOperand(i));
19707 unsigned ValOps = X86::AddrNumOperands;
19708 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19709 .addReg(MI->getOperand(ValOps).getReg());
19710 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19711 .addReg(MI->getOperand(ValOps+1).getReg());
19713 // The instruction doesn't actually take any operands though.
19714 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19716 MI->eraseFromParent(); // The pseudo is gone now.
19720 MachineBasicBlock *
19721 X86TargetLowering::EmitVAARG64WithCustomInserter(
19723 MachineBasicBlock *MBB) const {
19724 // Emit va_arg instruction on X86-64.
19726 // Operands to this pseudo-instruction:
19727 // 0 ) Output : destination address (reg)
19728 // 1-5) Input : va_list address (addr, i64mem)
19729 // 6 ) ArgSize : Size (in bytes) of vararg type
19730 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19731 // 8 ) Align : Alignment of type
19732 // 9 ) EFLAGS (implicit-def)
19734 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19735 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19737 unsigned DestReg = MI->getOperand(0).getReg();
19738 MachineOperand &Base = MI->getOperand(1);
19739 MachineOperand &Scale = MI->getOperand(2);
19740 MachineOperand &Index = MI->getOperand(3);
19741 MachineOperand &Disp = MI->getOperand(4);
19742 MachineOperand &Segment = MI->getOperand(5);
19743 unsigned ArgSize = MI->getOperand(6).getImm();
19744 unsigned ArgMode = MI->getOperand(7).getImm();
19745 unsigned Align = MI->getOperand(8).getImm();
19747 // Memory Reference
19748 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19749 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19750 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19752 // Machine Information
19753 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19754 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19755 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19756 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19757 DebugLoc DL = MI->getDebugLoc();
19759 // struct va_list {
19762 // i64 overflow_area (address)
19763 // i64 reg_save_area (address)
19765 // sizeof(va_list) = 24
19766 // alignment(va_list) = 8
19768 unsigned TotalNumIntRegs = 6;
19769 unsigned TotalNumXMMRegs = 8;
19770 bool UseGPOffset = (ArgMode == 1);
19771 bool UseFPOffset = (ArgMode == 2);
19772 unsigned MaxOffset = TotalNumIntRegs * 8 +
19773 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19775 /* Align ArgSize to a multiple of 8 */
19776 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19777 bool NeedsAlign = (Align > 8);
19779 MachineBasicBlock *thisMBB = MBB;
19780 MachineBasicBlock *overflowMBB;
19781 MachineBasicBlock *offsetMBB;
19782 MachineBasicBlock *endMBB;
19784 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19785 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19786 unsigned OffsetReg = 0;
19788 if (!UseGPOffset && !UseFPOffset) {
19789 // If we only pull from the overflow region, we don't create a branch.
19790 // We don't need to alter control flow.
19791 OffsetDestReg = 0; // unused
19792 OverflowDestReg = DestReg;
19794 offsetMBB = nullptr;
19795 overflowMBB = thisMBB;
19798 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19799 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19800 // If not, pull from overflow_area. (branch to overflowMBB)
19805 // offsetMBB overflowMBB
19810 // Registers for the PHI in endMBB
19811 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19812 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19814 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19815 MachineFunction *MF = MBB->getParent();
19816 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19817 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19818 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19820 MachineFunction::iterator MBBIter = MBB;
19823 // Insert the new basic blocks
19824 MF->insert(MBBIter, offsetMBB);
19825 MF->insert(MBBIter, overflowMBB);
19826 MF->insert(MBBIter, endMBB);
19828 // Transfer the remainder of MBB and its successor edges to endMBB.
19829 endMBB->splice(endMBB->begin(), thisMBB,
19830 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19831 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19833 // Make offsetMBB and overflowMBB successors of thisMBB
19834 thisMBB->addSuccessor(offsetMBB);
19835 thisMBB->addSuccessor(overflowMBB);
19837 // endMBB is a successor of both offsetMBB and overflowMBB
19838 offsetMBB->addSuccessor(endMBB);
19839 overflowMBB->addSuccessor(endMBB);
19841 // Load the offset value into a register
19842 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19843 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19847 .addDisp(Disp, UseFPOffset ? 4 : 0)
19848 .addOperand(Segment)
19849 .setMemRefs(MMOBegin, MMOEnd);
19851 // Check if there is enough room left to pull this argument.
19852 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19854 .addImm(MaxOffset + 8 - ArgSizeA8);
19856 // Branch to "overflowMBB" if offset >= max
19857 // Fall through to "offsetMBB" otherwise
19858 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19859 .addMBB(overflowMBB);
19862 // In offsetMBB, emit code to use the reg_save_area.
19864 assert(OffsetReg != 0);
19866 // Read the reg_save_area address.
19867 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19868 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19873 .addOperand(Segment)
19874 .setMemRefs(MMOBegin, MMOEnd);
19876 // Zero-extend the offset
19877 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19878 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19881 .addImm(X86::sub_32bit);
19883 // Add the offset to the reg_save_area to get the final address.
19884 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19885 .addReg(OffsetReg64)
19886 .addReg(RegSaveReg);
19888 // Compute the offset for the next argument
19889 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19890 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19892 .addImm(UseFPOffset ? 16 : 8);
19894 // Store it back into the va_list.
19895 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19899 .addDisp(Disp, UseFPOffset ? 4 : 0)
19900 .addOperand(Segment)
19901 .addReg(NextOffsetReg)
19902 .setMemRefs(MMOBegin, MMOEnd);
19905 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19910 // Emit code to use overflow area
19913 // Load the overflow_area address into a register.
19914 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19915 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19920 .addOperand(Segment)
19921 .setMemRefs(MMOBegin, MMOEnd);
19923 // If we need to align it, do so. Otherwise, just copy the address
19924 // to OverflowDestReg.
19926 // Align the overflow address
19927 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19928 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19930 // aligned_addr = (addr + (align-1)) & ~(align-1)
19931 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19932 .addReg(OverflowAddrReg)
19935 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19937 .addImm(~(uint64_t)(Align-1));
19939 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19940 .addReg(OverflowAddrReg);
19943 // Compute the next overflow address after this argument.
19944 // (the overflow address should be kept 8-byte aligned)
19945 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19946 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19947 .addReg(OverflowDestReg)
19948 .addImm(ArgSizeA8);
19950 // Store the new overflow address.
19951 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19956 .addOperand(Segment)
19957 .addReg(NextAddrReg)
19958 .setMemRefs(MMOBegin, MMOEnd);
19960 // If we branched, emit the PHI to the front of endMBB.
19962 BuildMI(*endMBB, endMBB->begin(), DL,
19963 TII->get(X86::PHI), DestReg)
19964 .addReg(OffsetDestReg).addMBB(offsetMBB)
19965 .addReg(OverflowDestReg).addMBB(overflowMBB);
19968 // Erase the pseudo instruction
19969 MI->eraseFromParent();
19974 MachineBasicBlock *
19975 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19977 MachineBasicBlock *MBB) const {
19978 // Emit code to save XMM registers to the stack. The ABI says that the
19979 // number of registers to save is given in %al, so it's theoretically
19980 // possible to do an indirect jump trick to avoid saving all of them,
19981 // however this code takes a simpler approach and just executes all
19982 // of the stores if %al is non-zero. It's less code, and it's probably
19983 // easier on the hardware branch predictor, and stores aren't all that
19984 // expensive anyway.
19986 // Create the new basic blocks. One block contains all the XMM stores,
19987 // and one block is the final destination regardless of whether any
19988 // stores were performed.
19989 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19990 MachineFunction *F = MBB->getParent();
19991 MachineFunction::iterator MBBIter = MBB;
19993 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19994 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19995 F->insert(MBBIter, XMMSaveMBB);
19996 F->insert(MBBIter, EndMBB);
19998 // Transfer the remainder of MBB and its successor edges to EndMBB.
19999 EndMBB->splice(EndMBB->begin(), MBB,
20000 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20001 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20003 // The original block will now fall through to the XMM save block.
20004 MBB->addSuccessor(XMMSaveMBB);
20005 // The XMMSaveMBB will fall through to the end block.
20006 XMMSaveMBB->addSuccessor(EndMBB);
20008 // Now add the instructions.
20009 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20010 DebugLoc DL = MI->getDebugLoc();
20012 unsigned CountReg = MI->getOperand(0).getReg();
20013 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20014 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20016 if (!Subtarget->isTargetWin64()) {
20017 // If %al is 0, branch around the XMM save block.
20018 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20019 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20020 MBB->addSuccessor(EndMBB);
20023 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20024 // that was just emitted, but clearly shouldn't be "saved".
20025 assert((MI->getNumOperands() <= 3 ||
20026 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20027 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20028 && "Expected last argument to be EFLAGS");
20029 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20030 // In the XMM save block, save all the XMM argument registers.
20031 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20032 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20033 MachineMemOperand *MMO =
20034 F->getMachineMemOperand(
20035 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20036 MachineMemOperand::MOStore,
20037 /*Size=*/16, /*Align=*/16);
20038 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20039 .addFrameIndex(RegSaveFrameIndex)
20040 .addImm(/*Scale=*/1)
20041 .addReg(/*IndexReg=*/0)
20042 .addImm(/*Disp=*/Offset)
20043 .addReg(/*Segment=*/0)
20044 .addReg(MI->getOperand(i).getReg())
20045 .addMemOperand(MMO);
20048 MI->eraseFromParent(); // The pseudo instruction is gone now.
20053 // The EFLAGS operand of SelectItr might be missing a kill marker
20054 // because there were multiple uses of EFLAGS, and ISel didn't know
20055 // which to mark. Figure out whether SelectItr should have had a
20056 // kill marker, and set it if it should. Returns the correct kill
20058 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20059 MachineBasicBlock* BB,
20060 const TargetRegisterInfo* TRI) {
20061 // Scan forward through BB for a use/def of EFLAGS.
20062 MachineBasicBlock::iterator miI(std::next(SelectItr));
20063 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20064 const MachineInstr& mi = *miI;
20065 if (mi.readsRegister(X86::EFLAGS))
20067 if (mi.definesRegister(X86::EFLAGS))
20068 break; // Should have kill-flag - update below.
20071 // If we hit the end of the block, check whether EFLAGS is live into a
20073 if (miI == BB->end()) {
20074 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20075 sEnd = BB->succ_end();
20076 sItr != sEnd; ++sItr) {
20077 MachineBasicBlock* succ = *sItr;
20078 if (succ->isLiveIn(X86::EFLAGS))
20083 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20084 // out. SelectMI should have a kill flag on EFLAGS.
20085 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20089 MachineBasicBlock *
20090 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20091 MachineBasicBlock *BB) const {
20092 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20093 DebugLoc DL = MI->getDebugLoc();
20095 // To "insert" a SELECT_CC instruction, we actually have to insert the
20096 // diamond control-flow pattern. The incoming instruction knows the
20097 // destination vreg to set, the condition code register to branch on, the
20098 // true/false values to select between, and a branch opcode to use.
20099 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20100 MachineFunction::iterator It = BB;
20106 // cmpTY ccX, r1, r2
20108 // fallthrough --> copy0MBB
20109 MachineBasicBlock *thisMBB = BB;
20110 MachineFunction *F = BB->getParent();
20111 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20112 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20113 F->insert(It, copy0MBB);
20114 F->insert(It, sinkMBB);
20116 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20117 // live into the sink and copy blocks.
20118 const TargetRegisterInfo *TRI =
20119 BB->getParent()->getSubtarget().getRegisterInfo();
20120 if (!MI->killsRegister(X86::EFLAGS) &&
20121 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20122 copy0MBB->addLiveIn(X86::EFLAGS);
20123 sinkMBB->addLiveIn(X86::EFLAGS);
20126 // Transfer the remainder of BB and its successor edges to sinkMBB.
20127 sinkMBB->splice(sinkMBB->begin(), BB,
20128 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20129 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20131 // Add the true and fallthrough blocks as its successors.
20132 BB->addSuccessor(copy0MBB);
20133 BB->addSuccessor(sinkMBB);
20135 // Create the conditional branch instruction.
20137 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20138 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20141 // %FalseValue = ...
20142 // # fallthrough to sinkMBB
20143 copy0MBB->addSuccessor(sinkMBB);
20146 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20148 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20149 TII->get(X86::PHI), MI->getOperand(0).getReg())
20150 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20151 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20153 MI->eraseFromParent(); // The pseudo instruction is gone now.
20157 MachineBasicBlock *
20158 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20159 MachineBasicBlock *BB) const {
20160 MachineFunction *MF = BB->getParent();
20161 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20162 DebugLoc DL = MI->getDebugLoc();
20163 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20165 assert(MF->shouldSplitStack());
20167 const bool Is64Bit = Subtarget->is64Bit();
20168 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20170 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20171 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20174 // ... [Till the alloca]
20175 // If stacklet is not large enough, jump to mallocMBB
20178 // Allocate by subtracting from RSP
20179 // Jump to continueMBB
20182 // Allocate by call to runtime
20186 // [rest of original BB]
20189 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20190 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20191 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20193 MachineRegisterInfo &MRI = MF->getRegInfo();
20194 const TargetRegisterClass *AddrRegClass =
20195 getRegClassFor(getPointerTy());
20197 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20198 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20199 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20200 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20201 sizeVReg = MI->getOperand(1).getReg(),
20202 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20204 MachineFunction::iterator MBBIter = BB;
20207 MF->insert(MBBIter, bumpMBB);
20208 MF->insert(MBBIter, mallocMBB);
20209 MF->insert(MBBIter, continueMBB);
20211 continueMBB->splice(continueMBB->begin(), BB,
20212 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20213 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20215 // Add code to the main basic block to check if the stack limit has been hit,
20216 // and if so, jump to mallocMBB otherwise to bumpMBB.
20217 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20218 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20219 .addReg(tmpSPVReg).addReg(sizeVReg);
20220 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20221 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20222 .addReg(SPLimitVReg);
20223 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20225 // bumpMBB simply decreases the stack pointer, since we know the current
20226 // stacklet has enough space.
20227 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20228 .addReg(SPLimitVReg);
20229 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20230 .addReg(SPLimitVReg);
20231 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20233 // Calls into a routine in libgcc to allocate more space from the heap.
20234 const uint32_t *RegMask = MF->getTarget()
20235 .getSubtargetImpl()
20236 ->getRegisterInfo()
20237 ->getCallPreservedMask(CallingConv::C);
20239 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20241 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20242 .addExternalSymbol("__morestack_allocate_stack_space")
20243 .addRegMask(RegMask)
20244 .addReg(X86::RDI, RegState::Implicit)
20245 .addReg(X86::RAX, RegState::ImplicitDefine);
20246 } else if (Is64Bit) {
20247 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20249 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20250 .addExternalSymbol("__morestack_allocate_stack_space")
20251 .addRegMask(RegMask)
20252 .addReg(X86::EDI, RegState::Implicit)
20253 .addReg(X86::EAX, RegState::ImplicitDefine);
20255 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20257 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20258 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20259 .addExternalSymbol("__morestack_allocate_stack_space")
20260 .addRegMask(RegMask)
20261 .addReg(X86::EAX, RegState::ImplicitDefine);
20265 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20268 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20269 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20270 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20272 // Set up the CFG correctly.
20273 BB->addSuccessor(bumpMBB);
20274 BB->addSuccessor(mallocMBB);
20275 mallocMBB->addSuccessor(continueMBB);
20276 bumpMBB->addSuccessor(continueMBB);
20278 // Take care of the PHI nodes.
20279 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20280 MI->getOperand(0).getReg())
20281 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20282 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20284 // Delete the original pseudo instruction.
20285 MI->eraseFromParent();
20288 return continueMBB;
20291 MachineBasicBlock *
20292 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20293 MachineBasicBlock *BB) const {
20294 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20295 DebugLoc DL = MI->getDebugLoc();
20297 assert(!Subtarget->isTargetMacho());
20299 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20300 // non-trivial part is impdef of ESP.
20302 if (Subtarget->isTargetWin64()) {
20303 if (Subtarget->isTargetCygMing()) {
20304 // ___chkstk(Mingw64):
20305 // Clobbers R10, R11, RAX and EFLAGS.
20307 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20308 .addExternalSymbol("___chkstk")
20309 .addReg(X86::RAX, RegState::Implicit)
20310 .addReg(X86::RSP, RegState::Implicit)
20311 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20312 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20313 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20315 // __chkstk(MSVCRT): does not update stack pointer.
20316 // Clobbers R10, R11 and EFLAGS.
20317 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20318 .addExternalSymbol("__chkstk")
20319 .addReg(X86::RAX, RegState::Implicit)
20320 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20321 // RAX has the offset to be subtracted from RSP.
20322 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20327 const char *StackProbeSymbol =
20328 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20330 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20331 .addExternalSymbol(StackProbeSymbol)
20332 .addReg(X86::EAX, RegState::Implicit)
20333 .addReg(X86::ESP, RegState::Implicit)
20334 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20335 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20336 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20339 MI->eraseFromParent(); // The pseudo instruction is gone now.
20343 MachineBasicBlock *
20344 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20345 MachineBasicBlock *BB) const {
20346 // This is pretty easy. We're taking the value that we received from
20347 // our load from the relocation, sticking it in either RDI (x86-64)
20348 // or EAX and doing an indirect call. The return value will then
20349 // be in the normal return register.
20350 MachineFunction *F = BB->getParent();
20351 const X86InstrInfo *TII =
20352 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20353 DebugLoc DL = MI->getDebugLoc();
20355 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20356 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20358 // Get a register mask for the lowered call.
20359 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20360 // proper register mask.
20361 const uint32_t *RegMask = F->getTarget()
20362 .getSubtargetImpl()
20363 ->getRegisterInfo()
20364 ->getCallPreservedMask(CallingConv::C);
20365 if (Subtarget->is64Bit()) {
20366 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20367 TII->get(X86::MOV64rm), X86::RDI)
20369 .addImm(0).addReg(0)
20370 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20371 MI->getOperand(3).getTargetFlags())
20373 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20374 addDirectMem(MIB, X86::RDI);
20375 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20376 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20377 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20378 TII->get(X86::MOV32rm), X86::EAX)
20380 .addImm(0).addReg(0)
20381 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20382 MI->getOperand(3).getTargetFlags())
20384 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20385 addDirectMem(MIB, X86::EAX);
20386 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20388 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20389 TII->get(X86::MOV32rm), X86::EAX)
20390 .addReg(TII->getGlobalBaseReg(F))
20391 .addImm(0).addReg(0)
20392 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20393 MI->getOperand(3).getTargetFlags())
20395 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20396 addDirectMem(MIB, X86::EAX);
20397 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20400 MI->eraseFromParent(); // The pseudo instruction is gone now.
20404 MachineBasicBlock *
20405 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20406 MachineBasicBlock *MBB) const {
20407 DebugLoc DL = MI->getDebugLoc();
20408 MachineFunction *MF = MBB->getParent();
20409 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20410 MachineRegisterInfo &MRI = MF->getRegInfo();
20412 const BasicBlock *BB = MBB->getBasicBlock();
20413 MachineFunction::iterator I = MBB;
20416 // Memory Reference
20417 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20418 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20421 unsigned MemOpndSlot = 0;
20423 unsigned CurOp = 0;
20425 DstReg = MI->getOperand(CurOp++).getReg();
20426 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20427 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20428 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20429 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20431 MemOpndSlot = CurOp;
20433 MVT PVT = getPointerTy();
20434 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20435 "Invalid Pointer Size!");
20437 // For v = setjmp(buf), we generate
20440 // buf[LabelOffset] = restoreMBB
20441 // SjLjSetup restoreMBB
20447 // v = phi(main, restore)
20452 MachineBasicBlock *thisMBB = MBB;
20453 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20454 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20455 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20456 MF->insert(I, mainMBB);
20457 MF->insert(I, sinkMBB);
20458 MF->push_back(restoreMBB);
20460 MachineInstrBuilder MIB;
20462 // Transfer the remainder of BB and its successor edges to sinkMBB.
20463 sinkMBB->splice(sinkMBB->begin(), MBB,
20464 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20465 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20468 unsigned PtrStoreOpc = 0;
20469 unsigned LabelReg = 0;
20470 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20471 Reloc::Model RM = MF->getTarget().getRelocationModel();
20472 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20473 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20475 // Prepare IP either in reg or imm.
20476 if (!UseImmLabel) {
20477 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20478 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20479 LabelReg = MRI.createVirtualRegister(PtrRC);
20480 if (Subtarget->is64Bit()) {
20481 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20485 .addMBB(restoreMBB)
20488 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20489 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20490 .addReg(XII->getGlobalBaseReg(MF))
20493 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20497 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20499 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20500 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20501 if (i == X86::AddrDisp)
20502 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20504 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20507 MIB.addReg(LabelReg);
20509 MIB.addMBB(restoreMBB);
20510 MIB.setMemRefs(MMOBegin, MMOEnd);
20512 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20513 .addMBB(restoreMBB);
20515 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20516 MF->getSubtarget().getRegisterInfo());
20517 MIB.addRegMask(RegInfo->getNoPreservedMask());
20518 thisMBB->addSuccessor(mainMBB);
20519 thisMBB->addSuccessor(restoreMBB);
20523 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20524 mainMBB->addSuccessor(sinkMBB);
20527 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20528 TII->get(X86::PHI), DstReg)
20529 .addReg(mainDstReg).addMBB(mainMBB)
20530 .addReg(restoreDstReg).addMBB(restoreMBB);
20533 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20534 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20535 restoreMBB->addSuccessor(sinkMBB);
20537 MI->eraseFromParent();
20541 MachineBasicBlock *
20542 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20543 MachineBasicBlock *MBB) const {
20544 DebugLoc DL = MI->getDebugLoc();
20545 MachineFunction *MF = MBB->getParent();
20546 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20547 MachineRegisterInfo &MRI = MF->getRegInfo();
20549 // Memory Reference
20550 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20551 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20553 MVT PVT = getPointerTy();
20554 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20555 "Invalid Pointer Size!");
20557 const TargetRegisterClass *RC =
20558 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20559 unsigned Tmp = MRI.createVirtualRegister(RC);
20560 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20561 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20562 MF->getSubtarget().getRegisterInfo());
20563 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20564 unsigned SP = RegInfo->getStackRegister();
20566 MachineInstrBuilder MIB;
20568 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20569 const int64_t SPOffset = 2 * PVT.getStoreSize();
20571 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20572 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20575 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20576 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20577 MIB.addOperand(MI->getOperand(i));
20578 MIB.setMemRefs(MMOBegin, MMOEnd);
20580 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20581 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20582 if (i == X86::AddrDisp)
20583 MIB.addDisp(MI->getOperand(i), LabelOffset);
20585 MIB.addOperand(MI->getOperand(i));
20587 MIB.setMemRefs(MMOBegin, MMOEnd);
20589 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20590 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20591 if (i == X86::AddrDisp)
20592 MIB.addDisp(MI->getOperand(i), SPOffset);
20594 MIB.addOperand(MI->getOperand(i));
20596 MIB.setMemRefs(MMOBegin, MMOEnd);
20598 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20600 MI->eraseFromParent();
20604 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20605 // accumulator loops. Writing back to the accumulator allows the coalescer
20606 // to remove extra copies in the loop.
20607 MachineBasicBlock *
20608 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20609 MachineBasicBlock *MBB) const {
20610 MachineOperand &AddendOp = MI->getOperand(3);
20612 // Bail out early if the addend isn't a register - we can't switch these.
20613 if (!AddendOp.isReg())
20616 MachineFunction &MF = *MBB->getParent();
20617 MachineRegisterInfo &MRI = MF.getRegInfo();
20619 // Check whether the addend is defined by a PHI:
20620 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20621 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20622 if (!AddendDef.isPHI())
20625 // Look for the following pattern:
20627 // %addend = phi [%entry, 0], [%loop, %result]
20629 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20633 // %addend = phi [%entry, 0], [%loop, %result]
20635 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20637 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20638 assert(AddendDef.getOperand(i).isReg());
20639 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20640 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20641 if (&PHISrcInst == MI) {
20642 // Found a matching instruction.
20643 unsigned NewFMAOpc = 0;
20644 switch (MI->getOpcode()) {
20645 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20646 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20647 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20648 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20649 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20650 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20651 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20652 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20653 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20654 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20655 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20656 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20657 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20658 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20659 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20660 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20661 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20662 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20663 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20664 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20666 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20667 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20668 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20669 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20670 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20671 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20672 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20673 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20674 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20675 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20676 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20677 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20678 default: llvm_unreachable("Unrecognized FMA variant.");
20681 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20682 MachineInstrBuilder MIB =
20683 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20684 .addOperand(MI->getOperand(0))
20685 .addOperand(MI->getOperand(3))
20686 .addOperand(MI->getOperand(2))
20687 .addOperand(MI->getOperand(1));
20688 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20689 MI->eraseFromParent();
20696 MachineBasicBlock *
20697 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20698 MachineBasicBlock *BB) const {
20699 switch (MI->getOpcode()) {
20700 default: llvm_unreachable("Unexpected instr type to insert");
20701 case X86::TAILJMPd64:
20702 case X86::TAILJMPr64:
20703 case X86::TAILJMPm64:
20704 llvm_unreachable("TAILJMP64 would not be touched here.");
20705 case X86::TCRETURNdi64:
20706 case X86::TCRETURNri64:
20707 case X86::TCRETURNmi64:
20709 case X86::WIN_ALLOCA:
20710 return EmitLoweredWinAlloca(MI, BB);
20711 case X86::SEG_ALLOCA_32:
20712 case X86::SEG_ALLOCA_64:
20713 return EmitLoweredSegAlloca(MI, BB);
20714 case X86::TLSCall_32:
20715 case X86::TLSCall_64:
20716 return EmitLoweredTLSCall(MI, BB);
20717 case X86::CMOV_GR8:
20718 case X86::CMOV_FR32:
20719 case X86::CMOV_FR64:
20720 case X86::CMOV_V4F32:
20721 case X86::CMOV_V2F64:
20722 case X86::CMOV_V2I64:
20723 case X86::CMOV_V8F32:
20724 case X86::CMOV_V4F64:
20725 case X86::CMOV_V4I64:
20726 case X86::CMOV_V16F32:
20727 case X86::CMOV_V8F64:
20728 case X86::CMOV_V8I64:
20729 case X86::CMOV_GR16:
20730 case X86::CMOV_GR32:
20731 case X86::CMOV_RFP32:
20732 case X86::CMOV_RFP64:
20733 case X86::CMOV_RFP80:
20734 return EmitLoweredSelect(MI, BB);
20736 case X86::FP32_TO_INT16_IN_MEM:
20737 case X86::FP32_TO_INT32_IN_MEM:
20738 case X86::FP32_TO_INT64_IN_MEM:
20739 case X86::FP64_TO_INT16_IN_MEM:
20740 case X86::FP64_TO_INT32_IN_MEM:
20741 case X86::FP64_TO_INT64_IN_MEM:
20742 case X86::FP80_TO_INT16_IN_MEM:
20743 case X86::FP80_TO_INT32_IN_MEM:
20744 case X86::FP80_TO_INT64_IN_MEM: {
20745 MachineFunction *F = BB->getParent();
20746 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20747 DebugLoc DL = MI->getDebugLoc();
20749 // Change the floating point control register to use "round towards zero"
20750 // mode when truncating to an integer value.
20751 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20752 addFrameReference(BuildMI(*BB, MI, DL,
20753 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20755 // Load the old value of the high byte of the control word...
20757 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20758 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20761 // Set the high part to be round to zero...
20762 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20765 // Reload the modified control word now...
20766 addFrameReference(BuildMI(*BB, MI, DL,
20767 TII->get(X86::FLDCW16m)), CWFrameIdx);
20769 // Restore the memory image of control word to original value
20770 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20773 // Get the X86 opcode to use.
20775 switch (MI->getOpcode()) {
20776 default: llvm_unreachable("illegal opcode!");
20777 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20778 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20779 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20780 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20781 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20782 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20783 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20784 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20785 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20789 MachineOperand &Op = MI->getOperand(0);
20791 AM.BaseType = X86AddressMode::RegBase;
20792 AM.Base.Reg = Op.getReg();
20794 AM.BaseType = X86AddressMode::FrameIndexBase;
20795 AM.Base.FrameIndex = Op.getIndex();
20797 Op = MI->getOperand(1);
20799 AM.Scale = Op.getImm();
20800 Op = MI->getOperand(2);
20802 AM.IndexReg = Op.getImm();
20803 Op = MI->getOperand(3);
20804 if (Op.isGlobal()) {
20805 AM.GV = Op.getGlobal();
20807 AM.Disp = Op.getImm();
20809 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20810 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20812 // Reload the original control word now.
20813 addFrameReference(BuildMI(*BB, MI, DL,
20814 TII->get(X86::FLDCW16m)), CWFrameIdx);
20816 MI->eraseFromParent(); // The pseudo instruction is gone now.
20819 // String/text processing lowering.
20820 case X86::PCMPISTRM128REG:
20821 case X86::VPCMPISTRM128REG:
20822 case X86::PCMPISTRM128MEM:
20823 case X86::VPCMPISTRM128MEM:
20824 case X86::PCMPESTRM128REG:
20825 case X86::VPCMPESTRM128REG:
20826 case X86::PCMPESTRM128MEM:
20827 case X86::VPCMPESTRM128MEM:
20828 assert(Subtarget->hasSSE42() &&
20829 "Target must have SSE4.2 or AVX features enabled");
20830 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20832 // String/text processing lowering.
20833 case X86::PCMPISTRIREG:
20834 case X86::VPCMPISTRIREG:
20835 case X86::PCMPISTRIMEM:
20836 case X86::VPCMPISTRIMEM:
20837 case X86::PCMPESTRIREG:
20838 case X86::VPCMPESTRIREG:
20839 case X86::PCMPESTRIMEM:
20840 case X86::VPCMPESTRIMEM:
20841 assert(Subtarget->hasSSE42() &&
20842 "Target must have SSE4.2 or AVX features enabled");
20843 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20845 // Thread synchronization.
20847 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20852 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20854 case X86::VASTART_SAVE_XMM_REGS:
20855 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20857 case X86::VAARG_64:
20858 return EmitVAARG64WithCustomInserter(MI, BB);
20860 case X86::EH_SjLj_SetJmp32:
20861 case X86::EH_SjLj_SetJmp64:
20862 return emitEHSjLjSetJmp(MI, BB);
20864 case X86::EH_SjLj_LongJmp32:
20865 case X86::EH_SjLj_LongJmp64:
20866 return emitEHSjLjLongJmp(MI, BB);
20868 case TargetOpcode::STACKMAP:
20869 case TargetOpcode::PATCHPOINT:
20870 return emitPatchPoint(MI, BB);
20872 case X86::VFMADDPDr213r:
20873 case X86::VFMADDPSr213r:
20874 case X86::VFMADDSDr213r:
20875 case X86::VFMADDSSr213r:
20876 case X86::VFMSUBPDr213r:
20877 case X86::VFMSUBPSr213r:
20878 case X86::VFMSUBSDr213r:
20879 case X86::VFMSUBSSr213r:
20880 case X86::VFNMADDPDr213r:
20881 case X86::VFNMADDPSr213r:
20882 case X86::VFNMADDSDr213r:
20883 case X86::VFNMADDSSr213r:
20884 case X86::VFNMSUBPDr213r:
20885 case X86::VFNMSUBPSr213r:
20886 case X86::VFNMSUBSDr213r:
20887 case X86::VFNMSUBSSr213r:
20888 case X86::VFMADDSUBPDr213r:
20889 case X86::VFMADDSUBPSr213r:
20890 case X86::VFMSUBADDPDr213r:
20891 case X86::VFMSUBADDPSr213r:
20892 case X86::VFMADDPDr213rY:
20893 case X86::VFMADDPSr213rY:
20894 case X86::VFMSUBPDr213rY:
20895 case X86::VFMSUBPSr213rY:
20896 case X86::VFNMADDPDr213rY:
20897 case X86::VFNMADDPSr213rY:
20898 case X86::VFNMSUBPDr213rY:
20899 case X86::VFNMSUBPSr213rY:
20900 case X86::VFMADDSUBPDr213rY:
20901 case X86::VFMADDSUBPSr213rY:
20902 case X86::VFMSUBADDPDr213rY:
20903 case X86::VFMSUBADDPSr213rY:
20904 return emitFMA3Instr(MI, BB);
20908 //===----------------------------------------------------------------------===//
20909 // X86 Optimization Hooks
20910 //===----------------------------------------------------------------------===//
20912 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20915 const SelectionDAG &DAG,
20916 unsigned Depth) const {
20917 unsigned BitWidth = KnownZero.getBitWidth();
20918 unsigned Opc = Op.getOpcode();
20919 assert((Opc >= ISD::BUILTIN_OP_END ||
20920 Opc == ISD::INTRINSIC_WO_CHAIN ||
20921 Opc == ISD::INTRINSIC_W_CHAIN ||
20922 Opc == ISD::INTRINSIC_VOID) &&
20923 "Should use MaskedValueIsZero if you don't know whether Op"
20924 " is a target node!");
20926 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20940 // These nodes' second result is a boolean.
20941 if (Op.getResNo() == 0)
20944 case X86ISD::SETCC:
20945 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20947 case ISD::INTRINSIC_WO_CHAIN: {
20948 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20949 unsigned NumLoBits = 0;
20952 case Intrinsic::x86_sse_movmsk_ps:
20953 case Intrinsic::x86_avx_movmsk_ps_256:
20954 case Intrinsic::x86_sse2_movmsk_pd:
20955 case Intrinsic::x86_avx_movmsk_pd_256:
20956 case Intrinsic::x86_mmx_pmovmskb:
20957 case Intrinsic::x86_sse2_pmovmskb_128:
20958 case Intrinsic::x86_avx2_pmovmskb: {
20959 // High bits of movmskp{s|d}, pmovmskb are known zero.
20961 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20962 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20963 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20964 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20965 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20966 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20967 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20968 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20970 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20979 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20981 const SelectionDAG &,
20982 unsigned Depth) const {
20983 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20984 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20985 return Op.getValueType().getScalarType().getSizeInBits();
20991 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20992 /// node is a GlobalAddress + offset.
20993 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20994 const GlobalValue* &GA,
20995 int64_t &Offset) const {
20996 if (N->getOpcode() == X86ISD::Wrapper) {
20997 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20998 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20999 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21003 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21006 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21007 /// same as extracting the high 128-bit part of 256-bit vector and then
21008 /// inserting the result into the low part of a new 256-bit vector
21009 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21010 EVT VT = SVOp->getValueType(0);
21011 unsigned NumElems = VT.getVectorNumElements();
21013 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21014 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21015 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21016 SVOp->getMaskElt(j) >= 0)
21022 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21023 /// same as extracting the low 128-bit part of 256-bit vector and then
21024 /// inserting the result into the high part of a new 256-bit vector
21025 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21026 EVT VT = SVOp->getValueType(0);
21027 unsigned NumElems = VT.getVectorNumElements();
21029 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21030 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21031 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21032 SVOp->getMaskElt(j) >= 0)
21038 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21039 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21040 TargetLowering::DAGCombinerInfo &DCI,
21041 const X86Subtarget* Subtarget) {
21043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21044 SDValue V1 = SVOp->getOperand(0);
21045 SDValue V2 = SVOp->getOperand(1);
21046 EVT VT = SVOp->getValueType(0);
21047 unsigned NumElems = VT.getVectorNumElements();
21049 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21050 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21054 // V UNDEF BUILD_VECTOR UNDEF
21056 // CONCAT_VECTOR CONCAT_VECTOR
21059 // RESULT: V + zero extended
21061 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21062 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21063 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21066 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21069 // To match the shuffle mask, the first half of the mask should
21070 // be exactly the first vector, and all the rest a splat with the
21071 // first element of the second one.
21072 for (unsigned i = 0; i != NumElems/2; ++i)
21073 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21074 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21077 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21078 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21079 if (Ld->hasNUsesOfValue(1, 0)) {
21080 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21081 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21083 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21085 Ld->getPointerInfo(),
21086 Ld->getAlignment(),
21087 false/*isVolatile*/, true/*ReadMem*/,
21088 false/*WriteMem*/);
21090 // Make sure the newly-created LOAD is in the same position as Ld in
21091 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21092 // and update uses of Ld's output chain to use the TokenFactor.
21093 if (Ld->hasAnyUseOfValue(1)) {
21094 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21095 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21096 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21097 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21098 SDValue(ResNode.getNode(), 1));
21101 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21105 // Emit a zeroed vector and insert the desired subvector on its
21107 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21108 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21109 return DCI.CombineTo(N, InsV);
21112 //===--------------------------------------------------------------------===//
21113 // Combine some shuffles into subvector extracts and inserts:
21116 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21117 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21118 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21119 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21120 return DCI.CombineTo(N, InsV);
21123 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21124 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21125 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21126 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21127 return DCI.CombineTo(N, InsV);
21133 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21136 /// This is the leaf of the recursive combinine below. When we have found some
21137 /// chain of single-use x86 shuffle instructions and accumulated the combined
21138 /// shuffle mask represented by them, this will try to pattern match that mask
21139 /// into either a single instruction if there is a special purpose instruction
21140 /// for this operation, or into a PSHUFB instruction which is a fully general
21141 /// instruction but should only be used to replace chains over a certain depth.
21142 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21143 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21144 TargetLowering::DAGCombinerInfo &DCI,
21145 const X86Subtarget *Subtarget) {
21146 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21148 // Find the operand that enters the chain. Note that multiple uses are OK
21149 // here, we're not going to remove the operand we find.
21150 SDValue Input = Op.getOperand(0);
21151 while (Input.getOpcode() == ISD::BITCAST)
21152 Input = Input.getOperand(0);
21154 MVT VT = Input.getSimpleValueType();
21155 MVT RootVT = Root.getSimpleValueType();
21158 // Just remove no-op shuffle masks.
21159 if (Mask.size() == 1) {
21160 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21165 // Use the float domain if the operand type is a floating point type.
21166 bool FloatDomain = VT.isFloatingPoint();
21168 // For floating point shuffles, we don't have free copies in the shuffle
21169 // instructions or the ability to load as part of the instruction, so
21170 // canonicalize their shuffles to UNPCK or MOV variants.
21172 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21173 // vectors because it can have a load folded into it that UNPCK cannot. This
21174 // doesn't preclude something switching to the shorter encoding post-RA.
21176 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21177 bool Lo = Mask.equals(0, 0);
21180 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21181 // is no slower than UNPCKLPD but has the option to fold the input operand
21182 // into even an unaligned memory load.
21183 if (Lo && Subtarget->hasSSE3()) {
21184 Shuffle = X86ISD::MOVDDUP;
21185 ShuffleVT = MVT::v2f64;
21187 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21188 // than the UNPCK variants.
21189 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21190 ShuffleVT = MVT::v4f32;
21192 if (Depth == 1 && Root->getOpcode() == Shuffle)
21193 return false; // Nothing to do!
21194 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21195 DCI.AddToWorklist(Op.getNode());
21196 if (Shuffle == X86ISD::MOVDDUP)
21197 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21199 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21200 DCI.AddToWorklist(Op.getNode());
21201 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21205 if (Subtarget->hasSSE3() &&
21206 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21207 bool Lo = Mask.equals(0, 0, 2, 2);
21208 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21209 MVT ShuffleVT = MVT::v4f32;
21210 if (Depth == 1 && Root->getOpcode() == Shuffle)
21211 return false; // Nothing to do!
21212 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21213 DCI.AddToWorklist(Op.getNode());
21214 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21215 DCI.AddToWorklist(Op.getNode());
21216 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21220 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21221 bool Lo = Mask.equals(0, 0, 1, 1);
21222 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21223 MVT ShuffleVT = MVT::v4f32;
21224 if (Depth == 1 && Root->getOpcode() == Shuffle)
21225 return false; // Nothing to do!
21226 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21227 DCI.AddToWorklist(Op.getNode());
21228 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21229 DCI.AddToWorklist(Op.getNode());
21230 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21236 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21237 // variants as none of these have single-instruction variants that are
21238 // superior to the UNPCK formulation.
21239 if (!FloatDomain &&
21240 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21241 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21242 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21243 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21245 bool Lo = Mask[0] == 0;
21246 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21247 if (Depth == 1 && Root->getOpcode() == Shuffle)
21248 return false; // Nothing to do!
21250 switch (Mask.size()) {
21252 ShuffleVT = MVT::v8i16;
21255 ShuffleVT = MVT::v16i8;
21258 llvm_unreachable("Impossible mask size!");
21260 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21261 DCI.AddToWorklist(Op.getNode());
21262 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21263 DCI.AddToWorklist(Op.getNode());
21264 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21269 // Don't try to re-form single instruction chains under any circumstances now
21270 // that we've done encoding canonicalization for them.
21274 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21275 // can replace them with a single PSHUFB instruction profitably. Intel's
21276 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21277 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21278 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21279 SmallVector<SDValue, 16> PSHUFBMask;
21280 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21281 int Ratio = 16 / Mask.size();
21282 for (unsigned i = 0; i < 16; ++i) {
21283 if (Mask[i / Ratio] == SM_SentinelUndef) {
21284 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21287 int M = Mask[i / Ratio] != SM_SentinelZero
21288 ? Ratio * Mask[i / Ratio] + i % Ratio
21290 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21292 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21293 DCI.AddToWorklist(Op.getNode());
21294 SDValue PSHUFBMaskOp =
21295 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21296 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21297 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21298 DCI.AddToWorklist(Op.getNode());
21299 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21304 // Failed to find any combines.
21308 /// \brief Fully generic combining of x86 shuffle instructions.
21310 /// This should be the last combine run over the x86 shuffle instructions. Once
21311 /// they have been fully optimized, this will recursively consider all chains
21312 /// of single-use shuffle instructions, build a generic model of the cumulative
21313 /// shuffle operation, and check for simpler instructions which implement this
21314 /// operation. We use this primarily for two purposes:
21316 /// 1) Collapse generic shuffles to specialized single instructions when
21317 /// equivalent. In most cases, this is just an encoding size win, but
21318 /// sometimes we will collapse multiple generic shuffles into a single
21319 /// special-purpose shuffle.
21320 /// 2) Look for sequences of shuffle instructions with 3 or more total
21321 /// instructions, and replace them with the slightly more expensive SSSE3
21322 /// PSHUFB instruction if available. We do this as the last combining step
21323 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21324 /// a suitable short sequence of other instructions. The PHUFB will either
21325 /// use a register or have to read from memory and so is slightly (but only
21326 /// slightly) more expensive than the other shuffle instructions.
21328 /// Because this is inherently a quadratic operation (for each shuffle in
21329 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21330 /// This should never be an issue in practice as the shuffle lowering doesn't
21331 /// produce sequences of more than 8 instructions.
21333 /// FIXME: We will currently miss some cases where the redundant shuffling
21334 /// would simplify under the threshold for PSHUFB formation because of
21335 /// combine-ordering. To fix this, we should do the redundant instruction
21336 /// combining in this recursive walk.
21337 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21338 ArrayRef<int> RootMask,
21339 int Depth, bool HasPSHUFB,
21341 TargetLowering::DAGCombinerInfo &DCI,
21342 const X86Subtarget *Subtarget) {
21343 // Bound the depth of our recursive combine because this is ultimately
21344 // quadratic in nature.
21348 // Directly rip through bitcasts to find the underlying operand.
21349 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21350 Op = Op.getOperand(0);
21352 MVT VT = Op.getSimpleValueType();
21353 if (!VT.isVector())
21354 return false; // Bail if we hit a non-vector.
21355 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21356 // version should be added.
21357 if (VT.getSizeInBits() != 128)
21360 assert(Root.getSimpleValueType().isVector() &&
21361 "Shuffles operate on vector types!");
21362 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21363 "Can only combine shuffles of the same vector register size.");
21365 if (!isTargetShuffle(Op.getOpcode()))
21367 SmallVector<int, 16> OpMask;
21369 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21370 // We only can combine unary shuffles which we can decode the mask for.
21371 if (!HaveMask || !IsUnary)
21374 assert(VT.getVectorNumElements() == OpMask.size() &&
21375 "Different mask size from vector size!");
21376 assert(((RootMask.size() > OpMask.size() &&
21377 RootMask.size() % OpMask.size() == 0) ||
21378 (OpMask.size() > RootMask.size() &&
21379 OpMask.size() % RootMask.size() == 0) ||
21380 OpMask.size() == RootMask.size()) &&
21381 "The smaller number of elements must divide the larger.");
21382 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21383 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21384 assert(((RootRatio == 1 && OpRatio == 1) ||
21385 (RootRatio == 1) != (OpRatio == 1)) &&
21386 "Must not have a ratio for both incoming and op masks!");
21388 SmallVector<int, 16> Mask;
21389 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21391 // Merge this shuffle operation's mask into our accumulated mask. Note that
21392 // this shuffle's mask will be the first applied to the input, followed by the
21393 // root mask to get us all the way to the root value arrangement. The reason
21394 // for this order is that we are recursing up the operation chain.
21395 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21396 int RootIdx = i / RootRatio;
21397 if (RootMask[RootIdx] < 0) {
21398 // This is a zero or undef lane, we're done.
21399 Mask.push_back(RootMask[RootIdx]);
21403 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21404 int OpIdx = RootMaskedIdx / OpRatio;
21405 if (OpMask[OpIdx] < 0) {
21406 // The incoming lanes are zero or undef, it doesn't matter which ones we
21408 Mask.push_back(OpMask[OpIdx]);
21412 // Ok, we have non-zero lanes, map them through.
21413 Mask.push_back(OpMask[OpIdx] * OpRatio +
21414 RootMaskedIdx % OpRatio);
21417 // See if we can recurse into the operand to combine more things.
21418 switch (Op.getOpcode()) {
21419 case X86ISD::PSHUFB:
21421 case X86ISD::PSHUFD:
21422 case X86ISD::PSHUFHW:
21423 case X86ISD::PSHUFLW:
21424 if (Op.getOperand(0).hasOneUse() &&
21425 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21426 HasPSHUFB, DAG, DCI, Subtarget))
21430 case X86ISD::UNPCKL:
21431 case X86ISD::UNPCKH:
21432 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21433 // We can't check for single use, we have to check that this shuffle is the only user.
21434 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21435 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21436 HasPSHUFB, DAG, DCI, Subtarget))
21441 // Minor canonicalization of the accumulated shuffle mask to make it easier
21442 // to match below. All this does is detect masks with squential pairs of
21443 // elements, and shrink them to the half-width mask. It does this in a loop
21444 // so it will reduce the size of the mask to the minimal width mask which
21445 // performs an equivalent shuffle.
21446 SmallVector<int, 16> WidenedMask;
21447 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21448 Mask = std::move(WidenedMask);
21449 WidenedMask.clear();
21452 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21456 /// \brief Get the PSHUF-style mask from PSHUF node.
21458 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21459 /// PSHUF-style masks that can be reused with such instructions.
21460 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21461 SmallVector<int, 4> Mask;
21463 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21467 switch (N.getOpcode()) {
21468 case X86ISD::PSHUFD:
21470 case X86ISD::PSHUFLW:
21473 case X86ISD::PSHUFHW:
21474 Mask.erase(Mask.begin(), Mask.begin() + 4);
21475 for (int &M : Mask)
21479 llvm_unreachable("No valid shuffle instruction found!");
21483 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21485 /// We walk up the chain and look for a combinable shuffle, skipping over
21486 /// shuffles that we could hoist this shuffle's transformation past without
21487 /// altering anything.
21489 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21491 TargetLowering::DAGCombinerInfo &DCI) {
21492 assert(N.getOpcode() == X86ISD::PSHUFD &&
21493 "Called with something other than an x86 128-bit half shuffle!");
21496 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21497 // of the shuffles in the chain so that we can form a fresh chain to replace
21499 SmallVector<SDValue, 8> Chain;
21500 SDValue V = N.getOperand(0);
21501 for (; V.hasOneUse(); V = V.getOperand(0)) {
21502 switch (V.getOpcode()) {
21504 return SDValue(); // Nothing combined!
21507 // Skip bitcasts as we always know the type for the target specific
21511 case X86ISD::PSHUFD:
21512 // Found another dword shuffle.
21515 case X86ISD::PSHUFLW:
21516 // Check that the low words (being shuffled) are the identity in the
21517 // dword shuffle, and the high words are self-contained.
21518 if (Mask[0] != 0 || Mask[1] != 1 ||
21519 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21522 Chain.push_back(V);
21525 case X86ISD::PSHUFHW:
21526 // Check that the high words (being shuffled) are the identity in the
21527 // dword shuffle, and the low words are self-contained.
21528 if (Mask[2] != 2 || Mask[3] != 3 ||
21529 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21532 Chain.push_back(V);
21535 case X86ISD::UNPCKL:
21536 case X86ISD::UNPCKH:
21537 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21538 // shuffle into a preceding word shuffle.
21539 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21542 // Search for a half-shuffle which we can combine with.
21543 unsigned CombineOp =
21544 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21545 if (V.getOperand(0) != V.getOperand(1) ||
21546 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21548 Chain.push_back(V);
21549 V = V.getOperand(0);
21551 switch (V.getOpcode()) {
21553 return SDValue(); // Nothing to combine.
21555 case X86ISD::PSHUFLW:
21556 case X86ISD::PSHUFHW:
21557 if (V.getOpcode() == CombineOp)
21560 Chain.push_back(V);
21564 V = V.getOperand(0);
21568 } while (V.hasOneUse());
21571 // Break out of the loop if we break out of the switch.
21575 if (!V.hasOneUse())
21576 // We fell out of the loop without finding a viable combining instruction.
21579 // Merge this node's mask and our incoming mask.
21580 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21581 for (int &M : Mask)
21583 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21584 getV4X86ShuffleImm8ForMask(Mask, DAG));
21586 // Rebuild the chain around this new shuffle.
21587 while (!Chain.empty()) {
21588 SDValue W = Chain.pop_back_val();
21590 if (V.getValueType() != W.getOperand(0).getValueType())
21591 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21593 switch (W.getOpcode()) {
21595 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21597 case X86ISD::UNPCKL:
21598 case X86ISD::UNPCKH:
21599 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21602 case X86ISD::PSHUFD:
21603 case X86ISD::PSHUFLW:
21604 case X86ISD::PSHUFHW:
21605 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21609 if (V.getValueType() != N.getValueType())
21610 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21612 // Return the new chain to replace N.
21616 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21618 /// We walk up the chain, skipping shuffles of the other half and looking
21619 /// through shuffles which switch halves trying to find a shuffle of the same
21620 /// pair of dwords.
21621 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21623 TargetLowering::DAGCombinerInfo &DCI) {
21625 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21626 "Called with something other than an x86 128-bit half shuffle!");
21628 unsigned CombineOpcode = N.getOpcode();
21630 // Walk up a single-use chain looking for a combinable shuffle.
21631 SDValue V = N.getOperand(0);
21632 for (; V.hasOneUse(); V = V.getOperand(0)) {
21633 switch (V.getOpcode()) {
21635 return false; // Nothing combined!
21638 // Skip bitcasts as we always know the type for the target specific
21642 case X86ISD::PSHUFLW:
21643 case X86ISD::PSHUFHW:
21644 if (V.getOpcode() == CombineOpcode)
21647 // Other-half shuffles are no-ops.
21650 // Break out of the loop if we break out of the switch.
21654 if (!V.hasOneUse())
21655 // We fell out of the loop without finding a viable combining instruction.
21658 // Combine away the bottom node as its shuffle will be accumulated into
21659 // a preceding shuffle.
21660 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21662 // Record the old value.
21665 // Merge this node's mask and our incoming mask (adjusted to account for all
21666 // the pshufd instructions encountered).
21667 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21668 for (int &M : Mask)
21670 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21671 getV4X86ShuffleImm8ForMask(Mask, DAG));
21673 // Check that the shuffles didn't cancel each other out. If not, we need to
21674 // combine to the new one.
21676 // Replace the combinable shuffle with the combined one, updating all users
21677 // so that we re-evaluate the chain here.
21678 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21683 /// \brief Try to combine x86 target specific shuffles.
21684 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21685 TargetLowering::DAGCombinerInfo &DCI,
21686 const X86Subtarget *Subtarget) {
21688 MVT VT = N.getSimpleValueType();
21689 SmallVector<int, 4> Mask;
21691 switch (N.getOpcode()) {
21692 case X86ISD::PSHUFD:
21693 case X86ISD::PSHUFLW:
21694 case X86ISD::PSHUFHW:
21695 Mask = getPSHUFShuffleMask(N);
21696 assert(Mask.size() == 4);
21702 // Nuke no-op shuffles that show up after combining.
21703 if (isNoopShuffleMask(Mask))
21704 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21706 // Look for simplifications involving one or two shuffle instructions.
21707 SDValue V = N.getOperand(0);
21708 switch (N.getOpcode()) {
21711 case X86ISD::PSHUFLW:
21712 case X86ISD::PSHUFHW:
21713 assert(VT == MVT::v8i16);
21716 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21717 return SDValue(); // We combined away this shuffle, so we're done.
21719 // See if this reduces to a PSHUFD which is no more expensive and can
21720 // combine with more operations. Note that it has to at least flip the
21721 // dwords as otherwise it would have been removed as a no-op.
21722 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21723 int DMask[] = {0, 1, 2, 3};
21724 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21725 DMask[DOffset + 0] = DOffset + 1;
21726 DMask[DOffset + 1] = DOffset + 0;
21727 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21728 DCI.AddToWorklist(V.getNode());
21729 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21730 getV4X86ShuffleImm8ForMask(DMask, DAG));
21731 DCI.AddToWorklist(V.getNode());
21732 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21735 // Look for shuffle patterns which can be implemented as a single unpack.
21736 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21737 // only works when we have a PSHUFD followed by two half-shuffles.
21738 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21739 (V.getOpcode() == X86ISD::PSHUFLW ||
21740 V.getOpcode() == X86ISD::PSHUFHW) &&
21741 V.getOpcode() != N.getOpcode() &&
21743 SDValue D = V.getOperand(0);
21744 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21745 D = D.getOperand(0);
21746 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21747 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21748 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21749 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21750 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21752 for (int i = 0; i < 4; ++i) {
21753 WordMask[i + NOffset] = Mask[i] + NOffset;
21754 WordMask[i + VOffset] = VMask[i] + VOffset;
21756 // Map the word mask through the DWord mask.
21758 for (int i = 0; i < 8; ++i)
21759 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21760 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21761 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21762 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21763 std::begin(UnpackLoMask)) ||
21764 std::equal(std::begin(MappedMask), std::end(MappedMask),
21765 std::begin(UnpackHiMask))) {
21766 // We can replace all three shuffles with an unpack.
21767 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21768 DCI.AddToWorklist(V.getNode());
21769 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21771 DL, MVT::v8i16, V, V);
21778 case X86ISD::PSHUFD:
21779 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21788 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21790 /// We combine this directly on the abstract vector shuffle nodes so it is
21791 /// easier to generically match. We also insert dummy vector shuffle nodes for
21792 /// the operands which explicitly discard the lanes which are unused by this
21793 /// operation to try to flow through the rest of the combiner the fact that
21794 /// they're unused.
21795 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21797 EVT VT = N->getValueType(0);
21799 // We only handle target-independent shuffles.
21800 // FIXME: It would be easy and harmless to use the target shuffle mask
21801 // extraction tool to support more.
21802 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21805 auto *SVN = cast<ShuffleVectorSDNode>(N);
21806 ArrayRef<int> Mask = SVN->getMask();
21807 SDValue V1 = N->getOperand(0);
21808 SDValue V2 = N->getOperand(1);
21810 // We require the first shuffle operand to be the SUB node, and the second to
21811 // be the ADD node.
21812 // FIXME: We should support the commuted patterns.
21813 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21816 // If there are other uses of these operations we can't fold them.
21817 if (!V1->hasOneUse() || !V2->hasOneUse())
21820 // Ensure that both operations have the same operands. Note that we can
21821 // commute the FADD operands.
21822 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21823 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21824 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21827 // We're looking for blends between FADD and FSUB nodes. We insist on these
21828 // nodes being lined up in a specific expected pattern.
21829 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21830 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21831 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21834 // Only specific types are legal at this point, assert so we notice if and
21835 // when these change.
21836 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21837 VT == MVT::v4f64) &&
21838 "Unknown vector type encountered!");
21840 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21843 /// PerformShuffleCombine - Performs several different shuffle combines.
21844 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21845 TargetLowering::DAGCombinerInfo &DCI,
21846 const X86Subtarget *Subtarget) {
21848 SDValue N0 = N->getOperand(0);
21849 SDValue N1 = N->getOperand(1);
21850 EVT VT = N->getValueType(0);
21852 // Don't create instructions with illegal types after legalize types has run.
21853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21854 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21857 // If we have legalized the vector types, look for blends of FADD and FSUB
21858 // nodes that we can fuse into an ADDSUB node.
21859 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21860 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21863 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21864 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21865 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21866 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21868 // During Type Legalization, when promoting illegal vector types,
21869 // the backend might introduce new shuffle dag nodes and bitcasts.
21871 // This code performs the following transformation:
21872 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21873 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21875 // We do this only if both the bitcast and the BINOP dag nodes have
21876 // one use. Also, perform this transformation only if the new binary
21877 // operation is legal. This is to avoid introducing dag nodes that
21878 // potentially need to be further expanded (or custom lowered) into a
21879 // less optimal sequence of dag nodes.
21880 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21881 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21882 N0.getOpcode() == ISD::BITCAST) {
21883 SDValue BC0 = N0.getOperand(0);
21884 EVT SVT = BC0.getValueType();
21885 unsigned Opcode = BC0.getOpcode();
21886 unsigned NumElts = VT.getVectorNumElements();
21888 if (BC0.hasOneUse() && SVT.isVector() &&
21889 SVT.getVectorNumElements() * 2 == NumElts &&
21890 TLI.isOperationLegal(Opcode, VT)) {
21891 bool CanFold = false;
21903 unsigned SVTNumElts = SVT.getVectorNumElements();
21904 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21905 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21906 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21907 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21908 CanFold = SVOp->getMaskElt(i) < 0;
21911 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21912 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21913 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21914 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21919 // Only handle 128 wide vector from here on.
21920 if (!VT.is128BitVector())
21923 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21924 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21925 // consecutive, non-overlapping, and in the right order.
21926 SmallVector<SDValue, 16> Elts;
21927 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21928 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21930 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21934 if (isTargetShuffle(N->getOpcode())) {
21936 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21937 if (Shuffle.getNode())
21940 // Try recursively combining arbitrary sequences of x86 shuffle
21941 // instructions into higher-order shuffles. We do this after combining
21942 // specific PSHUF instruction sequences into their minimal form so that we
21943 // can evaluate how many specialized shuffle instructions are involved in
21944 // a particular chain.
21945 SmallVector<int, 1> NonceMask; // Just a placeholder.
21946 NonceMask.push_back(0);
21947 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21948 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21950 return SDValue(); // This routine will use CombineTo to replace N.
21956 /// PerformTruncateCombine - Converts truncate operation to
21957 /// a sequence of vector shuffle operations.
21958 /// It is possible when we truncate 256-bit vector to 128-bit vector
21959 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21960 TargetLowering::DAGCombinerInfo &DCI,
21961 const X86Subtarget *Subtarget) {
21965 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21966 /// specific shuffle of a load can be folded into a single element load.
21967 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21968 /// shuffles have been custom lowered so we need to handle those here.
21969 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21970 TargetLowering::DAGCombinerInfo &DCI) {
21971 if (DCI.isBeforeLegalizeOps())
21974 SDValue InVec = N->getOperand(0);
21975 SDValue EltNo = N->getOperand(1);
21977 if (!isa<ConstantSDNode>(EltNo))
21980 EVT OriginalVT = InVec.getValueType();
21982 if (InVec.getOpcode() == ISD::BITCAST) {
21983 // Don't duplicate a load with other uses.
21984 if (!InVec.hasOneUse())
21986 EVT BCVT = InVec.getOperand(0).getValueType();
21987 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21989 InVec = InVec.getOperand(0);
21992 EVT CurrentVT = InVec.getValueType();
21994 if (!isTargetShuffle(InVec.getOpcode()))
21997 // Don't duplicate a load with other uses.
21998 if (!InVec.hasOneUse())
22001 SmallVector<int, 16> ShuffleMask;
22003 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22004 ShuffleMask, UnaryShuffle))
22007 // Select the input vector, guarding against out of range extract vector.
22008 unsigned NumElems = CurrentVT.getVectorNumElements();
22009 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22010 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22011 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22012 : InVec.getOperand(1);
22014 // If inputs to shuffle are the same for both ops, then allow 2 uses
22015 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22017 if (LdNode.getOpcode() == ISD::BITCAST) {
22018 // Don't duplicate a load with other uses.
22019 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22022 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22023 LdNode = LdNode.getOperand(0);
22026 if (!ISD::isNormalLoad(LdNode.getNode()))
22029 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22031 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22034 EVT EltVT = N->getValueType(0);
22035 // If there's a bitcast before the shuffle, check if the load type and
22036 // alignment is valid.
22037 unsigned Align = LN0->getAlignment();
22038 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22039 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22040 EltVT.getTypeForEVT(*DAG.getContext()));
22042 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22045 // All checks match so transform back to vector_shuffle so that DAG combiner
22046 // can finish the job
22049 // Create shuffle node taking into account the case that its a unary shuffle
22050 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22051 : InVec.getOperand(1);
22052 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22053 InVec.getOperand(0), Shuffle,
22055 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22056 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22060 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22061 /// generation and convert it from being a bunch of shuffles and extracts
22062 /// to a simple store and scalar loads to extract the elements.
22063 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22064 TargetLowering::DAGCombinerInfo &DCI) {
22065 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22066 if (NewOp.getNode())
22069 SDValue InputVector = N->getOperand(0);
22071 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22072 // from mmx to v2i32 has a single usage.
22073 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22074 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22075 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22076 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22077 N->getValueType(0),
22078 InputVector.getNode()->getOperand(0));
22080 // Only operate on vectors of 4 elements, where the alternative shuffling
22081 // gets to be more expensive.
22082 if (InputVector.getValueType() != MVT::v4i32)
22085 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22086 // single use which is a sign-extend or zero-extend, and all elements are
22088 SmallVector<SDNode *, 4> Uses;
22089 unsigned ExtractedElements = 0;
22090 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22091 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22092 if (UI.getUse().getResNo() != InputVector.getResNo())
22095 SDNode *Extract = *UI;
22096 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22099 if (Extract->getValueType(0) != MVT::i32)
22101 if (!Extract->hasOneUse())
22103 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22104 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22106 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22109 // Record which element was extracted.
22110 ExtractedElements |=
22111 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22113 Uses.push_back(Extract);
22116 // If not all the elements were used, this may not be worthwhile.
22117 if (ExtractedElements != 15)
22120 // Ok, we've now decided to do the transformation.
22121 SDLoc dl(InputVector);
22123 // Store the value to a temporary stack slot.
22124 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22125 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22126 MachinePointerInfo(), false, false, 0);
22128 // Replace each use (extract) with a load of the appropriate element.
22129 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22130 UE = Uses.end(); UI != UE; ++UI) {
22131 SDNode *Extract = *UI;
22133 // cOMpute the element's address.
22134 SDValue Idx = Extract->getOperand(1);
22136 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22137 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22139 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22141 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22142 StackPtr, OffsetVal);
22144 // Load the scalar.
22145 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22146 ScalarAddr, MachinePointerInfo(),
22147 false, false, false, 0);
22149 // Replace the exact with the load.
22150 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22153 // The replacement was made in place; don't return anything.
22157 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22158 static std::pair<unsigned, bool>
22159 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22160 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22161 if (!VT.isVector())
22162 return std::make_pair(0, false);
22164 bool NeedSplit = false;
22165 switch (VT.getSimpleVT().SimpleTy) {
22166 default: return std::make_pair(0, false);
22170 if (!Subtarget->hasAVX2())
22172 if (!Subtarget->hasAVX())
22173 return std::make_pair(0, false);
22178 if (!Subtarget->hasSSE2())
22179 return std::make_pair(0, false);
22182 // SSE2 has only a small subset of the operations.
22183 bool hasUnsigned = Subtarget->hasSSE41() ||
22184 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22185 bool hasSigned = Subtarget->hasSSE41() ||
22186 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22188 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22191 // Check for x CC y ? x : y.
22192 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22193 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22198 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22201 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22204 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22207 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22209 // Check for x CC y ? y : x -- a min/max with reversed arms.
22210 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22211 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22216 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22219 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22222 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22225 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22229 return std::make_pair(Opc, NeedSplit);
22233 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22234 const X86Subtarget *Subtarget) {
22236 SDValue Cond = N->getOperand(0);
22237 SDValue LHS = N->getOperand(1);
22238 SDValue RHS = N->getOperand(2);
22240 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22241 SDValue CondSrc = Cond->getOperand(0);
22242 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22243 Cond = CondSrc->getOperand(0);
22246 MVT VT = N->getSimpleValueType(0);
22247 MVT EltVT = VT.getVectorElementType();
22248 unsigned NumElems = VT.getVectorNumElements();
22249 // There is no blend with immediate in AVX-512.
22250 if (VT.is512BitVector())
22253 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22255 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22258 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22261 // A vselect where all conditions and data are constants can be optimized into
22262 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22263 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22264 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22267 unsigned MaskValue = 0;
22268 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22271 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22272 for (unsigned i = 0; i < NumElems; ++i) {
22273 // Be sure we emit undef where we can.
22274 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22275 ShuffleMask[i] = -1;
22277 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22280 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22283 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22285 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22286 TargetLowering::DAGCombinerInfo &DCI,
22287 const X86Subtarget *Subtarget) {
22289 SDValue Cond = N->getOperand(0);
22290 // Get the LHS/RHS of the select.
22291 SDValue LHS = N->getOperand(1);
22292 SDValue RHS = N->getOperand(2);
22293 EVT VT = LHS.getValueType();
22294 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22296 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22297 // instructions match the semantics of the common C idiom x<y?x:y but not
22298 // x<=y?x:y, because of how they handle negative zero (which can be
22299 // ignored in unsafe-math mode).
22300 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22301 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22302 (Subtarget->hasSSE2() ||
22303 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22304 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22306 unsigned Opcode = 0;
22307 // Check for x CC y ? x : y.
22308 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22309 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22313 // Converting this to a min would handle NaNs incorrectly, and swapping
22314 // the operands would cause it to handle comparisons between positive
22315 // and negative zero incorrectly.
22316 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22317 if (!DAG.getTarget().Options.UnsafeFPMath &&
22318 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22320 std::swap(LHS, RHS);
22322 Opcode = X86ISD::FMIN;
22325 // Converting this to a min would handle comparisons between positive
22326 // and negative zero incorrectly.
22327 if (!DAG.getTarget().Options.UnsafeFPMath &&
22328 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22330 Opcode = X86ISD::FMIN;
22333 // Converting this to a min would handle both negative zeros and NaNs
22334 // incorrectly, but we can swap the operands to fix both.
22335 std::swap(LHS, RHS);
22339 Opcode = X86ISD::FMIN;
22343 // Converting this to a max would handle comparisons between positive
22344 // and negative zero incorrectly.
22345 if (!DAG.getTarget().Options.UnsafeFPMath &&
22346 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22348 Opcode = X86ISD::FMAX;
22351 // Converting this to a max would handle NaNs incorrectly, and swapping
22352 // the operands would cause it to handle comparisons between positive
22353 // and negative zero incorrectly.
22354 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22355 if (!DAG.getTarget().Options.UnsafeFPMath &&
22356 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22358 std::swap(LHS, RHS);
22360 Opcode = X86ISD::FMAX;
22363 // Converting this to a max would handle both negative zeros and NaNs
22364 // incorrectly, but we can swap the operands to fix both.
22365 std::swap(LHS, RHS);
22369 Opcode = X86ISD::FMAX;
22372 // Check for x CC y ? y : x -- a min/max with reversed arms.
22373 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22374 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22378 // Converting this to a min would handle comparisons between positive
22379 // and negative zero incorrectly, and swapping the operands would
22380 // cause it to handle NaNs incorrectly.
22381 if (!DAG.getTarget().Options.UnsafeFPMath &&
22382 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22383 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22385 std::swap(LHS, RHS);
22387 Opcode = X86ISD::FMIN;
22390 // Converting this to a min would handle NaNs incorrectly.
22391 if (!DAG.getTarget().Options.UnsafeFPMath &&
22392 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22394 Opcode = X86ISD::FMIN;
22397 // Converting this to a min would handle both negative zeros and NaNs
22398 // incorrectly, but we can swap the operands to fix both.
22399 std::swap(LHS, RHS);
22403 Opcode = X86ISD::FMIN;
22407 // Converting this to a max would handle NaNs incorrectly.
22408 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22410 Opcode = X86ISD::FMAX;
22413 // Converting this to a max would handle comparisons between positive
22414 // and negative zero incorrectly, and swapping the operands would
22415 // cause it to handle NaNs incorrectly.
22416 if (!DAG.getTarget().Options.UnsafeFPMath &&
22417 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22418 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22420 std::swap(LHS, RHS);
22422 Opcode = X86ISD::FMAX;
22425 // Converting this to a max would handle both negative zeros and NaNs
22426 // incorrectly, but we can swap the operands to fix both.
22427 std::swap(LHS, RHS);
22431 Opcode = X86ISD::FMAX;
22437 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22440 EVT CondVT = Cond.getValueType();
22441 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22442 CondVT.getVectorElementType() == MVT::i1) {
22443 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22444 // lowering on KNL. In this case we convert it to
22445 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22446 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22447 // Since SKX these selects have a proper lowering.
22448 EVT OpVT = LHS.getValueType();
22449 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22450 (OpVT.getVectorElementType() == MVT::i8 ||
22451 OpVT.getVectorElementType() == MVT::i16) &&
22452 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22453 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22454 DCI.AddToWorklist(Cond.getNode());
22455 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22458 // If this is a select between two integer constants, try to do some
22460 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22461 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22462 // Don't do this for crazy integer types.
22463 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22464 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22465 // so that TrueC (the true value) is larger than FalseC.
22466 bool NeedsCondInvert = false;
22468 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22469 // Efficiently invertible.
22470 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22471 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22472 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22473 NeedsCondInvert = true;
22474 std::swap(TrueC, FalseC);
22477 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22478 if (FalseC->getAPIntValue() == 0 &&
22479 TrueC->getAPIntValue().isPowerOf2()) {
22480 if (NeedsCondInvert) // Invert the condition if needed.
22481 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22482 DAG.getConstant(1, Cond.getValueType()));
22484 // Zero extend the condition if needed.
22485 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22487 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22488 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22489 DAG.getConstant(ShAmt, MVT::i8));
22492 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22493 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22494 if (NeedsCondInvert) // Invert the condition if needed.
22495 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22496 DAG.getConstant(1, Cond.getValueType()));
22498 // Zero extend the condition if needed.
22499 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22500 FalseC->getValueType(0), Cond);
22501 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22502 SDValue(FalseC, 0));
22505 // Optimize cases that will turn into an LEA instruction. This requires
22506 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22507 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22508 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22509 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22511 bool isFastMultiplier = false;
22513 switch ((unsigned char)Diff) {
22515 case 1: // result = add base, cond
22516 case 2: // result = lea base( , cond*2)
22517 case 3: // result = lea base(cond, cond*2)
22518 case 4: // result = lea base( , cond*4)
22519 case 5: // result = lea base(cond, cond*4)
22520 case 8: // result = lea base( , cond*8)
22521 case 9: // result = lea base(cond, cond*8)
22522 isFastMultiplier = true;
22527 if (isFastMultiplier) {
22528 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22529 if (NeedsCondInvert) // Invert the condition if needed.
22530 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22531 DAG.getConstant(1, Cond.getValueType()));
22533 // Zero extend the condition if needed.
22534 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22536 // Scale the condition by the difference.
22538 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22539 DAG.getConstant(Diff, Cond.getValueType()));
22541 // Add the base if non-zero.
22542 if (FalseC->getAPIntValue() != 0)
22543 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22544 SDValue(FalseC, 0));
22551 // Canonicalize max and min:
22552 // (x > y) ? x : y -> (x >= y) ? x : y
22553 // (x < y) ? x : y -> (x <= y) ? x : y
22554 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22555 // the need for an extra compare
22556 // against zero. e.g.
22557 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22559 // testl %edi, %edi
22561 // cmovgl %edi, %eax
22565 // cmovsl %eax, %edi
22566 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22567 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22568 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22569 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22574 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22575 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22576 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22577 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22582 // Early exit check
22583 if (!TLI.isTypeLegal(VT))
22586 // Match VSELECTs into subs with unsigned saturation.
22587 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22588 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22589 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22590 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22591 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22593 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22594 // left side invert the predicate to simplify logic below.
22596 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22598 CC = ISD::getSetCCInverse(CC, true);
22599 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22603 if (Other.getNode() && Other->getNumOperands() == 2 &&
22604 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22605 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22606 SDValue CondRHS = Cond->getOperand(1);
22608 // Look for a general sub with unsigned saturation first.
22609 // x >= y ? x-y : 0 --> subus x, y
22610 // x > y ? x-y : 0 --> subus x, y
22611 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22612 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22613 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22615 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22616 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22617 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22618 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22619 // If the RHS is a constant we have to reverse the const
22620 // canonicalization.
22621 // x > C-1 ? x+-C : 0 --> subus x, C
22622 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22623 CondRHSConst->getAPIntValue() ==
22624 (-OpRHSConst->getAPIntValue() - 1))
22625 return DAG.getNode(
22626 X86ISD::SUBUS, DL, VT, OpLHS,
22627 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22629 // Another special case: If C was a sign bit, the sub has been
22630 // canonicalized into a xor.
22631 // FIXME: Would it be better to use computeKnownBits to determine
22632 // whether it's safe to decanonicalize the xor?
22633 // x s< 0 ? x^C : 0 --> subus x, C
22634 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22635 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22636 OpRHSConst->getAPIntValue().isSignBit())
22637 // Note that we have to rebuild the RHS constant here to ensure we
22638 // don't rely on particular values of undef lanes.
22639 return DAG.getNode(
22640 X86ISD::SUBUS, DL, VT, OpLHS,
22641 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22646 // Try to match a min/max vector operation.
22647 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22648 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22649 unsigned Opc = ret.first;
22650 bool NeedSplit = ret.second;
22652 if (Opc && NeedSplit) {
22653 unsigned NumElems = VT.getVectorNumElements();
22654 // Extract the LHS vectors
22655 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22656 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22658 // Extract the RHS vectors
22659 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22660 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22662 // Create min/max for each subvector
22663 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22664 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22666 // Merge the result
22667 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22669 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22672 // Simplify vector selection if condition value type matches vselect
22674 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22675 assert(Cond.getValueType().isVector() &&
22676 "vector select expects a vector selector!");
22678 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22679 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22681 // Try invert the condition if true value is not all 1s and false value
22683 if (!TValIsAllOnes && !FValIsAllZeros &&
22684 // Check if the selector will be produced by CMPP*/PCMP*
22685 Cond.getOpcode() == ISD::SETCC &&
22686 // Check if SETCC has already been promoted
22687 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22688 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22689 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22691 if (TValIsAllZeros || FValIsAllOnes) {
22692 SDValue CC = Cond.getOperand(2);
22693 ISD::CondCode NewCC =
22694 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22695 Cond.getOperand(0).getValueType().isInteger());
22696 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22697 std::swap(LHS, RHS);
22698 TValIsAllOnes = FValIsAllOnes;
22699 FValIsAllZeros = TValIsAllZeros;
22703 if (TValIsAllOnes || FValIsAllZeros) {
22706 if (TValIsAllOnes && FValIsAllZeros)
22708 else if (TValIsAllOnes)
22709 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22710 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22711 else if (FValIsAllZeros)
22712 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22713 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22715 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22719 // Try to fold this VSELECT into a MOVSS/MOVSD
22720 if (N->getOpcode() == ISD::VSELECT &&
22721 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22722 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22723 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22724 bool CanFold = false;
22725 unsigned NumElems = Cond.getNumOperands();
22729 if (isZero(Cond.getOperand(0))) {
22732 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22733 // fold (vselect <0,-1> -> (movsd A, B)
22734 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22735 CanFold = isAllOnes(Cond.getOperand(i));
22736 } else if (isAllOnes(Cond.getOperand(0))) {
22740 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22741 // fold (vselect <-1,0> -> (movsd B, A)
22742 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22743 CanFold = isZero(Cond.getOperand(i));
22747 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22748 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22749 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22752 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22753 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22754 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22755 // (v2i64 (bitcast B)))))
22757 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22758 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22759 // (v2f64 (bitcast B)))))
22761 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22762 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22763 // (v2i64 (bitcast A)))))
22765 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22766 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22767 // (v2f64 (bitcast A)))))
22769 CanFold = (isZero(Cond.getOperand(0)) &&
22770 isZero(Cond.getOperand(1)) &&
22771 isAllOnes(Cond.getOperand(2)) &&
22772 isAllOnes(Cond.getOperand(3)));
22774 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22775 isAllOnes(Cond.getOperand(1)) &&
22776 isZero(Cond.getOperand(2)) &&
22777 isZero(Cond.getOperand(3))) {
22779 std::swap(LHS, RHS);
22783 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22784 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22785 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22786 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22788 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22794 // If we know that this node is legal then we know that it is going to be
22795 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22796 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22797 // to simplify previous instructions.
22798 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22799 !DCI.isBeforeLegalize() &&
22800 // We explicitly check against v8i16 and v16i16 because, although
22801 // they're marked as Custom, they might only be legal when Cond is a
22802 // build_vector of constants. This will be taken care in a later
22804 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22805 VT != MVT::v8i16) &&
22806 // Don't optimize vector of constants. Those are handled by
22807 // the generic code and all the bits must be properly set for
22808 // the generic optimizer.
22809 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22810 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22812 // Don't optimize vector selects that map to mask-registers.
22816 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22817 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22819 APInt KnownZero, KnownOne;
22820 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22821 DCI.isBeforeLegalizeOps());
22822 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22823 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22825 // If we changed the computation somewhere in the DAG, this change
22826 // will affect all users of Cond.
22827 // Make sure it is fine and update all the nodes so that we do not
22828 // use the generic VSELECT anymore. Otherwise, we may perform
22829 // wrong optimizations as we messed up with the actual expectation
22830 // for the vector boolean values.
22831 if (Cond != TLO.Old) {
22832 // Check all uses of that condition operand to check whether it will be
22833 // consumed by non-BLEND instructions, which may depend on all bits are
22835 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22837 if (I->getOpcode() != ISD::VSELECT)
22838 // TODO: Add other opcodes eventually lowered into BLEND.
22841 // Update all the users of the condition, before committing the change,
22842 // so that the VSELECT optimizations that expect the correct vector
22843 // boolean value will not be triggered.
22844 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22846 DAG.ReplaceAllUsesOfValueWith(
22848 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22849 Cond, I->getOperand(1), I->getOperand(2)));
22850 DCI.CommitTargetLoweringOpt(TLO);
22853 // At this point, only Cond is changed. Change the condition
22854 // just for N to keep the opportunity to optimize all other
22855 // users their own way.
22856 DAG.ReplaceAllUsesOfValueWith(
22858 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22859 TLO.New, N->getOperand(1), N->getOperand(2)));
22864 // We should generate an X86ISD::BLENDI from a vselect if its argument
22865 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22866 // constants. This specific pattern gets generated when we split a
22867 // selector for a 512 bit vector in a machine without AVX512 (but with
22868 // 256-bit vectors), during legalization:
22870 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22872 // Iff we find this pattern and the build_vectors are built from
22873 // constants, we translate the vselect into a shuffle_vector that we
22874 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22875 if ((N->getOpcode() == ISD::VSELECT ||
22876 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22877 !DCI.isBeforeLegalize()) {
22878 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22879 if (Shuffle.getNode())
22886 // Check whether a boolean test is testing a boolean value generated by
22887 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22890 // Simplify the following patterns:
22891 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22892 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22893 // to (Op EFLAGS Cond)
22895 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22896 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22897 // to (Op EFLAGS !Cond)
22899 // where Op could be BRCOND or CMOV.
22901 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22902 // Quit if not CMP and SUB with its value result used.
22903 if (Cmp.getOpcode() != X86ISD::CMP &&
22904 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22907 // Quit if not used as a boolean value.
22908 if (CC != X86::COND_E && CC != X86::COND_NE)
22911 // Check CMP operands. One of them should be 0 or 1 and the other should be
22912 // an SetCC or extended from it.
22913 SDValue Op1 = Cmp.getOperand(0);
22914 SDValue Op2 = Cmp.getOperand(1);
22917 const ConstantSDNode* C = nullptr;
22918 bool needOppositeCond = (CC == X86::COND_E);
22919 bool checkAgainstTrue = false; // Is it a comparison against 1?
22921 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22923 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22925 else // Quit if all operands are not constants.
22928 if (C->getZExtValue() == 1) {
22929 needOppositeCond = !needOppositeCond;
22930 checkAgainstTrue = true;
22931 } else if (C->getZExtValue() != 0)
22932 // Quit if the constant is neither 0 or 1.
22935 bool truncatedToBoolWithAnd = false;
22936 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22937 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22938 SetCC.getOpcode() == ISD::TRUNCATE ||
22939 SetCC.getOpcode() == ISD::AND) {
22940 if (SetCC.getOpcode() == ISD::AND) {
22942 ConstantSDNode *CS;
22943 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22944 CS->getZExtValue() == 1)
22946 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22947 CS->getZExtValue() == 1)
22951 SetCC = SetCC.getOperand(OpIdx);
22952 truncatedToBoolWithAnd = true;
22954 SetCC = SetCC.getOperand(0);
22957 switch (SetCC.getOpcode()) {
22958 case X86ISD::SETCC_CARRY:
22959 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22960 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22961 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22962 // truncated to i1 using 'and'.
22963 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22965 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22966 "Invalid use of SETCC_CARRY!");
22968 case X86ISD::SETCC:
22969 // Set the condition code or opposite one if necessary.
22970 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22971 if (needOppositeCond)
22972 CC = X86::GetOppositeBranchCondition(CC);
22973 return SetCC.getOperand(1);
22974 case X86ISD::CMOV: {
22975 // Check whether false/true value has canonical one, i.e. 0 or 1.
22976 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22977 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22978 // Quit if true value is not a constant.
22981 // Quit if false value is not a constant.
22983 SDValue Op = SetCC.getOperand(0);
22984 // Skip 'zext' or 'trunc' node.
22985 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22986 Op.getOpcode() == ISD::TRUNCATE)
22987 Op = Op.getOperand(0);
22988 // A special case for rdrand/rdseed, where 0 is set if false cond is
22990 if ((Op.getOpcode() != X86ISD::RDRAND &&
22991 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22994 // Quit if false value is not the constant 0 or 1.
22995 bool FValIsFalse = true;
22996 if (FVal && FVal->getZExtValue() != 0) {
22997 if (FVal->getZExtValue() != 1)
22999 // If FVal is 1, opposite cond is needed.
23000 needOppositeCond = !needOppositeCond;
23001 FValIsFalse = false;
23003 // Quit if TVal is not the constant opposite of FVal.
23004 if (FValIsFalse && TVal->getZExtValue() != 1)
23006 if (!FValIsFalse && TVal->getZExtValue() != 0)
23008 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23009 if (needOppositeCond)
23010 CC = X86::GetOppositeBranchCondition(CC);
23011 return SetCC.getOperand(3);
23018 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23019 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23020 TargetLowering::DAGCombinerInfo &DCI,
23021 const X86Subtarget *Subtarget) {
23024 // If the flag operand isn't dead, don't touch this CMOV.
23025 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23028 SDValue FalseOp = N->getOperand(0);
23029 SDValue TrueOp = N->getOperand(1);
23030 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23031 SDValue Cond = N->getOperand(3);
23033 if (CC == X86::COND_E || CC == X86::COND_NE) {
23034 switch (Cond.getOpcode()) {
23038 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23039 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23040 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23046 Flags = checkBoolTestSetCCCombine(Cond, CC);
23047 if (Flags.getNode() &&
23048 // Extra check as FCMOV only supports a subset of X86 cond.
23049 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23050 SDValue Ops[] = { FalseOp, TrueOp,
23051 DAG.getConstant(CC, MVT::i8), Flags };
23052 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23055 // If this is a select between two integer constants, try to do some
23056 // optimizations. Note that the operands are ordered the opposite of SELECT
23058 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23059 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23060 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23061 // larger than FalseC (the false value).
23062 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23063 CC = X86::GetOppositeBranchCondition(CC);
23064 std::swap(TrueC, FalseC);
23065 std::swap(TrueOp, FalseOp);
23068 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23069 // This is efficient for any integer data type (including i8/i16) and
23071 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23072 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23073 DAG.getConstant(CC, MVT::i8), Cond);
23075 // Zero extend the condition if needed.
23076 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23078 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23079 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23080 DAG.getConstant(ShAmt, MVT::i8));
23081 if (N->getNumValues() == 2) // Dead flag value?
23082 return DCI.CombineTo(N, Cond, SDValue());
23086 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23087 // for any integer data type, including i8/i16.
23088 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23089 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23090 DAG.getConstant(CC, MVT::i8), Cond);
23092 // Zero extend the condition if needed.
23093 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23094 FalseC->getValueType(0), Cond);
23095 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23096 SDValue(FalseC, 0));
23098 if (N->getNumValues() == 2) // Dead flag value?
23099 return DCI.CombineTo(N, Cond, SDValue());
23103 // Optimize cases that will turn into an LEA instruction. This requires
23104 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23105 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23106 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23107 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23109 bool isFastMultiplier = false;
23111 switch ((unsigned char)Diff) {
23113 case 1: // result = add base, cond
23114 case 2: // result = lea base( , cond*2)
23115 case 3: // result = lea base(cond, cond*2)
23116 case 4: // result = lea base( , cond*4)
23117 case 5: // result = lea base(cond, cond*4)
23118 case 8: // result = lea base( , cond*8)
23119 case 9: // result = lea base(cond, cond*8)
23120 isFastMultiplier = true;
23125 if (isFastMultiplier) {
23126 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23127 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23128 DAG.getConstant(CC, MVT::i8), Cond);
23129 // Zero extend the condition if needed.
23130 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23132 // Scale the condition by the difference.
23134 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23135 DAG.getConstant(Diff, Cond.getValueType()));
23137 // Add the base if non-zero.
23138 if (FalseC->getAPIntValue() != 0)
23139 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23140 SDValue(FalseC, 0));
23141 if (N->getNumValues() == 2) // Dead flag value?
23142 return DCI.CombineTo(N, Cond, SDValue());
23149 // Handle these cases:
23150 // (select (x != c), e, c) -> select (x != c), e, x),
23151 // (select (x == c), c, e) -> select (x == c), x, e)
23152 // where the c is an integer constant, and the "select" is the combination
23153 // of CMOV and CMP.
23155 // The rationale for this change is that the conditional-move from a constant
23156 // needs two instructions, however, conditional-move from a register needs
23157 // only one instruction.
23159 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23160 // some instruction-combining opportunities. This opt needs to be
23161 // postponed as late as possible.
23163 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23164 // the DCI.xxxx conditions are provided to postpone the optimization as
23165 // late as possible.
23167 ConstantSDNode *CmpAgainst = nullptr;
23168 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23169 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23170 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23172 if (CC == X86::COND_NE &&
23173 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23174 CC = X86::GetOppositeBranchCondition(CC);
23175 std::swap(TrueOp, FalseOp);
23178 if (CC == X86::COND_E &&
23179 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23180 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23181 DAG.getConstant(CC, MVT::i8), Cond };
23182 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23190 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23191 const X86Subtarget *Subtarget) {
23192 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23194 default: return SDValue();
23195 // SSE/AVX/AVX2 blend intrinsics.
23196 case Intrinsic::x86_avx2_pblendvb:
23197 case Intrinsic::x86_avx2_pblendw:
23198 case Intrinsic::x86_avx2_pblendd_128:
23199 case Intrinsic::x86_avx2_pblendd_256:
23200 // Don't try to simplify this intrinsic if we don't have AVX2.
23201 if (!Subtarget->hasAVX2())
23204 case Intrinsic::x86_avx_blend_pd_256:
23205 case Intrinsic::x86_avx_blend_ps_256:
23206 case Intrinsic::x86_avx_blendv_pd_256:
23207 case Intrinsic::x86_avx_blendv_ps_256:
23208 // Don't try to simplify this intrinsic if we don't have AVX.
23209 if (!Subtarget->hasAVX())
23212 case Intrinsic::x86_sse41_pblendw:
23213 case Intrinsic::x86_sse41_blendpd:
23214 case Intrinsic::x86_sse41_blendps:
23215 case Intrinsic::x86_sse41_blendvps:
23216 case Intrinsic::x86_sse41_blendvpd:
23217 case Intrinsic::x86_sse41_pblendvb: {
23218 SDValue Op0 = N->getOperand(1);
23219 SDValue Op1 = N->getOperand(2);
23220 SDValue Mask = N->getOperand(3);
23222 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23223 if (!Subtarget->hasSSE41())
23226 // fold (blend A, A, Mask) -> A
23229 // fold (blend A, B, allZeros) -> A
23230 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23232 // fold (blend A, B, allOnes) -> B
23233 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23236 // Simplify the case where the mask is a constant i32 value.
23237 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23238 if (C->isNullValue())
23240 if (C->isAllOnesValue())
23247 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23248 case Intrinsic::x86_sse2_psrai_w:
23249 case Intrinsic::x86_sse2_psrai_d:
23250 case Intrinsic::x86_avx2_psrai_w:
23251 case Intrinsic::x86_avx2_psrai_d:
23252 case Intrinsic::x86_sse2_psra_w:
23253 case Intrinsic::x86_sse2_psra_d:
23254 case Intrinsic::x86_avx2_psra_w:
23255 case Intrinsic::x86_avx2_psra_d: {
23256 SDValue Op0 = N->getOperand(1);
23257 SDValue Op1 = N->getOperand(2);
23258 EVT VT = Op0.getValueType();
23259 assert(VT.isVector() && "Expected a vector type!");
23261 if (isa<BuildVectorSDNode>(Op1))
23262 Op1 = Op1.getOperand(0);
23264 if (!isa<ConstantSDNode>(Op1))
23267 EVT SVT = VT.getVectorElementType();
23268 unsigned SVTBits = SVT.getSizeInBits();
23270 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23271 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23272 uint64_t ShAmt = C.getZExtValue();
23274 // Don't try to convert this shift into a ISD::SRA if the shift
23275 // count is bigger than or equal to the element size.
23276 if (ShAmt >= SVTBits)
23279 // Trivial case: if the shift count is zero, then fold this
23280 // into the first operand.
23284 // Replace this packed shift intrinsic with a target independent
23286 SDValue Splat = DAG.getConstant(C, VT);
23287 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23292 /// PerformMulCombine - Optimize a single multiply with constant into two
23293 /// in order to implement it with two cheaper instructions, e.g.
23294 /// LEA + SHL, LEA + LEA.
23295 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23296 TargetLowering::DAGCombinerInfo &DCI) {
23297 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23300 EVT VT = N->getValueType(0);
23301 if (VT != MVT::i64)
23304 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23307 uint64_t MulAmt = C->getZExtValue();
23308 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23311 uint64_t MulAmt1 = 0;
23312 uint64_t MulAmt2 = 0;
23313 if ((MulAmt % 9) == 0) {
23315 MulAmt2 = MulAmt / 9;
23316 } else if ((MulAmt % 5) == 0) {
23318 MulAmt2 = MulAmt / 5;
23319 } else if ((MulAmt % 3) == 0) {
23321 MulAmt2 = MulAmt / 3;
23324 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23327 if (isPowerOf2_64(MulAmt2) &&
23328 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23329 // If second multiplifer is pow2, issue it first. We want the multiply by
23330 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23332 std::swap(MulAmt1, MulAmt2);
23335 if (isPowerOf2_64(MulAmt1))
23336 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23337 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23339 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23340 DAG.getConstant(MulAmt1, VT));
23342 if (isPowerOf2_64(MulAmt2))
23343 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23344 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23346 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23347 DAG.getConstant(MulAmt2, VT));
23349 // Do not add new nodes to DAG combiner worklist.
23350 DCI.CombineTo(N, NewMul, false);
23355 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23356 SDValue N0 = N->getOperand(0);
23357 SDValue N1 = N->getOperand(1);
23358 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23359 EVT VT = N0.getValueType();
23361 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23362 // since the result of setcc_c is all zero's or all ones.
23363 if (VT.isInteger() && !VT.isVector() &&
23364 N1C && N0.getOpcode() == ISD::AND &&
23365 N0.getOperand(1).getOpcode() == ISD::Constant) {
23366 SDValue N00 = N0.getOperand(0);
23367 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23368 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23369 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23370 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23371 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23372 APInt ShAmt = N1C->getAPIntValue();
23373 Mask = Mask.shl(ShAmt);
23375 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23376 N00, DAG.getConstant(Mask, VT));
23380 // Hardware support for vector shifts is sparse which makes us scalarize the
23381 // vector operations in many cases. Also, on sandybridge ADD is faster than
23383 // (shl V, 1) -> add V,V
23384 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23385 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23386 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23387 // We shift all of the values by one. In many cases we do not have
23388 // hardware support for this operation. This is better expressed as an ADD
23390 if (N1SplatC->getZExtValue() == 1)
23391 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23397 /// \brief Returns a vector of 0s if the node in input is a vector logical
23398 /// shift by a constant amount which is known to be bigger than or equal
23399 /// to the vector element size in bits.
23400 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23401 const X86Subtarget *Subtarget) {
23402 EVT VT = N->getValueType(0);
23404 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23405 (!Subtarget->hasInt256() ||
23406 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23409 SDValue Amt = N->getOperand(1);
23411 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23412 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23413 APInt ShiftAmt = AmtSplat->getAPIntValue();
23414 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23416 // SSE2/AVX2 logical shifts always return a vector of 0s
23417 // if the shift amount is bigger than or equal to
23418 // the element size. The constant shift amount will be
23419 // encoded as a 8-bit immediate.
23420 if (ShiftAmt.trunc(8).uge(MaxAmount))
23421 return getZeroVector(VT, Subtarget, DAG, DL);
23427 /// PerformShiftCombine - Combine shifts.
23428 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23429 TargetLowering::DAGCombinerInfo &DCI,
23430 const X86Subtarget *Subtarget) {
23431 if (N->getOpcode() == ISD::SHL) {
23432 SDValue V = PerformSHLCombine(N, DAG);
23433 if (V.getNode()) return V;
23436 if (N->getOpcode() != ISD::SRA) {
23437 // Try to fold this logical shift into a zero vector.
23438 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23439 if (V.getNode()) return V;
23445 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23446 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23447 // and friends. Likewise for OR -> CMPNEQSS.
23448 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23449 TargetLowering::DAGCombinerInfo &DCI,
23450 const X86Subtarget *Subtarget) {
23453 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23454 // we're requiring SSE2 for both.
23455 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23456 SDValue N0 = N->getOperand(0);
23457 SDValue N1 = N->getOperand(1);
23458 SDValue CMP0 = N0->getOperand(1);
23459 SDValue CMP1 = N1->getOperand(1);
23462 // The SETCCs should both refer to the same CMP.
23463 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23466 SDValue CMP00 = CMP0->getOperand(0);
23467 SDValue CMP01 = CMP0->getOperand(1);
23468 EVT VT = CMP00.getValueType();
23470 if (VT == MVT::f32 || VT == MVT::f64) {
23471 bool ExpectingFlags = false;
23472 // Check for any users that want flags:
23473 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23474 !ExpectingFlags && UI != UE; ++UI)
23475 switch (UI->getOpcode()) {
23480 ExpectingFlags = true;
23482 case ISD::CopyToReg:
23483 case ISD::SIGN_EXTEND:
23484 case ISD::ZERO_EXTEND:
23485 case ISD::ANY_EXTEND:
23489 if (!ExpectingFlags) {
23490 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23491 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23493 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23494 X86::CondCode tmp = cc0;
23499 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23500 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23501 // FIXME: need symbolic constants for these magic numbers.
23502 // See X86ATTInstPrinter.cpp:printSSECC().
23503 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23504 if (Subtarget->hasAVX512()) {
23505 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23506 CMP01, DAG.getConstant(x86cc, MVT::i8));
23507 if (N->getValueType(0) != MVT::i1)
23508 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23512 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23513 CMP00.getValueType(), CMP00, CMP01,
23514 DAG.getConstant(x86cc, MVT::i8));
23516 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23517 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23519 if (is64BitFP && !Subtarget->is64Bit()) {
23520 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23521 // 64-bit integer, since that's not a legal type. Since
23522 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23523 // bits, but can do this little dance to extract the lowest 32 bits
23524 // and work with those going forward.
23525 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23527 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23529 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23530 Vector32, DAG.getIntPtrConstant(0));
23534 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23535 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23536 DAG.getConstant(1, IntVT));
23537 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23538 return OneBitOfTruth;
23546 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23547 /// so it can be folded inside ANDNP.
23548 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23549 EVT VT = N->getValueType(0);
23551 // Match direct AllOnes for 128 and 256-bit vectors
23552 if (ISD::isBuildVectorAllOnes(N))
23555 // Look through a bit convert.
23556 if (N->getOpcode() == ISD::BITCAST)
23557 N = N->getOperand(0).getNode();
23559 // Sometimes the operand may come from a insert_subvector building a 256-bit
23561 if (VT.is256BitVector() &&
23562 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23563 SDValue V1 = N->getOperand(0);
23564 SDValue V2 = N->getOperand(1);
23566 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23567 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23568 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23569 ISD::isBuildVectorAllOnes(V2.getNode()))
23576 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23577 // register. In most cases we actually compare or select YMM-sized registers
23578 // and mixing the two types creates horrible code. This method optimizes
23579 // some of the transition sequences.
23580 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23581 TargetLowering::DAGCombinerInfo &DCI,
23582 const X86Subtarget *Subtarget) {
23583 EVT VT = N->getValueType(0);
23584 if (!VT.is256BitVector())
23587 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23588 N->getOpcode() == ISD::ZERO_EXTEND ||
23589 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23591 SDValue Narrow = N->getOperand(0);
23592 EVT NarrowVT = Narrow->getValueType(0);
23593 if (!NarrowVT.is128BitVector())
23596 if (Narrow->getOpcode() != ISD::XOR &&
23597 Narrow->getOpcode() != ISD::AND &&
23598 Narrow->getOpcode() != ISD::OR)
23601 SDValue N0 = Narrow->getOperand(0);
23602 SDValue N1 = Narrow->getOperand(1);
23605 // The Left side has to be a trunc.
23606 if (N0.getOpcode() != ISD::TRUNCATE)
23609 // The type of the truncated inputs.
23610 EVT WideVT = N0->getOperand(0)->getValueType(0);
23614 // The right side has to be a 'trunc' or a constant vector.
23615 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23616 ConstantSDNode *RHSConstSplat = nullptr;
23617 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23618 RHSConstSplat = RHSBV->getConstantSplatNode();
23619 if (!RHSTrunc && !RHSConstSplat)
23622 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23624 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23627 // Set N0 and N1 to hold the inputs to the new wide operation.
23628 N0 = N0->getOperand(0);
23629 if (RHSConstSplat) {
23630 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23631 SDValue(RHSConstSplat, 0));
23632 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23633 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23634 } else if (RHSTrunc) {
23635 N1 = N1->getOperand(0);
23638 // Generate the wide operation.
23639 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23640 unsigned Opcode = N->getOpcode();
23642 case ISD::ANY_EXTEND:
23644 case ISD::ZERO_EXTEND: {
23645 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23646 APInt Mask = APInt::getAllOnesValue(InBits);
23647 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23648 return DAG.getNode(ISD::AND, DL, VT,
23649 Op, DAG.getConstant(Mask, VT));
23651 case ISD::SIGN_EXTEND:
23652 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23653 Op, DAG.getValueType(NarrowVT));
23655 llvm_unreachable("Unexpected opcode");
23659 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23660 TargetLowering::DAGCombinerInfo &DCI,
23661 const X86Subtarget *Subtarget) {
23662 EVT VT = N->getValueType(0);
23663 if (DCI.isBeforeLegalizeOps())
23666 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23670 // Create BEXTR instructions
23671 // BEXTR is ((X >> imm) & (2**size-1))
23672 if (VT == MVT::i32 || VT == MVT::i64) {
23673 SDValue N0 = N->getOperand(0);
23674 SDValue N1 = N->getOperand(1);
23677 // Check for BEXTR.
23678 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23679 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23680 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23681 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23682 if (MaskNode && ShiftNode) {
23683 uint64_t Mask = MaskNode->getZExtValue();
23684 uint64_t Shift = ShiftNode->getZExtValue();
23685 if (isMask_64(Mask)) {
23686 uint64_t MaskSize = CountPopulation_64(Mask);
23687 if (Shift + MaskSize <= VT.getSizeInBits())
23688 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23689 DAG.getConstant(Shift | (MaskSize << 8), VT));
23697 // Want to form ANDNP nodes:
23698 // 1) In the hopes of then easily combining them with OR and AND nodes
23699 // to form PBLEND/PSIGN.
23700 // 2) To match ANDN packed intrinsics
23701 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23704 SDValue N0 = N->getOperand(0);
23705 SDValue N1 = N->getOperand(1);
23708 // Check LHS for vnot
23709 if (N0.getOpcode() == ISD::XOR &&
23710 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23711 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23712 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23714 // Check RHS for vnot
23715 if (N1.getOpcode() == ISD::XOR &&
23716 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23717 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23718 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23723 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23724 TargetLowering::DAGCombinerInfo &DCI,
23725 const X86Subtarget *Subtarget) {
23726 if (DCI.isBeforeLegalizeOps())
23729 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23733 SDValue N0 = N->getOperand(0);
23734 SDValue N1 = N->getOperand(1);
23735 EVT VT = N->getValueType(0);
23737 // look for psign/blend
23738 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23739 if (!Subtarget->hasSSSE3() ||
23740 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23743 // Canonicalize pandn to RHS
23744 if (N0.getOpcode() == X86ISD::ANDNP)
23746 // or (and (m, y), (pandn m, x))
23747 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23748 SDValue Mask = N1.getOperand(0);
23749 SDValue X = N1.getOperand(1);
23751 if (N0.getOperand(0) == Mask)
23752 Y = N0.getOperand(1);
23753 if (N0.getOperand(1) == Mask)
23754 Y = N0.getOperand(0);
23756 // Check to see if the mask appeared in both the AND and ANDNP and
23760 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23761 // Look through mask bitcast.
23762 if (Mask.getOpcode() == ISD::BITCAST)
23763 Mask = Mask.getOperand(0);
23764 if (X.getOpcode() == ISD::BITCAST)
23765 X = X.getOperand(0);
23766 if (Y.getOpcode() == ISD::BITCAST)
23767 Y = Y.getOperand(0);
23769 EVT MaskVT = Mask.getValueType();
23771 // Validate that the Mask operand is a vector sra node.
23772 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23773 // there is no psrai.b
23774 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23775 unsigned SraAmt = ~0;
23776 if (Mask.getOpcode() == ISD::SRA) {
23777 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23778 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23779 SraAmt = AmtConst->getZExtValue();
23780 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23781 SDValue SraC = Mask.getOperand(1);
23782 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23784 if ((SraAmt + 1) != EltBits)
23789 // Now we know we at least have a plendvb with the mask val. See if
23790 // we can form a psignb/w/d.
23791 // psign = x.type == y.type == mask.type && y = sub(0, x);
23792 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23793 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23794 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23795 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23796 "Unsupported VT for PSIGN");
23797 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23798 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23800 // PBLENDVB only available on SSE 4.1
23801 if (!Subtarget->hasSSE41())
23804 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23806 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23807 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23808 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23809 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23810 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23814 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23817 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23818 MachineFunction &MF = DAG.getMachineFunction();
23819 bool OptForSize = MF.getFunction()->getAttributes().
23820 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23822 // SHLD/SHRD instructions have lower register pressure, but on some
23823 // platforms they have higher latency than the equivalent
23824 // series of shifts/or that would otherwise be generated.
23825 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23826 // have higher latencies and we are not optimizing for size.
23827 if (!OptForSize && Subtarget->isSHLDSlow())
23830 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23832 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23834 if (!N0.hasOneUse() || !N1.hasOneUse())
23837 SDValue ShAmt0 = N0.getOperand(1);
23838 if (ShAmt0.getValueType() != MVT::i8)
23840 SDValue ShAmt1 = N1.getOperand(1);
23841 if (ShAmt1.getValueType() != MVT::i8)
23843 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23844 ShAmt0 = ShAmt0.getOperand(0);
23845 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23846 ShAmt1 = ShAmt1.getOperand(0);
23849 unsigned Opc = X86ISD::SHLD;
23850 SDValue Op0 = N0.getOperand(0);
23851 SDValue Op1 = N1.getOperand(0);
23852 if (ShAmt0.getOpcode() == ISD::SUB) {
23853 Opc = X86ISD::SHRD;
23854 std::swap(Op0, Op1);
23855 std::swap(ShAmt0, ShAmt1);
23858 unsigned Bits = VT.getSizeInBits();
23859 if (ShAmt1.getOpcode() == ISD::SUB) {
23860 SDValue Sum = ShAmt1.getOperand(0);
23861 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23862 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23863 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23864 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23865 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23866 return DAG.getNode(Opc, DL, VT,
23868 DAG.getNode(ISD::TRUNCATE, DL,
23871 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23872 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23874 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23875 return DAG.getNode(Opc, DL, VT,
23876 N0.getOperand(0), N1.getOperand(0),
23877 DAG.getNode(ISD::TRUNCATE, DL,
23884 // Generate NEG and CMOV for integer abs.
23885 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23886 EVT VT = N->getValueType(0);
23888 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23889 // 8-bit integer abs to NEG and CMOV.
23890 if (VT.isInteger() && VT.getSizeInBits() == 8)
23893 SDValue N0 = N->getOperand(0);
23894 SDValue N1 = N->getOperand(1);
23897 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23898 // and change it to SUB and CMOV.
23899 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23900 N0.getOpcode() == ISD::ADD &&
23901 N0.getOperand(1) == N1 &&
23902 N1.getOpcode() == ISD::SRA &&
23903 N1.getOperand(0) == N0.getOperand(0))
23904 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23905 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23906 // Generate SUB & CMOV.
23907 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23908 DAG.getConstant(0, VT), N0.getOperand(0));
23910 SDValue Ops[] = { N0.getOperand(0), Neg,
23911 DAG.getConstant(X86::COND_GE, MVT::i8),
23912 SDValue(Neg.getNode(), 1) };
23913 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23918 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23919 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23920 TargetLowering::DAGCombinerInfo &DCI,
23921 const X86Subtarget *Subtarget) {
23922 if (DCI.isBeforeLegalizeOps())
23925 if (Subtarget->hasCMov()) {
23926 SDValue RV = performIntegerAbsCombine(N, DAG);
23934 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23935 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23936 TargetLowering::DAGCombinerInfo &DCI,
23937 const X86Subtarget *Subtarget) {
23938 LoadSDNode *Ld = cast<LoadSDNode>(N);
23939 EVT RegVT = Ld->getValueType(0);
23940 EVT MemVT = Ld->getMemoryVT();
23942 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23944 // On Sandybridge unaligned 256bit loads are inefficient.
23945 ISD::LoadExtType Ext = Ld->getExtensionType();
23946 unsigned Alignment = Ld->getAlignment();
23947 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23948 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23949 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23950 unsigned NumElems = RegVT.getVectorNumElements();
23954 SDValue Ptr = Ld->getBasePtr();
23955 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23957 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23959 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23960 Ld->getPointerInfo(), Ld->isVolatile(),
23961 Ld->isNonTemporal(), Ld->isInvariant(),
23963 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23964 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23965 Ld->getPointerInfo(), Ld->isVolatile(),
23966 Ld->isNonTemporal(), Ld->isInvariant(),
23967 std::min(16U, Alignment));
23968 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23970 Load2.getValue(1));
23972 SDValue NewVec = DAG.getUNDEF(RegVT);
23973 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23974 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23975 return DCI.CombineTo(N, NewVec, TF, true);
23981 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23982 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23983 const X86Subtarget *Subtarget) {
23984 StoreSDNode *St = cast<StoreSDNode>(N);
23985 EVT VT = St->getValue().getValueType();
23986 EVT StVT = St->getMemoryVT();
23988 SDValue StoredVal = St->getOperand(1);
23989 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23991 // If we are saving a concatenation of two XMM registers, perform two stores.
23992 // On Sandy Bridge, 256-bit memory operations are executed by two
23993 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23994 // memory operation.
23995 unsigned Alignment = St->getAlignment();
23996 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23997 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23998 StVT == VT && !IsAligned) {
23999 unsigned NumElems = VT.getVectorNumElements();
24003 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24004 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24006 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24007 SDValue Ptr0 = St->getBasePtr();
24008 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24010 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24011 St->getPointerInfo(), St->isVolatile(),
24012 St->isNonTemporal(), Alignment);
24013 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24014 St->getPointerInfo(), St->isVolatile(),
24015 St->isNonTemporal(),
24016 std::min(16U, Alignment));
24017 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24020 // Optimize trunc store (of multiple scalars) to shuffle and store.
24021 // First, pack all of the elements in one place. Next, store to memory
24022 // in fewer chunks.
24023 if (St->isTruncatingStore() && VT.isVector()) {
24024 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24025 unsigned NumElems = VT.getVectorNumElements();
24026 assert(StVT != VT && "Cannot truncate to the same type");
24027 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24028 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24030 // From, To sizes and ElemCount must be pow of two
24031 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24032 // We are going to use the original vector elt for storing.
24033 // Accumulated smaller vector elements must be a multiple of the store size.
24034 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24036 unsigned SizeRatio = FromSz / ToSz;
24038 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24040 // Create a type on which we perform the shuffle
24041 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24042 StVT.getScalarType(), NumElems*SizeRatio);
24044 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24046 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24047 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24048 for (unsigned i = 0; i != NumElems; ++i)
24049 ShuffleVec[i] = i * SizeRatio;
24051 // Can't shuffle using an illegal type.
24052 if (!TLI.isTypeLegal(WideVecVT))
24055 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24056 DAG.getUNDEF(WideVecVT),
24058 // At this point all of the data is stored at the bottom of the
24059 // register. We now need to save it to mem.
24061 // Find the largest store unit
24062 MVT StoreType = MVT::i8;
24063 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24064 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24065 MVT Tp = (MVT::SimpleValueType)tp;
24066 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24070 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24071 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24072 (64 <= NumElems * ToSz))
24073 StoreType = MVT::f64;
24075 // Bitcast the original vector into a vector of store-size units
24076 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24077 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24078 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24079 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24080 SmallVector<SDValue, 8> Chains;
24081 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24082 TLI.getPointerTy());
24083 SDValue Ptr = St->getBasePtr();
24085 // Perform one or more big stores into memory.
24086 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24087 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24088 StoreType, ShuffWide,
24089 DAG.getIntPtrConstant(i));
24090 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24091 St->getPointerInfo(), St->isVolatile(),
24092 St->isNonTemporal(), St->getAlignment());
24093 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24094 Chains.push_back(Ch);
24097 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24100 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24101 // the FP state in cases where an emms may be missing.
24102 // A preferable solution to the general problem is to figure out the right
24103 // places to insert EMMS. This qualifies as a quick hack.
24105 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24106 if (VT.getSizeInBits() != 64)
24109 const Function *F = DAG.getMachineFunction().getFunction();
24110 bool NoImplicitFloatOps = F->getAttributes().
24111 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24112 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24113 && Subtarget->hasSSE2();
24114 if ((VT.isVector() ||
24115 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24116 isa<LoadSDNode>(St->getValue()) &&
24117 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24118 St->getChain().hasOneUse() && !St->isVolatile()) {
24119 SDNode* LdVal = St->getValue().getNode();
24120 LoadSDNode *Ld = nullptr;
24121 int TokenFactorIndex = -1;
24122 SmallVector<SDValue, 8> Ops;
24123 SDNode* ChainVal = St->getChain().getNode();
24124 // Must be a store of a load. We currently handle two cases: the load
24125 // is a direct child, and it's under an intervening TokenFactor. It is
24126 // possible to dig deeper under nested TokenFactors.
24127 if (ChainVal == LdVal)
24128 Ld = cast<LoadSDNode>(St->getChain());
24129 else if (St->getValue().hasOneUse() &&
24130 ChainVal->getOpcode() == ISD::TokenFactor) {
24131 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24132 if (ChainVal->getOperand(i).getNode() == LdVal) {
24133 TokenFactorIndex = i;
24134 Ld = cast<LoadSDNode>(St->getValue());
24136 Ops.push_back(ChainVal->getOperand(i));
24140 if (!Ld || !ISD::isNormalLoad(Ld))
24143 // If this is not the MMX case, i.e. we are just turning i64 load/store
24144 // into f64 load/store, avoid the transformation if there are multiple
24145 // uses of the loaded value.
24146 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24151 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24152 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24154 if (Subtarget->is64Bit() || F64IsLegal) {
24155 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24156 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24157 Ld->getPointerInfo(), Ld->isVolatile(),
24158 Ld->isNonTemporal(), Ld->isInvariant(),
24159 Ld->getAlignment());
24160 SDValue NewChain = NewLd.getValue(1);
24161 if (TokenFactorIndex != -1) {
24162 Ops.push_back(NewChain);
24163 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24165 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24166 St->getPointerInfo(),
24167 St->isVolatile(), St->isNonTemporal(),
24168 St->getAlignment());
24171 // Otherwise, lower to two pairs of 32-bit loads / stores.
24172 SDValue LoAddr = Ld->getBasePtr();
24173 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24174 DAG.getConstant(4, MVT::i32));
24176 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24177 Ld->getPointerInfo(),
24178 Ld->isVolatile(), Ld->isNonTemporal(),
24179 Ld->isInvariant(), Ld->getAlignment());
24180 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24181 Ld->getPointerInfo().getWithOffset(4),
24182 Ld->isVolatile(), Ld->isNonTemporal(),
24184 MinAlign(Ld->getAlignment(), 4));
24186 SDValue NewChain = LoLd.getValue(1);
24187 if (TokenFactorIndex != -1) {
24188 Ops.push_back(LoLd);
24189 Ops.push_back(HiLd);
24190 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24193 LoAddr = St->getBasePtr();
24194 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24195 DAG.getConstant(4, MVT::i32));
24197 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24198 St->getPointerInfo(),
24199 St->isVolatile(), St->isNonTemporal(),
24200 St->getAlignment());
24201 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24202 St->getPointerInfo().getWithOffset(4),
24204 St->isNonTemporal(),
24205 MinAlign(St->getAlignment(), 4));
24206 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24211 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24212 /// and return the operands for the horizontal operation in LHS and RHS. A
24213 /// horizontal operation performs the binary operation on successive elements
24214 /// of its first operand, then on successive elements of its second operand,
24215 /// returning the resulting values in a vector. For example, if
24216 /// A = < float a0, float a1, float a2, float a3 >
24218 /// B = < float b0, float b1, float b2, float b3 >
24219 /// then the result of doing a horizontal operation on A and B is
24220 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24221 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24222 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24223 /// set to A, RHS to B, and the routine returns 'true'.
24224 /// Note that the binary operation should have the property that if one of the
24225 /// operands is UNDEF then the result is UNDEF.
24226 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24227 // Look for the following pattern: if
24228 // A = < float a0, float a1, float a2, float a3 >
24229 // B = < float b0, float b1, float b2, float b3 >
24231 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24232 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24233 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24234 // which is A horizontal-op B.
24236 // At least one of the operands should be a vector shuffle.
24237 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24238 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24241 MVT VT = LHS.getSimpleValueType();
24243 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24244 "Unsupported vector type for horizontal add/sub");
24246 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24247 // operate independently on 128-bit lanes.
24248 unsigned NumElts = VT.getVectorNumElements();
24249 unsigned NumLanes = VT.getSizeInBits()/128;
24250 unsigned NumLaneElts = NumElts / NumLanes;
24251 assert((NumLaneElts % 2 == 0) &&
24252 "Vector type should have an even number of elements in each lane");
24253 unsigned HalfLaneElts = NumLaneElts/2;
24255 // View LHS in the form
24256 // LHS = VECTOR_SHUFFLE A, B, LMask
24257 // If LHS is not a shuffle then pretend it is the shuffle
24258 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24259 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24262 SmallVector<int, 16> LMask(NumElts);
24263 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24264 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24265 A = LHS.getOperand(0);
24266 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24267 B = LHS.getOperand(1);
24268 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24269 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24271 if (LHS.getOpcode() != ISD::UNDEF)
24273 for (unsigned i = 0; i != NumElts; ++i)
24277 // Likewise, view RHS in the form
24278 // RHS = VECTOR_SHUFFLE C, D, RMask
24280 SmallVector<int, 16> RMask(NumElts);
24281 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24282 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24283 C = RHS.getOperand(0);
24284 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24285 D = RHS.getOperand(1);
24286 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24287 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24289 if (RHS.getOpcode() != ISD::UNDEF)
24291 for (unsigned i = 0; i != NumElts; ++i)
24295 // Check that the shuffles are both shuffling the same vectors.
24296 if (!(A == C && B == D) && !(A == D && B == C))
24299 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24300 if (!A.getNode() && !B.getNode())
24303 // If A and B occur in reverse order in RHS, then "swap" them (which means
24304 // rewriting the mask).
24306 CommuteVectorShuffleMask(RMask, NumElts);
24308 // At this point LHS and RHS are equivalent to
24309 // LHS = VECTOR_SHUFFLE A, B, LMask
24310 // RHS = VECTOR_SHUFFLE A, B, RMask
24311 // Check that the masks correspond to performing a horizontal operation.
24312 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24313 for (unsigned i = 0; i != NumLaneElts; ++i) {
24314 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24316 // Ignore any UNDEF components.
24317 if (LIdx < 0 || RIdx < 0 ||
24318 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24319 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24322 // Check that successive elements are being operated on. If not, this is
24323 // not a horizontal operation.
24324 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24325 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24326 if (!(LIdx == Index && RIdx == Index + 1) &&
24327 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24332 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24333 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24337 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24338 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24339 const X86Subtarget *Subtarget) {
24340 EVT VT = N->getValueType(0);
24341 SDValue LHS = N->getOperand(0);
24342 SDValue RHS = N->getOperand(1);
24344 // Try to synthesize horizontal adds from adds of shuffles.
24345 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24346 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24347 isHorizontalBinOp(LHS, RHS, true))
24348 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24352 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24353 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24354 const X86Subtarget *Subtarget) {
24355 EVT VT = N->getValueType(0);
24356 SDValue LHS = N->getOperand(0);
24357 SDValue RHS = N->getOperand(1);
24359 // Try to synthesize horizontal subs from subs of shuffles.
24360 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24361 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24362 isHorizontalBinOp(LHS, RHS, false))
24363 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24367 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24368 /// X86ISD::FXOR nodes.
24369 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24370 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24371 // F[X]OR(0.0, x) -> x
24372 // F[X]OR(x, 0.0) -> x
24373 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24374 if (C->getValueAPF().isPosZero())
24375 return N->getOperand(1);
24376 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24377 if (C->getValueAPF().isPosZero())
24378 return N->getOperand(0);
24382 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24383 /// X86ISD::FMAX nodes.
24384 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24385 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24387 // Only perform optimizations if UnsafeMath is used.
24388 if (!DAG.getTarget().Options.UnsafeFPMath)
24391 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24392 // into FMINC and FMAXC, which are Commutative operations.
24393 unsigned NewOp = 0;
24394 switch (N->getOpcode()) {
24395 default: llvm_unreachable("unknown opcode");
24396 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24397 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24400 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24401 N->getOperand(0), N->getOperand(1));
24404 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24405 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24406 // FAND(0.0, x) -> 0.0
24407 // FAND(x, 0.0) -> 0.0
24408 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24409 if (C->getValueAPF().isPosZero())
24410 return N->getOperand(0);
24411 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24412 if (C->getValueAPF().isPosZero())
24413 return N->getOperand(1);
24417 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24418 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24419 // FANDN(x, 0.0) -> 0.0
24420 // FANDN(0.0, x) -> x
24421 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24422 if (C->getValueAPF().isPosZero())
24423 return N->getOperand(1);
24424 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24425 if (C->getValueAPF().isPosZero())
24426 return N->getOperand(1);
24430 static SDValue PerformBTCombine(SDNode *N,
24432 TargetLowering::DAGCombinerInfo &DCI) {
24433 // BT ignores high bits in the bit index operand.
24434 SDValue Op1 = N->getOperand(1);
24435 if (Op1.hasOneUse()) {
24436 unsigned BitWidth = Op1.getValueSizeInBits();
24437 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24438 APInt KnownZero, KnownOne;
24439 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24440 !DCI.isBeforeLegalizeOps());
24441 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24442 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24443 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24444 DCI.CommitTargetLoweringOpt(TLO);
24449 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24450 SDValue Op = N->getOperand(0);
24451 if (Op.getOpcode() == ISD::BITCAST)
24452 Op = Op.getOperand(0);
24453 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24454 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24455 VT.getVectorElementType().getSizeInBits() ==
24456 OpVT.getVectorElementType().getSizeInBits()) {
24457 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24462 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24463 const X86Subtarget *Subtarget) {
24464 EVT VT = N->getValueType(0);
24465 if (!VT.isVector())
24468 SDValue N0 = N->getOperand(0);
24469 SDValue N1 = N->getOperand(1);
24470 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24473 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24474 // both SSE and AVX2 since there is no sign-extended shift right
24475 // operation on a vector with 64-bit elements.
24476 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24477 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24478 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24479 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24480 SDValue N00 = N0.getOperand(0);
24482 // EXTLOAD has a better solution on AVX2,
24483 // it may be replaced with X86ISD::VSEXT node.
24484 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24485 if (!ISD::isNormalLoad(N00.getNode()))
24488 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24489 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24491 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24497 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24498 TargetLowering::DAGCombinerInfo &DCI,
24499 const X86Subtarget *Subtarget) {
24500 SDValue N0 = N->getOperand(0);
24501 EVT VT = N->getValueType(0);
24503 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24504 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24505 // This exposes the sext to the sdivrem lowering, so that it directly extends
24506 // from AH (which we otherwise need to do contortions to access).
24507 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24508 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24510 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24511 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24512 N0.getOperand(0), N0.getOperand(1));
24513 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24514 return R.getValue(1);
24517 if (!DCI.isBeforeLegalizeOps())
24520 if (!Subtarget->hasFp256())
24523 if (VT.isVector() && VT.getSizeInBits() == 256) {
24524 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24532 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24533 const X86Subtarget* Subtarget) {
24535 EVT VT = N->getValueType(0);
24537 // Let legalize expand this if it isn't a legal type yet.
24538 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24541 EVT ScalarVT = VT.getScalarType();
24542 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24543 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24546 SDValue A = N->getOperand(0);
24547 SDValue B = N->getOperand(1);
24548 SDValue C = N->getOperand(2);
24550 bool NegA = (A.getOpcode() == ISD::FNEG);
24551 bool NegB = (B.getOpcode() == ISD::FNEG);
24552 bool NegC = (C.getOpcode() == ISD::FNEG);
24554 // Negative multiplication when NegA xor NegB
24555 bool NegMul = (NegA != NegB);
24557 A = A.getOperand(0);
24559 B = B.getOperand(0);
24561 C = C.getOperand(0);
24565 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24567 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24569 return DAG.getNode(Opcode, dl, VT, A, B, C);
24572 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24573 TargetLowering::DAGCombinerInfo &DCI,
24574 const X86Subtarget *Subtarget) {
24575 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24576 // (and (i32 x86isd::setcc_carry), 1)
24577 // This eliminates the zext. This transformation is necessary because
24578 // ISD::SETCC is always legalized to i8.
24580 SDValue N0 = N->getOperand(0);
24581 EVT VT = N->getValueType(0);
24583 if (N0.getOpcode() == ISD::AND &&
24585 N0.getOperand(0).hasOneUse()) {
24586 SDValue N00 = N0.getOperand(0);
24587 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24588 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24589 if (!C || C->getZExtValue() != 1)
24591 return DAG.getNode(ISD::AND, dl, VT,
24592 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24593 N00.getOperand(0), N00.getOperand(1)),
24594 DAG.getConstant(1, VT));
24598 if (N0.getOpcode() == ISD::TRUNCATE &&
24600 N0.getOperand(0).hasOneUse()) {
24601 SDValue N00 = N0.getOperand(0);
24602 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24603 return DAG.getNode(ISD::AND, dl, VT,
24604 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24605 N00.getOperand(0), N00.getOperand(1)),
24606 DAG.getConstant(1, VT));
24609 if (VT.is256BitVector()) {
24610 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24615 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24616 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24617 // This exposes the zext to the udivrem lowering, so that it directly extends
24618 // from AH (which we otherwise need to do contortions to access).
24619 if (N0.getOpcode() == ISD::UDIVREM &&
24620 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24621 (VT == MVT::i32 || VT == MVT::i64)) {
24622 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24623 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24624 N0.getOperand(0), N0.getOperand(1));
24625 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24626 return R.getValue(1);
24632 // Optimize x == -y --> x+y == 0
24633 // x != -y --> x+y != 0
24634 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24635 const X86Subtarget* Subtarget) {
24636 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24637 SDValue LHS = N->getOperand(0);
24638 SDValue RHS = N->getOperand(1);
24639 EVT VT = N->getValueType(0);
24642 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24643 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24644 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24645 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24646 LHS.getValueType(), RHS, LHS.getOperand(1));
24647 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24648 addV, DAG.getConstant(0, addV.getValueType()), CC);
24650 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24651 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24652 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24653 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24654 RHS.getValueType(), LHS, RHS.getOperand(1));
24655 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24656 addV, DAG.getConstant(0, addV.getValueType()), CC);
24659 if (VT.getScalarType() == MVT::i1) {
24660 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24661 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24662 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24663 if (!IsSEXT0 && !IsVZero0)
24665 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24666 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24667 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24669 if (!IsSEXT1 && !IsVZero1)
24672 if (IsSEXT0 && IsVZero1) {
24673 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24674 if (CC == ISD::SETEQ)
24675 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24676 return LHS.getOperand(0);
24678 if (IsSEXT1 && IsVZero0) {
24679 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24680 if (CC == ISD::SETEQ)
24681 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24682 return RHS.getOperand(0);
24689 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24690 const X86Subtarget *Subtarget) {
24692 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24693 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24694 "X86insertps is only defined for v4x32");
24696 SDValue Ld = N->getOperand(1);
24697 if (MayFoldLoad(Ld)) {
24698 // Extract the countS bits from the immediate so we can get the proper
24699 // address when narrowing the vector load to a specific element.
24700 // When the second source op is a memory address, interps doesn't use
24701 // countS and just gets an f32 from that address.
24702 unsigned DestIndex =
24703 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24704 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24708 // Create this as a scalar to vector to match the instruction pattern.
24709 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24710 // countS bits are ignored when loading from memory on insertps, which
24711 // means we don't need to explicitly set them to 0.
24712 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24713 LoadScalarToVector, N->getOperand(2));
24716 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24717 // as "sbb reg,reg", since it can be extended without zext and produces
24718 // an all-ones bit which is more useful than 0/1 in some cases.
24719 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24722 return DAG.getNode(ISD::AND, DL, VT,
24723 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24724 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24725 DAG.getConstant(1, VT));
24726 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24727 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24728 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24729 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24732 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24733 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24734 TargetLowering::DAGCombinerInfo &DCI,
24735 const X86Subtarget *Subtarget) {
24737 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24738 SDValue EFLAGS = N->getOperand(1);
24740 if (CC == X86::COND_A) {
24741 // Try to convert COND_A into COND_B in an attempt to facilitate
24742 // materializing "setb reg".
24744 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24745 // cannot take an immediate as its first operand.
24747 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24748 EFLAGS.getValueType().isInteger() &&
24749 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24750 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24751 EFLAGS.getNode()->getVTList(),
24752 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24753 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24754 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24758 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24759 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24761 if (CC == X86::COND_B)
24762 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24766 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24767 if (Flags.getNode()) {
24768 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24769 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24775 // Optimize branch condition evaluation.
24777 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24778 TargetLowering::DAGCombinerInfo &DCI,
24779 const X86Subtarget *Subtarget) {
24781 SDValue Chain = N->getOperand(0);
24782 SDValue Dest = N->getOperand(1);
24783 SDValue EFLAGS = N->getOperand(3);
24784 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24788 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24789 if (Flags.getNode()) {
24790 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24791 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24798 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24799 SelectionDAG &DAG) {
24800 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24801 // optimize away operation when it's from a constant.
24803 // The general transformation is:
24804 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24805 // AND(VECTOR_CMP(x,y), constant2)
24806 // constant2 = UNARYOP(constant)
24808 // Early exit if this isn't a vector operation, the operand of the
24809 // unary operation isn't a bitwise AND, or if the sizes of the operations
24810 // aren't the same.
24811 EVT VT = N->getValueType(0);
24812 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24813 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24814 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24817 // Now check that the other operand of the AND is a constant. We could
24818 // make the transformation for non-constant splats as well, but it's unclear
24819 // that would be a benefit as it would not eliminate any operations, just
24820 // perform one more step in scalar code before moving to the vector unit.
24821 if (BuildVectorSDNode *BV =
24822 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24823 // Bail out if the vector isn't a constant.
24824 if (!BV->isConstant())
24827 // Everything checks out. Build up the new and improved node.
24829 EVT IntVT = BV->getValueType(0);
24830 // Create a new constant of the appropriate type for the transformed
24832 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24833 // The AND node needs bitcasts to/from an integer vector type around it.
24834 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24835 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24836 N->getOperand(0)->getOperand(0), MaskConst);
24837 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24844 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24845 const X86TargetLowering *XTLI) {
24846 // First try to optimize away the conversion entirely when it's
24847 // conditionally from a constant. Vectors only.
24848 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24849 if (Res != SDValue())
24852 // Now move on to more general possibilities.
24853 SDValue Op0 = N->getOperand(0);
24854 EVT InVT = Op0->getValueType(0);
24856 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24857 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24859 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24860 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24861 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24864 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24865 // a 32-bit target where SSE doesn't support i64->FP operations.
24866 if (Op0.getOpcode() == ISD::LOAD) {
24867 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24868 EVT VT = Ld->getValueType(0);
24869 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24870 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24871 !XTLI->getSubtarget()->is64Bit() &&
24873 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24874 Ld->getChain(), Op0, DAG);
24875 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24882 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24883 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24884 X86TargetLowering::DAGCombinerInfo &DCI) {
24885 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24886 // the result is either zero or one (depending on the input carry bit).
24887 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24888 if (X86::isZeroNode(N->getOperand(0)) &&
24889 X86::isZeroNode(N->getOperand(1)) &&
24890 // We don't have a good way to replace an EFLAGS use, so only do this when
24892 SDValue(N, 1).use_empty()) {
24894 EVT VT = N->getValueType(0);
24895 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24896 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24897 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24898 DAG.getConstant(X86::COND_B,MVT::i8),
24900 DAG.getConstant(1, VT));
24901 return DCI.CombineTo(N, Res1, CarryOut);
24907 // fold (add Y, (sete X, 0)) -> adc 0, Y
24908 // (add Y, (setne X, 0)) -> sbb -1, Y
24909 // (sub (sete X, 0), Y) -> sbb 0, Y
24910 // (sub (setne X, 0), Y) -> adc -1, Y
24911 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24914 // Look through ZExts.
24915 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24916 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24919 SDValue SetCC = Ext.getOperand(0);
24920 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24923 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24924 if (CC != X86::COND_E && CC != X86::COND_NE)
24927 SDValue Cmp = SetCC.getOperand(1);
24928 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24929 !X86::isZeroNode(Cmp.getOperand(1)) ||
24930 !Cmp.getOperand(0).getValueType().isInteger())
24933 SDValue CmpOp0 = Cmp.getOperand(0);
24934 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24935 DAG.getConstant(1, CmpOp0.getValueType()));
24937 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24938 if (CC == X86::COND_NE)
24939 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24940 DL, OtherVal.getValueType(), OtherVal,
24941 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24942 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24943 DL, OtherVal.getValueType(), OtherVal,
24944 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24947 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24948 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24949 const X86Subtarget *Subtarget) {
24950 EVT VT = N->getValueType(0);
24951 SDValue Op0 = N->getOperand(0);
24952 SDValue Op1 = N->getOperand(1);
24954 // Try to synthesize horizontal adds from adds of shuffles.
24955 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24956 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24957 isHorizontalBinOp(Op0, Op1, true))
24958 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24960 return OptimizeConditionalInDecrement(N, DAG);
24963 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24964 const X86Subtarget *Subtarget) {
24965 SDValue Op0 = N->getOperand(0);
24966 SDValue Op1 = N->getOperand(1);
24968 // X86 can't encode an immediate LHS of a sub. See if we can push the
24969 // negation into a preceding instruction.
24970 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24971 // If the RHS of the sub is a XOR with one use and a constant, invert the
24972 // immediate. Then add one to the LHS of the sub so we can turn
24973 // X-Y -> X+~Y+1, saving one register.
24974 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24975 isa<ConstantSDNode>(Op1.getOperand(1))) {
24976 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24977 EVT VT = Op0.getValueType();
24978 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24980 DAG.getConstant(~XorC, VT));
24981 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24982 DAG.getConstant(C->getAPIntValue()+1, VT));
24986 // Try to synthesize horizontal adds from adds of shuffles.
24987 EVT VT = N->getValueType(0);
24988 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24989 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24990 isHorizontalBinOp(Op0, Op1, true))
24991 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24993 return OptimizeConditionalInDecrement(N, DAG);
24996 /// performVZEXTCombine - Performs build vector combines
24997 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24998 TargetLowering::DAGCombinerInfo &DCI,
24999 const X86Subtarget *Subtarget) {
25001 MVT VT = N->getSimpleValueType(0);
25002 SDValue Op = N->getOperand(0);
25003 MVT OpVT = Op.getSimpleValueType();
25004 MVT OpEltVT = OpVT.getVectorElementType();
25005 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25007 // (vzext (bitcast (vzext (x)) -> (vzext x)
25009 while (V.getOpcode() == ISD::BITCAST)
25010 V = V.getOperand(0);
25012 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25013 MVT InnerVT = V.getSimpleValueType();
25014 MVT InnerEltVT = InnerVT.getVectorElementType();
25016 // If the element sizes match exactly, we can just do one larger vzext. This
25017 // is always an exact type match as vzext operates on integer types.
25018 if (OpEltVT == InnerEltVT) {
25019 assert(OpVT == InnerVT && "Types must match for vzext!");
25020 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25023 // The only other way we can combine them is if only a single element of the
25024 // inner vzext is used in the input to the outer vzext.
25025 if (InnerEltVT.getSizeInBits() < InputBits)
25028 // In this case, the inner vzext is completely dead because we're going to
25029 // only look at bits inside of the low element. Just do the outer vzext on
25030 // a bitcast of the input to the inner.
25031 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25032 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25035 // Check if we can bypass extracting and re-inserting an element of an input
25036 // vector. Essentialy:
25037 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25038 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25039 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25040 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25041 SDValue ExtractedV = V.getOperand(0);
25042 SDValue OrigV = ExtractedV.getOperand(0);
25043 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25044 if (ExtractIdx->getZExtValue() == 0) {
25045 MVT OrigVT = OrigV.getSimpleValueType();
25046 // Extract a subvector if necessary...
25047 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25048 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25049 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25050 OrigVT.getVectorNumElements() / Ratio);
25051 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25052 DAG.getIntPtrConstant(0));
25054 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25055 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25062 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25063 DAGCombinerInfo &DCI) const {
25064 SelectionDAG &DAG = DCI.DAG;
25065 switch (N->getOpcode()) {
25067 case ISD::EXTRACT_VECTOR_ELT:
25068 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25071 case X86ISD::SHRUNKBLEND:
25072 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25073 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25074 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25075 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25076 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25077 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25080 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25081 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25082 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25083 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25084 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25085 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25086 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25087 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25088 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25090 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25092 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25093 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25094 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25095 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25096 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25097 case ISD::ANY_EXTEND:
25098 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25099 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25100 case ISD::SIGN_EXTEND_INREG:
25101 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25102 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25103 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25104 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25105 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25106 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25107 case X86ISD::SHUFP: // Handle all target specific shuffles
25108 case X86ISD::PALIGNR:
25109 case X86ISD::UNPCKH:
25110 case X86ISD::UNPCKL:
25111 case X86ISD::MOVHLPS:
25112 case X86ISD::MOVLHPS:
25113 case X86ISD::PSHUFB:
25114 case X86ISD::PSHUFD:
25115 case X86ISD::PSHUFHW:
25116 case X86ISD::PSHUFLW:
25117 case X86ISD::MOVSS:
25118 case X86ISD::MOVSD:
25119 case X86ISD::VPERMILPI:
25120 case X86ISD::VPERM2X128:
25121 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25122 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25123 case ISD::INTRINSIC_WO_CHAIN:
25124 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25125 case X86ISD::INSERTPS:
25126 return PerformINSERTPSCombine(N, DAG, Subtarget);
25127 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25133 /// isTypeDesirableForOp - Return true if the target has native support for
25134 /// the specified value type and it is 'desirable' to use the type for the
25135 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25136 /// instruction encodings are longer and some i16 instructions are slow.
25137 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25138 if (!isTypeLegal(VT))
25140 if (VT != MVT::i16)
25147 case ISD::SIGN_EXTEND:
25148 case ISD::ZERO_EXTEND:
25149 case ISD::ANY_EXTEND:
25162 /// IsDesirableToPromoteOp - This method query the target whether it is
25163 /// beneficial for dag combiner to promote the specified node. If true, it
25164 /// should return the desired promotion type by reference.
25165 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25166 EVT VT = Op.getValueType();
25167 if (VT != MVT::i16)
25170 bool Promote = false;
25171 bool Commute = false;
25172 switch (Op.getOpcode()) {
25175 LoadSDNode *LD = cast<LoadSDNode>(Op);
25176 // If the non-extending load has a single use and it's not live out, then it
25177 // might be folded.
25178 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25179 Op.hasOneUse()*/) {
25180 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25181 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25182 // The only case where we'd want to promote LOAD (rather then it being
25183 // promoted as an operand is when it's only use is liveout.
25184 if (UI->getOpcode() != ISD::CopyToReg)
25191 case ISD::SIGN_EXTEND:
25192 case ISD::ZERO_EXTEND:
25193 case ISD::ANY_EXTEND:
25198 SDValue N0 = Op.getOperand(0);
25199 // Look out for (store (shl (load), x)).
25200 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25213 SDValue N0 = Op.getOperand(0);
25214 SDValue N1 = Op.getOperand(1);
25215 if (!Commute && MayFoldLoad(N1))
25217 // Avoid disabling potential load folding opportunities.
25218 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25220 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25230 //===----------------------------------------------------------------------===//
25231 // X86 Inline Assembly Support
25232 //===----------------------------------------------------------------------===//
25235 // Helper to match a string separated by whitespace.
25236 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25237 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25239 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25240 StringRef piece(*args[i]);
25241 if (!s.startswith(piece)) // Check if the piece matches.
25244 s = s.substr(piece.size());
25245 StringRef::size_type pos = s.find_first_not_of(" \t");
25246 if (pos == 0) // We matched a prefix.
25254 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25257 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25259 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25260 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25261 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25262 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25264 if (AsmPieces.size() == 3)
25266 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25273 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25274 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25276 std::string AsmStr = IA->getAsmString();
25278 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25279 if (!Ty || Ty->getBitWidth() % 16 != 0)
25282 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25283 SmallVector<StringRef, 4> AsmPieces;
25284 SplitString(AsmStr, AsmPieces, ";\n");
25286 switch (AsmPieces.size()) {
25287 default: return false;
25289 // FIXME: this should verify that we are targeting a 486 or better. If not,
25290 // we will turn this bswap into something that will be lowered to logical
25291 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25292 // lower so don't worry about this.
25294 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25295 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25296 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25297 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25298 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25299 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25300 // No need to check constraints, nothing other than the equivalent of
25301 // "=r,0" would be valid here.
25302 return IntrinsicLowering::LowerToByteSwap(CI);
25305 // rorw $$8, ${0:w} --> llvm.bswap.i16
25306 if (CI->getType()->isIntegerTy(16) &&
25307 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25308 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25309 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25311 const std::string &ConstraintsStr = IA->getConstraintString();
25312 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25313 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25314 if (clobbersFlagRegisters(AsmPieces))
25315 return IntrinsicLowering::LowerToByteSwap(CI);
25319 if (CI->getType()->isIntegerTy(32) &&
25320 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25321 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25322 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25323 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25325 const std::string &ConstraintsStr = IA->getConstraintString();
25326 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25327 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25328 if (clobbersFlagRegisters(AsmPieces))
25329 return IntrinsicLowering::LowerToByteSwap(CI);
25332 if (CI->getType()->isIntegerTy(64)) {
25333 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25334 if (Constraints.size() >= 2 &&
25335 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25336 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25337 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25338 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25339 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25340 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25341 return IntrinsicLowering::LowerToByteSwap(CI);
25349 /// getConstraintType - Given a constraint letter, return the type of
25350 /// constraint it is for this target.
25351 X86TargetLowering::ConstraintType
25352 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25353 if (Constraint.size() == 1) {
25354 switch (Constraint[0]) {
25365 return C_RegisterClass;
25389 return TargetLowering::getConstraintType(Constraint);
25392 /// Examine constraint type and operand type and determine a weight value.
25393 /// This object must already have been set up with the operand type
25394 /// and the current alternative constraint selected.
25395 TargetLowering::ConstraintWeight
25396 X86TargetLowering::getSingleConstraintMatchWeight(
25397 AsmOperandInfo &info, const char *constraint) const {
25398 ConstraintWeight weight = CW_Invalid;
25399 Value *CallOperandVal = info.CallOperandVal;
25400 // If we don't have a value, we can't do a match,
25401 // but allow it at the lowest weight.
25402 if (!CallOperandVal)
25404 Type *type = CallOperandVal->getType();
25405 // Look at the constraint type.
25406 switch (*constraint) {
25408 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25419 if (CallOperandVal->getType()->isIntegerTy())
25420 weight = CW_SpecificReg;
25425 if (type->isFloatingPointTy())
25426 weight = CW_SpecificReg;
25429 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25430 weight = CW_SpecificReg;
25434 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25435 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25436 weight = CW_Register;
25439 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25440 if (C->getZExtValue() <= 31)
25441 weight = CW_Constant;
25445 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25446 if (C->getZExtValue() <= 63)
25447 weight = CW_Constant;
25451 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25452 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25453 weight = CW_Constant;
25457 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25458 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25459 weight = CW_Constant;
25463 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25464 if (C->getZExtValue() <= 3)
25465 weight = CW_Constant;
25469 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25470 if (C->getZExtValue() <= 0xff)
25471 weight = CW_Constant;
25476 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25477 weight = CW_Constant;
25481 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25482 if ((C->getSExtValue() >= -0x80000000LL) &&
25483 (C->getSExtValue() <= 0x7fffffffLL))
25484 weight = CW_Constant;
25488 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25489 if (C->getZExtValue() <= 0xffffffff)
25490 weight = CW_Constant;
25497 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25498 /// with another that has more specific requirements based on the type of the
25499 /// corresponding operand.
25500 const char *X86TargetLowering::
25501 LowerXConstraint(EVT ConstraintVT) const {
25502 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25503 // 'f' like normal targets.
25504 if (ConstraintVT.isFloatingPoint()) {
25505 if (Subtarget->hasSSE2())
25507 if (Subtarget->hasSSE1())
25511 return TargetLowering::LowerXConstraint(ConstraintVT);
25514 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25515 /// vector. If it is invalid, don't add anything to Ops.
25516 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25517 std::string &Constraint,
25518 std::vector<SDValue>&Ops,
25519 SelectionDAG &DAG) const {
25522 // Only support length 1 constraints for now.
25523 if (Constraint.length() > 1) return;
25525 char ConstraintLetter = Constraint[0];
25526 switch (ConstraintLetter) {
25529 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25530 if (C->getZExtValue() <= 31) {
25531 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25537 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25538 if (C->getZExtValue() <= 63) {
25539 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25546 if (isInt<8>(C->getSExtValue())) {
25547 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25554 if (C->getZExtValue() <= 255) {
25555 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25561 // 32-bit signed value
25562 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25563 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25564 C->getSExtValue())) {
25565 // Widen to 64 bits here to get it sign extended.
25566 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25569 // FIXME gcc accepts some relocatable values here too, but only in certain
25570 // memory models; it's complicated.
25575 // 32-bit unsigned value
25576 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25577 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25578 C->getZExtValue())) {
25579 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25583 // FIXME gcc accepts some relocatable values here too, but only in certain
25584 // memory models; it's complicated.
25588 // Literal immediates are always ok.
25589 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25590 // Widen to 64 bits here to get it sign extended.
25591 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25595 // In any sort of PIC mode addresses need to be computed at runtime by
25596 // adding in a register or some sort of table lookup. These can't
25597 // be used as immediates.
25598 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25601 // If we are in non-pic codegen mode, we allow the address of a global (with
25602 // an optional displacement) to be used with 'i'.
25603 GlobalAddressSDNode *GA = nullptr;
25604 int64_t Offset = 0;
25606 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25608 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25609 Offset += GA->getOffset();
25611 } else if (Op.getOpcode() == ISD::ADD) {
25612 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25613 Offset += C->getZExtValue();
25614 Op = Op.getOperand(0);
25617 } else if (Op.getOpcode() == ISD::SUB) {
25618 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25619 Offset += -C->getZExtValue();
25620 Op = Op.getOperand(0);
25625 // Otherwise, this isn't something we can handle, reject it.
25629 const GlobalValue *GV = GA->getGlobal();
25630 // If we require an extra load to get this address, as in PIC mode, we
25631 // can't accept it.
25632 if (isGlobalStubReference(
25633 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25636 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25637 GA->getValueType(0), Offset);
25642 if (Result.getNode()) {
25643 Ops.push_back(Result);
25646 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25649 std::pair<unsigned, const TargetRegisterClass*>
25650 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25652 // First, see if this is a constraint that directly corresponds to an LLVM
25654 if (Constraint.size() == 1) {
25655 // GCC Constraint Letters
25656 switch (Constraint[0]) {
25658 // TODO: Slight differences here in allocation order and leaving
25659 // RIP in the class. Do they matter any more here than they do
25660 // in the normal allocation?
25661 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25662 if (Subtarget->is64Bit()) {
25663 if (VT == MVT::i32 || VT == MVT::f32)
25664 return std::make_pair(0U, &X86::GR32RegClass);
25665 if (VT == MVT::i16)
25666 return std::make_pair(0U, &X86::GR16RegClass);
25667 if (VT == MVT::i8 || VT == MVT::i1)
25668 return std::make_pair(0U, &X86::GR8RegClass);
25669 if (VT == MVT::i64 || VT == MVT::f64)
25670 return std::make_pair(0U, &X86::GR64RegClass);
25673 // 32-bit fallthrough
25674 case 'Q': // Q_REGS
25675 if (VT == MVT::i32 || VT == MVT::f32)
25676 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25677 if (VT == MVT::i16)
25678 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25679 if (VT == MVT::i8 || VT == MVT::i1)
25680 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25681 if (VT == MVT::i64)
25682 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25684 case 'r': // GENERAL_REGS
25685 case 'l': // INDEX_REGS
25686 if (VT == MVT::i8 || VT == MVT::i1)
25687 return std::make_pair(0U, &X86::GR8RegClass);
25688 if (VT == MVT::i16)
25689 return std::make_pair(0U, &X86::GR16RegClass);
25690 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25691 return std::make_pair(0U, &X86::GR32RegClass);
25692 return std::make_pair(0U, &X86::GR64RegClass);
25693 case 'R': // LEGACY_REGS
25694 if (VT == MVT::i8 || VT == MVT::i1)
25695 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25696 if (VT == MVT::i16)
25697 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25698 if (VT == MVT::i32 || !Subtarget->is64Bit())
25699 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25700 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25701 case 'f': // FP Stack registers.
25702 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25703 // value to the correct fpstack register class.
25704 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25705 return std::make_pair(0U, &X86::RFP32RegClass);
25706 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25707 return std::make_pair(0U, &X86::RFP64RegClass);
25708 return std::make_pair(0U, &X86::RFP80RegClass);
25709 case 'y': // MMX_REGS if MMX allowed.
25710 if (!Subtarget->hasMMX()) break;
25711 return std::make_pair(0U, &X86::VR64RegClass);
25712 case 'Y': // SSE_REGS if SSE2 allowed
25713 if (!Subtarget->hasSSE2()) break;
25715 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25716 if (!Subtarget->hasSSE1()) break;
25718 switch (VT.SimpleTy) {
25720 // Scalar SSE types.
25723 return std::make_pair(0U, &X86::FR32RegClass);
25726 return std::make_pair(0U, &X86::FR64RegClass);
25734 return std::make_pair(0U, &X86::VR128RegClass);
25742 return std::make_pair(0U, &X86::VR256RegClass);
25747 return std::make_pair(0U, &X86::VR512RegClass);
25753 // Use the default implementation in TargetLowering to convert the register
25754 // constraint into a member of a register class.
25755 std::pair<unsigned, const TargetRegisterClass*> Res;
25756 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25758 // Not found as a standard register?
25760 // Map st(0) -> st(7) -> ST0
25761 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25762 tolower(Constraint[1]) == 's' &&
25763 tolower(Constraint[2]) == 't' &&
25764 Constraint[3] == '(' &&
25765 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25766 Constraint[5] == ')' &&
25767 Constraint[6] == '}') {
25769 Res.first = X86::FP0+Constraint[4]-'0';
25770 Res.second = &X86::RFP80RegClass;
25774 // GCC allows "st(0)" to be called just plain "st".
25775 if (StringRef("{st}").equals_lower(Constraint)) {
25776 Res.first = X86::FP0;
25777 Res.second = &X86::RFP80RegClass;
25782 if (StringRef("{flags}").equals_lower(Constraint)) {
25783 Res.first = X86::EFLAGS;
25784 Res.second = &X86::CCRRegClass;
25788 // 'A' means EAX + EDX.
25789 if (Constraint == "A") {
25790 Res.first = X86::EAX;
25791 Res.second = &X86::GR32_ADRegClass;
25797 // Otherwise, check to see if this is a register class of the wrong value
25798 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25799 // turn into {ax},{dx}.
25800 if (Res.second->hasType(VT))
25801 return Res; // Correct type already, nothing to do.
25803 // All of the single-register GCC register classes map their values onto
25804 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25805 // really want an 8-bit or 32-bit register, map to the appropriate register
25806 // class and return the appropriate register.
25807 if (Res.second == &X86::GR16RegClass) {
25808 if (VT == MVT::i8 || VT == MVT::i1) {
25809 unsigned DestReg = 0;
25810 switch (Res.first) {
25812 case X86::AX: DestReg = X86::AL; break;
25813 case X86::DX: DestReg = X86::DL; break;
25814 case X86::CX: DestReg = X86::CL; break;
25815 case X86::BX: DestReg = X86::BL; break;
25818 Res.first = DestReg;
25819 Res.second = &X86::GR8RegClass;
25821 } else if (VT == MVT::i32 || VT == MVT::f32) {
25822 unsigned DestReg = 0;
25823 switch (Res.first) {
25825 case X86::AX: DestReg = X86::EAX; break;
25826 case X86::DX: DestReg = X86::EDX; break;
25827 case X86::CX: DestReg = X86::ECX; break;
25828 case X86::BX: DestReg = X86::EBX; break;
25829 case X86::SI: DestReg = X86::ESI; break;
25830 case X86::DI: DestReg = X86::EDI; break;
25831 case X86::BP: DestReg = X86::EBP; break;
25832 case X86::SP: DestReg = X86::ESP; break;
25835 Res.first = DestReg;
25836 Res.second = &X86::GR32RegClass;
25838 } else if (VT == MVT::i64 || VT == MVT::f64) {
25839 unsigned DestReg = 0;
25840 switch (Res.first) {
25842 case X86::AX: DestReg = X86::RAX; break;
25843 case X86::DX: DestReg = X86::RDX; break;
25844 case X86::CX: DestReg = X86::RCX; break;
25845 case X86::BX: DestReg = X86::RBX; break;
25846 case X86::SI: DestReg = X86::RSI; break;
25847 case X86::DI: DestReg = X86::RDI; break;
25848 case X86::BP: DestReg = X86::RBP; break;
25849 case X86::SP: DestReg = X86::RSP; break;
25852 Res.first = DestReg;
25853 Res.second = &X86::GR64RegClass;
25856 } else if (Res.second == &X86::FR32RegClass ||
25857 Res.second == &X86::FR64RegClass ||
25858 Res.second == &X86::VR128RegClass ||
25859 Res.second == &X86::VR256RegClass ||
25860 Res.second == &X86::FR32XRegClass ||
25861 Res.second == &X86::FR64XRegClass ||
25862 Res.second == &X86::VR128XRegClass ||
25863 Res.second == &X86::VR256XRegClass ||
25864 Res.second == &X86::VR512RegClass) {
25865 // Handle references to XMM physical registers that got mapped into the
25866 // wrong class. This can happen with constraints like {xmm0} where the
25867 // target independent register mapper will just pick the first match it can
25868 // find, ignoring the required type.
25870 if (VT == MVT::f32 || VT == MVT::i32)
25871 Res.second = &X86::FR32RegClass;
25872 else if (VT == MVT::f64 || VT == MVT::i64)
25873 Res.second = &X86::FR64RegClass;
25874 else if (X86::VR128RegClass.hasType(VT))
25875 Res.second = &X86::VR128RegClass;
25876 else if (X86::VR256RegClass.hasType(VT))
25877 Res.second = &X86::VR256RegClass;
25878 else if (X86::VR512RegClass.hasType(VT))
25879 Res.second = &X86::VR512RegClass;
25885 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25887 // Scaling factors are not free at all.
25888 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25889 // will take 2 allocations in the out of order engine instead of 1
25890 // for plain addressing mode, i.e. inst (reg1).
25892 // vaddps (%rsi,%drx), %ymm0, %ymm1
25893 // Requires two allocations (one for the load, one for the computation)
25895 // vaddps (%rsi), %ymm0, %ymm1
25896 // Requires just 1 allocation, i.e., freeing allocations for other operations
25897 // and having less micro operations to execute.
25899 // For some X86 architectures, this is even worse because for instance for
25900 // stores, the complex addressing mode forces the instruction to use the
25901 // "load" ports instead of the dedicated "store" port.
25902 // E.g., on Haswell:
25903 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25904 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25905 if (isLegalAddressingMode(AM, Ty))
25906 // Scale represents reg2 * scale, thus account for 1
25907 // as soon as we use a second register.
25908 return AM.Scale != 0;
25912 bool X86TargetLowering::isTargetFTOL() const {
25913 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();