1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1164 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1166 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1168 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1170 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1173 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1174 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1179 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1184 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1188 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1190 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1193 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1196 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1198 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1200 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1202 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1203 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1206 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1207 setOperationAction(ISD::FMA, MVT::f32, Legal);
1208 setOperationAction(ISD::FMA, MVT::f64, Legal);
1211 if (Subtarget->hasInt256()) {
1212 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1213 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1215 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1217 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1218 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1219 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1220 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1222 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1223 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1224 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1225 // Don't lower v32i8 because there is no 128-bit byte mul
1227 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1229 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1231 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1232 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1234 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1239 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1241 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1242 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1243 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1244 // Don't lower v32i8 because there is no 128-bit byte mul
1247 // In the customized shift lowering, the legal cases in AVX2 will be
1249 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1252 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1253 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1255 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1257 // Custom lower several nodes for 256-bit types.
1258 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1259 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1260 MVT VT = (MVT::SimpleValueType)i;
1262 // Extract subvector is special because the value type
1263 // (result) is 128-bit but the source is 256-bit wide.
1264 if (VT.is128BitVector())
1265 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1267 // Do not attempt to custom lower other non-256-bit vectors
1268 if (!VT.is256BitVector())
1271 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1272 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1273 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1275 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1276 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1277 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1280 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1281 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1282 MVT VT = (MVT::SimpleValueType)i;
1284 // Do not attempt to promote non-256-bit vectors
1285 if (!VT.is256BitVector())
1288 setOperationAction(ISD::AND, VT, Promote);
1289 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1290 setOperationAction(ISD::OR, VT, Promote);
1291 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1292 setOperationAction(ISD::XOR, VT, Promote);
1293 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1294 setOperationAction(ISD::LOAD, VT, Promote);
1295 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1296 setOperationAction(ISD::SELECT, VT, Promote);
1297 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1301 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1302 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1308 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1310 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1315 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1317 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1322 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1324 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1329 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1330 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1332 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1336 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1337 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1338 if (Subtarget->is64Bit()) {
1339 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1340 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1341 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1342 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1344 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1345 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1346 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1347 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1348 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1349 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1350 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1351 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1353 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1354 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1355 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1356 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1357 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1358 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1359 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1360 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1361 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1362 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1364 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1366 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1367 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1370 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1372 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1373 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1375 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1377 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1378 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1379 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1380 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1381 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1383 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1386 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1387 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1389 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1391 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1392 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1394 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1395 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1397 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1398 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1400 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1401 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1402 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1403 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1404 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1405 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1407 // Custom lower several nodes.
1408 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1409 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1410 MVT VT = (MVT::SimpleValueType)i;
1412 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1413 // Extract subvector is special because the value type
1414 // (result) is 256/128-bit but the source is 512-bit wide.
1415 if (VT.is128BitVector() || VT.is256BitVector())
1416 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1418 if (VT.getVectorElementType() == MVT::i1)
1419 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1421 // Do not attempt to custom lower other non-512-bit vectors
1422 if (!VT.is512BitVector())
1425 if ( EltSize >= 32) {
1426 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1427 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1428 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1429 setOperationAction(ISD::VSELECT, VT, Legal);
1430 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1431 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1432 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1435 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1436 MVT VT = (MVT::SimpleValueType)i;
1438 // Do not attempt to promote non-256-bit vectors
1439 if (!VT.is512BitVector())
1442 setOperationAction(ISD::SELECT, VT, Promote);
1443 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1447 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1448 // of this type with custom code.
1449 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1450 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1451 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1455 // We want to custom lower some of our intrinsics.
1456 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1457 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1458 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1460 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1461 // handle type legalization for these operations here.
1463 // FIXME: We really should do custom legalization for addition and
1464 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1465 // than generic legalization for 64-bit multiplication-with-overflow, though.
1466 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1467 // Add/Sub/Mul with overflow operations are custom lowered.
1469 setOperationAction(ISD::SADDO, VT, Custom);
1470 setOperationAction(ISD::UADDO, VT, Custom);
1471 setOperationAction(ISD::SSUBO, VT, Custom);
1472 setOperationAction(ISD::USUBO, VT, Custom);
1473 setOperationAction(ISD::SMULO, VT, Custom);
1474 setOperationAction(ISD::UMULO, VT, Custom);
1477 // There are no 8-bit 3-address imul/mul instructions
1478 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1479 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1481 if (!Subtarget->is64Bit()) {
1482 // These libcalls are not available in 32-bit.
1483 setLibcallName(RTLIB::SHL_I128, 0);
1484 setLibcallName(RTLIB::SRL_I128, 0);
1485 setLibcallName(RTLIB::SRA_I128, 0);
1488 // Combine sin / cos into one node or libcall if possible.
1489 if (Subtarget->hasSinCos()) {
1490 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1491 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1492 if (Subtarget->isTargetDarwin()) {
1493 // For MacOSX, we don't want to the normal expansion of a libcall to
1494 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1496 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1497 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1501 // We have target-specific dag combine patterns for the following nodes:
1502 setTargetDAGCombine(ISD::CONCAT_VECTORS);
1503 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1504 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1505 setTargetDAGCombine(ISD::VSELECT);
1506 setTargetDAGCombine(ISD::SELECT);
1507 setTargetDAGCombine(ISD::SHL);
1508 setTargetDAGCombine(ISD::SRA);
1509 setTargetDAGCombine(ISD::SRL);
1510 setTargetDAGCombine(ISD::OR);
1511 setTargetDAGCombine(ISD::AND);
1512 setTargetDAGCombine(ISD::ADD);
1513 setTargetDAGCombine(ISD::FADD);
1514 setTargetDAGCombine(ISD::FSUB);
1515 setTargetDAGCombine(ISD::FMA);
1516 setTargetDAGCombine(ISD::SUB);
1517 setTargetDAGCombine(ISD::LOAD);
1518 setTargetDAGCombine(ISD::STORE);
1519 setTargetDAGCombine(ISD::ZERO_EXTEND);
1520 setTargetDAGCombine(ISD::ANY_EXTEND);
1521 setTargetDAGCombine(ISD::SIGN_EXTEND);
1522 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1523 setTargetDAGCombine(ISD::TRUNCATE);
1524 setTargetDAGCombine(ISD::SINT_TO_FP);
1525 setTargetDAGCombine(ISD::SETCC);
1526 if (Subtarget->is64Bit())
1527 setTargetDAGCombine(ISD::MUL);
1528 setTargetDAGCombine(ISD::XOR);
1530 computeRegisterProperties();
1532 // On Darwin, -Os means optimize for size without hurting performance,
1533 // do not reduce the limit.
1534 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1535 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1536 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1537 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1538 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1539 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1540 setPrefLoopAlignment(4); // 2^4 bytes.
1542 // Predictable cmov don't hurt on atom because it's in-order.
1543 PredictableSelectIsExpensive = !Subtarget->isAtom();
1545 setPrefFunctionAlignment(4); // 2^4 bytes.
1548 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1549 if (!VT.isVector()) return MVT::i8;
1550 return VT.changeVectorElementTypeToInteger();
1553 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1554 /// the desired ByVal argument alignment.
1555 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1558 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1559 if (VTy->getBitWidth() == 128)
1561 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1562 unsigned EltAlign = 0;
1563 getMaxByValAlign(ATy->getElementType(), EltAlign);
1564 if (EltAlign > MaxAlign)
1565 MaxAlign = EltAlign;
1566 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1567 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1568 unsigned EltAlign = 0;
1569 getMaxByValAlign(STy->getElementType(i), EltAlign);
1570 if (EltAlign > MaxAlign)
1571 MaxAlign = EltAlign;
1578 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1579 /// function arguments in the caller parameter area. For X86, aggregates
1580 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1581 /// are at 4-byte boundaries.
1582 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1583 if (Subtarget->is64Bit()) {
1584 // Max of 8 and alignment of type.
1585 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1592 if (Subtarget->hasSSE1())
1593 getMaxByValAlign(Ty, Align);
1597 /// getOptimalMemOpType - Returns the target specific optimal type for load
1598 /// and store operations as a result of memset, memcpy, and memmove
1599 /// lowering. If DstAlign is zero that means it's safe to destination
1600 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1601 /// means there isn't a need to check it against alignment requirement,
1602 /// probably because the source does not need to be loaded. If 'IsMemset' is
1603 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1604 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1605 /// source is constant so it does not need to be loaded.
1606 /// It returns EVT::Other if the type should be determined using generic
1607 /// target-independent logic.
1609 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1610 unsigned DstAlign, unsigned SrcAlign,
1611 bool IsMemset, bool ZeroMemset,
1613 MachineFunction &MF) const {
1614 const Function *F = MF.getFunction();
1615 if ((!IsMemset || ZeroMemset) &&
1616 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1617 Attribute::NoImplicitFloat)) {
1619 (Subtarget->isUnalignedMemAccessFast() ||
1620 ((DstAlign == 0 || DstAlign >= 16) &&
1621 (SrcAlign == 0 || SrcAlign >= 16)))) {
1623 if (Subtarget->hasInt256())
1625 if (Subtarget->hasFp256())
1628 if (Subtarget->hasSSE2())
1630 if (Subtarget->hasSSE1())
1632 } else if (!MemcpyStrSrc && Size >= 8 &&
1633 !Subtarget->is64Bit() &&
1634 Subtarget->hasSSE2()) {
1635 // Do not use f64 to lower memcpy if source is string constant. It's
1636 // better to use i32 to avoid the loads.
1640 if (Subtarget->is64Bit() && Size >= 8)
1645 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1647 return X86ScalarSSEf32;
1648 else if (VT == MVT::f64)
1649 return X86ScalarSSEf64;
1654 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1656 *Fast = Subtarget->isUnalignedMemAccessFast();
1660 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1661 /// current function. The returned value is a member of the
1662 /// MachineJumpTableInfo::JTEntryKind enum.
1663 unsigned X86TargetLowering::getJumpTableEncoding() const {
1664 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1666 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1667 Subtarget->isPICStyleGOT())
1668 return MachineJumpTableInfo::EK_Custom32;
1670 // Otherwise, use the normal jump table encoding heuristics.
1671 return TargetLowering::getJumpTableEncoding();
1675 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1676 const MachineBasicBlock *MBB,
1677 unsigned uid,MCContext &Ctx) const{
1678 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1679 Subtarget->isPICStyleGOT());
1680 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1682 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1683 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1686 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1688 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1689 SelectionDAG &DAG) const {
1690 if (!Subtarget->is64Bit())
1691 // This doesn't have SDLoc associated with it, but is not really the
1692 // same as a Register.
1693 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1697 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1698 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1700 const MCExpr *X86TargetLowering::
1701 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1702 MCContext &Ctx) const {
1703 // X86-64 uses RIP relative addressing based on the jump table label.
1704 if (Subtarget->isPICStyleRIPRel())
1705 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1707 // Otherwise, the reference is relative to the PIC base.
1708 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1711 // FIXME: Why this routine is here? Move to RegInfo!
1712 std::pair<const TargetRegisterClass*, uint8_t>
1713 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1714 const TargetRegisterClass *RRC = 0;
1716 switch (VT.SimpleTy) {
1718 return TargetLowering::findRepresentativeClass(VT);
1719 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1720 RRC = Subtarget->is64Bit() ?
1721 (const TargetRegisterClass*)&X86::GR64RegClass :
1722 (const TargetRegisterClass*)&X86::GR32RegClass;
1725 RRC = &X86::VR64RegClass;
1727 case MVT::f32: case MVT::f64:
1728 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1729 case MVT::v4f32: case MVT::v2f64:
1730 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1732 RRC = &X86::VR128RegClass;
1735 return std::make_pair(RRC, Cost);
1738 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1739 unsigned &Offset) const {
1740 if (!Subtarget->isTargetLinux())
1743 if (Subtarget->is64Bit()) {
1744 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1746 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1758 //===----------------------------------------------------------------------===//
1759 // Return Value Calling Convention Implementation
1760 //===----------------------------------------------------------------------===//
1762 #include "X86GenCallingConv.inc"
1765 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1766 MachineFunction &MF, bool isVarArg,
1767 const SmallVectorImpl<ISD::OutputArg> &Outs,
1768 LLVMContext &Context) const {
1769 SmallVector<CCValAssign, 16> RVLocs;
1770 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1772 return CCInfo.CheckReturn(Outs, RetCC_X86);
1776 X86TargetLowering::LowerReturn(SDValue Chain,
1777 CallingConv::ID CallConv, bool isVarArg,
1778 const SmallVectorImpl<ISD::OutputArg> &Outs,
1779 const SmallVectorImpl<SDValue> &OutVals,
1780 SDLoc dl, SelectionDAG &DAG) const {
1781 MachineFunction &MF = DAG.getMachineFunction();
1782 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1784 SmallVector<CCValAssign, 16> RVLocs;
1785 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1786 RVLocs, *DAG.getContext());
1787 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1790 SmallVector<SDValue, 6> RetOps;
1791 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1792 // Operand #1 = Bytes To Pop
1793 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1796 // Copy the result values into the output registers.
1797 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1798 CCValAssign &VA = RVLocs[i];
1799 assert(VA.isRegLoc() && "Can only return in registers!");
1800 SDValue ValToCopy = OutVals[i];
1801 EVT ValVT = ValToCopy.getValueType();
1803 // Promote values to the appropriate types
1804 if (VA.getLocInfo() == CCValAssign::SExt)
1805 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1806 else if (VA.getLocInfo() == CCValAssign::ZExt)
1807 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1808 else if (VA.getLocInfo() == CCValAssign::AExt)
1809 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1810 else if (VA.getLocInfo() == CCValAssign::BCvt)
1811 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1813 // If this is x86-64, and we disabled SSE, we can't return FP values,
1814 // or SSE or MMX vectors.
1815 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1816 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1817 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1818 report_fatal_error("SSE register return with SSE disabled");
1820 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1821 // llvm-gcc has never done it right and no one has noticed, so this
1822 // should be OK for now.
1823 if (ValVT == MVT::f64 &&
1824 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1825 report_fatal_error("SSE2 register return with SSE2 disabled");
1827 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1828 // the RET instruction and handled by the FP Stackifier.
1829 if (VA.getLocReg() == X86::ST0 ||
1830 VA.getLocReg() == X86::ST1) {
1831 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1832 // change the value to the FP stack register class.
1833 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1834 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1835 RetOps.push_back(ValToCopy);
1836 // Don't emit a copytoreg.
1840 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1841 // which is returned in RAX / RDX.
1842 if (Subtarget->is64Bit()) {
1843 if (ValVT == MVT::x86mmx) {
1844 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1845 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1846 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1848 // If we don't have SSE2 available, convert to v4f32 so the generated
1849 // register is legal.
1850 if (!Subtarget->hasSSE2())
1851 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1856 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1857 Flag = Chain.getValue(1);
1858 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1861 // The x86-64 ABIs require that for returning structs by value we copy
1862 // the sret argument into %rax/%eax (depending on ABI) for the return.
1863 // Win32 requires us to put the sret argument to %eax as well.
1864 // We saved the argument into a virtual register in the entry block,
1865 // so now we copy the value out and into %rax/%eax.
1866 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1867 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1868 MachineFunction &MF = DAG.getMachineFunction();
1869 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1870 unsigned Reg = FuncInfo->getSRetReturnReg();
1872 "SRetReturnReg should have been set in LowerFormalArguments().");
1873 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1876 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1877 X86::RAX : X86::EAX;
1878 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1879 Flag = Chain.getValue(1);
1881 // RAX/EAX now acts like a return value.
1882 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1885 RetOps[0] = Chain; // Update chain.
1887 // Add the flag if we have it.
1889 RetOps.push_back(Flag);
1891 return DAG.getNode(X86ISD::RET_FLAG, dl,
1892 MVT::Other, &RetOps[0], RetOps.size());
1895 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1896 if (N->getNumValues() != 1)
1898 if (!N->hasNUsesOfValue(1, 0))
1901 SDValue TCChain = Chain;
1902 SDNode *Copy = *N->use_begin();
1903 if (Copy->getOpcode() == ISD::CopyToReg) {
1904 // If the copy has a glue operand, we conservatively assume it isn't safe to
1905 // perform a tail call.
1906 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1908 TCChain = Copy->getOperand(0);
1909 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1912 bool HasRet = false;
1913 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1915 if (UI->getOpcode() != X86ISD::RET_FLAG)
1928 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1929 ISD::NodeType ExtendKind) const {
1931 // TODO: Is this also valid on 32-bit?
1932 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1933 ReturnMVT = MVT::i8;
1935 ReturnMVT = MVT::i32;
1937 MVT MinVT = getRegisterType(ReturnMVT);
1938 return VT.bitsLT(MinVT) ? MinVT : VT;
1941 /// LowerCallResult - Lower the result values of a call into the
1942 /// appropriate copies out of appropriate physical registers.
1945 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1946 CallingConv::ID CallConv, bool isVarArg,
1947 const SmallVectorImpl<ISD::InputArg> &Ins,
1948 SDLoc dl, SelectionDAG &DAG,
1949 SmallVectorImpl<SDValue> &InVals) const {
1951 // Assign locations to each value returned by this call.
1952 SmallVector<CCValAssign, 16> RVLocs;
1953 bool Is64Bit = Subtarget->is64Bit();
1954 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1955 getTargetMachine(), RVLocs, *DAG.getContext());
1956 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1958 // Copy all of the result registers out of their specified physreg.
1959 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1960 CCValAssign &VA = RVLocs[i];
1961 EVT CopyVT = VA.getValVT();
1963 // If this is x86-64, and we disabled SSE, we can't return FP values
1964 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1965 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1966 report_fatal_error("SSE register return with SSE disabled");
1971 // If this is a call to a function that returns an fp value on the floating
1972 // point stack, we must guarantee the value is popped from the stack, so
1973 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1974 // if the return value is not used. We use the FpPOP_RETVAL instruction
1976 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1977 // If we prefer to use the value in xmm registers, copy it out as f80 and
1978 // use a truncate to move it from fp stack reg to xmm reg.
1979 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1980 SDValue Ops[] = { Chain, InFlag };
1981 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1982 MVT::Other, MVT::Glue, Ops), 1);
1983 Val = Chain.getValue(0);
1985 // Round the f80 to the right size, which also moves it to the appropriate
1987 if (CopyVT != VA.getValVT())
1988 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1989 // This truncation won't change the value.
1990 DAG.getIntPtrConstant(1));
1992 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1993 CopyVT, InFlag).getValue(1);
1994 Val = Chain.getValue(0);
1996 InFlag = Chain.getValue(2);
1997 InVals.push_back(Val);
2003 //===----------------------------------------------------------------------===//
2004 // C & StdCall & Fast Calling Convention implementation
2005 //===----------------------------------------------------------------------===//
2006 // StdCall calling convention seems to be standard for many Windows' API
2007 // routines and around. It differs from C calling convention just a little:
2008 // callee should clean up the stack, not caller. Symbols should be also
2009 // decorated in some fancy way :) It doesn't support any vector arguments.
2010 // For info on fast calling convention see Fast Calling Convention (tail call)
2011 // implementation LowerX86_32FastCCCallTo.
2013 /// CallIsStructReturn - Determines whether a call uses struct return
2015 enum StructReturnType {
2020 static StructReturnType
2021 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2023 return NotStructReturn;
2025 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2026 if (!Flags.isSRet())
2027 return NotStructReturn;
2028 if (Flags.isInReg())
2029 return RegStructReturn;
2030 return StackStructReturn;
2033 /// ArgsAreStructReturn - Determines whether a function uses struct
2034 /// return semantics.
2035 static StructReturnType
2036 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2038 return NotStructReturn;
2040 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2041 if (!Flags.isSRet())
2042 return NotStructReturn;
2043 if (Flags.isInReg())
2044 return RegStructReturn;
2045 return StackStructReturn;
2048 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2049 /// by "Src" to address "Dst" with size and alignment information specified by
2050 /// the specific parameter attribute. The copy will be passed as a byval
2051 /// function parameter.
2053 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2054 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2056 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2058 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2059 /*isVolatile*/false, /*AlwaysInline=*/true,
2060 MachinePointerInfo(), MachinePointerInfo());
2063 /// IsTailCallConvention - Return true if the calling convention is one that
2064 /// supports tail call optimization.
2065 static bool IsTailCallConvention(CallingConv::ID CC) {
2066 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2067 CC == CallingConv::HiPE);
2070 /// \brief Return true if the calling convention is a C calling convention.
2071 static bool IsCCallConvention(CallingConv::ID CC) {
2072 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2073 CC == CallingConv::X86_64_SysV);
2076 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2077 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2081 CallingConv::ID CalleeCC = CS.getCallingConv();
2082 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2088 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2089 /// a tailcall target by changing its ABI.
2090 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2091 bool GuaranteedTailCallOpt) {
2092 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2096 X86TargetLowering::LowerMemArgument(SDValue Chain,
2097 CallingConv::ID CallConv,
2098 const SmallVectorImpl<ISD::InputArg> &Ins,
2099 SDLoc dl, SelectionDAG &DAG,
2100 const CCValAssign &VA,
2101 MachineFrameInfo *MFI,
2103 // Create the nodes corresponding to a load from this parameter slot.
2104 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2105 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2106 getTargetMachine().Options.GuaranteedTailCallOpt);
2107 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2110 // If value is passed by pointer we have address passed instead of the value
2112 if (VA.getLocInfo() == CCValAssign::Indirect)
2113 ValVT = VA.getLocVT();
2115 ValVT = VA.getValVT();
2117 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2118 // changed with more analysis.
2119 // In case of tail call optimization mark all arguments mutable. Since they
2120 // could be overwritten by lowering of arguments in case of a tail call.
2121 if (Flags.isByVal()) {
2122 unsigned Bytes = Flags.getByValSize();
2123 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2124 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2125 return DAG.getFrameIndex(FI, getPointerTy());
2127 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2128 VA.getLocMemOffset(), isImmutable);
2129 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2130 return DAG.getLoad(ValVT, dl, Chain, FIN,
2131 MachinePointerInfo::getFixedStack(FI),
2132 false, false, false, 0);
2137 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2138 CallingConv::ID CallConv,
2140 const SmallVectorImpl<ISD::InputArg> &Ins,
2143 SmallVectorImpl<SDValue> &InVals)
2145 MachineFunction &MF = DAG.getMachineFunction();
2146 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2148 const Function* Fn = MF.getFunction();
2149 if (Fn->hasExternalLinkage() &&
2150 Subtarget->isTargetCygMing() &&
2151 Fn->getName() == "main")
2152 FuncInfo->setForceFramePointer(true);
2154 MachineFrameInfo *MFI = MF.getFrameInfo();
2155 bool Is64Bit = Subtarget->is64Bit();
2156 bool IsWindows = Subtarget->isTargetWindows();
2157 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2159 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2160 "Var args not supported with calling convention fastcc, ghc or hipe");
2162 // Assign locations to all of the incoming arguments.
2163 SmallVector<CCValAssign, 16> ArgLocs;
2164 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2165 ArgLocs, *DAG.getContext());
2167 // Allocate shadow area for Win64
2169 CCInfo.AllocateStack(32, 8);
2171 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2173 unsigned LastVal = ~0U;
2175 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2176 CCValAssign &VA = ArgLocs[i];
2177 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2179 assert(VA.getValNo() != LastVal &&
2180 "Don't support value assigned to multiple locs yet");
2182 LastVal = VA.getValNo();
2184 if (VA.isRegLoc()) {
2185 EVT RegVT = VA.getLocVT();
2186 const TargetRegisterClass *RC;
2187 if (RegVT == MVT::i32)
2188 RC = &X86::GR32RegClass;
2189 else if (Is64Bit && RegVT == MVT::i64)
2190 RC = &X86::GR64RegClass;
2191 else if (RegVT == MVT::f32)
2192 RC = &X86::FR32RegClass;
2193 else if (RegVT == MVT::f64)
2194 RC = &X86::FR64RegClass;
2195 else if (RegVT.is512BitVector())
2196 RC = &X86::VR512RegClass;
2197 else if (RegVT.is256BitVector())
2198 RC = &X86::VR256RegClass;
2199 else if (RegVT.is128BitVector())
2200 RC = &X86::VR128RegClass;
2201 else if (RegVT == MVT::x86mmx)
2202 RC = &X86::VR64RegClass;
2203 else if (RegVT == MVT::v8i1)
2204 RC = &X86::VK8RegClass;
2205 else if (RegVT == MVT::v16i1)
2206 RC = &X86::VK16RegClass;
2208 llvm_unreachable("Unknown argument type!");
2210 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2211 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2213 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2214 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2216 if (VA.getLocInfo() == CCValAssign::SExt)
2217 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2218 DAG.getValueType(VA.getValVT()));
2219 else if (VA.getLocInfo() == CCValAssign::ZExt)
2220 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2221 DAG.getValueType(VA.getValVT()));
2222 else if (VA.getLocInfo() == CCValAssign::BCvt)
2223 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2225 if (VA.isExtInLoc()) {
2226 // Handle MMX values passed in XMM regs.
2227 if (RegVT.isVector())
2228 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2230 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2233 assert(VA.isMemLoc());
2234 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2237 // If value is passed via pointer - do a load.
2238 if (VA.getLocInfo() == CCValAssign::Indirect)
2239 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2240 MachinePointerInfo(), false, false, false, 0);
2242 InVals.push_back(ArgValue);
2245 // The x86-64 ABIs require that for returning structs by value we copy
2246 // the sret argument into %rax/%eax (depending on ABI) for the return.
2247 // Win32 requires us to put the sret argument to %eax as well.
2248 // Save the argument into a virtual register so that we can access it
2249 // from the return points.
2250 if (MF.getFunction()->hasStructRetAttr() &&
2251 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2252 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2253 unsigned Reg = FuncInfo->getSRetReturnReg();
2255 MVT PtrTy = getPointerTy();
2256 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2257 FuncInfo->setSRetReturnReg(Reg);
2259 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2260 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2263 unsigned StackSize = CCInfo.getNextStackOffset();
2264 // Align stack specially for tail calls.
2265 if (FuncIsMadeTailCallSafe(CallConv,
2266 MF.getTarget().Options.GuaranteedTailCallOpt))
2267 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2269 // If the function takes variable number of arguments, make a frame index for
2270 // the start of the first vararg value... for expansion of llvm.va_start.
2272 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2273 CallConv != CallingConv::X86_ThisCall)) {
2274 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2277 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2279 // FIXME: We should really autogenerate these arrays
2280 static const uint16_t GPR64ArgRegsWin64[] = {
2281 X86::RCX, X86::RDX, X86::R8, X86::R9
2283 static const uint16_t GPR64ArgRegs64Bit[] = {
2284 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2286 static const uint16_t XMMArgRegs64Bit[] = {
2287 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2288 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2290 const uint16_t *GPR64ArgRegs;
2291 unsigned NumXMMRegs = 0;
2294 // The XMM registers which might contain var arg parameters are shadowed
2295 // in their paired GPR. So we only need to save the GPR to their home
2297 TotalNumIntRegs = 4;
2298 GPR64ArgRegs = GPR64ArgRegsWin64;
2300 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2301 GPR64ArgRegs = GPR64ArgRegs64Bit;
2303 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2306 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2309 bool NoImplicitFloatOps = Fn->getAttributes().
2310 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2311 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2312 "SSE register cannot be used when SSE is disabled!");
2313 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2314 NoImplicitFloatOps) &&
2315 "SSE register cannot be used when SSE is disabled!");
2316 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2317 !Subtarget->hasSSE1())
2318 // Kernel mode asks for SSE to be disabled, so don't push them
2320 TotalNumXMMRegs = 0;
2323 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2324 // Get to the caller-allocated home save location. Add 8 to account
2325 // for the return address.
2326 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2327 FuncInfo->setRegSaveFrameIndex(
2328 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2329 // Fixup to set vararg frame on shadow area (4 x i64).
2331 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2333 // For X86-64, if there are vararg parameters that are passed via
2334 // registers, then we must store them to their spots on the stack so
2335 // they may be loaded by deferencing the result of va_next.
2336 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2337 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2338 FuncInfo->setRegSaveFrameIndex(
2339 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2343 // Store the integer parameter registers.
2344 SmallVector<SDValue, 8> MemOps;
2345 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2347 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2348 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2349 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2350 DAG.getIntPtrConstant(Offset));
2351 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2352 &X86::GR64RegClass);
2353 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2355 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2356 MachinePointerInfo::getFixedStack(
2357 FuncInfo->getRegSaveFrameIndex(), Offset),
2359 MemOps.push_back(Store);
2363 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2364 // Now store the XMM (fp + vector) parameter registers.
2365 SmallVector<SDValue, 11> SaveXMMOps;
2366 SaveXMMOps.push_back(Chain);
2368 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2369 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2370 SaveXMMOps.push_back(ALVal);
2372 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2373 FuncInfo->getRegSaveFrameIndex()));
2374 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2375 FuncInfo->getVarArgsFPOffset()));
2377 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2378 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2379 &X86::VR128RegClass);
2380 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2381 SaveXMMOps.push_back(Val);
2383 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2385 &SaveXMMOps[0], SaveXMMOps.size()));
2388 if (!MemOps.empty())
2389 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2390 &MemOps[0], MemOps.size());
2394 // Some CCs need callee pop.
2395 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2396 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2397 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2399 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2400 // If this is an sret function, the return should pop the hidden pointer.
2401 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2402 argsAreStructReturn(Ins) == StackStructReturn)
2403 FuncInfo->setBytesToPopOnReturn(4);
2407 // RegSaveFrameIndex is X86-64 only.
2408 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2409 if (CallConv == CallingConv::X86_FastCall ||
2410 CallConv == CallingConv::X86_ThisCall)
2411 // fastcc functions can't have varargs.
2412 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2415 FuncInfo->setArgumentStackSize(StackSize);
2421 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2422 SDValue StackPtr, SDValue Arg,
2423 SDLoc dl, SelectionDAG &DAG,
2424 const CCValAssign &VA,
2425 ISD::ArgFlagsTy Flags) const {
2426 unsigned LocMemOffset = VA.getLocMemOffset();
2427 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2428 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2429 if (Flags.isByVal())
2430 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2432 return DAG.getStore(Chain, dl, Arg, PtrOff,
2433 MachinePointerInfo::getStack(LocMemOffset),
2437 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2438 /// optimization is performed and it is required.
2440 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2441 SDValue &OutRetAddr, SDValue Chain,
2442 bool IsTailCall, bool Is64Bit,
2443 int FPDiff, SDLoc dl) const {
2444 // Adjust the Return address stack slot.
2445 EVT VT = getPointerTy();
2446 OutRetAddr = getReturnAddressFrameIndex(DAG);
2448 // Load the "old" Return address.
2449 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2450 false, false, false, 0);
2451 return SDValue(OutRetAddr.getNode(), 1);
2454 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2455 /// optimization is performed and it is required (FPDiff!=0).
2457 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2458 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2459 unsigned SlotSize, int FPDiff, SDLoc dl) {
2460 // Store the return address to the appropriate stack slot.
2461 if (!FPDiff) return Chain;
2462 // Calculate the new stack slot for the return address.
2463 int NewReturnAddrFI =
2464 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2466 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2467 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2468 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2474 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2475 SmallVectorImpl<SDValue> &InVals) const {
2476 SelectionDAG &DAG = CLI.DAG;
2478 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2479 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2480 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2481 SDValue Chain = CLI.Chain;
2482 SDValue Callee = CLI.Callee;
2483 CallingConv::ID CallConv = CLI.CallConv;
2484 bool &isTailCall = CLI.IsTailCall;
2485 bool isVarArg = CLI.IsVarArg;
2487 MachineFunction &MF = DAG.getMachineFunction();
2488 bool Is64Bit = Subtarget->is64Bit();
2489 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2490 bool IsWindows = Subtarget->isTargetWindows();
2491 StructReturnType SR = callIsStructReturn(Outs);
2492 bool IsSibcall = false;
2494 if (MF.getTarget().Options.DisableTailCalls)
2498 // Check if it's really possible to do a tail call.
2499 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2500 isVarArg, SR != NotStructReturn,
2501 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2502 Outs, OutVals, Ins, DAG);
2504 // Sibcalls are automatically detected tailcalls which do not require
2506 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2513 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2514 "Var args not supported with calling convention fastcc, ghc or hipe");
2516 // Analyze operands of the call, assigning locations to each operand.
2517 SmallVector<CCValAssign, 16> ArgLocs;
2518 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2519 ArgLocs, *DAG.getContext());
2521 // Allocate shadow area for Win64
2523 CCInfo.AllocateStack(32, 8);
2525 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2527 // Get a count of how many bytes are to be pushed on the stack.
2528 unsigned NumBytes = CCInfo.getNextStackOffset();
2530 // This is a sibcall. The memory operands are available in caller's
2531 // own caller's stack.
2533 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2534 IsTailCallConvention(CallConv))
2535 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2538 if (isTailCall && !IsSibcall) {
2539 // Lower arguments at fp - stackoffset + fpdiff.
2540 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2541 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2543 FPDiff = NumBytesCallerPushed - NumBytes;
2545 // Set the delta of movement of the returnaddr stackslot.
2546 // But only set if delta is greater than previous delta.
2547 if (FPDiff < X86Info->getTCReturnAddrDelta())
2548 X86Info->setTCReturnAddrDelta(FPDiff);
2552 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2555 SDValue RetAddrFrIdx;
2556 // Load return address for tail calls.
2557 if (isTailCall && FPDiff)
2558 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2559 Is64Bit, FPDiff, dl);
2561 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2562 SmallVector<SDValue, 8> MemOpChains;
2565 // Walk the register/memloc assignments, inserting copies/loads. In the case
2566 // of tail call optimization arguments are handle later.
2567 const X86RegisterInfo *RegInfo =
2568 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2569 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2570 CCValAssign &VA = ArgLocs[i];
2571 EVT RegVT = VA.getLocVT();
2572 SDValue Arg = OutVals[i];
2573 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2574 bool isByVal = Flags.isByVal();
2576 // Promote the value if needed.
2577 switch (VA.getLocInfo()) {
2578 default: llvm_unreachable("Unknown loc info!");
2579 case CCValAssign::Full: break;
2580 case CCValAssign::SExt:
2581 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2583 case CCValAssign::ZExt:
2584 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2586 case CCValAssign::AExt:
2587 if (RegVT.is128BitVector()) {
2588 // Special case: passing MMX values in XMM registers.
2589 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2590 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2591 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2593 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2595 case CCValAssign::BCvt:
2596 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2598 case CCValAssign::Indirect: {
2599 // Store the argument.
2600 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2601 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2602 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2603 MachinePointerInfo::getFixedStack(FI),
2610 if (VA.isRegLoc()) {
2611 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2612 if (isVarArg && IsWin64) {
2613 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2614 // shadow reg if callee is a varargs function.
2615 unsigned ShadowReg = 0;
2616 switch (VA.getLocReg()) {
2617 case X86::XMM0: ShadowReg = X86::RCX; break;
2618 case X86::XMM1: ShadowReg = X86::RDX; break;
2619 case X86::XMM2: ShadowReg = X86::R8; break;
2620 case X86::XMM3: ShadowReg = X86::R9; break;
2623 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2625 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2626 assert(VA.isMemLoc());
2627 if (StackPtr.getNode() == 0)
2628 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2630 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2631 dl, DAG, VA, Flags));
2635 if (!MemOpChains.empty())
2636 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2637 &MemOpChains[0], MemOpChains.size());
2639 if (Subtarget->isPICStyleGOT()) {
2640 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2643 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2644 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2646 // If we are tail calling and generating PIC/GOT style code load the
2647 // address of the callee into ECX. The value in ecx is used as target of
2648 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2649 // for tail calls on PIC/GOT architectures. Normally we would just put the
2650 // address of GOT into ebx and then call target@PLT. But for tail calls
2651 // ebx would be restored (since ebx is callee saved) before jumping to the
2654 // Note: The actual moving to ECX is done further down.
2655 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2656 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2657 !G->getGlobal()->hasProtectedVisibility())
2658 Callee = LowerGlobalAddress(Callee, DAG);
2659 else if (isa<ExternalSymbolSDNode>(Callee))
2660 Callee = LowerExternalSymbol(Callee, DAG);
2664 if (Is64Bit && isVarArg && !IsWin64) {
2665 // From AMD64 ABI document:
2666 // For calls that may call functions that use varargs or stdargs
2667 // (prototype-less calls or calls to functions containing ellipsis (...) in
2668 // the declaration) %al is used as hidden argument to specify the number
2669 // of SSE registers used. The contents of %al do not need to match exactly
2670 // the number of registers, but must be an ubound on the number of SSE
2671 // registers used and is in the range 0 - 8 inclusive.
2673 // Count the number of XMM registers allocated.
2674 static const uint16_t XMMArgRegs[] = {
2675 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2676 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2678 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2679 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2680 && "SSE registers cannot be used when SSE is disabled");
2682 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2683 DAG.getConstant(NumXMMRegs, MVT::i8)));
2686 // For tail calls lower the arguments to the 'real' stack slot.
2688 // Force all the incoming stack arguments to be loaded from the stack
2689 // before any new outgoing arguments are stored to the stack, because the
2690 // outgoing stack slots may alias the incoming argument stack slots, and
2691 // the alias isn't otherwise explicit. This is slightly more conservative
2692 // than necessary, because it means that each store effectively depends
2693 // on every argument instead of just those arguments it would clobber.
2694 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2696 SmallVector<SDValue, 8> MemOpChains2;
2699 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2700 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2701 CCValAssign &VA = ArgLocs[i];
2704 assert(VA.isMemLoc());
2705 SDValue Arg = OutVals[i];
2706 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2707 // Create frame index.
2708 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2709 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2710 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2711 FIN = DAG.getFrameIndex(FI, getPointerTy());
2713 if (Flags.isByVal()) {
2714 // Copy relative to framepointer.
2715 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2716 if (StackPtr.getNode() == 0)
2717 StackPtr = DAG.getCopyFromReg(Chain, dl,
2718 RegInfo->getStackRegister(),
2720 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2722 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2726 // Store relative to framepointer.
2727 MemOpChains2.push_back(
2728 DAG.getStore(ArgChain, dl, Arg, FIN,
2729 MachinePointerInfo::getFixedStack(FI),
2735 if (!MemOpChains2.empty())
2736 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2737 &MemOpChains2[0], MemOpChains2.size());
2739 // Store the return address to the appropriate stack slot.
2740 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2741 getPointerTy(), RegInfo->getSlotSize(),
2745 // Build a sequence of copy-to-reg nodes chained together with token chain
2746 // and flag operands which copy the outgoing args into registers.
2748 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2749 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2750 RegsToPass[i].second, InFlag);
2751 InFlag = Chain.getValue(1);
2754 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2755 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2756 // In the 64-bit large code model, we have to make all calls
2757 // through a register, since the call instruction's 32-bit
2758 // pc-relative offset may not be large enough to hold the whole
2760 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2761 // If the callee is a GlobalAddress node (quite common, every direct call
2762 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2765 // We should use extra load for direct calls to dllimported functions in
2767 const GlobalValue *GV = G->getGlobal();
2768 if (!GV->hasDLLImportLinkage()) {
2769 unsigned char OpFlags = 0;
2770 bool ExtraLoad = false;
2771 unsigned WrapperKind = ISD::DELETED_NODE;
2773 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2774 // external symbols most go through the PLT in PIC mode. If the symbol
2775 // has hidden or protected visibility, or if it is static or local, then
2776 // we don't need to use the PLT - we can directly call it.
2777 if (Subtarget->isTargetELF() &&
2778 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2779 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2780 OpFlags = X86II::MO_PLT;
2781 } else if (Subtarget->isPICStyleStubAny() &&
2782 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2783 (!Subtarget->getTargetTriple().isMacOSX() ||
2784 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2785 // PC-relative references to external symbols should go through $stub,
2786 // unless we're building with the leopard linker or later, which
2787 // automatically synthesizes these stubs.
2788 OpFlags = X86II::MO_DARWIN_STUB;
2789 } else if (Subtarget->isPICStyleRIPRel() &&
2790 isa<Function>(GV) &&
2791 cast<Function>(GV)->getAttributes().
2792 hasAttribute(AttributeSet::FunctionIndex,
2793 Attribute::NonLazyBind)) {
2794 // If the function is marked as non-lazy, generate an indirect call
2795 // which loads from the GOT directly. This avoids runtime overhead
2796 // at the cost of eager binding (and one extra byte of encoding).
2797 OpFlags = X86II::MO_GOTPCREL;
2798 WrapperKind = X86ISD::WrapperRIP;
2802 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2803 G->getOffset(), OpFlags);
2805 // Add a wrapper if needed.
2806 if (WrapperKind != ISD::DELETED_NODE)
2807 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2808 // Add extra indirection if needed.
2810 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2811 MachinePointerInfo::getGOT(),
2812 false, false, false, 0);
2814 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2815 unsigned char OpFlags = 0;
2817 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2818 // external symbols should go through the PLT.
2819 if (Subtarget->isTargetELF() &&
2820 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2821 OpFlags = X86II::MO_PLT;
2822 } else if (Subtarget->isPICStyleStubAny() &&
2823 (!Subtarget->getTargetTriple().isMacOSX() ||
2824 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2825 // PC-relative references to external symbols should go through $stub,
2826 // unless we're building with the leopard linker or later, which
2827 // automatically synthesizes these stubs.
2828 OpFlags = X86II::MO_DARWIN_STUB;
2831 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2835 // Returns a chain & a flag for retval copy to use.
2836 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2837 SmallVector<SDValue, 8> Ops;
2839 if (!IsSibcall && isTailCall) {
2840 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2841 DAG.getIntPtrConstant(0, true), InFlag, dl);
2842 InFlag = Chain.getValue(1);
2845 Ops.push_back(Chain);
2846 Ops.push_back(Callee);
2849 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2851 // Add argument registers to the end of the list so that they are known live
2853 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2854 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2855 RegsToPass[i].second.getValueType()));
2857 // Add a register mask operand representing the call-preserved registers.
2858 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2859 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2860 assert(Mask && "Missing call preserved mask for calling convention");
2861 Ops.push_back(DAG.getRegisterMask(Mask));
2863 if (InFlag.getNode())
2864 Ops.push_back(InFlag);
2868 //// If this is the first return lowered for this function, add the regs
2869 //// to the liveout set for the function.
2870 // This isn't right, although it's probably harmless on x86; liveouts
2871 // should be computed from returns not tail calls. Consider a void
2872 // function making a tail call to a function returning int.
2873 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2876 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2877 InFlag = Chain.getValue(1);
2879 // Create the CALLSEQ_END node.
2880 unsigned NumBytesForCalleeToPush;
2881 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2882 getTargetMachine().Options.GuaranteedTailCallOpt))
2883 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2884 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2885 SR == StackStructReturn)
2886 // If this is a call to a struct-return function, the callee
2887 // pops the hidden struct pointer, so we have to push it back.
2888 // This is common for Darwin/X86, Linux & Mingw32 targets.
2889 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2890 NumBytesForCalleeToPush = 4;
2892 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2894 // Returns a flag for retval copy to use.
2896 Chain = DAG.getCALLSEQ_END(Chain,
2897 DAG.getIntPtrConstant(NumBytes, true),
2898 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2901 InFlag = Chain.getValue(1);
2904 // Handle result values, copying them out of physregs into vregs that we
2906 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2907 Ins, dl, DAG, InVals);
2910 //===----------------------------------------------------------------------===//
2911 // Fast Calling Convention (tail call) implementation
2912 //===----------------------------------------------------------------------===//
2914 // Like std call, callee cleans arguments, convention except that ECX is
2915 // reserved for storing the tail called function address. Only 2 registers are
2916 // free for argument passing (inreg). Tail call optimization is performed
2918 // * tailcallopt is enabled
2919 // * caller/callee are fastcc
2920 // On X86_64 architecture with GOT-style position independent code only local
2921 // (within module) calls are supported at the moment.
2922 // To keep the stack aligned according to platform abi the function
2923 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2924 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2925 // If a tail called function callee has more arguments than the caller the
2926 // caller needs to make sure that there is room to move the RETADDR to. This is
2927 // achieved by reserving an area the size of the argument delta right after the
2928 // original REtADDR, but before the saved framepointer or the spilled registers
2929 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2941 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2942 /// for a 16 byte align requirement.
2944 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2945 SelectionDAG& DAG) const {
2946 MachineFunction &MF = DAG.getMachineFunction();
2947 const TargetMachine &TM = MF.getTarget();
2948 const X86RegisterInfo *RegInfo =
2949 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2950 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2951 unsigned StackAlignment = TFI.getStackAlignment();
2952 uint64_t AlignMask = StackAlignment - 1;
2953 int64_t Offset = StackSize;
2954 unsigned SlotSize = RegInfo->getSlotSize();
2955 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2956 // Number smaller than 12 so just add the difference.
2957 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2959 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2960 Offset = ((~AlignMask) & Offset) + StackAlignment +
2961 (StackAlignment-SlotSize);
2966 /// MatchingStackOffset - Return true if the given stack call argument is
2967 /// already available in the same position (relatively) of the caller's
2968 /// incoming argument stack.
2970 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2971 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2972 const X86InstrInfo *TII) {
2973 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2975 if (Arg.getOpcode() == ISD::CopyFromReg) {
2976 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2977 if (!TargetRegisterInfo::isVirtualRegister(VR))
2979 MachineInstr *Def = MRI->getVRegDef(VR);
2982 if (!Flags.isByVal()) {
2983 if (!TII->isLoadFromStackSlot(Def, FI))
2986 unsigned Opcode = Def->getOpcode();
2987 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2988 Def->getOperand(1).isFI()) {
2989 FI = Def->getOperand(1).getIndex();
2990 Bytes = Flags.getByValSize();
2994 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2995 if (Flags.isByVal())
2996 // ByVal argument is passed in as a pointer but it's now being
2997 // dereferenced. e.g.
2998 // define @foo(%struct.X* %A) {
2999 // tail call @bar(%struct.X* byval %A)
3002 SDValue Ptr = Ld->getBasePtr();
3003 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3006 FI = FINode->getIndex();
3007 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3008 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3009 FI = FINode->getIndex();
3010 Bytes = Flags.getByValSize();
3014 assert(FI != INT_MAX);
3015 if (!MFI->isFixedObjectIndex(FI))
3017 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3020 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3021 /// for tail call optimization. Targets which want to do tail call
3022 /// optimization should implement this function.
3024 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3025 CallingConv::ID CalleeCC,
3027 bool isCalleeStructRet,
3028 bool isCallerStructRet,
3030 const SmallVectorImpl<ISD::OutputArg> &Outs,
3031 const SmallVectorImpl<SDValue> &OutVals,
3032 const SmallVectorImpl<ISD::InputArg> &Ins,
3033 SelectionDAG &DAG) const {
3034 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3037 // If -tailcallopt is specified, make fastcc functions tail-callable.
3038 const MachineFunction &MF = DAG.getMachineFunction();
3039 const Function *CallerF = MF.getFunction();
3041 // If the function return type is x86_fp80 and the callee return type is not,
3042 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3043 // perform a tailcall optimization here.
3044 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3047 CallingConv::ID CallerCC = CallerF->getCallingConv();
3048 bool CCMatch = CallerCC == CalleeCC;
3049 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3050 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3052 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3053 if (IsTailCallConvention(CalleeCC) && CCMatch)
3058 // Look for obvious safe cases to perform tail call optimization that do not
3059 // require ABI changes. This is what gcc calls sibcall.
3061 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3062 // emit a special epilogue.
3063 const X86RegisterInfo *RegInfo =
3064 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3065 if (RegInfo->needsStackRealignment(MF))
3068 // Also avoid sibcall optimization if either caller or callee uses struct
3069 // return semantics.
3070 if (isCalleeStructRet || isCallerStructRet)
3073 // An stdcall caller is expected to clean up its arguments; the callee
3074 // isn't going to do that.
3075 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3078 // Do not sibcall optimize vararg calls unless all arguments are passed via
3080 if (isVarArg && !Outs.empty()) {
3082 // Optimizing for varargs on Win64 is unlikely to be safe without
3083 // additional testing.
3084 if (IsCalleeWin64 || IsCallerWin64)
3087 SmallVector<CCValAssign, 16> ArgLocs;
3088 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3089 getTargetMachine(), ArgLocs, *DAG.getContext());
3091 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3092 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3093 if (!ArgLocs[i].isRegLoc())
3097 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3098 // stack. Therefore, if it's not used by the call it is not safe to optimize
3099 // this into a sibcall.
3100 bool Unused = false;
3101 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3108 SmallVector<CCValAssign, 16> RVLocs;
3109 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3110 getTargetMachine(), RVLocs, *DAG.getContext());
3111 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3112 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3113 CCValAssign &VA = RVLocs[i];
3114 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3119 // If the calling conventions do not match, then we'd better make sure the
3120 // results are returned in the same way as what the caller expects.
3122 SmallVector<CCValAssign, 16> RVLocs1;
3123 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3124 getTargetMachine(), RVLocs1, *DAG.getContext());
3125 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3127 SmallVector<CCValAssign, 16> RVLocs2;
3128 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3129 getTargetMachine(), RVLocs2, *DAG.getContext());
3130 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3132 if (RVLocs1.size() != RVLocs2.size())
3134 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3135 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3137 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3139 if (RVLocs1[i].isRegLoc()) {
3140 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3143 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3149 // If the callee takes no arguments then go on to check the results of the
3151 if (!Outs.empty()) {
3152 // Check if stack adjustment is needed. For now, do not do this if any
3153 // argument is passed on the stack.
3154 SmallVector<CCValAssign, 16> ArgLocs;
3155 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3156 getTargetMachine(), ArgLocs, *DAG.getContext());
3158 // Allocate shadow area for Win64
3160 CCInfo.AllocateStack(32, 8);
3162 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3163 if (CCInfo.getNextStackOffset()) {
3164 MachineFunction &MF = DAG.getMachineFunction();
3165 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3168 // Check if the arguments are already laid out in the right way as
3169 // the caller's fixed stack objects.
3170 MachineFrameInfo *MFI = MF.getFrameInfo();
3171 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3172 const X86InstrInfo *TII =
3173 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3174 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3175 CCValAssign &VA = ArgLocs[i];
3176 SDValue Arg = OutVals[i];
3177 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3178 if (VA.getLocInfo() == CCValAssign::Indirect)
3180 if (!VA.isRegLoc()) {
3181 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3188 // If the tailcall address may be in a register, then make sure it's
3189 // possible to register allocate for it. In 32-bit, the call address can
3190 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3191 // callee-saved registers are restored. These happen to be the same
3192 // registers used to pass 'inreg' arguments so watch out for those.
3193 if (!Subtarget->is64Bit() &&
3194 ((!isa<GlobalAddressSDNode>(Callee) &&
3195 !isa<ExternalSymbolSDNode>(Callee)) ||
3196 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3197 unsigned NumInRegs = 0;
3198 // In PIC we need an extra register to formulate the address computation
3200 unsigned MaxInRegs =
3201 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3203 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3204 CCValAssign &VA = ArgLocs[i];
3207 unsigned Reg = VA.getLocReg();
3210 case X86::EAX: case X86::EDX: case X86::ECX:
3211 if (++NumInRegs == MaxInRegs)
3223 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3224 const TargetLibraryInfo *libInfo) const {
3225 return X86::createFastISel(funcInfo, libInfo);
3228 //===----------------------------------------------------------------------===//
3229 // Other Lowering Hooks
3230 //===----------------------------------------------------------------------===//
3232 static bool MayFoldLoad(SDValue Op) {
3233 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3236 static bool MayFoldIntoStore(SDValue Op) {
3237 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3240 static bool isTargetShuffle(unsigned Opcode) {
3242 default: return false;
3243 case X86ISD::PSHUFD:
3244 case X86ISD::PSHUFHW:
3245 case X86ISD::PSHUFLW:
3247 case X86ISD::PALIGNR:
3248 case X86ISD::MOVLHPS:
3249 case X86ISD::MOVLHPD:
3250 case X86ISD::MOVHLPS:
3251 case X86ISD::MOVLPS:
3252 case X86ISD::MOVLPD:
3253 case X86ISD::MOVSHDUP:
3254 case X86ISD::MOVSLDUP:
3255 case X86ISD::MOVDDUP:
3258 case X86ISD::UNPCKL:
3259 case X86ISD::UNPCKH:
3260 case X86ISD::VPERMILP:
3261 case X86ISD::VPERM2X128:
3262 case X86ISD::VPERMI:
3267 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3268 SDValue V1, SelectionDAG &DAG) {
3270 default: llvm_unreachable("Unknown x86 shuffle node");
3271 case X86ISD::MOVSHDUP:
3272 case X86ISD::MOVSLDUP:
3273 case X86ISD::MOVDDUP:
3274 return DAG.getNode(Opc, dl, VT, V1);
3278 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3279 SDValue V1, unsigned TargetMask,
3280 SelectionDAG &DAG) {
3282 default: llvm_unreachable("Unknown x86 shuffle node");
3283 case X86ISD::PSHUFD:
3284 case X86ISD::PSHUFHW:
3285 case X86ISD::PSHUFLW:
3286 case X86ISD::VPERMILP:
3287 case X86ISD::VPERMI:
3288 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3292 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3293 SDValue V1, SDValue V2, unsigned TargetMask,
3294 SelectionDAG &DAG) {
3296 default: llvm_unreachable("Unknown x86 shuffle node");
3297 case X86ISD::PALIGNR:
3299 case X86ISD::VPERM2X128:
3300 return DAG.getNode(Opc, dl, VT, V1, V2,
3301 DAG.getConstant(TargetMask, MVT::i8));
3305 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3306 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3308 default: llvm_unreachable("Unknown x86 shuffle node");
3309 case X86ISD::MOVLHPS:
3310 case X86ISD::MOVLHPD:
3311 case X86ISD::MOVHLPS:
3312 case X86ISD::MOVLPS:
3313 case X86ISD::MOVLPD:
3316 case X86ISD::UNPCKL:
3317 case X86ISD::UNPCKH:
3318 return DAG.getNode(Opc, dl, VT, V1, V2);
3322 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3323 MachineFunction &MF = DAG.getMachineFunction();
3324 const X86RegisterInfo *RegInfo =
3325 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3326 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3327 int ReturnAddrIndex = FuncInfo->getRAIndex();
3329 if (ReturnAddrIndex == 0) {
3330 // Set up a frame object for the return address.
3331 unsigned SlotSize = RegInfo->getSlotSize();
3332 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3335 FuncInfo->setRAIndex(ReturnAddrIndex);
3338 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3341 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3342 bool hasSymbolicDisplacement) {
3343 // Offset should fit into 32 bit immediate field.
3344 if (!isInt<32>(Offset))
3347 // If we don't have a symbolic displacement - we don't have any extra
3349 if (!hasSymbolicDisplacement)
3352 // FIXME: Some tweaks might be needed for medium code model.
3353 if (M != CodeModel::Small && M != CodeModel::Kernel)
3356 // For small code model we assume that latest object is 16MB before end of 31
3357 // bits boundary. We may also accept pretty large negative constants knowing
3358 // that all objects are in the positive half of address space.
3359 if (M == CodeModel::Small && Offset < 16*1024*1024)
3362 // For kernel code model we know that all object resist in the negative half
3363 // of 32bits address space. We may not accept negative offsets, since they may
3364 // be just off and we may accept pretty large positive ones.
3365 if (M == CodeModel::Kernel && Offset > 0)
3371 /// isCalleePop - Determines whether the callee is required to pop its
3372 /// own arguments. Callee pop is necessary to support tail calls.
3373 bool X86::isCalleePop(CallingConv::ID CallingConv,
3374 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3378 switch (CallingConv) {
3381 case CallingConv::X86_StdCall:
3383 case CallingConv::X86_FastCall:
3385 case CallingConv::X86_ThisCall:
3387 case CallingConv::Fast:
3389 case CallingConv::GHC:
3391 case CallingConv::HiPE:
3396 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3397 /// specific condition code, returning the condition code and the LHS/RHS of the
3398 /// comparison to make.
3399 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3400 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3402 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3403 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3404 // X > -1 -> X == 0, jump !sign.
3405 RHS = DAG.getConstant(0, RHS.getValueType());
3406 return X86::COND_NS;
3408 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3409 // X < 0 -> X == 0, jump on sign.
3412 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3414 RHS = DAG.getConstant(0, RHS.getValueType());
3415 return X86::COND_LE;
3419 switch (SetCCOpcode) {
3420 default: llvm_unreachable("Invalid integer condition!");
3421 case ISD::SETEQ: return X86::COND_E;
3422 case ISD::SETGT: return X86::COND_G;
3423 case ISD::SETGE: return X86::COND_GE;
3424 case ISD::SETLT: return X86::COND_L;
3425 case ISD::SETLE: return X86::COND_LE;
3426 case ISD::SETNE: return X86::COND_NE;
3427 case ISD::SETULT: return X86::COND_B;
3428 case ISD::SETUGT: return X86::COND_A;
3429 case ISD::SETULE: return X86::COND_BE;
3430 case ISD::SETUGE: return X86::COND_AE;
3434 // First determine if it is required or is profitable to flip the operands.
3436 // If LHS is a foldable load, but RHS is not, flip the condition.
3437 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3438 !ISD::isNON_EXTLoad(RHS.getNode())) {
3439 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3440 std::swap(LHS, RHS);
3443 switch (SetCCOpcode) {
3449 std::swap(LHS, RHS);
3453 // On a floating point condition, the flags are set as follows:
3455 // 0 | 0 | 0 | X > Y
3456 // 0 | 0 | 1 | X < Y
3457 // 1 | 0 | 0 | X == Y
3458 // 1 | 1 | 1 | unordered
3459 switch (SetCCOpcode) {
3460 default: llvm_unreachable("Condcode should be pre-legalized away");
3462 case ISD::SETEQ: return X86::COND_E;
3463 case ISD::SETOLT: // flipped
3465 case ISD::SETGT: return X86::COND_A;
3466 case ISD::SETOLE: // flipped
3468 case ISD::SETGE: return X86::COND_AE;
3469 case ISD::SETUGT: // flipped
3471 case ISD::SETLT: return X86::COND_B;
3472 case ISD::SETUGE: // flipped
3474 case ISD::SETLE: return X86::COND_BE;
3476 case ISD::SETNE: return X86::COND_NE;
3477 case ISD::SETUO: return X86::COND_P;
3478 case ISD::SETO: return X86::COND_NP;
3480 case ISD::SETUNE: return X86::COND_INVALID;
3484 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3485 /// code. Current x86 isa includes the following FP cmov instructions:
3486 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3487 static bool hasFPCMov(unsigned X86CC) {
3503 /// isFPImmLegal - Returns true if the target can instruction select the
3504 /// specified FP immediate natively. If false, the legalizer will
3505 /// materialize the FP immediate as a load from a constant pool.
3506 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3507 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3508 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3514 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3515 /// the specified range (L, H].
3516 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3517 return (Val < 0) || (Val >= Low && Val < Hi);
3520 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3521 /// specified value.
3522 static bool isUndefOrEqual(int Val, int CmpVal) {
3523 return (Val < 0 || Val == CmpVal);
3526 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3527 /// from position Pos and ending in Pos+Size, falls within the specified
3528 /// sequential range (L, L+Pos]. or is undef.
3529 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3530 unsigned Pos, unsigned Size, int Low) {
3531 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3532 if (!isUndefOrEqual(Mask[i], Low))
3537 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3538 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3539 /// the second operand.
3540 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3541 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3542 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3543 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3544 return (Mask[0] < 2 && Mask[1] < 2);
3548 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3549 /// is suitable for input to PSHUFHW.
3550 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3551 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3554 // Lower quadword copied in order or undef.
3555 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3558 // Upper quadword shuffled.
3559 for (unsigned i = 4; i != 8; ++i)
3560 if (!isUndefOrInRange(Mask[i], 4, 8))
3563 if (VT == MVT::v16i16) {
3564 // Lower quadword copied in order or undef.
3565 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3568 // Upper quadword shuffled.
3569 for (unsigned i = 12; i != 16; ++i)
3570 if (!isUndefOrInRange(Mask[i], 12, 16))
3577 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3578 /// is suitable for input to PSHUFLW.
3579 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3580 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3583 // Upper quadword copied in order.
3584 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3587 // Lower quadword shuffled.
3588 for (unsigned i = 0; i != 4; ++i)
3589 if (!isUndefOrInRange(Mask[i], 0, 4))
3592 if (VT == MVT::v16i16) {
3593 // Upper quadword copied in order.
3594 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3597 // Lower quadword shuffled.
3598 for (unsigned i = 8; i != 12; ++i)
3599 if (!isUndefOrInRange(Mask[i], 8, 12))
3606 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3607 /// is suitable for input to PALIGNR.
3608 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3609 const X86Subtarget *Subtarget) {
3610 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3611 (VT.is256BitVector() && !Subtarget->hasInt256()))
3614 unsigned NumElts = VT.getVectorNumElements();
3615 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3616 unsigned NumLaneElts = NumElts/NumLanes;
3618 // Do not handle 64-bit element shuffles with palignr.
3619 if (NumLaneElts == 2)
3622 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3624 for (i = 0; i != NumLaneElts; ++i) {
3629 // Lane is all undef, go to next lane
3630 if (i == NumLaneElts)
3633 int Start = Mask[i+l];
3635 // Make sure its in this lane in one of the sources
3636 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3637 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3640 // If not lane 0, then we must match lane 0
3641 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3644 // Correct second source to be contiguous with first source
3645 if (Start >= (int)NumElts)
3646 Start -= NumElts - NumLaneElts;
3648 // Make sure we're shifting in the right direction.
3649 if (Start <= (int)(i+l))
3654 // Check the rest of the elements to see if they are consecutive.
3655 for (++i; i != NumLaneElts; ++i) {
3656 int Idx = Mask[i+l];
3658 // Make sure its in this lane
3659 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3660 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3663 // If not lane 0, then we must match lane 0
3664 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3667 if (Idx >= (int)NumElts)
3668 Idx -= NumElts - NumLaneElts;
3670 if (!isUndefOrEqual(Idx, Start+i))
3679 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3680 /// the two vector operands have swapped position.
3681 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3682 unsigned NumElems) {
3683 for (unsigned i = 0; i != NumElems; ++i) {
3687 else if (idx < (int)NumElems)
3688 Mask[i] = idx + NumElems;
3690 Mask[i] = idx - NumElems;
3694 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3695 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3696 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3697 /// reverse of what x86 shuffles want.
3698 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3700 unsigned NumElems = VT.getVectorNumElements();
3701 unsigned NumLanes = VT.getSizeInBits()/128;
3702 unsigned NumLaneElems = NumElems/NumLanes;
3704 if (NumLaneElems != 2 && NumLaneElems != 4)
3707 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3708 bool symetricMaskRequired =
3709 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3711 // VSHUFPSY divides the resulting vector into 4 chunks.
3712 // The sources are also splitted into 4 chunks, and each destination
3713 // chunk must come from a different source chunk.
3715 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3716 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3718 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3719 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3721 // VSHUFPDY divides the resulting vector into 4 chunks.
3722 // The sources are also splitted into 4 chunks, and each destination
3723 // chunk must come from a different source chunk.
3725 // SRC1 => X3 X2 X1 X0
3726 // SRC2 => Y3 Y2 Y1 Y0
3728 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3730 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3731 unsigned HalfLaneElems = NumLaneElems/2;
3732 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3733 for (unsigned i = 0; i != NumLaneElems; ++i) {
3734 int Idx = Mask[i+l];
3735 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3736 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3738 // For VSHUFPSY, the mask of the second half must be the same as the
3739 // first but with the appropriate offsets. This works in the same way as
3740 // VPERMILPS works with masks.
3741 if (!symetricMaskRequired || Idx < 0)
3743 if (MaskVal[i] < 0) {
3744 MaskVal[i] = Idx - l;
3747 if ((signed)(Idx - l) != MaskVal[i])
3755 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3756 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3757 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3758 if (!VT.is128BitVector())
3761 unsigned NumElems = VT.getVectorNumElements();
3766 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3767 return isUndefOrEqual(Mask[0], 6) &&
3768 isUndefOrEqual(Mask[1], 7) &&
3769 isUndefOrEqual(Mask[2], 2) &&
3770 isUndefOrEqual(Mask[3], 3);
3773 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3774 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3776 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3777 if (!VT.is128BitVector())
3780 unsigned NumElems = VT.getVectorNumElements();
3785 return isUndefOrEqual(Mask[0], 2) &&
3786 isUndefOrEqual(Mask[1], 3) &&
3787 isUndefOrEqual(Mask[2], 2) &&
3788 isUndefOrEqual(Mask[3], 3);
3791 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3792 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3793 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3794 if (!VT.is128BitVector())
3797 unsigned NumElems = VT.getVectorNumElements();
3799 if (NumElems != 2 && NumElems != 4)
3802 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3803 if (!isUndefOrEqual(Mask[i], i + NumElems))
3806 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3807 if (!isUndefOrEqual(Mask[i], i))
3813 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3814 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3815 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3816 if (!VT.is128BitVector())
3819 unsigned NumElems = VT.getVectorNumElements();
3821 if (NumElems != 2 && NumElems != 4)
3824 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3825 if (!isUndefOrEqual(Mask[i], i))
3828 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3829 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3836 // Some special combinations that can be optimized.
3839 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3840 SelectionDAG &DAG) {
3841 MVT VT = SVOp->getSimpleValueType(0);
3844 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3847 ArrayRef<int> Mask = SVOp->getMask();
3849 // These are the special masks that may be optimized.
3850 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3851 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3852 bool MatchEvenMask = true;
3853 bool MatchOddMask = true;
3854 for (int i=0; i<8; ++i) {
3855 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3856 MatchEvenMask = false;
3857 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3858 MatchOddMask = false;
3861 if (!MatchEvenMask && !MatchOddMask)
3864 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3866 SDValue Op0 = SVOp->getOperand(0);
3867 SDValue Op1 = SVOp->getOperand(1);
3869 if (MatchEvenMask) {
3870 // Shift the second operand right to 32 bits.
3871 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3872 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3874 // Shift the first operand left to 32 bits.
3875 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3876 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3878 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3879 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3882 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3883 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3884 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3885 bool HasInt256, bool V2IsSplat = false) {
3887 assert(VT.getSizeInBits() >= 128 &&
3888 "Unsupported vector type for unpckl");
3890 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3892 unsigned NumOf256BitLanes;
3893 unsigned NumElts = VT.getVectorNumElements();
3894 if (VT.is256BitVector()) {
3895 if (NumElts != 4 && NumElts != 8 &&
3896 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3899 NumOf256BitLanes = 1;
3900 } else if (VT.is512BitVector()) {
3901 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3902 "Unsupported vector type for unpckh");
3904 NumOf256BitLanes = 2;
3907 NumOf256BitLanes = 1;
3910 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3911 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3913 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3914 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3915 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3916 int BitI = Mask[l256*NumEltsInStride+l+i];
3917 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3918 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3920 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3922 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3930 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3931 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3932 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3933 bool HasInt256, bool V2IsSplat = false) {
3934 assert(VT.getSizeInBits() >= 128 &&
3935 "Unsupported vector type for unpckh");
3937 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3939 unsigned NumOf256BitLanes;
3940 unsigned NumElts = VT.getVectorNumElements();
3941 if (VT.is256BitVector()) {
3942 if (NumElts != 4 && NumElts != 8 &&
3943 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3946 NumOf256BitLanes = 1;
3947 } else if (VT.is512BitVector()) {
3948 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3949 "Unsupported vector type for unpckh");
3951 NumOf256BitLanes = 2;
3954 NumOf256BitLanes = 1;
3957 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3958 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3960 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3961 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3962 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3963 int BitI = Mask[l256*NumEltsInStride+l+i];
3964 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3965 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3967 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3969 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3977 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3978 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3980 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3981 unsigned NumElts = VT.getVectorNumElements();
3982 bool Is256BitVec = VT.is256BitVector();
3984 if (VT.is512BitVector())
3986 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3987 "Unsupported vector type for unpckh");
3989 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3990 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3993 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3994 // FIXME: Need a better way to get rid of this, there's no latency difference
3995 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3996 // the former later. We should also remove the "_undef" special mask.
3997 if (NumElts == 4 && Is256BitVec)
4000 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4001 // independently on 128-bit lanes.
4002 unsigned NumLanes = VT.getSizeInBits()/128;
4003 unsigned NumLaneElts = NumElts/NumLanes;
4005 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4006 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4007 int BitI = Mask[l+i];
4008 int BitI1 = Mask[l+i+1];
4010 if (!isUndefOrEqual(BitI, j))
4012 if (!isUndefOrEqual(BitI1, j))
4020 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4021 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4023 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4024 unsigned NumElts = VT.getVectorNumElements();
4026 if (VT.is512BitVector())
4029 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4030 "Unsupported vector type for unpckh");
4032 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4033 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4036 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4037 // independently on 128-bit lanes.
4038 unsigned NumLanes = VT.getSizeInBits()/128;
4039 unsigned NumLaneElts = NumElts/NumLanes;
4041 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4042 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4043 int BitI = Mask[l+i];
4044 int BitI1 = Mask[l+i+1];
4045 if (!isUndefOrEqual(BitI, j))
4047 if (!isUndefOrEqual(BitI1, j))
4054 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4055 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4056 /// MOVSD, and MOVD, i.e. setting the lowest element.
4057 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4058 if (VT.getVectorElementType().getSizeInBits() < 32)
4060 if (!VT.is128BitVector())
4063 unsigned NumElts = VT.getVectorNumElements();
4065 if (!isUndefOrEqual(Mask[0], NumElts))
4068 for (unsigned i = 1; i != NumElts; ++i)
4069 if (!isUndefOrEqual(Mask[i], i))
4075 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4076 /// as permutations between 128-bit chunks or halves. As an example: this
4078 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4079 /// The first half comes from the second half of V1 and the second half from the
4080 /// the second half of V2.
4081 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4082 if (!HasFp256 || !VT.is256BitVector())
4085 // The shuffle result is divided into half A and half B. In total the two
4086 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4087 // B must come from C, D, E or F.
4088 unsigned HalfSize = VT.getVectorNumElements()/2;
4089 bool MatchA = false, MatchB = false;
4091 // Check if A comes from one of C, D, E, F.
4092 for (unsigned Half = 0; Half != 4; ++Half) {
4093 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4099 // Check if B comes from one of C, D, E, F.
4100 for (unsigned Half = 0; Half != 4; ++Half) {
4101 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4107 return MatchA && MatchB;
4110 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4111 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4112 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4113 MVT VT = SVOp->getSimpleValueType(0);
4115 unsigned HalfSize = VT.getVectorNumElements()/2;
4117 unsigned FstHalf = 0, SndHalf = 0;
4118 for (unsigned i = 0; i < HalfSize; ++i) {
4119 if (SVOp->getMaskElt(i) > 0) {
4120 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4124 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4125 if (SVOp->getMaskElt(i) > 0) {
4126 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4131 return (FstHalf | (SndHalf << 4));
4134 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4135 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4136 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4140 unsigned NumElts = VT.getVectorNumElements();
4142 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4143 for (unsigned i = 0; i != NumElts; ++i) {
4146 Imm8 |= Mask[i] << (i*2);
4151 unsigned LaneSize = 4;
4152 SmallVector<int, 4> MaskVal(LaneSize, -1);
4154 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4155 for (unsigned i = 0; i != LaneSize; ++i) {
4156 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4160 if (MaskVal[i] < 0) {
4161 MaskVal[i] = Mask[i+l] - l;
4162 Imm8 |= MaskVal[i] << (i*2);
4165 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4172 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4173 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4174 /// Note that VPERMIL mask matching is different depending whether theunderlying
4175 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4176 /// to the same elements of the low, but to the higher half of the source.
4177 /// In VPERMILPD the two lanes could be shuffled independently of each other
4178 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4179 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4180 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4181 if (VT.getSizeInBits() < 256 || EltSize < 32)
4183 bool symetricMaskRequired = (EltSize == 32);
4184 unsigned NumElts = VT.getVectorNumElements();
4186 unsigned NumLanes = VT.getSizeInBits()/128;
4187 unsigned LaneSize = NumElts/NumLanes;
4188 // 2 or 4 elements in one lane
4190 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4191 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4192 for (unsigned i = 0; i != LaneSize; ++i) {
4193 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4195 if (symetricMaskRequired) {
4196 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4197 ExpectedMaskVal[i] = Mask[i+l] - l;
4200 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4208 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4209 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4210 /// element of vector 2 and the other elements to come from vector 1 in order.
4211 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4212 bool V2IsSplat = false, bool V2IsUndef = false) {
4213 if (!VT.is128BitVector())
4216 unsigned NumOps = VT.getVectorNumElements();
4217 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4220 if (!isUndefOrEqual(Mask[0], 0))
4223 for (unsigned i = 1; i != NumOps; ++i)
4224 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4225 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4226 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4232 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4233 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4234 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4235 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4236 const X86Subtarget *Subtarget) {
4237 if (!Subtarget->hasSSE3())
4240 unsigned NumElems = VT.getVectorNumElements();
4242 if ((VT.is128BitVector() && NumElems != 4) ||
4243 (VT.is256BitVector() && NumElems != 8) ||
4244 (VT.is512BitVector() && NumElems != 16))
4247 // "i+1" is the value the indexed mask element must have
4248 for (unsigned i = 0; i != NumElems; i += 2)
4249 if (!isUndefOrEqual(Mask[i], i+1) ||
4250 !isUndefOrEqual(Mask[i+1], i+1))
4256 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4257 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4258 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4259 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4260 const X86Subtarget *Subtarget) {
4261 if (!Subtarget->hasSSE3())
4264 unsigned NumElems = VT.getVectorNumElements();
4266 if ((VT.is128BitVector() && NumElems != 4) ||
4267 (VT.is256BitVector() && NumElems != 8) ||
4268 (VT.is512BitVector() && NumElems != 16))
4271 // "i" is the value the indexed mask element must have
4272 for (unsigned i = 0; i != NumElems; i += 2)
4273 if (!isUndefOrEqual(Mask[i], i) ||
4274 !isUndefOrEqual(Mask[i+1], i))
4280 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4281 /// specifies a shuffle of elements that is suitable for input to 256-bit
4282 /// version of MOVDDUP.
4283 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4284 if (!HasFp256 || !VT.is256BitVector())
4287 unsigned NumElts = VT.getVectorNumElements();
4291 for (unsigned i = 0; i != NumElts/2; ++i)
4292 if (!isUndefOrEqual(Mask[i], 0))
4294 for (unsigned i = NumElts/2; i != NumElts; ++i)
4295 if (!isUndefOrEqual(Mask[i], NumElts/2))
4300 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4301 /// specifies a shuffle of elements that is suitable for input to 128-bit
4302 /// version of MOVDDUP.
4303 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4304 if (!VT.is128BitVector())
4307 unsigned e = VT.getVectorNumElements() / 2;
4308 for (unsigned i = 0; i != e; ++i)
4309 if (!isUndefOrEqual(Mask[i], i))
4311 for (unsigned i = 0; i != e; ++i)
4312 if (!isUndefOrEqual(Mask[e+i], i))
4317 /// isVEXTRACTIndex - Return true if the specified
4318 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4319 /// suitable for instruction that extract 128 or 256 bit vectors
4320 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4321 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4322 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4325 // The index should be aligned on a vecWidth-bit boundary.
4327 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4329 MVT VT = N->getSimpleValueType(0);
4330 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4331 bool Result = (Index * ElSize) % vecWidth == 0;
4336 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4337 /// operand specifies a subvector insert that is suitable for input to
4338 /// insertion of 128 or 256-bit subvectors
4339 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4340 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4341 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4343 // The index should be aligned on a vecWidth-bit boundary.
4345 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4347 MVT VT = N->getSimpleValueType(0);
4348 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4349 bool Result = (Index * ElSize) % vecWidth == 0;
4354 bool X86::isVINSERT128Index(SDNode *N) {
4355 return isVINSERTIndex(N, 128);
4358 bool X86::isVINSERT256Index(SDNode *N) {
4359 return isVINSERTIndex(N, 256);
4362 bool X86::isVEXTRACT128Index(SDNode *N) {
4363 return isVEXTRACTIndex(N, 128);
4366 bool X86::isVEXTRACT256Index(SDNode *N) {
4367 return isVEXTRACTIndex(N, 256);
4370 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4371 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4372 /// Handles 128-bit and 256-bit.
4373 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4374 MVT VT = N->getSimpleValueType(0);
4376 assert((VT.getSizeInBits() >= 128) &&
4377 "Unsupported vector type for PSHUF/SHUFP");
4379 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4380 // independently on 128-bit lanes.
4381 unsigned NumElts = VT.getVectorNumElements();
4382 unsigned NumLanes = VT.getSizeInBits()/128;
4383 unsigned NumLaneElts = NumElts/NumLanes;
4385 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4386 "Only supports 2, 4 or 8 elements per lane");
4388 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4390 for (unsigned i = 0; i != NumElts; ++i) {
4391 int Elt = N->getMaskElt(i);
4392 if (Elt < 0) continue;
4393 Elt &= NumLaneElts - 1;
4394 unsigned ShAmt = (i << Shift) % 8;
4395 Mask |= Elt << ShAmt;
4401 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4402 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4403 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4404 MVT VT = N->getSimpleValueType(0);
4406 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4407 "Unsupported vector type for PSHUFHW");
4409 unsigned NumElts = VT.getVectorNumElements();
4412 for (unsigned l = 0; l != NumElts; l += 8) {
4413 // 8 nodes per lane, but we only care about the last 4.
4414 for (unsigned i = 0; i < 4; ++i) {
4415 int Elt = N->getMaskElt(l+i+4);
4416 if (Elt < 0) continue;
4417 Elt &= 0x3; // only 2-bits.
4418 Mask |= Elt << (i * 2);
4425 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4426 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4427 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4428 MVT VT = N->getSimpleValueType(0);
4430 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4431 "Unsupported vector type for PSHUFHW");
4433 unsigned NumElts = VT.getVectorNumElements();
4436 for (unsigned l = 0; l != NumElts; l += 8) {
4437 // 8 nodes per lane, but we only care about the first 4.
4438 for (unsigned i = 0; i < 4; ++i) {
4439 int Elt = N->getMaskElt(l+i);
4440 if (Elt < 0) continue;
4441 Elt &= 0x3; // only 2-bits
4442 Mask |= Elt << (i * 2);
4449 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4450 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4451 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4452 MVT VT = SVOp->getSimpleValueType(0);
4453 unsigned EltSize = VT.is512BitVector() ? 1 :
4454 VT.getVectorElementType().getSizeInBits() >> 3;
4456 unsigned NumElts = VT.getVectorNumElements();
4457 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4458 unsigned NumLaneElts = NumElts/NumLanes;
4462 for (i = 0; i != NumElts; ++i) {
4463 Val = SVOp->getMaskElt(i);
4467 if (Val >= (int)NumElts)
4468 Val -= NumElts - NumLaneElts;
4470 assert(Val - i > 0 && "PALIGNR imm should be positive");
4471 return (Val - i) * EltSize;
4474 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4475 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4476 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4477 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4480 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4482 MVT VecVT = N->getOperand(0).getSimpleValueType();
4483 MVT ElVT = VecVT.getVectorElementType();
4485 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4486 return Index / NumElemsPerChunk;
4489 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4490 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4491 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4492 llvm_unreachable("Illegal insert subvector for VINSERT");
4495 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4497 MVT VecVT = N->getSimpleValueType(0);
4498 MVT ElVT = VecVT.getVectorElementType();
4500 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4501 return Index / NumElemsPerChunk;
4504 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4505 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4506 /// and VINSERTI128 instructions.
4507 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4508 return getExtractVEXTRACTImmediate(N, 128);
4511 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4512 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4513 /// and VINSERTI64x4 instructions.
4514 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4515 return getExtractVEXTRACTImmediate(N, 256);
4518 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4519 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4520 /// and VINSERTI128 instructions.
4521 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4522 return getInsertVINSERTImmediate(N, 128);
4525 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4526 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4527 /// and VINSERTI64x4 instructions.
4528 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4529 return getInsertVINSERTImmediate(N, 256);
4532 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4534 bool X86::isZeroNode(SDValue Elt) {
4535 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4536 return CN->isNullValue();
4537 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4538 return CFP->getValueAPF().isPosZero();
4542 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4543 /// their permute mask.
4544 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4545 SelectionDAG &DAG) {
4546 MVT VT = SVOp->getSimpleValueType(0);
4547 unsigned NumElems = VT.getVectorNumElements();
4548 SmallVector<int, 8> MaskVec;
4550 for (unsigned i = 0; i != NumElems; ++i) {
4551 int Idx = SVOp->getMaskElt(i);
4553 if (Idx < (int)NumElems)
4558 MaskVec.push_back(Idx);
4560 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4561 SVOp->getOperand(0), &MaskVec[0]);
4564 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4565 /// match movhlps. The lower half elements should come from upper half of
4566 /// V1 (and in order), and the upper half elements should come from the upper
4567 /// half of V2 (and in order).
4568 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4569 if (!VT.is128BitVector())
4571 if (VT.getVectorNumElements() != 4)
4573 for (unsigned i = 0, e = 2; i != e; ++i)
4574 if (!isUndefOrEqual(Mask[i], i+2))
4576 for (unsigned i = 2; i != 4; ++i)
4577 if (!isUndefOrEqual(Mask[i], i+4))
4582 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4583 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4585 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4586 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4588 N = N->getOperand(0).getNode();
4589 if (!ISD::isNON_EXTLoad(N))
4592 *LD = cast<LoadSDNode>(N);
4596 // Test whether the given value is a vector value which will be legalized
4598 static bool WillBeConstantPoolLoad(SDNode *N) {
4599 if (N->getOpcode() != ISD::BUILD_VECTOR)
4602 // Check for any non-constant elements.
4603 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4604 switch (N->getOperand(i).getNode()->getOpcode()) {
4606 case ISD::ConstantFP:
4613 // Vectors of all-zeros and all-ones are materialized with special
4614 // instructions rather than being loaded.
4615 return !ISD::isBuildVectorAllZeros(N) &&
4616 !ISD::isBuildVectorAllOnes(N);
4619 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4620 /// match movlp{s|d}. The lower half elements should come from lower half of
4621 /// V1 (and in order), and the upper half elements should come from the upper
4622 /// half of V2 (and in order). And since V1 will become the source of the
4623 /// MOVLP, it must be either a vector load or a scalar load to vector.
4624 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4625 ArrayRef<int> Mask, MVT VT) {
4626 if (!VT.is128BitVector())
4629 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4631 // Is V2 is a vector load, don't do this transformation. We will try to use
4632 // load folding shufps op.
4633 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4636 unsigned NumElems = VT.getVectorNumElements();
4638 if (NumElems != 2 && NumElems != 4)
4640 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4641 if (!isUndefOrEqual(Mask[i], i))
4643 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4644 if (!isUndefOrEqual(Mask[i], i+NumElems))
4649 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4651 static bool isSplatVector(SDNode *N) {
4652 if (N->getOpcode() != ISD::BUILD_VECTOR)
4655 SDValue SplatValue = N->getOperand(0);
4656 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4657 if (N->getOperand(i) != SplatValue)
4662 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4663 /// to an zero vector.
4664 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4665 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4666 SDValue V1 = N->getOperand(0);
4667 SDValue V2 = N->getOperand(1);
4668 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4669 for (unsigned i = 0; i != NumElems; ++i) {
4670 int Idx = N->getMaskElt(i);
4671 if (Idx >= (int)NumElems) {
4672 unsigned Opc = V2.getOpcode();
4673 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4675 if (Opc != ISD::BUILD_VECTOR ||
4676 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4678 } else if (Idx >= 0) {
4679 unsigned Opc = V1.getOpcode();
4680 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4682 if (Opc != ISD::BUILD_VECTOR ||
4683 !X86::isZeroNode(V1.getOperand(Idx)))
4690 /// getZeroVector - Returns a vector of specified type with all zero elements.
4692 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4693 SelectionDAG &DAG, SDLoc dl) {
4694 assert(VT.isVector() && "Expected a vector type");
4696 // Always build SSE zero vectors as <4 x i32> bitcasted
4697 // to their dest type. This ensures they get CSE'd.
4699 if (VT.is128BitVector()) { // SSE
4700 if (Subtarget->hasSSE2()) { // SSE2
4701 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4702 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4704 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4705 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4707 } else if (VT.is256BitVector()) { // AVX
4708 if (Subtarget->hasInt256()) { // AVX2
4709 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4710 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4711 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4712 array_lengthof(Ops));
4714 // 256-bit logic and arithmetic instructions in AVX are all
4715 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4716 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4717 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4718 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4719 array_lengthof(Ops));
4721 } else if (VT.is512BitVector()) { // AVX-512
4722 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4723 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4724 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4725 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4727 llvm_unreachable("Unexpected vector type");
4729 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4732 /// getOnesVector - Returns a vector of specified type with all bits set.
4733 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4734 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4735 /// Then bitcast to their original type, ensuring they get CSE'd.
4736 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4738 assert(VT.isVector() && "Expected a vector type");
4740 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4742 if (VT.is256BitVector()) {
4743 if (HasInt256) { // AVX2
4744 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4745 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4746 array_lengthof(Ops));
4748 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4749 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4751 } else if (VT.is128BitVector()) {
4752 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4754 llvm_unreachable("Unexpected vector type");
4756 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4759 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4760 /// that point to V2 points to its first element.
4761 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4762 for (unsigned i = 0; i != NumElems; ++i) {
4763 if (Mask[i] > (int)NumElems) {
4769 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4770 /// operation of specified width.
4771 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4773 unsigned NumElems = VT.getVectorNumElements();
4774 SmallVector<int, 8> Mask;
4775 Mask.push_back(NumElems);
4776 for (unsigned i = 1; i != NumElems; ++i)
4778 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4781 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4782 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4784 unsigned NumElems = VT.getVectorNumElements();
4785 SmallVector<int, 8> Mask;
4786 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4788 Mask.push_back(i + NumElems);
4790 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4793 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4794 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4796 unsigned NumElems = VT.getVectorNumElements();
4797 SmallVector<int, 8> Mask;
4798 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4799 Mask.push_back(i + Half);
4800 Mask.push_back(i + NumElems + Half);
4802 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4805 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4806 // a generic shuffle instruction because the target has no such instructions.
4807 // Generate shuffles which repeat i16 and i8 several times until they can be
4808 // represented by v4f32 and then be manipulated by target suported shuffles.
4809 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4810 MVT VT = V.getSimpleValueType();
4811 int NumElems = VT.getVectorNumElements();
4814 while (NumElems > 4) {
4815 if (EltNo < NumElems/2) {
4816 V = getUnpackl(DAG, dl, VT, V, V);
4818 V = getUnpackh(DAG, dl, VT, V, V);
4819 EltNo -= NumElems/2;
4826 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4827 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4828 MVT VT = V.getSimpleValueType();
4831 if (VT.is128BitVector()) {
4832 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4833 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4834 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4836 } else if (VT.is256BitVector()) {
4837 // To use VPERMILPS to splat scalars, the second half of indicies must
4838 // refer to the higher part, which is a duplication of the lower one,
4839 // because VPERMILPS can only handle in-lane permutations.
4840 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4841 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4843 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4844 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4847 llvm_unreachable("Vector size not supported");
4849 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4852 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4853 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4854 MVT SrcVT = SV->getSimpleValueType(0);
4855 SDValue V1 = SV->getOperand(0);
4858 int EltNo = SV->getSplatIndex();
4859 int NumElems = SrcVT.getVectorNumElements();
4860 bool Is256BitVec = SrcVT.is256BitVector();
4862 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4863 "Unknown how to promote splat for type");
4865 // Extract the 128-bit part containing the splat element and update
4866 // the splat element index when it refers to the higher register.
4868 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4869 if (EltNo >= NumElems/2)
4870 EltNo -= NumElems/2;
4873 // All i16 and i8 vector types can't be used directly by a generic shuffle
4874 // instruction because the target has no such instruction. Generate shuffles
4875 // which repeat i16 and i8 several times until they fit in i32, and then can
4876 // be manipulated by target suported shuffles.
4877 MVT EltVT = SrcVT.getVectorElementType();
4878 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4879 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4881 // Recreate the 256-bit vector and place the same 128-bit vector
4882 // into the low and high part. This is necessary because we want
4883 // to use VPERM* to shuffle the vectors
4885 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4888 return getLegalSplat(DAG, V1, EltNo);
4891 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4892 /// vector of zero or undef vector. This produces a shuffle where the low
4893 /// element of V2 is swizzled into the zero/undef vector, landing at element
4894 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4895 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4897 const X86Subtarget *Subtarget,
4898 SelectionDAG &DAG) {
4899 MVT VT = V2.getSimpleValueType();
4901 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4902 unsigned NumElems = VT.getVectorNumElements();
4903 SmallVector<int, 16> MaskVec;
4904 for (unsigned i = 0; i != NumElems; ++i)
4905 // If this is the insertion idx, put the low elt of V2 here.
4906 MaskVec.push_back(i == Idx ? NumElems : i);
4907 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4910 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4911 /// target specific opcode. Returns true if the Mask could be calculated.
4912 /// Sets IsUnary to true if only uses one source.
4913 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4914 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4915 unsigned NumElems = VT.getVectorNumElements();
4919 switch(N->getOpcode()) {
4921 ImmN = N->getOperand(N->getNumOperands()-1);
4922 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4924 case X86ISD::UNPCKH:
4925 DecodeUNPCKHMask(VT, Mask);
4927 case X86ISD::UNPCKL:
4928 DecodeUNPCKLMask(VT, Mask);
4930 case X86ISD::MOVHLPS:
4931 DecodeMOVHLPSMask(NumElems, Mask);
4933 case X86ISD::MOVLHPS:
4934 DecodeMOVLHPSMask(NumElems, Mask);
4936 case X86ISD::PALIGNR:
4937 ImmN = N->getOperand(N->getNumOperands()-1);
4938 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4940 case X86ISD::PSHUFD:
4941 case X86ISD::VPERMILP:
4942 ImmN = N->getOperand(N->getNumOperands()-1);
4943 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4946 case X86ISD::PSHUFHW:
4947 ImmN = N->getOperand(N->getNumOperands()-1);
4948 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4951 case X86ISD::PSHUFLW:
4952 ImmN = N->getOperand(N->getNumOperands()-1);
4953 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4956 case X86ISD::VPERMI:
4957 ImmN = N->getOperand(N->getNumOperands()-1);
4958 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4962 case X86ISD::MOVSD: {
4963 // The index 0 always comes from the first element of the second source,
4964 // this is why MOVSS and MOVSD are used in the first place. The other
4965 // elements come from the other positions of the first source vector
4966 Mask.push_back(NumElems);
4967 for (unsigned i = 1; i != NumElems; ++i) {
4972 case X86ISD::VPERM2X128:
4973 ImmN = N->getOperand(N->getNumOperands()-1);
4974 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4975 if (Mask.empty()) return false;
4977 case X86ISD::MOVDDUP:
4978 case X86ISD::MOVLHPD:
4979 case X86ISD::MOVLPD:
4980 case X86ISD::MOVLPS:
4981 case X86ISD::MOVSHDUP:
4982 case X86ISD::MOVSLDUP:
4983 // Not yet implemented
4985 default: llvm_unreachable("unknown target shuffle node");
4991 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4992 /// element of the result of the vector shuffle.
4993 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4996 return SDValue(); // Limit search depth.
4998 SDValue V = SDValue(N, 0);
4999 EVT VT = V.getValueType();
5000 unsigned Opcode = V.getOpcode();
5002 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5003 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5004 int Elt = SV->getMaskElt(Index);
5007 return DAG.getUNDEF(VT.getVectorElementType());
5009 unsigned NumElems = VT.getVectorNumElements();
5010 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5011 : SV->getOperand(1);
5012 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5015 // Recurse into target specific vector shuffles to find scalars.
5016 if (isTargetShuffle(Opcode)) {
5017 MVT ShufVT = V.getSimpleValueType();
5018 unsigned NumElems = ShufVT.getVectorNumElements();
5019 SmallVector<int, 16> ShuffleMask;
5022 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5025 int Elt = ShuffleMask[Index];
5027 return DAG.getUNDEF(ShufVT.getVectorElementType());
5029 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5031 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5035 // Actual nodes that may contain scalar elements
5036 if (Opcode == ISD::BITCAST) {
5037 V = V.getOperand(0);
5038 EVT SrcVT = V.getValueType();
5039 unsigned NumElems = VT.getVectorNumElements();
5041 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5045 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5046 return (Index == 0) ? V.getOperand(0)
5047 : DAG.getUNDEF(VT.getVectorElementType());
5049 if (V.getOpcode() == ISD::BUILD_VECTOR)
5050 return V.getOperand(Index);
5055 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5056 /// shuffle operation which come from a consecutively from a zero. The
5057 /// search can start in two different directions, from left or right.
5058 /// We count undefs as zeros until PreferredNum is reached.
5059 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5060 unsigned NumElems, bool ZerosFromLeft,
5062 unsigned PreferredNum = -1U) {
5063 unsigned NumZeros = 0;
5064 for (unsigned i = 0; i != NumElems; ++i) {
5065 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5066 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5070 if (X86::isZeroNode(Elt))
5072 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5073 NumZeros = std::min(NumZeros + 1, PreferredNum);
5081 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5082 /// correspond consecutively to elements from one of the vector operands,
5083 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5085 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5086 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5087 unsigned NumElems, unsigned &OpNum) {
5088 bool SeenV1 = false;
5089 bool SeenV2 = false;
5091 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5092 int Idx = SVOp->getMaskElt(i);
5093 // Ignore undef indicies
5097 if (Idx < (int)NumElems)
5102 // Only accept consecutive elements from the same vector
5103 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5107 OpNum = SeenV1 ? 0 : 1;
5111 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5112 /// logical left shift of a vector.
5113 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5114 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5116 SVOp->getSimpleValueType(0).getVectorNumElements();
5117 unsigned NumZeros = getNumOfConsecutiveZeros(
5118 SVOp, NumElems, false /* check zeros from right */, DAG,
5119 SVOp->getMaskElt(0));
5125 // Considering the elements in the mask that are not consecutive zeros,
5126 // check if they consecutively come from only one of the source vectors.
5128 // V1 = {X, A, B, C} 0
5130 // vector_shuffle V1, V2 <1, 2, 3, X>
5132 if (!isShuffleMaskConsecutive(SVOp,
5133 0, // Mask Start Index
5134 NumElems-NumZeros, // Mask End Index(exclusive)
5135 NumZeros, // Where to start looking in the src vector
5136 NumElems, // Number of elements in vector
5137 OpSrc)) // Which source operand ?
5142 ShVal = SVOp->getOperand(OpSrc);
5146 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5147 /// logical left shift of a vector.
5148 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5149 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5151 SVOp->getSimpleValueType(0).getVectorNumElements();
5152 unsigned NumZeros = getNumOfConsecutiveZeros(
5153 SVOp, NumElems, true /* check zeros from left */, DAG,
5154 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5160 // Considering the elements in the mask that are not consecutive zeros,
5161 // check if they consecutively come from only one of the source vectors.
5163 // 0 { A, B, X, X } = V2
5165 // vector_shuffle V1, V2 <X, X, 4, 5>
5167 if (!isShuffleMaskConsecutive(SVOp,
5168 NumZeros, // Mask Start Index
5169 NumElems, // Mask End Index(exclusive)
5170 0, // Where to start looking in the src vector
5171 NumElems, // Number of elements in vector
5172 OpSrc)) // Which source operand ?
5177 ShVal = SVOp->getOperand(OpSrc);
5181 /// isVectorShift - Returns true if the shuffle can be implemented as a
5182 /// logical left or right shift of a vector.
5183 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5184 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5185 // Although the logic below support any bitwidth size, there are no
5186 // shift instructions which handle more than 128-bit vectors.
5187 if (!SVOp->getSimpleValueType(0).is128BitVector())
5190 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5191 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5197 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5199 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5200 unsigned NumNonZero, unsigned NumZero,
5202 const X86Subtarget* Subtarget,
5203 const TargetLowering &TLI) {
5210 for (unsigned i = 0; i < 16; ++i) {
5211 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5212 if (ThisIsNonZero && First) {
5214 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5216 V = DAG.getUNDEF(MVT::v8i16);
5221 SDValue ThisElt(0, 0), LastElt(0, 0);
5222 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5223 if (LastIsNonZero) {
5224 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5225 MVT::i16, Op.getOperand(i-1));
5227 if (ThisIsNonZero) {
5228 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5229 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5230 ThisElt, DAG.getConstant(8, MVT::i8));
5232 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5236 if (ThisElt.getNode())
5237 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5238 DAG.getIntPtrConstant(i/2));
5242 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5245 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5247 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5248 unsigned NumNonZero, unsigned NumZero,
5250 const X86Subtarget* Subtarget,
5251 const TargetLowering &TLI) {
5258 for (unsigned i = 0; i < 8; ++i) {
5259 bool isNonZero = (NonZeros & (1 << i)) != 0;
5263 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5265 V = DAG.getUNDEF(MVT::v8i16);
5268 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5269 MVT::v8i16, V, Op.getOperand(i),
5270 DAG.getIntPtrConstant(i));
5277 /// getVShift - Return a vector logical shift node.
5279 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5280 unsigned NumBits, SelectionDAG &DAG,
5281 const TargetLowering &TLI, SDLoc dl) {
5282 assert(VT.is128BitVector() && "Unknown type for VShift");
5283 EVT ShVT = MVT::v2i64;
5284 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5285 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5286 return DAG.getNode(ISD::BITCAST, dl, VT,
5287 DAG.getNode(Opc, dl, ShVT, SrcOp,
5288 DAG.getConstant(NumBits,
5289 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5293 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5295 // Check if the scalar load can be widened into a vector load. And if
5296 // the address is "base + cst" see if the cst can be "absorbed" into
5297 // the shuffle mask.
5298 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5299 SDValue Ptr = LD->getBasePtr();
5300 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5302 EVT PVT = LD->getValueType(0);
5303 if (PVT != MVT::i32 && PVT != MVT::f32)
5308 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5309 FI = FINode->getIndex();
5311 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5312 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5313 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5314 Offset = Ptr.getConstantOperandVal(1);
5315 Ptr = Ptr.getOperand(0);
5320 // FIXME: 256-bit vector instructions don't require a strict alignment,
5321 // improve this code to support it better.
5322 unsigned RequiredAlign = VT.getSizeInBits()/8;
5323 SDValue Chain = LD->getChain();
5324 // Make sure the stack object alignment is at least 16 or 32.
5325 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5326 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5327 if (MFI->isFixedObjectIndex(FI)) {
5328 // Can't change the alignment. FIXME: It's possible to compute
5329 // the exact stack offset and reference FI + adjust offset instead.
5330 // If someone *really* cares about this. That's the way to implement it.
5333 MFI->setObjectAlignment(FI, RequiredAlign);
5337 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5338 // Ptr + (Offset & ~15).
5341 if ((Offset % RequiredAlign) & 3)
5343 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5345 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5346 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5348 int EltNo = (Offset - StartOffset) >> 2;
5349 unsigned NumElems = VT.getVectorNumElements();
5351 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5352 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5353 LD->getPointerInfo().getWithOffset(StartOffset),
5354 false, false, false, 0);
5356 SmallVector<int, 8> Mask;
5357 for (unsigned i = 0; i != NumElems; ++i)
5358 Mask.push_back(EltNo);
5360 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5366 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5367 /// vector of type 'VT', see if the elements can be replaced by a single large
5368 /// load which has the same value as a build_vector whose operands are 'elts'.
5370 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5372 /// FIXME: we'd also like to handle the case where the last elements are zero
5373 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5374 /// There's even a handy isZeroNode for that purpose.
5375 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5376 SDLoc &DL, SelectionDAG &DAG) {
5377 EVT EltVT = VT.getVectorElementType();
5378 unsigned NumElems = Elts.size();
5380 LoadSDNode *LDBase = NULL;
5381 unsigned LastLoadedElt = -1U;
5383 // For each element in the initializer, see if we've found a load or an undef.
5384 // If we don't find an initial load element, or later load elements are
5385 // non-consecutive, bail out.
5386 for (unsigned i = 0; i < NumElems; ++i) {
5387 SDValue Elt = Elts[i];
5389 if (!Elt.getNode() ||
5390 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5393 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5395 LDBase = cast<LoadSDNode>(Elt.getNode());
5399 if (Elt.getOpcode() == ISD::UNDEF)
5402 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5403 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5408 // If we have found an entire vector of loads and undefs, then return a large
5409 // load of the entire vector width starting at the base pointer. If we found
5410 // consecutive loads for the low half, generate a vzext_load node.
5411 if (LastLoadedElt == NumElems - 1) {
5412 SDValue NewLd = SDValue();
5413 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5414 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5415 LDBase->getPointerInfo(),
5416 LDBase->isVolatile(), LDBase->isNonTemporal(),
5417 LDBase->isInvariant(), 0);
5418 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5419 LDBase->getPointerInfo(),
5420 LDBase->isVolatile(), LDBase->isNonTemporal(),
5421 LDBase->isInvariant(), LDBase->getAlignment());
5423 if (LDBase->hasAnyUseOfValue(1)) {
5424 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5426 SDValue(NewLd.getNode(), 1));
5427 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5428 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5429 SDValue(NewLd.getNode(), 1));
5434 if (NumElems == 4 && LastLoadedElt == 1 &&
5435 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5436 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5437 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5439 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5440 array_lengthof(Ops), MVT::i64,
5441 LDBase->getPointerInfo(),
5442 LDBase->getAlignment(),
5443 false/*isVolatile*/, true/*ReadMem*/,
5446 // Make sure the newly-created LOAD is in the same position as LDBase in
5447 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5448 // update uses of LDBase's output chain to use the TokenFactor.
5449 if (LDBase->hasAnyUseOfValue(1)) {
5450 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5451 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5452 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5453 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5454 SDValue(ResNode.getNode(), 1));
5457 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5462 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5463 /// to generate a splat value for the following cases:
5464 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5465 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5466 /// a scalar load, or a constant.
5467 /// The VBROADCAST node is returned when a pattern is found,
5468 /// or SDValue() otherwise.
5469 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5470 SelectionDAG &DAG) {
5471 if (!Subtarget->hasFp256())
5474 MVT VT = Op.getSimpleValueType();
5477 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5478 "Unsupported vector type for broadcast.");
5483 switch (Op.getOpcode()) {
5485 // Unknown pattern found.
5488 case ISD::BUILD_VECTOR: {
5489 // The BUILD_VECTOR node must be a splat.
5490 if (!isSplatVector(Op.getNode()))
5493 Ld = Op.getOperand(0);
5494 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5495 Ld.getOpcode() == ISD::ConstantFP);
5497 // The suspected load node has several users. Make sure that all
5498 // of its users are from the BUILD_VECTOR node.
5499 // Constants may have multiple users.
5500 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5505 case ISD::VECTOR_SHUFFLE: {
5506 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5508 // Shuffles must have a splat mask where the first element is
5510 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5513 SDValue Sc = Op.getOperand(0);
5514 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5515 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5517 if (!Subtarget->hasInt256())
5520 // Use the register form of the broadcast instruction available on AVX2.
5521 if (VT.getSizeInBits() >= 256)
5522 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5523 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5526 Ld = Sc.getOperand(0);
5527 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5528 Ld.getOpcode() == ISD::ConstantFP);
5530 // The scalar_to_vector node and the suspected
5531 // load node must have exactly one user.
5532 // Constants may have multiple users.
5534 // AVX-512 has register version of the broadcast
5535 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5536 Ld.getValueType().getSizeInBits() >= 32;
5537 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5544 bool IsGE256 = (VT.getSizeInBits() >= 256);
5546 // Handle the broadcasting a single constant scalar from the constant pool
5547 // into a vector. On Sandybridge it is still better to load a constant vector
5548 // from the constant pool and not to broadcast it from a scalar.
5549 if (ConstSplatVal && Subtarget->hasInt256()) {
5550 EVT CVT = Ld.getValueType();
5551 assert(!CVT.isVector() && "Must not broadcast a vector type");
5552 unsigned ScalarSize = CVT.getSizeInBits();
5554 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5555 const Constant *C = 0;
5556 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5557 C = CI->getConstantIntValue();
5558 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5559 C = CF->getConstantFPValue();
5561 assert(C && "Invalid constant type");
5563 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5564 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5565 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5566 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5567 MachinePointerInfo::getConstantPool(),
5568 false, false, false, Alignment);
5570 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5574 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5575 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5577 // Handle AVX2 in-register broadcasts.
5578 if (!IsLoad && Subtarget->hasInt256() &&
5579 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5580 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5582 // The scalar source must be a normal load.
5586 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5587 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5589 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5590 // double since there is no vbroadcastsd xmm
5591 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5592 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5593 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5596 // Unsupported broadcast.
5600 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5601 MVT VT = Op.getSimpleValueType();
5603 // Skip if insert_vec_elt is not supported.
5604 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5605 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5609 unsigned NumElems = Op.getNumOperands();
5613 SmallVector<unsigned, 4> InsertIndices;
5614 SmallVector<int, 8> Mask(NumElems, -1);
5616 for (unsigned i = 0; i != NumElems; ++i) {
5617 unsigned Opc = Op.getOperand(i).getOpcode();
5619 if (Opc == ISD::UNDEF)
5622 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5623 // Quit if more than 1 elements need inserting.
5624 if (InsertIndices.size() > 1)
5627 InsertIndices.push_back(i);
5631 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5632 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5634 // Quit if extracted from vector of different type.
5635 if (ExtractedFromVec.getValueType() != VT)
5638 // Quit if non-constant index.
5639 if (!isa<ConstantSDNode>(ExtIdx))
5642 if (VecIn1.getNode() == 0)
5643 VecIn1 = ExtractedFromVec;
5644 else if (VecIn1 != ExtractedFromVec) {
5645 if (VecIn2.getNode() == 0)
5646 VecIn2 = ExtractedFromVec;
5647 else if (VecIn2 != ExtractedFromVec)
5648 // Quit if more than 2 vectors to shuffle
5652 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5654 if (ExtractedFromVec == VecIn1)
5656 else if (ExtractedFromVec == VecIn2)
5657 Mask[i] = Idx + NumElems;
5660 if (VecIn1.getNode() == 0)
5663 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5664 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5665 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5666 unsigned Idx = InsertIndices[i];
5667 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5668 DAG.getIntPtrConstant(Idx));
5674 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5676 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5678 MVT VT = Op.getSimpleValueType();
5679 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5680 "Unexpected type in LowerBUILD_VECTORvXi1!");
5683 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5684 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5685 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5686 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5687 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5688 Ops, VT.getVectorNumElements());
5691 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5692 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5693 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5694 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5695 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5696 Ops, VT.getVectorNumElements());
5699 bool AllContants = true;
5700 uint64_t Immediate = 0;
5701 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5702 SDValue In = Op.getOperand(idx);
5703 if (In.getOpcode() == ISD::UNDEF)
5705 if (!isa<ConstantSDNode>(In)) {
5706 AllContants = false;
5709 if (cast<ConstantSDNode>(In)->getZExtValue())
5710 Immediate |= (1ULL << idx);
5714 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5715 DAG.getConstant(Immediate, MVT::i16));
5716 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5717 DAG.getIntPtrConstant(0));
5720 // Splat vector (with undefs)
5721 SDValue In = Op.getOperand(0);
5722 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5723 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5724 llvm_unreachable("Unsupported predicate operation");
5727 SDValue EFLAGS, X86CC;
5728 if (In.getOpcode() == ISD::SETCC) {
5729 SDValue Op0 = In.getOperand(0);
5730 SDValue Op1 = In.getOperand(1);
5731 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5732 bool isFP = Op1.getValueType().isFloatingPoint();
5733 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5735 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5737 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5738 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5739 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5740 } else if (In.getOpcode() == X86ISD::SETCC) {
5741 X86CC = In.getOperand(0);
5742 EFLAGS = In.getOperand(1);
5751 // res = allOnes ### CMOVNE -1, %res
5754 MVT InVT = In.getSimpleValueType();
5755 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5756 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5757 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5760 if (VT == MVT::v16i1) {
5761 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5762 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5763 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5764 Cst0, Cst1, X86CC, EFLAGS);
5765 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5768 if (VT == MVT::v8i1) {
5769 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5770 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5771 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5772 Cst0, Cst1, X86CC, EFLAGS);
5773 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5774 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5776 llvm_unreachable("Unsupported predicate operation");
5780 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5783 MVT VT = Op.getSimpleValueType();
5784 MVT ExtVT = VT.getVectorElementType();
5785 unsigned NumElems = Op.getNumOperands();
5787 // Generate vectors for predicate vectors.
5788 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5789 return LowerBUILD_VECTORvXi1(Op, DAG);
5791 // Vectors containing all zeros can be matched by pxor and xorps later
5792 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5793 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5794 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5795 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5798 return getZeroVector(VT, Subtarget, DAG, dl);
5801 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5802 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5803 // vpcmpeqd on 256-bit vectors.
5804 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5805 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5808 if (!VT.is512BitVector())
5809 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5812 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5813 if (Broadcast.getNode())
5816 unsigned EVTBits = ExtVT.getSizeInBits();
5818 unsigned NumZero = 0;
5819 unsigned NumNonZero = 0;
5820 unsigned NonZeros = 0;
5821 bool IsAllConstants = true;
5822 SmallSet<SDValue, 8> Values;
5823 for (unsigned i = 0; i < NumElems; ++i) {
5824 SDValue Elt = Op.getOperand(i);
5825 if (Elt.getOpcode() == ISD::UNDEF)
5828 if (Elt.getOpcode() != ISD::Constant &&
5829 Elt.getOpcode() != ISD::ConstantFP)
5830 IsAllConstants = false;
5831 if (X86::isZeroNode(Elt))
5834 NonZeros |= (1 << i);
5839 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5840 if (NumNonZero == 0)
5841 return DAG.getUNDEF(VT);
5843 // Special case for single non-zero, non-undef, element.
5844 if (NumNonZero == 1) {
5845 unsigned Idx = countTrailingZeros(NonZeros);
5846 SDValue Item = Op.getOperand(Idx);
5848 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5849 // the value are obviously zero, truncate the value to i32 and do the
5850 // insertion that way. Only do this if the value is non-constant or if the
5851 // value is a constant being inserted into element 0. It is cheaper to do
5852 // a constant pool load than it is to do a movd + shuffle.
5853 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5854 (!IsAllConstants || Idx == 0)) {
5855 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5857 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5858 EVT VecVT = MVT::v4i32;
5859 unsigned VecElts = 4;
5861 // Truncate the value (which may itself be a constant) to i32, and
5862 // convert it to a vector with movd (S2V+shuffle to zero extend).
5863 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5864 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5865 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5867 // Now we have our 32-bit value zero extended in the low element of
5868 // a vector. If Idx != 0, swizzle it into place.
5870 SmallVector<int, 4> Mask;
5871 Mask.push_back(Idx);
5872 for (unsigned i = 1; i != VecElts; ++i)
5874 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5877 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5881 // If we have a constant or non-constant insertion into the low element of
5882 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5883 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5884 // depending on what the source datatype is.
5887 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5889 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5890 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5891 if (VT.is256BitVector() || VT.is512BitVector()) {
5892 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5893 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5894 Item, DAG.getIntPtrConstant(0));
5896 assert(VT.is128BitVector() && "Expected an SSE value type!");
5897 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5898 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5899 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5902 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5903 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5904 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5905 if (VT.is256BitVector()) {
5906 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5907 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5909 assert(VT.is128BitVector() && "Expected an SSE value type!");
5910 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5912 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5916 // Is it a vector logical left shift?
5917 if (NumElems == 2 && Idx == 1 &&
5918 X86::isZeroNode(Op.getOperand(0)) &&
5919 !X86::isZeroNode(Op.getOperand(1))) {
5920 unsigned NumBits = VT.getSizeInBits();
5921 return getVShift(true, VT,
5922 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5923 VT, Op.getOperand(1)),
5924 NumBits/2, DAG, *this, dl);
5927 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5930 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5931 // is a non-constant being inserted into an element other than the low one,
5932 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5933 // movd/movss) to move this into the low element, then shuffle it into
5935 if (EVTBits == 32) {
5936 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5938 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5939 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5940 SmallVector<int, 8> MaskVec;
5941 for (unsigned i = 0; i != NumElems; ++i)
5942 MaskVec.push_back(i == Idx ? 0 : 1);
5943 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5947 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5948 if (Values.size() == 1) {
5949 if (EVTBits == 32) {
5950 // Instead of a shuffle like this:
5951 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5952 // Check if it's possible to issue this instead.
5953 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5954 unsigned Idx = countTrailingZeros(NonZeros);
5955 SDValue Item = Op.getOperand(Idx);
5956 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5957 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5962 // A vector full of immediates; various special cases are already
5963 // handled, so this is best done with a single constant-pool load.
5967 // For AVX-length vectors, build the individual 128-bit pieces and use
5968 // shuffles to put them in place.
5969 if (VT.is256BitVector()) {
5970 SmallVector<SDValue, 32> V;
5971 for (unsigned i = 0; i != NumElems; ++i)
5972 V.push_back(Op.getOperand(i));
5974 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5976 // Build both the lower and upper subvector.
5977 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5978 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5981 // Recreate the wider vector with the lower and upper part.
5982 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5985 // Let legalizer expand 2-wide build_vectors.
5986 if (EVTBits == 64) {
5987 if (NumNonZero == 1) {
5988 // One half is zero or undef.
5989 unsigned Idx = countTrailingZeros(NonZeros);
5990 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5991 Op.getOperand(Idx));
5992 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5997 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5998 if (EVTBits == 8 && NumElems == 16) {
5999 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6001 if (V.getNode()) return V;
6004 if (EVTBits == 16 && NumElems == 8) {
6005 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6007 if (V.getNode()) return V;
6010 // If element VT is == 32 bits, turn it into a number of shuffles.
6011 SmallVector<SDValue, 8> V(NumElems);
6012 if (NumElems == 4 && NumZero > 0) {
6013 for (unsigned i = 0; i < 4; ++i) {
6014 bool isZero = !(NonZeros & (1 << i));
6016 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6018 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6021 for (unsigned i = 0; i < 2; ++i) {
6022 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6025 V[i] = V[i*2]; // Must be a zero vector.
6028 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6031 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6034 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6039 bool Reverse1 = (NonZeros & 0x3) == 2;
6040 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6044 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6045 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6047 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6050 if (Values.size() > 1 && VT.is128BitVector()) {
6051 // Check for a build vector of consecutive loads.
6052 for (unsigned i = 0; i < NumElems; ++i)
6053 V[i] = Op.getOperand(i);
6055 // Check for elements which are consecutive loads.
6056 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6060 // Check for a build vector from mostly shuffle plus few inserting.
6061 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6065 // For SSE 4.1, use insertps to put the high elements into the low element.
6066 if (getSubtarget()->hasSSE41()) {
6068 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6069 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6071 Result = DAG.getUNDEF(VT);
6073 for (unsigned i = 1; i < NumElems; ++i) {
6074 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6075 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6076 Op.getOperand(i), DAG.getIntPtrConstant(i));
6081 // Otherwise, expand into a number of unpckl*, start by extending each of
6082 // our (non-undef) elements to the full vector width with the element in the
6083 // bottom slot of the vector (which generates no code for SSE).
6084 for (unsigned i = 0; i < NumElems; ++i) {
6085 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6086 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6088 V[i] = DAG.getUNDEF(VT);
6091 // Next, we iteratively mix elements, e.g. for v4f32:
6092 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6093 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6094 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6095 unsigned EltStride = NumElems >> 1;
6096 while (EltStride != 0) {
6097 for (unsigned i = 0; i < EltStride; ++i) {
6098 // If V[i+EltStride] is undef and this is the first round of mixing,
6099 // then it is safe to just drop this shuffle: V[i] is already in the
6100 // right place, the one element (since it's the first round) being
6101 // inserted as undef can be dropped. This isn't safe for successive
6102 // rounds because they will permute elements within both vectors.
6103 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6104 EltStride == NumElems/2)
6107 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6116 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6117 // to create 256-bit vectors from two other 128-bit ones.
6118 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6120 MVT ResVT = Op.getSimpleValueType();
6122 assert((ResVT.is256BitVector() ||
6123 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6125 SDValue V1 = Op.getOperand(0);
6126 SDValue V2 = Op.getOperand(1);
6127 unsigned NumElems = ResVT.getVectorNumElements();
6128 if(ResVT.is256BitVector())
6129 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6131 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6134 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6135 assert(Op.getNumOperands() == 2);
6137 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6138 // from two other 128-bit ones.
6139 return LowerAVXCONCAT_VECTORS(Op, DAG);
6142 // Try to lower a shuffle node into a simple blend instruction.
6144 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6145 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6146 SDValue V1 = SVOp->getOperand(0);
6147 SDValue V2 = SVOp->getOperand(1);
6149 MVT VT = SVOp->getSimpleValueType(0);
6150 MVT EltVT = VT.getVectorElementType();
6151 unsigned NumElems = VT.getVectorNumElements();
6153 // There is no blend with immediate in AVX-512.
6154 if (VT.is512BitVector())
6157 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6159 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6162 // Check the mask for BLEND and build the value.
6163 unsigned MaskValue = 0;
6164 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6165 unsigned NumLanes = (NumElems-1)/8 + 1;
6166 unsigned NumElemsInLane = NumElems / NumLanes;
6168 // Blend for v16i16 should be symetric for the both lanes.
6169 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6171 int SndLaneEltIdx = (NumLanes == 2) ?
6172 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6173 int EltIdx = SVOp->getMaskElt(i);
6175 if ((EltIdx < 0 || EltIdx == (int)i) &&
6176 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6179 if (((unsigned)EltIdx == (i + NumElems)) &&
6180 (SndLaneEltIdx < 0 ||
6181 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6182 MaskValue |= (1<<i);
6187 // Convert i32 vectors to floating point if it is not AVX2.
6188 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6190 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6191 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6193 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6194 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6197 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6198 DAG.getConstant(MaskValue, MVT::i32));
6199 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6202 // v8i16 shuffles - Prefer shuffles in the following order:
6203 // 1. [all] pshuflw, pshufhw, optional move
6204 // 2. [ssse3] 1 x pshufb
6205 // 3. [ssse3] 2 x pshufb + 1 x por
6206 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6208 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6209 SelectionDAG &DAG) {
6210 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6211 SDValue V1 = SVOp->getOperand(0);
6212 SDValue V2 = SVOp->getOperand(1);
6214 SmallVector<int, 8> MaskVals;
6216 // Determine if more than 1 of the words in each of the low and high quadwords
6217 // of the result come from the same quadword of one of the two inputs. Undef
6218 // mask values count as coming from any quadword, for better codegen.
6219 unsigned LoQuad[] = { 0, 0, 0, 0 };
6220 unsigned HiQuad[] = { 0, 0, 0, 0 };
6221 std::bitset<4> InputQuads;
6222 for (unsigned i = 0; i < 8; ++i) {
6223 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6224 int EltIdx = SVOp->getMaskElt(i);
6225 MaskVals.push_back(EltIdx);
6234 InputQuads.set(EltIdx / 4);
6237 int BestLoQuad = -1;
6238 unsigned MaxQuad = 1;
6239 for (unsigned i = 0; i < 4; ++i) {
6240 if (LoQuad[i] > MaxQuad) {
6242 MaxQuad = LoQuad[i];
6246 int BestHiQuad = -1;
6248 for (unsigned i = 0; i < 4; ++i) {
6249 if (HiQuad[i] > MaxQuad) {
6251 MaxQuad = HiQuad[i];
6255 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6256 // of the two input vectors, shuffle them into one input vector so only a
6257 // single pshufb instruction is necessary. If There are more than 2 input
6258 // quads, disable the next transformation since it does not help SSSE3.
6259 bool V1Used = InputQuads[0] || InputQuads[1];
6260 bool V2Used = InputQuads[2] || InputQuads[3];
6261 if (Subtarget->hasSSSE3()) {
6262 if (InputQuads.count() == 2 && V1Used && V2Used) {
6263 BestLoQuad = InputQuads[0] ? 0 : 1;
6264 BestHiQuad = InputQuads[2] ? 2 : 3;
6266 if (InputQuads.count() > 2) {
6272 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6273 // the shuffle mask. If a quad is scored as -1, that means that it contains
6274 // words from all 4 input quadwords.
6276 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6278 BestLoQuad < 0 ? 0 : BestLoQuad,
6279 BestHiQuad < 0 ? 1 : BestHiQuad
6281 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6282 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6283 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6284 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6286 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6287 // source words for the shuffle, to aid later transformations.
6288 bool AllWordsInNewV = true;
6289 bool InOrder[2] = { true, true };
6290 for (unsigned i = 0; i != 8; ++i) {
6291 int idx = MaskVals[i];
6293 InOrder[i/4] = false;
6294 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6296 AllWordsInNewV = false;
6300 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6301 if (AllWordsInNewV) {
6302 for (int i = 0; i != 8; ++i) {
6303 int idx = MaskVals[i];
6306 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6307 if ((idx != i) && idx < 4)
6309 if ((idx != i) && idx > 3)
6318 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6319 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6320 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6321 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6322 unsigned TargetMask = 0;
6323 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6324 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6325 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6326 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6327 getShufflePSHUFLWImmediate(SVOp);
6328 V1 = NewV.getOperand(0);
6329 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6333 // Promote splats to a larger type which usually leads to more efficient code.
6334 // FIXME: Is this true if pshufb is available?
6335 if (SVOp->isSplat())
6336 return PromoteSplat(SVOp, DAG);
6338 // If we have SSSE3, and all words of the result are from 1 input vector,
6339 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6340 // is present, fall back to case 4.
6341 if (Subtarget->hasSSSE3()) {
6342 SmallVector<SDValue,16> pshufbMask;
6344 // If we have elements from both input vectors, set the high bit of the
6345 // shuffle mask element to zero out elements that come from V2 in the V1
6346 // mask, and elements that come from V1 in the V2 mask, so that the two
6347 // results can be OR'd together.
6348 bool TwoInputs = V1Used && V2Used;
6349 for (unsigned i = 0; i != 8; ++i) {
6350 int EltIdx = MaskVals[i] * 2;
6351 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6352 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6353 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6354 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6356 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6357 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6358 DAG.getNode(ISD::BUILD_VECTOR, dl,
6359 MVT::v16i8, &pshufbMask[0], 16));
6361 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6363 // Calculate the shuffle mask for the second input, shuffle it, and
6364 // OR it with the first shuffled input.
6366 for (unsigned i = 0; i != 8; ++i) {
6367 int EltIdx = MaskVals[i] * 2;
6368 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6369 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6370 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6371 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6373 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6374 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6375 DAG.getNode(ISD::BUILD_VECTOR, dl,
6376 MVT::v16i8, &pshufbMask[0], 16));
6377 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6378 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6381 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6382 // and update MaskVals with new element order.
6383 std::bitset<8> InOrder;
6384 if (BestLoQuad >= 0) {
6385 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6386 for (int i = 0; i != 4; ++i) {
6387 int idx = MaskVals[i];
6390 } else if ((idx / 4) == BestLoQuad) {
6395 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6398 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6399 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6400 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6402 getShufflePSHUFLWImmediate(SVOp), DAG);
6406 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6407 // and update MaskVals with the new element order.
6408 if (BestHiQuad >= 0) {
6409 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6410 for (unsigned i = 4; i != 8; ++i) {
6411 int idx = MaskVals[i];
6414 } else if ((idx / 4) == BestHiQuad) {
6415 MaskV[i] = (idx & 3) + 4;
6419 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6422 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6423 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6424 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6426 getShufflePSHUFHWImmediate(SVOp), DAG);
6430 // In case BestHi & BestLo were both -1, which means each quadword has a word
6431 // from each of the four input quadwords, calculate the InOrder bitvector now
6432 // before falling through to the insert/extract cleanup.
6433 if (BestLoQuad == -1 && BestHiQuad == -1) {
6435 for (int i = 0; i != 8; ++i)
6436 if (MaskVals[i] < 0 || MaskVals[i] == i)
6440 // The other elements are put in the right place using pextrw and pinsrw.
6441 for (unsigned i = 0; i != 8; ++i) {
6444 int EltIdx = MaskVals[i];
6447 SDValue ExtOp = (EltIdx < 8) ?
6448 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6449 DAG.getIntPtrConstant(EltIdx)) :
6450 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6451 DAG.getIntPtrConstant(EltIdx - 8));
6452 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6453 DAG.getIntPtrConstant(i));
6458 // v16i8 shuffles - Prefer shuffles in the following order:
6459 // 1. [ssse3] 1 x pshufb
6460 // 2. [ssse3] 2 x pshufb + 1 x por
6461 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6462 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6463 const X86Subtarget* Subtarget,
6464 SelectionDAG &DAG) {
6465 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6466 SDValue V1 = SVOp->getOperand(0);
6467 SDValue V2 = SVOp->getOperand(1);
6469 ArrayRef<int> MaskVals = SVOp->getMask();
6471 // Promote splats to a larger type which usually leads to more efficient code.
6472 // FIXME: Is this true if pshufb is available?
6473 if (SVOp->isSplat())
6474 return PromoteSplat(SVOp, DAG);
6476 // If we have SSSE3, case 1 is generated when all result bytes come from
6477 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6478 // present, fall back to case 3.
6480 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6481 if (Subtarget->hasSSSE3()) {
6482 SmallVector<SDValue,16> pshufbMask;
6484 // If all result elements are from one input vector, then only translate
6485 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6487 // Otherwise, we have elements from both input vectors, and must zero out
6488 // elements that come from V2 in the first mask, and V1 in the second mask
6489 // so that we can OR them together.
6490 for (unsigned i = 0; i != 16; ++i) {
6491 int EltIdx = MaskVals[i];
6492 if (EltIdx < 0 || EltIdx >= 16)
6494 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6496 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6497 DAG.getNode(ISD::BUILD_VECTOR, dl,
6498 MVT::v16i8, &pshufbMask[0], 16));
6500 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6501 // the 2nd operand if it's undefined or zero.
6502 if (V2.getOpcode() == ISD::UNDEF ||
6503 ISD::isBuildVectorAllZeros(V2.getNode()))
6506 // Calculate the shuffle mask for the second input, shuffle it, and
6507 // OR it with the first shuffled input.
6509 for (unsigned i = 0; i != 16; ++i) {
6510 int EltIdx = MaskVals[i];
6511 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6512 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6514 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6515 DAG.getNode(ISD::BUILD_VECTOR, dl,
6516 MVT::v16i8, &pshufbMask[0], 16));
6517 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6520 // No SSSE3 - Calculate in place words and then fix all out of place words
6521 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6522 // the 16 different words that comprise the two doublequadword input vectors.
6523 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6524 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6526 for (int i = 0; i != 8; ++i) {
6527 int Elt0 = MaskVals[i*2];
6528 int Elt1 = MaskVals[i*2+1];
6530 // This word of the result is all undef, skip it.
6531 if (Elt0 < 0 && Elt1 < 0)
6534 // This word of the result is already in the correct place, skip it.
6535 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6538 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6539 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6542 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6543 // using a single extract together, load it and store it.
6544 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6545 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6546 DAG.getIntPtrConstant(Elt1 / 2));
6547 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6548 DAG.getIntPtrConstant(i));
6552 // If Elt1 is defined, extract it from the appropriate source. If the
6553 // source byte is not also odd, shift the extracted word left 8 bits
6554 // otherwise clear the bottom 8 bits if we need to do an or.
6556 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6557 DAG.getIntPtrConstant(Elt1 / 2));
6558 if ((Elt1 & 1) == 0)
6559 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6561 TLI.getShiftAmountTy(InsElt.getValueType())));
6563 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6564 DAG.getConstant(0xFF00, MVT::i16));
6566 // If Elt0 is defined, extract it from the appropriate source. If the
6567 // source byte is not also even, shift the extracted word right 8 bits. If
6568 // Elt1 was also defined, OR the extracted values together before
6569 // inserting them in the result.
6571 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6572 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6573 if ((Elt0 & 1) != 0)
6574 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6576 TLI.getShiftAmountTy(InsElt0.getValueType())));
6578 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6579 DAG.getConstant(0x00FF, MVT::i16));
6580 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6583 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6584 DAG.getIntPtrConstant(i));
6586 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6589 // v32i8 shuffles - Translate to VPSHUFB if possible.
6591 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6592 const X86Subtarget *Subtarget,
6593 SelectionDAG &DAG) {
6594 MVT VT = SVOp->getSimpleValueType(0);
6595 SDValue V1 = SVOp->getOperand(0);
6596 SDValue V2 = SVOp->getOperand(1);
6598 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6600 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6601 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6602 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6604 // VPSHUFB may be generated if
6605 // (1) one of input vector is undefined or zeroinitializer.
6606 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6607 // And (2) the mask indexes don't cross the 128-bit lane.
6608 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6609 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6612 if (V1IsAllZero && !V2IsAllZero) {
6613 CommuteVectorShuffleMask(MaskVals, 32);
6616 SmallVector<SDValue, 32> pshufbMask;
6617 for (unsigned i = 0; i != 32; i++) {
6618 int EltIdx = MaskVals[i];
6619 if (EltIdx < 0 || EltIdx >= 32)
6622 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6623 // Cross lane is not allowed.
6627 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6629 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6630 DAG.getNode(ISD::BUILD_VECTOR, dl,
6631 MVT::v32i8, &pshufbMask[0], 32));
6634 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6635 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6636 /// done when every pair / quad of shuffle mask elements point to elements in
6637 /// the right sequence. e.g.
6638 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6640 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6641 SelectionDAG &DAG) {
6642 MVT VT = SVOp->getSimpleValueType(0);
6644 unsigned NumElems = VT.getVectorNumElements();
6647 switch (VT.SimpleTy) {
6648 default: llvm_unreachable("Unexpected!");
6649 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6650 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6651 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6652 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6653 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6654 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6657 SmallVector<int, 8> MaskVec;
6658 for (unsigned i = 0; i != NumElems; i += Scale) {
6660 for (unsigned j = 0; j != Scale; ++j) {
6661 int EltIdx = SVOp->getMaskElt(i+j);
6665 StartIdx = (EltIdx / Scale);
6666 if (EltIdx != (int)(StartIdx*Scale + j))
6669 MaskVec.push_back(StartIdx);
6672 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6673 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6674 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6677 /// getVZextMovL - Return a zero-extending vector move low node.
6679 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6680 SDValue SrcOp, SelectionDAG &DAG,
6681 const X86Subtarget *Subtarget, SDLoc dl) {
6682 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6683 LoadSDNode *LD = NULL;
6684 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6685 LD = dyn_cast<LoadSDNode>(SrcOp);
6687 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6689 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6690 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6691 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6692 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6693 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6695 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6696 return DAG.getNode(ISD::BITCAST, dl, VT,
6697 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6698 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6706 return DAG.getNode(ISD::BITCAST, dl, VT,
6707 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6708 DAG.getNode(ISD::BITCAST, dl,
6712 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6713 /// which could not be matched by any known target speficic shuffle
6715 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6717 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6718 if (NewOp.getNode())
6721 MVT VT = SVOp->getSimpleValueType(0);
6723 unsigned NumElems = VT.getVectorNumElements();
6724 unsigned NumLaneElems = NumElems / 2;
6727 MVT EltVT = VT.getVectorElementType();
6728 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6731 SmallVector<int, 16> Mask;
6732 for (unsigned l = 0; l < 2; ++l) {
6733 // Build a shuffle mask for the output, discovering on the fly which
6734 // input vectors to use as shuffle operands (recorded in InputUsed).
6735 // If building a suitable shuffle vector proves too hard, then bail
6736 // out with UseBuildVector set.
6737 bool UseBuildVector = false;
6738 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6739 unsigned LaneStart = l * NumLaneElems;
6740 for (unsigned i = 0; i != NumLaneElems; ++i) {
6741 // The mask element. This indexes into the input.
6742 int Idx = SVOp->getMaskElt(i+LaneStart);
6744 // the mask element does not index into any input vector.
6749 // The input vector this mask element indexes into.
6750 int Input = Idx / NumLaneElems;
6752 // Turn the index into an offset from the start of the input vector.
6753 Idx -= Input * NumLaneElems;
6755 // Find or create a shuffle vector operand to hold this input.
6757 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6758 if (InputUsed[OpNo] == Input)
6759 // This input vector is already an operand.
6761 if (InputUsed[OpNo] < 0) {
6762 // Create a new operand for this input vector.
6763 InputUsed[OpNo] = Input;
6768 if (OpNo >= array_lengthof(InputUsed)) {
6769 // More than two input vectors used! Give up on trying to create a
6770 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6771 UseBuildVector = true;
6775 // Add the mask index for the new shuffle vector.
6776 Mask.push_back(Idx + OpNo * NumLaneElems);
6779 if (UseBuildVector) {
6780 SmallVector<SDValue, 16> SVOps;
6781 for (unsigned i = 0; i != NumLaneElems; ++i) {
6782 // The mask element. This indexes into the input.
6783 int Idx = SVOp->getMaskElt(i+LaneStart);
6785 SVOps.push_back(DAG.getUNDEF(EltVT));
6789 // The input vector this mask element indexes into.
6790 int Input = Idx / NumElems;
6792 // Turn the index into an offset from the start of the input vector.
6793 Idx -= Input * NumElems;
6795 // Extract the vector element by hand.
6796 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6797 SVOp->getOperand(Input),
6798 DAG.getIntPtrConstant(Idx)));
6801 // Construct the output using a BUILD_VECTOR.
6802 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6804 } else if (InputUsed[0] < 0) {
6805 // No input vectors were used! The result is undefined.
6806 Output[l] = DAG.getUNDEF(NVT);
6808 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6809 (InputUsed[0] % 2) * NumLaneElems,
6811 // If only one input was used, use an undefined vector for the other.
6812 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6813 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6814 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6815 // At least one input vector was used. Create a new shuffle vector.
6816 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6822 // Concatenate the result back
6823 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6826 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6827 /// 4 elements, and match them with several different shuffle types.
6829 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6830 SDValue V1 = SVOp->getOperand(0);
6831 SDValue V2 = SVOp->getOperand(1);
6833 MVT VT = SVOp->getSimpleValueType(0);
6835 assert(VT.is128BitVector() && "Unsupported vector size");
6837 std::pair<int, int> Locs[4];
6838 int Mask1[] = { -1, -1, -1, -1 };
6839 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6843 for (unsigned i = 0; i != 4; ++i) {
6844 int Idx = PermMask[i];
6846 Locs[i] = std::make_pair(-1, -1);
6848 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6850 Locs[i] = std::make_pair(0, NumLo);
6854 Locs[i] = std::make_pair(1, NumHi);
6856 Mask1[2+NumHi] = Idx;
6862 if (NumLo <= 2 && NumHi <= 2) {
6863 // If no more than two elements come from either vector. This can be
6864 // implemented with two shuffles. First shuffle gather the elements.
6865 // The second shuffle, which takes the first shuffle as both of its
6866 // vector operands, put the elements into the right order.
6867 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6869 int Mask2[] = { -1, -1, -1, -1 };
6871 for (unsigned i = 0; i != 4; ++i)
6872 if (Locs[i].first != -1) {
6873 unsigned Idx = (i < 2) ? 0 : 4;
6874 Idx += Locs[i].first * 2 + Locs[i].second;
6878 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6881 if (NumLo == 3 || NumHi == 3) {
6882 // Otherwise, we must have three elements from one vector, call it X, and
6883 // one element from the other, call it Y. First, use a shufps to build an
6884 // intermediate vector with the one element from Y and the element from X
6885 // that will be in the same half in the final destination (the indexes don't
6886 // matter). Then, use a shufps to build the final vector, taking the half
6887 // containing the element from Y from the intermediate, and the other half
6890 // Normalize it so the 3 elements come from V1.
6891 CommuteVectorShuffleMask(PermMask, 4);
6895 // Find the element from V2.
6897 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6898 int Val = PermMask[HiIndex];
6905 Mask1[0] = PermMask[HiIndex];
6907 Mask1[2] = PermMask[HiIndex^1];
6909 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6912 Mask1[0] = PermMask[0];
6913 Mask1[1] = PermMask[1];
6914 Mask1[2] = HiIndex & 1 ? 6 : 4;
6915 Mask1[3] = HiIndex & 1 ? 4 : 6;
6916 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6919 Mask1[0] = HiIndex & 1 ? 2 : 0;
6920 Mask1[1] = HiIndex & 1 ? 0 : 2;
6921 Mask1[2] = PermMask[2];
6922 Mask1[3] = PermMask[3];
6927 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6930 // Break it into (shuffle shuffle_hi, shuffle_lo).
6931 int LoMask[] = { -1, -1, -1, -1 };
6932 int HiMask[] = { -1, -1, -1, -1 };
6934 int *MaskPtr = LoMask;
6935 unsigned MaskIdx = 0;
6938 for (unsigned i = 0; i != 4; ++i) {
6945 int Idx = PermMask[i];
6947 Locs[i] = std::make_pair(-1, -1);
6948 } else if (Idx < 4) {
6949 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6950 MaskPtr[LoIdx] = Idx;
6953 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6954 MaskPtr[HiIdx] = Idx;
6959 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6960 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6961 int MaskOps[] = { -1, -1, -1, -1 };
6962 for (unsigned i = 0; i != 4; ++i)
6963 if (Locs[i].first != -1)
6964 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6965 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6968 static bool MayFoldVectorLoad(SDValue V) {
6969 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6970 V = V.getOperand(0);
6972 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6973 V = V.getOperand(0);
6974 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6975 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6976 // BUILD_VECTOR (load), undef
6977 V = V.getOperand(0);
6979 return MayFoldLoad(V);
6983 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6984 MVT VT = Op.getSimpleValueType();
6986 // Canonizalize to v2f64.
6987 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6988 return DAG.getNode(ISD::BITCAST, dl, VT,
6989 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6994 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6996 SDValue V1 = Op.getOperand(0);
6997 SDValue V2 = Op.getOperand(1);
6998 MVT VT = Op.getSimpleValueType();
7000 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7002 if (HasSSE2 && VT == MVT::v2f64)
7003 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7005 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7006 return DAG.getNode(ISD::BITCAST, dl, VT,
7007 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7008 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7009 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7013 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7014 SDValue V1 = Op.getOperand(0);
7015 SDValue V2 = Op.getOperand(1);
7016 MVT VT = Op.getSimpleValueType();
7018 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7019 "unsupported shuffle type");
7021 if (V2.getOpcode() == ISD::UNDEF)
7025 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7029 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7030 SDValue V1 = Op.getOperand(0);
7031 SDValue V2 = Op.getOperand(1);
7032 MVT VT = Op.getSimpleValueType();
7033 unsigned NumElems = VT.getVectorNumElements();
7035 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7036 // operand of these instructions is only memory, so check if there's a
7037 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7039 bool CanFoldLoad = false;
7041 // Trivial case, when V2 comes from a load.
7042 if (MayFoldVectorLoad(V2))
7045 // When V1 is a load, it can be folded later into a store in isel, example:
7046 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7048 // (MOVLPSmr addr:$src1, VR128:$src2)
7049 // So, recognize this potential and also use MOVLPS or MOVLPD
7050 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7053 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7055 if (HasSSE2 && NumElems == 2)
7056 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7059 // If we don't care about the second element, proceed to use movss.
7060 if (SVOp->getMaskElt(1) != -1)
7061 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7064 // movl and movlp will both match v2i64, but v2i64 is never matched by
7065 // movl earlier because we make it strict to avoid messing with the movlp load
7066 // folding logic (see the code above getMOVLP call). Match it here then,
7067 // this is horrible, but will stay like this until we move all shuffle
7068 // matching to x86 specific nodes. Note that for the 1st condition all
7069 // types are matched with movsd.
7071 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7072 // as to remove this logic from here, as much as possible
7073 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7074 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7075 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7078 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7080 // Invert the operand order and use SHUFPS to match it.
7081 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7082 getShuffleSHUFImmediate(SVOp), DAG);
7085 // Reduce a vector shuffle to zext.
7086 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7087 SelectionDAG &DAG) {
7088 // PMOVZX is only available from SSE41.
7089 if (!Subtarget->hasSSE41())
7092 MVT VT = Op.getSimpleValueType();
7094 // Only AVX2 support 256-bit vector integer extending.
7095 if (!Subtarget->hasInt256() && VT.is256BitVector())
7098 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7100 SDValue V1 = Op.getOperand(0);
7101 SDValue V2 = Op.getOperand(1);
7102 unsigned NumElems = VT.getVectorNumElements();
7104 // Extending is an unary operation and the element type of the source vector
7105 // won't be equal to or larger than i64.
7106 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7107 VT.getVectorElementType() == MVT::i64)
7110 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7111 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7112 while ((1U << Shift) < NumElems) {
7113 if (SVOp->getMaskElt(1U << Shift) == 1)
7116 // The maximal ratio is 8, i.e. from i8 to i64.
7121 // Check the shuffle mask.
7122 unsigned Mask = (1U << Shift) - 1;
7123 for (unsigned i = 0; i != NumElems; ++i) {
7124 int EltIdx = SVOp->getMaskElt(i);
7125 if ((i & Mask) != 0 && EltIdx != -1)
7127 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7131 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7132 MVT NeVT = MVT::getIntegerVT(NBits);
7133 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7135 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7138 // Simplify the operand as it's prepared to be fed into shuffle.
7139 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7140 if (V1.getOpcode() == ISD::BITCAST &&
7141 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7142 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7143 V1.getOperand(0).getOperand(0)
7144 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7145 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7146 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7147 ConstantSDNode *CIdx =
7148 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7149 // If it's foldable, i.e. normal load with single use, we will let code
7150 // selection to fold it. Otherwise, we will short the conversion sequence.
7151 if (CIdx && CIdx->getZExtValue() == 0 &&
7152 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7153 MVT FullVT = V.getSimpleValueType();
7154 MVT V1VT = V1.getSimpleValueType();
7155 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7156 // The "ext_vec_elt" node is wider than the result node.
7157 // In this case we should extract subvector from V.
7158 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7159 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7160 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7161 FullVT.getVectorNumElements()/Ratio);
7162 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7163 DAG.getIntPtrConstant(0));
7165 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7169 return DAG.getNode(ISD::BITCAST, DL, VT,
7170 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7174 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7175 SelectionDAG &DAG) {
7176 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7177 MVT VT = Op.getSimpleValueType();
7179 SDValue V1 = Op.getOperand(0);
7180 SDValue V2 = Op.getOperand(1);
7182 if (isZeroShuffle(SVOp))
7183 return getZeroVector(VT, Subtarget, DAG, dl);
7185 // Handle splat operations
7186 if (SVOp->isSplat()) {
7187 // Use vbroadcast whenever the splat comes from a foldable load
7188 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7189 if (Broadcast.getNode())
7193 // Check integer expanding shuffles.
7194 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7195 if (NewOp.getNode())
7198 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7200 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7201 VT == MVT::v16i16 || VT == MVT::v32i8) {
7202 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7203 if (NewOp.getNode())
7204 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7205 } else if ((VT == MVT::v4i32 ||
7206 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7207 // FIXME: Figure out a cleaner way to do this.
7208 // Try to make use of movq to zero out the top part.
7209 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7210 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7211 if (NewOp.getNode()) {
7212 MVT NewVT = NewOp.getSimpleValueType();
7213 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7214 NewVT, true, false))
7215 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7216 DAG, Subtarget, dl);
7218 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7219 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7220 if (NewOp.getNode()) {
7221 MVT NewVT = NewOp.getSimpleValueType();
7222 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7223 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7224 DAG, Subtarget, dl);
7232 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7233 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7234 SDValue V1 = Op.getOperand(0);
7235 SDValue V2 = Op.getOperand(1);
7236 MVT VT = Op.getSimpleValueType();
7238 unsigned NumElems = VT.getVectorNumElements();
7239 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7240 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7241 bool V1IsSplat = false;
7242 bool V2IsSplat = false;
7243 bool HasSSE2 = Subtarget->hasSSE2();
7244 bool HasFp256 = Subtarget->hasFp256();
7245 bool HasInt256 = Subtarget->hasInt256();
7246 MachineFunction &MF = DAG.getMachineFunction();
7247 bool OptForSize = MF.getFunction()->getAttributes().
7248 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7250 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7252 if (V1IsUndef && V2IsUndef)
7253 return DAG.getUNDEF(VT);
7255 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7257 // Vector shuffle lowering takes 3 steps:
7259 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7260 // narrowing and commutation of operands should be handled.
7261 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7263 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7264 // so the shuffle can be broken into other shuffles and the legalizer can
7265 // try the lowering again.
7267 // The general idea is that no vector_shuffle operation should be left to
7268 // be matched during isel, all of them must be converted to a target specific
7271 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7272 // narrowing and commutation of operands should be handled. The actual code
7273 // doesn't include all of those, work in progress...
7274 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7275 if (NewOp.getNode())
7278 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7280 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7281 // unpckh_undef). Only use pshufd if speed is more important than size.
7282 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7283 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7284 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7285 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7287 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7288 V2IsUndef && MayFoldVectorLoad(V1))
7289 return getMOVDDup(Op, dl, V1, DAG);
7291 if (isMOVHLPS_v_undef_Mask(M, VT))
7292 return getMOVHighToLow(Op, dl, DAG);
7294 // Use to match splats
7295 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7296 (VT == MVT::v2f64 || VT == MVT::v2i64))
7297 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7299 if (isPSHUFDMask(M, VT)) {
7300 // The actual implementation will match the mask in the if above and then
7301 // during isel it can match several different instructions, not only pshufd
7302 // as its name says, sad but true, emulate the behavior for now...
7303 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7304 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7306 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7308 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7309 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7311 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7312 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7315 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7319 if (isPALIGNRMask(M, VT, Subtarget))
7320 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7321 getShufflePALIGNRImmediate(SVOp),
7324 // Check if this can be converted into a logical shift.
7325 bool isLeft = false;
7328 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7329 if (isShift && ShVal.hasOneUse()) {
7330 // If the shifted value has multiple uses, it may be cheaper to use
7331 // v_set0 + movlhps or movhlps, etc.
7332 MVT EltVT = VT.getVectorElementType();
7333 ShAmt *= EltVT.getSizeInBits();
7334 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7337 if (isMOVLMask(M, VT)) {
7338 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7339 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7340 if (!isMOVLPMask(M, VT)) {
7341 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7342 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7344 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7345 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7349 // FIXME: fold these into legal mask.
7350 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7351 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7353 if (isMOVHLPSMask(M, VT))
7354 return getMOVHighToLow(Op, dl, DAG);
7356 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7357 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7359 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7360 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7362 if (isMOVLPMask(M, VT))
7363 return getMOVLP(Op, dl, DAG, HasSSE2);
7365 if (ShouldXformToMOVHLPS(M, VT) ||
7366 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7367 return CommuteVectorShuffle(SVOp, DAG);
7370 // No better options. Use a vshldq / vsrldq.
7371 MVT EltVT = VT.getVectorElementType();
7372 ShAmt *= EltVT.getSizeInBits();
7373 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7376 bool Commuted = false;
7377 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7378 // 1,1,1,1 -> v8i16 though.
7379 V1IsSplat = isSplatVector(V1.getNode());
7380 V2IsSplat = isSplatVector(V2.getNode());
7382 // Canonicalize the splat or undef, if present, to be on the RHS.
7383 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7384 CommuteVectorShuffleMask(M, NumElems);
7386 std::swap(V1IsSplat, V2IsSplat);
7390 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7391 // Shuffling low element of v1 into undef, just return v1.
7394 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7395 // the instruction selector will not match, so get a canonical MOVL with
7396 // swapped operands to undo the commute.
7397 return getMOVL(DAG, dl, VT, V2, V1);
7400 if (isUNPCKLMask(M, VT, HasInt256))
7401 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7403 if (isUNPCKHMask(M, VT, HasInt256))
7404 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7407 // Normalize mask so all entries that point to V2 points to its first
7408 // element then try to match unpck{h|l} again. If match, return a
7409 // new vector_shuffle with the corrected mask.p
7410 SmallVector<int, 8> NewMask(M.begin(), M.end());
7411 NormalizeMask(NewMask, NumElems);
7412 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7413 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7414 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7415 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7419 // Commute is back and try unpck* again.
7420 // FIXME: this seems wrong.
7421 CommuteVectorShuffleMask(M, NumElems);
7423 std::swap(V1IsSplat, V2IsSplat);
7426 if (isUNPCKLMask(M, VT, HasInt256))
7427 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7429 if (isUNPCKHMask(M, VT, HasInt256))
7430 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7433 // Normalize the node to match x86 shuffle ops if needed
7434 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7435 return CommuteVectorShuffle(SVOp, DAG);
7437 // The checks below are all present in isShuffleMaskLegal, but they are
7438 // inlined here right now to enable us to directly emit target specific
7439 // nodes, and remove one by one until they don't return Op anymore.
7441 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7442 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7443 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7444 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7447 if (isPSHUFHWMask(M, VT, HasInt256))
7448 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7449 getShufflePSHUFHWImmediate(SVOp),
7452 if (isPSHUFLWMask(M, VT, HasInt256))
7453 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7454 getShufflePSHUFLWImmediate(SVOp),
7457 if (isSHUFPMask(M, VT))
7458 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7459 getShuffleSHUFImmediate(SVOp), DAG);
7461 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7462 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7463 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7464 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7466 //===--------------------------------------------------------------------===//
7467 // Generate target specific nodes for 128 or 256-bit shuffles only
7468 // supported in the AVX instruction set.
7471 // Handle VMOVDDUPY permutations
7472 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7473 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7475 // Handle VPERMILPS/D* permutations
7476 if (isVPERMILPMask(M, VT)) {
7477 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7478 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7479 getShuffleSHUFImmediate(SVOp), DAG);
7480 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7481 getShuffleSHUFImmediate(SVOp), DAG);
7484 // Handle VPERM2F128/VPERM2I128 permutations
7485 if (isVPERM2X128Mask(M, VT, HasFp256))
7486 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7487 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7489 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7490 if (BlendOp.getNode())
7494 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7495 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7497 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7498 VT.is512BitVector()) {
7499 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7500 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7501 SmallVector<SDValue, 16> permclMask;
7502 for (unsigned i = 0; i != NumElems; ++i) {
7503 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7506 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7507 &permclMask[0], NumElems);
7509 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7510 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7511 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7512 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7513 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7516 //===--------------------------------------------------------------------===//
7517 // Since no target specific shuffle was selected for this generic one,
7518 // lower it into other known shuffles. FIXME: this isn't true yet, but
7519 // this is the plan.
7522 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7523 if (VT == MVT::v8i16) {
7524 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7525 if (NewOp.getNode())
7529 if (VT == MVT::v16i8) {
7530 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7531 if (NewOp.getNode())
7535 if (VT == MVT::v32i8) {
7536 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7537 if (NewOp.getNode())
7541 // Handle all 128-bit wide vectors with 4 elements, and match them with
7542 // several different shuffle types.
7543 if (NumElems == 4 && VT.is128BitVector())
7544 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7546 // Handle general 256-bit shuffles
7547 if (VT.is256BitVector())
7548 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7553 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7554 MVT VT = Op.getSimpleValueType();
7557 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7560 if (VT.getSizeInBits() == 8) {
7561 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7562 Op.getOperand(0), Op.getOperand(1));
7563 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7564 DAG.getValueType(VT));
7565 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7568 if (VT.getSizeInBits() == 16) {
7569 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7570 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7572 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7574 DAG.getNode(ISD::BITCAST, dl,
7578 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7579 Op.getOperand(0), Op.getOperand(1));
7580 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7581 DAG.getValueType(VT));
7582 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7585 if (VT == MVT::f32) {
7586 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7587 // the result back to FR32 register. It's only worth matching if the
7588 // result has a single use which is a store or a bitcast to i32. And in
7589 // the case of a store, it's not worth it if the index is a constant 0,
7590 // because a MOVSSmr can be used instead, which is smaller and faster.
7591 if (!Op.hasOneUse())
7593 SDNode *User = *Op.getNode()->use_begin();
7594 if ((User->getOpcode() != ISD::STORE ||
7595 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7596 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7597 (User->getOpcode() != ISD::BITCAST ||
7598 User->getValueType(0) != MVT::i32))
7600 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7601 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7604 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7607 if (VT == MVT::i32 || VT == MVT::i64) {
7608 // ExtractPS/pextrq works with constant index.
7609 if (isa<ConstantSDNode>(Op.getOperand(1)))
7616 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7617 SelectionDAG &DAG) const {
7619 SDValue Vec = Op.getOperand(0);
7620 MVT VecVT = Vec.getSimpleValueType();
7621 SDValue Idx = Op.getOperand(1);
7622 if (!isa<ConstantSDNode>(Idx)) {
7623 if (VecVT.is512BitVector() ||
7624 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7625 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7628 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7629 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7630 MaskEltVT.getSizeInBits());
7632 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7633 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7634 getZeroVector(MaskVT, Subtarget, DAG, dl),
7635 Idx, DAG.getConstant(0, getPointerTy()));
7636 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7637 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7638 Perm, DAG.getConstant(0, getPointerTy()));
7643 // If this is a 256-bit vector result, first extract the 128-bit vector and
7644 // then extract the element from the 128-bit vector.
7645 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7647 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7648 // Get the 128-bit vector.
7649 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7650 MVT EltVT = VecVT.getVectorElementType();
7652 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7654 //if (IdxVal >= NumElems/2)
7655 // IdxVal -= NumElems/2;
7656 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7657 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7658 DAG.getConstant(IdxVal, MVT::i32));
7661 assert(VecVT.is128BitVector() && "Unexpected vector length");
7663 if (Subtarget->hasSSE41()) {
7664 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7669 MVT VT = Op.getSimpleValueType();
7670 // TODO: handle v16i8.
7671 if (VT.getSizeInBits() == 16) {
7672 SDValue Vec = Op.getOperand(0);
7673 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7675 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7676 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7677 DAG.getNode(ISD::BITCAST, dl,
7680 // Transform it so it match pextrw which produces a 32-bit result.
7681 MVT EltVT = MVT::i32;
7682 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7683 Op.getOperand(0), Op.getOperand(1));
7684 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7685 DAG.getValueType(VT));
7686 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7689 if (VT.getSizeInBits() == 32) {
7690 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7694 // SHUFPS the element to the lowest double word, then movss.
7695 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7696 MVT VVT = Op.getOperand(0).getSimpleValueType();
7697 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7698 DAG.getUNDEF(VVT), Mask);
7699 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7700 DAG.getIntPtrConstant(0));
7703 if (VT.getSizeInBits() == 64) {
7704 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7705 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7706 // to match extract_elt for f64.
7707 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7711 // UNPCKHPD the element to the lowest double word, then movsd.
7712 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7713 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7714 int Mask[2] = { 1, -1 };
7715 MVT VVT = Op.getOperand(0).getSimpleValueType();
7716 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7717 DAG.getUNDEF(VVT), Mask);
7718 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7719 DAG.getIntPtrConstant(0));
7725 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7726 MVT VT = Op.getSimpleValueType();
7727 MVT EltVT = VT.getVectorElementType();
7730 SDValue N0 = Op.getOperand(0);
7731 SDValue N1 = Op.getOperand(1);
7732 SDValue N2 = Op.getOperand(2);
7734 if (!VT.is128BitVector())
7737 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7738 isa<ConstantSDNode>(N2)) {
7740 if (VT == MVT::v8i16)
7741 Opc = X86ISD::PINSRW;
7742 else if (VT == MVT::v16i8)
7743 Opc = X86ISD::PINSRB;
7745 Opc = X86ISD::PINSRB;
7747 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7749 if (N1.getValueType() != MVT::i32)
7750 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7751 if (N2.getValueType() != MVT::i32)
7752 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7753 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7756 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7757 // Bits [7:6] of the constant are the source select. This will always be
7758 // zero here. The DAG Combiner may combine an extract_elt index into these
7759 // bits. For example (insert (extract, 3), 2) could be matched by putting
7760 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7761 // Bits [5:4] of the constant are the destination select. This is the
7762 // value of the incoming immediate.
7763 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7764 // combine either bitwise AND or insert of float 0.0 to set these bits.
7765 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7766 // Create this as a scalar to vector..
7767 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7768 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7771 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7772 // PINSR* works with constant index.
7779 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7780 MVT VT = Op.getSimpleValueType();
7781 MVT EltVT = VT.getVectorElementType();
7784 SDValue N0 = Op.getOperand(0);
7785 SDValue N1 = Op.getOperand(1);
7786 SDValue N2 = Op.getOperand(2);
7788 // If this is a 256-bit vector result, first extract the 128-bit vector,
7789 // insert the element into the extracted half and then place it back.
7790 if (VT.is256BitVector() || VT.is512BitVector()) {
7791 if (!isa<ConstantSDNode>(N2))
7794 // Get the desired 128-bit vector half.
7795 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7796 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7798 // Insert the element into the desired half.
7799 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7800 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7802 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7803 DAG.getConstant(IdxIn128, MVT::i32));
7805 // Insert the changed part back to the 256-bit vector
7806 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7809 if (Subtarget->hasSSE41())
7810 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7812 if (EltVT == MVT::i8)
7815 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7816 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7817 // as its second argument.
7818 if (N1.getValueType() != MVT::i32)
7819 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7820 if (N2.getValueType() != MVT::i32)
7821 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7822 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7827 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7829 MVT OpVT = Op.getSimpleValueType();
7831 // If this is a 256-bit vector result, first insert into a 128-bit
7832 // vector and then insert into the 256-bit vector.
7833 if (!OpVT.is128BitVector()) {
7834 // Insert into a 128-bit vector.
7835 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7836 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7837 OpVT.getVectorNumElements() / SizeFactor);
7839 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7841 // Insert the 128-bit vector.
7842 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7845 if (OpVT == MVT::v1i64 &&
7846 Op.getOperand(0).getValueType() == MVT::i64)
7847 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7849 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7850 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7851 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7852 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7855 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7856 // a simple subregister reference or explicit instructions to grab
7857 // upper bits of a vector.
7858 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7859 SelectionDAG &DAG) {
7861 SDValue In = Op.getOperand(0);
7862 SDValue Idx = Op.getOperand(1);
7863 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7864 MVT ResVT = Op.getSimpleValueType();
7865 MVT InVT = In.getSimpleValueType();
7867 if (Subtarget->hasFp256()) {
7868 if (ResVT.is128BitVector() &&
7869 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7870 isa<ConstantSDNode>(Idx)) {
7871 return Extract128BitVector(In, IdxVal, DAG, dl);
7873 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7874 isa<ConstantSDNode>(Idx)) {
7875 return Extract256BitVector(In, IdxVal, DAG, dl);
7881 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7882 // simple superregister reference or explicit instructions to insert
7883 // the upper bits of a vector.
7884 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7885 SelectionDAG &DAG) {
7886 if (Subtarget->hasFp256()) {
7887 SDLoc dl(Op.getNode());
7888 SDValue Vec = Op.getNode()->getOperand(0);
7889 SDValue SubVec = Op.getNode()->getOperand(1);
7890 SDValue Idx = Op.getNode()->getOperand(2);
7892 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7893 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7894 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7895 isa<ConstantSDNode>(Idx)) {
7896 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7897 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7900 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7901 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7902 isa<ConstantSDNode>(Idx)) {
7903 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7904 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7910 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7911 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7912 // one of the above mentioned nodes. It has to be wrapped because otherwise
7913 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7914 // be used to form addressing mode. These wrapped nodes will be selected
7917 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7918 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7920 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7922 unsigned char OpFlag = 0;
7923 unsigned WrapperKind = X86ISD::Wrapper;
7924 CodeModel::Model M = getTargetMachine().getCodeModel();
7926 if (Subtarget->isPICStyleRIPRel() &&
7927 (M == CodeModel::Small || M == CodeModel::Kernel))
7928 WrapperKind = X86ISD::WrapperRIP;
7929 else if (Subtarget->isPICStyleGOT())
7930 OpFlag = X86II::MO_GOTOFF;
7931 else if (Subtarget->isPICStyleStubPIC())
7932 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7934 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7936 CP->getOffset(), OpFlag);
7938 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7939 // With PIC, the address is actually $g + Offset.
7941 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7942 DAG.getNode(X86ISD::GlobalBaseReg,
7943 SDLoc(), getPointerTy()),
7950 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7951 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7953 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7955 unsigned char OpFlag = 0;
7956 unsigned WrapperKind = X86ISD::Wrapper;
7957 CodeModel::Model M = getTargetMachine().getCodeModel();
7959 if (Subtarget->isPICStyleRIPRel() &&
7960 (M == CodeModel::Small || M == CodeModel::Kernel))
7961 WrapperKind = X86ISD::WrapperRIP;
7962 else if (Subtarget->isPICStyleGOT())
7963 OpFlag = X86II::MO_GOTOFF;
7964 else if (Subtarget->isPICStyleStubPIC())
7965 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7967 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7970 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7972 // With PIC, the address is actually $g + Offset.
7974 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7975 DAG.getNode(X86ISD::GlobalBaseReg,
7976 SDLoc(), getPointerTy()),
7983 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7984 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7986 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7988 unsigned char OpFlag = 0;
7989 unsigned WrapperKind = X86ISD::Wrapper;
7990 CodeModel::Model M = getTargetMachine().getCodeModel();
7992 if (Subtarget->isPICStyleRIPRel() &&
7993 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7994 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7995 OpFlag = X86II::MO_GOTPCREL;
7996 WrapperKind = X86ISD::WrapperRIP;
7997 } else if (Subtarget->isPICStyleGOT()) {
7998 OpFlag = X86II::MO_GOT;
7999 } else if (Subtarget->isPICStyleStubPIC()) {
8000 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8001 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8002 OpFlag = X86II::MO_DARWIN_NONLAZY;
8005 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8008 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8010 // With PIC, the address is actually $g + Offset.
8011 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8012 !Subtarget->is64Bit()) {
8013 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8014 DAG.getNode(X86ISD::GlobalBaseReg,
8015 SDLoc(), getPointerTy()),
8019 // For symbols that require a load from a stub to get the address, emit the
8021 if (isGlobalStubReference(OpFlag))
8022 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8023 MachinePointerInfo::getGOT(), false, false, false, 0);
8029 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8030 // Create the TargetBlockAddressAddress node.
8031 unsigned char OpFlags =
8032 Subtarget->ClassifyBlockAddressReference();
8033 CodeModel::Model M = getTargetMachine().getCodeModel();
8034 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8035 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8037 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8040 if (Subtarget->isPICStyleRIPRel() &&
8041 (M == CodeModel::Small || M == CodeModel::Kernel))
8042 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8044 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8046 // With PIC, the address is actually $g + Offset.
8047 if (isGlobalRelativeToPICBase(OpFlags)) {
8048 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8049 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8057 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8058 int64_t Offset, SelectionDAG &DAG) const {
8059 // Create the TargetGlobalAddress node, folding in the constant
8060 // offset if it is legal.
8061 unsigned char OpFlags =
8062 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8063 CodeModel::Model M = getTargetMachine().getCodeModel();
8065 if (OpFlags == X86II::MO_NO_FLAG &&
8066 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8067 // A direct static reference to a global.
8068 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8071 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8074 if (Subtarget->isPICStyleRIPRel() &&
8075 (M == CodeModel::Small || M == CodeModel::Kernel))
8076 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8078 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8080 // With PIC, the address is actually $g + Offset.
8081 if (isGlobalRelativeToPICBase(OpFlags)) {
8082 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8083 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8087 // For globals that require a load from a stub to get the address, emit the
8089 if (isGlobalStubReference(OpFlags))
8090 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8091 MachinePointerInfo::getGOT(), false, false, false, 0);
8093 // If there was a non-zero offset that we didn't fold, create an explicit
8096 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8097 DAG.getConstant(Offset, getPointerTy()));
8103 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8104 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8105 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8106 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8110 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8111 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8112 unsigned char OperandFlags, bool LocalDynamic = false) {
8113 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8114 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8116 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8117 GA->getValueType(0),
8121 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8125 SDValue Ops[] = { Chain, TGA, *InFlag };
8126 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8128 SDValue Ops[] = { Chain, TGA };
8129 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8132 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8133 MFI->setAdjustsStack(true);
8135 SDValue Flag = Chain.getValue(1);
8136 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8139 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8141 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8144 SDLoc dl(GA); // ? function entry point might be better
8145 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8146 DAG.getNode(X86ISD::GlobalBaseReg,
8147 SDLoc(), PtrVT), InFlag);
8148 InFlag = Chain.getValue(1);
8150 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8153 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8155 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8157 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8158 X86::RAX, X86II::MO_TLSGD);
8161 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8167 // Get the start address of the TLS block for this module.
8168 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8169 .getInfo<X86MachineFunctionInfo>();
8170 MFI->incNumLocalDynamicTLSAccesses();
8174 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8175 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8178 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8179 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8180 InFlag = Chain.getValue(1);
8181 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8182 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8185 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8189 unsigned char OperandFlags = X86II::MO_DTPOFF;
8190 unsigned WrapperKind = X86ISD::Wrapper;
8191 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8192 GA->getValueType(0),
8193 GA->getOffset(), OperandFlags);
8194 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8196 // Add x@dtpoff with the base.
8197 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8200 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8201 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8202 const EVT PtrVT, TLSModel::Model model,
8203 bool is64Bit, bool isPIC) {
8206 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8207 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8208 is64Bit ? 257 : 256));
8210 SDValue ThreadPointer =
8211 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8212 MachinePointerInfo(Ptr), false, false, false, 0);
8214 unsigned char OperandFlags = 0;
8215 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8217 unsigned WrapperKind = X86ISD::Wrapper;
8218 if (model == TLSModel::LocalExec) {
8219 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8220 } else if (model == TLSModel::InitialExec) {
8222 OperandFlags = X86II::MO_GOTTPOFF;
8223 WrapperKind = X86ISD::WrapperRIP;
8225 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8228 llvm_unreachable("Unexpected model");
8231 // emit "addl x@ntpoff,%eax" (local exec)
8232 // or "addl x@indntpoff,%eax" (initial exec)
8233 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8235 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8236 GA->getOffset(), OperandFlags);
8237 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8239 if (model == TLSModel::InitialExec) {
8240 if (isPIC && !is64Bit) {
8241 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8242 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8246 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8247 MachinePointerInfo::getGOT(), false, false, false, 0);
8250 // The address of the thread local variable is the add of the thread
8251 // pointer with the offset of the variable.
8252 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8256 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8258 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8259 const GlobalValue *GV = GA->getGlobal();
8261 if (Subtarget->isTargetELF()) {
8262 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8265 case TLSModel::GeneralDynamic:
8266 if (Subtarget->is64Bit())
8267 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8268 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8269 case TLSModel::LocalDynamic:
8270 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8271 Subtarget->is64Bit());
8272 case TLSModel::InitialExec:
8273 case TLSModel::LocalExec:
8274 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8275 Subtarget->is64Bit(),
8276 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8278 llvm_unreachable("Unknown TLS model.");
8281 if (Subtarget->isTargetDarwin()) {
8282 // Darwin only has one model of TLS. Lower to that.
8283 unsigned char OpFlag = 0;
8284 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8285 X86ISD::WrapperRIP : X86ISD::Wrapper;
8287 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8289 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8290 !Subtarget->is64Bit();
8292 OpFlag = X86II::MO_TLVP_PIC_BASE;
8294 OpFlag = X86II::MO_TLVP;
8296 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8297 GA->getValueType(0),
8298 GA->getOffset(), OpFlag);
8299 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8301 // With PIC32, the address is actually $g + Offset.
8303 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8304 DAG.getNode(X86ISD::GlobalBaseReg,
8305 SDLoc(), getPointerTy()),
8308 // Lowering the machine isd will make sure everything is in the right
8310 SDValue Chain = DAG.getEntryNode();
8311 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8312 SDValue Args[] = { Chain, Offset };
8313 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8315 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8316 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8317 MFI->setAdjustsStack(true);
8319 // And our return value (tls address) is in the standard call return value
8321 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8322 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8326 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8327 // Just use the implicit TLS architecture
8328 // Need to generate someting similar to:
8329 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8331 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8332 // mov rcx, qword [rdx+rcx*8]
8333 // mov eax, .tls$:tlsvar
8334 // [rax+rcx] contains the address
8335 // Windows 64bit: gs:0x58
8336 // Windows 32bit: fs:__tls_array
8338 // If GV is an alias then use the aliasee for determining
8339 // thread-localness.
8340 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8341 GV = GA->resolveAliasedGlobal(false);
8343 SDValue Chain = DAG.getEntryNode();
8345 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8346 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8347 // use its literal value of 0x2C.
8348 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8349 ? Type::getInt8PtrTy(*DAG.getContext(),
8351 : Type::getInt32PtrTy(*DAG.getContext(),
8354 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8355 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8356 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8358 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8359 MachinePointerInfo(Ptr),
8360 false, false, false, 0);
8362 // Load the _tls_index variable
8363 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8364 if (Subtarget->is64Bit())
8365 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8366 IDX, MachinePointerInfo(), MVT::i32,
8369 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8370 false, false, false, 0);
8372 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8374 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8376 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8377 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8378 false, false, false, 0);
8380 // Get the offset of start of .tls section
8381 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8382 GA->getValueType(0),
8383 GA->getOffset(), X86II::MO_SECREL);
8384 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8386 // The address of the thread local variable is the add of the thread
8387 // pointer with the offset of the variable.
8388 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8391 llvm_unreachable("TLS not implemented for this target.");
8394 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8395 /// and take a 2 x i32 value to shift plus a shift amount.
8396 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8397 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8398 EVT VT = Op.getValueType();
8399 unsigned VTBits = VT.getSizeInBits();
8401 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8402 SDValue ShOpLo = Op.getOperand(0);
8403 SDValue ShOpHi = Op.getOperand(1);
8404 SDValue ShAmt = Op.getOperand(2);
8405 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8406 DAG.getConstant(VTBits - 1, MVT::i8))
8407 : DAG.getConstant(0, VT);
8410 if (Op.getOpcode() == ISD::SHL_PARTS) {
8411 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8412 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8414 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8415 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8418 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8419 DAG.getConstant(VTBits, MVT::i8));
8420 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8421 AndNode, DAG.getConstant(0, MVT::i8));
8424 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8425 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8426 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8428 if (Op.getOpcode() == ISD::SHL_PARTS) {
8429 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8430 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8432 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8433 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8436 SDValue Ops[2] = { Lo, Hi };
8437 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8440 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8441 SelectionDAG &DAG) const {
8442 EVT SrcVT = Op.getOperand(0).getValueType();
8444 if (SrcVT.isVector())
8447 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8448 "Unknown SINT_TO_FP to lower!");
8450 // These are really Legal; return the operand so the caller accepts it as
8452 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8454 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8455 Subtarget->is64Bit()) {
8460 unsigned Size = SrcVT.getSizeInBits()/8;
8461 MachineFunction &MF = DAG.getMachineFunction();
8462 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8463 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8464 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8466 MachinePointerInfo::getFixedStack(SSFI),
8468 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8471 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8473 SelectionDAG &DAG) const {
8477 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8479 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8481 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8483 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8485 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8486 MachineMemOperand *MMO;
8488 int SSFI = FI->getIndex();
8490 DAG.getMachineFunction()
8491 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8492 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8494 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8495 StackSlot = StackSlot.getOperand(1);
8497 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8498 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8500 Tys, Ops, array_lengthof(Ops),
8504 Chain = Result.getValue(1);
8505 SDValue InFlag = Result.getValue(2);
8507 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8508 // shouldn't be necessary except that RFP cannot be live across
8509 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8510 MachineFunction &MF = DAG.getMachineFunction();
8511 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8512 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8513 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8514 Tys = DAG.getVTList(MVT::Other);
8516 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8518 MachineMemOperand *MMO =
8519 DAG.getMachineFunction()
8520 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8521 MachineMemOperand::MOStore, SSFISize, SSFISize);
8523 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8524 Ops, array_lengthof(Ops),
8525 Op.getValueType(), MMO);
8526 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8527 MachinePointerInfo::getFixedStack(SSFI),
8528 false, false, false, 0);
8534 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8535 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8536 SelectionDAG &DAG) const {
8537 // This algorithm is not obvious. Here it is what we're trying to output:
8540 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8541 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8545 pshufd $0x4e, %xmm0, %xmm1
8551 LLVMContext *Context = DAG.getContext();
8553 // Build some magic constants.
8554 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8555 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8556 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8558 SmallVector<Constant*,2> CV1;
8560 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8561 APInt(64, 0x4330000000000000ULL))));
8563 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8564 APInt(64, 0x4530000000000000ULL))));
8565 Constant *C1 = ConstantVector::get(CV1);
8566 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8568 // Load the 64-bit value into an XMM register.
8569 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8571 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8572 MachinePointerInfo::getConstantPool(),
8573 false, false, false, 16);
8574 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8575 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8578 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8579 MachinePointerInfo::getConstantPool(),
8580 false, false, false, 16);
8581 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8582 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8585 if (Subtarget->hasSSE3()) {
8586 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8587 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8589 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8590 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8592 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8593 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8597 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8598 DAG.getIntPtrConstant(0));
8601 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8602 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8603 SelectionDAG &DAG) const {
8605 // FP constant to bias correct the final result.
8606 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8609 // Load the 32-bit value into an XMM register.
8610 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8613 // Zero out the upper parts of the register.
8614 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8616 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8617 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8618 DAG.getIntPtrConstant(0));
8620 // Or the load with the bias.
8621 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8622 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8623 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8625 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8626 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8627 MVT::v2f64, Bias)));
8628 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8629 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8630 DAG.getIntPtrConstant(0));
8632 // Subtract the bias.
8633 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8635 // Handle final rounding.
8636 EVT DestVT = Op.getValueType();
8638 if (DestVT.bitsLT(MVT::f64))
8639 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8640 DAG.getIntPtrConstant(0));
8641 if (DestVT.bitsGT(MVT::f64))
8642 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8644 // Handle final rounding.
8648 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8649 SelectionDAG &DAG) const {
8650 SDValue N0 = Op.getOperand(0);
8651 EVT SVT = N0.getValueType();
8654 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8655 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8656 "Custom UINT_TO_FP is not supported!");
8658 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8659 SVT.getVectorNumElements());
8660 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8661 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8664 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8665 SelectionDAG &DAG) const {
8666 SDValue N0 = Op.getOperand(0);
8669 if (Op.getValueType().isVector())
8670 return lowerUINT_TO_FP_vec(Op, DAG);
8672 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8673 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8674 // the optimization here.
8675 if (DAG.SignBitIsZero(N0))
8676 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8678 EVT SrcVT = N0.getValueType();
8679 EVT DstVT = Op.getValueType();
8680 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8681 return LowerUINT_TO_FP_i64(Op, DAG);
8682 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8683 return LowerUINT_TO_FP_i32(Op, DAG);
8684 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8687 // Make a 64-bit buffer, and use it to build an FILD.
8688 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8689 if (SrcVT == MVT::i32) {
8690 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8691 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8692 getPointerTy(), StackSlot, WordOff);
8693 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8694 StackSlot, MachinePointerInfo(),
8696 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8697 OffsetSlot, MachinePointerInfo(),
8699 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8703 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8704 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8705 StackSlot, MachinePointerInfo(),
8707 // For i64 source, we need to add the appropriate power of 2 if the input
8708 // was negative. This is the same as the optimization in
8709 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8710 // we must be careful to do the computation in x87 extended precision, not
8711 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8712 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8713 MachineMemOperand *MMO =
8714 DAG.getMachineFunction()
8715 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8716 MachineMemOperand::MOLoad, 8, 8);
8718 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8719 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8720 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8721 array_lengthof(Ops), MVT::i64, MMO);
8723 APInt FF(32, 0x5F800000ULL);
8725 // Check whether the sign bit is set.
8726 SDValue SignSet = DAG.getSetCC(dl,
8727 getSetCCResultType(*DAG.getContext(), MVT::i64),
8728 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8731 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8732 SDValue FudgePtr = DAG.getConstantPool(
8733 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8736 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8737 SDValue Zero = DAG.getIntPtrConstant(0);
8738 SDValue Four = DAG.getIntPtrConstant(4);
8739 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8741 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8743 // Load the value out, extending it from f32 to f80.
8744 // FIXME: Avoid the extend by constructing the right constant pool?
8745 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8746 FudgePtr, MachinePointerInfo::getConstantPool(),
8747 MVT::f32, false, false, 4);
8748 // Extend everything to 80 bits to force it to be done on x87.
8749 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8750 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8753 std::pair<SDValue,SDValue>
8754 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8755 bool IsSigned, bool IsReplace) const {
8758 EVT DstTy = Op.getValueType();
8760 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8761 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8765 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8766 DstTy.getSimpleVT() >= MVT::i16 &&
8767 "Unknown FP_TO_INT to lower!");
8769 // These are really Legal.
8770 if (DstTy == MVT::i32 &&
8771 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8772 return std::make_pair(SDValue(), SDValue());
8773 if (Subtarget->is64Bit() &&
8774 DstTy == MVT::i64 &&
8775 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8776 return std::make_pair(SDValue(), SDValue());
8778 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8779 // stack slot, or into the FTOL runtime function.
8780 MachineFunction &MF = DAG.getMachineFunction();
8781 unsigned MemSize = DstTy.getSizeInBits()/8;
8782 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8783 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8786 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8787 Opc = X86ISD::WIN_FTOL;
8789 switch (DstTy.getSimpleVT().SimpleTy) {
8790 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8791 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8792 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8793 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8796 SDValue Chain = DAG.getEntryNode();
8797 SDValue Value = Op.getOperand(0);
8798 EVT TheVT = Op.getOperand(0).getValueType();
8799 // FIXME This causes a redundant load/store if the SSE-class value is already
8800 // in memory, such as if it is on the callstack.
8801 if (isScalarFPTypeInSSEReg(TheVT)) {
8802 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8803 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8804 MachinePointerInfo::getFixedStack(SSFI),
8806 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8808 Chain, StackSlot, DAG.getValueType(TheVT)
8811 MachineMemOperand *MMO =
8812 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8813 MachineMemOperand::MOLoad, MemSize, MemSize);
8814 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8815 array_lengthof(Ops), DstTy, MMO);
8816 Chain = Value.getValue(1);
8817 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8818 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8821 MachineMemOperand *MMO =
8822 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8823 MachineMemOperand::MOStore, MemSize, MemSize);
8825 if (Opc != X86ISD::WIN_FTOL) {
8826 // Build the FP_TO_INT*_IN_MEM
8827 SDValue Ops[] = { Chain, Value, StackSlot };
8828 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8829 Ops, array_lengthof(Ops), DstTy,
8831 return std::make_pair(FIST, StackSlot);
8833 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8834 DAG.getVTList(MVT::Other, MVT::Glue),
8836 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8837 MVT::i32, ftol.getValue(1));
8838 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8839 MVT::i32, eax.getValue(2));
8840 SDValue Ops[] = { eax, edx };
8841 SDValue pair = IsReplace
8842 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8843 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8844 return std::make_pair(pair, SDValue());
8848 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8849 const X86Subtarget *Subtarget) {
8850 MVT VT = Op->getSimpleValueType(0);
8851 SDValue In = Op->getOperand(0);
8852 MVT InVT = In.getSimpleValueType();
8855 // Optimize vectors in AVX mode:
8858 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8859 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8860 // Concat upper and lower parts.
8863 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8864 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8865 // Concat upper and lower parts.
8868 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8869 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8870 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8873 if (Subtarget->hasInt256())
8874 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8876 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8877 SDValue Undef = DAG.getUNDEF(InVT);
8878 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8879 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8880 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8882 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8883 VT.getVectorNumElements()/2);
8885 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8886 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8888 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8891 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8892 SelectionDAG &DAG) {
8893 MVT VT = Op->getValueType(0).getSimpleVT();
8894 SDValue In = Op->getOperand(0);
8895 MVT InVT = In.getValueType().getSimpleVT();
8897 unsigned int NumElts = VT.getVectorNumElements();
8898 if (NumElts != 8 && NumElts != 16)
8901 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8902 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8904 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8906 // Now we have only mask extension
8907 assert(InVT.getVectorElementType() == MVT::i1);
8908 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8909 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8910 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8911 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8912 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8913 MachinePointerInfo::getConstantPool(),
8914 false, false, false, Alignment);
8916 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8917 if (VT.is512BitVector())
8919 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8922 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8923 SelectionDAG &DAG) {
8924 if (Subtarget->hasFp256()) {
8925 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8933 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8934 SelectionDAG &DAG) {
8936 MVT VT = Op.getSimpleValueType();
8937 SDValue In = Op.getOperand(0);
8938 MVT SVT = In.getSimpleValueType();
8940 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8941 return LowerZERO_EXTEND_AVX512(Op, DAG);
8943 if (Subtarget->hasFp256()) {
8944 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8949 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
8950 VT.getVectorNumElements() != SVT.getVectorNumElements());
8954 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8956 MVT VT = Op.getSimpleValueType();
8957 SDValue In = Op.getOperand(0);
8958 MVT InVT = In.getSimpleValueType();
8959 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8960 "Invalid TRUNCATE operation");
8962 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
8963 if (VT.getVectorElementType().getSizeInBits() >=8)
8964 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
8966 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
8967 unsigned NumElts = InVT.getVectorNumElements();
8968 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
8969 if (InVT.getSizeInBits() < 512) {
8970 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
8971 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
8974 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
8975 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8976 SDValue CP = DAG.getConstantPool(C, getPointerTy());
8977 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8978 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8979 MachinePointerInfo::getConstantPool(),
8980 false, false, false, Alignment);
8981 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
8982 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
8983 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
8986 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
8987 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8988 if (Subtarget->hasInt256()) {
8989 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8990 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8991 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8993 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8994 DAG.getIntPtrConstant(0));
8997 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8998 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8999 DAG.getIntPtrConstant(0));
9000 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9001 DAG.getIntPtrConstant(2));
9003 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9004 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9007 static const int ShufMask1[] = {0, 2, 0, 0};
9008 SDValue Undef = DAG.getUNDEF(VT);
9009 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9010 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9012 // The MOVLHPS mask:
9013 static const int ShufMask2[] = {0, 1, 4, 5};
9014 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9017 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9018 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9019 if (Subtarget->hasInt256()) {
9020 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9022 SmallVector<SDValue,32> pshufbMask;
9023 for (unsigned i = 0; i < 2; ++i) {
9024 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9025 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9026 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9027 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9028 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9029 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9030 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9031 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9032 for (unsigned j = 0; j < 8; ++j)
9033 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9035 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9036 &pshufbMask[0], 32);
9037 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9038 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9040 static const int ShufMask[] = {0, 2, -1, -1};
9041 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9043 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9044 DAG.getIntPtrConstant(0));
9045 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9048 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9049 DAG.getIntPtrConstant(0));
9051 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9052 DAG.getIntPtrConstant(4));
9054 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9055 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9058 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9059 -1, -1, -1, -1, -1, -1, -1, -1};
9061 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9062 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9063 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9065 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9066 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9068 // The MOVLHPS Mask:
9069 static const int ShufMask2[] = {0, 1, 4, 5};
9070 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9071 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9074 // Handle truncation of V256 to V128 using shuffles.
9075 if (!VT.is128BitVector() || !InVT.is256BitVector())
9078 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9080 unsigned NumElems = VT.getVectorNumElements();
9081 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9084 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9085 // Prepare truncation shuffle mask
9086 for (unsigned i = 0; i != NumElems; ++i)
9088 SDValue V = DAG.getVectorShuffle(NVT, DL,
9089 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9090 DAG.getUNDEF(NVT), &MaskVec[0]);
9091 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9092 DAG.getIntPtrConstant(0));
9095 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9096 SelectionDAG &DAG) const {
9097 MVT VT = Op.getSimpleValueType();
9098 if (VT.isVector()) {
9099 if (VT == MVT::v8i16)
9100 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9101 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9102 MVT::v8i32, Op.getOperand(0)));
9106 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9107 /*IsSigned=*/ true, /*IsReplace=*/ false);
9108 SDValue FIST = Vals.first, StackSlot = Vals.second;
9109 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9110 if (FIST.getNode() == 0) return Op;
9112 if (StackSlot.getNode())
9114 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9115 FIST, StackSlot, MachinePointerInfo(),
9116 false, false, false, 0);
9118 // The node is the result.
9122 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9123 SelectionDAG &DAG) const {
9124 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9125 /*IsSigned=*/ false, /*IsReplace=*/ false);
9126 SDValue FIST = Vals.first, StackSlot = Vals.second;
9127 assert(FIST.getNode() && "Unexpected failure");
9129 if (StackSlot.getNode())
9131 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9132 FIST, StackSlot, MachinePointerInfo(),
9133 false, false, false, 0);
9135 // The node is the result.
9139 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9141 MVT VT = Op.getSimpleValueType();
9142 SDValue In = Op.getOperand(0);
9143 MVT SVT = In.getSimpleValueType();
9145 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9147 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9148 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9149 In, DAG.getUNDEF(SVT)));
9152 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9153 LLVMContext *Context = DAG.getContext();
9155 MVT VT = Op.getSimpleValueType();
9157 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9158 if (VT.isVector()) {
9159 EltVT = VT.getVectorElementType();
9160 NumElts = VT.getVectorNumElements();
9163 if (EltVT == MVT::f64)
9164 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9165 APInt(64, ~(1ULL << 63))));
9167 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9168 APInt(32, ~(1U << 31))));
9169 C = ConstantVector::getSplat(NumElts, C);
9170 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9171 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9172 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9173 MachinePointerInfo::getConstantPool(),
9174 false, false, false, Alignment);
9175 if (VT.isVector()) {
9176 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9177 return DAG.getNode(ISD::BITCAST, dl, VT,
9178 DAG.getNode(ISD::AND, dl, ANDVT,
9179 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9181 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9183 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9186 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9187 LLVMContext *Context = DAG.getContext();
9189 MVT VT = Op.getSimpleValueType();
9191 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9192 if (VT.isVector()) {
9193 EltVT = VT.getVectorElementType();
9194 NumElts = VT.getVectorNumElements();
9197 if (EltVT == MVT::f64)
9198 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9199 APInt(64, 1ULL << 63)));
9201 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9202 APInt(32, 1U << 31)));
9203 C = ConstantVector::getSplat(NumElts, C);
9204 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9205 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9206 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9207 MachinePointerInfo::getConstantPool(),
9208 false, false, false, Alignment);
9209 if (VT.isVector()) {
9210 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9211 return DAG.getNode(ISD::BITCAST, dl, VT,
9212 DAG.getNode(ISD::XOR, dl, XORVT,
9213 DAG.getNode(ISD::BITCAST, dl, XORVT,
9215 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9218 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9221 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9222 LLVMContext *Context = DAG.getContext();
9223 SDValue Op0 = Op.getOperand(0);
9224 SDValue Op1 = Op.getOperand(1);
9226 MVT VT = Op.getSimpleValueType();
9227 MVT SrcVT = Op1.getSimpleValueType();
9229 // If second operand is smaller, extend it first.
9230 if (SrcVT.bitsLT(VT)) {
9231 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9234 // And if it is bigger, shrink it first.
9235 if (SrcVT.bitsGT(VT)) {
9236 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9240 // At this point the operands and the result should have the same
9241 // type, and that won't be f80 since that is not custom lowered.
9243 // First get the sign bit of second operand.
9244 SmallVector<Constant*,4> CV;
9245 if (SrcVT == MVT::f64) {
9246 const fltSemantics &Sem = APFloat::IEEEdouble;
9247 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9248 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9250 const fltSemantics &Sem = APFloat::IEEEsingle;
9251 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9252 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9253 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9254 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9256 Constant *C = ConstantVector::get(CV);
9257 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9258 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9259 MachinePointerInfo::getConstantPool(),
9260 false, false, false, 16);
9261 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9263 // Shift sign bit right or left if the two operands have different types.
9264 if (SrcVT.bitsGT(VT)) {
9265 // Op0 is MVT::f32, Op1 is MVT::f64.
9266 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9267 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9268 DAG.getConstant(32, MVT::i32));
9269 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9270 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9271 DAG.getIntPtrConstant(0));
9274 // Clear first operand sign bit.
9276 if (VT == MVT::f64) {
9277 const fltSemantics &Sem = APFloat::IEEEdouble;
9278 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9279 APInt(64, ~(1ULL << 63)))));
9280 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9282 const fltSemantics &Sem = APFloat::IEEEsingle;
9283 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9284 APInt(32, ~(1U << 31)))));
9285 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9286 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9287 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9289 C = ConstantVector::get(CV);
9290 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9291 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9292 MachinePointerInfo::getConstantPool(),
9293 false, false, false, 16);
9294 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9296 // Or the value with the sign bit.
9297 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9300 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9301 SDValue N0 = Op.getOperand(0);
9303 MVT VT = Op.getSimpleValueType();
9305 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9306 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9307 DAG.getConstant(1, VT));
9308 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9311 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9313 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9314 SelectionDAG &DAG) {
9315 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9317 if (!Subtarget->hasSSE41())
9320 if (!Op->hasOneUse())
9323 SDNode *N = Op.getNode();
9326 SmallVector<SDValue, 8> Opnds;
9327 DenseMap<SDValue, unsigned> VecInMap;
9328 EVT VT = MVT::Other;
9330 // Recognize a special case where a vector is casted into wide integer to
9332 Opnds.push_back(N->getOperand(0));
9333 Opnds.push_back(N->getOperand(1));
9335 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9336 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9337 // BFS traverse all OR'd operands.
9338 if (I->getOpcode() == ISD::OR) {
9339 Opnds.push_back(I->getOperand(0));
9340 Opnds.push_back(I->getOperand(1));
9341 // Re-evaluate the number of nodes to be traversed.
9342 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9346 // Quit if a non-EXTRACT_VECTOR_ELT
9347 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9350 // Quit if without a constant index.
9351 SDValue Idx = I->getOperand(1);
9352 if (!isa<ConstantSDNode>(Idx))
9355 SDValue ExtractedFromVec = I->getOperand(0);
9356 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9357 if (M == VecInMap.end()) {
9358 VT = ExtractedFromVec.getValueType();
9359 // Quit if not 128/256-bit vector.
9360 if (!VT.is128BitVector() && !VT.is256BitVector())
9362 // Quit if not the same type.
9363 if (VecInMap.begin() != VecInMap.end() &&
9364 VT != VecInMap.begin()->first.getValueType())
9366 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9368 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9371 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9372 "Not extracted from 128-/256-bit vector.");
9374 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9375 SmallVector<SDValue, 8> VecIns;
9377 for (DenseMap<SDValue, unsigned>::const_iterator
9378 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9379 // Quit if not all elements are used.
9380 if (I->second != FullMask)
9382 VecIns.push_back(I->first);
9385 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9387 // Cast all vectors into TestVT for PTEST.
9388 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9389 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9391 // If more than one full vectors are evaluated, OR them first before PTEST.
9392 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9393 // Each iteration will OR 2 nodes and append the result until there is only
9394 // 1 node left, i.e. the final OR'd value of all vectors.
9395 SDValue LHS = VecIns[Slot];
9396 SDValue RHS = VecIns[Slot + 1];
9397 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9400 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9401 VecIns.back(), VecIns.back());
9404 /// Emit nodes that will be selected as "test Op0,Op0", or something
9406 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9407 SelectionDAG &DAG) const {
9410 // CF and OF aren't always set the way we want. Determine which
9411 // of these we need.
9412 bool NeedCF = false;
9413 bool NeedOF = false;
9416 case X86::COND_A: case X86::COND_AE:
9417 case X86::COND_B: case X86::COND_BE:
9420 case X86::COND_G: case X86::COND_GE:
9421 case X86::COND_L: case X86::COND_LE:
9422 case X86::COND_O: case X86::COND_NO:
9427 // See if we can use the EFLAGS value from the operand instead of
9428 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9429 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9430 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9431 // Emit a CMP with 0, which is the TEST pattern.
9432 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9433 DAG.getConstant(0, Op.getValueType()));
9435 unsigned Opcode = 0;
9436 unsigned NumOperands = 0;
9438 // Truncate operations may prevent the merge of the SETCC instruction
9439 // and the arithmetic instruction before it. Attempt to truncate the operands
9440 // of the arithmetic instruction and use a reduced bit-width instruction.
9441 bool NeedTruncation = false;
9442 SDValue ArithOp = Op;
9443 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9444 SDValue Arith = Op->getOperand(0);
9445 // Both the trunc and the arithmetic op need to have one user each.
9446 if (Arith->hasOneUse())
9447 switch (Arith.getOpcode()) {
9454 NeedTruncation = true;
9460 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9461 // which may be the result of a CAST. We use the variable 'Op', which is the
9462 // non-casted variable when we check for possible users.
9463 switch (ArithOp.getOpcode()) {
9465 // Due to an isel shortcoming, be conservative if this add is likely to be
9466 // selected as part of a load-modify-store instruction. When the root node
9467 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9468 // uses of other nodes in the match, such as the ADD in this case. This
9469 // leads to the ADD being left around and reselected, with the result being
9470 // two adds in the output. Alas, even if none our users are stores, that
9471 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9472 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9473 // climbing the DAG back to the root, and it doesn't seem to be worth the
9475 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9476 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9477 if (UI->getOpcode() != ISD::CopyToReg &&
9478 UI->getOpcode() != ISD::SETCC &&
9479 UI->getOpcode() != ISD::STORE)
9482 if (ConstantSDNode *C =
9483 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9484 // An add of one will be selected as an INC.
9485 if (C->getAPIntValue() == 1) {
9486 Opcode = X86ISD::INC;
9491 // An add of negative one (subtract of one) will be selected as a DEC.
9492 if (C->getAPIntValue().isAllOnesValue()) {
9493 Opcode = X86ISD::DEC;
9499 // Otherwise use a regular EFLAGS-setting add.
9500 Opcode = X86ISD::ADD;
9504 // If the primary and result isn't used, don't bother using X86ISD::AND,
9505 // because a TEST instruction will be better.
9506 bool NonFlagUse = false;
9507 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9508 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9510 unsigned UOpNo = UI.getOperandNo();
9511 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9512 // Look pass truncate.
9513 UOpNo = User->use_begin().getOperandNo();
9514 User = *User->use_begin();
9517 if (User->getOpcode() != ISD::BRCOND &&
9518 User->getOpcode() != ISD::SETCC &&
9519 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9532 // Due to the ISEL shortcoming noted above, be conservative if this op is
9533 // likely to be selected as part of a load-modify-store instruction.
9534 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9535 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9536 if (UI->getOpcode() == ISD::STORE)
9539 // Otherwise use a regular EFLAGS-setting instruction.
9540 switch (ArithOp.getOpcode()) {
9541 default: llvm_unreachable("unexpected operator!");
9542 case ISD::SUB: Opcode = X86ISD::SUB; break;
9543 case ISD::XOR: Opcode = X86ISD::XOR; break;
9544 case ISD::AND: Opcode = X86ISD::AND; break;
9546 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9547 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9548 if (EFLAGS.getNode())
9551 Opcode = X86ISD::OR;
9565 return SDValue(Op.getNode(), 1);
9571 // If we found that truncation is beneficial, perform the truncation and
9573 if (NeedTruncation) {
9574 EVT VT = Op.getValueType();
9575 SDValue WideVal = Op->getOperand(0);
9576 EVT WideVT = WideVal.getValueType();
9577 unsigned ConvertedOp = 0;
9578 // Use a target machine opcode to prevent further DAGCombine
9579 // optimizations that may separate the arithmetic operations
9580 // from the setcc node.
9581 switch (WideVal.getOpcode()) {
9583 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9584 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9585 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9586 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9587 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9591 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9592 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9593 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9594 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9595 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9601 // Emit a CMP with 0, which is the TEST pattern.
9602 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9603 DAG.getConstant(0, Op.getValueType()));
9605 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9606 SmallVector<SDValue, 4> Ops;
9607 for (unsigned i = 0; i != NumOperands; ++i)
9608 Ops.push_back(Op.getOperand(i));
9610 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9611 DAG.ReplaceAllUsesWith(Op, New);
9612 return SDValue(New.getNode(), 1);
9615 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9617 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9618 SelectionDAG &DAG) const {
9619 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9620 if (C->getAPIntValue() == 0)
9621 return EmitTest(Op0, X86CC, DAG);
9624 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9625 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9626 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9627 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9628 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9630 return SDValue(Sub.getNode(), 1);
9632 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9635 /// Convert a comparison if required by the subtarget.
9636 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9637 SelectionDAG &DAG) const {
9638 // If the subtarget does not support the FUCOMI instruction, floating-point
9639 // comparisons have to be converted.
9640 if (Subtarget->hasCMov() ||
9641 Cmp.getOpcode() != X86ISD::CMP ||
9642 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9643 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9646 // The instruction selector will select an FUCOM instruction instead of
9647 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9648 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9649 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9651 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9652 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9653 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9654 DAG.getConstant(8, MVT::i8));
9655 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9656 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9659 static bool isAllOnes(SDValue V) {
9660 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9661 return C && C->isAllOnesValue();
9664 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9665 /// if it's possible.
9666 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9667 SDLoc dl, SelectionDAG &DAG) const {
9668 SDValue Op0 = And.getOperand(0);
9669 SDValue Op1 = And.getOperand(1);
9670 if (Op0.getOpcode() == ISD::TRUNCATE)
9671 Op0 = Op0.getOperand(0);
9672 if (Op1.getOpcode() == ISD::TRUNCATE)
9673 Op1 = Op1.getOperand(0);
9676 if (Op1.getOpcode() == ISD::SHL)
9677 std::swap(Op0, Op1);
9678 if (Op0.getOpcode() == ISD::SHL) {
9679 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9680 if (And00C->getZExtValue() == 1) {
9681 // If we looked past a truncate, check that it's only truncating away
9683 unsigned BitWidth = Op0.getValueSizeInBits();
9684 unsigned AndBitWidth = And.getValueSizeInBits();
9685 if (BitWidth > AndBitWidth) {
9687 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9688 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9692 RHS = Op0.getOperand(1);
9694 } else if (Op1.getOpcode() == ISD::Constant) {
9695 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9696 uint64_t AndRHSVal = AndRHS->getZExtValue();
9697 SDValue AndLHS = Op0;
9699 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9700 LHS = AndLHS.getOperand(0);
9701 RHS = AndLHS.getOperand(1);
9704 // Use BT if the immediate can't be encoded in a TEST instruction.
9705 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9707 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9711 if (LHS.getNode()) {
9712 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9713 // instruction. Since the shift amount is in-range-or-undefined, we know
9714 // that doing a bittest on the i32 value is ok. We extend to i32 because
9715 // the encoding for the i16 version is larger than the i32 version.
9716 // Also promote i16 to i32 for performance / code size reason.
9717 if (LHS.getValueType() == MVT::i8 ||
9718 LHS.getValueType() == MVT::i16)
9719 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9721 // If the operand types disagree, extend the shift amount to match. Since
9722 // BT ignores high bits (like shifts) we can use anyextend.
9723 if (LHS.getValueType() != RHS.getValueType())
9724 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9726 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9727 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9728 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9729 DAG.getConstant(Cond, MVT::i8), BT);
9735 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9737 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9742 // SSE Condition code mapping:
9751 switch (SetCCOpcode) {
9752 default: llvm_unreachable("Unexpected SETCC condition");
9754 case ISD::SETEQ: SSECC = 0; break;
9756 case ISD::SETGT: Swap = true; // Fallthrough
9758 case ISD::SETOLT: SSECC = 1; break;
9760 case ISD::SETGE: Swap = true; // Fallthrough
9762 case ISD::SETOLE: SSECC = 2; break;
9763 case ISD::SETUO: SSECC = 3; break;
9765 case ISD::SETNE: SSECC = 4; break;
9766 case ISD::SETULE: Swap = true; // Fallthrough
9767 case ISD::SETUGE: SSECC = 5; break;
9768 case ISD::SETULT: Swap = true; // Fallthrough
9769 case ISD::SETUGT: SSECC = 6; break;
9770 case ISD::SETO: SSECC = 7; break;
9772 case ISD::SETONE: SSECC = 8; break;
9775 std::swap(Op0, Op1);
9780 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9781 // ones, and then concatenate the result back.
9782 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9783 MVT VT = Op.getSimpleValueType();
9785 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9786 "Unsupported value type for operation");
9788 unsigned NumElems = VT.getVectorNumElements();
9790 SDValue CC = Op.getOperand(2);
9792 // Extract the LHS vectors
9793 SDValue LHS = Op.getOperand(0);
9794 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9795 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9797 // Extract the RHS vectors
9798 SDValue RHS = Op.getOperand(1);
9799 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9800 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9802 // Issue the operation on the smaller types and concatenate the result back
9803 MVT EltVT = VT.getVectorElementType();
9804 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9805 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9806 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9807 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9810 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9811 SDValue Op0 = Op.getOperand(0);
9812 SDValue Op1 = Op.getOperand(1);
9813 SDValue CC = Op.getOperand(2);
9814 MVT VT = Op.getSimpleValueType();
9816 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9817 Op.getValueType().getScalarType() == MVT::i1 &&
9818 "Cannot set masked compare for this operation");
9820 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9823 bool Unsigned = false;
9825 switch (SetCCOpcode) {
9826 default: llvm_unreachable("Unexpected SETCC condition");
9827 case ISD::SETNE: SSECC = 4; break;
9828 case ISD::SETEQ: SSECC = 0; break;
9829 case ISD::SETUGT: Unsigned = true;
9830 case ISD::SETGT: SSECC = 6; break; // NLE
9831 case ISD::SETULT: Unsigned = true;
9832 case ISD::SETLT: SSECC = 1; break;
9833 case ISD::SETUGE: Unsigned = true;
9834 case ISD::SETGE: SSECC = 5; break; // NLT
9835 case ISD::SETULE: Unsigned = true;
9836 case ISD::SETLE: SSECC = 2; break;
9838 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9839 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9840 DAG.getConstant(SSECC, MVT::i8));
9844 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9845 SelectionDAG &DAG) {
9846 SDValue Op0 = Op.getOperand(0);
9847 SDValue Op1 = Op.getOperand(1);
9848 SDValue CC = Op.getOperand(2);
9849 MVT VT = Op.getSimpleValueType();
9850 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9851 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9856 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9857 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9860 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9861 unsigned Opc = X86ISD::CMPP;
9862 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9863 assert(VT.getVectorNumElements() <= 16);
9866 // In the two special cases we can't handle, emit two comparisons.
9869 unsigned CombineOpc;
9870 if (SetCCOpcode == ISD::SETUEQ) {
9871 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9873 assert(SetCCOpcode == ISD::SETONE);
9874 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9877 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9878 DAG.getConstant(CC0, MVT::i8));
9879 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9880 DAG.getConstant(CC1, MVT::i8));
9881 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9883 // Handle all other FP comparisons here.
9884 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9885 DAG.getConstant(SSECC, MVT::i8));
9888 // Break 256-bit integer vector compare into smaller ones.
9889 if (VT.is256BitVector() && !Subtarget->hasInt256())
9890 return Lower256IntVSETCC(Op, DAG);
9892 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9893 EVT OpVT = Op1.getValueType();
9894 if (Subtarget->hasAVX512()) {
9895 if (Op1.getValueType().is512BitVector() ||
9896 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9897 return LowerIntVSETCC_AVX512(Op, DAG);
9899 // In AVX-512 architecture setcc returns mask with i1 elements,
9900 // But there is no compare instruction for i8 and i16 elements.
9901 // We are not talking about 512-bit operands in this case, these
9902 // types are illegal.
9904 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9905 OpVT.getVectorElementType().getSizeInBits() >= 8))
9906 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9907 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9910 // We are handling one of the integer comparisons here. Since SSE only has
9911 // GT and EQ comparisons for integer, swapping operands and multiple
9912 // operations may be required for some comparisons.
9914 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9916 switch (SetCCOpcode) {
9917 default: llvm_unreachable("Unexpected SETCC condition");
9918 case ISD::SETNE: Invert = true;
9919 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9920 case ISD::SETLT: Swap = true;
9921 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9922 case ISD::SETGE: Swap = true;
9923 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9924 Invert = true; break;
9925 case ISD::SETULT: Swap = true;
9926 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9927 FlipSigns = true; break;
9928 case ISD::SETUGE: Swap = true;
9929 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9930 FlipSigns = true; Invert = true; break;
9933 // Special case: Use min/max operations for SETULE/SETUGE
9934 MVT VET = VT.getVectorElementType();
9936 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9937 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9940 switch (SetCCOpcode) {
9942 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9943 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9946 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9950 std::swap(Op0, Op1);
9952 // Check that the operation in question is available (most are plain SSE2,
9953 // but PCMPGTQ and PCMPEQQ have different requirements).
9954 if (VT == MVT::v2i64) {
9955 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9956 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9958 // First cast everything to the right type.
9959 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9960 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9962 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9963 // bits of the inputs before performing those operations. The lower
9964 // compare is always unsigned.
9967 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9969 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9970 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9971 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9972 Sign, Zero, Sign, Zero);
9974 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9975 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9977 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9978 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9979 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9981 // Create masks for only the low parts/high parts of the 64 bit integers.
9982 static const int MaskHi[] = { 1, 1, 3, 3 };
9983 static const int MaskLo[] = { 0, 0, 2, 2 };
9984 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9985 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9986 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9988 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9989 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9992 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9994 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9997 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9998 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9999 // pcmpeqd + pshufd + pand.
10000 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10002 // First cast everything to the right type.
10003 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10004 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10007 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10009 // Make sure the lower and upper halves are both all-ones.
10010 static const int Mask[] = { 1, 0, 3, 2 };
10011 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10012 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10015 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10017 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10021 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10022 // bits of the inputs before performing those operations.
10024 EVT EltVT = VT.getVectorElementType();
10025 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10026 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10027 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10030 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10032 // If the logical-not of the result is required, perform that now.
10034 Result = DAG.getNOT(dl, Result, VT);
10037 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10042 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10044 MVT VT = Op.getSimpleValueType();
10046 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10048 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10049 SDValue Op0 = Op.getOperand(0);
10050 SDValue Op1 = Op.getOperand(1);
10052 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10054 // Optimize to BT if possible.
10055 // Lower (X & (1 << N)) == 0 to BT(X, N).
10056 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10057 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10058 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10059 Op1.getOpcode() == ISD::Constant &&
10060 cast<ConstantSDNode>(Op1)->isNullValue() &&
10061 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10062 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10063 if (NewSetCC.getNode())
10067 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10069 if (Op1.getOpcode() == ISD::Constant &&
10070 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10071 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10072 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10074 // If the input is a setcc, then reuse the input setcc or use a new one with
10075 // the inverted condition.
10076 if (Op0.getOpcode() == X86ISD::SETCC) {
10077 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10078 bool Invert = (CC == ISD::SETNE) ^
10079 cast<ConstantSDNode>(Op1)->isNullValue();
10080 if (!Invert) return Op0;
10082 CCode = X86::GetOppositeBranchCondition(CCode);
10083 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10084 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10088 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10089 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10090 if (X86CC == X86::COND_INVALID)
10093 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10094 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10095 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10096 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10099 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10100 static bool isX86LogicalCmp(SDValue Op) {
10101 unsigned Opc = Op.getNode()->getOpcode();
10102 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10103 Opc == X86ISD::SAHF)
10105 if (Op.getResNo() == 1 &&
10106 (Opc == X86ISD::ADD ||
10107 Opc == X86ISD::SUB ||
10108 Opc == X86ISD::ADC ||
10109 Opc == X86ISD::SBB ||
10110 Opc == X86ISD::SMUL ||
10111 Opc == X86ISD::UMUL ||
10112 Opc == X86ISD::INC ||
10113 Opc == X86ISD::DEC ||
10114 Opc == X86ISD::OR ||
10115 Opc == X86ISD::XOR ||
10116 Opc == X86ISD::AND))
10119 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10125 static bool isZero(SDValue V) {
10126 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10127 return C && C->isNullValue();
10130 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10131 if (V.getOpcode() != ISD::TRUNCATE)
10134 SDValue VOp0 = V.getOperand(0);
10135 unsigned InBits = VOp0.getValueSizeInBits();
10136 unsigned Bits = V.getValueSizeInBits();
10137 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10140 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10141 bool addTest = true;
10142 SDValue Cond = Op.getOperand(0);
10143 SDValue Op1 = Op.getOperand(1);
10144 SDValue Op2 = Op.getOperand(2);
10146 EVT VT = Op1.getValueType();
10149 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10150 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10151 // sequence later on.
10152 if (Cond.getOpcode() == ISD::SETCC &&
10153 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10154 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10155 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10156 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10157 int SSECC = translateX86FSETCC(
10158 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10161 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10162 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10163 DAG.getConstant(SSECC, MVT::i8));
10164 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10165 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10166 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10170 if (Cond.getOpcode() == ISD::SETCC) {
10171 SDValue NewCond = LowerSETCC(Cond, DAG);
10172 if (NewCond.getNode())
10176 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10177 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10178 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10179 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10180 if (Cond.getOpcode() == X86ISD::SETCC &&
10181 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10182 isZero(Cond.getOperand(1).getOperand(1))) {
10183 SDValue Cmp = Cond.getOperand(1);
10185 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10187 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10188 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10189 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10191 SDValue CmpOp0 = Cmp.getOperand(0);
10192 // Apply further optimizations for special cases
10193 // (select (x != 0), -1, 0) -> neg & sbb
10194 // (select (x == 0), 0, -1) -> neg & sbb
10195 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10196 if (YC->isNullValue() &&
10197 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10198 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10199 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10200 DAG.getConstant(0, CmpOp0.getValueType()),
10202 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10203 DAG.getConstant(X86::COND_B, MVT::i8),
10204 SDValue(Neg.getNode(), 1));
10208 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10209 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10210 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10212 SDValue Res = // Res = 0 or -1.
10213 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10214 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10216 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10217 Res = DAG.getNOT(DL, Res, Res.getValueType());
10219 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10220 if (N2C == 0 || !N2C->isNullValue())
10221 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10226 // Look past (and (setcc_carry (cmp ...)), 1).
10227 if (Cond.getOpcode() == ISD::AND &&
10228 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10229 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10230 if (C && C->getAPIntValue() == 1)
10231 Cond = Cond.getOperand(0);
10234 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10235 // setting operand in place of the X86ISD::SETCC.
10236 unsigned CondOpcode = Cond.getOpcode();
10237 if (CondOpcode == X86ISD::SETCC ||
10238 CondOpcode == X86ISD::SETCC_CARRY) {
10239 CC = Cond.getOperand(0);
10241 SDValue Cmp = Cond.getOperand(1);
10242 unsigned Opc = Cmp.getOpcode();
10243 MVT VT = Op.getSimpleValueType();
10245 bool IllegalFPCMov = false;
10246 if (VT.isFloatingPoint() && !VT.isVector() &&
10247 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10248 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10250 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10251 Opc == X86ISD::BT) { // FIXME
10255 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10256 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10257 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10258 Cond.getOperand(0).getValueType() != MVT::i8)) {
10259 SDValue LHS = Cond.getOperand(0);
10260 SDValue RHS = Cond.getOperand(1);
10261 unsigned X86Opcode;
10264 switch (CondOpcode) {
10265 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10266 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10267 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10268 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10269 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10270 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10271 default: llvm_unreachable("unexpected overflowing operator");
10273 if (CondOpcode == ISD::UMULO)
10274 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10277 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10279 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10281 if (CondOpcode == ISD::UMULO)
10282 Cond = X86Op.getValue(2);
10284 Cond = X86Op.getValue(1);
10286 CC = DAG.getConstant(X86Cond, MVT::i8);
10291 // Look pass the truncate if the high bits are known zero.
10292 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10293 Cond = Cond.getOperand(0);
10295 // We know the result of AND is compared against zero. Try to match
10297 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10298 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10299 if (NewSetCC.getNode()) {
10300 CC = NewSetCC.getOperand(0);
10301 Cond = NewSetCC.getOperand(1);
10308 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10309 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10312 // a < b ? -1 : 0 -> RES = ~setcc_carry
10313 // a < b ? 0 : -1 -> RES = setcc_carry
10314 // a >= b ? -1 : 0 -> RES = setcc_carry
10315 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10316 if (Cond.getOpcode() == X86ISD::SUB) {
10317 Cond = ConvertCmpIfNecessary(Cond, DAG);
10318 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10320 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10321 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10322 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10323 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10324 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10325 return DAG.getNOT(DL, Res, Res.getValueType());
10330 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10331 // widen the cmov and push the truncate through. This avoids introducing a new
10332 // branch during isel and doesn't add any extensions.
10333 if (Op.getValueType() == MVT::i8 &&
10334 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10335 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10336 if (T1.getValueType() == T2.getValueType() &&
10337 // Blacklist CopyFromReg to avoid partial register stalls.
10338 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10339 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10340 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10341 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10345 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10346 // condition is true.
10347 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10348 SDValue Ops[] = { Op2, Op1, CC, Cond };
10349 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10352 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10353 MVT VT = Op->getSimpleValueType(0);
10354 SDValue In = Op->getOperand(0);
10355 MVT InVT = In.getSimpleValueType();
10358 unsigned int NumElts = VT.getVectorNumElements();
10359 if (NumElts != 8 && NumElts != 16)
10362 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10363 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10365 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10366 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10368 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10369 Constant *C = ConstantInt::get(*DAG.getContext(),
10370 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10372 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10373 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10374 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10375 MachinePointerInfo::getConstantPool(),
10376 false, false, false, Alignment);
10377 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10378 if (VT.is512BitVector())
10380 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10383 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10384 SelectionDAG &DAG) {
10385 MVT VT = Op->getSimpleValueType(0);
10386 SDValue In = Op->getOperand(0);
10387 MVT InVT = In.getSimpleValueType();
10390 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10391 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10393 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10394 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10397 if (Subtarget->hasInt256())
10398 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10400 // Optimize vectors in AVX mode
10401 // Sign extend v8i16 to v8i32 and
10404 // Divide input vector into two parts
10405 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10406 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10407 // concat the vectors to original VT
10409 unsigned NumElems = InVT.getVectorNumElements();
10410 SDValue Undef = DAG.getUNDEF(InVT);
10412 SmallVector<int,8> ShufMask1(NumElems, -1);
10413 for (unsigned i = 0; i != NumElems/2; ++i)
10416 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10418 SmallVector<int,8> ShufMask2(NumElems, -1);
10419 for (unsigned i = 0; i != NumElems/2; ++i)
10420 ShufMask2[i] = i + NumElems/2;
10422 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10424 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10425 VT.getVectorNumElements()/2);
10427 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10428 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10430 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10433 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10434 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10435 // from the AND / OR.
10436 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10437 Opc = Op.getOpcode();
10438 if (Opc != ISD::OR && Opc != ISD::AND)
10440 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10441 Op.getOperand(0).hasOneUse() &&
10442 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10443 Op.getOperand(1).hasOneUse());
10446 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10447 // 1 and that the SETCC node has a single use.
10448 static bool isXor1OfSetCC(SDValue Op) {
10449 if (Op.getOpcode() != ISD::XOR)
10451 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10452 if (N1C && N1C->getAPIntValue() == 1) {
10453 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10454 Op.getOperand(0).hasOneUse();
10459 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10460 bool addTest = true;
10461 SDValue Chain = Op.getOperand(0);
10462 SDValue Cond = Op.getOperand(1);
10463 SDValue Dest = Op.getOperand(2);
10466 bool Inverted = false;
10468 if (Cond.getOpcode() == ISD::SETCC) {
10469 // Check for setcc([su]{add,sub,mul}o == 0).
10470 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10471 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10472 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10473 Cond.getOperand(0).getResNo() == 1 &&
10474 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10475 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10476 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10477 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10478 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10479 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10481 Cond = Cond.getOperand(0);
10483 SDValue NewCond = LowerSETCC(Cond, DAG);
10484 if (NewCond.getNode())
10489 // FIXME: LowerXALUO doesn't handle these!!
10490 else if (Cond.getOpcode() == X86ISD::ADD ||
10491 Cond.getOpcode() == X86ISD::SUB ||
10492 Cond.getOpcode() == X86ISD::SMUL ||
10493 Cond.getOpcode() == X86ISD::UMUL)
10494 Cond = LowerXALUO(Cond, DAG);
10497 // Look pass (and (setcc_carry (cmp ...)), 1).
10498 if (Cond.getOpcode() == ISD::AND &&
10499 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10500 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10501 if (C && C->getAPIntValue() == 1)
10502 Cond = Cond.getOperand(0);
10505 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10506 // setting operand in place of the X86ISD::SETCC.
10507 unsigned CondOpcode = Cond.getOpcode();
10508 if (CondOpcode == X86ISD::SETCC ||
10509 CondOpcode == X86ISD::SETCC_CARRY) {
10510 CC = Cond.getOperand(0);
10512 SDValue Cmp = Cond.getOperand(1);
10513 unsigned Opc = Cmp.getOpcode();
10514 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10515 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10519 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10523 // These can only come from an arithmetic instruction with overflow,
10524 // e.g. SADDO, UADDO.
10525 Cond = Cond.getNode()->getOperand(1);
10531 CondOpcode = Cond.getOpcode();
10532 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10533 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10534 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10535 Cond.getOperand(0).getValueType() != MVT::i8)) {
10536 SDValue LHS = Cond.getOperand(0);
10537 SDValue RHS = Cond.getOperand(1);
10538 unsigned X86Opcode;
10541 switch (CondOpcode) {
10542 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10543 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10544 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10545 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10546 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10547 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10548 default: llvm_unreachable("unexpected overflowing operator");
10551 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10552 if (CondOpcode == ISD::UMULO)
10553 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10556 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10558 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10560 if (CondOpcode == ISD::UMULO)
10561 Cond = X86Op.getValue(2);
10563 Cond = X86Op.getValue(1);
10565 CC = DAG.getConstant(X86Cond, MVT::i8);
10569 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10570 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10571 if (CondOpc == ISD::OR) {
10572 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10573 // two branches instead of an explicit OR instruction with a
10575 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10576 isX86LogicalCmp(Cmp)) {
10577 CC = Cond.getOperand(0).getOperand(0);
10578 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10579 Chain, Dest, CC, Cmp);
10580 CC = Cond.getOperand(1).getOperand(0);
10584 } else { // ISD::AND
10585 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10586 // two branches instead of an explicit AND instruction with a
10587 // separate test. However, we only do this if this block doesn't
10588 // have a fall-through edge, because this requires an explicit
10589 // jmp when the condition is false.
10590 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10591 isX86LogicalCmp(Cmp) &&
10592 Op.getNode()->hasOneUse()) {
10593 X86::CondCode CCode =
10594 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10595 CCode = X86::GetOppositeBranchCondition(CCode);
10596 CC = DAG.getConstant(CCode, MVT::i8);
10597 SDNode *User = *Op.getNode()->use_begin();
10598 // Look for an unconditional branch following this conditional branch.
10599 // We need this because we need to reverse the successors in order
10600 // to implement FCMP_OEQ.
10601 if (User->getOpcode() == ISD::BR) {
10602 SDValue FalseBB = User->getOperand(1);
10604 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10605 assert(NewBR == User);
10609 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10610 Chain, Dest, CC, Cmp);
10611 X86::CondCode CCode =
10612 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10613 CCode = X86::GetOppositeBranchCondition(CCode);
10614 CC = DAG.getConstant(CCode, MVT::i8);
10620 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10621 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10622 // It should be transformed during dag combiner except when the condition
10623 // is set by a arithmetics with overflow node.
10624 X86::CondCode CCode =
10625 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10626 CCode = X86::GetOppositeBranchCondition(CCode);
10627 CC = DAG.getConstant(CCode, MVT::i8);
10628 Cond = Cond.getOperand(0).getOperand(1);
10630 } else if (Cond.getOpcode() == ISD::SETCC &&
10631 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10632 // For FCMP_OEQ, we can emit
10633 // two branches instead of an explicit AND instruction with a
10634 // separate test. However, we only do this if this block doesn't
10635 // have a fall-through edge, because this requires an explicit
10636 // jmp when the condition is false.
10637 if (Op.getNode()->hasOneUse()) {
10638 SDNode *User = *Op.getNode()->use_begin();
10639 // Look for an unconditional branch following this conditional branch.
10640 // We need this because we need to reverse the successors in order
10641 // to implement FCMP_OEQ.
10642 if (User->getOpcode() == ISD::BR) {
10643 SDValue FalseBB = User->getOperand(1);
10645 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10646 assert(NewBR == User);
10650 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10651 Cond.getOperand(0), Cond.getOperand(1));
10652 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10653 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10654 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10655 Chain, Dest, CC, Cmp);
10656 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10661 } else if (Cond.getOpcode() == ISD::SETCC &&
10662 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10663 // For FCMP_UNE, we can emit
10664 // two branches instead of an explicit AND instruction with a
10665 // separate test. However, we only do this if this block doesn't
10666 // have a fall-through edge, because this requires an explicit
10667 // jmp when the condition is false.
10668 if (Op.getNode()->hasOneUse()) {
10669 SDNode *User = *Op.getNode()->use_begin();
10670 // Look for an unconditional branch following this conditional branch.
10671 // We need this because we need to reverse the successors in order
10672 // to implement FCMP_UNE.
10673 if (User->getOpcode() == ISD::BR) {
10674 SDValue FalseBB = User->getOperand(1);
10676 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10677 assert(NewBR == User);
10680 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10681 Cond.getOperand(0), Cond.getOperand(1));
10682 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10683 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10684 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10685 Chain, Dest, CC, Cmp);
10686 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10696 // Look pass the truncate if the high bits are known zero.
10697 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10698 Cond = Cond.getOperand(0);
10700 // We know the result of AND is compared against zero. Try to match
10702 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10703 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10704 if (NewSetCC.getNode()) {
10705 CC = NewSetCC.getOperand(0);
10706 Cond = NewSetCC.getOperand(1);
10713 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10714 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10716 Cond = ConvertCmpIfNecessary(Cond, DAG);
10717 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10718 Chain, Dest, CC, Cond);
10721 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10722 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10723 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10724 // that the guard pages used by the OS virtual memory manager are allocated in
10725 // correct sequence.
10727 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10728 SelectionDAG &DAG) const {
10729 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10730 getTargetMachine().Options.EnableSegmentedStacks) &&
10731 "This should be used only on Windows targets or when segmented stacks "
10733 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10737 SDValue Chain = Op.getOperand(0);
10738 SDValue Size = Op.getOperand(1);
10739 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10740 EVT VT = Op.getNode()->getValueType(0);
10742 bool Is64Bit = Subtarget->is64Bit();
10743 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10745 if (getTargetMachine().Options.EnableSegmentedStacks) {
10746 MachineFunction &MF = DAG.getMachineFunction();
10747 MachineRegisterInfo &MRI = MF.getRegInfo();
10750 // The 64 bit implementation of segmented stacks needs to clobber both r10
10751 // r11. This makes it impossible to use it along with nested parameters.
10752 const Function *F = MF.getFunction();
10754 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10756 if (I->hasNestAttr())
10757 report_fatal_error("Cannot use segmented stacks with functions that "
10758 "have nested arguments.");
10761 const TargetRegisterClass *AddrRegClass =
10762 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10763 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10764 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10765 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10766 DAG.getRegister(Vreg, SPTy));
10767 SDValue Ops1[2] = { Value, Chain };
10768 return DAG.getMergeValues(Ops1, 2, dl);
10771 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10773 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10774 Flag = Chain.getValue(1);
10775 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10777 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10779 const X86RegisterInfo *RegInfo =
10780 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10781 unsigned SPReg = RegInfo->getStackRegister();
10782 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10783 Chain = SP.getValue(1);
10786 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10787 DAG.getConstant(-(uint64_t)Align, VT));
10788 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10791 SDValue Ops1[2] = { SP, Chain };
10792 return DAG.getMergeValues(Ops1, 2, dl);
10796 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10797 MachineFunction &MF = DAG.getMachineFunction();
10798 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10800 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10803 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10804 // vastart just stores the address of the VarArgsFrameIndex slot into the
10805 // memory location argument.
10806 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10808 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10809 MachinePointerInfo(SV), false, false, 0);
10813 // gp_offset (0 - 6 * 8)
10814 // fp_offset (48 - 48 + 8 * 16)
10815 // overflow_arg_area (point to parameters coming in memory).
10817 SmallVector<SDValue, 8> MemOps;
10818 SDValue FIN = Op.getOperand(1);
10820 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10821 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10823 FIN, MachinePointerInfo(SV), false, false, 0);
10824 MemOps.push_back(Store);
10827 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10828 FIN, DAG.getIntPtrConstant(4));
10829 Store = DAG.getStore(Op.getOperand(0), DL,
10830 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10832 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10833 MemOps.push_back(Store);
10835 // Store ptr to overflow_arg_area
10836 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10837 FIN, DAG.getIntPtrConstant(4));
10838 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10840 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10841 MachinePointerInfo(SV, 8),
10843 MemOps.push_back(Store);
10845 // Store ptr to reg_save_area.
10846 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10847 FIN, DAG.getIntPtrConstant(8));
10848 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10850 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10851 MachinePointerInfo(SV, 16), false, false, 0);
10852 MemOps.push_back(Store);
10853 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10854 &MemOps[0], MemOps.size());
10857 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10858 assert(Subtarget->is64Bit() &&
10859 "LowerVAARG only handles 64-bit va_arg!");
10860 assert((Subtarget->isTargetLinux() ||
10861 Subtarget->isTargetDarwin()) &&
10862 "Unhandled target in LowerVAARG");
10863 assert(Op.getNode()->getNumOperands() == 4);
10864 SDValue Chain = Op.getOperand(0);
10865 SDValue SrcPtr = Op.getOperand(1);
10866 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10867 unsigned Align = Op.getConstantOperandVal(3);
10870 EVT ArgVT = Op.getNode()->getValueType(0);
10871 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10872 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10875 // Decide which area this value should be read from.
10876 // TODO: Implement the AMD64 ABI in its entirety. This simple
10877 // selection mechanism works only for the basic types.
10878 if (ArgVT == MVT::f80) {
10879 llvm_unreachable("va_arg for f80 not yet implemented");
10880 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10881 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10882 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10883 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10885 llvm_unreachable("Unhandled argument type in LowerVAARG");
10888 if (ArgMode == 2) {
10889 // Sanity Check: Make sure using fp_offset makes sense.
10890 assert(!getTargetMachine().Options.UseSoftFloat &&
10891 !(DAG.getMachineFunction()
10892 .getFunction()->getAttributes()
10893 .hasAttribute(AttributeSet::FunctionIndex,
10894 Attribute::NoImplicitFloat)) &&
10895 Subtarget->hasSSE1());
10898 // Insert VAARG_64 node into the DAG
10899 // VAARG_64 returns two values: Variable Argument Address, Chain
10900 SmallVector<SDValue, 11> InstOps;
10901 InstOps.push_back(Chain);
10902 InstOps.push_back(SrcPtr);
10903 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10904 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10905 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10906 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10907 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10908 VTs, &InstOps[0], InstOps.size(),
10910 MachinePointerInfo(SV),
10912 /*Volatile=*/false,
10914 /*WriteMem=*/true);
10915 Chain = VAARG.getValue(1);
10917 // Load the next argument and return it
10918 return DAG.getLoad(ArgVT, dl,
10921 MachinePointerInfo(),
10922 false, false, false, 0);
10925 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10926 SelectionDAG &DAG) {
10927 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10928 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10929 SDValue Chain = Op.getOperand(0);
10930 SDValue DstPtr = Op.getOperand(1);
10931 SDValue SrcPtr = Op.getOperand(2);
10932 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10933 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10936 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10937 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10939 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10942 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
10943 // amount is a constant. Takes immediate version of shift as input.
10944 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
10945 SDValue SrcOp, uint64_t ShiftAmt,
10946 SelectionDAG &DAG) {
10948 // Check for ShiftAmt >= element width
10949 if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
10950 if (Opc == X86ISD::VSRAI)
10951 ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
10953 return DAG.getConstant(0, VT);
10956 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
10957 && "Unknown target vector shift-by-constant node");
10959 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
10962 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10963 // may or may not be a constant. Takes immediate version of shift as input.
10964 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10965 SDValue SrcOp, SDValue ShAmt,
10966 SelectionDAG &DAG) {
10967 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10969 // Catch shift-by-constant.
10970 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
10971 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
10972 CShAmt->getZExtValue(), DAG);
10974 // Change opcode to non-immediate version
10976 default: llvm_unreachable("Unknown target vector shift node");
10977 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10978 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10979 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10982 // Need to build a vector containing shift amount
10983 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10986 ShOps[1] = DAG.getConstant(0, MVT::i32);
10987 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10988 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10990 // The return type has to be a 128-bit type with the same element
10991 // type as the input type.
10992 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10993 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10995 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10996 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10999 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11001 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11003 default: return SDValue(); // Don't custom lower most intrinsics.
11004 // Comparison intrinsics.
11005 case Intrinsic::x86_sse_comieq_ss:
11006 case Intrinsic::x86_sse_comilt_ss:
11007 case Intrinsic::x86_sse_comile_ss:
11008 case Intrinsic::x86_sse_comigt_ss:
11009 case Intrinsic::x86_sse_comige_ss:
11010 case Intrinsic::x86_sse_comineq_ss:
11011 case Intrinsic::x86_sse_ucomieq_ss:
11012 case Intrinsic::x86_sse_ucomilt_ss:
11013 case Intrinsic::x86_sse_ucomile_ss:
11014 case Intrinsic::x86_sse_ucomigt_ss:
11015 case Intrinsic::x86_sse_ucomige_ss:
11016 case Intrinsic::x86_sse_ucomineq_ss:
11017 case Intrinsic::x86_sse2_comieq_sd:
11018 case Intrinsic::x86_sse2_comilt_sd:
11019 case Intrinsic::x86_sse2_comile_sd:
11020 case Intrinsic::x86_sse2_comigt_sd:
11021 case Intrinsic::x86_sse2_comige_sd:
11022 case Intrinsic::x86_sse2_comineq_sd:
11023 case Intrinsic::x86_sse2_ucomieq_sd:
11024 case Intrinsic::x86_sse2_ucomilt_sd:
11025 case Intrinsic::x86_sse2_ucomile_sd:
11026 case Intrinsic::x86_sse2_ucomigt_sd:
11027 case Intrinsic::x86_sse2_ucomige_sd:
11028 case Intrinsic::x86_sse2_ucomineq_sd: {
11032 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11033 case Intrinsic::x86_sse_comieq_ss:
11034 case Intrinsic::x86_sse2_comieq_sd:
11035 Opc = X86ISD::COMI;
11038 case Intrinsic::x86_sse_comilt_ss:
11039 case Intrinsic::x86_sse2_comilt_sd:
11040 Opc = X86ISD::COMI;
11043 case Intrinsic::x86_sse_comile_ss:
11044 case Intrinsic::x86_sse2_comile_sd:
11045 Opc = X86ISD::COMI;
11048 case Intrinsic::x86_sse_comigt_ss:
11049 case Intrinsic::x86_sse2_comigt_sd:
11050 Opc = X86ISD::COMI;
11053 case Intrinsic::x86_sse_comige_ss:
11054 case Intrinsic::x86_sse2_comige_sd:
11055 Opc = X86ISD::COMI;
11058 case Intrinsic::x86_sse_comineq_ss:
11059 case Intrinsic::x86_sse2_comineq_sd:
11060 Opc = X86ISD::COMI;
11063 case Intrinsic::x86_sse_ucomieq_ss:
11064 case Intrinsic::x86_sse2_ucomieq_sd:
11065 Opc = X86ISD::UCOMI;
11068 case Intrinsic::x86_sse_ucomilt_ss:
11069 case Intrinsic::x86_sse2_ucomilt_sd:
11070 Opc = X86ISD::UCOMI;
11073 case Intrinsic::x86_sse_ucomile_ss:
11074 case Intrinsic::x86_sse2_ucomile_sd:
11075 Opc = X86ISD::UCOMI;
11078 case Intrinsic::x86_sse_ucomigt_ss:
11079 case Intrinsic::x86_sse2_ucomigt_sd:
11080 Opc = X86ISD::UCOMI;
11083 case Intrinsic::x86_sse_ucomige_ss:
11084 case Intrinsic::x86_sse2_ucomige_sd:
11085 Opc = X86ISD::UCOMI;
11088 case Intrinsic::x86_sse_ucomineq_ss:
11089 case Intrinsic::x86_sse2_ucomineq_sd:
11090 Opc = X86ISD::UCOMI;
11095 SDValue LHS = Op.getOperand(1);
11096 SDValue RHS = Op.getOperand(2);
11097 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11098 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11099 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11100 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11101 DAG.getConstant(X86CC, MVT::i8), Cond);
11102 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11105 // Arithmetic intrinsics.
11106 case Intrinsic::x86_sse2_pmulu_dq:
11107 case Intrinsic::x86_avx2_pmulu_dq:
11108 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11109 Op.getOperand(1), Op.getOperand(2));
11111 // SSE2/AVX2 sub with unsigned saturation intrinsics
11112 case Intrinsic::x86_sse2_psubus_b:
11113 case Intrinsic::x86_sse2_psubus_w:
11114 case Intrinsic::x86_avx2_psubus_b:
11115 case Intrinsic::x86_avx2_psubus_w:
11116 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11117 Op.getOperand(1), Op.getOperand(2));
11119 // SSE3/AVX horizontal add/sub intrinsics
11120 case Intrinsic::x86_sse3_hadd_ps:
11121 case Intrinsic::x86_sse3_hadd_pd:
11122 case Intrinsic::x86_avx_hadd_ps_256:
11123 case Intrinsic::x86_avx_hadd_pd_256:
11124 case Intrinsic::x86_sse3_hsub_ps:
11125 case Intrinsic::x86_sse3_hsub_pd:
11126 case Intrinsic::x86_avx_hsub_ps_256:
11127 case Intrinsic::x86_avx_hsub_pd_256:
11128 case Intrinsic::x86_ssse3_phadd_w_128:
11129 case Intrinsic::x86_ssse3_phadd_d_128:
11130 case Intrinsic::x86_avx2_phadd_w:
11131 case Intrinsic::x86_avx2_phadd_d:
11132 case Intrinsic::x86_ssse3_phsub_w_128:
11133 case Intrinsic::x86_ssse3_phsub_d_128:
11134 case Intrinsic::x86_avx2_phsub_w:
11135 case Intrinsic::x86_avx2_phsub_d: {
11138 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11139 case Intrinsic::x86_sse3_hadd_ps:
11140 case Intrinsic::x86_sse3_hadd_pd:
11141 case Intrinsic::x86_avx_hadd_ps_256:
11142 case Intrinsic::x86_avx_hadd_pd_256:
11143 Opcode = X86ISD::FHADD;
11145 case Intrinsic::x86_sse3_hsub_ps:
11146 case Intrinsic::x86_sse3_hsub_pd:
11147 case Intrinsic::x86_avx_hsub_ps_256:
11148 case Intrinsic::x86_avx_hsub_pd_256:
11149 Opcode = X86ISD::FHSUB;
11151 case Intrinsic::x86_ssse3_phadd_w_128:
11152 case Intrinsic::x86_ssse3_phadd_d_128:
11153 case Intrinsic::x86_avx2_phadd_w:
11154 case Intrinsic::x86_avx2_phadd_d:
11155 Opcode = X86ISD::HADD;
11157 case Intrinsic::x86_ssse3_phsub_w_128:
11158 case Intrinsic::x86_ssse3_phsub_d_128:
11159 case Intrinsic::x86_avx2_phsub_w:
11160 case Intrinsic::x86_avx2_phsub_d:
11161 Opcode = X86ISD::HSUB;
11164 return DAG.getNode(Opcode, dl, Op.getValueType(),
11165 Op.getOperand(1), Op.getOperand(2));
11168 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11169 case Intrinsic::x86_sse2_pmaxu_b:
11170 case Intrinsic::x86_sse41_pmaxuw:
11171 case Intrinsic::x86_sse41_pmaxud:
11172 case Intrinsic::x86_avx2_pmaxu_b:
11173 case Intrinsic::x86_avx2_pmaxu_w:
11174 case Intrinsic::x86_avx2_pmaxu_d:
11175 case Intrinsic::x86_sse2_pminu_b:
11176 case Intrinsic::x86_sse41_pminuw:
11177 case Intrinsic::x86_sse41_pminud:
11178 case Intrinsic::x86_avx2_pminu_b:
11179 case Intrinsic::x86_avx2_pminu_w:
11180 case Intrinsic::x86_avx2_pminu_d:
11181 case Intrinsic::x86_sse41_pmaxsb:
11182 case Intrinsic::x86_sse2_pmaxs_w:
11183 case Intrinsic::x86_sse41_pmaxsd:
11184 case Intrinsic::x86_avx2_pmaxs_b:
11185 case Intrinsic::x86_avx2_pmaxs_w:
11186 case Intrinsic::x86_avx2_pmaxs_d:
11187 case Intrinsic::x86_sse41_pminsb:
11188 case Intrinsic::x86_sse2_pmins_w:
11189 case Intrinsic::x86_sse41_pminsd:
11190 case Intrinsic::x86_avx2_pmins_b:
11191 case Intrinsic::x86_avx2_pmins_w:
11192 case Intrinsic::x86_avx2_pmins_d: {
11195 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11196 case Intrinsic::x86_sse2_pmaxu_b:
11197 case Intrinsic::x86_sse41_pmaxuw:
11198 case Intrinsic::x86_sse41_pmaxud:
11199 case Intrinsic::x86_avx2_pmaxu_b:
11200 case Intrinsic::x86_avx2_pmaxu_w:
11201 case Intrinsic::x86_avx2_pmaxu_d:
11202 Opcode = X86ISD::UMAX;
11204 case Intrinsic::x86_sse2_pminu_b:
11205 case Intrinsic::x86_sse41_pminuw:
11206 case Intrinsic::x86_sse41_pminud:
11207 case Intrinsic::x86_avx2_pminu_b:
11208 case Intrinsic::x86_avx2_pminu_w:
11209 case Intrinsic::x86_avx2_pminu_d:
11210 Opcode = X86ISD::UMIN;
11212 case Intrinsic::x86_sse41_pmaxsb:
11213 case Intrinsic::x86_sse2_pmaxs_w:
11214 case Intrinsic::x86_sse41_pmaxsd:
11215 case Intrinsic::x86_avx2_pmaxs_b:
11216 case Intrinsic::x86_avx2_pmaxs_w:
11217 case Intrinsic::x86_avx2_pmaxs_d:
11218 Opcode = X86ISD::SMAX;
11220 case Intrinsic::x86_sse41_pminsb:
11221 case Intrinsic::x86_sse2_pmins_w:
11222 case Intrinsic::x86_sse41_pminsd:
11223 case Intrinsic::x86_avx2_pmins_b:
11224 case Intrinsic::x86_avx2_pmins_w:
11225 case Intrinsic::x86_avx2_pmins_d:
11226 Opcode = X86ISD::SMIN;
11229 return DAG.getNode(Opcode, dl, Op.getValueType(),
11230 Op.getOperand(1), Op.getOperand(2));
11233 // SSE/SSE2/AVX floating point max/min intrinsics.
11234 case Intrinsic::x86_sse_max_ps:
11235 case Intrinsic::x86_sse2_max_pd:
11236 case Intrinsic::x86_avx_max_ps_256:
11237 case Intrinsic::x86_avx_max_pd_256:
11238 case Intrinsic::x86_avx512_max_ps_512:
11239 case Intrinsic::x86_avx512_max_pd_512:
11240 case Intrinsic::x86_sse_min_ps:
11241 case Intrinsic::x86_sse2_min_pd:
11242 case Intrinsic::x86_avx_min_ps_256:
11243 case Intrinsic::x86_avx_min_pd_256:
11244 case Intrinsic::x86_avx512_min_ps_512:
11245 case Intrinsic::x86_avx512_min_pd_512: {
11248 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11249 case Intrinsic::x86_sse_max_ps:
11250 case Intrinsic::x86_sse2_max_pd:
11251 case Intrinsic::x86_avx_max_ps_256:
11252 case Intrinsic::x86_avx_max_pd_256:
11253 case Intrinsic::x86_avx512_max_ps_512:
11254 case Intrinsic::x86_avx512_max_pd_512:
11255 Opcode = X86ISD::FMAX;
11257 case Intrinsic::x86_sse_min_ps:
11258 case Intrinsic::x86_sse2_min_pd:
11259 case Intrinsic::x86_avx_min_ps_256:
11260 case Intrinsic::x86_avx_min_pd_256:
11261 case Intrinsic::x86_avx512_min_ps_512:
11262 case Intrinsic::x86_avx512_min_pd_512:
11263 Opcode = X86ISD::FMIN;
11266 return DAG.getNode(Opcode, dl, Op.getValueType(),
11267 Op.getOperand(1), Op.getOperand(2));
11270 // AVX2 variable shift intrinsics
11271 case Intrinsic::x86_avx2_psllv_d:
11272 case Intrinsic::x86_avx2_psllv_q:
11273 case Intrinsic::x86_avx2_psllv_d_256:
11274 case Intrinsic::x86_avx2_psllv_q_256:
11275 case Intrinsic::x86_avx2_psrlv_d:
11276 case Intrinsic::x86_avx2_psrlv_q:
11277 case Intrinsic::x86_avx2_psrlv_d_256:
11278 case Intrinsic::x86_avx2_psrlv_q_256:
11279 case Intrinsic::x86_avx2_psrav_d:
11280 case Intrinsic::x86_avx2_psrav_d_256: {
11283 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11284 case Intrinsic::x86_avx2_psllv_d:
11285 case Intrinsic::x86_avx2_psllv_q:
11286 case Intrinsic::x86_avx2_psllv_d_256:
11287 case Intrinsic::x86_avx2_psllv_q_256:
11290 case Intrinsic::x86_avx2_psrlv_d:
11291 case Intrinsic::x86_avx2_psrlv_q:
11292 case Intrinsic::x86_avx2_psrlv_d_256:
11293 case Intrinsic::x86_avx2_psrlv_q_256:
11296 case Intrinsic::x86_avx2_psrav_d:
11297 case Intrinsic::x86_avx2_psrav_d_256:
11301 return DAG.getNode(Opcode, dl, Op.getValueType(),
11302 Op.getOperand(1), Op.getOperand(2));
11305 case Intrinsic::x86_ssse3_pshuf_b_128:
11306 case Intrinsic::x86_avx2_pshuf_b:
11307 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11308 Op.getOperand(1), Op.getOperand(2));
11310 case Intrinsic::x86_ssse3_psign_b_128:
11311 case Intrinsic::x86_ssse3_psign_w_128:
11312 case Intrinsic::x86_ssse3_psign_d_128:
11313 case Intrinsic::x86_avx2_psign_b:
11314 case Intrinsic::x86_avx2_psign_w:
11315 case Intrinsic::x86_avx2_psign_d:
11316 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11317 Op.getOperand(1), Op.getOperand(2));
11319 case Intrinsic::x86_sse41_insertps:
11320 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11321 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11323 case Intrinsic::x86_avx_vperm2f128_ps_256:
11324 case Intrinsic::x86_avx_vperm2f128_pd_256:
11325 case Intrinsic::x86_avx_vperm2f128_si_256:
11326 case Intrinsic::x86_avx2_vperm2i128:
11327 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11328 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11330 case Intrinsic::x86_avx2_permd:
11331 case Intrinsic::x86_avx2_permps:
11332 // Operands intentionally swapped. Mask is last operand to intrinsic,
11333 // but second operand for node/instruction.
11334 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11335 Op.getOperand(2), Op.getOperand(1));
11337 case Intrinsic::x86_sse_sqrt_ps:
11338 case Intrinsic::x86_sse2_sqrt_pd:
11339 case Intrinsic::x86_avx_sqrt_ps_256:
11340 case Intrinsic::x86_avx_sqrt_pd_256:
11341 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11343 // ptest and testp intrinsics. The intrinsic these come from are designed to
11344 // return an integer value, not just an instruction so lower it to the ptest
11345 // or testp pattern and a setcc for the result.
11346 case Intrinsic::x86_sse41_ptestz:
11347 case Intrinsic::x86_sse41_ptestc:
11348 case Intrinsic::x86_sse41_ptestnzc:
11349 case Intrinsic::x86_avx_ptestz_256:
11350 case Intrinsic::x86_avx_ptestc_256:
11351 case Intrinsic::x86_avx_ptestnzc_256:
11352 case Intrinsic::x86_avx_vtestz_ps:
11353 case Intrinsic::x86_avx_vtestc_ps:
11354 case Intrinsic::x86_avx_vtestnzc_ps:
11355 case Intrinsic::x86_avx_vtestz_pd:
11356 case Intrinsic::x86_avx_vtestc_pd:
11357 case Intrinsic::x86_avx_vtestnzc_pd:
11358 case Intrinsic::x86_avx_vtestz_ps_256:
11359 case Intrinsic::x86_avx_vtestc_ps_256:
11360 case Intrinsic::x86_avx_vtestnzc_ps_256:
11361 case Intrinsic::x86_avx_vtestz_pd_256:
11362 case Intrinsic::x86_avx_vtestc_pd_256:
11363 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11364 bool IsTestPacked = false;
11367 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11368 case Intrinsic::x86_avx_vtestz_ps:
11369 case Intrinsic::x86_avx_vtestz_pd:
11370 case Intrinsic::x86_avx_vtestz_ps_256:
11371 case Intrinsic::x86_avx_vtestz_pd_256:
11372 IsTestPacked = true; // Fallthrough
11373 case Intrinsic::x86_sse41_ptestz:
11374 case Intrinsic::x86_avx_ptestz_256:
11376 X86CC = X86::COND_E;
11378 case Intrinsic::x86_avx_vtestc_ps:
11379 case Intrinsic::x86_avx_vtestc_pd:
11380 case Intrinsic::x86_avx_vtestc_ps_256:
11381 case Intrinsic::x86_avx_vtestc_pd_256:
11382 IsTestPacked = true; // Fallthrough
11383 case Intrinsic::x86_sse41_ptestc:
11384 case Intrinsic::x86_avx_ptestc_256:
11386 X86CC = X86::COND_B;
11388 case Intrinsic::x86_avx_vtestnzc_ps:
11389 case Intrinsic::x86_avx_vtestnzc_pd:
11390 case Intrinsic::x86_avx_vtestnzc_ps_256:
11391 case Intrinsic::x86_avx_vtestnzc_pd_256:
11392 IsTestPacked = true; // Fallthrough
11393 case Intrinsic::x86_sse41_ptestnzc:
11394 case Intrinsic::x86_avx_ptestnzc_256:
11396 X86CC = X86::COND_A;
11400 SDValue LHS = Op.getOperand(1);
11401 SDValue RHS = Op.getOperand(2);
11402 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11403 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11404 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11405 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11406 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11408 case Intrinsic::x86_avx512_kortestz:
11409 case Intrinsic::x86_avx512_kortestc: {
11410 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11411 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11412 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11413 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11414 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11415 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11416 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11419 // SSE/AVX shift intrinsics
11420 case Intrinsic::x86_sse2_psll_w:
11421 case Intrinsic::x86_sse2_psll_d:
11422 case Intrinsic::x86_sse2_psll_q:
11423 case Intrinsic::x86_avx2_psll_w:
11424 case Intrinsic::x86_avx2_psll_d:
11425 case Intrinsic::x86_avx2_psll_q:
11426 case Intrinsic::x86_sse2_psrl_w:
11427 case Intrinsic::x86_sse2_psrl_d:
11428 case Intrinsic::x86_sse2_psrl_q:
11429 case Intrinsic::x86_avx2_psrl_w:
11430 case Intrinsic::x86_avx2_psrl_d:
11431 case Intrinsic::x86_avx2_psrl_q:
11432 case Intrinsic::x86_sse2_psra_w:
11433 case Intrinsic::x86_sse2_psra_d:
11434 case Intrinsic::x86_avx2_psra_w:
11435 case Intrinsic::x86_avx2_psra_d: {
11438 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11439 case Intrinsic::x86_sse2_psll_w:
11440 case Intrinsic::x86_sse2_psll_d:
11441 case Intrinsic::x86_sse2_psll_q:
11442 case Intrinsic::x86_avx2_psll_w:
11443 case Intrinsic::x86_avx2_psll_d:
11444 case Intrinsic::x86_avx2_psll_q:
11445 Opcode = X86ISD::VSHL;
11447 case Intrinsic::x86_sse2_psrl_w:
11448 case Intrinsic::x86_sse2_psrl_d:
11449 case Intrinsic::x86_sse2_psrl_q:
11450 case Intrinsic::x86_avx2_psrl_w:
11451 case Intrinsic::x86_avx2_psrl_d:
11452 case Intrinsic::x86_avx2_psrl_q:
11453 Opcode = X86ISD::VSRL;
11455 case Intrinsic::x86_sse2_psra_w:
11456 case Intrinsic::x86_sse2_psra_d:
11457 case Intrinsic::x86_avx2_psra_w:
11458 case Intrinsic::x86_avx2_psra_d:
11459 Opcode = X86ISD::VSRA;
11462 return DAG.getNode(Opcode, dl, Op.getValueType(),
11463 Op.getOperand(1), Op.getOperand(2));
11466 // SSE/AVX immediate shift intrinsics
11467 case Intrinsic::x86_sse2_pslli_w:
11468 case Intrinsic::x86_sse2_pslli_d:
11469 case Intrinsic::x86_sse2_pslli_q:
11470 case Intrinsic::x86_avx2_pslli_w:
11471 case Intrinsic::x86_avx2_pslli_d:
11472 case Intrinsic::x86_avx2_pslli_q:
11473 case Intrinsic::x86_sse2_psrli_w:
11474 case Intrinsic::x86_sse2_psrli_d:
11475 case Intrinsic::x86_sse2_psrli_q:
11476 case Intrinsic::x86_avx2_psrli_w:
11477 case Intrinsic::x86_avx2_psrli_d:
11478 case Intrinsic::x86_avx2_psrli_q:
11479 case Intrinsic::x86_sse2_psrai_w:
11480 case Intrinsic::x86_sse2_psrai_d:
11481 case Intrinsic::x86_avx2_psrai_w:
11482 case Intrinsic::x86_avx2_psrai_d: {
11485 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11486 case Intrinsic::x86_sse2_pslli_w:
11487 case Intrinsic::x86_sse2_pslli_d:
11488 case Intrinsic::x86_sse2_pslli_q:
11489 case Intrinsic::x86_avx2_pslli_w:
11490 case Intrinsic::x86_avx2_pslli_d:
11491 case Intrinsic::x86_avx2_pslli_q:
11492 Opcode = X86ISD::VSHLI;
11494 case Intrinsic::x86_sse2_psrli_w:
11495 case Intrinsic::x86_sse2_psrli_d:
11496 case Intrinsic::x86_sse2_psrli_q:
11497 case Intrinsic::x86_avx2_psrli_w:
11498 case Intrinsic::x86_avx2_psrli_d:
11499 case Intrinsic::x86_avx2_psrli_q:
11500 Opcode = X86ISD::VSRLI;
11502 case Intrinsic::x86_sse2_psrai_w:
11503 case Intrinsic::x86_sse2_psrai_d:
11504 case Intrinsic::x86_avx2_psrai_w:
11505 case Intrinsic::x86_avx2_psrai_d:
11506 Opcode = X86ISD::VSRAI;
11509 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11510 Op.getOperand(1), Op.getOperand(2), DAG);
11513 case Intrinsic::x86_sse42_pcmpistria128:
11514 case Intrinsic::x86_sse42_pcmpestria128:
11515 case Intrinsic::x86_sse42_pcmpistric128:
11516 case Intrinsic::x86_sse42_pcmpestric128:
11517 case Intrinsic::x86_sse42_pcmpistrio128:
11518 case Intrinsic::x86_sse42_pcmpestrio128:
11519 case Intrinsic::x86_sse42_pcmpistris128:
11520 case Intrinsic::x86_sse42_pcmpestris128:
11521 case Intrinsic::x86_sse42_pcmpistriz128:
11522 case Intrinsic::x86_sse42_pcmpestriz128: {
11526 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11527 case Intrinsic::x86_sse42_pcmpistria128:
11528 Opcode = X86ISD::PCMPISTRI;
11529 X86CC = X86::COND_A;
11531 case Intrinsic::x86_sse42_pcmpestria128:
11532 Opcode = X86ISD::PCMPESTRI;
11533 X86CC = X86::COND_A;
11535 case Intrinsic::x86_sse42_pcmpistric128:
11536 Opcode = X86ISD::PCMPISTRI;
11537 X86CC = X86::COND_B;
11539 case Intrinsic::x86_sse42_pcmpestric128:
11540 Opcode = X86ISD::PCMPESTRI;
11541 X86CC = X86::COND_B;
11543 case Intrinsic::x86_sse42_pcmpistrio128:
11544 Opcode = X86ISD::PCMPISTRI;
11545 X86CC = X86::COND_O;
11547 case Intrinsic::x86_sse42_pcmpestrio128:
11548 Opcode = X86ISD::PCMPESTRI;
11549 X86CC = X86::COND_O;
11551 case Intrinsic::x86_sse42_pcmpistris128:
11552 Opcode = X86ISD::PCMPISTRI;
11553 X86CC = X86::COND_S;
11555 case Intrinsic::x86_sse42_pcmpestris128:
11556 Opcode = X86ISD::PCMPESTRI;
11557 X86CC = X86::COND_S;
11559 case Intrinsic::x86_sse42_pcmpistriz128:
11560 Opcode = X86ISD::PCMPISTRI;
11561 X86CC = X86::COND_E;
11563 case Intrinsic::x86_sse42_pcmpestriz128:
11564 Opcode = X86ISD::PCMPESTRI;
11565 X86CC = X86::COND_E;
11568 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11569 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11570 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11571 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11572 DAG.getConstant(X86CC, MVT::i8),
11573 SDValue(PCMP.getNode(), 1));
11574 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11577 case Intrinsic::x86_sse42_pcmpistri128:
11578 case Intrinsic::x86_sse42_pcmpestri128: {
11580 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11581 Opcode = X86ISD::PCMPISTRI;
11583 Opcode = X86ISD::PCMPESTRI;
11585 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11586 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11587 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11589 case Intrinsic::x86_fma_vfmadd_ps:
11590 case Intrinsic::x86_fma_vfmadd_pd:
11591 case Intrinsic::x86_fma_vfmsub_ps:
11592 case Intrinsic::x86_fma_vfmsub_pd:
11593 case Intrinsic::x86_fma_vfnmadd_ps:
11594 case Intrinsic::x86_fma_vfnmadd_pd:
11595 case Intrinsic::x86_fma_vfnmsub_ps:
11596 case Intrinsic::x86_fma_vfnmsub_pd:
11597 case Intrinsic::x86_fma_vfmaddsub_ps:
11598 case Intrinsic::x86_fma_vfmaddsub_pd:
11599 case Intrinsic::x86_fma_vfmsubadd_ps:
11600 case Intrinsic::x86_fma_vfmsubadd_pd:
11601 case Intrinsic::x86_fma_vfmadd_ps_256:
11602 case Intrinsic::x86_fma_vfmadd_pd_256:
11603 case Intrinsic::x86_fma_vfmsub_ps_256:
11604 case Intrinsic::x86_fma_vfmsub_pd_256:
11605 case Intrinsic::x86_fma_vfnmadd_ps_256:
11606 case Intrinsic::x86_fma_vfnmadd_pd_256:
11607 case Intrinsic::x86_fma_vfnmsub_ps_256:
11608 case Intrinsic::x86_fma_vfnmsub_pd_256:
11609 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11610 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11611 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11612 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11615 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11616 case Intrinsic::x86_fma_vfmadd_ps:
11617 case Intrinsic::x86_fma_vfmadd_pd:
11618 case Intrinsic::x86_fma_vfmadd_ps_256:
11619 case Intrinsic::x86_fma_vfmadd_pd_256:
11620 Opc = X86ISD::FMADD;
11622 case Intrinsic::x86_fma_vfmsub_ps:
11623 case Intrinsic::x86_fma_vfmsub_pd:
11624 case Intrinsic::x86_fma_vfmsub_ps_256:
11625 case Intrinsic::x86_fma_vfmsub_pd_256:
11626 Opc = X86ISD::FMSUB;
11628 case Intrinsic::x86_fma_vfnmadd_ps:
11629 case Intrinsic::x86_fma_vfnmadd_pd:
11630 case Intrinsic::x86_fma_vfnmadd_ps_256:
11631 case Intrinsic::x86_fma_vfnmadd_pd_256:
11632 Opc = X86ISD::FNMADD;
11634 case Intrinsic::x86_fma_vfnmsub_ps:
11635 case Intrinsic::x86_fma_vfnmsub_pd:
11636 case Intrinsic::x86_fma_vfnmsub_ps_256:
11637 case Intrinsic::x86_fma_vfnmsub_pd_256:
11638 Opc = X86ISD::FNMSUB;
11640 case Intrinsic::x86_fma_vfmaddsub_ps:
11641 case Intrinsic::x86_fma_vfmaddsub_pd:
11642 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11643 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11644 Opc = X86ISD::FMADDSUB;
11646 case Intrinsic::x86_fma_vfmsubadd_ps:
11647 case Intrinsic::x86_fma_vfmsubadd_pd:
11648 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11649 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11650 Opc = X86ISD::FMSUBADD;
11654 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11655 Op.getOperand(2), Op.getOperand(3));
11660 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11661 SDValue Base, SDValue Index,
11662 SDValue ScaleOp, SDValue Chain,
11663 const X86Subtarget * Subtarget) {
11665 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11666 assert(C && "Invalid scale type");
11667 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11668 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11669 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11670 Index.getValueType().getVectorNumElements());
11671 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11672 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11673 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11674 SDValue Segment = DAG.getRegister(0, MVT::i32);
11675 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11676 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11677 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11678 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11681 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11682 SDValue Src, SDValue Mask, SDValue Base,
11683 SDValue Index, SDValue ScaleOp, SDValue Chain,
11684 const X86Subtarget * Subtarget) {
11686 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11687 assert(C && "Invalid scale type");
11688 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11689 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11690 Index.getValueType().getVectorNumElements());
11691 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11692 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11693 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11694 SDValue Segment = DAG.getRegister(0, MVT::i32);
11695 if (Src.getOpcode() == ISD::UNDEF)
11696 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11697 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11698 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11699 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11700 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11703 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11704 SDValue Src, SDValue Base, SDValue Index,
11705 SDValue ScaleOp, SDValue Chain) {
11707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11708 assert(C && "Invalid scale type");
11709 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11710 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11711 SDValue Segment = DAG.getRegister(0, MVT::i32);
11712 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11713 Index.getValueType().getVectorNumElements());
11714 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11715 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11716 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11717 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11718 return SDValue(Res, 1);
11721 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11722 SDValue Src, SDValue Mask, SDValue Base,
11723 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11725 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11726 assert(C && "Invalid scale type");
11727 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11728 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11729 SDValue Segment = DAG.getRegister(0, MVT::i32);
11730 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11731 Index.getValueType().getVectorNumElements());
11732 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11733 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11734 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11735 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11736 return SDValue(Res, 1);
11739 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11740 SelectionDAG &DAG) {
11742 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11744 default: return SDValue(); // Don't custom lower most intrinsics.
11746 // RDRAND/RDSEED intrinsics.
11747 case Intrinsic::x86_rdrand_16:
11748 case Intrinsic::x86_rdrand_32:
11749 case Intrinsic::x86_rdrand_64:
11750 case Intrinsic::x86_rdseed_16:
11751 case Intrinsic::x86_rdseed_32:
11752 case Intrinsic::x86_rdseed_64: {
11753 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11754 IntNo == Intrinsic::x86_rdseed_32 ||
11755 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11757 // Emit the node with the right value type.
11758 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11759 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11761 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11762 // Otherwise return the value from Rand, which is always 0, casted to i32.
11763 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11764 DAG.getConstant(1, Op->getValueType(1)),
11765 DAG.getConstant(X86::COND_B, MVT::i32),
11766 SDValue(Result.getNode(), 1) };
11767 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11768 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11769 Ops, array_lengthof(Ops));
11771 // Return { result, isValid, chain }.
11772 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11773 SDValue(Result.getNode(), 2));
11775 //int_gather(index, base, scale);
11776 case Intrinsic::x86_avx512_gather_qpd_512:
11777 case Intrinsic::x86_avx512_gather_qps_512:
11778 case Intrinsic::x86_avx512_gather_dpd_512:
11779 case Intrinsic::x86_avx512_gather_qpi_512:
11780 case Intrinsic::x86_avx512_gather_qpq_512:
11781 case Intrinsic::x86_avx512_gather_dpq_512:
11782 case Intrinsic::x86_avx512_gather_dps_512:
11783 case Intrinsic::x86_avx512_gather_dpi_512: {
11786 default: llvm_unreachable("Unexpected intrinsic!");
11787 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11788 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11789 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11790 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11791 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11792 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11793 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11794 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11796 SDValue Chain = Op.getOperand(0);
11797 SDValue Index = Op.getOperand(2);
11798 SDValue Base = Op.getOperand(3);
11799 SDValue Scale = Op.getOperand(4);
11800 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11802 //int_gather_mask(v1, mask, index, base, scale);
11803 case Intrinsic::x86_avx512_gather_qps_mask_512:
11804 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11805 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11806 case Intrinsic::x86_avx512_gather_dps_mask_512:
11807 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11808 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11809 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11810 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11813 default: llvm_unreachable("Unexpected intrinsic!");
11814 case Intrinsic::x86_avx512_gather_qps_mask_512:
11815 Opc = X86::VGATHERQPSZrm; break;
11816 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11817 Opc = X86::VGATHERQPDZrm; break;
11818 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11819 Opc = X86::VGATHERDPDZrm; break;
11820 case Intrinsic::x86_avx512_gather_dps_mask_512:
11821 Opc = X86::VGATHERDPSZrm; break;
11822 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11823 Opc = X86::VPGATHERQDZrm; break;
11824 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11825 Opc = X86::VPGATHERQQZrm; break;
11826 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11827 Opc = X86::VPGATHERDDZrm; break;
11828 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11829 Opc = X86::VPGATHERDQZrm; break;
11831 SDValue Chain = Op.getOperand(0);
11832 SDValue Src = Op.getOperand(2);
11833 SDValue Mask = Op.getOperand(3);
11834 SDValue Index = Op.getOperand(4);
11835 SDValue Base = Op.getOperand(5);
11836 SDValue Scale = Op.getOperand(6);
11837 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11840 //int_scatter(base, index, v1, scale);
11841 case Intrinsic::x86_avx512_scatter_qpd_512:
11842 case Intrinsic::x86_avx512_scatter_qps_512:
11843 case Intrinsic::x86_avx512_scatter_dpd_512:
11844 case Intrinsic::x86_avx512_scatter_qpi_512:
11845 case Intrinsic::x86_avx512_scatter_qpq_512:
11846 case Intrinsic::x86_avx512_scatter_dpq_512:
11847 case Intrinsic::x86_avx512_scatter_dps_512:
11848 case Intrinsic::x86_avx512_scatter_dpi_512: {
11851 default: llvm_unreachable("Unexpected intrinsic!");
11852 case Intrinsic::x86_avx512_scatter_qpd_512:
11853 Opc = X86::VSCATTERQPDZmr; break;
11854 case Intrinsic::x86_avx512_scatter_qps_512:
11855 Opc = X86::VSCATTERQPSZmr; break;
11856 case Intrinsic::x86_avx512_scatter_dpd_512:
11857 Opc = X86::VSCATTERDPDZmr; break;
11858 case Intrinsic::x86_avx512_scatter_dps_512:
11859 Opc = X86::VSCATTERDPSZmr; break;
11860 case Intrinsic::x86_avx512_scatter_qpi_512:
11861 Opc = X86::VPSCATTERQDZmr; break;
11862 case Intrinsic::x86_avx512_scatter_qpq_512:
11863 Opc = X86::VPSCATTERQQZmr; break;
11864 case Intrinsic::x86_avx512_scatter_dpq_512:
11865 Opc = X86::VPSCATTERDQZmr; break;
11866 case Intrinsic::x86_avx512_scatter_dpi_512:
11867 Opc = X86::VPSCATTERDDZmr; break;
11869 SDValue Chain = Op.getOperand(0);
11870 SDValue Base = Op.getOperand(2);
11871 SDValue Index = Op.getOperand(3);
11872 SDValue Src = Op.getOperand(4);
11873 SDValue Scale = Op.getOperand(5);
11874 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11876 //int_scatter_mask(base, mask, index, v1, scale);
11877 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11878 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11879 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11880 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11881 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11882 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11883 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11884 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11887 default: llvm_unreachable("Unexpected intrinsic!");
11888 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11889 Opc = X86::VSCATTERQPDZmr; break;
11890 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11891 Opc = X86::VSCATTERQPSZmr; break;
11892 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11893 Opc = X86::VSCATTERDPDZmr; break;
11894 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11895 Opc = X86::VSCATTERDPSZmr; break;
11896 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11897 Opc = X86::VPSCATTERQDZmr; break;
11898 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11899 Opc = X86::VPSCATTERQQZmr; break;
11900 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11901 Opc = X86::VPSCATTERDQZmr; break;
11902 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11903 Opc = X86::VPSCATTERDDZmr; break;
11905 SDValue Chain = Op.getOperand(0);
11906 SDValue Base = Op.getOperand(2);
11907 SDValue Mask = Op.getOperand(3);
11908 SDValue Index = Op.getOperand(4);
11909 SDValue Src = Op.getOperand(5);
11910 SDValue Scale = Op.getOperand(6);
11911 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11913 // XTEST intrinsics.
11914 case Intrinsic::x86_xtest: {
11915 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11916 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11917 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11918 DAG.getConstant(X86::COND_NE, MVT::i8),
11920 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11921 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11922 Ret, SDValue(InTrans.getNode(), 1));
11927 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11928 SelectionDAG &DAG) const {
11929 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11930 MFI->setReturnAddressIsTaken(true);
11932 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11934 EVT PtrVT = getPointerTy();
11937 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11938 const X86RegisterInfo *RegInfo =
11939 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11940 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11941 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11942 DAG.getNode(ISD::ADD, dl, PtrVT,
11943 FrameAddr, Offset),
11944 MachinePointerInfo(), false, false, false, 0);
11947 // Just load the return address.
11948 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11949 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11950 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11953 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11954 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11955 MFI->setFrameAddressIsTaken(true);
11957 EVT VT = Op.getValueType();
11958 SDLoc dl(Op); // FIXME probably not meaningful
11959 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11960 const X86RegisterInfo *RegInfo =
11961 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11962 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11963 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11964 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11965 "Invalid Frame Register!");
11966 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11968 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11969 MachinePointerInfo(),
11970 false, false, false, 0);
11974 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11975 SelectionDAG &DAG) const {
11976 const X86RegisterInfo *RegInfo =
11977 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11978 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11981 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11982 SDValue Chain = Op.getOperand(0);
11983 SDValue Offset = Op.getOperand(1);
11984 SDValue Handler = Op.getOperand(2);
11987 EVT PtrVT = getPointerTy();
11988 const X86RegisterInfo *RegInfo =
11989 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11990 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11991 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11992 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11993 "Invalid Frame Register!");
11994 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11995 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11997 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11998 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11999 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12000 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12002 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12004 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12005 DAG.getRegister(StoreAddrReg, PtrVT));
12008 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12009 SelectionDAG &DAG) const {
12011 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12012 DAG.getVTList(MVT::i32, MVT::Other),
12013 Op.getOperand(0), Op.getOperand(1));
12016 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12017 SelectionDAG &DAG) const {
12019 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12020 Op.getOperand(0), Op.getOperand(1));
12023 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12024 return Op.getOperand(0);
12027 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12028 SelectionDAG &DAG) const {
12029 SDValue Root = Op.getOperand(0);
12030 SDValue Trmp = Op.getOperand(1); // trampoline
12031 SDValue FPtr = Op.getOperand(2); // nested function
12032 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12035 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12036 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12038 if (Subtarget->is64Bit()) {
12039 SDValue OutChains[6];
12041 // Large code-model.
12042 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12043 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12045 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12046 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12048 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12050 // Load the pointer to the nested function into R11.
12051 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12052 SDValue Addr = Trmp;
12053 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12054 Addr, MachinePointerInfo(TrmpAddr),
12057 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12058 DAG.getConstant(2, MVT::i64));
12059 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12060 MachinePointerInfo(TrmpAddr, 2),
12063 // Load the 'nest' parameter value into R10.
12064 // R10 is specified in X86CallingConv.td
12065 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12066 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12067 DAG.getConstant(10, MVT::i64));
12068 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12069 Addr, MachinePointerInfo(TrmpAddr, 10),
12072 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12073 DAG.getConstant(12, MVT::i64));
12074 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12075 MachinePointerInfo(TrmpAddr, 12),
12078 // Jump to the nested function.
12079 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12080 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12081 DAG.getConstant(20, MVT::i64));
12082 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12083 Addr, MachinePointerInfo(TrmpAddr, 20),
12086 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12087 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12088 DAG.getConstant(22, MVT::i64));
12089 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12090 MachinePointerInfo(TrmpAddr, 22),
12093 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12095 const Function *Func =
12096 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12097 CallingConv::ID CC = Func->getCallingConv();
12102 llvm_unreachable("Unsupported calling convention");
12103 case CallingConv::C:
12104 case CallingConv::X86_StdCall: {
12105 // Pass 'nest' parameter in ECX.
12106 // Must be kept in sync with X86CallingConv.td
12107 NestReg = X86::ECX;
12109 // Check that ECX wasn't needed by an 'inreg' parameter.
12110 FunctionType *FTy = Func->getFunctionType();
12111 const AttributeSet &Attrs = Func->getAttributes();
12113 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12114 unsigned InRegCount = 0;
12117 for (FunctionType::param_iterator I = FTy->param_begin(),
12118 E = FTy->param_end(); I != E; ++I, ++Idx)
12119 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12120 // FIXME: should only count parameters that are lowered to integers.
12121 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12123 if (InRegCount > 2) {
12124 report_fatal_error("Nest register in use - reduce number of inreg"
12130 case CallingConv::X86_FastCall:
12131 case CallingConv::X86_ThisCall:
12132 case CallingConv::Fast:
12133 // Pass 'nest' parameter in EAX.
12134 // Must be kept in sync with X86CallingConv.td
12135 NestReg = X86::EAX;
12139 SDValue OutChains[4];
12140 SDValue Addr, Disp;
12142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12143 DAG.getConstant(10, MVT::i32));
12144 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12146 // This is storing the opcode for MOV32ri.
12147 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12148 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12149 OutChains[0] = DAG.getStore(Root, dl,
12150 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12151 Trmp, MachinePointerInfo(TrmpAddr),
12154 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12155 DAG.getConstant(1, MVT::i32));
12156 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12157 MachinePointerInfo(TrmpAddr, 1),
12160 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12161 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12162 DAG.getConstant(5, MVT::i32));
12163 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12164 MachinePointerInfo(TrmpAddr, 5),
12167 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12168 DAG.getConstant(6, MVT::i32));
12169 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12170 MachinePointerInfo(TrmpAddr, 6),
12173 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12177 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12178 SelectionDAG &DAG) const {
12180 The rounding mode is in bits 11:10 of FPSR, and has the following
12182 00 Round to nearest
12187 FLT_ROUNDS, on the other hand, expects the following:
12194 To perform the conversion, we do:
12195 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12198 MachineFunction &MF = DAG.getMachineFunction();
12199 const TargetMachine &TM = MF.getTarget();
12200 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12201 unsigned StackAlignment = TFI.getStackAlignment();
12202 EVT VT = Op.getValueType();
12205 // Save FP Control Word to stack slot
12206 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12207 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12209 MachineMemOperand *MMO =
12210 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12211 MachineMemOperand::MOStore, 2, 2);
12213 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12214 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12215 DAG.getVTList(MVT::Other),
12216 Ops, array_lengthof(Ops), MVT::i16,
12219 // Load FP Control Word from stack slot
12220 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12221 MachinePointerInfo(), false, false, false, 0);
12223 // Transform as necessary
12225 DAG.getNode(ISD::SRL, DL, MVT::i16,
12226 DAG.getNode(ISD::AND, DL, MVT::i16,
12227 CWD, DAG.getConstant(0x800, MVT::i16)),
12228 DAG.getConstant(11, MVT::i8));
12230 DAG.getNode(ISD::SRL, DL, MVT::i16,
12231 DAG.getNode(ISD::AND, DL, MVT::i16,
12232 CWD, DAG.getConstant(0x400, MVT::i16)),
12233 DAG.getConstant(9, MVT::i8));
12236 DAG.getNode(ISD::AND, DL, MVT::i16,
12237 DAG.getNode(ISD::ADD, DL, MVT::i16,
12238 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12239 DAG.getConstant(1, MVT::i16)),
12240 DAG.getConstant(3, MVT::i16));
12242 return DAG.getNode((VT.getSizeInBits() < 16 ?
12243 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12246 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12247 EVT VT = Op.getValueType();
12249 unsigned NumBits = VT.getSizeInBits();
12252 Op = Op.getOperand(0);
12253 if (VT == MVT::i8) {
12254 // Zero extend to i32 since there is not an i8 bsr.
12256 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12259 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12260 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12261 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12263 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12266 DAG.getConstant(NumBits+NumBits-1, OpVT),
12267 DAG.getConstant(X86::COND_E, MVT::i8),
12270 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12272 // Finally xor with NumBits-1.
12273 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12276 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12280 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12281 EVT VT = Op.getValueType();
12283 unsigned NumBits = VT.getSizeInBits();
12286 Op = Op.getOperand(0);
12287 if (VT == MVT::i8) {
12288 // Zero extend to i32 since there is not an i8 bsr.
12290 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12293 // Issue a bsr (scan bits in reverse).
12294 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12295 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12297 // And xor with NumBits-1.
12298 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12301 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12305 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12306 EVT VT = Op.getValueType();
12307 unsigned NumBits = VT.getSizeInBits();
12309 Op = Op.getOperand(0);
12311 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12312 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12313 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12315 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12318 DAG.getConstant(NumBits, VT),
12319 DAG.getConstant(X86::COND_E, MVT::i8),
12322 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12325 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12326 // ones, and then concatenate the result back.
12327 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12328 EVT VT = Op.getValueType();
12330 assert(VT.is256BitVector() && VT.isInteger() &&
12331 "Unsupported value type for operation");
12333 unsigned NumElems = VT.getVectorNumElements();
12336 // Extract the LHS vectors
12337 SDValue LHS = Op.getOperand(0);
12338 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12339 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12341 // Extract the RHS vectors
12342 SDValue RHS = Op.getOperand(1);
12343 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12344 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12346 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12347 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12349 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12350 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12351 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12354 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12355 assert(Op.getValueType().is256BitVector() &&
12356 Op.getValueType().isInteger() &&
12357 "Only handle AVX 256-bit vector integer operation");
12358 return Lower256IntArith(Op, DAG);
12361 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12362 assert(Op.getValueType().is256BitVector() &&
12363 Op.getValueType().isInteger() &&
12364 "Only handle AVX 256-bit vector integer operation");
12365 return Lower256IntArith(Op, DAG);
12368 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12369 SelectionDAG &DAG) {
12371 EVT VT = Op.getValueType();
12373 // Decompose 256-bit ops into smaller 128-bit ops.
12374 if (VT.is256BitVector() && !Subtarget->hasInt256())
12375 return Lower256IntArith(Op, DAG);
12377 SDValue A = Op.getOperand(0);
12378 SDValue B = Op.getOperand(1);
12380 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12381 if (VT == MVT::v4i32) {
12382 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12383 "Should not custom lower when pmuldq is available!");
12385 // Extract the odd parts.
12386 static const int UnpackMask[] = { 1, -1, 3, -1 };
12387 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12388 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12390 // Multiply the even parts.
12391 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12392 // Now multiply odd parts.
12393 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12395 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12396 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12398 // Merge the two vectors back together with a shuffle. This expands into 2
12400 static const int ShufMask[] = { 0, 4, 2, 6 };
12401 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12404 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12405 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12407 // Ahi = psrlqi(a, 32);
12408 // Bhi = psrlqi(b, 32);
12410 // AloBlo = pmuludq(a, b);
12411 // AloBhi = pmuludq(a, Bhi);
12412 // AhiBlo = pmuludq(Ahi, b);
12414 // AloBhi = psllqi(AloBhi, 32);
12415 // AhiBlo = psllqi(AhiBlo, 32);
12416 // return AloBlo + AloBhi + AhiBlo;
12418 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12419 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12421 // Bit cast to 32-bit vectors for MULUDQ
12422 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12423 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12424 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12425 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12426 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12427 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12429 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12430 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12431 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12433 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12434 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12436 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12437 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12440 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12441 EVT VT = Op.getValueType();
12442 EVT EltTy = VT.getVectorElementType();
12443 unsigned NumElts = VT.getVectorNumElements();
12444 SDValue N0 = Op.getOperand(0);
12447 // Lower sdiv X, pow2-const.
12448 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12452 APInt SplatValue, SplatUndef;
12453 unsigned SplatBitSize;
12455 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12457 EltTy.getSizeInBits() < SplatBitSize)
12460 if ((SplatValue != 0) &&
12461 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12462 unsigned Lg2 = SplatValue.countTrailingZeros();
12463 // Splat the sign bit.
12464 SmallVector<SDValue, 16> Sz(NumElts,
12465 DAG.getConstant(EltTy.getSizeInBits() - 1,
12467 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12468 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12470 // Add (N0 < 0) ? abs2 - 1 : 0;
12471 SmallVector<SDValue, 16> Amt(NumElts,
12472 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12474 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12475 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12477 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12478 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12479 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12480 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12483 // If we're dividing by a positive value, we're done. Otherwise, we must
12484 // negate the result.
12485 if (SplatValue.isNonNegative())
12488 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12489 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12490 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12495 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12496 const X86Subtarget *Subtarget) {
12497 EVT VT = Op.getValueType();
12499 SDValue R = Op.getOperand(0);
12500 SDValue Amt = Op.getOperand(1);
12502 // Optimize shl/srl/sra with constant shift amount.
12503 if (isSplatVector(Amt.getNode())) {
12504 SDValue SclrAmt = Amt->getOperand(0);
12505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12506 uint64_t ShiftAmt = C->getZExtValue();
12508 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12509 (Subtarget->hasInt256() &&
12510 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12511 (Subtarget->hasAVX512() &&
12512 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12513 if (Op.getOpcode() == ISD::SHL)
12514 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12516 if (Op.getOpcode() == ISD::SRL)
12517 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12519 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12520 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12524 if (VT == MVT::v16i8) {
12525 if (Op.getOpcode() == ISD::SHL) {
12526 // Make a large shift.
12527 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12528 MVT::v8i16, R, ShiftAmt,
12530 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12531 // Zero out the rightmost bits.
12532 SmallVector<SDValue, 16> V(16,
12533 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12535 return DAG.getNode(ISD::AND, dl, VT, SHL,
12536 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12538 if (Op.getOpcode() == ISD::SRL) {
12539 // Make a large shift.
12540 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12541 MVT::v8i16, R, ShiftAmt,
12543 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12544 // Zero out the leftmost bits.
12545 SmallVector<SDValue, 16> V(16,
12546 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12548 return DAG.getNode(ISD::AND, dl, VT, SRL,
12549 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12551 if (Op.getOpcode() == ISD::SRA) {
12552 if (ShiftAmt == 7) {
12553 // R s>> 7 === R s< 0
12554 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12555 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12558 // R s>> a === ((R u>> a) ^ m) - m
12559 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12560 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12562 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12563 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12564 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12567 llvm_unreachable("Unknown shift opcode.");
12570 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12571 if (Op.getOpcode() == ISD::SHL) {
12572 // Make a large shift.
12573 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12574 MVT::v16i16, R, ShiftAmt,
12576 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12577 // Zero out the rightmost bits.
12578 SmallVector<SDValue, 32> V(32,
12579 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12581 return DAG.getNode(ISD::AND, dl, VT, SHL,
12582 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12584 if (Op.getOpcode() == ISD::SRL) {
12585 // Make a large shift.
12586 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12587 MVT::v16i16, R, ShiftAmt,
12589 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12590 // Zero out the leftmost bits.
12591 SmallVector<SDValue, 32> V(32,
12592 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12594 return DAG.getNode(ISD::AND, dl, VT, SRL,
12595 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12597 if (Op.getOpcode() == ISD::SRA) {
12598 if (ShiftAmt == 7) {
12599 // R s>> 7 === R s< 0
12600 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12601 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12604 // R s>> a === ((R u>> a) ^ m) - m
12605 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12606 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12608 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12609 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12610 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12613 llvm_unreachable("Unknown shift opcode.");
12618 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12619 if (!Subtarget->is64Bit() &&
12620 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12621 Amt.getOpcode() == ISD::BITCAST &&
12622 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12623 Amt = Amt.getOperand(0);
12624 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12625 VT.getVectorNumElements();
12626 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12627 uint64_t ShiftAmt = 0;
12628 for (unsigned i = 0; i != Ratio; ++i) {
12629 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12633 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12635 // Check remaining shift amounts.
12636 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12637 uint64_t ShAmt = 0;
12638 for (unsigned j = 0; j != Ratio; ++j) {
12639 ConstantSDNode *C =
12640 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12644 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12646 if (ShAmt != ShiftAmt)
12649 switch (Op.getOpcode()) {
12651 llvm_unreachable("Unknown shift opcode!");
12653 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12656 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12659 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12667 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12668 const X86Subtarget* Subtarget) {
12669 EVT VT = Op.getValueType();
12671 SDValue R = Op.getOperand(0);
12672 SDValue Amt = Op.getOperand(1);
12674 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12675 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12676 (Subtarget->hasInt256() &&
12677 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12678 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12679 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12681 EVT EltVT = VT.getVectorElementType();
12683 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12684 unsigned NumElts = VT.getVectorNumElements();
12686 for (i = 0; i != NumElts; ++i) {
12687 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12691 for (j = i; j != NumElts; ++j) {
12692 SDValue Arg = Amt.getOperand(j);
12693 if (Arg.getOpcode() == ISD::UNDEF) continue;
12694 if (Arg != Amt.getOperand(i))
12697 if (i != NumElts && j == NumElts)
12698 BaseShAmt = Amt.getOperand(i);
12700 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12701 Amt = Amt.getOperand(0);
12702 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12703 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12704 SDValue InVec = Amt.getOperand(0);
12705 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12706 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12708 for (; i != NumElts; ++i) {
12709 SDValue Arg = InVec.getOperand(i);
12710 if (Arg.getOpcode() == ISD::UNDEF) continue;
12714 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12715 if (ConstantSDNode *C =
12716 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12717 unsigned SplatIdx =
12718 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12719 if (C->getZExtValue() == SplatIdx)
12720 BaseShAmt = InVec.getOperand(1);
12723 if (BaseShAmt.getNode() == 0)
12724 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12725 DAG.getIntPtrConstant(0));
12729 if (BaseShAmt.getNode()) {
12730 if (EltVT.bitsGT(MVT::i32))
12731 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12732 else if (EltVT.bitsLT(MVT::i32))
12733 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12735 switch (Op.getOpcode()) {
12737 llvm_unreachable("Unknown shift opcode!");
12739 switch (VT.getSimpleVT().SimpleTy) {
12740 default: return SDValue();
12749 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12752 switch (VT.getSimpleVT().SimpleTy) {
12753 default: return SDValue();
12760 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12763 switch (VT.getSimpleVT().SimpleTy) {
12764 default: return SDValue();
12773 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12779 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12780 if (!Subtarget->is64Bit() &&
12781 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12782 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12783 Amt.getOpcode() == ISD::BITCAST &&
12784 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12785 Amt = Amt.getOperand(0);
12786 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12787 VT.getVectorNumElements();
12788 std::vector<SDValue> Vals(Ratio);
12789 for (unsigned i = 0; i != Ratio; ++i)
12790 Vals[i] = Amt.getOperand(i);
12791 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12792 for (unsigned j = 0; j != Ratio; ++j)
12793 if (Vals[j] != Amt.getOperand(i + j))
12796 switch (Op.getOpcode()) {
12798 llvm_unreachable("Unknown shift opcode!");
12800 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12802 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12804 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12811 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12812 SelectionDAG &DAG) {
12814 EVT VT = Op.getValueType();
12816 SDValue R = Op.getOperand(0);
12817 SDValue Amt = Op.getOperand(1);
12820 if (!Subtarget->hasSSE2())
12823 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12827 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12831 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12833 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12834 if (Subtarget->hasInt256()) {
12835 if (Op.getOpcode() == ISD::SRL &&
12836 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12837 VT == MVT::v4i64 || VT == MVT::v8i32))
12839 if (Op.getOpcode() == ISD::SHL &&
12840 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12841 VT == MVT::v4i64 || VT == MVT::v8i32))
12843 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12847 // Lower SHL with variable shift amount.
12848 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12849 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12851 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12852 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12853 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12854 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12856 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12857 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12860 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12861 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12863 // Turn 'a' into a mask suitable for VSELECT
12864 SDValue VSelM = DAG.getConstant(0x80, VT);
12865 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12866 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12868 SDValue CM1 = DAG.getConstant(0x0f, VT);
12869 SDValue CM2 = DAG.getConstant(0x3f, VT);
12871 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12872 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12873 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
12874 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12875 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12878 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12879 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12880 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12882 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12883 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12884 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
12885 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12886 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12889 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12890 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12891 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12893 // return VSELECT(r, r+r, a);
12894 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12895 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12899 // Decompose 256-bit shifts into smaller 128-bit shifts.
12900 if (VT.is256BitVector()) {
12901 unsigned NumElems = VT.getVectorNumElements();
12902 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12903 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12905 // Extract the two vectors
12906 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12907 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12909 // Recreate the shift amount vectors
12910 SDValue Amt1, Amt2;
12911 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12912 // Constant shift amount
12913 SmallVector<SDValue, 4> Amt1Csts;
12914 SmallVector<SDValue, 4> Amt2Csts;
12915 for (unsigned i = 0; i != NumElems/2; ++i)
12916 Amt1Csts.push_back(Amt->getOperand(i));
12917 for (unsigned i = NumElems/2; i != NumElems; ++i)
12918 Amt2Csts.push_back(Amt->getOperand(i));
12920 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12921 &Amt1Csts[0], NumElems/2);
12922 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12923 &Amt2Csts[0], NumElems/2);
12925 // Variable shift amount
12926 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12927 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12930 // Issue new vector shifts for the smaller types
12931 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12932 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12934 // Concatenate the result back
12935 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12941 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12942 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12943 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12944 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12945 // has only one use.
12946 SDNode *N = Op.getNode();
12947 SDValue LHS = N->getOperand(0);
12948 SDValue RHS = N->getOperand(1);
12949 unsigned BaseOp = 0;
12952 switch (Op.getOpcode()) {
12953 default: llvm_unreachable("Unknown ovf instruction!");
12955 // A subtract of one will be selected as a INC. Note that INC doesn't
12956 // set CF, so we can't do this for UADDO.
12957 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12959 BaseOp = X86ISD::INC;
12960 Cond = X86::COND_O;
12963 BaseOp = X86ISD::ADD;
12964 Cond = X86::COND_O;
12967 BaseOp = X86ISD::ADD;
12968 Cond = X86::COND_B;
12971 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12972 // set CF, so we can't do this for USUBO.
12973 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12975 BaseOp = X86ISD::DEC;
12976 Cond = X86::COND_O;
12979 BaseOp = X86ISD::SUB;
12980 Cond = X86::COND_O;
12983 BaseOp = X86ISD::SUB;
12984 Cond = X86::COND_B;
12987 BaseOp = X86ISD::SMUL;
12988 Cond = X86::COND_O;
12990 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12991 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12993 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12996 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12997 DAG.getConstant(X86::COND_O, MVT::i32),
12998 SDValue(Sum.getNode(), 2));
13000 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13004 // Also sets EFLAGS.
13005 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13006 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13009 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13010 DAG.getConstant(Cond, MVT::i32),
13011 SDValue(Sum.getNode(), 1));
13013 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13016 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13017 SelectionDAG &DAG) const {
13019 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13020 EVT VT = Op.getValueType();
13022 if (!Subtarget->hasSSE2() || !VT.isVector())
13025 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13026 ExtraVT.getScalarType().getSizeInBits();
13028 switch (VT.getSimpleVT().SimpleTy) {
13029 default: return SDValue();
13032 if (!Subtarget->hasFp256())
13034 if (!Subtarget->hasInt256()) {
13035 // needs to be split
13036 unsigned NumElems = VT.getVectorNumElements();
13038 // Extract the LHS vectors
13039 SDValue LHS = Op.getOperand(0);
13040 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13041 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13043 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13044 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13046 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13047 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13048 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13050 SDValue Extra = DAG.getValueType(ExtraVT);
13052 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13053 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13055 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13060 // (sext (vzext x)) -> (vsext x)
13061 SDValue Op0 = Op.getOperand(0);
13062 SDValue Op00 = Op0.getOperand(0);
13064 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13065 if (Op0.getOpcode() == ISD::BITCAST &&
13066 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13067 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13068 if (Tmp1.getNode()) {
13069 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13070 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13071 "This optimization is invalid without a VZEXT.");
13072 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13075 // If the above didn't work, then just use Shift-Left + Shift-Right.
13076 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13078 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13084 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13085 SelectionDAG &DAG) {
13087 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13088 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13089 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13090 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13092 // The only fence that needs an instruction is a sequentially-consistent
13093 // cross-thread fence.
13094 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13095 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13096 // no-sse2). There isn't any reason to disable it if the target processor
13098 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13099 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13101 SDValue Chain = Op.getOperand(0);
13102 SDValue Zero = DAG.getConstant(0, MVT::i32);
13104 DAG.getRegister(X86::ESP, MVT::i32), // Base
13105 DAG.getTargetConstant(1, MVT::i8), // Scale
13106 DAG.getRegister(0, MVT::i32), // Index
13107 DAG.getTargetConstant(0, MVT::i32), // Disp
13108 DAG.getRegister(0, MVT::i32), // Segment.
13112 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13113 return SDValue(Res, 0);
13116 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13117 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13120 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13121 SelectionDAG &DAG) {
13122 EVT T = Op.getValueType();
13126 switch(T.getSimpleVT().SimpleTy) {
13127 default: llvm_unreachable("Invalid value type!");
13128 case MVT::i8: Reg = X86::AL; size = 1; break;
13129 case MVT::i16: Reg = X86::AX; size = 2; break;
13130 case MVT::i32: Reg = X86::EAX; size = 4; break;
13132 assert(Subtarget->is64Bit() && "Node not type legal!");
13133 Reg = X86::RAX; size = 8;
13136 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13137 Op.getOperand(2), SDValue());
13138 SDValue Ops[] = { cpIn.getValue(0),
13141 DAG.getTargetConstant(size, MVT::i8),
13142 cpIn.getValue(1) };
13143 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13144 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13145 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13146 Ops, array_lengthof(Ops), T, MMO);
13148 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13152 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13153 SelectionDAG &DAG) {
13154 assert(Subtarget->is64Bit() && "Result not type legalized?");
13155 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13156 SDValue TheChain = Op.getOperand(0);
13158 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13159 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13160 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13162 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13163 DAG.getConstant(32, MVT::i8));
13165 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13168 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13171 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13172 SelectionDAG &DAG) {
13173 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13174 MVT DstVT = Op.getSimpleValueType();
13175 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13176 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13177 assert((DstVT == MVT::i64 ||
13178 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13179 "Unexpected custom BITCAST");
13180 // i64 <=> MMX conversions are Legal.
13181 if (SrcVT==MVT::i64 && DstVT.isVector())
13183 if (DstVT==MVT::i64 && SrcVT.isVector())
13185 // MMX <=> MMX conversions are Legal.
13186 if (SrcVT.isVector() && DstVT.isVector())
13188 // All other conversions need to be expanded.
13192 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13193 SDNode *Node = Op.getNode();
13195 EVT T = Node->getValueType(0);
13196 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13197 DAG.getConstant(0, T), Node->getOperand(2));
13198 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13199 cast<AtomicSDNode>(Node)->getMemoryVT(),
13200 Node->getOperand(0),
13201 Node->getOperand(1), negOp,
13202 cast<AtomicSDNode>(Node)->getSrcValue(),
13203 cast<AtomicSDNode>(Node)->getAlignment(),
13204 cast<AtomicSDNode>(Node)->getOrdering(),
13205 cast<AtomicSDNode>(Node)->getSynchScope());
13208 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13209 SDNode *Node = Op.getNode();
13211 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13213 // Convert seq_cst store -> xchg
13214 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13215 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13216 // (The only way to get a 16-byte store is cmpxchg16b)
13217 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13218 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13219 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13220 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13221 cast<AtomicSDNode>(Node)->getMemoryVT(),
13222 Node->getOperand(0),
13223 Node->getOperand(1), Node->getOperand(2),
13224 cast<AtomicSDNode>(Node)->getMemOperand(),
13225 cast<AtomicSDNode>(Node)->getOrdering(),
13226 cast<AtomicSDNode>(Node)->getSynchScope());
13227 return Swap.getValue(1);
13229 // Other atomic stores have a simple pattern.
13233 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13234 EVT VT = Op.getNode()->getValueType(0);
13236 // Let legalize expand this if it isn't a legal type yet.
13237 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13240 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13243 bool ExtraOp = false;
13244 switch (Op.getOpcode()) {
13245 default: llvm_unreachable("Invalid code");
13246 case ISD::ADDC: Opc = X86ISD::ADD; break;
13247 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13248 case ISD::SUBC: Opc = X86ISD::SUB; break;
13249 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13253 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13255 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13256 Op.getOperand(1), Op.getOperand(2));
13259 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13260 SelectionDAG &DAG) {
13261 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13263 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13264 // which returns the values as { float, float } (in XMM0) or
13265 // { double, double } (which is returned in XMM0, XMM1).
13267 SDValue Arg = Op.getOperand(0);
13268 EVT ArgVT = Arg.getValueType();
13269 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13271 TargetLowering::ArgListTy Args;
13272 TargetLowering::ArgListEntry Entry;
13276 Entry.isSExt = false;
13277 Entry.isZExt = false;
13278 Args.push_back(Entry);
13280 bool isF64 = ArgVT == MVT::f64;
13281 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13282 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13283 // the results are returned via SRet in memory.
13284 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13285 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13286 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13288 Type *RetTy = isF64
13289 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13290 : (Type*)VectorType::get(ArgTy, 4);
13292 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13293 false, false, false, false, 0,
13294 CallingConv::C, /*isTaillCall=*/false,
13295 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13296 Callee, Args, DAG, dl);
13297 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13300 // Returned in xmm0 and xmm1.
13301 return CallResult.first;
13303 // Returned in bits 0:31 and 32:64 xmm0.
13304 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13305 CallResult.first, DAG.getIntPtrConstant(0));
13306 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13307 CallResult.first, DAG.getIntPtrConstant(1));
13308 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13309 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13312 /// LowerOperation - Provide custom lowering hooks for some operations.
13314 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13315 switch (Op.getOpcode()) {
13316 default: llvm_unreachable("Should not custom lower this!");
13317 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13318 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13319 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13320 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13321 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13322 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13323 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13324 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13325 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13326 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13327 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13328 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13329 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13330 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13331 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13332 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13333 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13334 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13335 case ISD::SHL_PARTS:
13336 case ISD::SRA_PARTS:
13337 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13338 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13339 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13340 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13341 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13342 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13343 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13344 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13345 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13346 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13347 case ISD::FABS: return LowerFABS(Op, DAG);
13348 case ISD::FNEG: return LowerFNEG(Op, DAG);
13349 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13350 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13351 case ISD::SETCC: return LowerSETCC(Op, DAG);
13352 case ISD::SELECT: return LowerSELECT(Op, DAG);
13353 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13354 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13355 case ISD::VASTART: return LowerVASTART(Op, DAG);
13356 case ISD::VAARG: return LowerVAARG(Op, DAG);
13357 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13358 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13359 case ISD::INTRINSIC_VOID:
13360 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13361 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13362 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13363 case ISD::FRAME_TO_ARGS_OFFSET:
13364 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13365 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13366 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13367 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13368 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13369 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13370 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13371 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13372 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13373 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13374 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13375 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13378 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13384 case ISD::UMULO: return LowerXALUO(Op, DAG);
13385 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13386 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13390 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13391 case ISD::ADD: return LowerADD(Op, DAG);
13392 case ISD::SUB: return LowerSUB(Op, DAG);
13393 case ISD::SDIV: return LowerSDIV(Op, DAG);
13394 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13398 static void ReplaceATOMIC_LOAD(SDNode *Node,
13399 SmallVectorImpl<SDValue> &Results,
13400 SelectionDAG &DAG) {
13402 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13404 // Convert wide load -> cmpxchg8b/cmpxchg16b
13405 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13406 // (The only way to get a 16-byte load is cmpxchg16b)
13407 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13408 SDValue Zero = DAG.getConstant(0, VT);
13409 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13410 Node->getOperand(0),
13411 Node->getOperand(1), Zero, Zero,
13412 cast<AtomicSDNode>(Node)->getMemOperand(),
13413 cast<AtomicSDNode>(Node)->getOrdering(),
13414 cast<AtomicSDNode>(Node)->getSynchScope());
13415 Results.push_back(Swap.getValue(0));
13416 Results.push_back(Swap.getValue(1));
13420 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13421 SelectionDAG &DAG, unsigned NewOp) {
13423 assert (Node->getValueType(0) == MVT::i64 &&
13424 "Only know how to expand i64 atomics");
13426 SDValue Chain = Node->getOperand(0);
13427 SDValue In1 = Node->getOperand(1);
13428 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13429 Node->getOperand(2), DAG.getIntPtrConstant(0));
13430 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13431 Node->getOperand(2), DAG.getIntPtrConstant(1));
13432 SDValue Ops[] = { Chain, In1, In2L, In2H };
13433 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13435 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13436 cast<MemSDNode>(Node)->getMemOperand());
13437 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13438 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13439 Results.push_back(Result.getValue(2));
13442 /// ReplaceNodeResults - Replace a node with an illegal result type
13443 /// with a new node built out of custom code.
13444 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13445 SmallVectorImpl<SDValue>&Results,
13446 SelectionDAG &DAG) const {
13448 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13449 switch (N->getOpcode()) {
13451 llvm_unreachable("Do not know how to custom type legalize this operation!");
13452 case ISD::SIGN_EXTEND_INREG:
13457 // We don't want to expand or promote these.
13459 case ISD::FP_TO_SINT:
13460 case ISD::FP_TO_UINT: {
13461 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13463 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13466 std::pair<SDValue,SDValue> Vals =
13467 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13468 SDValue FIST = Vals.first, StackSlot = Vals.second;
13469 if (FIST.getNode() != 0) {
13470 EVT VT = N->getValueType(0);
13471 // Return a load from the stack slot.
13472 if (StackSlot.getNode() != 0)
13473 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13474 MachinePointerInfo(),
13475 false, false, false, 0));
13477 Results.push_back(FIST);
13481 case ISD::UINT_TO_FP: {
13482 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13483 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13484 N->getValueType(0) != MVT::v2f32)
13486 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13488 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13490 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13491 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13492 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13493 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13494 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13495 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13498 case ISD::FP_ROUND: {
13499 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13501 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13502 Results.push_back(V);
13505 case ISD::READCYCLECOUNTER: {
13506 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13507 SDValue TheChain = N->getOperand(0);
13508 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13509 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13511 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13513 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13514 SDValue Ops[] = { eax, edx };
13515 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13516 array_lengthof(Ops)));
13517 Results.push_back(edx.getValue(1));
13520 case ISD::ATOMIC_CMP_SWAP: {
13521 EVT T = N->getValueType(0);
13522 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13523 bool Regs64bit = T == MVT::i128;
13524 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13525 SDValue cpInL, cpInH;
13526 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13527 DAG.getConstant(0, HalfT));
13528 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13529 DAG.getConstant(1, HalfT));
13530 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13531 Regs64bit ? X86::RAX : X86::EAX,
13533 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13534 Regs64bit ? X86::RDX : X86::EDX,
13535 cpInH, cpInL.getValue(1));
13536 SDValue swapInL, swapInH;
13537 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13538 DAG.getConstant(0, HalfT));
13539 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13540 DAG.getConstant(1, HalfT));
13541 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13542 Regs64bit ? X86::RBX : X86::EBX,
13543 swapInL, cpInH.getValue(1));
13544 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13545 Regs64bit ? X86::RCX : X86::ECX,
13546 swapInH, swapInL.getValue(1));
13547 SDValue Ops[] = { swapInH.getValue(0),
13549 swapInH.getValue(1) };
13550 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13551 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13552 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13553 X86ISD::LCMPXCHG8_DAG;
13554 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13555 Ops, array_lengthof(Ops), T, MMO);
13556 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13557 Regs64bit ? X86::RAX : X86::EAX,
13558 HalfT, Result.getValue(1));
13559 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13560 Regs64bit ? X86::RDX : X86::EDX,
13561 HalfT, cpOutL.getValue(2));
13562 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13563 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13564 Results.push_back(cpOutH.getValue(1));
13567 case ISD::ATOMIC_LOAD_ADD:
13568 case ISD::ATOMIC_LOAD_AND:
13569 case ISD::ATOMIC_LOAD_NAND:
13570 case ISD::ATOMIC_LOAD_OR:
13571 case ISD::ATOMIC_LOAD_SUB:
13572 case ISD::ATOMIC_LOAD_XOR:
13573 case ISD::ATOMIC_LOAD_MAX:
13574 case ISD::ATOMIC_LOAD_MIN:
13575 case ISD::ATOMIC_LOAD_UMAX:
13576 case ISD::ATOMIC_LOAD_UMIN:
13577 case ISD::ATOMIC_SWAP: {
13579 switch (N->getOpcode()) {
13580 default: llvm_unreachable("Unexpected opcode");
13581 case ISD::ATOMIC_LOAD_ADD:
13582 Opc = X86ISD::ATOMADD64_DAG;
13584 case ISD::ATOMIC_LOAD_AND:
13585 Opc = X86ISD::ATOMAND64_DAG;
13587 case ISD::ATOMIC_LOAD_NAND:
13588 Opc = X86ISD::ATOMNAND64_DAG;
13590 case ISD::ATOMIC_LOAD_OR:
13591 Opc = X86ISD::ATOMOR64_DAG;
13593 case ISD::ATOMIC_LOAD_SUB:
13594 Opc = X86ISD::ATOMSUB64_DAG;
13596 case ISD::ATOMIC_LOAD_XOR:
13597 Opc = X86ISD::ATOMXOR64_DAG;
13599 case ISD::ATOMIC_LOAD_MAX:
13600 Opc = X86ISD::ATOMMAX64_DAG;
13602 case ISD::ATOMIC_LOAD_MIN:
13603 Opc = X86ISD::ATOMMIN64_DAG;
13605 case ISD::ATOMIC_LOAD_UMAX:
13606 Opc = X86ISD::ATOMUMAX64_DAG;
13608 case ISD::ATOMIC_LOAD_UMIN:
13609 Opc = X86ISD::ATOMUMIN64_DAG;
13611 case ISD::ATOMIC_SWAP:
13612 Opc = X86ISD::ATOMSWAP64_DAG;
13615 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13618 case ISD::ATOMIC_LOAD:
13619 ReplaceATOMIC_LOAD(N, Results, DAG);
13623 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13625 default: return NULL;
13626 case X86ISD::BSF: return "X86ISD::BSF";
13627 case X86ISD::BSR: return "X86ISD::BSR";
13628 case X86ISD::SHLD: return "X86ISD::SHLD";
13629 case X86ISD::SHRD: return "X86ISD::SHRD";
13630 case X86ISD::FAND: return "X86ISD::FAND";
13631 case X86ISD::FANDN: return "X86ISD::FANDN";
13632 case X86ISD::FOR: return "X86ISD::FOR";
13633 case X86ISD::FXOR: return "X86ISD::FXOR";
13634 case X86ISD::FSRL: return "X86ISD::FSRL";
13635 case X86ISD::FILD: return "X86ISD::FILD";
13636 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13637 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13638 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13639 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13640 case X86ISD::FLD: return "X86ISD::FLD";
13641 case X86ISD::FST: return "X86ISD::FST";
13642 case X86ISD::CALL: return "X86ISD::CALL";
13643 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13644 case X86ISD::BT: return "X86ISD::BT";
13645 case X86ISD::CMP: return "X86ISD::CMP";
13646 case X86ISD::COMI: return "X86ISD::COMI";
13647 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13648 case X86ISD::CMPM: return "X86ISD::CMPM";
13649 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13650 case X86ISD::SETCC: return "X86ISD::SETCC";
13651 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13652 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13653 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13654 case X86ISD::CMOV: return "X86ISD::CMOV";
13655 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13656 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13657 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13658 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13659 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13660 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13661 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13662 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13663 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13664 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13665 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13666 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13667 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13668 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13669 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13670 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13671 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13672 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13673 case X86ISD::HADD: return "X86ISD::HADD";
13674 case X86ISD::HSUB: return "X86ISD::HSUB";
13675 case X86ISD::FHADD: return "X86ISD::FHADD";
13676 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13677 case X86ISD::UMAX: return "X86ISD::UMAX";
13678 case X86ISD::UMIN: return "X86ISD::UMIN";
13679 case X86ISD::SMAX: return "X86ISD::SMAX";
13680 case X86ISD::SMIN: return "X86ISD::SMIN";
13681 case X86ISD::FMAX: return "X86ISD::FMAX";
13682 case X86ISD::FMIN: return "X86ISD::FMIN";
13683 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13684 case X86ISD::FMINC: return "X86ISD::FMINC";
13685 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13686 case X86ISD::FRCP: return "X86ISD::FRCP";
13687 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13688 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13689 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13690 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13691 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13692 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13693 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13694 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13695 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13696 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13697 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13698 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13699 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13700 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13701 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13702 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13703 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13704 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13705 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13706 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13707 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13708 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13709 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13710 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13711 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13712 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13713 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13714 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13715 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13716 case X86ISD::VSHL: return "X86ISD::VSHL";
13717 case X86ISD::VSRL: return "X86ISD::VSRL";
13718 case X86ISD::VSRA: return "X86ISD::VSRA";
13719 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13720 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13721 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13722 case X86ISD::CMPP: return "X86ISD::CMPP";
13723 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13724 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13725 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13726 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13727 case X86ISD::ADD: return "X86ISD::ADD";
13728 case X86ISD::SUB: return "X86ISD::SUB";
13729 case X86ISD::ADC: return "X86ISD::ADC";
13730 case X86ISD::SBB: return "X86ISD::SBB";
13731 case X86ISD::SMUL: return "X86ISD::SMUL";
13732 case X86ISD::UMUL: return "X86ISD::UMUL";
13733 case X86ISD::INC: return "X86ISD::INC";
13734 case X86ISD::DEC: return "X86ISD::DEC";
13735 case X86ISD::OR: return "X86ISD::OR";
13736 case X86ISD::XOR: return "X86ISD::XOR";
13737 case X86ISD::AND: return "X86ISD::AND";
13738 case X86ISD::BLSI: return "X86ISD::BLSI";
13739 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13740 case X86ISD::BLSR: return "X86ISD::BLSR";
13741 case X86ISD::BZHI: return "X86ISD::BZHI";
13742 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13743 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13744 case X86ISD::PTEST: return "X86ISD::PTEST";
13745 case X86ISD::TESTP: return "X86ISD::TESTP";
13746 case X86ISD::TESTM: return "X86ISD::TESTM";
13747 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13748 case X86ISD::KTEST: return "X86ISD::KTEST";
13749 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13750 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13751 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13752 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13753 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13754 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13755 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13756 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13757 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13758 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13759 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13760 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13761 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13762 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13763 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13764 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13765 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13766 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13767 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13768 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13769 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13770 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13771 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13772 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13773 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13774 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13775 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13776 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13777 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13778 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13779 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13780 case X86ISD::SAHF: return "X86ISD::SAHF";
13781 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13782 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13783 case X86ISD::FMADD: return "X86ISD::FMADD";
13784 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13785 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13786 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13787 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13788 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13789 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13790 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13791 case X86ISD::XTEST: return "X86ISD::XTEST";
13795 // isLegalAddressingMode - Return true if the addressing mode represented
13796 // by AM is legal for this target, for a load/store of the specified type.
13797 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13799 // X86 supports extremely general addressing modes.
13800 CodeModel::Model M = getTargetMachine().getCodeModel();
13801 Reloc::Model R = getTargetMachine().getRelocationModel();
13803 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13804 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13809 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13811 // If a reference to this global requires an extra load, we can't fold it.
13812 if (isGlobalStubReference(GVFlags))
13815 // If BaseGV requires a register for the PIC base, we cannot also have a
13816 // BaseReg specified.
13817 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13820 // If lower 4G is not available, then we must use rip-relative addressing.
13821 if ((M != CodeModel::Small || R != Reloc::Static) &&
13822 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13826 switch (AM.Scale) {
13832 // These scales always work.
13837 // These scales are formed with basereg+scalereg. Only accept if there is
13842 default: // Other stuff never works.
13849 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13850 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13852 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13853 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13854 return NumBits1 > NumBits2;
13857 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13858 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13861 if (!isTypeLegal(EVT::getEVT(Ty1)))
13864 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13866 // Assuming the caller doesn't have a zeroext or signext return parameter,
13867 // truncation all the way down to i1 is valid.
13871 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13872 return isInt<32>(Imm);
13875 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13876 // Can also use sub to handle negated immediates.
13877 return isInt<32>(Imm);
13880 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13881 if (!VT1.isInteger() || !VT2.isInteger())
13883 unsigned NumBits1 = VT1.getSizeInBits();
13884 unsigned NumBits2 = VT2.getSizeInBits();
13885 return NumBits1 > NumBits2;
13888 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13889 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13890 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13893 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13894 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13895 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13898 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13899 EVT VT1 = Val.getValueType();
13900 if (isZExtFree(VT1, VT2))
13903 if (Val.getOpcode() != ISD::LOAD)
13906 if (!VT1.isSimple() || !VT1.isInteger() ||
13907 !VT2.isSimple() || !VT2.isInteger())
13910 switch (VT1.getSimpleVT().SimpleTy) {
13915 // X86 has 8, 16, and 32-bit zero-extending loads.
13923 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13924 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13927 VT = VT.getScalarType();
13929 if (!VT.isSimple())
13932 switch (VT.getSimpleVT().SimpleTy) {
13943 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13944 // i16 instructions are longer (0x66 prefix) and potentially slower.
13945 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13948 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13949 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13950 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13951 /// are assumed to be legal.
13953 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13955 if (!VT.isSimple())
13958 MVT SVT = VT.getSimpleVT();
13960 // Very little shuffling can be done for 64-bit vectors right now.
13961 if (VT.getSizeInBits() == 64)
13964 // FIXME: pshufb, blends, shifts.
13965 return (SVT.getVectorNumElements() == 2 ||
13966 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13967 isMOVLMask(M, SVT) ||
13968 isSHUFPMask(M, SVT) ||
13969 isPSHUFDMask(M, SVT) ||
13970 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13971 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13972 isPALIGNRMask(M, SVT, Subtarget) ||
13973 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13974 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13975 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13976 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
13980 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13982 if (!VT.isSimple())
13985 MVT SVT = VT.getSimpleVT();
13986 unsigned NumElts = SVT.getVectorNumElements();
13987 // FIXME: This collection of masks seems suspect.
13990 if (NumElts == 4 && SVT.is128BitVector()) {
13991 return (isMOVLMask(Mask, SVT) ||
13992 isCommutedMOVLMask(Mask, SVT, true) ||
13993 isSHUFPMask(Mask, SVT) ||
13994 isSHUFPMask(Mask, SVT, /* Commuted */ true));
13999 //===----------------------------------------------------------------------===//
14000 // X86 Scheduler Hooks
14001 //===----------------------------------------------------------------------===//
14003 /// Utility function to emit xbegin specifying the start of an RTM region.
14004 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14005 const TargetInstrInfo *TII) {
14006 DebugLoc DL = MI->getDebugLoc();
14008 const BasicBlock *BB = MBB->getBasicBlock();
14009 MachineFunction::iterator I = MBB;
14012 // For the v = xbegin(), we generate
14023 MachineBasicBlock *thisMBB = MBB;
14024 MachineFunction *MF = MBB->getParent();
14025 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14026 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14027 MF->insert(I, mainMBB);
14028 MF->insert(I, sinkMBB);
14030 // Transfer the remainder of BB and its successor edges to sinkMBB.
14031 sinkMBB->splice(sinkMBB->begin(), MBB,
14032 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14033 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14037 // # fallthrough to mainMBB
14038 // # abortion to sinkMBB
14039 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14040 thisMBB->addSuccessor(mainMBB);
14041 thisMBB->addSuccessor(sinkMBB);
14045 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14046 mainMBB->addSuccessor(sinkMBB);
14049 // EAX is live into the sinkMBB
14050 sinkMBB->addLiveIn(X86::EAX);
14051 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14052 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14055 MI->eraseFromParent();
14059 // Get CMPXCHG opcode for the specified data type.
14060 static unsigned getCmpXChgOpcode(EVT VT) {
14061 switch (VT.getSimpleVT().SimpleTy) {
14062 case MVT::i8: return X86::LCMPXCHG8;
14063 case MVT::i16: return X86::LCMPXCHG16;
14064 case MVT::i32: return X86::LCMPXCHG32;
14065 case MVT::i64: return X86::LCMPXCHG64;
14069 llvm_unreachable("Invalid operand size!");
14072 // Get LOAD opcode for the specified data type.
14073 static unsigned getLoadOpcode(EVT VT) {
14074 switch (VT.getSimpleVT().SimpleTy) {
14075 case MVT::i8: return X86::MOV8rm;
14076 case MVT::i16: return X86::MOV16rm;
14077 case MVT::i32: return X86::MOV32rm;
14078 case MVT::i64: return X86::MOV64rm;
14082 llvm_unreachable("Invalid operand size!");
14085 // Get opcode of the non-atomic one from the specified atomic instruction.
14086 static unsigned getNonAtomicOpcode(unsigned Opc) {
14088 case X86::ATOMAND8: return X86::AND8rr;
14089 case X86::ATOMAND16: return X86::AND16rr;
14090 case X86::ATOMAND32: return X86::AND32rr;
14091 case X86::ATOMAND64: return X86::AND64rr;
14092 case X86::ATOMOR8: return X86::OR8rr;
14093 case X86::ATOMOR16: return X86::OR16rr;
14094 case X86::ATOMOR32: return X86::OR32rr;
14095 case X86::ATOMOR64: return X86::OR64rr;
14096 case X86::ATOMXOR8: return X86::XOR8rr;
14097 case X86::ATOMXOR16: return X86::XOR16rr;
14098 case X86::ATOMXOR32: return X86::XOR32rr;
14099 case X86::ATOMXOR64: return X86::XOR64rr;
14101 llvm_unreachable("Unhandled atomic-load-op opcode!");
14104 // Get opcode of the non-atomic one from the specified atomic instruction with
14106 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14107 unsigned &ExtraOpc) {
14109 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14110 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14111 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14112 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14113 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14114 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14115 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14116 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14117 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14118 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14119 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14120 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14121 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14122 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14123 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14124 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14125 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14126 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14127 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14128 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14130 llvm_unreachable("Unhandled atomic-load-op opcode!");
14133 // Get opcode of the non-atomic one from the specified atomic instruction for
14134 // 64-bit data type on 32-bit target.
14135 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14137 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14138 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14139 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14140 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14141 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14142 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14143 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14144 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14145 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14146 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14148 llvm_unreachable("Unhandled atomic-load-op opcode!");
14151 // Get opcode of the non-atomic one from the specified atomic instruction for
14152 // 64-bit data type on 32-bit target with extra opcode.
14153 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14155 unsigned &ExtraOpc) {
14157 case X86::ATOMNAND6432:
14158 ExtraOpc = X86::NOT32r;
14159 HiOpc = X86::AND32rr;
14160 return X86::AND32rr;
14162 llvm_unreachable("Unhandled atomic-load-op opcode!");
14165 // Get pseudo CMOV opcode from the specified data type.
14166 static unsigned getPseudoCMOVOpc(EVT VT) {
14167 switch (VT.getSimpleVT().SimpleTy) {
14168 case MVT::i8: return X86::CMOV_GR8;
14169 case MVT::i16: return X86::CMOV_GR16;
14170 case MVT::i32: return X86::CMOV_GR32;
14174 llvm_unreachable("Unknown CMOV opcode!");
14177 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14178 // They will be translated into a spin-loop or compare-exchange loop from
14181 // dst = atomic-fetch-op MI.addr, MI.val
14187 // t1 = LOAD MI.addr
14189 // t4 = phi(t1, t3 / loop)
14190 // t2 = OP MI.val, t4
14192 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14198 MachineBasicBlock *
14199 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14200 MachineBasicBlock *MBB) const {
14201 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14202 DebugLoc DL = MI->getDebugLoc();
14204 MachineFunction *MF = MBB->getParent();
14205 MachineRegisterInfo &MRI = MF->getRegInfo();
14207 const BasicBlock *BB = MBB->getBasicBlock();
14208 MachineFunction::iterator I = MBB;
14211 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14212 "Unexpected number of operands");
14214 assert(MI->hasOneMemOperand() &&
14215 "Expected atomic-load-op to have one memoperand");
14217 // Memory Reference
14218 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14219 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14221 unsigned DstReg, SrcReg;
14222 unsigned MemOpndSlot;
14224 unsigned CurOp = 0;
14226 DstReg = MI->getOperand(CurOp++).getReg();
14227 MemOpndSlot = CurOp;
14228 CurOp += X86::AddrNumOperands;
14229 SrcReg = MI->getOperand(CurOp++).getReg();
14231 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14232 MVT::SimpleValueType VT = *RC->vt_begin();
14233 unsigned t1 = MRI.createVirtualRegister(RC);
14234 unsigned t2 = MRI.createVirtualRegister(RC);
14235 unsigned t3 = MRI.createVirtualRegister(RC);
14236 unsigned t4 = MRI.createVirtualRegister(RC);
14237 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14239 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14240 unsigned LOADOpc = getLoadOpcode(VT);
14242 // For the atomic load-arith operator, we generate
14245 // t1 = LOAD [MI.addr]
14247 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14248 // t1 = OP MI.val, EAX
14250 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14256 MachineBasicBlock *thisMBB = MBB;
14257 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14258 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14259 MF->insert(I, mainMBB);
14260 MF->insert(I, sinkMBB);
14262 MachineInstrBuilder MIB;
14264 // Transfer the remainder of BB and its successor edges to sinkMBB.
14265 sinkMBB->splice(sinkMBB->begin(), MBB,
14266 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14267 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14270 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14271 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14272 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14274 NewMO.setIsKill(false);
14275 MIB.addOperand(NewMO);
14277 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14278 unsigned flags = (*MMOI)->getFlags();
14279 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14280 MachineMemOperand *MMO =
14281 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14282 (*MMOI)->getSize(),
14283 (*MMOI)->getBaseAlignment(),
14284 (*MMOI)->getTBAAInfo(),
14285 (*MMOI)->getRanges());
14286 MIB.addMemOperand(MMO);
14289 thisMBB->addSuccessor(mainMBB);
14292 MachineBasicBlock *origMainMBB = mainMBB;
14295 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14296 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14298 unsigned Opc = MI->getOpcode();
14301 llvm_unreachable("Unhandled atomic-load-op opcode!");
14302 case X86::ATOMAND8:
14303 case X86::ATOMAND16:
14304 case X86::ATOMAND32:
14305 case X86::ATOMAND64:
14307 case X86::ATOMOR16:
14308 case X86::ATOMOR32:
14309 case X86::ATOMOR64:
14310 case X86::ATOMXOR8:
14311 case X86::ATOMXOR16:
14312 case X86::ATOMXOR32:
14313 case X86::ATOMXOR64: {
14314 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14315 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14319 case X86::ATOMNAND8:
14320 case X86::ATOMNAND16:
14321 case X86::ATOMNAND32:
14322 case X86::ATOMNAND64: {
14323 unsigned Tmp = MRI.createVirtualRegister(RC);
14325 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14326 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14328 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14331 case X86::ATOMMAX8:
14332 case X86::ATOMMAX16:
14333 case X86::ATOMMAX32:
14334 case X86::ATOMMAX64:
14335 case X86::ATOMMIN8:
14336 case X86::ATOMMIN16:
14337 case X86::ATOMMIN32:
14338 case X86::ATOMMIN64:
14339 case X86::ATOMUMAX8:
14340 case X86::ATOMUMAX16:
14341 case X86::ATOMUMAX32:
14342 case X86::ATOMUMAX64:
14343 case X86::ATOMUMIN8:
14344 case X86::ATOMUMIN16:
14345 case X86::ATOMUMIN32:
14346 case X86::ATOMUMIN64: {
14348 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14350 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14354 if (Subtarget->hasCMov()) {
14355 if (VT != MVT::i8) {
14357 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14361 // Promote i8 to i32 to use CMOV32
14362 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14363 const TargetRegisterClass *RC32 =
14364 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14365 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14366 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14367 unsigned Tmp = MRI.createVirtualRegister(RC32);
14369 unsigned Undef = MRI.createVirtualRegister(RC32);
14370 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14372 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14375 .addImm(X86::sub_8bit);
14376 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14379 .addImm(X86::sub_8bit);
14381 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14385 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14386 .addReg(Tmp, 0, X86::sub_8bit);
14389 // Use pseudo select and lower them.
14390 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14391 "Invalid atomic-load-op transformation!");
14392 unsigned SelOpc = getPseudoCMOVOpc(VT);
14393 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14394 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14395 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14396 .addReg(SrcReg).addReg(t4)
14398 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14399 // Replace the original PHI node as mainMBB is changed after CMOV
14401 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14402 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14403 Phi->eraseFromParent();
14409 // Copy PhyReg back from virtual register.
14410 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14413 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14414 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14415 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14417 NewMO.setIsKill(false);
14418 MIB.addOperand(NewMO);
14421 MIB.setMemRefs(MMOBegin, MMOEnd);
14423 // Copy PhyReg back to virtual register.
14424 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14427 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14429 mainMBB->addSuccessor(origMainMBB);
14430 mainMBB->addSuccessor(sinkMBB);
14433 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14434 TII->get(TargetOpcode::COPY), DstReg)
14437 MI->eraseFromParent();
14441 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14442 // instructions. They will be translated into a spin-loop or compare-exchange
14446 // dst = atomic-fetch-op MI.addr, MI.val
14452 // t1L = LOAD [MI.addr + 0]
14453 // t1H = LOAD [MI.addr + 4]
14455 // t4L = phi(t1L, t3L / loop)
14456 // t4H = phi(t1H, t3H / loop)
14457 // t2L = OP MI.val.lo, t4L
14458 // t2H = OP MI.val.hi, t4H
14463 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14471 MachineBasicBlock *
14472 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14473 MachineBasicBlock *MBB) const {
14474 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14475 DebugLoc DL = MI->getDebugLoc();
14477 MachineFunction *MF = MBB->getParent();
14478 MachineRegisterInfo &MRI = MF->getRegInfo();
14480 const BasicBlock *BB = MBB->getBasicBlock();
14481 MachineFunction::iterator I = MBB;
14484 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14485 "Unexpected number of operands");
14487 assert(MI->hasOneMemOperand() &&
14488 "Expected atomic-load-op32 to have one memoperand");
14490 // Memory Reference
14491 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14492 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14494 unsigned DstLoReg, DstHiReg;
14495 unsigned SrcLoReg, SrcHiReg;
14496 unsigned MemOpndSlot;
14498 unsigned CurOp = 0;
14500 DstLoReg = MI->getOperand(CurOp++).getReg();
14501 DstHiReg = MI->getOperand(CurOp++).getReg();
14502 MemOpndSlot = CurOp;
14503 CurOp += X86::AddrNumOperands;
14504 SrcLoReg = MI->getOperand(CurOp++).getReg();
14505 SrcHiReg = MI->getOperand(CurOp++).getReg();
14507 const TargetRegisterClass *RC = &X86::GR32RegClass;
14508 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14510 unsigned t1L = MRI.createVirtualRegister(RC);
14511 unsigned t1H = MRI.createVirtualRegister(RC);
14512 unsigned t2L = MRI.createVirtualRegister(RC);
14513 unsigned t2H = MRI.createVirtualRegister(RC);
14514 unsigned t3L = MRI.createVirtualRegister(RC);
14515 unsigned t3H = MRI.createVirtualRegister(RC);
14516 unsigned t4L = MRI.createVirtualRegister(RC);
14517 unsigned t4H = MRI.createVirtualRegister(RC);
14519 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14520 unsigned LOADOpc = X86::MOV32rm;
14522 // For the atomic load-arith operator, we generate
14525 // t1L = LOAD [MI.addr + 0]
14526 // t1H = LOAD [MI.addr + 4]
14528 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14529 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14530 // t2L = OP MI.val.lo, t4L
14531 // t2H = OP MI.val.hi, t4H
14534 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14542 MachineBasicBlock *thisMBB = MBB;
14543 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14544 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14545 MF->insert(I, mainMBB);
14546 MF->insert(I, sinkMBB);
14548 MachineInstrBuilder MIB;
14550 // Transfer the remainder of BB and its successor edges to sinkMBB.
14551 sinkMBB->splice(sinkMBB->begin(), MBB,
14552 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14553 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14557 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14558 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14559 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14561 NewMO.setIsKill(false);
14562 MIB.addOperand(NewMO);
14564 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14565 unsigned flags = (*MMOI)->getFlags();
14566 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14567 MachineMemOperand *MMO =
14568 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14569 (*MMOI)->getSize(),
14570 (*MMOI)->getBaseAlignment(),
14571 (*MMOI)->getTBAAInfo(),
14572 (*MMOI)->getRanges());
14573 MIB.addMemOperand(MMO);
14575 MachineInstr *LowMI = MIB;
14578 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14579 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14580 if (i == X86::AddrDisp) {
14581 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14583 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14585 NewMO.setIsKill(false);
14586 MIB.addOperand(NewMO);
14589 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14591 thisMBB->addSuccessor(mainMBB);
14594 MachineBasicBlock *origMainMBB = mainMBB;
14597 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14598 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14599 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14600 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14602 unsigned Opc = MI->getOpcode();
14605 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14606 case X86::ATOMAND6432:
14607 case X86::ATOMOR6432:
14608 case X86::ATOMXOR6432:
14609 case X86::ATOMADD6432:
14610 case X86::ATOMSUB6432: {
14612 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14613 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14615 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14619 case X86::ATOMNAND6432: {
14620 unsigned HiOpc, NOTOpc;
14621 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14622 unsigned TmpL = MRI.createVirtualRegister(RC);
14623 unsigned TmpH = MRI.createVirtualRegister(RC);
14624 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14626 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14628 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14629 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14632 case X86::ATOMMAX6432:
14633 case X86::ATOMMIN6432:
14634 case X86::ATOMUMAX6432:
14635 case X86::ATOMUMIN6432: {
14637 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14638 unsigned cL = MRI.createVirtualRegister(RC8);
14639 unsigned cH = MRI.createVirtualRegister(RC8);
14640 unsigned cL32 = MRI.createVirtualRegister(RC);
14641 unsigned cH32 = MRI.createVirtualRegister(RC);
14642 unsigned cc = MRI.createVirtualRegister(RC);
14643 // cl := cmp src_lo, lo
14644 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14645 .addReg(SrcLoReg).addReg(t4L);
14646 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14647 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14648 // ch := cmp src_hi, hi
14649 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14650 .addReg(SrcHiReg).addReg(t4H);
14651 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14652 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14653 // cc := if (src_hi == hi) ? cl : ch;
14654 if (Subtarget->hasCMov()) {
14655 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14656 .addReg(cH32).addReg(cL32);
14658 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14659 .addReg(cH32).addReg(cL32)
14660 .addImm(X86::COND_E);
14661 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14663 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14664 if (Subtarget->hasCMov()) {
14665 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14666 .addReg(SrcLoReg).addReg(t4L);
14667 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14668 .addReg(SrcHiReg).addReg(t4H);
14670 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14671 .addReg(SrcLoReg).addReg(t4L)
14672 .addImm(X86::COND_NE);
14673 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14674 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14675 // 2nd CMOV lowering.
14676 mainMBB->addLiveIn(X86::EFLAGS);
14677 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14678 .addReg(SrcHiReg).addReg(t4H)
14679 .addImm(X86::COND_NE);
14680 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14681 // Replace the original PHI node as mainMBB is changed after CMOV
14683 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14684 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14685 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14686 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14687 PhiL->eraseFromParent();
14688 PhiH->eraseFromParent();
14692 case X86::ATOMSWAP6432: {
14694 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14695 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14696 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14701 // Copy EDX:EAX back from HiReg:LoReg
14702 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14703 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14704 // Copy ECX:EBX from t1H:t1L
14705 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14706 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14708 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14709 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14710 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14712 NewMO.setIsKill(false);
14713 MIB.addOperand(NewMO);
14715 MIB.setMemRefs(MMOBegin, MMOEnd);
14717 // Copy EDX:EAX back to t3H:t3L
14718 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14719 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14721 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14723 mainMBB->addSuccessor(origMainMBB);
14724 mainMBB->addSuccessor(sinkMBB);
14727 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14728 TII->get(TargetOpcode::COPY), DstLoReg)
14730 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14731 TII->get(TargetOpcode::COPY), DstHiReg)
14734 MI->eraseFromParent();
14738 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14739 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14740 // in the .td file.
14741 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14742 const TargetInstrInfo *TII) {
14744 switch (MI->getOpcode()) {
14745 default: llvm_unreachable("illegal opcode!");
14746 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14747 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14748 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14749 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14750 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14751 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14752 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14753 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14756 DebugLoc dl = MI->getDebugLoc();
14757 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14759 unsigned NumArgs = MI->getNumOperands();
14760 for (unsigned i = 1; i < NumArgs; ++i) {
14761 MachineOperand &Op = MI->getOperand(i);
14762 if (!(Op.isReg() && Op.isImplicit()))
14763 MIB.addOperand(Op);
14765 if (MI->hasOneMemOperand())
14766 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14768 BuildMI(*BB, MI, dl,
14769 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14770 .addReg(X86::XMM0);
14772 MI->eraseFromParent();
14776 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14777 // defs in an instruction pattern
14778 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14779 const TargetInstrInfo *TII) {
14781 switch (MI->getOpcode()) {
14782 default: llvm_unreachable("illegal opcode!");
14783 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14784 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14785 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14786 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14787 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14788 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14789 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14790 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14793 DebugLoc dl = MI->getDebugLoc();
14794 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14796 unsigned NumArgs = MI->getNumOperands(); // remove the results
14797 for (unsigned i = 1; i < NumArgs; ++i) {
14798 MachineOperand &Op = MI->getOperand(i);
14799 if (!(Op.isReg() && Op.isImplicit()))
14800 MIB.addOperand(Op);
14802 if (MI->hasOneMemOperand())
14803 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14805 BuildMI(*BB, MI, dl,
14806 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14809 MI->eraseFromParent();
14813 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14814 const TargetInstrInfo *TII,
14815 const X86Subtarget* Subtarget) {
14816 DebugLoc dl = MI->getDebugLoc();
14818 // Address into RAX/EAX, other two args into ECX, EDX.
14819 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14820 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14821 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14822 for (int i = 0; i < X86::AddrNumOperands; ++i)
14823 MIB.addOperand(MI->getOperand(i));
14825 unsigned ValOps = X86::AddrNumOperands;
14826 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14827 .addReg(MI->getOperand(ValOps).getReg());
14828 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14829 .addReg(MI->getOperand(ValOps+1).getReg());
14831 // The instruction doesn't actually take any operands though.
14832 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14834 MI->eraseFromParent(); // The pseudo is gone now.
14838 MachineBasicBlock *
14839 X86TargetLowering::EmitVAARG64WithCustomInserter(
14841 MachineBasicBlock *MBB) const {
14842 // Emit va_arg instruction on X86-64.
14844 // Operands to this pseudo-instruction:
14845 // 0 ) Output : destination address (reg)
14846 // 1-5) Input : va_list address (addr, i64mem)
14847 // 6 ) ArgSize : Size (in bytes) of vararg type
14848 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14849 // 8 ) Align : Alignment of type
14850 // 9 ) EFLAGS (implicit-def)
14852 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14853 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14855 unsigned DestReg = MI->getOperand(0).getReg();
14856 MachineOperand &Base = MI->getOperand(1);
14857 MachineOperand &Scale = MI->getOperand(2);
14858 MachineOperand &Index = MI->getOperand(3);
14859 MachineOperand &Disp = MI->getOperand(4);
14860 MachineOperand &Segment = MI->getOperand(5);
14861 unsigned ArgSize = MI->getOperand(6).getImm();
14862 unsigned ArgMode = MI->getOperand(7).getImm();
14863 unsigned Align = MI->getOperand(8).getImm();
14865 // Memory Reference
14866 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14867 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14868 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14870 // Machine Information
14871 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14872 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14873 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14874 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14875 DebugLoc DL = MI->getDebugLoc();
14877 // struct va_list {
14880 // i64 overflow_area (address)
14881 // i64 reg_save_area (address)
14883 // sizeof(va_list) = 24
14884 // alignment(va_list) = 8
14886 unsigned TotalNumIntRegs = 6;
14887 unsigned TotalNumXMMRegs = 8;
14888 bool UseGPOffset = (ArgMode == 1);
14889 bool UseFPOffset = (ArgMode == 2);
14890 unsigned MaxOffset = TotalNumIntRegs * 8 +
14891 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14893 /* Align ArgSize to a multiple of 8 */
14894 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14895 bool NeedsAlign = (Align > 8);
14897 MachineBasicBlock *thisMBB = MBB;
14898 MachineBasicBlock *overflowMBB;
14899 MachineBasicBlock *offsetMBB;
14900 MachineBasicBlock *endMBB;
14902 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14903 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14904 unsigned OffsetReg = 0;
14906 if (!UseGPOffset && !UseFPOffset) {
14907 // If we only pull from the overflow region, we don't create a branch.
14908 // We don't need to alter control flow.
14909 OffsetDestReg = 0; // unused
14910 OverflowDestReg = DestReg;
14913 overflowMBB = thisMBB;
14916 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14917 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14918 // If not, pull from overflow_area. (branch to overflowMBB)
14923 // offsetMBB overflowMBB
14928 // Registers for the PHI in endMBB
14929 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14930 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14932 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14933 MachineFunction *MF = MBB->getParent();
14934 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14935 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14936 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14938 MachineFunction::iterator MBBIter = MBB;
14941 // Insert the new basic blocks
14942 MF->insert(MBBIter, offsetMBB);
14943 MF->insert(MBBIter, overflowMBB);
14944 MF->insert(MBBIter, endMBB);
14946 // Transfer the remainder of MBB and its successor edges to endMBB.
14947 endMBB->splice(endMBB->begin(), thisMBB,
14948 llvm::next(MachineBasicBlock::iterator(MI)),
14950 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14952 // Make offsetMBB and overflowMBB successors of thisMBB
14953 thisMBB->addSuccessor(offsetMBB);
14954 thisMBB->addSuccessor(overflowMBB);
14956 // endMBB is a successor of both offsetMBB and overflowMBB
14957 offsetMBB->addSuccessor(endMBB);
14958 overflowMBB->addSuccessor(endMBB);
14960 // Load the offset value into a register
14961 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14962 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14966 .addDisp(Disp, UseFPOffset ? 4 : 0)
14967 .addOperand(Segment)
14968 .setMemRefs(MMOBegin, MMOEnd);
14970 // Check if there is enough room left to pull this argument.
14971 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14973 .addImm(MaxOffset + 8 - ArgSizeA8);
14975 // Branch to "overflowMBB" if offset >= max
14976 // Fall through to "offsetMBB" otherwise
14977 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14978 .addMBB(overflowMBB);
14981 // In offsetMBB, emit code to use the reg_save_area.
14983 assert(OffsetReg != 0);
14985 // Read the reg_save_area address.
14986 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14987 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14992 .addOperand(Segment)
14993 .setMemRefs(MMOBegin, MMOEnd);
14995 // Zero-extend the offset
14996 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14997 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15000 .addImm(X86::sub_32bit);
15002 // Add the offset to the reg_save_area to get the final address.
15003 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15004 .addReg(OffsetReg64)
15005 .addReg(RegSaveReg);
15007 // Compute the offset for the next argument
15008 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15009 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15011 .addImm(UseFPOffset ? 16 : 8);
15013 // Store it back into the va_list.
15014 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15018 .addDisp(Disp, UseFPOffset ? 4 : 0)
15019 .addOperand(Segment)
15020 .addReg(NextOffsetReg)
15021 .setMemRefs(MMOBegin, MMOEnd);
15024 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15029 // Emit code to use overflow area
15032 // Load the overflow_area address into a register.
15033 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15034 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15039 .addOperand(Segment)
15040 .setMemRefs(MMOBegin, MMOEnd);
15042 // If we need to align it, do so. Otherwise, just copy the address
15043 // to OverflowDestReg.
15045 // Align the overflow address
15046 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15047 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15049 // aligned_addr = (addr + (align-1)) & ~(align-1)
15050 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15051 .addReg(OverflowAddrReg)
15054 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15056 .addImm(~(uint64_t)(Align-1));
15058 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15059 .addReg(OverflowAddrReg);
15062 // Compute the next overflow address after this argument.
15063 // (the overflow address should be kept 8-byte aligned)
15064 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15065 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15066 .addReg(OverflowDestReg)
15067 .addImm(ArgSizeA8);
15069 // Store the new overflow address.
15070 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15075 .addOperand(Segment)
15076 .addReg(NextAddrReg)
15077 .setMemRefs(MMOBegin, MMOEnd);
15079 // If we branched, emit the PHI to the front of endMBB.
15081 BuildMI(*endMBB, endMBB->begin(), DL,
15082 TII->get(X86::PHI), DestReg)
15083 .addReg(OffsetDestReg).addMBB(offsetMBB)
15084 .addReg(OverflowDestReg).addMBB(overflowMBB);
15087 // Erase the pseudo instruction
15088 MI->eraseFromParent();
15093 MachineBasicBlock *
15094 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15096 MachineBasicBlock *MBB) const {
15097 // Emit code to save XMM registers to the stack. The ABI says that the
15098 // number of registers to save is given in %al, so it's theoretically
15099 // possible to do an indirect jump trick to avoid saving all of them,
15100 // however this code takes a simpler approach and just executes all
15101 // of the stores if %al is non-zero. It's less code, and it's probably
15102 // easier on the hardware branch predictor, and stores aren't all that
15103 // expensive anyway.
15105 // Create the new basic blocks. One block contains all the XMM stores,
15106 // and one block is the final destination regardless of whether any
15107 // stores were performed.
15108 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15109 MachineFunction *F = MBB->getParent();
15110 MachineFunction::iterator MBBIter = MBB;
15112 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15113 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15114 F->insert(MBBIter, XMMSaveMBB);
15115 F->insert(MBBIter, EndMBB);
15117 // Transfer the remainder of MBB and its successor edges to EndMBB.
15118 EndMBB->splice(EndMBB->begin(), MBB,
15119 llvm::next(MachineBasicBlock::iterator(MI)),
15121 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15123 // The original block will now fall through to the XMM save block.
15124 MBB->addSuccessor(XMMSaveMBB);
15125 // The XMMSaveMBB will fall through to the end block.
15126 XMMSaveMBB->addSuccessor(EndMBB);
15128 // Now add the instructions.
15129 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15130 DebugLoc DL = MI->getDebugLoc();
15132 unsigned CountReg = MI->getOperand(0).getReg();
15133 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15134 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15136 if (!Subtarget->isTargetWin64()) {
15137 // If %al is 0, branch around the XMM save block.
15138 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15139 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15140 MBB->addSuccessor(EndMBB);
15143 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15144 // In the XMM save block, save all the XMM argument registers.
15145 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15146 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15147 MachineMemOperand *MMO =
15148 F->getMachineMemOperand(
15149 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15150 MachineMemOperand::MOStore,
15151 /*Size=*/16, /*Align=*/16);
15152 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15153 .addFrameIndex(RegSaveFrameIndex)
15154 .addImm(/*Scale=*/1)
15155 .addReg(/*IndexReg=*/0)
15156 .addImm(/*Disp=*/Offset)
15157 .addReg(/*Segment=*/0)
15158 .addReg(MI->getOperand(i).getReg())
15159 .addMemOperand(MMO);
15162 MI->eraseFromParent(); // The pseudo instruction is gone now.
15167 // The EFLAGS operand of SelectItr might be missing a kill marker
15168 // because there were multiple uses of EFLAGS, and ISel didn't know
15169 // which to mark. Figure out whether SelectItr should have had a
15170 // kill marker, and set it if it should. Returns the correct kill
15172 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15173 MachineBasicBlock* BB,
15174 const TargetRegisterInfo* TRI) {
15175 // Scan forward through BB for a use/def of EFLAGS.
15176 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15177 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15178 const MachineInstr& mi = *miI;
15179 if (mi.readsRegister(X86::EFLAGS))
15181 if (mi.definesRegister(X86::EFLAGS))
15182 break; // Should have kill-flag - update below.
15185 // If we hit the end of the block, check whether EFLAGS is live into a
15187 if (miI == BB->end()) {
15188 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15189 sEnd = BB->succ_end();
15190 sItr != sEnd; ++sItr) {
15191 MachineBasicBlock* succ = *sItr;
15192 if (succ->isLiveIn(X86::EFLAGS))
15197 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15198 // out. SelectMI should have a kill flag on EFLAGS.
15199 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15203 MachineBasicBlock *
15204 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15205 MachineBasicBlock *BB) const {
15206 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15207 DebugLoc DL = MI->getDebugLoc();
15209 // To "insert" a SELECT_CC instruction, we actually have to insert the
15210 // diamond control-flow pattern. The incoming instruction knows the
15211 // destination vreg to set, the condition code register to branch on, the
15212 // true/false values to select between, and a branch opcode to use.
15213 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15214 MachineFunction::iterator It = BB;
15220 // cmpTY ccX, r1, r2
15222 // fallthrough --> copy0MBB
15223 MachineBasicBlock *thisMBB = BB;
15224 MachineFunction *F = BB->getParent();
15225 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15226 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15227 F->insert(It, copy0MBB);
15228 F->insert(It, sinkMBB);
15230 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15231 // live into the sink and copy blocks.
15232 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15233 if (!MI->killsRegister(X86::EFLAGS) &&
15234 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15235 copy0MBB->addLiveIn(X86::EFLAGS);
15236 sinkMBB->addLiveIn(X86::EFLAGS);
15239 // Transfer the remainder of BB and its successor edges to sinkMBB.
15240 sinkMBB->splice(sinkMBB->begin(), BB,
15241 llvm::next(MachineBasicBlock::iterator(MI)),
15243 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15245 // Add the true and fallthrough blocks as its successors.
15246 BB->addSuccessor(copy0MBB);
15247 BB->addSuccessor(sinkMBB);
15249 // Create the conditional branch instruction.
15251 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15252 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15255 // %FalseValue = ...
15256 // # fallthrough to sinkMBB
15257 copy0MBB->addSuccessor(sinkMBB);
15260 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15262 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15263 TII->get(X86::PHI), MI->getOperand(0).getReg())
15264 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15265 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15267 MI->eraseFromParent(); // The pseudo instruction is gone now.
15271 MachineBasicBlock *
15272 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15273 bool Is64Bit) const {
15274 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15275 DebugLoc DL = MI->getDebugLoc();
15276 MachineFunction *MF = BB->getParent();
15277 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15279 assert(getTargetMachine().Options.EnableSegmentedStacks);
15281 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15282 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15285 // ... [Till the alloca]
15286 // If stacklet is not large enough, jump to mallocMBB
15289 // Allocate by subtracting from RSP
15290 // Jump to continueMBB
15293 // Allocate by call to runtime
15297 // [rest of original BB]
15300 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15301 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15302 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15304 MachineRegisterInfo &MRI = MF->getRegInfo();
15305 const TargetRegisterClass *AddrRegClass =
15306 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15308 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15309 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15310 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15311 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15312 sizeVReg = MI->getOperand(1).getReg(),
15313 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15315 MachineFunction::iterator MBBIter = BB;
15318 MF->insert(MBBIter, bumpMBB);
15319 MF->insert(MBBIter, mallocMBB);
15320 MF->insert(MBBIter, continueMBB);
15322 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15323 (MachineBasicBlock::iterator(MI)), BB->end());
15324 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15326 // Add code to the main basic block to check if the stack limit has been hit,
15327 // and if so, jump to mallocMBB otherwise to bumpMBB.
15328 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15329 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15330 .addReg(tmpSPVReg).addReg(sizeVReg);
15331 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15332 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15333 .addReg(SPLimitVReg);
15334 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15336 // bumpMBB simply decreases the stack pointer, since we know the current
15337 // stacklet has enough space.
15338 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15339 .addReg(SPLimitVReg);
15340 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15341 .addReg(SPLimitVReg);
15342 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15344 // Calls into a routine in libgcc to allocate more space from the heap.
15345 const uint32_t *RegMask =
15346 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15348 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15350 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15351 .addExternalSymbol("__morestack_allocate_stack_space")
15352 .addRegMask(RegMask)
15353 .addReg(X86::RDI, RegState::Implicit)
15354 .addReg(X86::RAX, RegState::ImplicitDefine);
15356 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15358 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15359 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15360 .addExternalSymbol("__morestack_allocate_stack_space")
15361 .addRegMask(RegMask)
15362 .addReg(X86::EAX, RegState::ImplicitDefine);
15366 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15369 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15370 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15371 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15373 // Set up the CFG correctly.
15374 BB->addSuccessor(bumpMBB);
15375 BB->addSuccessor(mallocMBB);
15376 mallocMBB->addSuccessor(continueMBB);
15377 bumpMBB->addSuccessor(continueMBB);
15379 // Take care of the PHI nodes.
15380 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15381 MI->getOperand(0).getReg())
15382 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15383 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15385 // Delete the original pseudo instruction.
15386 MI->eraseFromParent();
15389 return continueMBB;
15392 MachineBasicBlock *
15393 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15394 MachineBasicBlock *BB) const {
15395 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15396 DebugLoc DL = MI->getDebugLoc();
15398 assert(!Subtarget->isTargetEnvMacho());
15400 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15401 // non-trivial part is impdef of ESP.
15403 if (Subtarget->isTargetWin64()) {
15404 if (Subtarget->isTargetCygMing()) {
15405 // ___chkstk(Mingw64):
15406 // Clobbers R10, R11, RAX and EFLAGS.
15408 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15409 .addExternalSymbol("___chkstk")
15410 .addReg(X86::RAX, RegState::Implicit)
15411 .addReg(X86::RSP, RegState::Implicit)
15412 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15413 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15414 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15416 // __chkstk(MSVCRT): does not update stack pointer.
15417 // Clobbers R10, R11 and EFLAGS.
15418 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15419 .addExternalSymbol("__chkstk")
15420 .addReg(X86::RAX, RegState::Implicit)
15421 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15422 // RAX has the offset to be subtracted from RSP.
15423 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15428 const char *StackProbeSymbol =
15429 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15431 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15432 .addExternalSymbol(StackProbeSymbol)
15433 .addReg(X86::EAX, RegState::Implicit)
15434 .addReg(X86::ESP, RegState::Implicit)
15435 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15436 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15437 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15440 MI->eraseFromParent(); // The pseudo instruction is gone now.
15444 MachineBasicBlock *
15445 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15446 MachineBasicBlock *BB) const {
15447 // This is pretty easy. We're taking the value that we received from
15448 // our load from the relocation, sticking it in either RDI (x86-64)
15449 // or EAX and doing an indirect call. The return value will then
15450 // be in the normal return register.
15451 const X86InstrInfo *TII
15452 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15453 DebugLoc DL = MI->getDebugLoc();
15454 MachineFunction *F = BB->getParent();
15456 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15457 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15459 // Get a register mask for the lowered call.
15460 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15461 // proper register mask.
15462 const uint32_t *RegMask =
15463 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15464 if (Subtarget->is64Bit()) {
15465 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15466 TII->get(X86::MOV64rm), X86::RDI)
15468 .addImm(0).addReg(0)
15469 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15470 MI->getOperand(3).getTargetFlags())
15472 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15473 addDirectMem(MIB, X86::RDI);
15474 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15475 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15476 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15477 TII->get(X86::MOV32rm), X86::EAX)
15479 .addImm(0).addReg(0)
15480 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15481 MI->getOperand(3).getTargetFlags())
15483 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15484 addDirectMem(MIB, X86::EAX);
15485 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15487 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15488 TII->get(X86::MOV32rm), X86::EAX)
15489 .addReg(TII->getGlobalBaseReg(F))
15490 .addImm(0).addReg(0)
15491 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15492 MI->getOperand(3).getTargetFlags())
15494 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15495 addDirectMem(MIB, X86::EAX);
15496 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15499 MI->eraseFromParent(); // The pseudo instruction is gone now.
15503 MachineBasicBlock *
15504 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15505 MachineBasicBlock *MBB) const {
15506 DebugLoc DL = MI->getDebugLoc();
15507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15509 MachineFunction *MF = MBB->getParent();
15510 MachineRegisterInfo &MRI = MF->getRegInfo();
15512 const BasicBlock *BB = MBB->getBasicBlock();
15513 MachineFunction::iterator I = MBB;
15516 // Memory Reference
15517 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15518 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15521 unsigned MemOpndSlot = 0;
15523 unsigned CurOp = 0;
15525 DstReg = MI->getOperand(CurOp++).getReg();
15526 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15527 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15528 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15529 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15531 MemOpndSlot = CurOp;
15533 MVT PVT = getPointerTy();
15534 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15535 "Invalid Pointer Size!");
15537 // For v = setjmp(buf), we generate
15540 // buf[LabelOffset] = restoreMBB
15541 // SjLjSetup restoreMBB
15547 // v = phi(main, restore)
15552 MachineBasicBlock *thisMBB = MBB;
15553 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15554 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15555 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15556 MF->insert(I, mainMBB);
15557 MF->insert(I, sinkMBB);
15558 MF->push_back(restoreMBB);
15560 MachineInstrBuilder MIB;
15562 // Transfer the remainder of BB and its successor edges to sinkMBB.
15563 sinkMBB->splice(sinkMBB->begin(), MBB,
15564 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15565 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15568 unsigned PtrStoreOpc = 0;
15569 unsigned LabelReg = 0;
15570 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15571 Reloc::Model RM = getTargetMachine().getRelocationModel();
15572 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15573 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15575 // Prepare IP either in reg or imm.
15576 if (!UseImmLabel) {
15577 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15578 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15579 LabelReg = MRI.createVirtualRegister(PtrRC);
15580 if (Subtarget->is64Bit()) {
15581 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15585 .addMBB(restoreMBB)
15588 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15589 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15590 .addReg(XII->getGlobalBaseReg(MF))
15593 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15597 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15599 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15600 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15601 if (i == X86::AddrDisp)
15602 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15604 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15607 MIB.addReg(LabelReg);
15609 MIB.addMBB(restoreMBB);
15610 MIB.setMemRefs(MMOBegin, MMOEnd);
15612 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15613 .addMBB(restoreMBB);
15615 const X86RegisterInfo *RegInfo =
15616 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15617 MIB.addRegMask(RegInfo->getNoPreservedMask());
15618 thisMBB->addSuccessor(mainMBB);
15619 thisMBB->addSuccessor(restoreMBB);
15623 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15624 mainMBB->addSuccessor(sinkMBB);
15627 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15628 TII->get(X86::PHI), DstReg)
15629 .addReg(mainDstReg).addMBB(mainMBB)
15630 .addReg(restoreDstReg).addMBB(restoreMBB);
15633 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15634 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15635 restoreMBB->addSuccessor(sinkMBB);
15637 MI->eraseFromParent();
15641 MachineBasicBlock *
15642 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15643 MachineBasicBlock *MBB) const {
15644 DebugLoc DL = MI->getDebugLoc();
15645 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15647 MachineFunction *MF = MBB->getParent();
15648 MachineRegisterInfo &MRI = MF->getRegInfo();
15650 // Memory Reference
15651 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15652 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15654 MVT PVT = getPointerTy();
15655 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15656 "Invalid Pointer Size!");
15658 const TargetRegisterClass *RC =
15659 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15660 unsigned Tmp = MRI.createVirtualRegister(RC);
15661 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15662 const X86RegisterInfo *RegInfo =
15663 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15664 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15665 unsigned SP = RegInfo->getStackRegister();
15667 MachineInstrBuilder MIB;
15669 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15670 const int64_t SPOffset = 2 * PVT.getStoreSize();
15672 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15673 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15676 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15677 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15678 MIB.addOperand(MI->getOperand(i));
15679 MIB.setMemRefs(MMOBegin, MMOEnd);
15681 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15682 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15683 if (i == X86::AddrDisp)
15684 MIB.addDisp(MI->getOperand(i), LabelOffset);
15686 MIB.addOperand(MI->getOperand(i));
15688 MIB.setMemRefs(MMOBegin, MMOEnd);
15690 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15691 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15692 if (i == X86::AddrDisp)
15693 MIB.addDisp(MI->getOperand(i), SPOffset);
15695 MIB.addOperand(MI->getOperand(i));
15697 MIB.setMemRefs(MMOBegin, MMOEnd);
15699 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15701 MI->eraseFromParent();
15705 MachineBasicBlock *
15706 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15707 MachineBasicBlock *BB) const {
15708 switch (MI->getOpcode()) {
15709 default: llvm_unreachable("Unexpected instr type to insert");
15710 case X86::TAILJMPd64:
15711 case X86::TAILJMPr64:
15712 case X86::TAILJMPm64:
15713 llvm_unreachable("TAILJMP64 would not be touched here.");
15714 case X86::TCRETURNdi64:
15715 case X86::TCRETURNri64:
15716 case X86::TCRETURNmi64:
15718 case X86::WIN_ALLOCA:
15719 return EmitLoweredWinAlloca(MI, BB);
15720 case X86::SEG_ALLOCA_32:
15721 return EmitLoweredSegAlloca(MI, BB, false);
15722 case X86::SEG_ALLOCA_64:
15723 return EmitLoweredSegAlloca(MI, BB, true);
15724 case X86::TLSCall_32:
15725 case X86::TLSCall_64:
15726 return EmitLoweredTLSCall(MI, BB);
15727 case X86::CMOV_GR8:
15728 case X86::CMOV_FR32:
15729 case X86::CMOV_FR64:
15730 case X86::CMOV_V4F32:
15731 case X86::CMOV_V2F64:
15732 case X86::CMOV_V2I64:
15733 case X86::CMOV_V8F32:
15734 case X86::CMOV_V4F64:
15735 case X86::CMOV_V4I64:
15736 case X86::CMOV_GR16:
15737 case X86::CMOV_GR32:
15738 case X86::CMOV_RFP32:
15739 case X86::CMOV_RFP64:
15740 case X86::CMOV_RFP80:
15741 return EmitLoweredSelect(MI, BB);
15743 case X86::FP32_TO_INT16_IN_MEM:
15744 case X86::FP32_TO_INT32_IN_MEM:
15745 case X86::FP32_TO_INT64_IN_MEM:
15746 case X86::FP64_TO_INT16_IN_MEM:
15747 case X86::FP64_TO_INT32_IN_MEM:
15748 case X86::FP64_TO_INT64_IN_MEM:
15749 case X86::FP80_TO_INT16_IN_MEM:
15750 case X86::FP80_TO_INT32_IN_MEM:
15751 case X86::FP80_TO_INT64_IN_MEM: {
15752 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15753 DebugLoc DL = MI->getDebugLoc();
15755 // Change the floating point control register to use "round towards zero"
15756 // mode when truncating to an integer value.
15757 MachineFunction *F = BB->getParent();
15758 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15759 addFrameReference(BuildMI(*BB, MI, DL,
15760 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15762 // Load the old value of the high byte of the control word...
15764 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15765 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15768 // Set the high part to be round to zero...
15769 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15772 // Reload the modified control word now...
15773 addFrameReference(BuildMI(*BB, MI, DL,
15774 TII->get(X86::FLDCW16m)), CWFrameIdx);
15776 // Restore the memory image of control word to original value
15777 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15780 // Get the X86 opcode to use.
15782 switch (MI->getOpcode()) {
15783 default: llvm_unreachable("illegal opcode!");
15784 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15785 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15786 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15787 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15788 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15789 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15790 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15791 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15792 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15796 MachineOperand &Op = MI->getOperand(0);
15798 AM.BaseType = X86AddressMode::RegBase;
15799 AM.Base.Reg = Op.getReg();
15801 AM.BaseType = X86AddressMode::FrameIndexBase;
15802 AM.Base.FrameIndex = Op.getIndex();
15804 Op = MI->getOperand(1);
15806 AM.Scale = Op.getImm();
15807 Op = MI->getOperand(2);
15809 AM.IndexReg = Op.getImm();
15810 Op = MI->getOperand(3);
15811 if (Op.isGlobal()) {
15812 AM.GV = Op.getGlobal();
15814 AM.Disp = Op.getImm();
15816 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15817 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15819 // Reload the original control word now.
15820 addFrameReference(BuildMI(*BB, MI, DL,
15821 TII->get(X86::FLDCW16m)), CWFrameIdx);
15823 MI->eraseFromParent(); // The pseudo instruction is gone now.
15826 // String/text processing lowering.
15827 case X86::PCMPISTRM128REG:
15828 case X86::VPCMPISTRM128REG:
15829 case X86::PCMPISTRM128MEM:
15830 case X86::VPCMPISTRM128MEM:
15831 case X86::PCMPESTRM128REG:
15832 case X86::VPCMPESTRM128REG:
15833 case X86::PCMPESTRM128MEM:
15834 case X86::VPCMPESTRM128MEM:
15835 assert(Subtarget->hasSSE42() &&
15836 "Target must have SSE4.2 or AVX features enabled");
15837 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15839 // String/text processing lowering.
15840 case X86::PCMPISTRIREG:
15841 case X86::VPCMPISTRIREG:
15842 case X86::PCMPISTRIMEM:
15843 case X86::VPCMPISTRIMEM:
15844 case X86::PCMPESTRIREG:
15845 case X86::VPCMPESTRIREG:
15846 case X86::PCMPESTRIMEM:
15847 case X86::VPCMPESTRIMEM:
15848 assert(Subtarget->hasSSE42() &&
15849 "Target must have SSE4.2 or AVX features enabled");
15850 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15852 // Thread synchronization.
15854 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15858 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15860 // Atomic Lowering.
15861 case X86::ATOMAND8:
15862 case X86::ATOMAND16:
15863 case X86::ATOMAND32:
15864 case X86::ATOMAND64:
15867 case X86::ATOMOR16:
15868 case X86::ATOMOR32:
15869 case X86::ATOMOR64:
15871 case X86::ATOMXOR16:
15872 case X86::ATOMXOR8:
15873 case X86::ATOMXOR32:
15874 case X86::ATOMXOR64:
15876 case X86::ATOMNAND8:
15877 case X86::ATOMNAND16:
15878 case X86::ATOMNAND32:
15879 case X86::ATOMNAND64:
15881 case X86::ATOMMAX8:
15882 case X86::ATOMMAX16:
15883 case X86::ATOMMAX32:
15884 case X86::ATOMMAX64:
15886 case X86::ATOMMIN8:
15887 case X86::ATOMMIN16:
15888 case X86::ATOMMIN32:
15889 case X86::ATOMMIN64:
15891 case X86::ATOMUMAX8:
15892 case X86::ATOMUMAX16:
15893 case X86::ATOMUMAX32:
15894 case X86::ATOMUMAX64:
15896 case X86::ATOMUMIN8:
15897 case X86::ATOMUMIN16:
15898 case X86::ATOMUMIN32:
15899 case X86::ATOMUMIN64:
15900 return EmitAtomicLoadArith(MI, BB);
15902 // This group does 64-bit operations on a 32-bit host.
15903 case X86::ATOMAND6432:
15904 case X86::ATOMOR6432:
15905 case X86::ATOMXOR6432:
15906 case X86::ATOMNAND6432:
15907 case X86::ATOMADD6432:
15908 case X86::ATOMSUB6432:
15909 case X86::ATOMMAX6432:
15910 case X86::ATOMMIN6432:
15911 case X86::ATOMUMAX6432:
15912 case X86::ATOMUMIN6432:
15913 case X86::ATOMSWAP6432:
15914 return EmitAtomicLoadArith6432(MI, BB);
15916 case X86::VASTART_SAVE_XMM_REGS:
15917 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15919 case X86::VAARG_64:
15920 return EmitVAARG64WithCustomInserter(MI, BB);
15922 case X86::EH_SjLj_SetJmp32:
15923 case X86::EH_SjLj_SetJmp64:
15924 return emitEHSjLjSetJmp(MI, BB);
15926 case X86::EH_SjLj_LongJmp32:
15927 case X86::EH_SjLj_LongJmp64:
15928 return emitEHSjLjLongJmp(MI, BB);
15932 //===----------------------------------------------------------------------===//
15933 // X86 Optimization Hooks
15934 //===----------------------------------------------------------------------===//
15936 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15939 const SelectionDAG &DAG,
15940 unsigned Depth) const {
15941 unsigned BitWidth = KnownZero.getBitWidth();
15942 unsigned Opc = Op.getOpcode();
15943 assert((Opc >= ISD::BUILTIN_OP_END ||
15944 Opc == ISD::INTRINSIC_WO_CHAIN ||
15945 Opc == ISD::INTRINSIC_W_CHAIN ||
15946 Opc == ISD::INTRINSIC_VOID) &&
15947 "Should use MaskedValueIsZero if you don't know whether Op"
15948 " is a target node!");
15950 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15964 // These nodes' second result is a boolean.
15965 if (Op.getResNo() == 0)
15968 case X86ISD::SETCC:
15969 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15971 case ISD::INTRINSIC_WO_CHAIN: {
15972 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15973 unsigned NumLoBits = 0;
15976 case Intrinsic::x86_sse_movmsk_ps:
15977 case Intrinsic::x86_avx_movmsk_ps_256:
15978 case Intrinsic::x86_sse2_movmsk_pd:
15979 case Intrinsic::x86_avx_movmsk_pd_256:
15980 case Intrinsic::x86_mmx_pmovmskb:
15981 case Intrinsic::x86_sse2_pmovmskb_128:
15982 case Intrinsic::x86_avx2_pmovmskb: {
15983 // High bits of movmskp{s|d}, pmovmskb are known zero.
15985 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15986 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15987 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15988 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15989 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15990 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15991 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15992 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15994 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16003 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16004 unsigned Depth) const {
16005 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16006 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16007 return Op.getValueType().getScalarType().getSizeInBits();
16013 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16014 /// node is a GlobalAddress + offset.
16015 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16016 const GlobalValue* &GA,
16017 int64_t &Offset) const {
16018 if (N->getOpcode() == X86ISD::Wrapper) {
16019 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16020 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16021 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16025 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16028 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16029 /// same as extracting the high 128-bit part of 256-bit vector and then
16030 /// inserting the result into the low part of a new 256-bit vector
16031 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16032 EVT VT = SVOp->getValueType(0);
16033 unsigned NumElems = VT.getVectorNumElements();
16035 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16036 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16037 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16038 SVOp->getMaskElt(j) >= 0)
16044 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16045 /// same as extracting the low 128-bit part of 256-bit vector and then
16046 /// inserting the result into the high part of a new 256-bit vector
16047 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16048 EVT VT = SVOp->getValueType(0);
16049 unsigned NumElems = VT.getVectorNumElements();
16051 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16052 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16053 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16054 SVOp->getMaskElt(j) >= 0)
16060 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16061 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16062 TargetLowering::DAGCombinerInfo &DCI,
16063 const X86Subtarget* Subtarget) {
16065 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16066 SDValue V1 = SVOp->getOperand(0);
16067 SDValue V2 = SVOp->getOperand(1);
16068 EVT VT = SVOp->getValueType(0);
16069 unsigned NumElems = VT.getVectorNumElements();
16071 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16072 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16076 // V UNDEF BUILD_VECTOR UNDEF
16078 // CONCAT_VECTOR CONCAT_VECTOR
16081 // RESULT: V + zero extended
16083 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16084 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16085 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16088 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16091 // To match the shuffle mask, the first half of the mask should
16092 // be exactly the first vector, and all the rest a splat with the
16093 // first element of the second one.
16094 for (unsigned i = 0; i != NumElems/2; ++i)
16095 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16096 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16099 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16100 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16101 if (Ld->hasNUsesOfValue(1, 0)) {
16102 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16103 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16105 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16106 array_lengthof(Ops),
16108 Ld->getPointerInfo(),
16109 Ld->getAlignment(),
16110 false/*isVolatile*/, true/*ReadMem*/,
16111 false/*WriteMem*/);
16113 // Make sure the newly-created LOAD is in the same position as Ld in
16114 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16115 // and update uses of Ld's output chain to use the TokenFactor.
16116 if (Ld->hasAnyUseOfValue(1)) {
16117 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16118 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16119 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16120 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16121 SDValue(ResNode.getNode(), 1));
16124 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16128 // Emit a zeroed vector and insert the desired subvector on its
16130 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16131 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16132 return DCI.CombineTo(N, InsV);
16135 //===--------------------------------------------------------------------===//
16136 // Combine some shuffles into subvector extracts and inserts:
16139 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16140 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16141 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16142 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16143 return DCI.CombineTo(N, InsV);
16146 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16147 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16148 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16149 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16150 return DCI.CombineTo(N, InsV);
16156 static SDValue PerformConcatCombine(SDNode *N, SelectionDAG &DAG,
16157 TargetLowering::DAGCombinerInfo &DCI,
16158 const X86Subtarget *Subtarget) {
16159 // Creating a v8i16 from a v4i16 argument and an undef runs into trouble in
16160 // type legalization and ends up spilling to the stack. Avoid that by
16161 // creating a vector first and bitcasting the result rather than
16162 // bitcasting the source then creating the vector. Similar problems with
16165 // No point in doing this after legalize, so early exit for that.
16166 if (!DCI.isBeforeLegalize())
16169 EVT VT = N->getValueType(0);
16170 SDValue Op0 = N->getOperand(0);
16171 SDValue Op1 = N->getOperand(1);
16172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16173 if (VT.getSizeInBits() == 128 && N->getNumOperands() == 2 &&
16174 Op1->getOpcode() == ISD::UNDEF &&
16175 Op0->getOpcode() == ISD::BITCAST &&
16176 !TLI.isTypeLegal(Op0->getValueType(0)) &&
16177 TLI.isTypeLegal(Op0->getOperand(0)->getValueType(0))) {
16178 if (Op0->getOperand(0)->getValueType(0).isVector())
16180 SDValue Scalar = Op0->getOperand(0);
16181 // Any legal type here will be a simple value type.
16182 MVT SVT = Scalar->getValueType(0).getSimpleVT();
16183 // As a special case, bail out on MMX values.
16184 if (SVT == MVT::x86mmx)
16186 EVT NVT = MVT::getVectorVT(SVT, 2);
16187 // If the result vector type isn't legal, this transform won't really
16188 // help, so bail on that, too.
16189 if (!TLI.isTypeLegal(NVT))
16191 SDLoc dl = SDLoc(N);
16192 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
16193 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);
16200 /// PerformShuffleCombine - Performs several different shuffle combines.
16201 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16202 TargetLowering::DAGCombinerInfo &DCI,
16203 const X86Subtarget *Subtarget) {
16205 EVT VT = N->getValueType(0);
16207 // Don't create instructions with illegal types after legalize types has run.
16208 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16209 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16212 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16213 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16214 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16215 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16217 // Only handle 128 wide vector from here on.
16218 if (!VT.is128BitVector())
16221 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16222 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16223 // consecutive, non-overlapping, and in the right order.
16224 SmallVector<SDValue, 16> Elts;
16225 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16226 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16228 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16231 /// PerformTruncateCombine - Converts truncate operation to
16232 /// a sequence of vector shuffle operations.
16233 /// It is possible when we truncate 256-bit vector to 128-bit vector
16234 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16235 TargetLowering::DAGCombinerInfo &DCI,
16236 const X86Subtarget *Subtarget) {
16240 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16241 /// specific shuffle of a load can be folded into a single element load.
16242 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16243 /// shuffles have been customed lowered so we need to handle those here.
16244 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16245 TargetLowering::DAGCombinerInfo &DCI) {
16246 if (DCI.isBeforeLegalizeOps())
16249 SDValue InVec = N->getOperand(0);
16250 SDValue EltNo = N->getOperand(1);
16252 if (!isa<ConstantSDNode>(EltNo))
16255 EVT VT = InVec.getValueType();
16257 bool HasShuffleIntoBitcast = false;
16258 if (InVec.getOpcode() == ISD::BITCAST) {
16259 // Don't duplicate a load with other uses.
16260 if (!InVec.hasOneUse())
16262 EVT BCVT = InVec.getOperand(0).getValueType();
16263 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16265 InVec = InVec.getOperand(0);
16266 HasShuffleIntoBitcast = true;
16269 if (!isTargetShuffle(InVec.getOpcode()))
16272 // Don't duplicate a load with other uses.
16273 if (!InVec.hasOneUse())
16276 SmallVector<int, 16> ShuffleMask;
16278 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16282 // Select the input vector, guarding against out of range extract vector.
16283 unsigned NumElems = VT.getVectorNumElements();
16284 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16285 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16286 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16287 : InVec.getOperand(1);
16289 // If inputs to shuffle are the same for both ops, then allow 2 uses
16290 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16292 if (LdNode.getOpcode() == ISD::BITCAST) {
16293 // Don't duplicate a load with other uses.
16294 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16297 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16298 LdNode = LdNode.getOperand(0);
16301 if (!ISD::isNormalLoad(LdNode.getNode()))
16304 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16306 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16309 if (HasShuffleIntoBitcast) {
16310 // If there's a bitcast before the shuffle, check if the load type and
16311 // alignment is valid.
16312 unsigned Align = LN0->getAlignment();
16313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16314 unsigned NewAlign = TLI.getDataLayout()->
16315 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16317 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16321 // All checks match so transform back to vector_shuffle so that DAG combiner
16322 // can finish the job
16325 // Create shuffle node taking into account the case that its a unary shuffle
16326 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16327 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16328 InVec.getOperand(0), Shuffle,
16330 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16331 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16335 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16336 /// generation and convert it from being a bunch of shuffles and extracts
16337 /// to a simple store and scalar loads to extract the elements.
16338 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16339 TargetLowering::DAGCombinerInfo &DCI) {
16340 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16341 if (NewOp.getNode())
16344 SDValue InputVector = N->getOperand(0);
16345 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16346 // from mmx to v2i32 has a single usage.
16347 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16348 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16349 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16350 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16351 N->getValueType(0),
16352 InputVector.getNode()->getOperand(0));
16354 // Only operate on vectors of 4 elements, where the alternative shuffling
16355 // gets to be more expensive.
16356 if (InputVector.getValueType() != MVT::v4i32)
16359 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16360 // single use which is a sign-extend or zero-extend, and all elements are
16362 SmallVector<SDNode *, 4> Uses;
16363 unsigned ExtractedElements = 0;
16364 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16365 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16366 if (UI.getUse().getResNo() != InputVector.getResNo())
16369 SDNode *Extract = *UI;
16370 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16373 if (Extract->getValueType(0) != MVT::i32)
16375 if (!Extract->hasOneUse())
16377 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16378 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16380 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16383 // Record which element was extracted.
16384 ExtractedElements |=
16385 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16387 Uses.push_back(Extract);
16390 // If not all the elements were used, this may not be worthwhile.
16391 if (ExtractedElements != 15)
16394 // Ok, we've now decided to do the transformation.
16395 SDLoc dl(InputVector);
16397 // Store the value to a temporary stack slot.
16398 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16399 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16400 MachinePointerInfo(), false, false, 0);
16402 // Replace each use (extract) with a load of the appropriate element.
16403 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16404 UE = Uses.end(); UI != UE; ++UI) {
16405 SDNode *Extract = *UI;
16407 // cOMpute the element's address.
16408 SDValue Idx = Extract->getOperand(1);
16410 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16411 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16413 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16415 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16416 StackPtr, OffsetVal);
16418 // Load the scalar.
16419 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16420 ScalarAddr, MachinePointerInfo(),
16421 false, false, false, 0);
16423 // Replace the exact with the load.
16424 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16427 // The replacement was made in place; don't return anything.
16431 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16432 static std::pair<unsigned, bool>
16433 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16434 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16435 if (!VT.isVector())
16436 return std::make_pair(0, false);
16438 bool NeedSplit = false;
16439 switch (VT.getSimpleVT().SimpleTy) {
16440 default: return std::make_pair(0, false);
16444 if (!Subtarget->hasAVX2())
16446 if (!Subtarget->hasAVX())
16447 return std::make_pair(0, false);
16452 if (!Subtarget->hasSSE2())
16453 return std::make_pair(0, false);
16456 // SSE2 has only a small subset of the operations.
16457 bool hasUnsigned = Subtarget->hasSSE41() ||
16458 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16459 bool hasSigned = Subtarget->hasSSE41() ||
16460 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16462 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16465 // Check for x CC y ? x : y.
16466 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16467 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16472 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16475 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16478 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16481 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16483 // Check for x CC y ? y : x -- a min/max with reversed arms.
16484 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16485 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16490 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16493 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16496 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16499 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16503 return std::make_pair(Opc, NeedSplit);
16506 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16508 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16509 TargetLowering::DAGCombinerInfo &DCI,
16510 const X86Subtarget *Subtarget) {
16512 SDValue Cond = N->getOperand(0);
16513 // Get the LHS/RHS of the select.
16514 SDValue LHS = N->getOperand(1);
16515 SDValue RHS = N->getOperand(2);
16516 EVT VT = LHS.getValueType();
16517 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16519 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16520 // instructions match the semantics of the common C idiom x<y?x:y but not
16521 // x<=y?x:y, because of how they handle negative zero (which can be
16522 // ignored in unsafe-math mode).
16523 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16524 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16525 (Subtarget->hasSSE2() ||
16526 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16527 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16529 unsigned Opcode = 0;
16530 // Check for x CC y ? x : y.
16531 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16532 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16536 // Converting this to a min would handle NaNs incorrectly, and swapping
16537 // the operands would cause it to handle comparisons between positive
16538 // and negative zero incorrectly.
16539 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16540 if (!DAG.getTarget().Options.UnsafeFPMath &&
16541 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16543 std::swap(LHS, RHS);
16545 Opcode = X86ISD::FMIN;
16548 // Converting this to a min would handle comparisons between positive
16549 // and negative zero incorrectly.
16550 if (!DAG.getTarget().Options.UnsafeFPMath &&
16551 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16553 Opcode = X86ISD::FMIN;
16556 // Converting this to a min would handle both negative zeros and NaNs
16557 // incorrectly, but we can swap the operands to fix both.
16558 std::swap(LHS, RHS);
16562 Opcode = X86ISD::FMIN;
16566 // Converting this to a max would handle comparisons between positive
16567 // and negative zero incorrectly.
16568 if (!DAG.getTarget().Options.UnsafeFPMath &&
16569 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16571 Opcode = X86ISD::FMAX;
16574 // Converting this to a max would handle NaNs incorrectly, and swapping
16575 // the operands would cause it to handle comparisons between positive
16576 // and negative zero incorrectly.
16577 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16578 if (!DAG.getTarget().Options.UnsafeFPMath &&
16579 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16581 std::swap(LHS, RHS);
16583 Opcode = X86ISD::FMAX;
16586 // Converting this to a max would handle both negative zeros and NaNs
16587 // incorrectly, but we can swap the operands to fix both.
16588 std::swap(LHS, RHS);
16592 Opcode = X86ISD::FMAX;
16595 // Check for x CC y ? y : x -- a min/max with reversed arms.
16596 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16597 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16601 // Converting this to a min would handle comparisons between positive
16602 // and negative zero incorrectly, and swapping the operands would
16603 // cause it to handle NaNs incorrectly.
16604 if (!DAG.getTarget().Options.UnsafeFPMath &&
16605 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16606 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16608 std::swap(LHS, RHS);
16610 Opcode = X86ISD::FMIN;
16613 // Converting this to a min would handle NaNs incorrectly.
16614 if (!DAG.getTarget().Options.UnsafeFPMath &&
16615 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16617 Opcode = X86ISD::FMIN;
16620 // Converting this to a min would handle both negative zeros and NaNs
16621 // incorrectly, but we can swap the operands to fix both.
16622 std::swap(LHS, RHS);
16626 Opcode = X86ISD::FMIN;
16630 // Converting this to a max would handle NaNs incorrectly.
16631 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16633 Opcode = X86ISD::FMAX;
16636 // Converting this to a max would handle comparisons between positive
16637 // and negative zero incorrectly, and swapping the operands would
16638 // cause it to handle NaNs incorrectly.
16639 if (!DAG.getTarget().Options.UnsafeFPMath &&
16640 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16641 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16643 std::swap(LHS, RHS);
16645 Opcode = X86ISD::FMAX;
16648 // Converting this to a max would handle both negative zeros and NaNs
16649 // incorrectly, but we can swap the operands to fix both.
16650 std::swap(LHS, RHS);
16654 Opcode = X86ISD::FMAX;
16660 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16663 if (Subtarget->hasAVX512() && VT.isVector() &&
16664 Cond.getValueType().getVectorElementType() == MVT::i1) {
16665 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16666 // lowering on AVX-512. In this case we convert it to
16667 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16668 // The same situation for all 128 and 256-bit vectors of i8 and i16
16669 EVT OpVT = LHS.getValueType();
16670 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16671 (OpVT.getVectorElementType() == MVT::i8 ||
16672 OpVT.getVectorElementType() == MVT::i16)) {
16673 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16674 DCI.AddToWorklist(Cond.getNode());
16675 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16678 // If this is a select between two integer constants, try to do some
16680 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16681 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16682 // Don't do this for crazy integer types.
16683 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16684 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16685 // so that TrueC (the true value) is larger than FalseC.
16686 bool NeedsCondInvert = false;
16688 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16689 // Efficiently invertible.
16690 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16691 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16692 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16693 NeedsCondInvert = true;
16694 std::swap(TrueC, FalseC);
16697 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16698 if (FalseC->getAPIntValue() == 0 &&
16699 TrueC->getAPIntValue().isPowerOf2()) {
16700 if (NeedsCondInvert) // Invert the condition if needed.
16701 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16702 DAG.getConstant(1, Cond.getValueType()));
16704 // Zero extend the condition if needed.
16705 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16707 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16708 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16709 DAG.getConstant(ShAmt, MVT::i8));
16712 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16713 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16714 if (NeedsCondInvert) // Invert the condition if needed.
16715 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16716 DAG.getConstant(1, Cond.getValueType()));
16718 // Zero extend the condition if needed.
16719 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16720 FalseC->getValueType(0), Cond);
16721 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16722 SDValue(FalseC, 0));
16725 // Optimize cases that will turn into an LEA instruction. This requires
16726 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16727 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16728 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16729 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16731 bool isFastMultiplier = false;
16733 switch ((unsigned char)Diff) {
16735 case 1: // result = add base, cond
16736 case 2: // result = lea base( , cond*2)
16737 case 3: // result = lea base(cond, cond*2)
16738 case 4: // result = lea base( , cond*4)
16739 case 5: // result = lea base(cond, cond*4)
16740 case 8: // result = lea base( , cond*8)
16741 case 9: // result = lea base(cond, cond*8)
16742 isFastMultiplier = true;
16747 if (isFastMultiplier) {
16748 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16749 if (NeedsCondInvert) // Invert the condition if needed.
16750 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16751 DAG.getConstant(1, Cond.getValueType()));
16753 // Zero extend the condition if needed.
16754 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16756 // Scale the condition by the difference.
16758 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16759 DAG.getConstant(Diff, Cond.getValueType()));
16761 // Add the base if non-zero.
16762 if (FalseC->getAPIntValue() != 0)
16763 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16764 SDValue(FalseC, 0));
16771 // Canonicalize max and min:
16772 // (x > y) ? x : y -> (x >= y) ? x : y
16773 // (x < y) ? x : y -> (x <= y) ? x : y
16774 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16775 // the need for an extra compare
16776 // against zero. e.g.
16777 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16779 // testl %edi, %edi
16781 // cmovgl %edi, %eax
16785 // cmovsl %eax, %edi
16786 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16787 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16788 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16789 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16794 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16795 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16796 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16797 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16802 // Early exit check
16803 if (!TLI.isTypeLegal(VT))
16806 // Match VSELECTs into subs with unsigned saturation.
16807 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16808 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16809 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16810 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16811 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16813 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16814 // left side invert the predicate to simplify logic below.
16816 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16818 CC = ISD::getSetCCInverse(CC, true);
16819 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16823 if (Other.getNode() && Other->getNumOperands() == 2 &&
16824 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16825 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16826 SDValue CondRHS = Cond->getOperand(1);
16828 // Look for a general sub with unsigned saturation first.
16829 // x >= y ? x-y : 0 --> subus x, y
16830 // x > y ? x-y : 0 --> subus x, y
16831 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16832 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16833 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16835 // If the RHS is a constant we have to reverse the const canonicalization.
16836 // x > C-1 ? x+-C : 0 --> subus x, C
16837 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16838 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16839 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16840 if (CondRHS.getConstantOperandVal(0) == -A-1)
16841 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16842 DAG.getConstant(-A, VT));
16845 // Another special case: If C was a sign bit, the sub has been
16846 // canonicalized into a xor.
16847 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16848 // it's safe to decanonicalize the xor?
16849 // x s< 0 ? x^C : 0 --> subus x, C
16850 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16851 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16852 isSplatVector(OpRHS.getNode())) {
16853 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16855 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16860 // Try to match a min/max vector operation.
16861 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16862 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16863 unsigned Opc = ret.first;
16864 bool NeedSplit = ret.second;
16866 if (Opc && NeedSplit) {
16867 unsigned NumElems = VT.getVectorNumElements();
16868 // Extract the LHS vectors
16869 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16870 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16872 // Extract the RHS vectors
16873 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16874 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16876 // Create min/max for each subvector
16877 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16878 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16880 // Merge the result
16881 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16883 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16886 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16887 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16888 // Check if SETCC has already been promoted
16889 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16891 assert(Cond.getValueType().isVector() &&
16892 "vector select expects a vector selector!");
16894 EVT IntVT = Cond.getValueType();
16895 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16896 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16898 if (!TValIsAllOnes && !FValIsAllZeros) {
16899 // Try invert the condition if true value is not all 1s and false value
16901 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16902 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16904 if (TValIsAllZeros || FValIsAllOnes) {
16905 SDValue CC = Cond.getOperand(2);
16906 ISD::CondCode NewCC =
16907 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16908 Cond.getOperand(0).getValueType().isInteger());
16909 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16910 std::swap(LHS, RHS);
16911 TValIsAllOnes = FValIsAllOnes;
16912 FValIsAllZeros = TValIsAllZeros;
16916 if (TValIsAllOnes || FValIsAllZeros) {
16919 if (TValIsAllOnes && FValIsAllZeros)
16921 else if (TValIsAllOnes)
16922 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16923 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16924 else if (FValIsAllZeros)
16925 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16926 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16928 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16932 // If we know that this node is legal then we know that it is going to be
16933 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16934 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16935 // to simplify previous instructions.
16936 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16937 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16938 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16940 // Don't optimize vector selects that map to mask-registers.
16944 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16945 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16947 APInt KnownZero, KnownOne;
16948 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16949 DCI.isBeforeLegalizeOps());
16950 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16951 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16952 DCI.CommitTargetLoweringOpt(TLO);
16958 // Check whether a boolean test is testing a boolean value generated by
16959 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16962 // Simplify the following patterns:
16963 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16964 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16965 // to (Op EFLAGS Cond)
16967 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16968 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16969 // to (Op EFLAGS !Cond)
16971 // where Op could be BRCOND or CMOV.
16973 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16974 // Quit if not CMP and SUB with its value result used.
16975 if (Cmp.getOpcode() != X86ISD::CMP &&
16976 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16979 // Quit if not used as a boolean value.
16980 if (CC != X86::COND_E && CC != X86::COND_NE)
16983 // Check CMP operands. One of them should be 0 or 1 and the other should be
16984 // an SetCC or extended from it.
16985 SDValue Op1 = Cmp.getOperand(0);
16986 SDValue Op2 = Cmp.getOperand(1);
16989 const ConstantSDNode* C = 0;
16990 bool needOppositeCond = (CC == X86::COND_E);
16991 bool checkAgainstTrue = false; // Is it a comparison against 1?
16993 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16995 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16997 else // Quit if all operands are not constants.
17000 if (C->getZExtValue() == 1) {
17001 needOppositeCond = !needOppositeCond;
17002 checkAgainstTrue = true;
17003 } else if (C->getZExtValue() != 0)
17004 // Quit if the constant is neither 0 or 1.
17007 bool truncatedToBoolWithAnd = false;
17008 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17009 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17010 SetCC.getOpcode() == ISD::TRUNCATE ||
17011 SetCC.getOpcode() == ISD::AND) {
17012 if (SetCC.getOpcode() == ISD::AND) {
17014 ConstantSDNode *CS;
17015 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17016 CS->getZExtValue() == 1)
17018 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17019 CS->getZExtValue() == 1)
17023 SetCC = SetCC.getOperand(OpIdx);
17024 truncatedToBoolWithAnd = true;
17026 SetCC = SetCC.getOperand(0);
17029 switch (SetCC.getOpcode()) {
17030 case X86ISD::SETCC_CARRY:
17031 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17032 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17033 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17034 // truncated to i1 using 'and'.
17035 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17037 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17038 "Invalid use of SETCC_CARRY!");
17040 case X86ISD::SETCC:
17041 // Set the condition code or opposite one if necessary.
17042 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17043 if (needOppositeCond)
17044 CC = X86::GetOppositeBranchCondition(CC);
17045 return SetCC.getOperand(1);
17046 case X86ISD::CMOV: {
17047 // Check whether false/true value has canonical one, i.e. 0 or 1.
17048 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17049 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17050 // Quit if true value is not a constant.
17053 // Quit if false value is not a constant.
17055 SDValue Op = SetCC.getOperand(0);
17056 // Skip 'zext' or 'trunc' node.
17057 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17058 Op.getOpcode() == ISD::TRUNCATE)
17059 Op = Op.getOperand(0);
17060 // A special case for rdrand/rdseed, where 0 is set if false cond is
17062 if ((Op.getOpcode() != X86ISD::RDRAND &&
17063 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17066 // Quit if false value is not the constant 0 or 1.
17067 bool FValIsFalse = true;
17068 if (FVal && FVal->getZExtValue() != 0) {
17069 if (FVal->getZExtValue() != 1)
17071 // If FVal is 1, opposite cond is needed.
17072 needOppositeCond = !needOppositeCond;
17073 FValIsFalse = false;
17075 // Quit if TVal is not the constant opposite of FVal.
17076 if (FValIsFalse && TVal->getZExtValue() != 1)
17078 if (!FValIsFalse && TVal->getZExtValue() != 0)
17080 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17081 if (needOppositeCond)
17082 CC = X86::GetOppositeBranchCondition(CC);
17083 return SetCC.getOperand(3);
17090 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17091 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17092 TargetLowering::DAGCombinerInfo &DCI,
17093 const X86Subtarget *Subtarget) {
17096 // If the flag operand isn't dead, don't touch this CMOV.
17097 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17100 SDValue FalseOp = N->getOperand(0);
17101 SDValue TrueOp = N->getOperand(1);
17102 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17103 SDValue Cond = N->getOperand(3);
17105 if (CC == X86::COND_E || CC == X86::COND_NE) {
17106 switch (Cond.getOpcode()) {
17110 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17111 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17112 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17118 Flags = checkBoolTestSetCCCombine(Cond, CC);
17119 if (Flags.getNode() &&
17120 // Extra check as FCMOV only supports a subset of X86 cond.
17121 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17122 SDValue Ops[] = { FalseOp, TrueOp,
17123 DAG.getConstant(CC, MVT::i8), Flags };
17124 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17125 Ops, array_lengthof(Ops));
17128 // If this is a select between two integer constants, try to do some
17129 // optimizations. Note that the operands are ordered the opposite of SELECT
17131 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17132 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17133 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17134 // larger than FalseC (the false value).
17135 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17136 CC = X86::GetOppositeBranchCondition(CC);
17137 std::swap(TrueC, FalseC);
17138 std::swap(TrueOp, FalseOp);
17141 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17142 // This is efficient for any integer data type (including i8/i16) and
17144 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17145 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17146 DAG.getConstant(CC, MVT::i8), Cond);
17148 // Zero extend the condition if needed.
17149 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17151 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17152 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17153 DAG.getConstant(ShAmt, MVT::i8));
17154 if (N->getNumValues() == 2) // Dead flag value?
17155 return DCI.CombineTo(N, Cond, SDValue());
17159 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17160 // for any integer data type, including i8/i16.
17161 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17162 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17163 DAG.getConstant(CC, MVT::i8), Cond);
17165 // Zero extend the condition if needed.
17166 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17167 FalseC->getValueType(0), Cond);
17168 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17169 SDValue(FalseC, 0));
17171 if (N->getNumValues() == 2) // Dead flag value?
17172 return DCI.CombineTo(N, Cond, SDValue());
17176 // Optimize cases that will turn into an LEA instruction. This requires
17177 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17178 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17179 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17180 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17182 bool isFastMultiplier = false;
17184 switch ((unsigned char)Diff) {
17186 case 1: // result = add base, cond
17187 case 2: // result = lea base( , cond*2)
17188 case 3: // result = lea base(cond, cond*2)
17189 case 4: // result = lea base( , cond*4)
17190 case 5: // result = lea base(cond, cond*4)
17191 case 8: // result = lea base( , cond*8)
17192 case 9: // result = lea base(cond, cond*8)
17193 isFastMultiplier = true;
17198 if (isFastMultiplier) {
17199 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17200 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17201 DAG.getConstant(CC, MVT::i8), Cond);
17202 // Zero extend the condition if needed.
17203 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17205 // Scale the condition by the difference.
17207 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17208 DAG.getConstant(Diff, Cond.getValueType()));
17210 // Add the base if non-zero.
17211 if (FalseC->getAPIntValue() != 0)
17212 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17213 SDValue(FalseC, 0));
17214 if (N->getNumValues() == 2) // Dead flag value?
17215 return DCI.CombineTo(N, Cond, SDValue());
17222 // Handle these cases:
17223 // (select (x != c), e, c) -> select (x != c), e, x),
17224 // (select (x == c), c, e) -> select (x == c), x, e)
17225 // where the c is an integer constant, and the "select" is the combination
17226 // of CMOV and CMP.
17228 // The rationale for this change is that the conditional-move from a constant
17229 // needs two instructions, however, conditional-move from a register needs
17230 // only one instruction.
17232 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17233 // some instruction-combining opportunities. This opt needs to be
17234 // postponed as late as possible.
17236 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17237 // the DCI.xxxx conditions are provided to postpone the optimization as
17238 // late as possible.
17240 ConstantSDNode *CmpAgainst = 0;
17241 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17242 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17243 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17245 if (CC == X86::COND_NE &&
17246 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17247 CC = X86::GetOppositeBranchCondition(CC);
17248 std::swap(TrueOp, FalseOp);
17251 if (CC == X86::COND_E &&
17252 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17253 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17254 DAG.getConstant(CC, MVT::i8), Cond };
17255 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17256 array_lengthof(Ops));
17264 /// PerformMulCombine - Optimize a single multiply with constant into two
17265 /// in order to implement it with two cheaper instructions, e.g.
17266 /// LEA + SHL, LEA + LEA.
17267 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17268 TargetLowering::DAGCombinerInfo &DCI) {
17269 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17272 EVT VT = N->getValueType(0);
17273 if (VT != MVT::i64)
17276 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17279 uint64_t MulAmt = C->getZExtValue();
17280 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17283 uint64_t MulAmt1 = 0;
17284 uint64_t MulAmt2 = 0;
17285 if ((MulAmt % 9) == 0) {
17287 MulAmt2 = MulAmt / 9;
17288 } else if ((MulAmt % 5) == 0) {
17290 MulAmt2 = MulAmt / 5;
17291 } else if ((MulAmt % 3) == 0) {
17293 MulAmt2 = MulAmt / 3;
17296 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17299 if (isPowerOf2_64(MulAmt2) &&
17300 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17301 // If second multiplifer is pow2, issue it first. We want the multiply by
17302 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17304 std::swap(MulAmt1, MulAmt2);
17307 if (isPowerOf2_64(MulAmt1))
17308 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17309 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17311 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17312 DAG.getConstant(MulAmt1, VT));
17314 if (isPowerOf2_64(MulAmt2))
17315 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17316 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17318 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17319 DAG.getConstant(MulAmt2, VT));
17321 // Do not add new nodes to DAG combiner worklist.
17322 DCI.CombineTo(N, NewMul, false);
17327 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17328 SDValue N0 = N->getOperand(0);
17329 SDValue N1 = N->getOperand(1);
17330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17331 EVT VT = N0.getValueType();
17333 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17334 // since the result of setcc_c is all zero's or all ones.
17335 if (VT.isInteger() && !VT.isVector() &&
17336 N1C && N0.getOpcode() == ISD::AND &&
17337 N0.getOperand(1).getOpcode() == ISD::Constant) {
17338 SDValue N00 = N0.getOperand(0);
17339 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17340 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17341 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17342 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17343 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17344 APInt ShAmt = N1C->getAPIntValue();
17345 Mask = Mask.shl(ShAmt);
17347 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17348 N00, DAG.getConstant(Mask, VT));
17352 // Hardware support for vector shifts is sparse which makes us scalarize the
17353 // vector operations in many cases. Also, on sandybridge ADD is faster than
17355 // (shl V, 1) -> add V,V
17356 if (isSplatVector(N1.getNode())) {
17357 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17358 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17359 // We shift all of the values by one. In many cases we do not have
17360 // hardware support for this operation. This is better expressed as an ADD
17362 if (N1C && (1 == N1C->getZExtValue())) {
17363 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17370 /// \brief Returns a vector of 0s if the node in input is a vector logical
17371 /// shift by a constant amount which is known to be bigger than or equal
17372 /// to the vector element size in bits.
17373 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17374 const X86Subtarget *Subtarget) {
17375 EVT VT = N->getValueType(0);
17377 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17378 (!Subtarget->hasInt256() ||
17379 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17382 SDValue Amt = N->getOperand(1);
17384 if (isSplatVector(Amt.getNode())) {
17385 SDValue SclrAmt = Amt->getOperand(0);
17386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17387 APInt ShiftAmt = C->getAPIntValue();
17388 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17390 // SSE2/AVX2 logical shifts always return a vector of 0s
17391 // if the shift amount is bigger than or equal to
17392 // the element size. The constant shift amount will be
17393 // encoded as a 8-bit immediate.
17394 if (ShiftAmt.trunc(8).uge(MaxAmount))
17395 return getZeroVector(VT, Subtarget, DAG, DL);
17402 /// PerformShiftCombine - Combine shifts.
17403 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17404 TargetLowering::DAGCombinerInfo &DCI,
17405 const X86Subtarget *Subtarget) {
17406 if (N->getOpcode() == ISD::SHL) {
17407 SDValue V = PerformSHLCombine(N, DAG);
17408 if (V.getNode()) return V;
17411 if (N->getOpcode() != ISD::SRA) {
17412 // Try to fold this logical shift into a zero vector.
17413 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17414 if (V.getNode()) return V;
17420 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17421 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17422 // and friends. Likewise for OR -> CMPNEQSS.
17423 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17424 TargetLowering::DAGCombinerInfo &DCI,
17425 const X86Subtarget *Subtarget) {
17428 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17429 // we're requiring SSE2 for both.
17430 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17431 SDValue N0 = N->getOperand(0);
17432 SDValue N1 = N->getOperand(1);
17433 SDValue CMP0 = N0->getOperand(1);
17434 SDValue CMP1 = N1->getOperand(1);
17437 // The SETCCs should both refer to the same CMP.
17438 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17441 SDValue CMP00 = CMP0->getOperand(0);
17442 SDValue CMP01 = CMP0->getOperand(1);
17443 EVT VT = CMP00.getValueType();
17445 if (VT == MVT::f32 || VT == MVT::f64) {
17446 bool ExpectingFlags = false;
17447 // Check for any users that want flags:
17448 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17449 !ExpectingFlags && UI != UE; ++UI)
17450 switch (UI->getOpcode()) {
17455 ExpectingFlags = true;
17457 case ISD::CopyToReg:
17458 case ISD::SIGN_EXTEND:
17459 case ISD::ZERO_EXTEND:
17460 case ISD::ANY_EXTEND:
17464 if (!ExpectingFlags) {
17465 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17466 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17468 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17469 X86::CondCode tmp = cc0;
17474 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17475 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17476 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17477 X86ISD::NodeType NTOperator = is64BitFP ?
17478 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17479 // FIXME: need symbolic constants for these magic numbers.
17480 // See X86ATTInstPrinter.cpp:printSSECC().
17481 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17482 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17483 DAG.getConstant(x86cc, MVT::i8));
17484 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17486 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17487 DAG.getConstant(1, MVT::i32));
17488 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17489 return OneBitOfTruth;
17497 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17498 /// so it can be folded inside ANDNP.
17499 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17500 EVT VT = N->getValueType(0);
17502 // Match direct AllOnes for 128 and 256-bit vectors
17503 if (ISD::isBuildVectorAllOnes(N))
17506 // Look through a bit convert.
17507 if (N->getOpcode() == ISD::BITCAST)
17508 N = N->getOperand(0).getNode();
17510 // Sometimes the operand may come from a insert_subvector building a 256-bit
17512 if (VT.is256BitVector() &&
17513 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17514 SDValue V1 = N->getOperand(0);
17515 SDValue V2 = N->getOperand(1);
17517 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17518 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17519 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17520 ISD::isBuildVectorAllOnes(V2.getNode()))
17527 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17528 // register. In most cases we actually compare or select YMM-sized registers
17529 // and mixing the two types creates horrible code. This method optimizes
17530 // some of the transition sequences.
17531 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17532 TargetLowering::DAGCombinerInfo &DCI,
17533 const X86Subtarget *Subtarget) {
17534 EVT VT = N->getValueType(0);
17535 if (!VT.is256BitVector())
17538 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17539 N->getOpcode() == ISD::ZERO_EXTEND ||
17540 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17542 SDValue Narrow = N->getOperand(0);
17543 EVT NarrowVT = Narrow->getValueType(0);
17544 if (!NarrowVT.is128BitVector())
17547 if (Narrow->getOpcode() != ISD::XOR &&
17548 Narrow->getOpcode() != ISD::AND &&
17549 Narrow->getOpcode() != ISD::OR)
17552 SDValue N0 = Narrow->getOperand(0);
17553 SDValue N1 = Narrow->getOperand(1);
17556 // The Left side has to be a trunc.
17557 if (N0.getOpcode() != ISD::TRUNCATE)
17560 // The type of the truncated inputs.
17561 EVT WideVT = N0->getOperand(0)->getValueType(0);
17565 // The right side has to be a 'trunc' or a constant vector.
17566 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17567 bool RHSConst = (isSplatVector(N1.getNode()) &&
17568 isa<ConstantSDNode>(N1->getOperand(0)));
17569 if (!RHSTrunc && !RHSConst)
17572 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17574 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17577 // Set N0 and N1 to hold the inputs to the new wide operation.
17578 N0 = N0->getOperand(0);
17580 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17581 N1->getOperand(0));
17582 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17583 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17584 } else if (RHSTrunc) {
17585 N1 = N1->getOperand(0);
17588 // Generate the wide operation.
17589 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17590 unsigned Opcode = N->getOpcode();
17592 case ISD::ANY_EXTEND:
17594 case ISD::ZERO_EXTEND: {
17595 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17596 APInt Mask = APInt::getAllOnesValue(InBits);
17597 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17598 return DAG.getNode(ISD::AND, DL, VT,
17599 Op, DAG.getConstant(Mask, VT));
17601 case ISD::SIGN_EXTEND:
17602 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17603 Op, DAG.getValueType(NarrowVT));
17605 llvm_unreachable("Unexpected opcode");
17609 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17610 TargetLowering::DAGCombinerInfo &DCI,
17611 const X86Subtarget *Subtarget) {
17612 EVT VT = N->getValueType(0);
17613 if (DCI.isBeforeLegalizeOps())
17616 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17620 // Create BLSI, BLSR, and BZHI instructions
17621 // BLSI is X & (-X)
17622 // BLSR is X & (X-1)
17623 // BZHI is X & ((1 << Y) - 1)
17624 // BEXTR is ((X >> imm) & (2**size-1))
17625 if (VT == MVT::i32 || VT == MVT::i64) {
17626 SDValue N0 = N->getOperand(0);
17627 SDValue N1 = N->getOperand(1);
17630 if (Subtarget->hasBMI()) {
17631 // Check LHS for neg
17632 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17633 isZero(N0.getOperand(0)))
17634 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17636 // Check RHS for neg
17637 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17638 isZero(N1.getOperand(0)))
17639 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17641 // Check LHS for X-1
17642 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17643 isAllOnes(N0.getOperand(1)))
17644 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17646 // Check RHS for X-1
17647 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17648 isAllOnes(N1.getOperand(1)))
17649 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17652 if (Subtarget->hasBMI2()) {
17653 // Check for (and (add (shl 1, Y), -1), X)
17654 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17655 SDValue N00 = N0.getOperand(0);
17656 if (N00.getOpcode() == ISD::SHL) {
17657 SDValue N001 = N00.getOperand(1);
17658 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17659 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17660 if (C && C->getZExtValue() == 1)
17661 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17665 // Check for (and X, (add (shl 1, Y), -1))
17666 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17667 SDValue N10 = N1.getOperand(0);
17668 if (N10.getOpcode() == ISD::SHL) {
17669 SDValue N101 = N10.getOperand(1);
17670 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17671 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17672 if (C && C->getZExtValue() == 1)
17673 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17678 // Check for BEXTR.
17679 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17680 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17681 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17682 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17683 if (MaskNode && ShiftNode) {
17684 uint64_t Mask = MaskNode->getZExtValue();
17685 uint64_t Shift = ShiftNode->getZExtValue();
17686 if (isMask_64(Mask)) {
17687 uint64_t MaskSize = CountPopulation_64(Mask);
17688 if (Shift + MaskSize <= VT.getSizeInBits())
17689 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17690 DAG.getConstant(Shift | (MaskSize << 8), VT));
17698 // Want to form ANDNP nodes:
17699 // 1) In the hopes of then easily combining them with OR and AND nodes
17700 // to form PBLEND/PSIGN.
17701 // 2) To match ANDN packed intrinsics
17702 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17705 SDValue N0 = N->getOperand(0);
17706 SDValue N1 = N->getOperand(1);
17709 // Check LHS for vnot
17710 if (N0.getOpcode() == ISD::XOR &&
17711 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17712 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17713 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17715 // Check RHS for vnot
17716 if (N1.getOpcode() == ISD::XOR &&
17717 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17718 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17719 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17724 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17725 TargetLowering::DAGCombinerInfo &DCI,
17726 const X86Subtarget *Subtarget) {
17727 EVT VT = N->getValueType(0);
17728 if (DCI.isBeforeLegalizeOps())
17731 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17735 SDValue N0 = N->getOperand(0);
17736 SDValue N1 = N->getOperand(1);
17738 // look for psign/blend
17739 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17740 if (!Subtarget->hasSSSE3() ||
17741 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17744 // Canonicalize pandn to RHS
17745 if (N0.getOpcode() == X86ISD::ANDNP)
17747 // or (and (m, y), (pandn m, x))
17748 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17749 SDValue Mask = N1.getOperand(0);
17750 SDValue X = N1.getOperand(1);
17752 if (N0.getOperand(0) == Mask)
17753 Y = N0.getOperand(1);
17754 if (N0.getOperand(1) == Mask)
17755 Y = N0.getOperand(0);
17757 // Check to see if the mask appeared in both the AND and ANDNP and
17761 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17762 // Look through mask bitcast.
17763 if (Mask.getOpcode() == ISD::BITCAST)
17764 Mask = Mask.getOperand(0);
17765 if (X.getOpcode() == ISD::BITCAST)
17766 X = X.getOperand(0);
17767 if (Y.getOpcode() == ISD::BITCAST)
17768 Y = Y.getOperand(0);
17770 EVT MaskVT = Mask.getValueType();
17772 // Validate that the Mask operand is a vector sra node.
17773 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17774 // there is no psrai.b
17775 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17776 unsigned SraAmt = ~0;
17777 if (Mask.getOpcode() == ISD::SRA) {
17778 SDValue Amt = Mask.getOperand(1);
17779 if (isSplatVector(Amt.getNode())) {
17780 SDValue SclrAmt = Amt->getOperand(0);
17781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17782 SraAmt = C->getZExtValue();
17784 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17785 SDValue SraC = Mask.getOperand(1);
17786 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17788 if ((SraAmt + 1) != EltBits)
17793 // Now we know we at least have a plendvb with the mask val. See if
17794 // we can form a psignb/w/d.
17795 // psign = x.type == y.type == mask.type && y = sub(0, x);
17796 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17797 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17798 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17799 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17800 "Unsupported VT for PSIGN");
17801 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17802 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17804 // PBLENDVB only available on SSE 4.1
17805 if (!Subtarget->hasSSE41())
17808 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17810 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17811 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17812 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17813 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17814 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17818 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17821 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17822 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17824 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17826 if (!N0.hasOneUse() || !N1.hasOneUse())
17829 SDValue ShAmt0 = N0.getOperand(1);
17830 if (ShAmt0.getValueType() != MVT::i8)
17832 SDValue ShAmt1 = N1.getOperand(1);
17833 if (ShAmt1.getValueType() != MVT::i8)
17835 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17836 ShAmt0 = ShAmt0.getOperand(0);
17837 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17838 ShAmt1 = ShAmt1.getOperand(0);
17841 unsigned Opc = X86ISD::SHLD;
17842 SDValue Op0 = N0.getOperand(0);
17843 SDValue Op1 = N1.getOperand(0);
17844 if (ShAmt0.getOpcode() == ISD::SUB) {
17845 Opc = X86ISD::SHRD;
17846 std::swap(Op0, Op1);
17847 std::swap(ShAmt0, ShAmt1);
17850 unsigned Bits = VT.getSizeInBits();
17851 if (ShAmt1.getOpcode() == ISD::SUB) {
17852 SDValue Sum = ShAmt1.getOperand(0);
17853 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17854 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17855 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17856 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17857 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17858 return DAG.getNode(Opc, DL, VT,
17860 DAG.getNode(ISD::TRUNCATE, DL,
17863 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17864 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17866 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17867 return DAG.getNode(Opc, DL, VT,
17868 N0.getOperand(0), N1.getOperand(0),
17869 DAG.getNode(ISD::TRUNCATE, DL,
17876 // Generate NEG and CMOV for integer abs.
17877 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17878 EVT VT = N->getValueType(0);
17880 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17881 // 8-bit integer abs to NEG and CMOV.
17882 if (VT.isInteger() && VT.getSizeInBits() == 8)
17885 SDValue N0 = N->getOperand(0);
17886 SDValue N1 = N->getOperand(1);
17889 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17890 // and change it to SUB and CMOV.
17891 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17892 N0.getOpcode() == ISD::ADD &&
17893 N0.getOperand(1) == N1 &&
17894 N1.getOpcode() == ISD::SRA &&
17895 N1.getOperand(0) == N0.getOperand(0))
17896 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17897 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17898 // Generate SUB & CMOV.
17899 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17900 DAG.getConstant(0, VT), N0.getOperand(0));
17902 SDValue Ops[] = { N0.getOperand(0), Neg,
17903 DAG.getConstant(X86::COND_GE, MVT::i8),
17904 SDValue(Neg.getNode(), 1) };
17905 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17906 Ops, array_lengthof(Ops));
17911 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17912 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17913 TargetLowering::DAGCombinerInfo &DCI,
17914 const X86Subtarget *Subtarget) {
17915 EVT VT = N->getValueType(0);
17916 if (DCI.isBeforeLegalizeOps())
17919 if (Subtarget->hasCMov()) {
17920 SDValue RV = performIntegerAbsCombine(N, DAG);
17925 // Try forming BMI if it is available.
17926 if (!Subtarget->hasBMI())
17929 if (VT != MVT::i32 && VT != MVT::i64)
17932 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17934 // Create BLSMSK instructions by finding X ^ (X-1)
17935 SDValue N0 = N->getOperand(0);
17936 SDValue N1 = N->getOperand(1);
17939 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17940 isAllOnes(N0.getOperand(1)))
17941 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17943 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17944 isAllOnes(N1.getOperand(1)))
17945 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17950 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17951 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17952 TargetLowering::DAGCombinerInfo &DCI,
17953 const X86Subtarget *Subtarget) {
17954 LoadSDNode *Ld = cast<LoadSDNode>(N);
17955 EVT RegVT = Ld->getValueType(0);
17956 EVT MemVT = Ld->getMemoryVT();
17958 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17959 unsigned RegSz = RegVT.getSizeInBits();
17961 // On Sandybridge unaligned 256bit loads are inefficient.
17962 ISD::LoadExtType Ext = Ld->getExtensionType();
17963 unsigned Alignment = Ld->getAlignment();
17964 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17965 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17966 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17967 unsigned NumElems = RegVT.getVectorNumElements();
17971 SDValue Ptr = Ld->getBasePtr();
17972 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17974 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17976 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17977 Ld->getPointerInfo(), Ld->isVolatile(),
17978 Ld->isNonTemporal(), Ld->isInvariant(),
17980 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17981 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17982 Ld->getPointerInfo(), Ld->isVolatile(),
17983 Ld->isNonTemporal(), Ld->isInvariant(),
17984 std::min(16U, Alignment));
17985 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17987 Load2.getValue(1));
17989 SDValue NewVec = DAG.getUNDEF(RegVT);
17990 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17991 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17992 return DCI.CombineTo(N, NewVec, TF, true);
17995 // If this is a vector EXT Load then attempt to optimize it using a
17996 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17997 // expansion is still better than scalar code.
17998 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17999 // emit a shuffle and a arithmetic shift.
18000 // TODO: It is possible to support ZExt by zeroing the undef values
18001 // during the shuffle phase or after the shuffle.
18002 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18003 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18004 assert(MemVT != RegVT && "Cannot extend to the same type");
18005 assert(MemVT.isVector() && "Must load a vector from memory");
18007 unsigned NumElems = RegVT.getVectorNumElements();
18008 unsigned MemSz = MemVT.getSizeInBits();
18009 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18011 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18014 // All sizes must be a power of two.
18015 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18018 // Attempt to load the original value using scalar loads.
18019 // Find the largest scalar type that divides the total loaded size.
18020 MVT SclrLoadTy = MVT::i8;
18021 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18022 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18023 MVT Tp = (MVT::SimpleValueType)tp;
18024 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18029 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18030 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18032 SclrLoadTy = MVT::f64;
18034 // Calculate the number of scalar loads that we need to perform
18035 // in order to load our vector from memory.
18036 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18037 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18040 unsigned loadRegZize = RegSz;
18041 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18044 // Represent our vector as a sequence of elements which are the
18045 // largest scalar that we can load.
18046 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18047 loadRegZize/SclrLoadTy.getSizeInBits());
18049 // Represent the data using the same element type that is stored in
18050 // memory. In practice, we ''widen'' MemVT.
18052 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18053 loadRegZize/MemVT.getScalarType().getSizeInBits());
18055 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18056 "Invalid vector type");
18058 // We can't shuffle using an illegal type.
18059 if (!TLI.isTypeLegal(WideVecVT))
18062 SmallVector<SDValue, 8> Chains;
18063 SDValue Ptr = Ld->getBasePtr();
18064 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18065 TLI.getPointerTy());
18066 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18068 for (unsigned i = 0; i < NumLoads; ++i) {
18069 // Perform a single load.
18070 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18071 Ptr, Ld->getPointerInfo(),
18072 Ld->isVolatile(), Ld->isNonTemporal(),
18073 Ld->isInvariant(), Ld->getAlignment());
18074 Chains.push_back(ScalarLoad.getValue(1));
18075 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18076 // another round of DAGCombining.
18078 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18080 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18081 ScalarLoad, DAG.getIntPtrConstant(i));
18083 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18086 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18089 // Bitcast the loaded value to a vector of the original element type, in
18090 // the size of the target vector type.
18091 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18092 unsigned SizeRatio = RegSz/MemSz;
18094 if (Ext == ISD::SEXTLOAD) {
18095 // If we have SSE4.1 we can directly emit a VSEXT node.
18096 if (Subtarget->hasSSE41()) {
18097 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18098 return DCI.CombineTo(N, Sext, TF, true);
18101 // Otherwise we'll shuffle the small elements in the high bits of the
18102 // larger type and perform an arithmetic shift. If the shift is not legal
18103 // it's better to scalarize.
18104 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18107 // Redistribute the loaded elements into the different locations.
18108 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18109 for (unsigned i = 0; i != NumElems; ++i)
18110 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18112 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18113 DAG.getUNDEF(WideVecVT),
18116 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18118 // Build the arithmetic shift.
18119 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18120 MemVT.getVectorElementType().getSizeInBits();
18121 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18122 DAG.getConstant(Amt, RegVT));
18124 return DCI.CombineTo(N, Shuff, TF, true);
18127 // Redistribute the loaded elements into the different locations.
18128 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18129 for (unsigned i = 0; i != NumElems; ++i)
18130 ShuffleVec[i*SizeRatio] = i;
18132 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18133 DAG.getUNDEF(WideVecVT),
18136 // Bitcast to the requested type.
18137 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18138 // Replace the original load with the new sequence
18139 // and return the new chain.
18140 return DCI.CombineTo(N, Shuff, TF, true);
18146 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18147 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18148 const X86Subtarget *Subtarget) {
18149 StoreSDNode *St = cast<StoreSDNode>(N);
18150 EVT VT = St->getValue().getValueType();
18151 EVT StVT = St->getMemoryVT();
18153 SDValue StoredVal = St->getOperand(1);
18154 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18156 // If we are saving a concatenation of two XMM registers, perform two stores.
18157 // On Sandy Bridge, 256-bit memory operations are executed by two
18158 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18159 // memory operation.
18160 unsigned Alignment = St->getAlignment();
18161 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18162 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18163 StVT == VT && !IsAligned) {
18164 unsigned NumElems = VT.getVectorNumElements();
18168 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18169 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18171 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18172 SDValue Ptr0 = St->getBasePtr();
18173 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18175 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18176 St->getPointerInfo(), St->isVolatile(),
18177 St->isNonTemporal(), Alignment);
18178 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18179 St->getPointerInfo(), St->isVolatile(),
18180 St->isNonTemporal(),
18181 std::min(16U, Alignment));
18182 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18185 // Optimize trunc store (of multiple scalars) to shuffle and store.
18186 // First, pack all of the elements in one place. Next, store to memory
18187 // in fewer chunks.
18188 if (St->isTruncatingStore() && VT.isVector()) {
18189 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18190 unsigned NumElems = VT.getVectorNumElements();
18191 assert(StVT != VT && "Cannot truncate to the same type");
18192 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18193 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18195 // From, To sizes and ElemCount must be pow of two
18196 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18197 // We are going to use the original vector elt for storing.
18198 // Accumulated smaller vector elements must be a multiple of the store size.
18199 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18201 unsigned SizeRatio = FromSz / ToSz;
18203 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18205 // Create a type on which we perform the shuffle
18206 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18207 StVT.getScalarType(), NumElems*SizeRatio);
18209 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18211 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18212 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18213 for (unsigned i = 0; i != NumElems; ++i)
18214 ShuffleVec[i] = i * SizeRatio;
18216 // Can't shuffle using an illegal type.
18217 if (!TLI.isTypeLegal(WideVecVT))
18220 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18221 DAG.getUNDEF(WideVecVT),
18223 // At this point all of the data is stored at the bottom of the
18224 // register. We now need to save it to mem.
18226 // Find the largest store unit
18227 MVT StoreType = MVT::i8;
18228 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18229 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18230 MVT Tp = (MVT::SimpleValueType)tp;
18231 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18235 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18236 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18237 (64 <= NumElems * ToSz))
18238 StoreType = MVT::f64;
18240 // Bitcast the original vector into a vector of store-size units
18241 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18242 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18243 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18244 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18245 SmallVector<SDValue, 8> Chains;
18246 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18247 TLI.getPointerTy());
18248 SDValue Ptr = St->getBasePtr();
18250 // Perform one or more big stores into memory.
18251 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18252 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18253 StoreType, ShuffWide,
18254 DAG.getIntPtrConstant(i));
18255 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18256 St->getPointerInfo(), St->isVolatile(),
18257 St->isNonTemporal(), St->getAlignment());
18258 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18259 Chains.push_back(Ch);
18262 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18266 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18267 // the FP state in cases where an emms may be missing.
18268 // A preferable solution to the general problem is to figure out the right
18269 // places to insert EMMS. This qualifies as a quick hack.
18271 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18272 if (VT.getSizeInBits() != 64)
18275 const Function *F = DAG.getMachineFunction().getFunction();
18276 bool NoImplicitFloatOps = F->getAttributes().
18277 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18278 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18279 && Subtarget->hasSSE2();
18280 if ((VT.isVector() ||
18281 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18282 isa<LoadSDNode>(St->getValue()) &&
18283 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18284 St->getChain().hasOneUse() && !St->isVolatile()) {
18285 SDNode* LdVal = St->getValue().getNode();
18286 LoadSDNode *Ld = 0;
18287 int TokenFactorIndex = -1;
18288 SmallVector<SDValue, 8> Ops;
18289 SDNode* ChainVal = St->getChain().getNode();
18290 // Must be a store of a load. We currently handle two cases: the load
18291 // is a direct child, and it's under an intervening TokenFactor. It is
18292 // possible to dig deeper under nested TokenFactors.
18293 if (ChainVal == LdVal)
18294 Ld = cast<LoadSDNode>(St->getChain());
18295 else if (St->getValue().hasOneUse() &&
18296 ChainVal->getOpcode() == ISD::TokenFactor) {
18297 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18298 if (ChainVal->getOperand(i).getNode() == LdVal) {
18299 TokenFactorIndex = i;
18300 Ld = cast<LoadSDNode>(St->getValue());
18302 Ops.push_back(ChainVal->getOperand(i));
18306 if (!Ld || !ISD::isNormalLoad(Ld))
18309 // If this is not the MMX case, i.e. we are just turning i64 load/store
18310 // into f64 load/store, avoid the transformation if there are multiple
18311 // uses of the loaded value.
18312 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18317 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18318 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18320 if (Subtarget->is64Bit() || F64IsLegal) {
18321 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18322 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18323 Ld->getPointerInfo(), Ld->isVolatile(),
18324 Ld->isNonTemporal(), Ld->isInvariant(),
18325 Ld->getAlignment());
18326 SDValue NewChain = NewLd.getValue(1);
18327 if (TokenFactorIndex != -1) {
18328 Ops.push_back(NewChain);
18329 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18332 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18333 St->getPointerInfo(),
18334 St->isVolatile(), St->isNonTemporal(),
18335 St->getAlignment());
18338 // Otherwise, lower to two pairs of 32-bit loads / stores.
18339 SDValue LoAddr = Ld->getBasePtr();
18340 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18341 DAG.getConstant(4, MVT::i32));
18343 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18344 Ld->getPointerInfo(),
18345 Ld->isVolatile(), Ld->isNonTemporal(),
18346 Ld->isInvariant(), Ld->getAlignment());
18347 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18348 Ld->getPointerInfo().getWithOffset(4),
18349 Ld->isVolatile(), Ld->isNonTemporal(),
18351 MinAlign(Ld->getAlignment(), 4));
18353 SDValue NewChain = LoLd.getValue(1);
18354 if (TokenFactorIndex != -1) {
18355 Ops.push_back(LoLd);
18356 Ops.push_back(HiLd);
18357 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18361 LoAddr = St->getBasePtr();
18362 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18363 DAG.getConstant(4, MVT::i32));
18365 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18366 St->getPointerInfo(),
18367 St->isVolatile(), St->isNonTemporal(),
18368 St->getAlignment());
18369 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18370 St->getPointerInfo().getWithOffset(4),
18372 St->isNonTemporal(),
18373 MinAlign(St->getAlignment(), 4));
18374 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18379 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18380 /// and return the operands for the horizontal operation in LHS and RHS. A
18381 /// horizontal operation performs the binary operation on successive elements
18382 /// of its first operand, then on successive elements of its second operand,
18383 /// returning the resulting values in a vector. For example, if
18384 /// A = < float a0, float a1, float a2, float a3 >
18386 /// B = < float b0, float b1, float b2, float b3 >
18387 /// then the result of doing a horizontal operation on A and B is
18388 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18389 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18390 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18391 /// set to A, RHS to B, and the routine returns 'true'.
18392 /// Note that the binary operation should have the property that if one of the
18393 /// operands is UNDEF then the result is UNDEF.
18394 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18395 // Look for the following pattern: if
18396 // A = < float a0, float a1, float a2, float a3 >
18397 // B = < float b0, float b1, float b2, float b3 >
18399 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18400 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18401 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18402 // which is A horizontal-op B.
18404 // At least one of the operands should be a vector shuffle.
18405 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18406 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18409 MVT VT = LHS.getSimpleValueType();
18411 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18412 "Unsupported vector type for horizontal add/sub");
18414 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18415 // operate independently on 128-bit lanes.
18416 unsigned NumElts = VT.getVectorNumElements();
18417 unsigned NumLanes = VT.getSizeInBits()/128;
18418 unsigned NumLaneElts = NumElts / NumLanes;
18419 assert((NumLaneElts % 2 == 0) &&
18420 "Vector type should have an even number of elements in each lane");
18421 unsigned HalfLaneElts = NumLaneElts/2;
18423 // View LHS in the form
18424 // LHS = VECTOR_SHUFFLE A, B, LMask
18425 // If LHS is not a shuffle then pretend it is the shuffle
18426 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18427 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18430 SmallVector<int, 16> LMask(NumElts);
18431 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18432 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18433 A = LHS.getOperand(0);
18434 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18435 B = LHS.getOperand(1);
18436 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18437 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18439 if (LHS.getOpcode() != ISD::UNDEF)
18441 for (unsigned i = 0; i != NumElts; ++i)
18445 // Likewise, view RHS in the form
18446 // RHS = VECTOR_SHUFFLE C, D, RMask
18448 SmallVector<int, 16> RMask(NumElts);
18449 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18450 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18451 C = RHS.getOperand(0);
18452 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18453 D = RHS.getOperand(1);
18454 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18455 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18457 if (RHS.getOpcode() != ISD::UNDEF)
18459 for (unsigned i = 0; i != NumElts; ++i)
18463 // Check that the shuffles are both shuffling the same vectors.
18464 if (!(A == C && B == D) && !(A == D && B == C))
18467 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18468 if (!A.getNode() && !B.getNode())
18471 // If A and B occur in reverse order in RHS, then "swap" them (which means
18472 // rewriting the mask).
18474 CommuteVectorShuffleMask(RMask, NumElts);
18476 // At this point LHS and RHS are equivalent to
18477 // LHS = VECTOR_SHUFFLE A, B, LMask
18478 // RHS = VECTOR_SHUFFLE A, B, RMask
18479 // Check that the masks correspond to performing a horizontal operation.
18480 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18481 for (unsigned i = 0; i != NumLaneElts; ++i) {
18482 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18484 // Ignore any UNDEF components.
18485 if (LIdx < 0 || RIdx < 0 ||
18486 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18487 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18490 // Check that successive elements are being operated on. If not, this is
18491 // not a horizontal operation.
18492 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18493 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18494 if (!(LIdx == Index && RIdx == Index + 1) &&
18495 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18500 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18501 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18505 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18506 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18507 const X86Subtarget *Subtarget) {
18508 EVT VT = N->getValueType(0);
18509 SDValue LHS = N->getOperand(0);
18510 SDValue RHS = N->getOperand(1);
18512 // Try to synthesize horizontal adds from adds of shuffles.
18513 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18514 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18515 isHorizontalBinOp(LHS, RHS, true))
18516 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18520 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18521 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18522 const X86Subtarget *Subtarget) {
18523 EVT VT = N->getValueType(0);
18524 SDValue LHS = N->getOperand(0);
18525 SDValue RHS = N->getOperand(1);
18527 // Try to synthesize horizontal subs from subs of shuffles.
18528 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18529 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18530 isHorizontalBinOp(LHS, RHS, false))
18531 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18535 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18536 /// X86ISD::FXOR nodes.
18537 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18538 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18539 // F[X]OR(0.0, x) -> x
18540 // F[X]OR(x, 0.0) -> x
18541 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18542 if (C->getValueAPF().isPosZero())
18543 return N->getOperand(1);
18544 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18545 if (C->getValueAPF().isPosZero())
18546 return N->getOperand(0);
18550 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18551 /// X86ISD::FMAX nodes.
18552 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18553 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18555 // Only perform optimizations if UnsafeMath is used.
18556 if (!DAG.getTarget().Options.UnsafeFPMath)
18559 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18560 // into FMINC and FMAXC, which are Commutative operations.
18561 unsigned NewOp = 0;
18562 switch (N->getOpcode()) {
18563 default: llvm_unreachable("unknown opcode");
18564 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18565 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18568 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18569 N->getOperand(0), N->getOperand(1));
18572 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18573 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18574 // FAND(0.0, x) -> 0.0
18575 // FAND(x, 0.0) -> 0.0
18576 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18577 if (C->getValueAPF().isPosZero())
18578 return N->getOperand(0);
18579 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18580 if (C->getValueAPF().isPosZero())
18581 return N->getOperand(1);
18585 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18586 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18587 // FANDN(x, 0.0) -> 0.0
18588 // FANDN(0.0, x) -> x
18589 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18590 if (C->getValueAPF().isPosZero())
18591 return N->getOperand(1);
18592 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18593 if (C->getValueAPF().isPosZero())
18594 return N->getOperand(1);
18598 static SDValue PerformBTCombine(SDNode *N,
18600 TargetLowering::DAGCombinerInfo &DCI) {
18601 // BT ignores high bits in the bit index operand.
18602 SDValue Op1 = N->getOperand(1);
18603 if (Op1.hasOneUse()) {
18604 unsigned BitWidth = Op1.getValueSizeInBits();
18605 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18606 APInt KnownZero, KnownOne;
18607 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18608 !DCI.isBeforeLegalizeOps());
18609 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18610 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18611 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18612 DCI.CommitTargetLoweringOpt(TLO);
18617 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18618 SDValue Op = N->getOperand(0);
18619 if (Op.getOpcode() == ISD::BITCAST)
18620 Op = Op.getOperand(0);
18621 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18622 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18623 VT.getVectorElementType().getSizeInBits() ==
18624 OpVT.getVectorElementType().getSizeInBits()) {
18625 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18630 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18631 const X86Subtarget *Subtarget) {
18632 EVT VT = N->getValueType(0);
18633 if (!VT.isVector())
18636 SDValue N0 = N->getOperand(0);
18637 SDValue N1 = N->getOperand(1);
18638 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18641 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18642 // both SSE and AVX2 since there is no sign-extended shift right
18643 // operation on a vector with 64-bit elements.
18644 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18645 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18646 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18647 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18648 SDValue N00 = N0.getOperand(0);
18650 // EXTLOAD has a better solution on AVX2,
18651 // it may be replaced with X86ISD::VSEXT node.
18652 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18653 if (!ISD::isNormalLoad(N00.getNode()))
18656 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18657 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18659 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18665 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18666 TargetLowering::DAGCombinerInfo &DCI,
18667 const X86Subtarget *Subtarget) {
18668 if (!DCI.isBeforeLegalizeOps())
18671 if (!Subtarget->hasFp256())
18674 EVT VT = N->getValueType(0);
18675 if (VT.isVector() && VT.getSizeInBits() == 256) {
18676 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18684 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18685 const X86Subtarget* Subtarget) {
18687 EVT VT = N->getValueType(0);
18689 // Let legalize expand this if it isn't a legal type yet.
18690 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18693 EVT ScalarVT = VT.getScalarType();
18694 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18695 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18698 SDValue A = N->getOperand(0);
18699 SDValue B = N->getOperand(1);
18700 SDValue C = N->getOperand(2);
18702 bool NegA = (A.getOpcode() == ISD::FNEG);
18703 bool NegB = (B.getOpcode() == ISD::FNEG);
18704 bool NegC = (C.getOpcode() == ISD::FNEG);
18706 // Negative multiplication when NegA xor NegB
18707 bool NegMul = (NegA != NegB);
18709 A = A.getOperand(0);
18711 B = B.getOperand(0);
18713 C = C.getOperand(0);
18717 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18719 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18721 return DAG.getNode(Opcode, dl, VT, A, B, C);
18724 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18725 TargetLowering::DAGCombinerInfo &DCI,
18726 const X86Subtarget *Subtarget) {
18727 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18728 // (and (i32 x86isd::setcc_carry), 1)
18729 // This eliminates the zext. This transformation is necessary because
18730 // ISD::SETCC is always legalized to i8.
18732 SDValue N0 = N->getOperand(0);
18733 EVT VT = N->getValueType(0);
18735 if (N0.getOpcode() == ISD::AND &&
18737 N0.getOperand(0).hasOneUse()) {
18738 SDValue N00 = N0.getOperand(0);
18739 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18740 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18741 if (!C || C->getZExtValue() != 1)
18743 return DAG.getNode(ISD::AND, dl, VT,
18744 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18745 N00.getOperand(0), N00.getOperand(1)),
18746 DAG.getConstant(1, VT));
18750 if (VT.is256BitVector()) {
18751 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18759 // Optimize x == -y --> x+y == 0
18760 // x != -y --> x+y != 0
18761 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18762 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18763 SDValue LHS = N->getOperand(0);
18764 SDValue RHS = N->getOperand(1);
18766 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18767 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18768 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18769 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18770 LHS.getValueType(), RHS, LHS.getOperand(1));
18771 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18772 addV, DAG.getConstant(0, addV.getValueType()), CC);
18774 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18775 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18776 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18777 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18778 RHS.getValueType(), LHS, RHS.getOperand(1));
18779 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18780 addV, DAG.getConstant(0, addV.getValueType()), CC);
18785 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18786 // as "sbb reg,reg", since it can be extended without zext and produces
18787 // an all-ones bit which is more useful than 0/1 in some cases.
18788 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18789 return DAG.getNode(ISD::AND, DL, MVT::i8,
18790 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18791 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18792 DAG.getConstant(1, MVT::i8));
18795 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18796 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18797 TargetLowering::DAGCombinerInfo &DCI,
18798 const X86Subtarget *Subtarget) {
18800 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18801 SDValue EFLAGS = N->getOperand(1);
18803 if (CC == X86::COND_A) {
18804 // Try to convert COND_A into COND_B in an attempt to facilitate
18805 // materializing "setb reg".
18807 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18808 // cannot take an immediate as its first operand.
18810 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18811 EFLAGS.getValueType().isInteger() &&
18812 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18813 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18814 EFLAGS.getNode()->getVTList(),
18815 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18816 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18817 return MaterializeSETB(DL, NewEFLAGS, DAG);
18821 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18822 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18824 if (CC == X86::COND_B)
18825 return MaterializeSETB(DL, EFLAGS, DAG);
18829 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18830 if (Flags.getNode()) {
18831 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18832 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18838 // Optimize branch condition evaluation.
18840 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18841 TargetLowering::DAGCombinerInfo &DCI,
18842 const X86Subtarget *Subtarget) {
18844 SDValue Chain = N->getOperand(0);
18845 SDValue Dest = N->getOperand(1);
18846 SDValue EFLAGS = N->getOperand(3);
18847 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18851 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18852 if (Flags.getNode()) {
18853 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18854 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18861 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18862 const X86TargetLowering *XTLI) {
18863 SDValue Op0 = N->getOperand(0);
18864 EVT InVT = Op0->getValueType(0);
18866 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18867 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18869 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18870 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18871 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18874 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18875 // a 32-bit target where SSE doesn't support i64->FP operations.
18876 if (Op0.getOpcode() == ISD::LOAD) {
18877 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18878 EVT VT = Ld->getValueType(0);
18879 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18880 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18881 !XTLI->getSubtarget()->is64Bit() &&
18883 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18884 Ld->getChain(), Op0, DAG);
18885 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18892 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18893 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18894 X86TargetLowering::DAGCombinerInfo &DCI) {
18895 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18896 // the result is either zero or one (depending on the input carry bit).
18897 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18898 if (X86::isZeroNode(N->getOperand(0)) &&
18899 X86::isZeroNode(N->getOperand(1)) &&
18900 // We don't have a good way to replace an EFLAGS use, so only do this when
18902 SDValue(N, 1).use_empty()) {
18904 EVT VT = N->getValueType(0);
18905 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18906 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18907 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18908 DAG.getConstant(X86::COND_B,MVT::i8),
18910 DAG.getConstant(1, VT));
18911 return DCI.CombineTo(N, Res1, CarryOut);
18917 // fold (add Y, (sete X, 0)) -> adc 0, Y
18918 // (add Y, (setne X, 0)) -> sbb -1, Y
18919 // (sub (sete X, 0), Y) -> sbb 0, Y
18920 // (sub (setne X, 0), Y) -> adc -1, Y
18921 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18924 // Look through ZExts.
18925 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18926 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18929 SDValue SetCC = Ext.getOperand(0);
18930 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18933 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18934 if (CC != X86::COND_E && CC != X86::COND_NE)
18937 SDValue Cmp = SetCC.getOperand(1);
18938 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18939 !X86::isZeroNode(Cmp.getOperand(1)) ||
18940 !Cmp.getOperand(0).getValueType().isInteger())
18943 SDValue CmpOp0 = Cmp.getOperand(0);
18944 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18945 DAG.getConstant(1, CmpOp0.getValueType()));
18947 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18948 if (CC == X86::COND_NE)
18949 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18950 DL, OtherVal.getValueType(), OtherVal,
18951 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18952 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18953 DL, OtherVal.getValueType(), OtherVal,
18954 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18957 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18958 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18959 const X86Subtarget *Subtarget) {
18960 EVT VT = N->getValueType(0);
18961 SDValue Op0 = N->getOperand(0);
18962 SDValue Op1 = N->getOperand(1);
18964 // Try to synthesize horizontal adds from adds of shuffles.
18965 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18966 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18967 isHorizontalBinOp(Op0, Op1, true))
18968 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18970 return OptimizeConditionalInDecrement(N, DAG);
18973 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18974 const X86Subtarget *Subtarget) {
18975 SDValue Op0 = N->getOperand(0);
18976 SDValue Op1 = N->getOperand(1);
18978 // X86 can't encode an immediate LHS of a sub. See if we can push the
18979 // negation into a preceding instruction.
18980 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18981 // If the RHS of the sub is a XOR with one use and a constant, invert the
18982 // immediate. Then add one to the LHS of the sub so we can turn
18983 // X-Y -> X+~Y+1, saving one register.
18984 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18985 isa<ConstantSDNode>(Op1.getOperand(1))) {
18986 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18987 EVT VT = Op0.getValueType();
18988 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18990 DAG.getConstant(~XorC, VT));
18991 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18992 DAG.getConstant(C->getAPIntValue()+1, VT));
18996 // Try to synthesize horizontal adds from adds of shuffles.
18997 EVT VT = N->getValueType(0);
18998 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18999 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19000 isHorizontalBinOp(Op0, Op1, true))
19001 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19003 return OptimizeConditionalInDecrement(N, DAG);
19006 /// performVZEXTCombine - Performs build vector combines
19007 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19008 TargetLowering::DAGCombinerInfo &DCI,
19009 const X86Subtarget *Subtarget) {
19010 // (vzext (bitcast (vzext (x)) -> (vzext x)
19011 SDValue In = N->getOperand(0);
19012 while (In.getOpcode() == ISD::BITCAST)
19013 In = In.getOperand(0);
19015 if (In.getOpcode() != X86ISD::VZEXT)
19018 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19022 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19023 DAGCombinerInfo &DCI) const {
19024 SelectionDAG &DAG = DCI.DAG;
19025 switch (N->getOpcode()) {
19027 case ISD::EXTRACT_VECTOR_ELT:
19028 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19030 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19031 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19032 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19033 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19034 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19035 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19038 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19039 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19040 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19041 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19042 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19043 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19044 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19045 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19046 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19048 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19050 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19051 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19052 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19053 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19054 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19055 case ISD::ANY_EXTEND:
19056 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19057 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19058 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19059 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19060 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19061 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19062 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19063 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19064 case X86ISD::SHUFP: // Handle all target specific shuffles
19065 case X86ISD::PALIGNR:
19066 case X86ISD::UNPCKH:
19067 case X86ISD::UNPCKL:
19068 case X86ISD::MOVHLPS:
19069 case X86ISD::MOVLHPS:
19070 case X86ISD::PSHUFD:
19071 case X86ISD::PSHUFHW:
19072 case X86ISD::PSHUFLW:
19073 case X86ISD::MOVSS:
19074 case X86ISD::MOVSD:
19075 case X86ISD::VPERMILP:
19076 case X86ISD::VPERM2X128:
19077 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19078 case ISD::CONCAT_VECTORS: return PerformConcatCombine(N, DAG, DCI, Subtarget);
19079 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19085 /// isTypeDesirableForOp - Return true if the target has native support for
19086 /// the specified value type and it is 'desirable' to use the type for the
19087 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19088 /// instruction encodings are longer and some i16 instructions are slow.
19089 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19090 if (!isTypeLegal(VT))
19092 if (VT != MVT::i16)
19099 case ISD::SIGN_EXTEND:
19100 case ISD::ZERO_EXTEND:
19101 case ISD::ANY_EXTEND:
19114 /// IsDesirableToPromoteOp - This method query the target whether it is
19115 /// beneficial for dag combiner to promote the specified node. If true, it
19116 /// should return the desired promotion type by reference.
19117 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19118 EVT VT = Op.getValueType();
19119 if (VT != MVT::i16)
19122 bool Promote = false;
19123 bool Commute = false;
19124 switch (Op.getOpcode()) {
19127 LoadSDNode *LD = cast<LoadSDNode>(Op);
19128 // If the non-extending load has a single use and it's not live out, then it
19129 // might be folded.
19130 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19131 Op.hasOneUse()*/) {
19132 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19133 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19134 // The only case where we'd want to promote LOAD (rather then it being
19135 // promoted as an operand is when it's only use is liveout.
19136 if (UI->getOpcode() != ISD::CopyToReg)
19143 case ISD::SIGN_EXTEND:
19144 case ISD::ZERO_EXTEND:
19145 case ISD::ANY_EXTEND:
19150 SDValue N0 = Op.getOperand(0);
19151 // Look out for (store (shl (load), x)).
19152 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19165 SDValue N0 = Op.getOperand(0);
19166 SDValue N1 = Op.getOperand(1);
19167 if (!Commute && MayFoldLoad(N1))
19169 // Avoid disabling potential load folding opportunities.
19170 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19172 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19182 //===----------------------------------------------------------------------===//
19183 // X86 Inline Assembly Support
19184 //===----------------------------------------------------------------------===//
19187 // Helper to match a string separated by whitespace.
19188 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19189 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19191 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19192 StringRef piece(*args[i]);
19193 if (!s.startswith(piece)) // Check if the piece matches.
19196 s = s.substr(piece.size());
19197 StringRef::size_type pos = s.find_first_not_of(" \t");
19198 if (pos == 0) // We matched a prefix.
19206 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19209 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19210 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19212 std::string AsmStr = IA->getAsmString();
19214 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19215 if (!Ty || Ty->getBitWidth() % 16 != 0)
19218 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19219 SmallVector<StringRef, 4> AsmPieces;
19220 SplitString(AsmStr, AsmPieces, ";\n");
19222 switch (AsmPieces.size()) {
19223 default: return false;
19225 // FIXME: this should verify that we are targeting a 486 or better. If not,
19226 // we will turn this bswap into something that will be lowered to logical
19227 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19228 // lower so don't worry about this.
19230 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19231 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19232 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19233 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19234 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19235 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19236 // No need to check constraints, nothing other than the equivalent of
19237 // "=r,0" would be valid here.
19238 return IntrinsicLowering::LowerToByteSwap(CI);
19241 // rorw $$8, ${0:w} --> llvm.bswap.i16
19242 if (CI->getType()->isIntegerTy(16) &&
19243 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19244 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19245 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19247 const std::string &ConstraintsStr = IA->getConstraintString();
19248 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19249 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19250 if (AsmPieces.size() == 4 &&
19251 AsmPieces[0] == "~{cc}" &&
19252 AsmPieces[1] == "~{dirflag}" &&
19253 AsmPieces[2] == "~{flags}" &&
19254 AsmPieces[3] == "~{fpsr}")
19255 return IntrinsicLowering::LowerToByteSwap(CI);
19259 if (CI->getType()->isIntegerTy(32) &&
19260 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19261 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19262 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19263 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19265 const std::string &ConstraintsStr = IA->getConstraintString();
19266 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19267 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19268 if (AsmPieces.size() == 4 &&
19269 AsmPieces[0] == "~{cc}" &&
19270 AsmPieces[1] == "~{dirflag}" &&
19271 AsmPieces[2] == "~{flags}" &&
19272 AsmPieces[3] == "~{fpsr}")
19273 return IntrinsicLowering::LowerToByteSwap(CI);
19276 if (CI->getType()->isIntegerTy(64)) {
19277 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19278 if (Constraints.size() >= 2 &&
19279 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19280 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19281 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19282 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19283 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19284 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19285 return IntrinsicLowering::LowerToByteSwap(CI);
19293 /// getConstraintType - Given a constraint letter, return the type of
19294 /// constraint it is for this target.
19295 X86TargetLowering::ConstraintType
19296 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19297 if (Constraint.size() == 1) {
19298 switch (Constraint[0]) {
19309 return C_RegisterClass;
19333 return TargetLowering::getConstraintType(Constraint);
19336 /// Examine constraint type and operand type and determine a weight value.
19337 /// This object must already have been set up with the operand type
19338 /// and the current alternative constraint selected.
19339 TargetLowering::ConstraintWeight
19340 X86TargetLowering::getSingleConstraintMatchWeight(
19341 AsmOperandInfo &info, const char *constraint) const {
19342 ConstraintWeight weight = CW_Invalid;
19343 Value *CallOperandVal = info.CallOperandVal;
19344 // If we don't have a value, we can't do a match,
19345 // but allow it at the lowest weight.
19346 if (CallOperandVal == NULL)
19348 Type *type = CallOperandVal->getType();
19349 // Look at the constraint type.
19350 switch (*constraint) {
19352 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19363 if (CallOperandVal->getType()->isIntegerTy())
19364 weight = CW_SpecificReg;
19369 if (type->isFloatingPointTy())
19370 weight = CW_SpecificReg;
19373 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19374 weight = CW_SpecificReg;
19378 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19379 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19380 weight = CW_Register;
19383 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19384 if (C->getZExtValue() <= 31)
19385 weight = CW_Constant;
19389 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19390 if (C->getZExtValue() <= 63)
19391 weight = CW_Constant;
19395 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19396 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19397 weight = CW_Constant;
19401 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19402 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19403 weight = CW_Constant;
19407 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19408 if (C->getZExtValue() <= 3)
19409 weight = CW_Constant;
19413 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19414 if (C->getZExtValue() <= 0xff)
19415 weight = CW_Constant;
19420 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19421 weight = CW_Constant;
19425 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19426 if ((C->getSExtValue() >= -0x80000000LL) &&
19427 (C->getSExtValue() <= 0x7fffffffLL))
19428 weight = CW_Constant;
19432 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19433 if (C->getZExtValue() <= 0xffffffff)
19434 weight = CW_Constant;
19441 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19442 /// with another that has more specific requirements based on the type of the
19443 /// corresponding operand.
19444 const char *X86TargetLowering::
19445 LowerXConstraint(EVT ConstraintVT) const {
19446 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19447 // 'f' like normal targets.
19448 if (ConstraintVT.isFloatingPoint()) {
19449 if (Subtarget->hasSSE2())
19451 if (Subtarget->hasSSE1())
19455 return TargetLowering::LowerXConstraint(ConstraintVT);
19458 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19459 /// vector. If it is invalid, don't add anything to Ops.
19460 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19461 std::string &Constraint,
19462 std::vector<SDValue>&Ops,
19463 SelectionDAG &DAG) const {
19464 SDValue Result(0, 0);
19466 // Only support length 1 constraints for now.
19467 if (Constraint.length() > 1) return;
19469 char ConstraintLetter = Constraint[0];
19470 switch (ConstraintLetter) {
19473 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19474 if (C->getZExtValue() <= 31) {
19475 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19481 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19482 if (C->getZExtValue() <= 63) {
19483 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19489 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19490 if (isInt<8>(C->getSExtValue())) {
19491 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19497 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19498 if (C->getZExtValue() <= 255) {
19499 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19505 // 32-bit signed value
19506 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19507 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19508 C->getSExtValue())) {
19509 // Widen to 64 bits here to get it sign extended.
19510 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19513 // FIXME gcc accepts some relocatable values here too, but only in certain
19514 // memory models; it's complicated.
19519 // 32-bit unsigned value
19520 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19521 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19522 C->getZExtValue())) {
19523 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19527 // FIXME gcc accepts some relocatable values here too, but only in certain
19528 // memory models; it's complicated.
19532 // Literal immediates are always ok.
19533 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19534 // Widen to 64 bits here to get it sign extended.
19535 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19539 // In any sort of PIC mode addresses need to be computed at runtime by
19540 // adding in a register or some sort of table lookup. These can't
19541 // be used as immediates.
19542 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19545 // If we are in non-pic codegen mode, we allow the address of a global (with
19546 // an optional displacement) to be used with 'i'.
19547 GlobalAddressSDNode *GA = 0;
19548 int64_t Offset = 0;
19550 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19552 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19553 Offset += GA->getOffset();
19555 } else if (Op.getOpcode() == ISD::ADD) {
19556 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19557 Offset += C->getZExtValue();
19558 Op = Op.getOperand(0);
19561 } else if (Op.getOpcode() == ISD::SUB) {
19562 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19563 Offset += -C->getZExtValue();
19564 Op = Op.getOperand(0);
19569 // Otherwise, this isn't something we can handle, reject it.
19573 const GlobalValue *GV = GA->getGlobal();
19574 // If we require an extra load to get this address, as in PIC mode, we
19575 // can't accept it.
19576 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19577 getTargetMachine())))
19580 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19581 GA->getValueType(0), Offset);
19586 if (Result.getNode()) {
19587 Ops.push_back(Result);
19590 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19593 std::pair<unsigned, const TargetRegisterClass*>
19594 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19596 // First, see if this is a constraint that directly corresponds to an LLVM
19598 if (Constraint.size() == 1) {
19599 // GCC Constraint Letters
19600 switch (Constraint[0]) {
19602 // TODO: Slight differences here in allocation order and leaving
19603 // RIP in the class. Do they matter any more here than they do
19604 // in the normal allocation?
19605 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19606 if (Subtarget->is64Bit()) {
19607 if (VT == MVT::i32 || VT == MVT::f32)
19608 return std::make_pair(0U, &X86::GR32RegClass);
19609 if (VT == MVT::i16)
19610 return std::make_pair(0U, &X86::GR16RegClass);
19611 if (VT == MVT::i8 || VT == MVT::i1)
19612 return std::make_pair(0U, &X86::GR8RegClass);
19613 if (VT == MVT::i64 || VT == MVT::f64)
19614 return std::make_pair(0U, &X86::GR64RegClass);
19617 // 32-bit fallthrough
19618 case 'Q': // Q_REGS
19619 if (VT == MVT::i32 || VT == MVT::f32)
19620 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19621 if (VT == MVT::i16)
19622 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19623 if (VT == MVT::i8 || VT == MVT::i1)
19624 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19625 if (VT == MVT::i64)
19626 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19628 case 'r': // GENERAL_REGS
19629 case 'l': // INDEX_REGS
19630 if (VT == MVT::i8 || VT == MVT::i1)
19631 return std::make_pair(0U, &X86::GR8RegClass);
19632 if (VT == MVT::i16)
19633 return std::make_pair(0U, &X86::GR16RegClass);
19634 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19635 return std::make_pair(0U, &X86::GR32RegClass);
19636 return std::make_pair(0U, &X86::GR64RegClass);
19637 case 'R': // LEGACY_REGS
19638 if (VT == MVT::i8 || VT == MVT::i1)
19639 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19640 if (VT == MVT::i16)
19641 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19642 if (VT == MVT::i32 || !Subtarget->is64Bit())
19643 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19644 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19645 case 'f': // FP Stack registers.
19646 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19647 // value to the correct fpstack register class.
19648 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19649 return std::make_pair(0U, &X86::RFP32RegClass);
19650 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19651 return std::make_pair(0U, &X86::RFP64RegClass);
19652 return std::make_pair(0U, &X86::RFP80RegClass);
19653 case 'y': // MMX_REGS if MMX allowed.
19654 if (!Subtarget->hasMMX()) break;
19655 return std::make_pair(0U, &X86::VR64RegClass);
19656 case 'Y': // SSE_REGS if SSE2 allowed
19657 if (!Subtarget->hasSSE2()) break;
19659 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19660 if (!Subtarget->hasSSE1()) break;
19662 switch (VT.SimpleTy) {
19664 // Scalar SSE types.
19667 return std::make_pair(0U, &X86::FR32RegClass);
19670 return std::make_pair(0U, &X86::FR64RegClass);
19678 return std::make_pair(0U, &X86::VR128RegClass);
19686 return std::make_pair(0U, &X86::VR256RegClass);
19691 return std::make_pair(0U, &X86::VR512RegClass);
19697 // Use the default implementation in TargetLowering to convert the register
19698 // constraint into a member of a register class.
19699 std::pair<unsigned, const TargetRegisterClass*> Res;
19700 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19702 // Not found as a standard register?
19703 if (Res.second == 0) {
19704 // Map st(0) -> st(7) -> ST0
19705 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19706 tolower(Constraint[1]) == 's' &&
19707 tolower(Constraint[2]) == 't' &&
19708 Constraint[3] == '(' &&
19709 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19710 Constraint[5] == ')' &&
19711 Constraint[6] == '}') {
19713 Res.first = X86::ST0+Constraint[4]-'0';
19714 Res.second = &X86::RFP80RegClass;
19718 // GCC allows "st(0)" to be called just plain "st".
19719 if (StringRef("{st}").equals_lower(Constraint)) {
19720 Res.first = X86::ST0;
19721 Res.second = &X86::RFP80RegClass;
19726 if (StringRef("{flags}").equals_lower(Constraint)) {
19727 Res.first = X86::EFLAGS;
19728 Res.second = &X86::CCRRegClass;
19732 // 'A' means EAX + EDX.
19733 if (Constraint == "A") {
19734 Res.first = X86::EAX;
19735 Res.second = &X86::GR32_ADRegClass;
19741 // Otherwise, check to see if this is a register class of the wrong value
19742 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19743 // turn into {ax},{dx}.
19744 if (Res.second->hasType(VT))
19745 return Res; // Correct type already, nothing to do.
19747 // All of the single-register GCC register classes map their values onto
19748 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19749 // really want an 8-bit or 32-bit register, map to the appropriate register
19750 // class and return the appropriate register.
19751 if (Res.second == &X86::GR16RegClass) {
19752 if (VT == MVT::i8 || VT == MVT::i1) {
19753 unsigned DestReg = 0;
19754 switch (Res.first) {
19756 case X86::AX: DestReg = X86::AL; break;
19757 case X86::DX: DestReg = X86::DL; break;
19758 case X86::CX: DestReg = X86::CL; break;
19759 case X86::BX: DestReg = X86::BL; break;
19762 Res.first = DestReg;
19763 Res.second = &X86::GR8RegClass;
19765 } else if (VT == MVT::i32 || VT == MVT::f32) {
19766 unsigned DestReg = 0;
19767 switch (Res.first) {
19769 case X86::AX: DestReg = X86::EAX; break;
19770 case X86::DX: DestReg = X86::EDX; break;
19771 case X86::CX: DestReg = X86::ECX; break;
19772 case X86::BX: DestReg = X86::EBX; break;
19773 case X86::SI: DestReg = X86::ESI; break;
19774 case X86::DI: DestReg = X86::EDI; break;
19775 case X86::BP: DestReg = X86::EBP; break;
19776 case X86::SP: DestReg = X86::ESP; break;
19779 Res.first = DestReg;
19780 Res.second = &X86::GR32RegClass;
19782 } else if (VT == MVT::i64 || VT == MVT::f64) {
19783 unsigned DestReg = 0;
19784 switch (Res.first) {
19786 case X86::AX: DestReg = X86::RAX; break;
19787 case X86::DX: DestReg = X86::RDX; break;
19788 case X86::CX: DestReg = X86::RCX; break;
19789 case X86::BX: DestReg = X86::RBX; break;
19790 case X86::SI: DestReg = X86::RSI; break;
19791 case X86::DI: DestReg = X86::RDI; break;
19792 case X86::BP: DestReg = X86::RBP; break;
19793 case X86::SP: DestReg = X86::RSP; break;
19796 Res.first = DestReg;
19797 Res.second = &X86::GR64RegClass;
19800 } else if (Res.second == &X86::FR32RegClass ||
19801 Res.second == &X86::FR64RegClass ||
19802 Res.second == &X86::VR128RegClass ||
19803 Res.second == &X86::VR256RegClass ||
19804 Res.second == &X86::FR32XRegClass ||
19805 Res.second == &X86::FR64XRegClass ||
19806 Res.second == &X86::VR128XRegClass ||
19807 Res.second == &X86::VR256XRegClass ||
19808 Res.second == &X86::VR512RegClass) {
19809 // Handle references to XMM physical registers that got mapped into the
19810 // wrong class. This can happen with constraints like {xmm0} where the
19811 // target independent register mapper will just pick the first match it can
19812 // find, ignoring the required type.
19814 if (VT == MVT::f32 || VT == MVT::i32)
19815 Res.second = &X86::FR32RegClass;
19816 else if (VT == MVT::f64 || VT == MVT::i64)
19817 Res.second = &X86::FR64RegClass;
19818 else if (X86::VR128RegClass.hasType(VT))
19819 Res.second = &X86::VR128RegClass;
19820 else if (X86::VR256RegClass.hasType(VT))
19821 Res.second = &X86::VR256RegClass;
19822 else if (X86::VR512RegClass.hasType(VT))
19823 Res.second = &X86::VR512RegClass;